Fairchild 6004 service manual
www.fairchildsemi.com
Application Note 6004
500W Power-Factor-Corrected (PFC) Converter Design with FAN4810
This application note describes the theory of operation and
step-by-step process to design a high performance Power
Factor Corrected (PFC) power supply using the FAN4810
controller IC. A complete application circuit is shown in
Figure 10 and an evaluation board using this design is available from Fairchild Sales. The evaluation board provides
500W at 400VDC and 1.25A, while operating from 90V to
264VAC line input.
Selection of Power Train
Components
The FAN4810 can be used in any active PFC pre-regulator
employing Continuous Conduction Mode (CCM) that has to
comply with the IEC 3000-3-2 standard. This section of the
application note covers calculation parameters and selection
of pre-regulator power train components: boost inductor,
output capacitor and semiconductors.
Selecting the Value of the Boost Inductor
The FAN4810 operates in a continuous conduction code to
minimize peak current and maximize available power. The
value boost inductance found by setting ∆ I, the peak-to- peak
value of high-frequency current, is typically in the area of
20% of the peak value of the maximum line current.
2P
I
_LINE_PK
Where I
_LINE_PK
low line, V
IN
----------------=
V
MIN
(1)
is a peak value of input current occurred at
is RMS value of minimum line voltage, P
MIN
output power and η is efficiency. Value I
value of ∆ I , where dI is the specified percentage rate.
I_L
I_L
is the inductor maximum current.
MAX
∆IdII
×=
_LINE_PK
MAXI_LINE_PK
∆I
------+=
2
Another factor influencing inductor selection is duty cycle D
and switching frequency f
V
2V
–
O
-----------------------------------=
D
MIN
V
O
(4)
.
S
L
P
O
------=
P
IN
η
_LINE_PK
D2V
×
--------------------------------=
f
∆I×
S
(2)
is
O
will define
(3)
MIN
(5)
Selecting the Value of the Bulk Capacitor
A major factor affecting bulk capacitor selection is hold up
time (T
). “Hold-up-time” is a time during which output of
hld
power supply remains in specified range, after interruption of
AC power. Energy J
stored in the bulk capacitor supplies
thd
the down-steam converter during power disruption. Voltage
across bulk capacitor drops during hold-up time, as capacitor
discharges. You should calculate the minimum bus voltage
V
, where output voltage stays in regulation, trans-
O_MIN
former properly resets and components stress are inside the
derating guidelines.
J
THDPOTHLD
×= J
1
---
THD
2
2P
---------------------------------------=
C
THLD××
O
2
V
V
–
O
O_MIN
2
CV
× C– V
O
2
(6)
×()=
O_MIN
2
Setting the Oscillator Frequency
Resistor R6 and capacitor C18 set the oscillator frequency.
Let’s assume a value of C18 = 470 pF. The following equation determines the value of R6
1
--------------------------------------=
R6
C18 0.51× f
×
S
(7)
Selecting Parameters of Gain
Modulator Input Circuits
The FAN4810 Gain Modulator employs three inputs:
1. A current representing a profile of input voltage .
This current is proportional to the instantaneous value
of the input voltage at any given time. This current
programmed by resistor R1, see Fig 1.
2. A voltage proportional to the average value of the
line voltage . To obtain this voltage the input voltage is
filtered and scaled. A two-stage filter consists of resistors R2,R3,R4 and capacitors C2,C3.
3. Output of voltage error amplifier .
REV. 1.0.1 10/31/03
AN6004 APPLICATION NOTE
16 1
VEAO
FB
AC
RMS
VEA
–
+
MODULATOR
3.6kΩ
GAIN
V
15
2.5V
I
2
V
4
I
SENSE
3
IEAO
IEA
+
–
3.6kΩ
Figure 1. Gain Modulator and Voltage Error Amplifier
The program resistor for Pin 2 (I
) current input of the
AC
Gain Modulator is based on the following formula:
× G
2V
--------------------------------------------------------------------
≥
R1
Where G
R
is the output resistor of Gain Modulator and
MO
V
GM_OUT_MAX
× RMO×
MIN
V
MAX
MAX
GM_OUT_MAX
is the maximum gain of the Gain Modulator,
is the maximum output voltage of the Gain
Modulator. See the FAN4810 Datasheet for reference.
The voltage divider and necessary filters for providing the
scaled value of average input voltage for the Gain Modulator
Pin 4 (V
) input are shown in Figure 2.
RMS
R2
480
420
360
300
240
180
120
60
VARIABLE GAIN BLOCK CONSTANT (K)
0
0123
VRMS(V)
Figure 3. Gain Modulator Transfer Characteristic
(8)
The voltage at Pin 4 sets V
and must be well-filtered
RMS
and yet able to respond well to transient line voltage
changes. A two-stage RC low pass filter consisting of R2,
R3, R4, C3 and C2 as shown in Figure. 2 is selected to meet
this requirement. The resisitive divider ratio gives an average
DC voltage of 1.1 volts at Pin 4 at minimum line voltage.
2
---
V
AV
2V
=
MIN
π
Va v is the value of average line voltage and V
minimum RMS value of line voltage. Assume R2=R1 and
R3=100k. These values are a common choice for Fairchild
PFC applications.
45
(9)
is the
MIN
R3
R4
C2
C3
Figure 2. Two-Stage Filter Schematic
This resistive divider ratio should provide 1.1V at the lowest
line voltage. The value of 1.1V is chosen based on the
FAN4810 datasheet and Gain Modulator Transfer Characteristic presented in Figure 3. The characteristic curve includes
two segments: the right segment is the area of normal operation conditions with line voltages from 80VAC to 264VAC
and the left segment is the area of brown-out conditions
where the line voltage drops below 80VAC. Maximum gain
occurs at V
V
(V) of 1.1V, corresponding to the maximum gain,
RMS
(V) =1.1V, see curve in Figure 3. The
RMS
defines the criteria selection or resistor divider.
I
RD1
Where V
VAVV
–
--------------------------------------------------=
GM_IN_MAX
R2 R3+
GM_IN_MAX
(10)
=1.1V and I
RD1
V
R4
GM_IN_MAX
--------------------------------=
I
RD1
is the current flowing
(11)
through the divider.
R
TOTAL
C3
C2
R2 R3 R4++=
R
----------------------------------------------------------------=
2 π× f1× R2 R3 R4+()×
1
-------------------------------------------------=
TOTAL
R4 R
×
TOTAL
----------------------------------+
R2 R3 R4+()
2 π× f2× R4×
(12)
(13)
(14)
Two poles circuits presented in Figure 2 has demonstrated
good performance with f
= 15Hz and f
1
= 23Hz.
2
2
REV. 1.0.1 10/31/03
APPLICATION NOTE AN6004
Selection Parameters of Current
Sense Circuit
A current sense circuit includes a current sense resistor and a
filter.
Selection of Current Sense Resistor
The voltage drop across the current sense resistor should not
exceed the maximum output voltage of the gain modulator,
whose output is connected to the inverting input of the current error amplifier. See Figure 5. The non-inverting input of
the current error amplifier is connected to the ground and its
inverting input acts as a summing node for summing the
Gain Modulator output with the negative voltage on the
current sense resistor as shown in Figure 4.
V
R5
GM_OUT_MAX
-------------------------------------=
I_L_
MAX
(15)
I_L_
MAXI_LINE_PK
Selection of Current Sense Filter
GND
IAC
VEAO
I
SENSE
3.5K
3.5K
R
filter
100Ω
R5
10
3
C
filter
100nF
Figure 4: Current Sense Amplifier Circuit
The current sense filter is needed to protect the I
from voltage surges at start-up caused by a high inrush
V
–
+
REF
EAO
sense
pin
∆I
------+=
2
current and to enhance Total Harmonic Distortion (THD)
performance when a small boost inductor is used and is
operating in Discontinuous Conduction Mode (DCM) at
light loads.
f_cf
---------------------------------------------=
2 π× R16× C19×
The f_cf filter frequency should be set between f
/6 < f_cf < fS.
f
S
1
and f
S
S
(16)
/6;
R16 = 100 Ω or less is recommended.
Selection Parameters of Current
Error Amplifier Compensation
Network
The FAN4810 employs two control loops for power factor
correction: a current control loop and a voltage control loop.
The current control loop shapes current based on the reference signal from the IAC Pin 2. The voltage loop stabilizes
output voltage and defines THD balance.
The output of the Gain Modulator is a current proportional to
the output of the error amplifier and full sine current IAC on
Pin 2 and is inverse-proportional to the V
4. Output current of the Gain Modulator generates a voltage
on internal resistor RMO (3.6k). This voltage subtracts from
the voltage on sense resistor R5. The difference between the
resulting voltage on the inverting pin of the current error
amplifier and virtual ground on the non-inverting pin generates an output voltage that is applied to the non-inverting
input of comparator. The ramp signal applied to the inverting
input of the comparator controls the output signal on Pin 12.
For example, if the output voltage is decreasing, the output
of the current error amplifier increases the duty cycle.
Increasing the duty cycle will in turn increase the output
voltage, thereby closing the control loop.
voltage on Pin
RMS
VEAO
15
2
4
3
7
V
2.5V
I
AC
V
I
SENSE
RAMP 1
FB
RMS
VEA
–
+
MODULATOR
REV. 1.0.1 10/31/03
16
GAIN
3.6kΩ
3.6kΩ
1
IEAO
IEA
+
-
POWER FACTOR CORRECTOR
0.5V
+
–
OSCILLATOR
TRI-FAULT
+
–
2.75V
-1V
OVP
+
–
+
–
PFC I
LIMIT
V
CC
17V
SRQ
SRQ
13
7.5V
REFERENCE
Q
Q
V
CC
PFC OUT
V
REF
14
12
Figure 5. FAN4810 PFC Block Diagram
3
Loading...