ESI ES29LV160D User Guide

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ES29LV160D

16Mbit(2M x 8/1M x 16)

CMOS 3.0 Volt-only, Boot Sector Flash Memory

GENERAL FEATURES

• Single power supply operation

- 2.7V -3.6V for read, program and erase operations

•Sector Structure

- 16Kbyte x 1, 8Kbyte x 2, 32Kbyte x 1 boot sectors

- 64Kbyte x 31 sectors

• Top or Bottom boot block

- ES29LV160DT for Top boot block device

- ES29LV160DB for Bottom boot block device

• Package Options

- 48-pin TSOP

- 48-ball FBGA ( 6 x 8 mm )

- Pb-free packages

- All Pb-free products are RoHS-Compliant

• Low Vcc write inhibit

• Manufactured on 0.18um process technology

• Compatible with JEDEC standards

- Pinout and software compatible with single-power
supply flash standard

DEVICE PERFORMANCE

• Read access time

- 90ns/120n for normal Vcc range ( 2.7V - 3.6V )

- 70ns for regulated Vcc range ( 3.0V - 3.6V )

• Program and erase time

- Program time : 6us/byte, 8us/word ( typical )

- Sector erase time : 0.7sec/sector ( typical )

• Power consumption (typical values)

- 200nA in standby or automatic sleep mode

- 9mA active read current at 5 MHz

- 15mA active write current during program or erase

• Minimum 100,000 program/erase cycles per sector

• 20 Year data retention at 125

o

C

SOFTWARE FEATURES

• Erase Suspend / Erase Resume

• Data# poll and toggle for Pro gr a m/erase status

• CFI ( Common Flash Interface) supported

• Unlock Bypass program

• Autoselect mode

• Auto-sleep mode after t

ACC

+ 30ns

HARDWARE FEATURES

• Hardware reset input pin ( RESET#)

- Provides a hardware reset to device

- Any internal device operation is terminated and the
device returns to read mode by the reset

• Ready/Busy# output pin ( RY/BY#)

- Provides a program or erase operational status
about whether it is finished for read or still being
progressed

• Sector protection / unprotection ( RESET# , A9 )

- Hardware method of locking a sector to prevent
any program or erase operation within that sector

- Two methods are provided :

- In-system method by RESET# pin

- A9 high-voltage method for PROM programmers

• Temporary Sector Unprotection ( RESET# )

- Allows temporary unprotection of previously
protected sectors to change data in-system

ES29LV160D

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Rev. 1C Jan 5 , 2006

GENERAL PRODUCT DESCRIPTION

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The ES29LV160 is a 16 megabit, 3.0 volt-only flash
memory device, organized as 2M x 8 bits (Byte
mode) or 1M x 16 bits (Word mode) which is config­urable by BYTE#. Four boot sectors and thirty one
main sectors are provided : 16Kbytes x 1, 8Kbytes
x 2, 32Kbytes x 1 and 64Kbytes x 31. The device is
manufactured with ESI’s proprietary, high perfor­mance and highly reliable 0.18um CMOS flash
technology. The device can be programmed or
erased in-system with standard 3.0 Volt Vcc supply
( 2.7V-3.6V) and can also be programmed in stan­dard EPROM programmers. The device of fers min­imum endurance of 100,000 program/erase cycles
and more than 10 years of data retention.

The ES29LV160 offers access time as fast as 70ns
or 90ns, allowing operation of high-speed micropro­cessors without wait states. Three separate control
pins are provided to eliminate bus contention : chip
enable (CE#), write enable (WE#) and output
enable (OE#).

All program and erase operation are automatically
and internally performed and controlled by embed­ded program/erase algorithms built in the device.
The device automatically generates and times the
necessary high-voltage pulses to be applied to the
cells, performs the verification, and counts the num­ber of sequences. Some status bits (DQ7, DQ6 and
DQ5) read by data# polling or toggling between
consecutive read cycles provide to the users the
internal status of program/erase operation: whether
it is successfully done or still being progressed.

The ES29LV160 is completely compatible with the
JEDEC standard command set of single power sup­ply Flash. Commands are written to the internal
command register using standard write timings of
microprocessor and data can be re ad out from the
cell array in the device with the same way as used i n
other EPROM or flash devices.

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PRODUCT SELECTOR GUIDE

Family Part Number ES29LV160

Voltage Range 3.0 ~ 3.6V 2.7 ~ 3.6V

Speed Option 70R 90 120

Max Access Time (ns) 70 90 120

CE# Access (ns) 70 90 120
OE# Access (ns) 35 40 50

FUNCTION BLOCK DIAGRAM

RY/BY#

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Vcc
Vss

WE

RESET#

A<0:19>

CE#
OE#

BYTE#

Vcc Detector

#

Command
Register

Chip Enable
Output Enable
Logic

Timer/
Counter

Write
State
Machine

Analog Bias
Generator

Sector Switches

Y-Decoder

X-Decoder

Address Latch

DQ0-DQ15(A-1)

Input/Output
Buffers

Data Latch/
Sense Amps

Y-Decoder

Cell Array

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PIN DESCRIPTION

Pin Description

A0-A19 20 Addresses

DQ0-DQ14 15 Data Inputs/Outputs

DQ15/A-1

CE# Chip Enable
OE# Output Enable

WE# Write Enable

RESET# Hardware Reset Pin, Active Low

BYTE# Se lects 8-bit or 16-bit mode

RY/BY# Ready/Busy Output (N/A SO 044)

Vcc

Vss Device Ground

NC Pin Not Connected Internally

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DQ15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)

3.0 volt-only single power supply
(see Product Selector Guide for speed options and voltage supply tolerances)

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LOGIC SYMBOL

20

A0 ~ A19

CE#

OE#
WE#
RESET#

BYTE#

16 or 8

DQ0 ~ DQ15
(A-1)

RY/BY#
(N/A SO 044)

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Rev. 1C Jan 5 , 2006

CONNECTION DIAGRAM

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A15
A14

A13
A12
A11
A10

A9
A8

A19

NC

WE#

RESET#

NC

NC

RY/BY#

A18
A17

A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48-Pin Standard TSOP

ES29LV160

48
47
46
45
44

43
42
41

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16
BYTE#
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13

DQ5
DQ12
DQ4
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
CE#
A0

48-Ball FBGA (6 x 8 mm)

(Top View, Balls Facing Down)

A B C D E F G H

6

5

4

3

2

1

A13 A12

A9

WE#

RY/

BY#

A7

A3

A8

RESET#

NC

A17

A4

A14

A10

NC

A18

A6

A2

A15

A16

A11 DQ7

A19

NC

A5

DQ5

DQ2

DQ0

A0A1

BYTE#

DQ14

DQ12

DQ10 DQ11 DQ3

DQ8 DQ9 DQ1

DQ15/

A-1

DQ13

Vcc

OE#CE#

Vss

DQ6

DQ4

Vss

ES29LV160D

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Rev. 1C Jan 5 , 2006

DEVICE BUS OPERATIONS

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Several device operational modes are provided in
the ES29LV160 device. Commands are used to ini­tiate the device operations. They are latched and
stored into internal registers with the address and
data information needed to execute the device
operation.

The available device operational modes are listed
in Table 1 with the required inputs, controls, and the
resulting outputs. Each operational mode is
described in further detail in the following subsec­tions.

Read

The internal state of the device is set for the read
mode and the device is ready for reading arra y da t a
upon device power-up, or after a hardware reset. To
read the stored data from the cell array of the
device, CE# and OE# pins should be driven to V

while WE# pin remains at VIH. CE# is the power
control and selects the device. OE# is the output

control and gates array data to the output pins.
Word or byte mode of output data is determined by

the BYTE# pin. No additional command is needed
in this mode to obtain array data. Standard micro­processor read cycles that assert valid addresses

on the device address inputs produce valid data on
the device data outputs. The device st ays at the read
mode until another operation is activated by writing
commands into the internal command register. Refer
to the AC read cycle timing diagrams for further
details ( Fig. 16 ).

Word/Byte Mode Configuration ( BYTE# )

The device data output can be configured by BYTE#
into one of two modes : word and byte modes. If the
BYTE# pin is set at logic ‘1’, the device is configured
in word mode, DQ0 - DQ15 are active and controlled
by CE# and OE#. If the BYTE# pin is set at logic ‘0’,
the device is configured in byte mode, and only data
I/O pins DQ0 - DQ7 are active and controlled by CE#
and OE#. The data I/O pins DQ8 - DQ14 are tri­stated, and the DQ15 pin is used as an input for the
LSB (A-1) address.

IL

Standby Mode

When the device is not selected or activated in a
system, it needs to stay at the standby mode, in
which current consumption is greatly reduced with
outputs in the high impedance state.

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The device enters the CMOS standby mode when
CE# and RESET# pins are both held at Vcc
(Note that this is a more restricted voltage range
than V

not within Vcc
standby mode, but the standby current will be
greater than the CMOS standby current (0.2uA typi­cally). When the device is in the standby mode, only
standard access time (t

access, before it is ready for read data. And even if
the device is deselected by CE# pin during erase or
programming operation, the device draws active cur ­rent until the operation is completely done. While the
device stays in the standby mode, the output is
placed in the high impedance state, independent of
the OE# input.

The device can enter the deep power-down mode
where current consumption is greatly reduced down
to less than 0.2uA typically by the following three
ways:

- CMOS standby ( CE#, RESET# = Vcc + 0.3V )

Refer to the CMOS DC characteristics Table11 for
further current specification .

) If CE# and RESET# are held at VIH, but

IH.

+

0.3V, the device will be still in the

) is required for read

CE

- During the device reset ( RESET# = Vss

- In Autosleep Mode ( after t

ACC

+ 30ns )

+

0.3V.

+ 0.3V )

Autosleep Mode

The device automatically enters a deep power-down
mode called the autosleep mode when addresses
remain stable for t

consumption is greatly reduced ( less than 0.2uA
typical ), regardless of CE#, WE# and OE# control
signals.

+30ns. In this mode, current

ACC

Writing Commands

To write a command or command sequences to ini­tiate some operations such as program or erase, the
system must drive WE# and CE# to V

. For program operations, the BYTE# pin deter-

V

IH

mines whether the device accepts pro gram data in
bytes or words. Refer to “BYTE# timings for Write
Operations” in the Fig. 19 for more information.

, and OE# to

IL

Unlock Bypass Mode

To reduce more the programming time, an unlock­bypass mode is provided. Once the device enters
this mode, only two write cycles are required to ini­tiate the programming operation instead of four
cycles in the normal program command sequences
which are composed of two unlock cycles, program

set-up cycle and the last cycle with the program data
and addresses. In this mode, two unlock cycles are
saved ( or bypassed ).

Sector Addresses

The entire memory space of cell array is divided into
a many of small sectors: 16Kbytes x 1, 8Kbytes x 2,
32Kbytes x 1 and 64Kbytes x 31 main sectors. In
erase operation, a single sector, multiple sectors, or
the entire device (chip erase) can be selected for
erase. The address space that each sector occupies
is shown in detail in the Table 3-4.

Autoselect Mode

Flash memories are intended for use in applications
where the local CPU alters memory contents. In
such applications, manufacturer and device identifi­cation (ID) codes must be accessible while the
device resides in the target system ( the so called
“in-system program”). On the other hand, signature
codes have been typically accessed by raising A9
pin to a high voltage in PROM programmers. How­ever, multiplexing high voltage onto address lines is
not the generally desired system design practice.
Therefore, in the ES29LV160 device an autoselect
command is provided to allow the system to access
the signature codes without any high voltage. The
conventional A9 high-voltage method used in the
PROM programers for signature codes are still sup­ported in this device.
If the system writes the autoselect command
sequence, the device enters the Autoselect mode.
The system can then read some useful codes such
as manufacturer and device ID from the int er na l re g­isters on DQ7 - DQ0. Standard read cycle timings
apply in this mode. In the Autoselect mode, the fol­lowing three informations can be acc essed through
either autoselect command method or A9 high-volt­age autoselect method. Refer to the Table 2.

-

-

-

Manufacturer ID
Device ID
Sector protection verify

Hardware Device Reset ( RESET# )

The RESET# pin provides a hardware method of
resetting the device to read array data. When the
RESET# pin is driven low for at least a period of t

RP

,

ES29LV160D

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Rev. 1C Jan 5 , 2006

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the device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the
RESET# pulse The device also resets the internal
state machine to reading array data. The operation
that was interrupted should be reinitiated once after
the device is ready to accept another command
sequence, to ensure data integrity.

CMOS Standby during Device Reset

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at Vss
device draws the greatly reduced CMOS standby
current ( I

within Vss

). If RESET# is held at VIL but not

CC4

+

0.3V, the standby current will be greater.

+

0.3V, the

RY/BY# and Terminating Operations

If RESET# is asserted during a program or erase
operation, the RY/BY# pin remains a “0” (busy) until
the internal reset operation is completed, which
requires a time of t

rithms). The system can thus monitor RY/BY# to
determine whether the reset operation is completed.
If RESET# is asserted when a program or erase
operation is not executing (RY/BY# pin is “1”), the
reset operation is completed within a time of t

(not during Embedded Algorithms). The system can
read data after the RESET# pin returns to V

requires a time of t

READY

RH.

(during Embedded Algo-

READY

, which

IH

Sector protection can be implemented via two
methods.

-

-

To check whether the sector protection was suc­cessfully executed or not, another operation called
“protect verification” needs to be performed after
the protection operation on a sector. All protection
and protect verifications provided in the device are
summarized in detail at the Table 1.

In-system protection
A9 High-voltage protection

In-System Protection

“In-system protection”, the primary method,
requires V

A6=0, A1=1, and A0=0. This method can be imple­mented either in-system or via programming equip­ment. This method uses standard microprocessor
bus cycle timing. Refer to Fig. 26 for timing diagram
and Fig. 2 for the protection algorithm.

(11.5V~12.5V) on the RESET# with

ID

A9 High-Voltage Protection

“High-voltage protection”, the alternate method
intended only for programming equipment, must
force V

trol pin OE# with A6=0, A1=1 and A0=0. Refer to
Fig. 28 for timing diagram and Fig. 4 for the protec­tion algorithm.

(11.5~12.5V) on address pin A9 and con-

ID

RESET# tied to the System Reset

The RESET# pin may be tied to the system reset cir­cuitry. A system reset would thus also reset the
Flash memory , enab ling the system to read the boot­up firmware from the Flash memory.Refer to the AC
Characteristics tables for RESET# parameters and
to Fig. 17 for the timing diagram.

SECTOR PROTECTION

The ES29LV160 features hardware sector protec­tion. In the device, sector protection is performed on
the sector previously defined in the Table 3-4. Once
after a sector is protected, any program or erase
operation is not allowed in the protected sector. The
previously protected sectors must be unprotected by
one of the unprotect methods provided here before
changing data in those sectors.

SECTOR UNPROTECTION

The previously protected sectors must be unpro­tected before modifying any data in the sectors.
The sector unprotection algorithm unprotects all
sectors in parallel. All unprotected sectors must first
be protected prior to the first sector unprotection
write cycle to avoid any over-erase due to the intrin­sic erase characteristics of the protection cell. After
the unprotection operation, all previously protected
sectors will need to be individually re-protected.
Standard microprocessor bus cycle timings are
used in the unprotection and unprotect verification
operations. Three unprotect methods are provided
in the ES29LV160 device. All unprotection and
unprotect verification cycles are summarized in
detail at the Table 1.

-

-

-

In-system unprotection
A9 High-voltage unprotection
T emporary sector unprotection

ES29LV160D

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Rev. 1C Jan 5 , 2006

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In-System Unprotection

“In-system unprotection”, the primary method,
requires V

(11.5V~12.5V) on the RESET# with

ID

A6=1, A1=1, and A0=0. This method can be imple­mented either in-system or via programming equip­ment. This method uses standard microprocessor
bus cycle timing. Refer to Fig. 26 for timing diagram
and Fig. 3 for the unprotection algorithm.

A9 High-Voltage Unprotection

“High-voltage unprotection”, the alternate method
intended only for programming equipment, must
force V

(11.5~12.5V) on address pin A9 and con-

ID

trol pin OE# with A6=1, A1=1 and A0=0. Refer to
Fig. 29 for timing diagram and Fig. 5 for the unpro­tection algorithm.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ­ously protected sectors to change data in-system.
The Sector Unprotect mode is activated by setting
the RESET# pin to V

(11.5V-12.5V). During this

ID

mode, formerly protected sectors can be pro­grammed or erased by selecting the sector
addresses. Once V

is removed from the RESET#

ID

pin, all the previously protected sectors are pro­tected again. Fig. 1 shows the algorithm, and Fig. 25
shows the timing diagrams for this feature.

HARDWARE DATA PROTECTION

The command register and all internal program/
erase circuits are disabled, and the devi ce resets to
the read mode. Subsequent writes are ignored until
Vcc is greater than V

. The system must provide

LKO

proper signals to the control pins to prevent unin­tentional writes when Vcc is greater than V

LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.

Logical inhibit

Write cycles are inhibited by holding any one of
OE#=V

, CE#=VIH or WE#=VIH. To initiate a write

IL

cycle, CE# and WE# must be a logical zero while
OE# is a logical one.

Power-up Write Inhibit

If WE#=CE#=VIL and OE#=VIH during power up,
the device does not accept any commands on the

rising edge of WE#. The internal state machine is
automatically reset to the read mode on power-up.

START

RESET# = V

(Note 1)

ID

The ES29LV160 device provides some protection
measures against accidental erasure or program­ming caused by spurious system level signals that
may exist during power transition. During power-up,
all internal registers and latches in the device are
cleared and the device automatically resets to the
read mode. In addition, with its internal state
machine built-in the device, any alteration of the
memory contents or any initiation of new operation­can only occur after successful completion of spe­cific command sequences. And several features are
incorporated to prevent inadvertent write cycles
resulting from Vcc power-up and power -dow n tr an si­tion or system noise.

Low Vcc Write inhibit

When Vcc is less than V
accept any write cycles. This protects data during

Vcc power-up and power-down.

ES29LV160D

, the device does not

LKO

9

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors are unprotected .

2. All previously protected sectors are protected once again.

IH

Figure 1. Temporary Sector Unprotect
Operation

Rev. 1C Jan 5 , 2006

Table 1. ES29LV160 Device Bus Operations

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Operation CE# OE# WE# RESET# Addresses

Read

Write

Standby

Output Disable
Reset

In-system

A9 High-Volt­age Method

L
L

Vcc+

0.3V

L H H H X High-Z High-Z
X X X L X High-Z High-Z

Sector Protect
(Note 2)

Sector Unprotect
(Note 2) L H L V

Temporary Sector
Unprotect X X X

Sector protect

Sector unprotect

LHL

L

L

H

L

L

H

XX Vcc+

V

L

ID

V

L

ID

H
H

0.3V

V

V

H

H

DQ0

~

(Note 1)

A

IN

A

IN

X High-Z High-Z

ID

ID

ID

SA,A6=L,

A1=H,A0=L

SA,A6=H,

A1=H,A0=L

A

IN

SA,A9=V

A6=L,

A1=H,A0=L
SA,A9=V

A6=H,

A1=H,A0=L

DQ7

D

OUT

(Note 3) (Note 3)

(Note 3) X X

(Note 3) X X

(Note 3) (Note 3) High-Z

,

ID

(Note 3) (Note 3) High-Z

,

ID

BYTE#

= V

D

OUT

DQ8~DQ15

IH

BYTE#

= V

IL

DQ8~DQ14 = High-Z,

DQ15 = A-1

High-Z

Legend:

D

L=Logic Low=VIL, H=Logic High=VIH, VID=11. 5-12.5V, X=Don’t Care, SA=Sector Address, AIN=Address In, DIN=Data In,

=Data Out

OUT

Notes:

1. Addresses are A19:A0 in word mode (BYTE#=VIH) , A19:A-1 in byte mode (BYTE#=VIL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Pro­ tection and Unprotection” section.

3. D

IN

or D

as required by command sequence, data polling, or sector protection algorithm.

OUT

Table 2. Autoselect Codes (A9 High-Voltage Method)

A19

Description CE# OE# WE#

ManufactureID:ESI

Device ID:

ES29LV160

Sector Protection

Verification

Legend:

T= Top Boot Block, B = Bottom Boot Block, L=Logic Low=VIL, H=Logic High=VIH, SA=Sector Address, X = Don’t care

L

L

LLHX X

LLHSAX

A12

H

A11

to

to

A10

XX

A9A8toA7A6

V

XLXLL X

ID

V

X L X L H 22h X C4h(T),49h(B)

ID

V

XLXHL X X

ID

A5

toA2A1 A0

DQ8~DQ15

BYTE#

= V

IH

BYTE#

= V

IL

X4Ah

DQ7~DQ0

01h(protected)

00h(unprotected)

ES29LV160D

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Table 3. Top Boot Sector Addresses (ES29LV160DT)

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Sector

SA0 00000XXX 64/32 000000h~00FFFFh 00000h~07FFFh
SA1 00001XXX 64/32 010000h~01FFFFh 08000h~0FFFFh
SA2 00010XXX 64/32 020000h~02FFFFh 10000h~17FFFh
SA3 00011XXX 64/32 030000h~03FFFFh 18000h~1FFFFh
SA4 00100XXX 64/32 040000h~04FFFFh 20000h~27FFFh
SA5 00101XXX 64/32 050000h~05FFFFh 28000h~2FFFFh
SA6 00110XXX 64/32 060000h~06FFFFh 30000h~37FFFh
SA7 00111XXX 64/32 070000h~07FFFFh 38000h~3FFFFh
SA8 01000XXX 64/32 080000h~08FFFFh 40000h~47FFFh

SA9 01001XXX 64/32 090000h~09FFFFh 48000h~4FFFFh
SA10 01010XXX 64/32 0A0000h~0AFFFFh 50000h~57FFFh
SA11 01011XXX 64/32 0B0000h~0BFFFFh 58000h~5FFFFh
SA12 01100XXX 64/32 0C0000h~0CFFFFh 60000h~67FFFh
SA13 01101XXX 64/32 0D0000h~0DFFFFh 68000h~6FFFFh
SA14 01110XXX 64/32 0E0000h~0EFFFFh 70000h~77FFFh
SA15 01111XXX 64/32 0F0000h~0FFFFFh 78000h~7FFFFh
SA16 10000XXX 64/32 100000h~10FFFFh 80000h~87FFFh
SA17 10001XXX 64/32 110000h~11FFFFh 88000h~8FFFFh
SA18 10010XXX 64/32 120000h~12FFFFh 90000h~97FFFh
SA19 10011XXX 64/32 130000h~13FFFFh 98000h~9FFFFh
SA20 10100XXX 64/32 140000h~14FFFFh A0000h~A7FFFh
SA21 10101XXX 64/32 150000h~15FFFFh A8000h~AFFFFh
SA22 10110XXX 64/32 160000h~16FFFFh B0000h~B7FFFh
SA23 10111XXX 64/32 170000h~17FFFFh B8000h~BFFFFh
SA24 11000XXX 64/32 180000h~18FFFFh C0000h~C7FFFh
SA25 11001XXX 64/32 190000h~19FFFFh C8000h~CFFFFh
SA26 11010XXX 64/32 1A0000h~1AFFFFh D0000h~D7FFFh
SA27 11011XXX 64/32 1B0000h~1BFFFFh D8000h~DFFFFh
SA28 11100XXX 64/32 1C0000h~1CFFFFh E0000h~E7FFFh
SA29 11101XXX 64/32 1D0000h~1DFFFFh E8000h~EFFFFh
SA30 11110XXX 64/32 1E0000h~1EFFFFh F0000h~F7FFFh
SA31 111110XX 32/16 1F0000h~1F7FFFh F8000h~FBFFFh
SA32 11111100 8/4 1F8000h~1F9FFFh FC000h~FCFFFh
SA33 11111101 8/4 1FA000h~1FBFFFh FD000h~FDFFFh
SA34 1111111X 16/8 1FC000h~1FFFFFh FE000h~FFFFFh

Sector address

A19~A12

Sector Size

(Kbytes/Kwords)

(X8)

Address Range

(X16)

Address Range

Remark

Main Sector

Boot Sector

Note:

The addresses range is A19:A-1 in byte mode (BYTE#=VIL) or A19:A0 in word mode (BYTE#=VIH).

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Table 4. Bottom Boot Sector Addresses (ES29LV160DB)

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Sector

SA0 0000000X 16/8 000000h~003FFFh 00000h~01FFFh
SA1 00000010 8/4 004000h~005FFFh 02000h~02FFFh
SA2 00000011 8/4 006000h~007FFFh 03000h~03FFFh
SA3 000001XX 32/16 008000h~00FFFFh 04000h~07FFFh
SA4 00001XXX 64/32 010000h~01FFFFh 08000h~0FFFFh
SA5 00010XXX 64/32 020000h~02FFFFh 10000h~17FFFh
SA6 00011XXX 64/32 030000h~03FFFFh 18000h~1FFFFh
SA7 00100XXX 64/32 040000h~04FFFFh 20000h~27FFFh
SA8 00101XXX 64/32 050000h~05FFFFh 28000h~2FFFFh
SA9 00110XXX 64/32 060000h~06FFFFh 30000h~37FFFh

SA10 00111XXX 64/32 070000h~07FFFFh 38000h~3FFFFh

SA11 01000XXX 64/32 080000h~08FFFFh 40000h~47FFFh
SA12 01001XXX 64/32 090000h~09FFFFh 48000h~4FFFFh
SA13 01010XXX 64/32 0A0000h~0AFFFFh 50000h~57FFFh
SA14 01011XXX 64/32 0B0000h~0BFFFFh 58000h~5FFFFh
SA15 01100XXX 64/32 0C0000h~0CFFFFh 60000h~67FFFh
SA16 01101XXX 64/32 0D0000h~0DFFFFh 68000h~6FFFFh
SA17 01110XXX 64/32 0E0000h~0EFFFFh 70000h~77FFFh
SA18 01111XXX 64/32 0F0000h~0FFFFFh 78000h~7FFFFh
SA19 10000XXX 64/32 100000h~10FFFFh 80000h~87FFFh
SA20 10001XXX 64/32 110000h~11FFFFh 88000h~8FFFFh
SA21 10010XXX 64/32 120000h~12FFFFh 90000h~97FFFh
SA22 10011XXX 64/32 130000h~13FFFFh 98000h~9FFFFh
SA23 10100XXX 64/32 140000h~14FFFFh A0000h~A7FFFh
SA24 10101XXX 64/32 150000h~15FFFFh A8000h~AFFFFh
SA25 10110XXX 64/32 160000h~16FFFFh B0000h~B7FFFh
SA26 10111XXX 64/32 170000h~17FFFFh B8000h~BFFFFh
SA27 11000XXX 64/32 180000h~18FFFFh C0000h~C7FFFh
SA28 11001XXX 64/32 190000h~19FFFFh C8000h~CFFFFh
SA29 11010XXX 64/32 1A0000h~1AFFFFh D0000h~D7FFFh
SA30 11011XXX 64/32 1B0000h~1BFFFFh D8000h~DFFFFh
SA31 11100XXX 64/32 1C0000h~1CFFFFh E0000h~E7FFFh
SA32 11101XXX 64/32 1D0000h~1DFFFFh E8000h~EFFFFh
SA33 11110XXX 64/32 1E0000h~1EFFFFh F0000h~F7FFFh
SA34 11111XXX 64/32 1F0000h~1FFFFFh F8000h~FFFFFh

Sector address

A19~A12

Sector Size

(Kbytes/Kwords)

(X8)

Address Range

(X16)

Address Range

Remark

Boot Sector

Main Sector

Note:

The addresses range is A19:A-1 in byte mode (BYTE#=VIL) or A19:A0 in word mode (BYTE#=VIH).

ES29LV160D

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Temporary Sector

Unprotect Mode

Increment

COUNT

No

COUNT=25?

Yes Yes

Device failed

No

Set up sector
address

Sector Protect:
Write 60h to sec­tor address with
A6 = 0, A1 = 1,
A0 = 0

Write 40h to sec-

tor address with

A6 = 0, A1 = 1,

Read from sec-

tor address with

A6 = 0, A1 = 1,

No

Sector Protect

In-System Protection / Unprotection Method

START

COUNT = 1

RESET# = V

Wait 1us

First Write
Cycle = 60h?

Yes

Wait 150us

Verify Se ctor

Protect:

A0 = 0

A0 = 0

Data = 01h?

Protect another

sector?

No

Remove VID

from RESET#

Write reset

command

complete

Protect all sectors:
The indicated por­tion of the sector

ID

Reset

COUNT = 1

Yes

protect algorithm
must be performed
for all unprotected
sectors prior to
issuing the first
sector unprotect
address

Increment

COUNT

No

COUNT
=1000?

Yes Yes

Device failed

No

No

START

COUNT = 1

RESET# = V

Wait 1us

First Write
Cycle = 60h?

All sectors

protected ?

Set up first sector
address

Sector Unpro­tect:
Write 60h to sec­tor address with
A6 = 1, A1 = 1,

Wait 15ms

Verify Se ctor
Unprotect:
Write 40h to sec­tor address with
A6 = 1, A1 = 1,
A0 = 0

Read from sec­tor address with
A6 = 1, A1 = 1,
A0 = 0

Data = 00h?

Last sector

verified?

Remove VID from
RESET#

Write reset

command

Yes

Yes

Yes

ID

No

Temporary Sector

Unprotect Mode

Set up next
sector address

No

Figure 2. In-System Sector
Protect Algorithm

ES29LV160D

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Sector Unprotect
complete

Figure 3. In-System Sector
Unprotect Algorithm

Rev. 1C Jan 5 , 2006

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A9 High-Voltage Method

Start

Start

COUNT = 1

SET A9=OE#=V

ID

Note: All sectors must be
previously protected.

COUNT = 1

SET A9=OE#=V

ID

Increase COUNT

No

COUNT= 25?

Yes

Device failed

CE#,OE#,A6,A0=V
RESET#, A1 = V

No

Set Sector Address
A<19 :12>
CE#, A6, A0=V

RESET#, A1=V

SET WE# = V

Wait 150 us

SET WE# = V

Read Data

Data = 01h?

Protect Another
Sector ?

Remove VID from
A9 and Write

Reset Command

IL

IH

IL

IH

IH

Yes

No

CE#, A0=V
RESET#,

A6, A1=V

SET WE# = V

Wait 15ms

SET WE# = V

Increase COUNT

IL

No

COUNT=1000?

Yes

Yes

Device failed

CE#,OE#, A0=V
RESET#, A6, A1=V

Set Sector AddressA<19 :12>

Read Data

No

Data = 00h?

Yes

The Last Sector
Address ?

Remove VID from A9 and
Write Reset Command

IH

Yes

,

IL

IL

IH

IL

IH

Increase Sector
Address

No

Sector Protection
Complete

Figure 4. Sector Protection Algorithm
(A9 High-Voltage Method)

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14

Sector Unprotection
Complete

Figure 5. Sector Un-Protection Algorithm
(A9 High-Voltage Method)

Rev. 1C Jan 5 , 2006

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Common Flash Memory
Interface (CFI)

CFI is supported in the ES29LV160 device. The
Common Flash Interface (CFI) specification out­lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde­pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their exist­ing interfaces for long-term compatibility.

Table 5. CFI Query Identification String

Addresses

(Word Mode)

10h
11h
12h

13h
14h

15h
16h

17h
18h

19h
1Ah

Addresses

(Byte Mode)

20h
22h
24h

26h
28h

2Ah
2Ch

2Eh

30h
32h

34h

Data Description

0051h
0052h
0059h

0002h
0000h

0040h
0000h

0000h
0000h

0000h
0000h

This device enters the CFI Query mode when the
system writes the CFI query command, 98h, to
address 55h in word mode (or address AAh in byte
mode), any time the device is ready to read array
data. The system can read CFI information at the
addresses given in Tables 5-8. To termin ate reading
CFI data, the system must write the reset com-
mand.The CFI query command can be written to the
system when the device is in the autoselect mode
or the erase-suspend-read mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 5-8.
When the reset command is written, the device
returns respectively to the read mode or erase-sus­pend-read mode.

Query Unique ASCII string “QRY”

Primary OEM Command Set

Address for Primary Extended Table

Alternate OEM Command Set(00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

Table 6. System Interface String

Addresses

(Word Mode)

1Bh 36h 0027h

1Ch 38h 0036h

1Dh 3Ah 0000h Vpp Min. voltage (00h = no Vpp pin present)
1Eh 3Ch 0000h Vpp Max. voltage (00h = no Vpp pin present)

1Fh 3Eh 0004h
20h 40h 0000h
21h 42h 000Ah
22h 44h 0000h
23h 46h 0005h
24h 48h 0000h
25h 4Ah 0004h
26h 4Ch 0000h

Addresses

(Byte Mode)

Data Description

Vcc Min. (write/erase)
D7-D4: volt, D3-D0: 100 millivolt

Vcc Max. (write/erase)
D7-D4: volt, D3-D0: 100 millivolt

Typical timeout per single byte/word write 2
Typical timeout for Min. size buffer write 2
Typical timeout per individual block erase 2
Typical timeout for full chip erase 2
Max. timeout for byte/word write 2
Max. timeout for buffer write 2
Max. timeout per individual block erase 2
Max. timeout for full chip erase 2

N

N

times typical

N

times typical (00h = not supported)

N

N

us (00h = not supported)

N

N

ms (00h = not supported)

times typical

N

times typical

us

ms

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Table 7. Device Geometry Definition

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Addresses

(Word Mode)

27h 4Eh 0015h
28h

29h

2Ah
2Bh

2Ch 58h 0004h Number of Erase Block Regions within device
2Dh

2Eh

2Fh
30h

31h
32h

33h
34h

35h
36h

37h
38h

39h

3Ah

Addresses

(Byte Mode)

50h
52h

54h
56h

5Ah
5Ch

5Eh
60h

62h
64h

66h
68h

6Ah
6Ch

6Eh
70h

72h
74h

Data Description

N

byte

0002h
0000h

0000h
0000h

0000h
0000h

0040h
0000h

0001h
0000h

0020h
0000h

0000h
0000h

0080h
0000h

001Eh
0000h

Device Size = 2
Flash Device Interface description

02 = x8, x16 Asynchronous
Max. number of bytes multi-byte write = 2

(00h = not supported)

Erase Block Region 1 Information
Number of identical size erase block = 0000h+1 = 1

Erase Block Region 1 Information
Block size in Region 1 = 0040h * 256 byte = 16 Kbyte

Erase Block Region 2 Information
Number of identical size erase block = 0001h+1 =2

Erase Block Region 2 Information
Block size in Region 2 = 0020h * 256 byte = 8 Kbyte

Erase Block Region 3 Information
Number of identical size erase block = 0000h+1 =1

Erase Block Region 3 Information
Block size in Region 3 = 0080h * 256 byte = 32 Kbyte

Erase Block Region 4 Information
Number of identical size erase block = 001Eh+1 =31

N

3Bh
3Ch

76h
78h

0000h
0001h

Erase Block Region 4 Information
Block size in Region 4 = 0100h * 256 byte = 64 Kbyte

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Table 8. Primary Vendor-Specific Extended Query

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Addresses

(Word Mode)

40h
41h
42h

43h 86h 0031h Major version number, ASCII
44h 88h 0030h Minor version number, ASCII

45h 8Ah 0000h

46h 8Ch 0002h

47h 8Eh 0001h

48h 90h 0001h

49h 92h 0004h

4Ah 94h 0000h

4Bh 96h 0000h

4Ch 98h 0000h

Addresses

(Byte Mode)

80h
82h
84h

Data Description

0050h
0052h
0049h

Query-unique ASCII string “PRI”

Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not required
Silicon Revision Number (Bits 7-2)

Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect
0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect
00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme
04 = In-System Method and A9 High-Voltage Method

Simultaneous Operation
00 = Not Supported

Burst Mode Type
00 = Not Supported, 01 = Supported

Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

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