ERICSSON PBL 386 14-1 User Manual

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Preliminary Information

Description

The PBL 386 14/1 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated
circuit for use in ISDN Network Terminal Adapters and other short loop
telecommunication equipment which often are remote powered, and by that, the
available power is limited. The PBL 386 14/1 has been optimized for low total line
interface cost, low power and requires a minimum of external components.
The PBL 386 14/1 has constant current feed, programmable to max 30mA. The SLIC
uses a first battery voltage for On-hook . A second battery voltage is used for
Off-hook and must be connected, to reduce short loop power dissipation. The SLIC
automatically switches between the two battery supply voltages without need for
external components or external control. The loop current controls the switching
between On-hook and Off-hook battery.
The SLIC incorporates loop current, ground key and ring trip detection functions.
The PBL 386 14/1 is compatible with loop start signalling. Two- to four-wire and
four- to two-wire voice frequency (vf) signal conversion is accomplished by the SLIC
in conjunction with either a conventional CODEC/filter or with a programmable
CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable line terminating
impedance could be complex or real to fit every market. Longitudinal voltages are
suppressed by a feedback loop in the SLIC and the longitudinal balance specifica­tions meet Bellcore TR909 requirements.
The PBL 386 14/1 package is a very PCB space efficient 28-pin SSOP.

DT

DR

TIPX

RINGX

HP

Two-wire
Interface

Ring Trip

Comparator

Ground Key

Detector

Line Feed
Controller

and

Longitudinal

Signal

Suppression

Ring Relay

Driver

Input

Decoder and

Control

RRLY

C1

C2

C3
VCC

DET

PSGTS
LP

REF

PLC

February 2000

PBL 386 14/1

Subscriber Line

Interface Circuit

Applications

• ISDN Network terminals

• Shortloop applications

Key Features

• Small footprint with SSOP package

• On-hook and Off-hook battery with
automatic switching, controlled by
loop current

• On-hook battery current is limited
to 6 mA

• 37 mW on-hook power dissipation in
active state

• Metering 0.5 Vrms (0.7 Vpeak)

• Adaptive Overhead Voltage
The overhead voltage follows
1Vpeak<signals<2.5Vpeak

• Battery supply as low as -10V

• Only +5V in addition to GND
and battery (VEE optional)

• Open loop voltage tracks On-hook
battery

• Full longitudinal current capability
during On-hook

• 43.5V open loop voltage @ -48V
battery feed

• Automatic compensation for
line leakage up to 5 mA

• On-hook transmission

• Programmable loop & ring-trip
detector threshold

• Ground key detector

• Analog temperature guard with status
exclusively viewed at detector output

• Integrated Ring Relay Driver

• Linevoltage measurement

VBAT2

VBAT

BGND

Figure 1. Block diagram.

Off-hook
Detector

VF Signal

Transmission

PLD
AGND

VTX

RSN

VEE
(optional)

PBL 386 14/1

Package: 28-pin SSOP

1

PBL 386 14/1

Maximum Ratings

Parameter Symbol Min Max Unit

Temperature, Humidity

Storage temperature range T
Operating temperature range T
Operating junction temperature range, Note 1 T

Power supply, 0°C ≤ T
V

with respect to AGND V

CC

V

with respect to AGND V

EE

V

with respect to A/BGND V

Bat2

V

with respect to BGND, continuous V

Bat

V

with respect to BGND, 10 ms V

Bat2

≤ +70°C

Amb

Stg

Amb

J

CC

EE

Bat2

Bat

Bat2

Power dissipation

Continuous power dissipation at T

≤ +70°CP

Amb

D

Ground

Voltage between AGND and BGND V

G

Relay Driver

Ring relay supply voltage BGND +13 V
Ring relay current 75 mA

-55 +150 °C

-40 +110 °C

-40 +140 °C

-0.4 6.5 V
V

Bat

V

Bat

0.4 V

0.4 V

-75 0.4 V

-80 0.4 V

0.8 W

-5 VCC V

Ring trip comparator

Input voltage V
Input current I

, V

DT

, I

DT

DR

V

DR

Bat

V

-5 5 mA

CC

V

Digital inputs, outputs (C1, C2, C3, DET)
Input voltage V

Output voltage (DET not active) V
Output current (DET) I

TIPX and RINGX terminals, 0°C < T

< +70°C, V

Amb

= -50 V

Bat

TIPX or RINGX current I
TIPX or RINGX voltage, continuous (referenced to AGND), Note 2 V
TIPX or RINGX, pulse < 10 ms, t
TIPX or RINGX, pulse < 1 µs, t
TIP or RING, pulse < 250 ns, t

> 10 s, Note 2 VTA, V

Rep

> 10 s, Note 2 VTA, V

Rep

> 10 s, Note 3 VTA, V

Rep

ID

OD

OD

TIPX

TA

, I

, V

-0.4 V

-0.4 V

-110 +110 mA

RINGX

V

RA

RA

RA

RA

Bat

V

- 20 5 V

Bat

V

- 40 10 V

Bat

V

- 70 15 V

Bat

2V

CC

CC

V
V

30 mA

Recommended Operating Condition

Parameter Symbol Min Max Unit

Ambient temperature T
V

with respect to AGND V

CC

V

with respect to AGND V

EE

V

with respect to BGND V

Bat

V

with respect to BGND V

Bat2

Amb

CC

EE

Bat

Bat2

0 +70 °C

4.75 5.25 V
V

Bat

-4.75 V

-58 -10 V
V

Bat

-10 V

Notes

1. The circuit includes thermal protection. Operation above max. junction temperature may degrade device reliability.

2. A diode in series with the VBat input increases the permitted continuous voltage and pulse < 10 ms to -85 V.

A pulse ≤1µs is increased to the greater of |-70V| and |VBat -40V|.

3. R

2

and RF2 ≥ 20 Ω is also required. Pulse is supplied to TIP and RING outside RF1 and RF2.

F1

Electrical Characteristics

0 °C ≤ T
R

= 600 Ω, RLD = 50 kΩ, RF1, RF2 = 0 Ω, R

L

current is positive if flowing into a pin. Active state includes active normal unless otherwise specified.
Battery definition: V

≤ +70 °C, VCC = +5V ±5 %, VEE = -5V ± 5%, V

Amb

= On-hook battery, V

Bat

= 15kΩ, CHP = 68nF, CLP=0.47 µF, RT = 120 kΩ, RRX = 120 kΩ, Current definition:

Ref

= Off-hook battery.

Bat2

= -58V to -40V, V

Bat

= -22V, RLC=18.7kΩ (IL = 27 mA),

Bat2

PBL 386 14/1

Parameter fig Conditions Min Typ Max Unit

Ref

Two-wire port

Overload level, V
Off-Hook, I
On-Hook, I
Metering I
Input impedance, Z
Longitudinal impedance, Z
Longitudinal current limit, I

TRO

≥ 10 mA 1% THD, Note 1 1.0 V

LDC

≤ 5 mA 1.0 V

LDC

≥ 10 mA Z

LDC

TR

LoT

LoT

, Z
, I

LoR

LoR

Longitudinal to metallic balance, B

LM

2 Active state

= 200 Ω, f = 16 kHz 0.7 V

LTTX

Note 2 ZT/200
0 < f < 100 Hz 20 35 Ω/wire
active state 12 mA
IEEE standard 455-1985, ZTRX = 736 Ω

rms

Peak

Peak

Peak

/wire

0.2 kHz < f < 1.0 kHz 53 70 dB

1.0 kHz < f < 3.4 kHz 53 70 dB

Longitudinal to metallic balance, B
E

B

= 20 • Log 0.2 kHz ≤ f ≤ 1.0 kHz 53 70 dB

LME

V

Lo

TR

Longitudinal to four-wire balance, B
E

B

= 20 • Log 0.2 kHz ≤ f ≤ 1.0 kHz 59 70 dB

LFE

V

Lo

TX

Metallic to longitudinal balance, B

VTR

B

= 20 • Log ;ERX = 0 0.2 kHz < f < 3.4 kHz 40 58 dB

MLE

V

Lo

LME

LFE

MLE

3 active state

1.0 kHz < f < 3.4 kHz 53 70 dB

3 active state

1.0 kHz < f < 3.4 kHz 59 70 dB

4 active state

Figure 2. Overload level, V

, two-wire

TRO

port

1
<< R
wC

R

T

, RL= 600 Ω

L

= 120 kΩ, RRX = 120 kΩ

Figure 3. Longitudinal to metallic (B
and Longitudinal to four-wire (B

LFE

balance

1
<< 150 Ω, R
wC

= RLT = RL /2= 300Ω

LR

RT = 120 kΩ, RRX = 120 kΩ

C

R

)

LME

)

E

Lo

V

L

TRO

C

I

LDC

R

LT

R

LR

V

TR

TIPX

VTX

PBL 386 14/1

RINGX

TIPX

RSN

VTX

PBL 386 14/1

RINGX RSN

R

T

R

RX

R

T

R

RX

E

RX

V

TX

3

PBL 386 14/1

Parameter fig Conditions Min Typ Max Unit

Four-wire to longitudinal balance, B

FLE

Ref

4 active state

B

= 20 • Log

FLE

E

RX

V

Lo

0.2 kHz < f < 3.4 kHz 40 58 dB

Two-wire return loss, r |Z

r = 20 • Log

+ ZL|

TR

- ZL|

|Z

TR

0.2 kHz < f < 0.5 kHz 25 dB

0.5 kHz < f < 1.0 kHz 27 dB

1.0 kHz < f < 3.4 kHz, Note 3 23 dB
TIPX idle voltage, V
RINGX idle voltage, V
|V

| active, IL = 0 |V

TR

Ti

Ri

active normal, IL = 0 - 1.3 V
active normal, IL = 0 V

+5.5| |V

Bat

+3.1 V

Bat

+ 4.5| V

Bat

Four-wire transmit port (VTX)
Overload level, V
Off-hook, I

TXO

≥ 10mA Load impedance > 20 kΩ, 0.5 V

L

On-hook, IL ≤ 5mA 1% THD, Note 4 0.5 V
Output offset voltage, ∆V
Output impedance, z

TX

TX

5

Peak
Peak

-60 60 mV

0.2 kHz < f < 3.4 kHz 5 20 Ω
Four-wire receive port (RSN)

Receive summing node (RSN) dc voltage I

= 0 mA GND +25 mV

RSN

Receive summing node (RSN) impedance 0.2 kHz < f < 3.4 kHz 10 50 Ω
Receive summing node (RSN) 0.3 kHz < f < 3.4 kHz
current (I
gain,α

) to metallic loop current (IL) 400 ratio

RSN

RSN

Frequency response

Two-wire to four-wire, g

2-4

6 relative to 0 dBm, 1.0 kHz. ERX = 0 V

0.3 kHz < f < 3.4 kHz -0.15 0.15 dB

f = 8.0 kHz, 12 kHz, 16 kHz -0.5 0 0.1 dB

Figure 4. Metallic to longitudinal and

TIPX

R

C

V

Lo

LT

V

TR

PBL 386 14/1

R

LR

RINGX RSN

C

R

L

I

LDC

E

L

VTX

TIPX

VTX

PBL 386 14/1

RINGX RSN

R

T

R

RX

E

RX

R

T

R

RX

V

TXO

four-wire to longitudinal balance

1
<< 150 Ω, R
ωC

= RLR = RL /2 =300Ω

LT

RT = 120 kΩ, RRX = 120 kΩ

Figure 5. Overload level, V
transmit port

1
<< R
ωC

= 120 kΩ, RRX = 120 kΩ

R

T

, RL = 600 Ω

L

, four-wire

TXO

4

PBL 386 14/1

Parameter fig Conditions Min Typ Max Unit

Four-wire to two-wire, g

4-2

Ref

6 relative to 0 dBm, 1.0 kHz. EL = 0 V

0.3 kHz < f < 3.4 kHz -0.15 0.15 dB

f = 8 kHz, 12 kHz, -1.0 -0.2 0 dB
16 kHz -1.0 -0.3 0 dB

Four-wire to four-wire, g

4-4

6 relative to 0 dBm, 1.0 kHz. EL = 0 V

0.3 kHz < f < 3.4 kHz -0.15 0.15 dB

Insertion loss

Two-wire to four-wire, G

Four-wire to two-wire, G

2-4

4-2

6 0 dBm, 1.0 kHz, Note 5

V

G

= 20 • Log ,ERX = 0

2-4

TX

V

TR

6 0 dBm, 1.0 kHz, Notes 5, 6

V

G

= 20 • Log ,EG = 0

4-2

TR

E

RX

-6.22 -6.02 -5.82 dB

-0.2 0.2 dB

Gain tracking

Two-wire to four-wire R

≤ 2kΩ 6 Ref. -10 dBm, 1.0 kHz, Note 7

LDC

-40 dBm to +3 dBm -0.1 0.1 dB

-55 dBm to -40 dBm -0.2 0.2 dB
Four-wire to two-wire R

≤ 2kΩ 6 Ref. -10 dBm, 1.0 kHz, Note 7

LDC

-40 dBm to +3 dBm -0.1 0.1 dB

-55 dBm to -40 dBm -0.2 0.2 dB

Noise

Idle channel noise at two-wire C-message weighting 7 12 dBrnC
(TIPX-RINGX) Psophometrical weighting -83 -78 dBmp

Note 8

Harmonic distortion

Two-wire to four-wire 6 0 dBm, 1.0 kHz test signal -50 dB
Four-wire to two-wire 0.3 kHz < f < 3.4 kHz -50 dB

Battery feed characteristics

Constant loop current, I

LConst

13 I

=

LProg

18 < I

500

R

LC

< 30 mA 0.95 I

LProg

LProg

I

LProg

1.05 I

LProg

mA

Figure 6.
Frequency response, insertion loss,
gain tracking.

1
<< R
ωC

, RL = 600 Ω

L

RT = 120 kΩ, RRX = 120 kΩ

R

L

E

L

C

V

TR

I

LDC

TIPX

VTX

PBL 386 14/1

RINGX RSN

R

T

R

RX

E

RX

V

TX

5

PBL 386 14/1

Parameter fig Conditions Min Typ Max Unit

Ref

Loop current detector

Programmable threshold, I
I

> 10 mA R

LTh

DET

500 0.9•I

I

=

LTh

LD

LThILTh

1.1•I

LTh

mA

Ground key detector

Ground key detector threshold
I

LTIPX

and I

current difference to trigger ground key det. 11 15 19 mA

LRINGX

Ring trip comparator

Offset voltage, ∆V
Input bias current, I

DTDR

B

Input common mode range, V

, V

DT

DR

Source resistance, RS = 0 Ω -20 0 20 mV
IB = (IDT + IDR)/2 -50 -20 nA

V

+1 -1 V

Bat

Ring relay driver

Saturation voltage, V

OL

Off state leakage current, I

Lk

IOL = 50 mA 0.2 0.5 V
V

= 12 V 100 µA

OH

Digital inputs (C1, C2, C3)
Input low voltage, V
Input high voltage, V
Input low current, |I
Input high current, I

IL

IH

|V

IL

IH

= 0.5 200 µA

IL

VIH = 2.5 V 200 µA

0 0.5 V

2.5 V

CC

V

Detector output (DET)
Output low voltage, V

Internal pull-up resistor to V
Power dissipation (V

P

1

@ VEE=-5V Active State I

P

2

P

@ VEE=VB2 Active State ILo = 0 mA, IL = 0 mA 40 47 mW

3

P

@ VEE = -5V Active RL = 300Ω (off-hook) 415 mW

4

P

@ VEE = -5V Active RL = 600Ω (off-hook) 200 mW

5

Power supply currents (V
V

current, I

CC

V

current, I

EE

V

current, I

Bat

V

current, I

CC

V

current, I

EE

V

current, I

Bat

CC
EE
Bat
CC
EE
Bat

OL

CC

= -48V, V

Bat

Bat

= -48V)

= -22V, note 9)

Bat2

, On-hook Active State ILo= 0 mA, IL = 0 mA -0.8 -0.5 mA

IOL = 1 mA 0.1 0.6 V

10 kΩ

Open circuit state 15 18 mW

= 0 mA, IL = 0 mA 37 44 mW

Lo

Open circuit state 1.3 mA
Open circuit state -0.2 -0.1 mA
Open circuit state -0.2 -0.1 mA
Active State ILo= 0 mA, IL = 0 mA 2.1 3.5 mA
Active State ILo= 0 mA, IL = 0 mA 0.1 0.3 mA

Power supply rejection ratios

VCC to 2- or 4-wire port Active State, f = 1 kHz, Vn = 100mV 30 45 dB
V

to 2- or 4-wire port Active State, f = 1 kHz, Vn = 100mV 28.5 55 dB

EE

V

to 2- or 4-wire port Active State, f = 1 kHz, Vn = 100mV 45 60 dB

Bat

V

to 2- or 4-wire port Active State, f = 1 kHz, Vn = 100mV 28.5 60 dB

Bat2

Temperature guard

Junction threshold temperature, T

JG

140 °C

Thermal resistance
28-pin SSOP, θ

JP28SSOP

55 °C/W

6

PBL 386 14/1

Notes

1. The overload level is automatically expanded to 2.5 V

when the signal level > 1.0 V

and is specified at the

Peak

two-wire port with the signal source at the four-wire
receive port.

2. The two-wire impedance is programmable by selection of

external component values according to:

= ZT/|G

Z

TR

Z

= impedance between the TIPX and RINGX

TR

2-4S αRSN

| where:

terminals

ZT= programming network between the VTX and RSN

terminals

G

= transmit gain, nominally = -0.5

2-4S

= receive current gain, nominally = 400 (current

α

RSN

defined as positive flowing into the receivesumm­ing node, RSN, and when flowing from tip to ring).

3. Higher return loss values can be achieved by adding a

reactive component to R

, the two-wire terminating

T

impedance programming resistance, e.g. by dividing R
into two equal halves and connecting a capacitor from the
common point to ground.

Peak

T

4. The overload level is automatically expanded as needed up
to 1.25 V

when the signal level >0.5 V

Peak

Peak

and is
specified at the four-wire transmit port, VTX, with the signal
source at the two-wire port. Note that the gain from the
two-wire port to the four-wire transmit port is G

5. Secondary protection resistors R
The specified insertion loss is for R

impact the insertion loss.

F

F

= 0.

2-4S

= -0.5.

6. The specified insertion loss tolerance does not include
errors caused by external components.

7. The level is specified at the four-wire receive port and
referenced to a 600 Ω programmed two-wire impedance
level.

8. The two-wire idle noise is specified with the four-wire
receive port grounded (E

= 0; see figure 6).

RX

The four-wire idle noise at VTX is the two-wire value -6 dB
and is specified with the two-wire port terminated in 600 Ω

). The noise specification is referenced to a 600 Ω

(R

L

programmed two-wire impedance level at VTX. The four­wire receive port is grounded (ERX = 0).

9. The V
programmed linecurrent, I

voltage is optimized for RL=600 Ω with a

Bat2

=27 mA. This gives V

L

=22 V at

Bat2

the terminal (e.g. calculated to 21.9V).

7

PBL 386 14/1

Pin Description

Refer to figure 7.

SSOP Symbol Description

1 RRLY Ring Relay driver output.
2 TS Tip Sense should be connected to TIPX.
3 HP High Pass connection for ac/dc separation capacitor CHP. Other end of CHP connects to RINGX (pin 26).
4 RINGX The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage

protection components and ring relay (and optional test relay).
5 BGND Battery Ground, should be tied together with AGND.
6 TIPX The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage

protection components and ring relay (and optional test relay).
7 VBAT On-hook battery voltage. Negative with respect to BGND.

8 VBAT2 Off-hook battery voltage, connected in series with a diode.
9 NC No Connect. Must be left open.

10 PSG Programmable Saturation Guard. Must be connected to VBAT2.
11 LP Low Pass saturation guard filter capacitor connected here to filter out noise and improve PSRR. Other end of

connects to VBAT2.

C
12 DT Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level

13 DR Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level

14 NC No Connect. Must be left open.
15 NC No Connect. Must be left open.

16 VEE -5V power supply, if not -5 V available connect to VB2 or VBAT (VB2 lower power dissipation than VBAT).
17 REF A 15kΩ resistor must be connected between this pin and AGND.
18 NC No Connect. Must be left open.
19 PLC Prog. Line Current, the constant current part of the DC feed characteristic is programmed by a resistor

20 PLD Programmable Loop Detector threshold. The loop detection threshold is programmed by a resistor

21 VCC +5 V power supply.
22 C3

23 C2 Operating states for details.
24 C1

25 DET Detector output. Active low when indicating loop or ring trip detection, active high when indicating ground

26 RSN Receive Summing Node. 400 times the current flowing into this pin equals the metallic (transversal) current

27 AGND Analog Ground, should be tied together with BGND.
28 VTX Transmit vf output. The ac voltage difference between TIPX and RINGX, the ac metallic voltage, is

}

LP

low, indicating off-hook condition. The ring trip network connects to this input.

low, indicating off-hook condition. The ring trip network connects to this input.

connected from this pin to AGND.

connected from this pin to AGND.

C1, C2 and C3 are digital inputs Controlling the SLIC operating states. Refer to section

key detection, active low when indicating temperature alarm.

flowing from TIPX to RINGX. Programming networks for two-wire impedance and receive gain connect to the

receive summing node.

reproduced as an unbalanced GND referenced signal at VTX with a gain of -0.5. The two-wire impedance

programming network connects between VTX and RSN.

8

PBL 386 14/1

RRLY

TS

HP

RINGX

BGND

TIPX

VBAT

VBAT2

*NC

PSG

LP

DT

DR

*NC

1
2
3
4
5
6

28-pin SSOP

7
8

9
10
11

12

13

14

28
27
26
25
24
23
22
21
20
19
18

17

16

15

VTX
AGND
RSN
DET

C1
C2
C3

VCC
PLD

PLC
NC*

REF
VEE
NC*

* Pins must be left open.

Figure 7. Pin configuration 28 pin SSOP package, top view.

SLIC Operating States

State C3 C2 C1 SLIC operating state Active detector

0 0 0 0 Open circuit Detector is set high
1 0 0 1 Ringing state Ring trip detector (active low)
2 0 1 0 Active state Loop detector (active low)
3 0 1 1 Active state Line Voltage measurament (pulse train)
4 1 0 0 Active state Temperature guard (active low)
5 1 0 1 Active state Ground key detector (active high)
6 1 1 0 Not applicable
7 1 1 1 Not applicable

Table 1. SLIC operating states.

9

PBL 386 14/1

R

F

R

F

RINGX

TIPX

+

R

G

HP

2-4S

-

TIP

+

Z

L

Z

V

TR

TR

-

E

L

-

+

RING

PBL 386 14/1

Figure 9. Simplified AC transmission circuit.

Functional Description and Applications
Information Transmission

General

A simplified AC model of the transmission
circuits is shown in figure 9. Circuit analysis
yields:

V

V

TR

G
VTX + VRX = I

Z

T

VTR = IL • ZL - E

TX

=

2-4S

ZRX α

- I

L

RSN

• 2R

L

L

(1)

F

(2)

(3)

where:
V

is a ground referenced version

TX

of the ac metallic voltage
between the TIPX and RINGX
terminals.

V

is the ac metallic voltage

TR

between tip and ring.

E

is the line open circuit ac metallic

L

voltage.

I

is the ac metallic current.

L

R

is a fuse resistor.

F

G

is the SLIC two-wire to four-

2-4S

wire gain (transmit direction) with
a nominal value of -0.5.
(phase shift 180°.)

Z

is the line impedance.

L

Z

determines the SLIC TIPX to

T

RINGX impedance for signal in
the 0 - 20kHz frequency range.

Z

controls four- to two-wire gain.

RX

is the analogue ground referenced

V

RX

receive signal.

α

is the receive summing node

RSN

current to metallic loop current
gain. The nominal value of

α

= 400

R

RSN

Internal resistor appprox. 180 kΩ

HP

Two-Wire Impedance

To calculate Z

, the impedance presented

TR

to the two-wire line by the SLIC including
the fuse resistor RF, let VRX = 0.

From (1) and (2):

ZT

ZTR =
α

Thus with ZTR, G

= α

Z

T

RSN

RSN

• G

• G

2-4S

, α

2-4S

• (2RF - |ZTR|)

2-4S

Two-Wire to Four-Wire Gain

From (1) and (2) with VRX = 0:

VTX = ZT/α

G

=

2-4

VTR ZT
α

RSN

• G

- 2R

F

, and RF known:

RSN

RSN

- 2R

2-4S

I

L

VTX

I

L

/α

I

RSN

L

RSN

Z

T

Z

RX

+

V

TX

-

+

V

RX

-

Four-Wire to Two-Wire Gain

From (1), (2) and (3) with EL = 0:

V

= ZT • Z

TR

=

G

4-2

VRX ZRX ZT
α

RSN

- G

L

2-4S

• ( ZL + 2RF)

In applications where
2RF - ZT/(α
to ZL, the expression for G

= -

G

4-2

ZRX 2 • G

Z

RSN

• 1

T

• G

) is chosen to be equal

2-4S

2-4S

simplifies to:

4-2

Four-Wire to Four-Wire Gain

From (1), (2) and (3) with E

VTX = ZT • G

G

=

4-4

VRX ZRX ZT
α

F

RSN

= 0:

L

• ( ZL + 2RF)

2-4S

- G

• ( ZL + 2RF)

2-4S

10

PBL 386 14/1

Hybrid Function

The hybrid function can easily be imple­mented utilizing the uncommitted amplifier
in conventional CODEC/filter combinations.
Please, refer to figure 10. Via impedance

a current proportional to VRX is injected

Z

B

into the summing node of the combination
CODEC/filter amplifier. As can be seen
from the expression for the four-wire to
four-wire gain a voltage proportional to V

RX

is returned to VTX. This voltage is converted
by RTX to a current flowing into the same
summing node. These currents can be
made to cancel by letting:

VTX + VRX
RTX Z

The four-wire to four-wire gain, G

= 0 (EL = 0)

B

, in-

4-4

cludes the required phase shift and thus
the balance network ZB can be calculated
from:

ZRX

•

VRX

•

=

TX

• ( ZL + 2RF)

- G

RSN

2-4S

• ( ZL + 2RF)

2-4S

α

Z

= - RTX •

B

V
ZT

- R

TX

ZT G
When choosing RTX, make sure the

output load of the VTX terminal is (R

//R

TX

in Figure 14) > 20 kΩ.

If calculation of the Z

formula above

B

yields a balance network containing an
inductor, an alternate method is recom­mended.

The PBL 386 14/1 SLIC may also be
used together with programmable CODEC/
filters. The programmable CODEC/filter
allows for system controller adjustment of
hybrid balance to accommodate different
line impedances without change of hard­ware. In addition, the transmit and receive
gain may be adjusted. Please, refer to the
programmable CODEC/filter data sheets
for design information.

Longitudinal Impedance

A feed back loop counteracts longitudinal
voltages at the two-wire port by injecting
longitudinal currents in opposing phase.

Thus longitudinal disturbances will ap­pear as longitudinal currents and the TIPX
and RINGX terminals will experience very
small longitudinal voltage excursions, leav­ing metallic voltages well within the SLIC
common mode range.

The SLIC longitudinal impedance per wire,
Z

LoT

and Z

, appears as typically 20 Ω to

LoR

longitudinal disturbances. It should be not­ed that longitudinal currents may exceed
the dc loop current without disturbing the vf
transmission.

Capacitors CTC and C

If RFI filtering is needed, the capacitors

T

designated CTC and CRC in figure 13, con-

RC

nected between TIPX and ground as well
as between RINGX and ground, may be
mounted.

CTC and CRC work as RFI filters in con­junction with suitable series impedances

(i.e. resistances, inductances). Resistors
RF1 and RF2 may be sufficient, but series
inductances can be added to form a sec­ond order filter. Current-compensated in­ductors are suitable since they suppress
common-mode signals with minimum influ­ence on return loss. Recommended values
for CTC and CRC are below 1 nF. Lower
values impose smaller degradation on re­turn loss and longitudinal balance, but also
attenuate radio frequencies to a smaller
extent. The influence on the impedance
loop must also be taken into consideration
when programming the CODEC. CTC and
CRC contribute to a metallic impedance of
1/(π•f•CTC) = 1/(π•f•CRC), a TIPX to ground
impedance of 1/(2•π•f•CTC) and a RINGX to
ground impedance of 1/(2•π•f•CRC).

AC - DC Separation Capacitor, C

HP

The high pass filter capacitor connected
between terminals HP and RINGX pro­vides the separation of the ac and dc
signals. CHP positions the low end frequen­cy response break point of the ac loop in the
SLIC. Refer to table 1 for recommended
value of CHP.

Example: A CHP value of 68 nF will
position the low end frequency response
3dB break point of the ac loop at 13 Hz (f
according to f

= 1/(2•π•R

3dB

HP•CHP

3dB

) where

RHP = 180 kΩ.

)

386 14/1

Figure 10. Hybrid function.

PBL

VTX

RSN

R

TX

V

T

Z

T

Z

B

Combination
CODEC/Filter

Z

RX

V

RX

11

PBL 386 14/1

High-Pass Transmit Filter

When CODEC/filter with a single 5 V power
supply is used, it is necessary to separate
the different signal reference voltages be­tween the SLIC and the CODEC/filter. In
the transmit direction this can be done by
connecting a capacitor between the VTX
output of the SLIC and the CODEC/filter
input. This capacitor will also form, togeth­er with RTX and/or the input impedance of
the CODEC/filter, a high-pass RC filter. It is
recommended to position the 3 dB break
point of this filter between 30 and 80 Hz to
get a fast enough response for the dc steps
that may occur with DTMF signaling.

1 V

Peak

Capacitor C

LP

The capacitor CLP, which connects between
the terminals LP and VBAT2, positions the
high end frequency break point of the low
pass filter in the dc loop in the SLIC. C
together with CHP and ZT (see section Two­Wire Impedance) forms the total two wire
output impedance of the SLIC.

R

FEED

C

C

LP

HP

[Ω] [nF] [nF]

•25 470 68

2

Table 1. CLP and CHP values.

Adaptive Overhead Voltage, AOV

The Adaptive Overhead Voltage feature
minimizes the power dissipation and at the
same time provides a flexible solution for
different system requirements and possi­ble future changes concerning voice, me­tering and other signal levels. This is done
by using an overhead voltage which auto­matically adapts to the signal level (voice +
metering).

The PBL38615/1 will behave as a SLIC
with fixed overhead for signals in the 0­20kHz range and with an amplitude less
than 1V
1V

Peak

function will expand the overhead voltage

. For signal amplitudes between

peak

and 2.5V

the adaptive overhead

Peak

making it possible for the signal to propa­gate through the SLIC without distortion (
This is the total sum of voice and metering
signal). The expansion of the overhead
occurs instantaneously. When the signal
amplitude decreases, the overhead returns
to its initial value with a time constant of
approximately one second (see figure 11).

2.50 V

2.50 V

2.50 V

Figure 11. The AOV funktion when the AOV-pin is left open. (Observe, burst
undersampled).

LP

During operation the influence of the adap­tive overhead function will not effect the
SLIC performance in the constant current
region of operation (see figure 11). If,

The open loop voltage, V
between the TIPX and RINGX terminals
tracks the battery voltage VBAT(references
J in Figure 16). According to the formula:

however, the SLIC is in the off-hook,
constant voltage region of operation then

V

TRMAX =

| VBAT | -4.6
the influence of the adaptive headroom will
be apparent as a slight decrease in line
voltage (and hence line current) as the
SLIC adjusts to accommodate the larger
(voice + metering) signal.

When the line current is approaching

open loop conditions (references G in Figure

16) the overhead voltage is reduced. The
line voltage is kept nearly constant with a
steep slope corresponding to 2x25 Ω

Line Feed

If V

< | VBAT2 | -5.7 approx (See formula

TR

C in Figure 16). the PBL 386 14/1 SLIC will
emulate constant current feed. (references

(references H in Figure 16), to ensure
maximum open loop voltage, even with a
leaking telephone line.

Constant Current Region

A-C in Figure 16). The constant current
region is adjustable between 18 mA and 30
mA.

If V

> | VBAT2 | -5.7 approx (See

TR

formula C in Figure 16). the PBL 38615/1
SLIC will emulate a constant voltage feed
with 2 x 25 Ω source impedance (refer­ences C-E in Figure 16). This section is
made as steep as possible to switch battery
faster.

If the loop current is less than 5.5mA then

The constant current (reference A-C in
Figure 16) is adjusted by connecting a
resistor, RLC, between terminal PLC and
ground according to the equation:

R

=

LC

I

500 - 10.4

LProg

• In (I

I

Can simplifies to:

500

=

R

LC

I

LProg

the SLIC will automatically switch to supply
the DC feed via Vbat rather than Vbat2
(references E in Figure 16). This will not
give any disturbances on the line.

LProg

TRMAX

LProg

, measured

• 32)

12

PBL 386 14/1

Battery Switch

To reduce short loop power dissipation, a
second battery voltage, Off-hook, must be
connected to the device via an external
diode at terminal VBAT2. The SLIC auto­matically switches between the two battery
supply voltages without need for external
control. The silent battery switching to VBAT
occurs when the line current is below 5.5
mA. This means that the current in the On­hook battery is limited to 6 mA. To calculate
the switching voltage use this formula (See
formula C in Figure 16):

=| VB2 | -4.4 - 50 · I

V

TR

If metering is used see section Metering
Applications down below.

Connect the terminal VBAT2 to the
second power supply via the diode DB2 in
Figure 14. A diode DBB connected between
VB and the VB2 power supply, see Figure
14, will make sure that the SLIC continues
to work on the second battery even if the
first battery voltage disappears.

The current commute between the differ­ent batteries as shown in figure 12, note
that some current is sourced from VB (typ.

0.5 mA, internal bias current) when the line
current is sourced from VB2. The next chart
(figure 13) is showing what power dissipa­tion the SLIC is using with different batter­ies and variation of the line.

LProg

mA
30

25

20

15

10

5

0

I

B2

I

B

Figure 12. Chart describing current in Vbat and Vbat2.

mW
800

700
600
500
400
300
200
100

28 V

25 V

0

22 V

V

BAT 2

∞ Ω10000Ω7500Ω5000Ω2500Ω1000Ω0Ω

∞ Ω10000Ω7500Ω5000Ω2500Ω1000Ω0Ω

Metering Applications, TTX

It is very easy to use PBL 386 14/1 in
metering applications; simply connect a
suitable resistor (R
capacitor (C
metering source. Capacitor C

TTX

all DC-voltages that may be superimposed
on the metering signal. The metering signal
gain can be calculated from the equation:

VTR

=

G

4-2TTX

V

ZT

R

TTX

α

TTX

Z

.

ZT + G

RSN

) in series with a

TTX

) between pin RSN and the

decouples

TTX

=

LTTX

2-4S

. (Z

LTTX

+ 2RF)

Figure 13. Chart describing Power dissipation with different Vbat2.

where:

V

is the wanted metering voltage

TTX

between the TIP and RING terminals

Z

is the line impedance seen by the 12

LTTX

or 16 kHz metering signal,

G

is the transmit gain through the SLIC,

2-4S

i e 0.5.

It is possible to mix voice voltage and
metering voltage up to 2.5 Vpeak (1.7 Vrms),
using AOV. Use following formula to
calculate the switching voltage of the Battery
Switch to get enough signal space.

V

=| VB2 | -3.4 -V

TR

voice-VTTX

where:
V

is the voice voltage, normaly 1 V

voice

V

is the the metering voltage in peak.

TTX

- 50 · I

LProg

peak

13

PBL 386 14/1

Analog Temperature Guard

The widely varying environmental
conditions in which SLICs operate may
lead to the chip temperature limitations
being exceeded. The PBL 386 14/1 SLIC
reduces the dc line current and the
longitudinal current limit when the chip
temperature reaches approximately 145°C
and increases it again automatically when
the temperature drops.

The detector output, DET, is forced to a
logic low level when the temperature guard
is active.

The Active state temperature guard is
exclusively viewed at detector output see
section Active Temperature guard.

Loop Monitoring Functions

The loop current, ground key and ring trip
detectors report their status through a com­mon output, DET. The status of the detec­tor pin, DET, is selected via the three bit
control interface C1, C2 and C3. Please
refer to section Control Inputs for a descrip­tion of the control interface.

Loop Current Detector

The loop current detector indicates that
the telephone is off hook and that DC
current is flowing in the loop by putting the
output pin DET, to a logic low level when
selected. The loop current detector thresh­old value, I
tector changes state, is programmable with
the RLD resistor. RLD connects between pin
PLD and ground and is calculated accord­ing to:

=

R

LD

I

Ground Key Detector

The ground key detector indicates when
the ground key is pressed (active) by put­ting the output pin DET to a logic high level
when selected. The ground key detector
circuit senses the difference between TIPX
and RINGX currents. The detector is trig­gered when the difference exceeds the
current threshold.

, where the loop current de-

LTh

500

LTh

Ring Trip Detector

Ring trip detection is accomplished by
connecting an external network to a com­parator in the SLIC with inputs DT and DR.
The ringing source can be balanced or
unbalanced e g superimposed on the bat­tery voltage or ground. The unbalanced
ringing source may be applied to either the
ring lead or the tip lead with return via the
other wire. A ring relay driven by the SLIC
ring relay driver connects the ringing source
to tip and ring.

The ring trip function is based on a polar­ity change at the comparator input when
the line goes off-hook. In the on-hook state
no dc current flows through the loop and
the voltage at comparator input DT is more
positive than the voltage at input DR. When
the line goes off-hook, while the ring relay
is energized, dc current flows and the com­parator input voltage reverses polarity.

Figure 14 gives an example of a ring trip
detection network. This network is applica­ble, when the ring voltage superimposed
on the battery voltage is injected on the ring
lead of the two-wire port. The dc voltage
across sense resistor RRT is monitored by
the ring trip comparator input DT and DR
via the filter network R1, R2, R3, R4, C1 and
C2. DT is more positive than DR, with the
line on-hook (no dc current). The DET
output will report logic level high, i.e. the
detector is not tripped. When the line goes
off-hook, while ringing, a dc current will flow
through the loop including sense resistor
RRT and will cause the input DT to become
more negative than input DR. This chang­es the output on the DET pin to logic level
low, i.e. tripped detector condition. The
system controller (or line card processor)
responds by de-energizing the ring relay
via the SLIC, i.e. ring trip.

Complete filtering of the 20 Hz ac compo­nent at terminals DT and DR is not neces­sary. A toggling DET output can be exam­ined by a software routine to determine the
duty cycle. Off-hook condition is indicated
when the DET output is at logic level low for
more than half the time.

Detector Output (DET)

The PBL 386 14/1 SLIC incorporates a
detector output driver designed as open
collector (npn) with a current sinking capa­bility of min 3 mA, and a 10 kΩ pull-up
resistor. The emitter of the drive transistor
is connected to AGND. A LED can be
connected in series with a resistor (≈1 kΩ)
at the DET output to visualize, for example
loop status.

Relay driver

The PBL 386 14/1 SLIC incorporates a
ring relay driver designed as open collector
(npn) with a current sinking capability of 50
mA.The emitter of the drive transistor is
connected to BGND. The relay driver has
an internal zener diode clamp to protect the
SLIC from inductive kick-back voltages. No
external clamp is needed.

Control Inputs

The PBL 386 14/1 SLIC has three digital
control inputs, C1, C2 and C3.
A decoder in the SLIC interprets the control
input condition and sets up the command­ed operating state.
C1 to C3 are internal pull-up inputs.

Open Circuit State

In the Open Circuit State the TIPX and
RINGX line drive amplifiers as well as other
circuit blocks are powered down. This caus­es the SLIC to present a high impedance to
the line. Power dissipation is at a minimum
and no detectors are active.

14

PBL 386 14/1

RING

TIP

VB2

KR

C

GG

R

F1

R

D

B

VB

E

RG

R

R

RF

OVP

F2

D

B2

D

BB

R

RT

+12 V /+5V

RESISTORS (values according to IEC­63 E96 series):

R

LD

R

LC

R

REF

R

T

R

TX

R

B

R

RX

R

1

R

2

R

3

R

4

R

RT

R

RF

RF1, R

= 49.9 kΩ 1% 1/10 W
= 18.7 kΩ 1% 1/10 W
= 15 kΩ 1% 1/10 W
= 105 kΩ 1% 1/10 W
= 32.4 kΩ 1% 1/10 W
= 57.6 kΩ 1% 1/10 W
= 105 kΩ 1% 1/10 W
= 604 kΩ 1% 1/10 W
= 604 kΩ 1% 1/10 W
= 249 kΩ 1% 1/10 W
= 280 kΩ 1% 1/10 W
= 332 Ω 5% 2 W
= 332 Ω 5% 2 W
= Line resistor, 40 Ω 1% match

F2

PBL 386 14/1

RRLY

TS

C

HP

HP

C

VB

1

R

2

RC

C

TC

C

B2

C

B

C

C

R

R

3

1

4

RINGX

BGND

TIPX

VBAT

VBAT2

NC

PSG

LP

LP

DT

DR

NC

C

2

CAPACITORS: (values according to
IEC-63 E6 series):

C

B

C

B2

C

VCC

C

VEE

C

TC

C

RC

C

HP

C

LP

C

GG

C

1

C

2

C

SPR

= 100 nF 100 V 20%
= 150 nF 100 V 20%
= 100 nF 10 V 20%
= 100 nF 10 V* 20%
= 1.0 nF 100 V 20%
= 1.0 nF 100 V 20%
= 68 nF 100 V 20%
= 470 nF 100 V 20%
= 220 nF 100 V 20%
= 330 nF 63 V 10%
= 330 nF 63 V 10%
= optional 10 V 20%

AGND

VTX

RSN

DET

C1

C2

C3

VCC

PLD

PLC

NC

REF

VEE

NC

VCC

R

LD

R

LC

R

REF

VEE

VBAT<VEE<-5 V

DIODES:
D

B

D

B2

D

BB

OVP:
Secondary protection ( e g Power
Innovations TISP PBL2). The ground termin­als of the secondary protection should be
connected to the common ground on the
Printed Board Assembly with a track as short
and wide as possible, preferably a
groundplane.

R

+5 V

T

R

TX

R

RX

SYSTEM CONTROL

INTERFACE

C

VCC

C

VEE

= 1N4448
= 1N4448
= 1N4448

­out

VCC

VEE

+

out
CODEC/

Filter

R

B

*100V if VEE pin connected to VBAT, VBAT2

Figure 14. Single-channel subscriber line interface with PBL 386 14/1 and combination CODEC/filter

Ringing State

In the ringing state the SLIC will behave as
in the active state with the exception that
the ring relay driver and the ring trip detec­tor are activated. The ring trip detector will
indicate off hook with a logic low level at the
detector output.

Active State

TIPX is the terminal closest to ground and
sources loop current while RINGX is the
more negative terminal and sinks loop cur­rent. The loop current or the ground key
detector is activated. The loop current de­tector indicates off hook with a logic low

Active Temperature guard state

The temperature guard indicates if an error
has occurred and the temperature guard is
activated. The output pin DET is forced to
a logic low level when activated .

level and the ground key detector indicates
active ground key with a logic high level
present at the detector output.

15

PBL 386 14/1

Line Voltage measurement

The line voltage is presented on the detec­tor output as a pulse train (see Figure 15)
with a frequency inversely proportional to
the voltage according to the equation:

106

freq =
|VTR| + 1

The line voltage measurement will be
started when entering this state from any
other state and the SLIC will be as in active
state except for the detector. The data can
be used in variety of ways, for example to
set transmission parameters in a program­mable CODEC, in line testing where short
circuits on the line can be detected and to
control the metering signal amplitude.

Overvoltage Protection

PBL 386 14/1 must be protected against
overvoltages on the telephone line. The
overvoltages could be caused for instance
by lightning, ac power contact and induc­tion. Refer to Maximum Ratings, TIPX and
RINGX terminals, for maximum continu­ous and transient voltages.

Secondary Protection

The circuit shown in Figure 14 utilizes series
resistors together with a programmable
overvoltage protector (e g Power Innova­tions TISP PBL2), serving as a secondary
protection.

The TISP PBL2 is a dual forward-con­ducting buffered p-gate overvoltage pro­tector. The protector gate references the
protection (clamping) voltage to negative
supply voltage (i.e. the battery voltage, VB).
As the protection voltage will track the
negative supply voltage the overvoltage
stress on the SLIC is minimized.

Positive overvoltages are clamped to
ground by a diode. Negative overvoltages
are initially clamped close to the SLIC neg­ative supply rail voltage and the protector
will crowbar into a low voltage on-state
condition, by firing an internal thyristor.

[Hz]

Figure 15. Line voltage measurment

A gate decoupling capacitor, C
ed to carry enough charge to supply a high
enough current to quickly turn on the thyris­tor in the protector. CGG should be placed
close to the overvoltage protection device.
Without the capacitor even the low induc­tance in the track to the VB supply will limit
the current and delay the activation of the
thyristor clamp.

The fuse resistors RF serve the dual
purposes of being non- destructive
energy dissipators, when transients are
clamped and of being fuses, when the
line is exposed to a power cross. If a
PTC is chosen for RF , note that it is
important to always use the PTC´s in
series with resistors not sensitive to
temperature, as the PTC will act as a
capacitance for fast transients and
therefore will not protect the TISP.

, is need-

GG

Power-up Sequence

No special power-up sequence is neces­sary except that ground has to be present
before all other power supply voltages.

The digital inputs C1 to C3 are internal

pull-up terminals.

Printed Circuit Board Layout

Care in Printed Circuit Board (PCB) layout
is essential for proper function;

The components connecting to the RSN
input should be placed in close proximity to
that pin, such that no interference is inject­ed into the RSN pin. Ground plane sur­rounding the RSN pin is advisable.

Analog ground (AGND) should be con­nected to battery ground (BGND) on the
PCB in one point.

RLC and R
AGND with short leads. Pin LP and pin
PSG are sensitive to leakage currents.

RSG and CLP connections to VBAT2 should
be short and very close to each other.

CB and CB2 must be connected with short
wide leads.

should be connected to

REF

16

PBL 386 14/1

A

[mA]

L

I

B

C

VTR [V]

A: IL (@ VTR = 0) = I

LConst

I

LConst

(typ) = I

LProg

=

500

RLC

.

B,C: IL = I

D: R

LConst

= 2 x 25 Ω

Feed

, VTR(@C)= V

E: IL ≈ 5.5 mA , VTR= V

F: V

(@IL =0) = V

APP

B2

- R

App

- R

App

*

- V

-3.7 * Is the forward voltage of diode D

F

Feed

. 5.5 mA

Feed

I

LProg

G: IL ≈ 5 mA

D

(13)

E

F

.

VBAT2

G

H

J

H: R

J: V

= 2 x 25 Ω

Feed

= |V

TRMAX

| - 4.6 @ IL = 0 mA

Bat

Figure 16. Battery feed characteristics (without the protection resistors on the line).

17

PBL 386 14/1

Ordering Information

Package Temp. Range Part No.

28pin SSOP Tape & Reel 0° - + 70 °C PBL 386 14/1 SHT

Information given in this data sheet is believed to be
accurate and reliable. However no responsibility is
assumed for the consequences of its use nor for any
infringement of patents or other rights of third
parties which may result from its use. No license is
granted by implication or otherwise under any patent
or patent rights of Ericsson Microelectronics AB.
These products are sold only according to Ericsson
Microelectronics general conditions of sale, unless
otherwise confirmed in writing.

Specifications subject to change without
notice.
1522-PBL 386 14/1 Uen Rev. R1A
© Ericsson Microelectronics AB, 2000

This product is an original Ericsson
product protected by US, European and
other patents.

Ericsson Microelectronics

SE-164 81 Kista-Stockholm, Sweden
Telephone: [phone]

18