Epson S1C33L03 User Manual

0 (0)

MF1574-01

CMOS 32-BIT SINGLE CHIP MICROCOMPUTER

S1C33L03

Technical Manual

S1C33L03 PRODUCT PART S1C33L03 FUNCTION PART

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency.

S1C33L03 Technical Manual

This ma nual des cribes the hardwa re specifications of the Seiko Epson original 32-bit microcomputer S1C33L03.

S1C33L03 PRODUCT PART

Describes t he hardware specifications of the S1C33L03 except for details of the peripheral circuits.

S1C33L03 FUNCTION PART

Describes de tails of all the peripheral circuit blocks for the S1C33 Family microcomputers.

Refer to the "S1C33000 Core CPU Manual" for details of the S1C33000 32-bit RISC CPU.

Configuration of product number

Devices

S1 C 33209 F 00E1

Development tools

S5U1 C 33000 H2 1

Packing specifications

00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C: TCP BR 2 directions 0D: TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape & reel FRONT 0G: TCP BT 4 directions 0H: TCP BD 4 directions 0J : TCP SL 2 directions 0K : TCP SR 2 directions 0L : Tape & reel LEFT 0M: TCP ST 2 directions 0N: TCP SD 2 directions 0P : TCP ST 4 directions 0Q: TCP SD 4 directions 0R: Tape & reel RIGHT 99 : Specs not fixed

Specification Package

D: die form; F: QFP

Model number Model name

C: microcomputer, digital products

Product classification

S1: semiconductor

Packing specifications

00: standard packing

Version

1: Version 1

Tool type

Hx : ICE Dx : Evaluation board Ex : ROM emulation board Mx: Emulation memory for external ROM Tx : A socket for mounting

Cx : Compiler package Sx : Middleware package

Corresponding model number

33L01: for S1C33L01

Tool classification

C: microcomputer use

Product classification

S5U1: development tool for semiconductor products

TABLE OF CONTENTS

S1C33L03 PRODUCT PART

Table of Contents

1Outline.....................................................................................................................................A-1

1.1Features.....................................................................................................................................A-1

1.2Block Diagram...........................................................................................................................A-3

1.3Pin Description............................................................................................................. .............A-4

1.3.1Pin Layout Diagram (plastic package) ......................................................................A-4

1.3.2Pin Functions .............................................................................................................A-5

2Power Supply.......................................................................................................................A-12

2.1Power Supply Pins..................................................................................................................A-12

2.2 Operating Voltage (V

2.3 Power Su pply for I/O Interface (V

2.4 Power Supply for An alog Circuits (AV

3Internal Memory...................................................................................................................A-14

3.1ROM and Boot Address..........................................................................................................A-14

3.2RAM.........................................................................................................................................A-15

4Peripheral Cir c uits ..............................................................................................................A-16

4.1List of Peripheral Circuits ........................................................................................................A-16

4.2I/O Memory Map......................................................................................................................A-17

5Power-Down Control...........................................................................................................A-65

DD, VSS).................................................................................................A-12

DDE)....................................................................................A-13

DDE).............................................................................A-13

6Basic External Wiring Diagram .........................................................................................A-68

7Precautions on Mounting...................................................................................................A-69

8Electrical Characteristics...................................................................................................A-71

8.1Absolute Maximum Rating......................................................................................................A-71

8.2Recommended Operating Conditions ....................................................................................A-72

8.3DC Characteristics ..................................................................................................................A-73

8.4Current Consumption..............................................................................................................A-75

8.5A/D Converter Characteristics................................................................................................A-76

8.6AC Characteristics...................................................................................................................A-78

8.6.1Symbol Descr ipt io n..................................................................................................A -7 8

8.6.2AC Characteristics Measurement Condition...........................................................A-78

8.6.3C33 Block AC Characteristic Tables.......................................................................A-79

8.6.4C33 Block AC Characteristic Timing Charts...........................................................A-87

8.6.5LCD Interface AC Characteristics ...........................................................................A-96

8.7Oscillation Characteristics.................................................................................................... A-107

8.8PLL Characteristics..............................................................................................................A-108

9Package ..............................................................................................................................A-109

9.1Plastic Package....................................................................................................................A-109

10 Pad Layou t .........................................................................................................................A-110

10.1 Pad Layout Diagram............................................................................................................. A-110

10.2 Pad Coordinate..................................................................................................................... A-111

S1C33L03 TECHNICAL MANUAL EPSON i

TABLE OF CONTENTS

Appendix A <Reference> External Device Interface Ti mi n gs.......................................... A-113

A.1DRAM (70ns)........................................................................................................................ A-114

A.2DRAM (60ns)........................................................................................................................ A-117

A.3ROM and Burst ROM........................................................................................................... A-121

A.4SRAM (55ns)........................................................................................................................A-123

A.5SRAM (70ns)........................................................................................................................A-125

A.68255A.................................................................................................................................... A-127

Appendix B Pin Characteristics........................................................................................... A-128

ii EPSON S1C33L03 TECHNICAL MANUAL

TABLE OF CONTENTS

S1C33L03 FUNCTION PART

Table of Contents

IOUTLINE

I-1 INTRODUCTION ............................................................................................................ B-I-1-1

I-2 BLOCK DIAGRAM......................................................................................................... B-I-2-1

I-3 LIST OF PINS.................................................................................................................B-I-3-1

List of External I/O Pins...............................................................................................................B-I-3-1

II CORE BLOCK

II-1 INTRODUCTION ........................................................................................................... B-II-1-1

II-2 CPU AND OPERATING MODE ................................................................................... B-II-2-1

CPU ............................................................................................................................................B-II-2-1

Standby Mode.............................................................................................................................B-II-2-2

HALT Mode.....................................................................................................................B-II-2-2

SLEEP Mode..................................................................................................................B-II-2-2

Notes on Standby Mode .................................................................................................B-II-2-3

Test Mode...................................................................................................................................B-II-2-3

Debug Mode ...............................................................................................................................B-II-2-3

Trap Table...................................................................................................................................B-II-2-4

II-3 INITI AL RESET .............................................................................................................B-II-3-1

Pins for Initial Reset....................................................................................................................B-II-3-1

Cold Start and Hot Start.............................................................................................................B-II-3-1

Power-on Reset..........................................................................................................................B-II-3-2

Reset Pulse.................................................................................................................................B-II-3-2

Boot Address ..............................................................................................................................B-II-3-3

Notes Related to Initial Reset.....................................................................................................B-II-3-3

II-4 BCU (Bus Control Unit)............................................................................................... B-II-4-1

Pin Assignment for External System Interface..........................................................................B-II-4-1

I/O Pin List................................................................................................................... ....B-II-4-1

Combination of System Bus Control Signals.................................................................B-II-4-3

Memory Area ..............................................................................................................................B-II-4-4

Memory Map...................................................................................................................B-II-4-4

External Memory Map and Chip Enable ........................................................................B-II-4-5

Using Internal Memory on External Memory Area.........................................................B-II-4-7

Exclusive Signals for Areas............................................................................................B-II-4 -7

Area 10............................................................................................................................B-II-4-8

Area 3..............................................................................................................................B-II-4-9

Setting External Bus Conditions ..............................................................................................B-II-4-10

Setting Device Type and Size......................................................................................B-II -4 -10

Setting SRAM Timing Conditions.................................................................................B-II-4-11

Setting Timing Conditions of Burst ROM.....................................................................B-II-4-12

Bus Operation...........................................................................................................................B-II-4-13

Data Arrangement in Memory......................................................................................B-II-4-13

Bus Operation of External Memory..............................................................................B-II-4-13

S1C33L03 TECHNICAL MANUAL EPSON iii

TABLE OF CONTENTS

Bus Clock..................................................................................................................................B-II-4-17

Bus Speed Mode..........................................................................................................B-II-4-18

Bus Clock Output..........................................................................................................B-II-4-18

Bus Cycles in External System Interface.................................................................................B-II-4-19

SRAM Read Cycles......................................................................................................B-II-4-19

Bus Timing....................................................................................................................B-II-4-20

SRAM Write Cycles ......................................................................................................B-II-4-21

Burst ROM Read Cycles .............................................................................................. B -II -4 -23

DRAM Direct Interface..............................................................................................................B-II-4-24

Outline of DRAM Interface............................................................................................B-II-4-24

DRAM Setting Conditions.............................................................................................B-II-4-25

DRAM Read/Write Cycles............................................................................................B-II-4-28

DRAM Refresh Cycles..................................................................................................B-II-4-31

Releasing External Bus............................................................................................................B-II-4-32

Power-down Control by External Device.................................................................................B-II-4-33

I/O Memory of BCU..................................................................................................................B-II-4-34

II-5 ITC (Interrupt Controller).............................................................................................B-II-5-1

Outline of Interrupt Functions.....................................................................................................B-II-5-1

Maskable Interrupts ........................................................................................................B-II-5-1

Interrupt Factors and Intelligent DMA ............................................................................B-II-5-3

Nonmaskable Interrupt (NMI).........................................................................................B-II-5-3

Interrupt Processing by the CPU....................................................................................B-II-5-3

Clearing Standby Mode by Interrupts.............................................................................B-II-5-3

Trap Table...................................................................................................................................B-II-5-4

Control of Maskable Interrupts...................................................................................................B-II-5-5

Structure of the Interrupt Controller................................................................................B-II-5-5

Processor Status Register (PSR)...................................................................................B-II-5-5

Interrupt Factor Flag and Interrupt Enable Register......................................................B-II-5-6

Interrupt Priority Register and Interrupt Levels..............................................................B-II-5-8

IDMA Invocation .........................................................................................................................B-II-5-9

HSDMA Invocation ...................................................................................................................B-II-5-11

I/O Memory of Interrupt Controller ...........................................................................................B-II-5-12

Programming Notes..................................................................................................................B-II-5-25

II-6 CLG (Cl o ck G e n era t o r)................................................................................................B-I I-6-1

Configuration of Clock Generator ..............................................................................................B-II-6-1

I/O Pins of Clock Generator.......................................................................................................B-II-6-2

High-Speed (OSC3) Oscilla ti on Circ ui t......................................................................................B-II-6-2

PLL ............................................................................................................................................B-II-6-3

Controlling Oscillation.................................................................................................................B-II-6-3

Setting and Switching Over the CPU Operatin g Clo ck .............................................................B-II-6-4

Power-Control Register Protection Flag....................................................................................B-II-6-5

Operation in Standby Mode .......................................................................................................B-II-6-5

I/O Memory of Clock Generator.................................................................................................B-II-6-6

Programming Notes....................................................................................................................B-II-6-9

II-7 DBG (Debug Unit).........................................................................................................B-II-7-1

Debug Circuit ..............................................................................................................................B-II-7-1

I/O Pins of Debug Circuit............................................................................................................B-II-7-1

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III PERIPHERAL BLOCK

III-1 INTRODUCTION ......................................................................................................... B-III-1-1

III-2 PRESCALER............................................................................................................... B-III-2-1

Configuration of Prescaler.........................................................................................................B-III-2-1

Source Clock .............................................................................................................................B-III-2-1

Selecting Division Ratio and Output Control for Prescaler ......................................................B-III-2-2

Source Clock Output to 8-Bit Programmable Timer.................................................................B-III-2-2

I/O Memory of Prescaler ...........................................................................................................B-III-2-3

Programming Notes...................................................................................................................B-III-2-8

III-3 8-BIT PROGRAMMABLE TIMERS............................................................................B-III-3-1

Configuration of 8-Bit Programmable Timer.............................................................................B-III-3-1

Output Pins of 8-Bit Programmable Timers..............................................................................B-III-3-1

Uses of 8-Bit Programmable Timers.........................................................................................B-III-3-2

Control and Operation of 8-Bit Programmable Timer...............................................................B-III-3-4

Control of Clock Output.............................................................................................................B-III-3-7

8-Bit Programmable Timer Interrupts and DMA.......................................................................B-III-3-8

I/O Memory of 8-Bit Programmable Timers............................................................................B-III-3-10

Programming Notes.................................................................................................................B-III-3-17

III-4 16-BIT PROGRAMMABLE TIMERS.......................................................................... B-III-4-1

Configuration of 16-Bit Programmable Timer...........................................................................B-III-4-1

I/O Pins of 16-Bit Programmable Timers..................................................................................B-III-4-2

Uses of 16-Bit Programmable Timers.......................................................................................B-III-4-3

Control and Operation of 16-Bit Programmable Timer ............................................................B-III-4-4

Controlling Clock Output ...........................................................................................................B-III-4-7

16-Bit Programmable Timer Interrupts and DMA.....................................................................B-III-4-9

I/O Memory of 16-Bit Programmable Timers..........................................................................B-III-4-12

Programming Notes.................................................................................................................B-III-4-25

III-5 WATCHDOG TIMER................................................................................................... B-III-5-1

Configuration of Watchdog Timer .............................................................................................B-III-5-1

Control of Watchdog Timer .......................................................................................................B-III-5-1

Operation in Standby Modes.....................................................................................................B-III-5-2

I/O Memory of Watchdog Timer................................................................................................B-III-5-3

Programming Notes...................................................................................................................B-III-5-3

III-6 LOW-SPEED (OSC1) OSCILLATION CIRCUIT.......................................................B-III-6-1

Configuration of Low-Speed (OSC1) Oscillation Circuit ..........................................................B-III-6-1

I/O Pins of Low-Spee d (OS C 1) Osc illa ti on Circ ui t ................................................................... B -III-6-1

Oscillator Types.........................................................................................................................B-III-6-2

Controlling Oscillation................................................................................................................B-III-6-3

Switching Over the CPU Operating Clo ck................................................................................B-III-6-3

Power-Control Register Protection Flag...................................................................................B-III-6-4

Operation in Standby Mode ......................................................................................................B-III-6-4

OSC1 Clock Output to External Devices ..................................................................................B-III-6-4

I/O Memory of Low-S p eed (O SC 1) Osc illa tion Circuit.............................................................B-II I-6 -5

Programming Notes...................................................................................................................B-III-6-8

S1C33L03 TECHNICAL MANUAL EPSON v

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III-7 CLOCK TIMER ............................................................................................................B-III-7-1

Configuration of Clock Timer.....................................................................................................B-III-7-1

Control and Operation of the Clock Timer................................................................................B-III-7-2

Interrupt Function.......................................................................................................................B-III-7-4

Examples of Use of Clock Timer...............................................................................................B-III-7-6

I/O Memory of Clock Timer.......................................................................................................B-III-7-7

Programming Notes.................................................................................................................B-III-7-12

III-8 SERIAL INTERFACE ..................................................................................................B-III-8-1

Configuration of Serial Interfaces..............................................................................................B-III-8-1

Features of Serial Interfaces .........................................................................................B-III-8-1

I/O Pins of Serial Interface.............................................................................................B-III-8-2

Setting Transfer Mode...................................................................................................B-III-8-3

Clock-Synchronized Interface ...................................................................................................B-III-8-4

Outline of Clock-Synchronized Interface.......................................................................B-III-8-4

Setting Clock-Synchroni ze d Interfa ce...........................................................................B-II I-8 -5

Control and Operation of Clock-Synchronized Transfer ..............................................B-III-8-7

Asynchronous Interface...........................................................................................................B-III-8-12

Outline of Asynchronous Interface..............................................................................B-III-8-12

Setting Asynchronous Inte rfa ce ..................................................................................B-III-8-13

Control and Operation of Asynchronous Transfer......................................................B-III-8-16

IrDA Interface...........................................................................................................................B-III-8-21

Outline of IrDA Interface..............................................................................................B-III-8-21

Setting IrDA Interface ..................................................................................................B-III-8-21

Control and Operation of IrDA Interface .....................................................................B-III-8-23

Serial Interface Interrupts and DMA........................................................................................B-III-8-24

I/O Memory of Serial Interface................................................................................................B-III-8-28

Programming Notes.................................................................................................................B-III-8-46

III-9 INPUT/OUTPUT PORTS.............................................................................................B-III-9-1

Input Ports (K Ports)..................................................................................................................B-III-9-1

Structure of Input Port....................................................................................................B-III-9-1

Input-Port Pins...............................................................................................................B-III-9-2

Notes on Use .................................................................................................................B-III-9-2

I/O Memory of Input Ports.............................................................................................B-III-9-3

I/O Ports (P Ports) .....................................................................................................................B-III-9-4

Structure of I/O Port.......................................................................................................B-III-9-4

I/O Port Pins...................................................................................................................B-III-9-4

I/O Control Reg is te r and I/O Mod e s ..............................................................................B-III-9-5

I/O Memory of I/O Ports.................................................................................................B-III-9-6

Input Interru p t ..........................................................................................................................B-III-9-12

Port Input Interrupt.......................................................................................................B-III-9-12

Key Input Interrupt .......................................................................................................B-III-9-14

Control Registe rs o f the Inte rru p t Contr oll er...............................................................B-II I-9 -16

I/O Memory for Input Interrupts...................................................................................B-III-9-18

Programming Notes.................................................................................................................B-III-9-25

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TABLE OF CONTENTS

IV ANALOG BLOCK

IV-1 INTRODUCTION .........................................................................................................B-IV-1-1

IV-2 A/D CONVERTER.......................................................................................................B-IV-2-1

Features and Structure of A/D Converter.................................................................................B-IV-2-1

I/O Pins of A/D Converter..........................................................................................................B-IV-2-2

Setting A/D Converter ...............................................................................................................B-IV-2-3

Control and Operation of A/D Conversion................................................................................B-IV-2-5

A/D Converter Interrupt and DMA.............................................................................................B-IV-2-7

I/O Memory of A/D Converter....................................................................................................B-IV-2-9

Programming Notes.................................................................................................................B-IV-2-15

VDMA BLOCK

V-1 INTRODUCTION ..........................................................................................................B-V-1-1

V-2 HSDMA (High-Speed DMA) .......................................................................................B-V-2-1

Functional Outline of HSDMA....................................................................................................B-V-2-1

I/O Pins of HSDMA.....................................................................................................................B-V-2-2

Programming Control Information..............................................................................................B-V-2-3

Setting the Registers in Dual-Ad dr es s Mod e .................................................................B -V -2 -3

Setting the Registers in Single -Ad dre s s Mode..............................................................B -V -2 -6

Enabling/Disabling DMA Transfer..............................................................................................B-V-2-7

Trigger Factor .............................................................................................................................B-V-2-8

Operation of HSDMA..................................................................................................................B-V-2-9

Operation in Dual-Address Mode...................................................................................B-V-2-9

Operation in Single-Address Mode..............................................................................B-V-2-12

Timing Chart..................................................................................................................B-V-2-13

Interrupt Function of HSDMA...................................................................................................B-V-2-15

I/O Memory of HSDMA.............................................................................................................B-V-2-17

Programming Notes..................................................................................................................B-V-2-36

V-3 IDMA (Intelligent DMA)...............................................................................................B-V-3-1

Functional Outline of IDMA........................................................................................................B-V-3-1

Programming Control Information..............................................................................................B-V-3-1

IDMA Invocation .........................................................................................................................B-V-3-5

Operation of IDMA......................................................................................................................B-V-3-8

Linking.......................................................................................................................................B-V-3-12

Interrupt Function of Intelligent DMA .......................................................................................B-V-3-13

I/O Memory of Intelligent DMA.................................................................................................B-V-3-14

Programming Notes..................................................................................................................B-V-3-17

S1C33L03 TECHNICAL MANUAL EPSON vii

TABLE OF CONTENTS

VI SDRAM CONTROLLER BLOCK

VI-1 INTRODUCTION......................................................................................................... B-VI-1-1

VI-2 SDRAM INTERFACE.................................................................................................B-VI-2-1

Outline of SDRAM Interface......................................................................................................B-VI-2-1

SDRAM Controller Block Diagram............................................................................................B-VI-2-1

I/O Pins and Connection ...........................................................................................................B-VI-2-2

I/O Pins...........................................................................................................................B-VI-2-2

Connection Examples.................................................................................................... B -V I-2 -2

SDRAM Controller Configuration..............................................................................................B-VI-2-5

Setting PLL.....................................................................................................................B-VI-2-5

BCU Configuration.........................................................................................................B-VI-2-5

SDRAM Setting Conditio ns ...........................................................................................B-VI-2 -6

SDRAM Operation...................................................................................................................B-VI-2-12

Synchronous Clock......................................................................................................B-VI-2-12

Power-up and Initializa tio n ..........................................................................................B-VI-2-13

SDRAM Commands ....................................................................................................B-VI-2-14

Burst Read Cycle.........................................................................................................B-VI-2-15

Single Read/Single Write.............................................................................................B-VI-2-16

Refresh Mode ..............................................................................................................B-VI-2-17

Power-down Mode.......................................................................................................B-VI-2-19

Bus Release Procedure...............................................................................................B-VI-2-19

I/O Memory of SDRAM Interface............................................................................................B-VI-2-21

Programming Notes.................................................................................................................B-VI-2-32

Examples of SDRAM Controller Initialization Program..........................................................B-VI-2-33

VII LCD CONTROLLER BLOCK

VII-1 INTRODUCTION........................................................................................................ B-VII-1-1

VII-2 LCD CONTROLLER..................................................................................................B-VII-2-1

Overview...................................................................................................................................B-VII-2-1

Features........................................................................................................................B-VII-2-1

Block Diagram...............................................................................................................B-VII-2-3

I/O Pins of the LCD Controller..................................................................................................B-VII-2-4

System Settings........................................................................................................................B-VII-2-5

Setting the BCU............................................................................................................B-VII-2-5

Display Memory ............................................................................................................B-VII-2-5

LCD Controller Setting Proce du re ................................................................................B-V II-2-6

Clock.............................................................................................................................B-VII-2-7

Setting the LCD Panel..............................................................................................................B-VII-2-8

Types of Panels ............................................................................................................B-VII-2-8

Resolution.....................................................................................................................B-VII-2-8

Display Modes ..............................................................................................................B-VII-2-9

Look-up Tables.......................................................................................................... B-VII-2-11

Frame Rates.............................................................................................................. B-VII-2-19

Other Settings............................................................................................................ B-VII-2-20

Display Control ...................................................................................................................... B-VII-2-21

Controlling LCD Power Up/Down.............................................................................. B-VII-2-21

Reading/Writing Display Data ................................................................................... B-VII-2-22

Setting the Display Start Address ............................................................................. B-VII-2 -22

Split-Screen Display .................................................................................................. B-VII-2-23

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TABLE OF CONTENTS

Virtual Screen and View Port....................................................................................B-VII-2-23

Inverting and Blanking the Display............................................................................ B-VII-2-25

Portrait Mode ............................................................................................................. B-VII-2-25

Power Save................................................................................................................B-VII-2-29

Controlling the GPIO Pins ......................................................................................... B-VII-2-30

I/O Memory of LCD Controller............................................................................................... B-VII-2-31

Programming Notes...............................................................................................................B-VII-2-42

Precautions on Using ICD33................................................................................................. B-VII-2-42

Examples of LCD Controller Setting Program...................................................................... B-VII-2-43

APPENDIX I/O MAP

S1C33L03 TECHNICAL MANUAL EPSON ix

S1C33L03

PRODUCT PART

1 OUTLINE

1 Outline

The S1C3 3L03 is a Seiko Epson original 32-bit microcomputer with a built-in LCD controller. It features high speed, low power and low-voltage operation and is most suitable for portable equipment that needs display function, such as information terminals, E-mail terminals, electronic dictionaries. The S1C33L03 consists of the S1C33000 32-bit RISC type CPU as the core, a bus control unit, a DMA controller, an interrupt controller, an LCD controller, an SDRAM controller, timers, serial interface circuits, an A/D converter, ROM and RAM. The S1C3 3L03 provides a DSP function, by using the internal MAC (multiplication and accumulation) operation function with the A/D converter, it makes it possible to design simply speech recognition and voice synthesis systems.

Table 1.1 Model Lineup

Model Package Internal RAM Internal ROM Data bus I/F

S1C33L03F00A 10 0 QFP20-144pin 8K bytes None CMOS/LV TTL S1C33L03F00A200 S1C33L03D00A1 00 Chip 8K bytes None CMOS/LV TTL

QFP20-144pin

(Pb-free package)

1.1 Features

Core CPU

Seiko Epson original 32-bit R IS C CPU S1C 3300 0 b uil t-i n

•Basic instruction set: 105 instructions (16-bit fixed size)

•Sixteen 32-bit general-purpose register

•32-bit ALU and 8-bit shifter

•Multiplication/division instructions and MAC (multiplication and accumulation) instruction are available

•20 ns of minimum inst ru ction execution time at 50 MHz operation

8K bytes None CMOS/LV TT L

A-1

Internal memory

RAM: 8K bytes

Internal peripheral circuits

Oscillation circuit: High-speed (OSC3) oscillation circuit 33 MHz max.

Crystal/ceramic oscillator or external clock input

Low-speed (OSC1) oscillation cir cuit 32.768 kHz typ.

Crystal oscillator or external clock input

LCD controller: 4 or 8-bit monoch rome/col or LCD int erface (based on the S1D13705)

2, 4 or 16-level (1, 2 or 4 bit- per-pixel) gray-scale display 2, 4, 16 or 256-level (1, 2, 4 or 8 bit- per-pixel) color display Resolution examples : 640 × 480 pixels with 1-bpp color depth

640 × 240 pixels with 2-bpp color depth 320 × 240 pixels with 4-bpp color depth 240 × 160 pixels with 8-bpp color depth

Timers: 8-bit timer 6 channels

16-bit timer 6 channels Watchdog timer (16-b it timer 0's function) Clock timer 1 channel (with alarm function)

Serial interface: 4 channels (clock-synchronous system, asynchronous system and IrDA

interface are selectable)

A/D converter: 10 bit s × 8 channels DMA controller: High-speed DMA 4 channels

Intelligent DMA 128 channels

S1C33L03 PRODUCT PART EPSON A-1

1 OUTLINE

Interrupt controller: Possible to invoke DMA

Input interrupt 10 types (programmable) DMA controller interrupt 5 types 16-bit programmable timer interrupt 12 types 8-bit programmable timer interrupt 4 types Serial interface inte rru pt 6 types A/D converter interrupt 1 type

Clock timer interrupt 1 type General-purpose input Shared with the I/O pins for internal peripheral circuits and outp ut port s: Input port 13 bits

I/O port 29 bits

External bus interface

BCU (bus control unit) built-in

•24-bit address bus (internal 28-bit processing)

•16-bit data bus Data size is selectable from 8 bits and 16 bits in each area.

•Little-endian memory access; big-endian may be set in each area.

•Memory ma pped I/O

•Chip enable and wait control circuits built-in

•DRAM direct interface fu nc tio n b uil t-i n Supports fast page mode and EDO page mode. Suppor ts self-refresh and CAS-before RAS refresh.

•Supports SDRAM. Supports SDRAM self-refr esh.

•Supports burst ROM.

Operating conditions and power consumption

Operating voltage: Core (VDD)1.8 V to 3.6 V

I/O (V

DDE)1.8 V to 5.5 V

Operating clock frequency: CPU operating clock frequency

50 MHz max. (core voltage = 3.3 V ±0.3 V)

LCD controller operating clock frequency

25 MHz max. (core voltage = 3.3 V ±0.3 V) * When the SDRAM controller is used (core voltage = 3.3 V ±0.3 V and PLL is used),

In x1 speed mode: CPU = Bus = 25 MHz max.

In x2 speed mode: CPU = 35 MHz max., Bus = 17.5 MHz max.

Operating temper at ure : -40 to 85°C Power con sumption: During SLEEP 3.5 µW typ. (3.3 V)

During HALT 100 mW typ. (3.3 V, 50 MHz) During execution 200 mW typ. (3.3 V, 50 MHz)

Note: The values of pow er consumption during exe cution were measured when a test

program that consisted of 55% load instructions, 23% arithmetic operation instructions, 1% mac instruction, 12% branch instructions and 9% ext instructio n w as bein g co nt inuously exec uted.

Supply form

QFP20-144pin plastic package, or chip.

A-2 EPSON S1C33L03 PRODUCT PART

1.2 Block Diagram

DDE

A[23:0] D[15:0]

#WRL/#WR/#WE

#HCAS, #LCAS, #RAS[1:0]

#CE10EX, #CE[9:3]

#DRD(P20), #DWE/#SDWE(P21)

#GAAS(P21), #GARD(P31)

SDA10, SDCKE, HDQM, LDQM

#DMAREQx(K50, K51, K53, K54)

#DMAACKx(P32, P33, P04, P06) #DMAENDx(P15, P16, P05, P07)

#SDCAS, #SDRAS

#RD

#WRH/#BSH

#EMEMRD

#WAIT(P30)

#SDCE[1:0]

OSC3 OSC4

PLLS[1:0]

PLLC

OSC1 OSC2

FOSC1(P14)

P00–07 P10–16 P20–27 P30–35

OSC3/PLL

Prescaler

OSC1

Clock Timer

Intelligent

DMA (128 ch.)

High-speed

DMA (4 ch.)

RAM

8KB

I/O Port

S1C33L03

S1C33000

CPU Core

Bus Control Unit

SDRAM Controller

Interrupt

Controller

16-bit

Programmable

Timer (6 ch.)

8-bit

Programmable

Timer (6 ch.)

Serial Interface

(4 ch.)

A/D Converter

(8 ch.)

LCD Controller

Input Port

1 OUTLINE

#RESET #NMI #X2SPD ICEMD DSIO EA10MD[1:0] BCLK #BUSREQ(P34) #BUSACK(P35) #BUSGET(P31) DST[2:0](P10–12) DPCO(P13) DCLK(P14)

EXCLx(P10–13, P15, P16) TMx(P22–27)

T8UFx(P10–13)

SINx(P00, P04, P27, P33) SOUTx(P01, P05, P26, P16) #SCLKx(P02, P06, P25, P15) #SRDYx(P03, P07, P24, P32)

AD0–7(K60–67) #ADTRG(K52)

DDE

FPDAT[7:4] FPDAT[3:0]/GPO[6:3] FPFRAME FPLINE FPSHIFT DRDY(MOD/FPSHIFT2) LCDPWR

K50–54 K60–67

A-1

Figure 1.2.1 S1C33L03 Block Diagram

S1C33L03 PRODUCT PART EPSON A-3

1 OUTLINE

1.3 Pin Description

1.3.1 Pin Layout Diagram (plastic package)

QFP20-144pin

73108

No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Pin name

P22/TM0 P23/TM1

V P24/TM2/#SRDY2 P25/TM3/#SCLK2 P26/TM4/SOUT2 P27/TM5/SIN2

V P07/#SRDY1/#DMAEND3 P06/#SCLK1/#DMAACK3 P05/SOUT1/#DMAEND2 P04/SIN1/#DMAACK2 FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3/GPO6 FPDAT2/GPO5 FPDAT1/GPO4 FPDAT0/GPO3

DDE

V DRDY(MOD/FPSHIFT2) FPFRAME FPLINE FPSHIFT LCDPWR

V K67/AD7 K66/AD6 K65/AD5 K64/AD4 K63/AD3 K62/AD2 K61/AD1 K60/AD0

DDE

109

144

No.

K54/#DMAREQ3

K53/#DMAREQ2

K52/#ADTRG

K51/#DMAREQ1

K50/#DMAREQ0

#WRH/#BSH

#WRL/#WR/#WE

#RD

V D15

D14

D13

D12

D11

D10

DDE

#CE8/#RAS1/#CE14/#RAS3/#SDCE1

#CE7/#RAS0/#CE13/#RAS2/#SDCE0

OSC2

OSC1

#RESET

P35/#BUSACK/GPIO1

P34/#BUSREQ/#CE6/GPIO0

P33/#DMAACK1/SIN3/SDA10

Pin name

Figure 1.3.1 Pin Layout Diagram (QFP20-144pin)

INDEX

361

No.

P32/#DMAACK0/#SRDY3/HDQM

P31/#BUSGET/#GARD/GPIO2

P30/#WAIT/#CE4&5

#LCAS/#SDRAS

#HCAS/#SDCAS

V P21/#DWE/#GAAS/#SDWE

P20/#DRD/SDCKE

BCLK/SDCLK

P16/EXCL5/#DMAEND1/SOUT3

P15/EXCL4/#DMAEND0/#SCLK3/LDQM

A0/#BSL

A1/SDA0

A2/SDA1

A3/SDA2

A4/SDA3

A5/SDA4

DDE

A6/SDA5

A7/SDA6

A8/SDA7

A9/SDA8

A10/SDA9

A11

A12/SDA11

A13/SDA12

100

A14/SDBA0

101

A15/SDBA1

102

A16

103

A17

104

105

A18

106

A19

107

A20

108

Pin name

No.

109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144

Pin name

A21 A22 A23 PLLS1 PLLS0

V PLLC

V DSIO P14/FOSC1/DCLK P13/EXCL3/T8UF3/DPCO P12/EXCL2/T8UF2/DST2 P11/EXCL1/T8UF1/DST1 P10/EXCL0/T8UF0/DST0 EA10MD1 EA10MD0 ICEMD #EMEMRD

V OSC4 OSC3 #NMI #CE9/#CE17/#CE17&18

DDE

V #CE5/#CE15/#CE15&16 N.C. #CE3

V #CE10EX/#CE9&10EX #CE6/#CE7&8 #CE4/#CE11/#CE11&12 #X2SPD P03/#SRDY0 P02/#SCLK0 P01/SOUT0 P00/SIN0

A-4 EPSON S1C33L03 PRODUCT PART

1.3.2 Pin Functions

Table 1.3.1 List of Pins for Power Supply System

Pin name Pin No. I/O Pull-up Function

VDD 8,51,78,127 – – Power supply (+) for the internal logic VSS 3,27,45,66,

82,98,105,

114,116,136 VDDE 21,59,91,132 – – Power supply (+) for the I/O block AVDDE 36 – – Analog system power supply (+); AVDDE = VDDE

Pin name Pin No. I/O Pull-up Function

A0 #BSL A[10:1] SDA[9:0] A11 97 O – Address bus (A11) A[13:12] SDA[12:11] A[15:14] SDBA[1:0] A[23:16] 103,104,

D[15:0] 46–50,52–58,

#CE10EX #CE9&10EX #CE9 #CE17 #CE17&18 #CE8 #RAS1 #CE14 #RAS3 #SDCE1

#CE7 #RAS0 #CE13 #RAS2 #SDCE0

#CE6 #CE7&8 #CE5 #CE15 #CE15&16 #CE4 #CE11 #CE11&12 #CE3 135 O – Area 3 chip enable #RD 44 O – Read signal #EMEMRD 126 O – Read signal for internal ROM emulation memory

85 O – A0: Address bus (A0) when SBUSST(D3/0x4812E) = "0" (default)

85–90,92–96 O

99,100 O – A[13:12]: A ddress bus (A12–A13)

101,102 O – A[15:14]: Address bus (A14–A15)

106–111

60–63

137 O – Area 10 chip enable for external memory

131 O – #CE9: Area 9 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default)

64 O – #CE8: Area 8 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00",

65 O – #CE7: Area 7 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00",

138 O – Area 6 chip enable

133 O – #CE5: Area 5 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default)

139 O – #CE4: Area 4 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default)

––Power supply (-); GND

Table 1.3.2 List of Pins for External Bus Interface Signals

#BSL: Bus strobe (low byte) signal when SBUSST(D3/0x4812E) = "1" A[10:1]: Address bus (A1–A10)

–

SDA[9:0]: SDRAM address bus (SDA0–SDA9)

SDA[12:11]: SDRAM address bus (SDA11–SDA12)

O–Address bus (A16–A23)

I/O – Data bus (D0–D15)

SDBA[1:0]: SDRAM bank select (SDBA0–SDBA1)

* When CEFUNC[1:0] = "1x", this pin outputs #CE9+#CE10EX signal.

#CE17: Area 17 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" * When CEFUNC[1:0] = "1x", this pin outputs #CE17+#CE18 signal.

A8DRA(D8/0x48128) = "0" and SDRPC1(D2/0x39FFC0) = "0" (default)

#RAS1: Area 8 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "00",

A8DRA(D8/0x48128) = "1" and SDRPC1(D2/0x39FFC0) = "0"

#CE14: Area 14 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" or "1x",

A14DRA(D8/0x48122) = "0" and SDRPC1(D2/0x39FFC0) = "0"

#RAS3: Area 14 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "01" or

"1x", A14DRA(D8/0x48122) = "1" and SDRPC1(D2/0x39FFC0) = "0"

#SDCE1: SDRAM chip enable 1 when SDRPC1(D2/0x39FFC0) = "1" and

SDRENA(D7/0x39FFC1) = "1"

A7DRA(D7/0x48128) = "0" and SDRPC0(D3/0x39FFC0) = "0" (default)

#RAS0: Area 7 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "00",

A7DRA(D7/0x48128) = "1" and SDRPC0(D3/0x39FFC0) = "0"

#CE13: Area 13 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" or "1x",

A13DRA(D7/0x48122) = "0" and SDRPC0(D3/0x39FFC0) = "0"

#RAS2: Area 13 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "01" or

"1x", A13DRA(D7/0x48122) = "1" and SDRPC0(D3/0x39FFC0) = "0"

#SDCE0: SDRAM chip enable 0 when SDRPC0(D3/0x39FFC0) = "1" and

SDRENA(D7/0x39FFC1) = "1"

* When CEFUNC[1:0] = "1x", this pin outputs #CE7+#CE8 signal.

#CE15: Area 15 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" * When CEFUNC[1:0] = "1x", this pin outputs #CE15+#CE16 signal.

#CE11: Area 11 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" * When CEFUNC[1:0] = "1x", this pin outputs #CE11+#CE12 signal.

1 OUTLINE

A-1

S1C33L03 PRODUCT PART EPSON A-5

1 OUTLINE

Pin name Pin No. I/O Pull-up Function

#WRL #WR #WE #WRH #BSH #HCAS #SDCAS

#LCAS #SDRAS

BCLK SDCLK P34 #BUSREQ #CE6 GPIO0

P35 #BUSACK GPIO1

P30 #WAIT #CE4&5

P20 #DRD SDCKE

P21 #DWE #GAAS #SDWE

P31 #BUSGET #GARD GPIO2

EA10MD1 123 I Pull-up Area 10 boot mode selection

EA10MD0 124 I – 1 1 External ROM mode

43 O – #WRL: Write (low byte) signal when SBUSST(D3/0x4812E) = "0" (default)

#WR: Write signal when SBUSST(D3/0x4812E) = "1" #WE: DRAM write signal

42 O – #WRH: Write (high byte) signal when SBUSST(D3/0x4812E) = "0" (default)

#BSH: Bus strobe (high byte) signal when SBUSST(D3/0x4812E) = "1"

77 O – #HCAS: DRAM column address strobe (high byte) signal when

SDRENA(D7/0x39FFC1) = "0" (default)

#SDCAS: SDRAM column address strobe when SDRENA(D7/0x39FFC1) = "1"

76 O – #LCAS: DRAM column address strobe (low byte) signal when

SDRENA(D7/0x39FFC1) = "0" (default)

#SDRAS: SDRAM row address strobe when SDRENA(D7/0x39FFC1) = "1"

81 O – BCLK: Bus clock output when SDRENA(D7/0x39FFC1) = "0" (default)

SDCLK: SDRAM clock output when SDRENA(D7/0x39FFC1) = "1"

71 I/O – P34: I/O port when CFP34(D4/0x402DC) = "0" (default)

#BUSREQ: Bus release request input when CFP34(D4/0x402DC) = "1" #CE6: Area 6 chip enable when CFP34(D4/0x402DC) = "1" and

IOC34(D4/0x402DE) = "1"

GPIO0: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and

BREQEN(D2/0x39FFFD) = "0"

70 I/O – P35: I/O port when CFP35(D5/0x402DC) = "0" (default)

#BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1" and

CFP34(D4/0x402DC) = "1"

GPIO1: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and

BREQEN(D2/0x39FFFD) = "0"

75 I/O – P30: I/O port when CFP30(D0/0x402DC) = "0" (default)

#WAIT: Wait cycle request input when CFP30(D0/0x402DC) = "1" #CE4&5: Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1" and

IOC30(D0/0x402DE) = "1"

80 I/O – P20: I/O port when CFP20(D0/0x402D8) = "0" and SDRENA(D7/0x39FFC1) =

"0" (default)

#DRD: DRAM read signal output for successive RAS mode when

CFP20(D0/0x402D8) = "1" and SDRENA(D7/0x39FFC1) = "0"

SDCKE: SDRAM clock enable signal when SDRENA(D7/0x39FFC1) = "1"

79 I/O – P21: I/O port when CFP21(D1/0x402D8) = "0", CFEX2(D2/0x402DF) = "0" and

SDRENA(D7/0x39FFC1) = "0" (default)

#DWE: DRAM write signal output for successive RAS mode when

CFP21(D1/0x402D8) = "1", CFEX2(D2/0x402DF) = "0" and SDRENA(D7/0x39FFC1) = "0"

#GAAS: Area address strobe output for GA when CFEX2(D2/0x402DF) = "1" and

SDRENA(D7/0x39FFC1) = "0"

#SDWE: SDRAM write signal when SDRENA(D7/0x39FFC1) = "1"

74 I/O – P31: I/O port when CFP31(D1/0x402DC) = "0" and CFEX3(D3/0x402DF) = "0"

(default)

#BUSGET: Bus status monitor signal output for bus release request when

CFP31(D1/0x402DC) = "1" and CFEX3(D3/0x402DF) = "0" #GARD: Area read signal output for GA when CFEX3(D3/0x402DF) = "1" GPIO2: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and

BREQEN(D2/0x39FFFD) = "0"

EA10MD1 EA10MD0 Mode

10Internal ROM mode

A-6 EPSON S1C33L03 PRODUCT PART

1 OUTLINE

Table 1.3.3 List of Pins for HSDMA Control Signals

Pin name Pin No. I/O P ull-up Function

K50 #DMAREQ0 K51 #DMAREQ1 K53 #DMAREQ2 K54 #DMAREQ3 P32 #DMAACK0 #SRDY3 HDQM

P33 #DMAACK1 SIN3 SDA10

P04 SIN1 #DMAACK2

P06 #SCLK1 #DMAACK3

P15 EXCL4 #DMAEND0 #SCLK3 LDQM

P16 EXCL5 #DMAEND1 SOUT3

P05 SOUT1 #DMAEND2

P07 #SRDY1 #DMAEND3

41 I Pull-up K50: Input port when CFK50(D0/0x402C0) = "0" (default)

#DMAREQ0: HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1"

40 I Pull-up K51: Input port when CFK51(D1/0x402C0) = "0" (default)

#DMAREQ1: HSDMA Ch. 1 request input when CFK51(D1/0x402C0) = "1"

38 I Pull-up K53: Input port when CFK53(D3/0x402C0) = "0" (default)

#DMAREQ2: HSDMA Ch. 2 request input when CFK53(D3/0x402C0) = "1"

37 I Pull-up K54: Input port when CFK54(D4/0x402C0) = "0" (default)

#DMAREQ3: HSDMA Ch. 3 request input when CFK54(D4/0x402C0) = "1"

73 I/O – P32: I/O port when CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"

(default)

#DMAACK0: HSDMA Ch. 0 acknowledge output when CFP32(D2/0x402DC) = "1" and

SDRENA(D7/0x39FFC1) = "0"

#SRDY3: Serial I/F Ch. 3 ready signal input/output when SSRDY3(D3/0x402D7) =

"1", CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"

HDQM: SDRAM data (high byte) input/output mask signal when

SDRENA(D7/0x39FFC1) = "1"

72 I/O – P33: I/O port when CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"

(default)

#DMAACK1: HSDMA Ch. 1 acknowledge output when CFP33(D3/0x402DC) = "1" and

SDRENA(D7/0x39FFC1) = "0"

SIN3:Serial I/F Ch. 3 data input when SSIN3(D0/0x402D7) = "1",

CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"

SDA10: SDRAM address bus bit 10 when SDRENA(D7/0x39FFC1) = "1"

12 I/O – P04: I/O port when CFP04(D4/0x402D0) = "0" and CFEX4(D4/0x402DF) = "0"

(default)

SIN1:Serial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1" and

CFEX4(D4/0x402DF) = "0"

#DMAACK2: HSDMA Ch. 2 acknowledge output when CFEX4(D4/0x402DF) = "1"

10 I/O – P06: I/O port when CFP06(D6/0x402D0) = "0" and CFEX6(D6/0x402DF) = "0"

(default)

#SCLK1: Serial I/F Ch. 1 clock input/output when CFP06(D6/0x402D0) = "1" and

CFEX6(D6/0x402DF) = "0"

#DMAACK3: HSDMA Ch. 3 acknowledge output when CFEX6(D6/0x402DF) = "1"

84 I/O – P15: I/O port when CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0"

(default)

EXCL4: 16-bit timer 4 event counter input when CFP15(D5/0x402D4) = "1",

IOC15(D5/0x402D6) = "0" and SDRENA(D7/0x39FFC1) = "0"

#DMAEND0: HSDMA Ch. 0 end-of-transfer signal output when CFP15(D5/0x402D4) =

"1", IOC15(D5/0x402D6) = "1" and SDRENA(D7/0x39FFC1) = "0"

#SCLK3: Serial I/F Ch. 3 clock input/output when SSCLK3(D2/0x402D7) = "1",

CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0"

LDQM: SDRAM data (low byte) input/output mask signal when

SDRENA(D7/0x39FFC1) = "1"

83 I/O – P16: I/O port when CFP16(D6/0x402D4) = "0" (default)

EXCL5: 16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1" and

IOC16(D6/0x402D6) = "0"

#DMAEND1: HSDMA Ch. 1 end-of-transfer signal output when CFP16(D6/0x402D4) = "1"

and IOC16(D6/0x402D6) = "1"

SOUT3: Serial I/F Ch. 3 data output when SSOUT3(D1/0x402D7) = "1" and

CFP16(D6/0x402D4) = "0"

11 I/O – P05: I/O port when CFP05(D5/0x402D0) = "0" and CFEX5(D5/0x402DF) = "0"

(default)

SOUT1: Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1" and

CFEX5(D5/0x402DF) = "0"

#DMAEND2: HSDMA Ch. 2 end-of-transfer signal output when CFEX5(D5/0x402DF) = "1"

9 I/O – P07: I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0"

(default)

#SRDY1: Serial I/F Ch. 1 ready signal output when CFP07(D7/0x402D0) = "1" and

CFEX5(D5/0x402DF) = "0"

#DMAEND3: HSDMA Ch. 3 end-of-transfer signal output when CFEX7(D7/0x402DF) = "1"

A-1

S1C33L03 PRODUCT PART EPSON A-7

1 OUTLINE

Table 1.3.4 List of Pins for Internal Peripheral Circuits

Pin name Pin No. I/O Pull-up Function

K50 #DMAREQ0 K51 #DMAREQ1 K52 #ADTRG K53 #DMAREQ2 K54 #DMAREQ3 K60 AD0 K61 AD1

K62 AD2 K63 AD3 K64 AD4 K65 AD5 K66 AD6 K67 AD7 P00 SIN0 P01 SOUT0 P02 #SCLK0 P03 #SRDY0 P04 SIN1 #DMAACK2

P05 SOUT1 #DMAEND2

P06 #SCLK1 #DMAACK3

P07 #SRDY1 #DMAEND3

P10 EXCL0 T8UF0 DST0

41 I Pull-up K50: Input port when CFK50(D0/0x402C0) = "0" (default)

#DMAREQ0: HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1"

40 I Pull-up K51: Input port when CFK51(D1/0x402C0) = "0" (default)

#DMAREQ1: HSDMA Ch. 1 request input when CFK51(D1/0x402C0) = "1"

39 I Pull-up K52: Input port when CFK52(D2/0x402C0) = "0" (default)

#ADTRG: A/D converter trigger input when CFK52(D2/0x402C0) = "1"

38 I Pull-up K53: Input port when CFK53(D3/0x402C0) = "0" (default)

#DMAREQ2: HSDMA Ch. 2 request input when CFK53(D3/0x402C0) = "1"

37 I Pull-up K54: Input port when CFK54(D4/0x402C0) = "0" (default)

#DMAREQ3: HSDMA Ch. 3 request input when CFK54(D4/0x402C0) = "1"

35 I – K60: Input port when CFK60(D0/0x402C3) = "0" (default)

AD0: A/D converter Ch. 0 input when CFK60(D0/0x402C3) = "1"

34 I – K61: Input port when CFK61(D1/0x402C3) = "0" (default)

AD1: A/D converter Ch. 1 input when CFK61(D1/0x402C3) = "1"

33 I – K62: Input port when CFK62(D2/0x402C3) = "0" (default)

AD2: A/D converter Ch. 2 input when CFK62(D2/0x402C3) = "1"

32 I – K63: Input port when CFK63(D3/0x402C3) = "0" (default)

AD3: A/D converter Ch. 3 input when CFK63(D3/0x402C3) = "1"

31 I – K64: Input port when CFK64(D4/0x402C3) = "0" (default)

AD4: A/D converter Ch. 4 input when CFK64(D4/0x402C3) = "1"

30 I – K65: Input port when CFK65(D5/0x402C3) = "0" (default)

AD5: A/D converter Ch. 5 input when CFK65(D5/0x402C3) = "1"

29 I – K66: Input port when CFK66(D6/0x402C3) = "0" (default)

AD6: A/D converter Ch. 6 input when CFK66(D6/0x402C3) = "1"

28 I – K67: Input port when CFK67(D7/0x402C3) = "0" (default)

AD7: A/D converter Ch. 7 input when CFK67(D7/0x402C3) = "1"

144 I/O – P00: I/O port when CFP00(D0/0x402D0) = "0" (default)

SIN0:Serial I/F Ch. 0 data input when CFP00(D0/0x402D0) = "1"

143 I/O – P01: I/O port when CFP01(D1/0x402D0) = "0" (default)

SOUT0: Serial I/F Ch. 0 data output when CFP01(D1/0x402D0) = "1"

142 I/O – P02: I/O port when CFP02(D2/0x402D0) = "0" (default)

#SCLK0: Serial I/F Ch. 0 clock input/output when CFP02(D2/0x402D0) = "1"

141 I/O – P03: I/O port when CFP03(D3/0x402D0) = "0" (default)

#SRDY0: Serial I/F Ch. 0 ready signal input/output when CFP03(D3/0x402D0) = "1"

12 I/O – P04: I/O port when CFP04(D4/0x402D0) = "0" and CFEX4(D4/0x402DF) = "0"

(default)

SIN1:Serial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1" and

CFEX4(D4/0x402DF) = "0"

#DMAACK2: HSDMA Ch. 2 acknowledge output when CFEX4(D4/0x402DF) = "1"

11 I/O – P05: I/O port when CFP05(D5/0x402D0) = "0" and CFEX5(D5/0x402DF) = "0"

(default)

SOUT1: Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1" and

CFEX5(D5/0x402DF) = "0"

#DMAEND2: HSDMA Ch. 2 end-of-transfer signal output when

CFEX5(D5/0x402DF) = "1"

10 I/O – P06: I/O port when CFP06(D6/0x402D0) = "0" and CFEX6(D6/0x402DF) = "0"

(default)

#SCLK1: Serial I/F Ch. 1 clock input/output when CFP06(D6/0x402D0) = "1" and

CFEX6(D6/0x402DF) = "0"

#DMAACK3: HSDMA Ch. 3 acknowledge output when CFEX6(D6/0x402DF) = "1"

9 I/O – P07: I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0"

(default)

#SRDY1: Serial I/F Ch. 1 ready signal output when CFP07(D7/0x402D0) = "1" and

CFEX5(D5/0x402DF) = "0"

#DMAEND3: HSDMA Ch. 3 end-of-transfer signal output when

CFEX7(D7/0x402DF) = "1"

122 I/O – P10: I/O port when CFP10(D0/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0"

EXCL0: 16-bit timer 0 event counter input when CFP10(D0/0x402D4) = "1",

IOC10(D0/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"

T8UF0: 8-bit timer 0 output when CFP10(D0/0x402D4) = "1", IOC10(D0/0x402D6)

= "1" and CFEX1(D1/0x402DF) = "0"

DST0:DST0 signal output when CFEX1(D1/0x402DF) = "1" (default)

A-8 EPSON S1C33L03 PRODUCT PART

1 OUTLINE

Pin name Pin No. I/O Pull-up Function

P11 EXCL1 T8UF1 DST1

P12 EXCL2 T8UF2 DST2

P13 EXCL3 T8UF3 DPCO

P14 FOSC1 DCLK

P15 EXCL4 #DMAEND0 #SCLK3 LDQM

P16 EXCL5 #DMAEND1 SOUT3

P20 #DRD SDCKE

P21 #DWE #GAAS #SDWE

P22 TM0 P23 TM1 P24 TM2 #SRDY2

P25 TM3 #SCLK2

121 I/O – P11: I/O port when CFP11(D1/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0"

EXCL1: 16-bit timer 1 event counter input when CFP11(D1/0x402D4) = "1",

IOC11(D1/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"

T8UF1: 8-bit timer 1 output when CFP11(D1/0x402D4) = "1", IOC11(D1/0x402D6)

= "1" and CFEX1(D1/0x402DF) = "0"

DST1:DST1 signal output when CFEX1(D1/0x402DF) = "1" (default)

120 I/O – P12: I/O port when CFP12(D2/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0"

EXCL2: 16-bit timer 2 event counter input when CFP12(D2/0x402D4) = "1",

IOC12(D2/0x402D6) = "0" and CFEX0(D0/0x402DF) = "0"

T8UF2: 8-bit timer 2 output when CFP12(D2/0x402D4) = "1", IOC12(D2/0x402D6)

= "1" and CFEX0(D0/0x402DF) = "0"

DST2:DST2 signal output when CFEX0(D0/0x402DF) = "1" (default)

119 I/O – P13: I/O port when CFP13(D3/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0"

EXCL3: 16-bit timer 3 event counter input when CFP13(D3/0x402D4) = "1",

IOC13(D3/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"

T8UF3: 8-bit timer 3 output when CFP13(D3/0x402D4) = "1", IOC13(D3/0x402D6)

= "1" and CFEX1(D1/0x402DF) = "0"

DPCO:DPCO signal output when CFEX1(D1/0x402DF) = "1" (default)

118 I/O – P14: I/O port when CFP14(D4/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0"

FOSC1: OSC1 clock output when CFP14(D4/0x402D4) = "1" and

CFEX0(D0/0x402DF) = "0"

DCLK: DCLK signal output when CFEX0(D0/0x402DF) = "1" (default)

84 I/O – P15: I/O port when CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1)

= "0" (default)

EXCL4: 16-bit timer 4 event counter input when CFP15(D5/0x402D4) = "1",

IOC15(D5/0x402D6) = "0" and SDRENA(D7/0x39FFC1) = "0"

#DMAEND0: HSDMA Ch. 0 end-of-transfer signal output when CFP15(D5/0x402D4)

= "1", IOC15(D5/0x402D6) = "1" and SDRENA(D7/0x39FFC1) = "0"

#SCLK3: Serial I/F Ch. 3 clock input/output when SSCLK3(D2/0x402D7) = "1",

CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0"

LDQM: SDRAM data (low byte) input/output mask signal when

SDRENA(D7/0x39FFC1) = "1"

83 I/O – P16: I/O port when CFP16(D6/0x402D4) = "0" (default)

EXCL5: 16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1" and

IOC16(D6/0x402D6) = "0"

#DMAEND1: HSDMA Ch. 1 end-of-transfer signal output when CFP16(D6/0x402D4) =

"1" and IOC16(D6/0x402D6) = "1"

SOUT3: Serial I/F Ch. 3 data output when SSOUT3(D1/0x402D7) = "1" and

CFP16(D6/0x402D4) = "0"

80 I/O – P20: I/O port when CFP20(D0/0x402D8) = "0" and SDRENA(D7/0x39FFC1)

= "0" (default)

#DRD: DRAM read signal output for successive RAS mode when

CFP20(D0/0x402D8) = "1" and SDRENA(D7/0x39FFC1) = "0"

SDCKE: SDRAM clock enable signal when SDRENA(D7/0x39FFC1) = "1"

79 I/O – P21: I/O port when CFP21(D1/0x402D8) = "0", CFEX2(D2/0x402DF) = "0" and

SDRENA(D7/0x39FFC1) = "0" (default)

#DWE: DRAM write signal output for successive RAS mode when

CFP21(D1/0x402D8) = "1", CFEX2(D2/0x402DF) = "0" and SDRENA(D7/0x39FFC1) = "0"

#GAAS: Area address strobe output for GA when CFEX2(D2/0x402DF) = "1" and

SDRENA(D7/0x39FFC1) = "0"

#SDWE: SDRAM write signal when SDRENA(D7/0x39FFC1) = "1"

1 I/O – P22: I/O port when CFP22(D2/0x402D8) = "0" (default)

TM0: 16-bit timer 0 output when CFP22(D2/0x402D8) = "1"

2 I/O – P23: I/O port when CFP23(D3/0x402D8) = "0" (default)

TM1: 16-bit timer 1 output when CFP23(D3/0x402D8) = "1"

4 I/O – P24: I/O port when CFP24(D4/0x402D8) = "0" (default)

TM2: 16-bit timer 2 output when CFP24(D4/0x402D8) = "1" #SRDY2: Serial I/F Ch. 2 ready signal input/output when SSRDY2(D3/0x402DB) = "1"

and CFP24(D4/0x402D8) = "0"

5 I/O – P25: I/O port when CFP25(D5/0x402D8) = "0" (default)

TM3: 16-bit timer 3 output when CFP25(D5/0x402D8) = "1" #SCLK2: Serial I/F Ch. 2 clock input/output when SSCLK2(D2/0x402DB) = "1" and

CFP25(D5/0x402D8) = "0"

A-1

S1C33L03 PRODUCT PART EPSON A-9

1 OUTLINE

Pin name Pin No. I/O Pull-up Function

P26 TM4 SOUT2

P27 TM5 SIN2

P30 #WAIT #CE4&5

P31 #BUSGET #GARD GPIO2

P32 #DMAACK0 #SRDY3 HDQM

P33 #DMAACK1 SIN3 SDA10

P34 #BUSREQ #CE6 GPIO0

P35 #BUSACK GPIO1

6 I/O – P26: I/O port when CFP26(D6/0x402D8) = "0" (default)

TM4: 16-bit timer 4 output when CFP26(D6/0x402D8) = "1" SOUT2: Serial I/F Ch. 2 data output when SSOUT2(D1/0x402DB) = "1" and

CFP26(D6/0x402D8) = "0"

7 I/O – P27: I/O port when CFP27(D7/0x402D8) = "0" (default)

TM5: 16-bit timer 5 output when CFP27(D7/0x402D8) = "1" SIN2:Serial I/F Ch. 2 data input when SSIN2(D0/0x402DB) = "1" and

CFP27(D7/0x402D8) = "0"

75 I/O – P30: I/O port when CFP30(D0/0x402DC) = "0" (default)

#WAIT: Wait cycle request input when CFP30(D0/0x402DC) = "1" #CE4&5: Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1" and

IOC30(D0/0x402DE) = "1"

74 I/O – P31: I/O port when CFP31(D1/0x402DC) = "0" and CFEX3(D3/0x402DF) = "0"

(default)

#BUSGET: Bus status monitor signal output for bus release request when

CFP31(D1/0x402DC) = "1" and CFEX3(D3/0x402DF) = "0" #GARD: Area read signal output for GA when CFEX3(D3/0x402DF) = "1" GPIO2: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and

BREQEN(D2/0x39FFFD) = "0"

73 I/O – P32: I/O port when CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1)

= "0" (default) #DMAACK0: HSDMA Ch. 0 acknowledge output when CFP32(D2/0x402DC) = "1" and

SDRENA(D7/0x39FFC1) = "0" #SRDY3: Serial I/F Ch. 3 ready signal input/output when SSRDY3(D3/0x402D7) =

"1", CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" HDQM: SDRAM data (high byte) input/output mask signal when

SDRENA(D7/0x39FFC1) = "1"

72 I/O – P33: I/O port when CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1)

= "0" (default) #DMAACK1: HSDMA Ch. 1 acknowledge output when CFP33(D3/0x402DC) = "1" and

SDRENA(D7/0x39FFC1) = "0" SIN3:Serial I/F Ch. 3 data input when SSIN3(D0/0x402D7) = "1",

CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" SDA10: SDRAM address bus bit 10 when SDRENA(D7/0x39FFC1) = "1"

71 I/O – P34: I/O port when CFP34(D4/0x402DC) = "0" (default)

#BUSREQ: Bus release request input when CFP34(D4/0x402DC) = "1" #CE6: Area 6 chip enable when CFP34(D4/0x402DC) = "1" and

IOC34(D4/0x402DE) = "1" GPIO0: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and

BREQEN(D2/0x39FFFD) = "0"

70 I/O – P35: I/O port when CFP35(D5/0x402DC) = "0" (default)

#BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1" and

CFP34(D4/0x402DC) = "1" GPIO1: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and

BREQEN(D2/0x39FFFD) = "0"

A-10 EPSON S1C33L03 PRODUCT PART

1 OUTLINE

Table 1.3.5 List of Pins for LCD Controller

Pin name Pin No. I/O Pull-up Function

FPDAT[7:4] 13–16 O – 4 high-order bits of data bus for 8-bit LCD panels

Data bus for 4-bit LCD panels FPDAT[3:0] GPO[6:3] FPFRAME 23 O – Frame pulse output FPLINE 24 O – Line pulse output FPSHIFT 25 O – Shift clock output DRDY(MOD) (FPSHIFT2) LCDPWR 26 O – LCD power control output (active high)

17–20 O – FPDAT[3:0]: 4 low-order bits of data bus for 8-bit LCD panels

GPO[6:3]: General-purpose outputs when a 4-bit LCD panel is used

22 O – MOD: LCD backplane bias (for panels other than 8-bit color panel format 1)

FPSHIFT2: Second shift clock (for 8-bit color panel format 1)

Table 1.3.6 List of Pins for Clock Generator

Pin name Pin No. I/O Pull-up Function

OSC1 68 I – Low-speed (OSC1) oscillation input (32 kHz crystal oscillator or external clock input) OSC2 67 O – Low-speed (OSC1) oscillation output OSC3 129 I – High-speed (OSC3) oscillation input (crystal/ceramic oscillator or external clock input) OSC4 128 O – High-speed (OSC3) oscillation output PLLS[1:0] 112,113 I – PLL set-up pins

PLLS1 PLLS0 fin (fOSC3)fout (fPSCIN)

1110–25MHz 20–50MHz 0110–12.5MHz 40–50MHz 00PLL is not used L

PLLC 115 – – Capacitor connecting pin for PLL

Table 1.3.7 List of Other Pins

Pin name Pin No. I/O

ICEMD 125 I Pull-

DSIO 117 I/O Pull-up Serial I/O pin for debugging

#X2SPD 140 I – Clock doubling mode set-up pin

#NMI 130 I Pull-up NMI request input pin #RESET 69 I Pull-up Initial reset input pin

Pull-up

/down

High-impedance control input pin

down

When this pin is set to High, all the output pins go into high-impedance state. This makes

it possible to disable the S1C33 chip on the board.

This pin is used to communicate with the debugging tool S5U1C33000H.

1: CPU clock = bus clock × 1, 0: CPU clock = bus clock × 2

Function

A-1

Note: "#" in the pin names indicates that the signal is low active.

S1C33L03 PRODUCT PART EPSON A-11

2 POWER SUPPLY

2 Power Supply

This chapter explains the operating voltage of the S1C33L03.

2.1 Power Supply Pins

The S1C3 3L03 has the power supply pins s hown in Tabl e 2.1.1.

Table 2.1.1 Power Supply Pins

Pin name Pin No. Function

VDD 8,51,78,127 Power supply (+) for the internal logic VSS 3,27,45,66,82,98,105,114,116,136Power supply (-); GND VDDE 21,59,91,132 Power supply (+) for the I/O block AVDDE 36 A na log sys tem power supply (+); AV DDE = VDDE

CPU core

DDE

interface circuit

DDE

Analog circuits

(A/D converter)

Internal

peripheral

circuit

I/O

1.8 to 3.6 V

1.8 to 5.5 V

GND

I/O pins

Figure 2.1.1 Power Supply System

2.2 Operating Voltage (VDD, VSS)

The core CPU and internal peripheral circuits operate with a voltage supplied between the VDD and VSS pins. The following operating voltage can be used:

DD = 1.8 V to 3.6 V (VSS = GND)

Note: The S1 C33L03 has 4 V

pins. Do not open any of them.

The ope rating clock frequency range (OSC3) is 5 MHz to 50 MHz with this voltage.

DD pins an d 10 VSS pins. Be sure to supply the operating voltage to all the

A-12 EPSON S1C33L03 PRODUCT PART

2 POWER SUPPLY

2.3 Power Supply for I/O Interface (VDDE)

The VDDE voltage is used for interfacing with external I/O signals. For the output interface of the S1C33L03, the V

DDE voltage is used as high level and the VSS voltage as low level.

Normally, supply the same voltage level as V pin is used for the ground common with VDD. The following voltage is enabled for V

DDE = 1.8 V to 5.5 V (VSS = GND)

DD. It can be suppli ed separately from VDD for 5 V interface. The VSS

DDE:

A-1 A-2

Notes:•The S1C33L03 has 4 V

DDE pin s. Be sure t o supp l y a volta ge to al l the pins. Do not open any of

them.

•When an ext ernal clock is input to the OSC1 or OSC3 pin, the clock signal level must be V

•The interface voltage level of the DSIO, P10, P11, P12, P13 and P14 pins is V

DD.

2.4 Power Supply for Analog Circuits (AVDDE)

The analog power supply pin (AVDDE) is provided separately from the VDD and VDDE pins in order that the digital circuits do not affect the analog circuit (A/D converter). The AV and the V Supply the same voltage level as the V

Note: Be sure to supply V

SS pin is used as the analog ground.

DDE to the AVDDE pin.

DDE = VDDE, VSS = GND

DDE to the AVDDE pin even if the analog circu it is not used .

Noise on the analog power lines decrease the A/D converting precision, so use a stabilized power supply and make the board pattern with consideration given to that.

DDE pin is used to supply an analog power voltage

S1C33L03 PRODUCT PART EPSON A-13

3 INTERNAL MEMORY

3 In ternal Memory

This chapter explains the internal memory configuration.

Figure 3.1 shows the S1C33L 03 memory map.

Area Areas 18–11

Area 10

Areas 9–7

Area 6

Areas 5–4

Area 3

Area 2

Area 1

Area 0

Address

0xFFFFFFF

0x1000000 0x0FFFFFF

0x0C00000 0x0BFFFFF

0x0400000 0x03FFFFF

0x0300000 0x02FFFFF

0x0100000 0x00FFFFF

0x0080000 0x007FFFF

0x0060000 0x005FFFF

0x0050000 0x004FFFF

0x0040000 0x003FFFF

0x0030000 0x002FFFF

0x0002000 0x0001FFF

0x0000000

Figure 3.1 Memory Map

For middleware use

For CPU, debug mode

Internal peripheral circuits

(Mirror of internal RAM)

Internal RAM (8KB)

External Memory

LCD controller

SDRAM controller

External Memory

(Reserved)

(Mirror of internal

peripheral circuits)

(Mirror of internal

peripheral circuits)

Area 2 is use d in debug mo de only and it cannot be accessed in user mode (normal program execution status).

3.1 ROM and Boot Address

The S1C3 3L03 does no t have a built-in ROM. Th e boot add ress is fixed at 0x0C00000, a nd so externa l ROM/Fla sh should be use d in Area 10.

For setting up Area 10, refer to the "BCU (Bus Control Unit)" in "S1C33L03 FUNCTION PART" in this manual.

A-14 EPSON S1C33L03 PRODUCT PART

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