Epson S1C31D50 Technical Instructions

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Seiko Epson Corporation

S1C31D50 TECHNICAL MANUAL

(Rev. 1.00)

CMOS 32-BIT SINGLE CHIP MICROCONTROLLER

S1C31D50

Technical Manual

Rev. 1.00

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Seiko Epson Corporation

S1C31D50 TECHNICAL MANUAL

(Rev. 1.00)

Evaluation board/kit and Development tool important notice

1. This evaluation board/kit or development tool is designed for use for engineering evaluation,

demonstration, or development purposes only. Do not use it for other purposes. It is not intended to meet the requirements of design for finished products.

2. This evaluation board/kit or development tool is intended for use by an electronics engineer

and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson dose not assume any responsibility or liability of any kind of damage and/or fire coursed by the use of it. The user should cease to use it when any abnormal issue occurs even during proper and safe use.

3. The part used for this evaluation board/kit or development tool may be changed without any

notice.

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. When exporting the products or technology described in this material, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You are requested not to use, to resell, to export and/or to otherwise dispose of the products (and any technical information furnished, if any) for the development and/or manufacture of weapon of mass destruction or for other military purposes.

ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies.

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Seiko Epson Corporation

S1C31D50 TECHNICAL MANUAL

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Preface

XXX register:

Represents a register including its all bits.

XXX.YYY bit:

Represents the one control bit YYY in the XXX register.

XXX.ZZZ[1:0] bits:

Represents the two control bits ZZZ1 and ZZZ0 in the XXX register

Initial:

Value set at initialization

Reset

Initialization condition. The initialization condition depends on the reset group (H0, H1, or S0). For more information on the reset groups, refer to “Initialization Conditions (Reset Groups)” in the “Power Supply, Reset, and Clocks” chapter.

R/W:

R =

Read only bit

W =

Write only bit

WP =

Write only bit with a write protection using the SYSPROT.PROT[15:0] bits

R/W =

Read/write bit

R/WP =

Read/write bit with a write protection using the SYSPROT.PROT[15:0] bits

Bit

0 or 1

to 4 bits

0x0 to 0xf

5 to 8 bits

0x00 to 0xff

9 to 12 bits

0x000 to 0xfff

13 to 16 bits

0x0000 to 0xffff

Decimal

0 to 9999...

Binary

0b0000... to 0b1111...

This is a technical manual for designers and programmers who develop a product using the S1C31D50. This document describes the functions of the IC, embedded peripheral circuit operations, and their control methods.

Notational conventions and symbols in this manual

Peripheral circuit chapters do not provide control register addresses. Refer to “Peripheral Circuit Area” in the “Memory and Bus” chapter or “List of Peripheral Circuit Control Registers” in the

Appendix.

In this manual, the register and control bit names are described as shown below to distinguish from signal and pin names.

(reserved): Reserved bit. Do not alter from the initial value.

Control bit read/write values

This manual describes control bit values in a hexadecimal notation except for one-bit values (and except when decimal or binary notation is required in terms of explanation). The values are described as shown below according to the control bit width.

Channel number

Multiple channels may be implemented in some peripheral circuits (e.g., 16-bit timer, etc.). The

peripheral circuit chapters use ‘n’ as the value that represents the channel number in the register

and pin names regard- less of the number of channel actually implemented. Normally, the descriptions are applied to all channels. If there is a channel that has different functions from others, the channel number is specified clearly. Example) T16_nCTL register of the 16-bit timer If one channel is implemented (Ch.0 only): T16_nCTL = T16_0CTL only If two channels are implemented (Ch.0 and Ch.1): T16_nCTL = T16_0CTL and T16_1CTL

For the number of channels implemented in the peripheral circuits of this IC, refer to “Features” in the “Overview” chapter.

Low power mode

This manual describes the low power modes as HALT mode and SLEEP mode. These terms refer to sleep mode and deep sleep mode in the Cortex®-M0+ processor, respectively.

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1. Overview ________________________________________________________ 1-1

1.1. Features ___________________________________________________________ 1-1

1.2. Block Diagram ______________________________________________________ 1-4

1.3.

Pins

_______________________________________________________________ 1-5

1.3.1. Pin Configuration Diagram ________________________________________________ 1-5

1.3.2. Pin Descriptions ________________________________________________________ 1-9

2. Power Supply, Reset, and Clocks _____________________________________ 2-1

2.1. Power Generator (PWGA) _____________________________________________ 2-1

2.1.1. Overview ______________________________________________________________ 2-1

2.1.2.

Pins

__________________________________________________________________ 2-2

2.1.3. VD1 Regulator Operation Mode ___________________________________________ 2-2

2.1.4. VD1 Regulator Voltage Mode _____________________________________________ 2-3

2.2. System Reset Controller (SRC) _________________________________________ 2-4

2.2.1. Overview ______________________________________________________________ 2-4

2.2.2. Input Pin ______________________________________________________________ 2-4

2.2.3. Reset Sources __________________________________________________________ 2-5

2.2.4. Initialization Conditions (Reset Groups) ______________________________________ 2-6

2.3. Clock Generator (CLG) ________________________________________________ 2-7

2.3.1. Overview ______________________________________________________________ 2-7

2.3.2. Input/Output Pins ______________________________________________________ 2-8

2.3.3. Clock Sources __________________________________________________________ 2-9

2.3.4. Operations ___________________________________________________________ 2-12

2.4. Operating Mode ___________________________________________________ 2-18

2.4.1. Initial Boot Sequence ___________________________________________________ 2-18

2.4.2. Transition between Operating Modes______________________________________ 2-18

2.5. Interrupts ________________________________________________________ 2-20

2.6. Control Registers ___________________________________________________ 2-21

3. CPU AND DEBUGGER ______________________________________________ 3-1

3.1. Overview __________________________________________________________ 3-1

3.2. CPU Core __________________________________________________________ 3-1

3.3. Debugger __________________________________________________________ 3-1

3.3.1. List of debugger input/output pins _________________________________________ 3-1

3.3.2. External Connection _____________________________________________________ 3-1

4. Memory and Bus __________________________________________________ 4-1

4.1. Overview __________________________________________________________ 4-1

4.2. Bus Access Cycle ____________________________________________________ 4-2

4.3. Flash Memory ______________________________________________________ 4-3

4.3.1. Flash Memory Pin _______________________________________________________ 4-3

4.3.2. Flash Bus Access Cycle Setting _____________________________________________ 4-3

4.3.3. Flash Programming ______________________________________________________ 4-3

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4.4. RAM ______________________________________________________________ 4-3

4.5. Peripheral Circuit Control Registers _____________________________________ 4-4

4.5.1. System-Protect Function _________________________________________________ 4-4

4.6. Instruction Cache ___________________________________________________ 4-4

4.7. Memory Mapped Access Area For External Flash Memory __________________ 4-4

4.8. Control Registers ____________________________________________________ 4-5

5. Interrupt ________________________________________________________ 5-1

5.1. Overview __________________________________________________________ 5-1

5.2. Vector Table ________________________________________________________ 5-2

5.2.1. Vector Table Offset Address (VTOR) _________________________________________ 5-5

5.2.2. Priority of Interrupts _____________________________________________________ 5-5

5.3. Peripheral Circuit Interrupt Control _____________________________________ 5-5

5.4.

NMI

______________________________________________________________ 5-5

6. DMA Controller (DMAC) ____________________________________________ 6-1

6.1. Overview __________________________________________________________ 6-1

6.2. Operations_________________________________________________________ 6-2

6.2.1.

Initialization

____________________________________________________________ 6-2

6.3.

Priority

____________________________________________________________ 6-2

6.4. Data Structure ______________________________________________________ 6-2

6.4.1. Transfer Source End Pointer _______________________________________________ 6-4

6.4.2. Transfer Destination End Pointer ___________________________________________ 6-4

6.4.3. Control Data ___________________________________________________________ 6-4

6.5. DMA Transfer Mode _________________________________________________ 6-6

6.5.1. Basic Transfer __________________________________________________________ 6-6

6.5.2. Auto-Request Transfer ___________________________________________________ 6-6

6.5.3. Ping-Pong Transfer ______________________________________________________ 6-7

6.5.4. Memory Scatter-Gather Transfer __________________________________________ 6-8

6.5.5. Peripheral Scatter-Gather Transfer ________________________________________ 6-11

6.6. DMA Transfer Cycle _________________________________________________ 6-12

6.7. Interrupts ________________________________________________________ 6-12

6.8. Control Registers ___________________________________________________ 6-13

7. I/O Ports (PPORT) _________________________________________________ 7-1

7.1. Overview __________________________________________________________ 7-1

7.2. I/O Cell Structure and Functions _______________________________________ 7-2

7.2.1. Schmitt Input __________________________________________________________ 7-2

7.2.2. Over Voltage Tolerant Fail-Safe Type I/O Cell _________________________________ 7-2

7.2.3. Pull-Up/Pull-Down ______________________________________________________ 7-2

7.2.4. CMOS Output and High Impedance State ___________________________________ 7-3

7.3. Clock Settings ______________________________________________________ 7-3

7.3.1. PPORT Operating Clock __________________________________________________ 7-3

7.3.2. Clock Supply in SLEEP Mode _______________________________________________ 7-3

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7.3.3. Clock Supply During Debugging ____________________________________________ 7-3

7.4.

Operations

_________________________________________________________ 7-4

7.4.1.

Initialization

____________________________________________________________ 7-4

7.4.2. Port Input/Output Control ________________________________________________ 7-6

7.5. Interrupts _________________________________________________________ 7-7

7.6. Control Registers ____________________________________________________ 7-8

7.7. Control Register and Port Function Configuration of this IC __________________ 7-14

7.7.1. P0 Port Group _________________________________________________________ 7-14

7.7.2. P1 Port Group _________________________________________________________ 7-15

7.7.3. P2 Port Group _________________________________________________________ 7-16

7.7.4. P3 Port Group _________________________________________________________ 7-17

7.7.5. P4 Port Group _________________________________________________________ 7-18

7.7.6. P5 Port Group _________________________________________________________ 7-19

7.7.7. P6 Port Group _________________________________________________________ 7-20

7.7.8. P7 Port Group _________________________________________________________ 7-21

7.7.9. P8 Port Group _________________________________________________________ 7-22

7.7.10. P9 Port Group _________________________________________________________ 7-23

7.7.11. PA Port Group _________________________________________________________ 7-24

7.7.12. PD Port Group _________________________________________________________ 7-25

7.7.13. Common Registers between Port Groups ___________________________________ 7-26

8. Universal Port Multiplexer (UPMUX) __________________________________ 8-1

8.1. Overview __________________________________________________________ 8-1

8.2. Peripheral Circuit I/O Function Assignment _______________________________ 8-1

8.3. Control Registers ____________________________________________________ 8-2

9. Watchdog Timer (WDT2) ____________________________________________ 9-1

9.1. Overview __________________________________________________________ 9-1

9.2. Clock Settings ______________________________________________________ 9-1

9.2.1. WDT2 Operating Clock ___________________________________________________ 9-1

9.2.2. Clock Supply in DEBUG Mode _____________________________________________ 9-1

9.3. Operations_________________________________________________________ 9-2

9.3.1. WDT2 Control __________________________________________________________ 9-2

9.3.2. Operations in HALT and SLEEP Modes _______________________________________ 9-3

9.4. Control Registers ____________________________________________________ 9-4

10. Real-Time Clock (RTCA) __________________________________________ 10-1

10.1. Overview _______________________________________________________ 10-1

10.2. Output Pin and External Connection _________________________________ 10-1

10.2.1. Output Pin ____________________________________________________________ 10-1

10.3. Clock Settings ___________________________________________________ 10-2

10.3.1. RTCA Operating Clock __________________________________________________ 10-2

10.3.2. Theoretical Regulation Function __________________________________________ 10-2

10.4. Operations ______________________________________________________ 10-4

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10.4.1. RTCA Control __________________________________________________________ 10-4

10.4.2. Real-Time Clock Counter Operations ______________________________________ 10-5

10.4.3. Stopwatch Control _____________________________________________________ 10-5

10.4.4. Stopwatch Count-up Pattern _____________________________________________ 10-6

10.5. Interrupts ______________________________________________________ 10-7

10.6. Control Registers _________________________________________________ 10-8

11. Supply Voltage Detector (SVD3) ___________________________________ 11-1

11.1. Overview _______________________________________________________ 11-1

11.2. Input Pins and External Connection __________________________________ 11-2

11.2.1. Input Pins ____________________________________________________________ 11-2

11.2.2. External Connection ____________________________________________________ 11-2

11.3. Clock Settings ___________________________________________________ 11-3

11.3.1. SVD3 Operating Clock __________________________________________________ 11-3

11.3.2. Clock Supply in SLEEP Mode ______________________________________________ 11-3

11.3.3. Clock Supply in DEBUG Mode ____________________________________________ 11-3

11.4. Operations ______________________________________________________ 11-4

11.4.1. SVD3 Control __________________________________________________________ 11-4

11.4.2. SVD3 Operations _______________________________________________________ 11-4

11.5. SVD3 Interrupt and Reset __________________________________________ 11-6

11.5.1. SVD3 Interrupt ________________________________________________________ 11-6

11.5.2. SVD3 Reset ___________________________________________________________ 11-6

11.6. Control Registers _________________________________________________ 11-7

12. 16-bit Timers (T16) _____________________________________________ 12-1

12.1. Overview _______________________________________________________ 12-1

12.2. Input Pin _______________________________________________________ 12-1

12.3. Clock Settings ___________________________________________________ 12-2

12.3.1. T16 Operating Clock ____________________________________________________ 12-2

12.3.2. Clock Supply in SLEEP Mode ______________________________________________ 12-2

12.3.3. Clock Supply During Debugging ___________________________________________ 12-2

12.3.4. Event Counter Clock ____________________________________________________ 12-2

12.4.

Operations

______________________________________________________ 12-3

12.4.1.

Initialization

___________________________________________________________ 12-3

12.4.2. Counter Underflow ____________________________________________________ 12-3

12.4.3. Operations in Repeat Mode _____________________________________________ 12-3

12.4.4. Operations in One-shot Mode ____________________________________________ 12-4

12.4.5. Counter Value Read ____________________________________________________ 12-4

12.5. Interrupt _______________________________________________________ 12-4

12.6. Control Registers _________________________________________________ 12-5

13. UART (UART3) __________________________________________________ 13-1

13.1. Overview _______________________________________________________ 13-1

13.2. Input/Output Pins and External Connections __________________________ 13-2

13.2.1. List of Input/Output Pins ________________________________________________ 13-2

13.2.2. External Connections ___________________________________________________ 13-3

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13.2.3. Input Pin Pull-Up Function _______________________________________________ 13-3

13.2.4. Output Pin Open-Drain Output Function____________________________________ 13-3

13.2.5. Input/Output Signal Inverting Function _____________________________________ 13-3

13.3. Clock Settings ___________________________________________________ 13-4

13.3.1. UART3 Operating Clock _________________________________________________ 13-4

13.3.2. Clock Supply in SLEEP Mode ______________________________________________ 13-4

13.3.3. Clock Supply During Debugging ___________________________________________ 13-4

13.3.4. Baud Rate Generator ___________________________________________________ 13-4

13.4. Data Format ____________________________________________________ 13-5

13.5. Operations ______________________________________________________ 13-6

13.5.1. Initialization __________________________________________________________ 13-6

13.5.2. Data Transmission ______________________________________________________ 13-6

13.5.3. Data Reception ________________________________________________________ 13-8

13.5.4. IrDA Interface _________________________________________________________ 13-9

13.5.5. Carrier Modulation____________________________________________________ 13-10

13.6. Receive Errors __________________________________________________ 13-11

13.6.1. Framing Error ________________________________________________________ 13-11

13.6.2. Parity Error __________________________________________________________ 13-11

13.6.3. Overrun Error ________________________________________________________ 13-11

13.7. Interrupts _____________________________________________________ 13-12

13.8. DMA Transfer Requests ___________________________________________ 13-12

13.9. Control Registers ________________________________________________ 13-13

14. Synchronous Serial Interface (SPIA) ________________________________ 14-1

14.1. Overview _______________________________________________________ 14-1

14.2. Input/Output Pins and External Connections __________________________ 14-2

14.2.1. List of Input/Output Pins ________________________________________________ 14-2

14.2.2. External Connections ___________________________________________________ 14-2

14.2.3. Pin Functions in Master Mode and Slave Mode ______________________________ 14-3

14.2.4. Input Pin Pull-Up/Pull-Down Function _____________________________________ 14-3

14.3. Clock Settings ___________________________________________________ 14-4

14.3.1. SPIA Operating Clock ___________________________________________________ 14-4

14.3.2. Clock Supply During Debugging ___________________________________________ 14-5

14.3.3. SPI Clock (SPICLKn) Phase and Polarity _____________________________________ 14-5

14.4. Data Format ____________________________________________________ 14-5

14.5. Operations ______________________________________________________ 14-6

14.5.1. Initialization __________________________________________________________ 14-6

14.5.2. Data Transmission in Master Mode ________________________________________ 14-6

14.5.3. Data Reception in Master Mode__________________________________________ 14-9

14.5.4. Terminating Data Transfer in Master Mode ________________________________ 14-11

14.5.5. Data Transfer in Slave Mode ____________________________________________ 14-11

14.5.6. Terminating Data Transfer in Slave Mode __________________________________ 14-12

14.6. Interrupts _____________________________________________________ 14-13

14.7. DMA Transfer Requests ___________________________________________ 14-14

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14.8. Control Registers ________________________________________________ 14-15

15. Quad Synchronous Serial Interface (QSPI) ___________________________ 15-1

15.1. Overview _______________________________________________________ 15-1

15.2. Input/Output Pins and External Connections __________________________ 15-2

15.2.1. List of Input/Output Pins ________________________________________________ 15-2

15.2.2. External Connections ___________________________________________________ 15-2

15.2.3. Pin Functions in Master Mode and Slave Mode ______________________________ 15-6

15.2.4. Input Pin Pull-Up/Pull-Down Function _____________________________________ 15-6

15.3. Clock Settings ___________________________________________________ 15-7

15.3.1. QSPI Operating Clock ___________________________________________________ 15-7

15.3.2. Clock Supply During Debugging ___________________________________________ 15-7

15.3.3. QSPI Clock (QSPICLKn) Phase and Polarity ___________________________________ 15-8

15.4. Data Format ____________________________________________________ 15-8

15.5.

Operations

_____________________________________________________ 15-10

15.5.1. Register Access Mode _________________________________________________ 15-10

15.5.2. Memory Mapped Access Mode _________________________________________ 15-10

15.5.3.

Initialization

__________________________________________________________ 15-12

15.5.4. Data Transmission in Master Mode _______________________________________ 15-13

15.5.5. Data Reception in Register Access Master Mode ___________________________ 15-15

15.5.6. Data Reception in Memory Mapped Access Mode __________________________ 15-18

15.5.7. Terminating Memory Mapped Access Operations ___________________________ 15-27

15.5.8. Terminating Data Transfer in Master Mode ________________________________ 15-27

15.5.9. Data Transfer in Slave Mode ____________________________________________ 15-28

15.5.10. Terminating Data Transfer in Slave Mode ________________________________ 15-29

15.6. Interrupts _____________________________________________________ 15-30

15.7. DMA Transfer Requests ___________________________________________ 15-32

15.8. Control Registers ________________________________________________ 15-33

16. I2C (I2C) ______________________________________________________ 16-1

16.1. Overview _______________________________________________________ 16-1

16.2. Input/Output Pins and External Connections __________________________ 16-2

16.2.1. List of Input/Output Pins ________________________________________________ 16-2

16.2.2. External Connections ___________________________________________________ 16-2

16.3. Clock Settings ___________________________________________________ 16-3

16.3.1. I2C Operating Clock ____________________________________________________ 16-3

16.3.2. Clock Supply During Debugging ___________________________________________ 16-3

16.3.3. Baud Rate Generator ___________________________________________________ 16-4

16.4. Operations ______________________________________________________ 16-5

16.4.1. Initialization __________________________________________________________ 16-5

16.4.2. Data Transmission in Master Mode ________________________________________ 16-5

16.4.3. Data Reception in Master Mode__________________________________________ 16-8

16.4.4. 10-bit Addressing in Master Mode _______________________________________ 16-11

16.4.5. Data Transmission in Slave Mode_________________________________________ 16-12

16.4.6. Data Reception in Slave Mode __________________________________________ 16-14

16.4.7. Slave Operations in 10-bit Address Mode __________________________________ 16-15

16.4.8. Automatic Bus Clearing Operation ________________________________________ 16-16

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16.4.9. Error Detection _______________________________________________________ 16-17

16.5. Interrupts _____________________________________________________ 16-18

16.6. DMA Transfer Requests ___________________________________________ 16-20

16.7. Control Registers ________________________________________________ 16-21

17. 16-bit PWM Timers (T16B) _______________________________________ 17-1

17.1. Overview _______________________________________________________ 17-1

17.2. Input/Output Pins ________________________________________________ 17-2

17.3. Clock Settings ___________________________________________________ 17-3

17.3.1. T16B Operating Clock ___________________________________________________ 17-3

17.3.2. Clock Supply in SLEEP Mode ______________________________________________ 17-3

17.3.3. Clock Supply During Debugging ___________________________________________ 17-3

17.3.4. Event Counter Clock ____________________________________________________ 17-3

17.4.

17.4.1.

17.4.2. Counter Block Operations _______________________________________________ 17-5

17.4.3. Comparator/Capture Block Operations ____________________________________ 17-8

17.4.4. TOUT Output Control __________________________________________________ 17-18

Operations

Initialization

______________________________________________________ 17-4

___________________________________________________________ 17-4

17.5. Interrupt ______________________________________________________ 17-24

17.6. DMA Transfer Requests ___________________________________________ 17-24

17.7. Control Registers ________________________________________________ 17-25

18. IR Remote Controller (REMC3) ____________________________________ 18-1

18.1. Overview _______________________________________________________ 18-1

18.2. Output Pins and External Connections ________________________________ 18-2

18.2.1. List of Output Pins _____________________________________________________ 18-2

18.2.2. External Connections ___________________________________________________ 18-2

18.3. Clock Settings ___________________________________________________ 18-2

18.3.1. REMC3 Operating Clock _________________________________________________ 18-2

18.3.2. Clock Supply in SLEEP Mode ______________________________________________ 18-2

18.3.3. Clock Supply During Debugging ___________________________________________ 18-3

18.4.

18.4.1.

18.4.2. Data Transmission Procedures ____________________________________________ 18-3

18.4.3. REMO Output Waveform ________________________________________________ 18-4

18.4.4. Continuous Data Transmission and Compare Buffers __________________________ 18-6

Operations

Initialization

______________________________________________________ 18-3

___________________________________________________________ 18-3

18.5. Interrupts ______________________________________________________ 18-7

18.6. Application Example: Driving EL Lamp _________________________________ 18-7

18.7. Control Registers _________________________________________________ 18-8

19. 12-bit A/D Converter (ADC12A) ____________________________________ 19-1

19.1. Overview _______________________________________________________ 19-1

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19.2. Input Pins and External Connections _________________________________ 19-2

19.2.1. List of Input Pins _______________________________________________________ 19-2

19.2.2. External Connections ___________________________________________________ 19-2

19.3. Clock Settings ___________________________________________________ 19-2

19.3.1. ADC12A Operating Clock ________________________________________________ 19-2

19.3.2. Sampling Time ________________________________________________________ 19-3

19.4. Operations ______________________________________________________ 19-3

19.4.1. Initialization __________________________________________________________ 19-3

19.4.2. Conversion Start Trigger Source ___________________________________________ 19-4

19.4.3. Conversion Mode and Analog Input Pin Settings______________________________ 19-4

19.4.4. A/D Conversion Operations and Control Procedures __________________________ 19-4

19.5. Interrupts ______________________________________________________ 19-7

19.6. DMA Transfer Requests ____________________________________________ 19-7

19.7. Control Registers _________________________________________________ 19-8

20. R/F Converter (RFC) _____________________________________________ 20-1

20.1. Overview _______________________________________________________ 20-1

20.2. Input/Output Pins and External Connections __________________________ 20-2

20.2.1. List of Input/Output Pins ________________________________________________ 20-2

20.2.2. External Connections ___________________________________________________ 20-2

20.3. Clock Settings ___________________________________________________ 20-3

20.3.1. RFC Operating Clock ____________________________________________________ 20-3

20.3.2. Clock Supply in SLEEP Mode ______________________________________________ 20-3

20.3.3. Clock Supply in DEBUG Mode ____________________________________________ 20-3

20.4.

20.4.1.

20.4.2. Operating Modes ______________________________________________________ 20-4

20.4.3. RFC Counters _________________________________________________________ 20-4

20.4.4. Converting Operations and Control Procedure _______________________________ 20-5

20.4.5. CR Oscillation Frequency Monitoring Function _______________________________ 20-7

Operations

Initialization

______________________________________________________ 20-4

___________________________________________________________ 20-4

20.5. Interrupts ______________________________________________________ 20-8

20.6. Control Registers _________________________________________________ 20-9

21. HW Processor(HWP)&Sound DAC(SDAC) ____________________________ 21-1

21.1. Overview _______________________________________________________ 21-1

21.2. Input/Output Pins and External Connections __________________________ 21-2

21.2.1. List of Input/Output Pins ________________________________________________ 21-2

21.2.2. External Connections ___________________________________________________ 21-2

21.3. Function Configulation Flow ________________________________________ 21-3

21.4. Sound Play Function ______________________________________________ 21-4

21.4.1. Overall Flow __________________________________________________________ 21-4

21.4.2. Clock Setting __________________________________________________________ 21-5

21.4.3. Sound DAC and external Audio AMP Settings ________________________________ 21-5

21.4.4. Sound Play State Transition ______________________________________________ 21-6

21.4.5. Sound Play Configuration________________________________________________ 21-8

21.4.6. Sound Start Command __________________________________________________ 21-9

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21.4.7. Sound Stop Command _________________________________________________ 21-10

21.4.8. Mute Command ______________________________________________________ 21-11

21.4.9. Release Mute Command _______________________________________________ 21-12

21.4.10. Pause Command ___________________________________________________ 21-14

21.4.11. Release Pause Command ____________________________________________ 21-15

21.4.12. Sound Play Error ___________________________________________________ 21-16

21.4.13. Sound Play Interrupt Masking _________________________________________ 21-16

21.4.14. Sound Play Function Registers ________________________________________ 21-17

21.4.15. Sound Flow Example ________________________________________________ 21-20

21.5. Memory Check Function __________________________________________ 21-25

21.5.1. Overall Flow _________________________________________________________ 21-25

21.5.2. Clock Setting _________________________________________________________ 21-25

21.5.3. Memory Check State Transition _________________________________________ 21-26

21.5.4. Memory Check Configuration ___________________________________________ 21-28

21.5.5. RAM Check R/W Start Command ________________________________________ 21-29

21.5.6. RAM Check March-C Start Command _____________________________________ 21-30

21.5.7. FLASH CHECKSUM Start Command _______________________________________ 21-31

21.5.8. FLASH CRC Start Command _____________________________________________ 21-32

21.5.9. Memory Check Error __________________________________________________ 21-33

21.5.10. Memory Check Interrupt Masking _____________________________________ 21-33

21.5.11. Memory Check Function Registers _____________________________________ 21-34

21.6. Control Registers ________________________________________________ 21-36

22. Peripheral Circuit Control Registers _________________________________ B-1

23. Electrical Characteristics _________________________________________ 23-1

23.1. Absolute Maximum Ratings ________________________________________ 23-1

23.2. Recommended Operating Conditions ________________________________ 23-1

23.3. Current Consumption _____________________________________________ 23-2

23.4. System Reset Controller (SRC) Characteristics __________________________ 23-5

23.5. Clock Generator (CLG) Characteristics ________________________________ 23-6

23.6. Flash Memory Characteristics_______________________________________ 23-9

23.7. Input/Output Port (PPORT) Characteristics ____________________________ 23-9

23.8. Supply Voltage Detector (SVD3) Characteristics ________________________ 23-10

23.9. UART (UART3) Characteristics ______________________________________ 23-12

23.10. Synchronous Serial Interface (SPIA) Characteristics _____________________ 23-13

23.11.

23.12. I2C (I2C) Characteristics __________________________________________ 23-16

23.13. 12-bit A/D Converter (ADC12A) Characteristics _______________________ 23-17

Quad Synchronous Serial Interface (QSPI) Characteristics

_________________ 23-15

23.14. R/F Converter (RFC) Characteristics _________________________________ 23-18

24. Basic External Connection Diagram ________________________________ 24-1

25. Package ______________________________________________________ 25-1

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26. Appendix _____________________________________________________ 26-1

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1. Overview

1.1. Features

The S1C31D50 is a 32-bit ARM® Cortex®-M0+ MCU which integrates a specific hardware block called the HW Processor. The HW Processor can perform 2ch Voice/Audio Play, Voice Speed Conversion, and Self Memory Check without using any CPU resource. The S1C31D50 is suitable for home electronics, white goods, and battery-based products which require voice and audio playback. With the HW Processor, low memory footprint and multi-language support are achievable because of its integrated high-compression algorithm for voice and audio.

Table 1.1.1 Features

Model S1C31D50

CPU

CPU core

ARM® 32-bit RISC CPU core Cortex®-M0+

Other

Serial-wire debug ports (SW-DP) and a micro trace buffer (MTB) included

Embedded Flash memory

Capacity

192K bytes (for both instructions and data)

Erase/program count

1,000 times (min.) * When being programmed by the dedicated flash loader

Other On-board programming function

Flash programming voltage can be generated internally.

Embedded RAMs

General-purpose RAM

8K bytes + 14K bytes (when HW Processor is not active)

Instruction cache

512 bytes

HW Processor

Sound Play FUNCTION

Sound Algorithm

EPSON high quality & High compress algorithm

Play channels

2ch mixing support(suitable for background music + Voice play

Sampling Frequency

15.625kHz, (suitable for background music + Voice play)

Bitrate

16/24/32/40 kbps

Voice Speed Conversion

75% - 125% (5% step)

Self Memory Check FUNCTION

On Chip RAM Check

W/R Check, MARCH-C

On Chip Flash check

Checksum, CRC

External SPI-Flash Check

Checksum, CRC

Sound DAC

Sampling Frequency

15.625kHz

Serial interfaces

UART (UART3)

3 channels

Baud-rate generator included, IrDA1.0 supported

Open drain output, signal polarity, and baud rate division ratio are configurable.

Infrared communication carrier modulation output function

Synchronous serial interface (SPIA)

3 channels

2 to 16-bit variable data length

The 16-bit timer (T16) can be used for the baud-rate generator in master mode.

Quad synchronous serial interface (QSPI)

1 channel

Supports single, dual, and quad transfer modes.

Low CPU overhead memory mapped access mode that can directly read data from the external flash memory with XIP (eXecute-In-Place) mode.

I2C (I2C) 3 channels

Baud-rate generator included

DMA Controller (DMAC)

Number of channels

4 channels

Data transfer path

Memory to memory, memory to peripheral, and peripheral to memory

Transfer mode

Basic, ping-pong, scatter-gather

DMA trigger source

UART3, SPIA, QSPI, I2C, T16B, ADC12A, and software

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Clock generator (CLG)

System clock source

4 sources (IOSC/OSC1/OSC3/EXOSC)

System clock frequency (operating frequency)

VD1 voltage mode = mode0: 16 MHz (max.) VD1 voltage mode = mode1: 1.8 MHz (max.)

IOSC oscillator circuit (boot clock source)

VD1 voltage mode = mode0: 8/2/1 MHz (typ.) software selectable VD1 voltage mode = mode1: 1.8/0.9 MHz (typ.) software selectable

10 µs (typ.) starting time (time from cancelation of SLEEP state to vector table read

OSC1 oscillator circuit

32.768 kHz (typ.) crystal oscillator

32kHz (typ.) embedded oscillator

Oscillation stop detection circuit included

OSC3 oscillator circuit 16 MHz (max.) crystal/ceramic oscillator

16/8/4MHz(typ) embedded oscillator

EXOSC clock input

16 MHz (max.) square or sine wave input

Other

Configurable system clock division ratio

Configurable system clock used at wake up from SLEEP state

Operating clock frequency for the CPU and all peripheral circuits is selectable.

I/O port (PPORT)

Number of general-purpose I/O ports PKG48pin : 39bits(max.) PKG64pin : 55bits(max.) PKG80pin : 71bits(max.) PKG100pin : 91bits(max.)

Pins are shared with the peripheral I/O.

Number of input interrupt ports

PKG48pin : 33bits(max.) PKG64pin : 49bits(max.) PKG80pin : 65bits(max.) PKG100pin : 85bits(max.)

Number of ports that support universal port multiplexer (UPMUX)

PKG48pin : 16bits(max.) PKG64pin : 24bits(max.) PKG80pin : 27bits(max.) PKG100pin : 32bits(max.)

A peripheral circuit I/O function selected via software can be assigned to each port.

Timers

Watchdog timer (WDT2) Generates NMI or watchdog timer reset.

Programmable NMI/reset generation cycle

Real-time clock (RTCA)

128–1 Hz counter, second/minute/hour/day/day of the week/month/year counters

Theoretical regulation function for 1-second correction

Alarm and stopwatch functions

16-bit timer (T16) 8 channels

Generates the SPIA and QSPI master clocks, and the ADC12A operating clock/

16-bit PWM timer (T16B)

2 channels

Event counter/capture function

PWM waveform generation function

Number of PWM output or capture input ports: 4 ports/channel

Supply voltage detector (SVD3)

Number of channels

1 channel

Detection voltage

VDD or an external voltage (2 external detection ports are available.)

Detection level

VDD: 28 levels (1.8 to 5.0 V)/external voltage: 32 levels (1.2 to 5.0 V)

Other Intermittent operation mode

Generates an interrupt or reset according to the detection level evaluation.

12-bit A/D converter (ADC12A)

Conversion method

Successive approximation type

Resolution

12 bits

Number of conversion channels

1 channel

Number of analog signal inputs

8 ports/channel (max)

R/F converter（RFC）

Conversion method

CR oscillation type 24-bit counters

Number of conversion channels

1 channel

Supported sensors

DC bias resistive sensors

IR remote controller (REMC3)

Number of transmitter channels

1 channel

Other EL lamp drive waveform can be generated (by the hardware) for an application

Output inversion function

Reset

#RESET pin

Reset when the reset pin is set to low.

Power-on reset

Reset at power on.

Brown-out reset

Reset when the power supply voltage drops (when VDD ≤ 1.45 V (typ.) is detected).

Watchdog timer reset

Reset when the watchdog timer overflows (can be enabled/disabled using a

Supply voltage detector reset

Reset when the supply voltage detector detects the set voltage level (can be enabled/ disabled using a register).

Interrupt

Non-maskable interrupt

6 systems (Reset, NMI, HardFault, SVCall, PendSV, SysTic)

Programmable interrupt External interrupt: 3 systems

Internal interrupt: 27 systems

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Power supply voltage

VDD operating voltage

1.8 to 5.5 V * If VDD > 3.6 V, the VD1 voltage mode must be mode0.

VDD operating voltage for Flash programming

2.4 to 5.5 V (when VPP is supplied externally)

2.7 to 5.5 V (when VPP is generated internally)

SPI-Flash interface power supply

3.0 to 3.6V（possible to set main VDD:5v, SPI-Flash power supply :3.3v）

Operating temperature

Operating temperature range

-40 to 85 °C

Current consumption (Typ. value)

SLEEP mode

0.46 µA IOSC = OFF, OSC1 = OFF, OSC3 = OFF

0.95 µA IOSC = OFF, OSC1 = 32.768 kHz (crystal oscillator), OSC3 = OFF, RTCA = ON

HALT mode

1.8 µA IOSC = OFF, OSC1 = 32.768 kHz (crystal oscillator), OSC3 = OFF

RUN mode

250 µA/MHz VD1 voltage mode = mode0, CPU = IOSC

155 µA/MHz VD1 voltage mode = mode1, CPU = IOSC

Shipping form

TQFP12-48 ( 7mm x 7mm, 0.5mm pitch)

QFP13-64 (10mm x 10mm, 0.5mm pitch)

TQFP14-80 (12mm x 12mm, 0.5mm pitch)

QFP15-100 (14mm x 14mm, 0.5mm pitch)

*1 SLEEP mode refers to deep sleep mode in the Cortex®-M0+ processor. *2 HALT mode refers to sleep mode in the Cortex®-M0+ processor.

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1.2. Block Diagram

Figure 1.2.1 S1C31D50 Block Diagram

CPU core, Interrupt

controller, and debugger

(Cortex-M0+)

SWCLK

SWD

Flash memory

192K bytes

MTB

RAM

8K bytes

DMA

controller

Synchronous

serial

interface

I2C

(I2C) 3 Ch.

HW Processor

I/O port01

(PPORT)

Watchdog

timer

(WDT2)

Real-time

clock

Supply

voltage

detector

16-bit timer

(T16) 8Ch.

16-bit PWM

timer

(T16B) 2 Ch.

UART

(UART3) 3 Ch.

Clock

generator

(CLG)

IOSC

oscillator

OSC1

oscillator

OSC3

oscillator

EXOSC

oscillator

System reset

controller

(SRC)

Power-on

reset/

Brown-out

reset

(POR/BOR)

Power generator

(PWGA)

System clock

Interrupt signal

DMA request

Cache

controller

Cache RAM

512 bytes

12bit A/D

convertor

(ADC12A) 1

ADIN00-07

I/O port23

(PPORT)

I/O

portOthers

(PPORT)

VREFA0

#RESET

EXCL00-01

CAP10-13

SDACOUT_P

SDACOUT_N

P00-07

P10-17

#ADTRG

QSDIO00-03

QSPICLK0

#QSPISS0

SDI0-2

SDO0-2

SPICLK0-2

USIN0-2

#SPISS0-2

SDA0-2

SCL0-2

USOUT0-2

P20-27

P30-37

P40-47

P50-57

P60-67

P70-77

P80-87

P90-95

PA0-A6

VDDQSPI

RAM

14K bytes

Sound_DAC

1 Ch.

EXSVD0-1

IR remote

controller

(REMC3)

REMO

CLPLS

EXCL10-11

R/F converter

(RFC) 1 Ch.

SENB0

REF0

RFCLKO0

RFIN0

SENA0

TOUT10-13

Quad

synchronous

serial

interface

CAP00-03

TOUT00-03

16-bit peripheral bus

32-bit AHB bus

PD0-D5

RTC1S

FOUT

OSC1

OSC2

OSC3

OSC4

EXOSC

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1.3.

Pins

1.3.1. Pin Configuration Diagram

TQFP12-48

VSS

VD1

PD3/OSC4

PD2/OSC3

SDACOUT_N/P51

SDACOUT_P/P50

P23/RFIN0/UPMUX

P22/REF0/UPMUX

P21/SENA0/UPMUX

P20/SENB0/UPMUX

P62/EXSVD1

P61/EXSVD0

36 35 34 33 32 31 30 29 28 27 26 25

#RESET

37 24

P46/RTC1S

VDD

38 23

P45/#ADTRG

OSC1

39 22

P40/VREFA

OSC2

40 21

P17/UPMUX/ADIN0

P83/EXOSC

41 20

P16/UPMUX/ADIN1

P84/EXCL00

42 19

P15/UPMUX/ADIN2

P85/EXCL01

43 18

P14/UPMUX/ADIN3

P72/EXCL10

44 17

P13/UPMUX/ADIN4

P73/EXCL11

45 16

P06/UPMUX

SWCLK/PD0

46 15

P05/UPMUX

SWD/PD1

47 14

P04/UPMUX

TEST

48 13

P03/UPMUX

1 2 3 4 5 6 7 8 9 10 11 12

P30/RFCLKO0/UPMUX

P31/REMO/UPMUX

P32/CLPLS/UPMUX

VPP

P90/QSPICLK0

P91/QSDIO00

P92/QSDIO01

P93/QSDIO02

P94/QSDIO03

P95/#QSPISS0

VDDQSPI

PA3/FOUT

TQFP12-48

Figure 1.3.1.1 S1C31D50 Pin Configuration Diagram (TQFP12-48)

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QFP13-64

VSS

VD1

PD3/OSC4

PD2/OSC3

SDACOUT_N/P51

SDACOUT_P/P50

P27/UPMUX

P26/UPMUX

P25/UPMUX

P24/UPMUX

P23/RFIN0/UPMUX

P22/REF0/UPMUX

P21/SENA0/UPMUX

P20/SENB0/UPMUX

P62/EXSVD1

P61/EXSVD0

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

#RESET

49 32

P46/RTC1S

VDD

50 31

P45/#ADTRG

OSC1

51 30

P44

OSC2

52 29

P43

P81

53 28

P40/VREFA

P82

54 27

P17/UPMUX/ADIN0

P83/EXOSC

55 26

P16/UPMUX/ADIN1

P84/EXCL00

56 25

P15/UPMUX/ADIN2

P85/EXCL01

57 24

P14/UPMUX/ADIN3

P70

58 23

P13/UPMUX/ADIN4

P71

59 22

P12/UPMUX/ADIN5

P72/EXCL10

60 21

P11/UPMUX/ADIN6

P73/EXCL11

61 20

P06/UPMUX

SWCLK/PD0

62 19

P05/UPMUX

SWD/PD1

63 18

P04/UPMUX

TEST

64 17

P03/UPMUX

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

P30/RFCLKO0/UPMUX

P31/REMO/UPMUX

P32/CLPLS/UPMUX

P33/UPMUX

P34/UPMUX

VPP

P90/QSPICLK0

P91/QSDIO00

P92/QSDIO01

P93/QSDIO02

P94/QSDIO03

P95/#QSPISS0

VDDQSPI

PA1

PA2

PA3/FOUT

QFP13-6 4

Figure 1.3.1.2 S1C31D50 Pin Configuration Diagram (QFP13-64)

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TQFP14-80pin

VSS

VD1

PD3/OSC4

PD2/OSC3

P53

P52

SDACOUT_N/P51

SDACOUT_P/P50

P27/UPMUX

P26/UPMUX

P25/UPMUX

P24/UPMUX

P23/RFIN0/UPMUX

P22/REF0/UPMUX

P21/SENA0/UPMUX

P20/SENB0/UPMUX

P64

P63

P62/EXSVD1

P61/EXSVD0

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

#RESET

61 40

P46/RTC1S

VDD

62 39

P45/#ADTRG

OSC1

63 38

P44

OSC2

64 37

P43

P80

65 36

P42

P81

66 35

P41

P82

67 34

P40/VREFA

P83/EXOSC

68 33

P17/UPMUX/ADIN0

P84/EXCL00

69 32

P16/UPMUX/ADIN1

P85/EXCL01

70 31

P15/UPMUX/ADIN2

P86

71 30

P14/UPMUX/ADIN3

P87

72 29

P13/UPMUX/ADIN4

P70

73 28

P12/UPMUX/ADIN5

P71

74 27

P11/UPMUX/ADIN6

P72/EXCL10

75 26

P10/UPMUX/ADIN7

P73/EXCL11

76 25

P07/UPMUX

P74

77 24

P06/UPMUX

SWCLK/PD0

78 23

P05/UPMUX

SWD/PD1

79 22

P04/UPMUX

TEST

80 21

P03/UPMUX

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

PD4

P30/RFCLKO0/UPMUX

P31/REMO/UPMUX

P32/CLPLS/UPMUX

P33/UPMUX

P34/UPMUX

P35/UPMUX

VPP

P90/QSPICLK0

P91/QSDIO00

P92/QSDIO01

P93/QSDIO02

P94/QSDIO03

P95/#QSPISS0

VDDQSPI

PA0

PA1

PA2

PA3/FOUT

PA4

TQFP14-80

Figure 1.3.1.3 S1C31D50 Pin Configuration Diagram (TQFP14-80)

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QFP15-100pin

VSS

VD1

PD3/OSC4

PD2/OSC3

P55

P54

P53

P52

SDACOUT_N/P51

SDACOUT_P/P50

P27/UPMUX

P26/UPMUX

P25/UPMUX

P24/UPMUX

P23/RFIN0/UPMUX

P22/REF0/UPMUX

P21/SENA0/UPMUX

P20/SENB0/UPMUX

P67

P66

P65

P64

P63

P62/EXSVD1

P61/EXSVD0

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

#RESET

76 50

P60

VDD

77 49

P47

OSC1

78 48

P46/RTC1S

OSC2

79 47

P45/#ADTRG

P56

80 46

P44

P57

81 45

P43

P80

82 44

P42

P81

83 43

P41

P82

84 42

P40/VREFA

P83/EXOSC

85 41

P17/UPMUX/ADIN0

P84/EXCL00

86 40

P16/UPMUX/ADIN1

P85/EXCL01

87 39

P15/UPMUX/ADIN2

P86

88 38

P14/UPMUX/ADIN3

P87

89 37

P13/UPMUX/ADIN4

P70

90 36

P12/UPMUX/ADIN5

P71

91 35

P11/UPMUX/ADIN6

P72/EXCL10

92 34

P10/UPMUX/ADIN7

P73/EXCL11

93 33

P07/UPMUX

P74

94 32

P06/UPMUX

P75

95 31

P05/UPMUX

SWCLK/PD0

96 30

P04/UPMUX

SWD/PD1

97 29

P03/UPMUX

TEST

98 28

P02/UPMUX

P76

99 27

P01/UPMUX

P77

100

P00/UPMUX

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

PD4

PD5

P30/RFCLKO0/UPMUX

P31/REMO/UPMUX

P32/CLPLS/UPMUX

P33/UPMUX

P34/UPMUX

P35/UPMUX

P36/UPMUX

VPP

P37/UPMUX

P90/QSPICLK0

P91/QSDIO00

P92/QSDIO01

P93/QSDIO02

P94/QSDIO03

P95/#QSPISS0

VDDQSPI

PA0

PA1

PA2

PA3/FOUT

PA4

PA5

PA6

QFP15-100

Figure 1.3.1.4 S1C31D50 Pin Configuration Diagram (QFP15-100)

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1.3.2. Pin Descriptions

Symbol meanings

Assigned signal: The signal listed at the top of each pin is assigned in the initial state. The pin function must be switched via software to assign another signal (see the “I/O Ports” chapter).

I/O: I = Input

O = Output I/O = Input/output P = Power supply A = Analog signal Hi-Z = High impedance state

Initial state: I (Pull-up) = Input with pulled up

I (Pull-down) = Input with pulled down Hi-Z = High impedance state O (H) = High level output O (L) = Low level output

Tolerant fail-safe structure:

✓ = Over voltage tolerant fail-safe type I/O cell included

(see the “I/O Ports” chapter)

Table 1.3.2.1 Pin Description

Pin name

Pin function

I/O

Initial

Tolerant fail-safe

structure

Description

VDD

VDD P - - Power(+)

VSS

VSS P - - GND

VPP

VPP P - - Flash Programing Power

VD1

VD1 A - - VD1 Regulator Output

VDDQSPI

P - -

SPI interface voltage supply.

OSC1

A - -

OSC1 oscillator input

OSC2

A - -

OSC1 oscillator output

TEST

TEST I I(Pull-down)

Test mode enable

#RESET

I(Pull-up)

Reset input

P00

I/O

Hi-Z ✓ I/O port

UPMUX

User-selected I/O (universal port multiplexer)

P01

I/O

Hi-Z ✓ I/O port

UPMUX

User-selected I/O (universal port multiplexer)

P02

I/O

Hi-Z ✓ I/O port

UPMUX

User-selected I/O (universal port multiplexer)

P03

I/O

Hi-Z ✓ I/O port

UPMUX

User-selected I/O (universal port multiplexer)

P04

I/O

Hi-Z ✓ I/O port

UPMUX

User-selected I/O (universal port multiplexer)

P05

I/O

Hi-Z ✓ I/O port

UPMUX

User-selected I/O (universal port multiplexer)

P06

I/O

Hi-Z ✓ I/O port

UPMUX

User-selected I/O (universal port multiplexer)

P07

I/O

Hi-Z ✓ I/O port

UPMUX

User-selected I/O (universal port multiplexer)

P10

I/O

Hi-Z - I/O port

UPMUX

User-selected I/O (universal port multiplexer)

ADIN7

ADC ch.7

P11

I/O

Hi-Z - I/O port

UPMUX

User-selected I/O (universal port multiplexer)

ADIN6

ADC ch.6

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P12

I/O

Hi-Z - I/O port

UPMUX

User-selected I/O (universal port multiplexer)

ADIN5

ADC ch.5

P13

I/O

Hi-Z - I/O port

UPMUX

User-selected I/O (universal port multiplexer)

ADIN4

ADC ch.4

P14

I/O

Hi-Z - I/O port

UPMUX

User-selected I/O (universal port multiplexer)

ADIN3

ADC ch.3

P15

I/O

Hi-Z - I/O port

UPMUX

User-selected I/O (universal port multiplexer)

ADIN2

ADC ch.2

P16

I/O

Hi-Z - I/O port

UPMUX

User-selected I/O (universal port multiplexer)

ADIN1

ADC ch.1

P17

I/O

Hi-Z - I/O port

UPMUX

User-selected I/O (universal port multiplexer)

ADIN0

ADC ch.0

P20

I/O

Hi-Z ✓ I/O port

SENB0

R/F converter Ch.0 sensor B oscillator pin

UPMUX

User-selected I/O (universal port multiplexer)

P21

I/O

Hi-Z ✓ I/O port

SENA0

R/F converter Ch.0 sensor A oscillator pin

UPMUX

User-selected I/O (universal port multiplexer)

P22

I/O

Hi-Z ✓ I/O port

REF0

R/F converter Ch.0 reference oscillator pin

UPMUX

User-selected I/O (universal port multiplexer)

P23

I/O

Hi-Z ✓ I/O port

RFIN0

R/F converter Ch.0 oscillation input

UPMUX

User-selected I/O (universal port multiplexer)

P24

I/O

Hi-Z ✓ I/O port

UPMUX

User-selected I/O (universal port multiplexer)

P25

I/O

Hi-Z ✓ I/O port

UPMUX

User-selected I/O (universal port multiplexer)

P26

I/O

Hi-Z ✓ I/O port

UPMUX

User-selected I/O (universal port multiplexer)

P27

I/O

Hi-Z ✓ I/O port

UPMUX

User-selected I/O (universal port multiplexer)

P30

I/O

Hi-Z ✓ I/O port

RFCLKO0

R/F converter Ch.0 clock monitor output

UPMUX

User-selected I/O (universal port multiplexer)

P31

I/O

Hi-Z ✓ I/O port

REMO

IR remote controller transmit data output

UPMUX

User-selected I/O (universal port multiplexer)

P32

I/O

Hi-Z ✓ I/O port

CLPLS

IR remote controller clear pulse output

UPMUX

User-selected I/O (universal port multiplexer)

P33

I/O

Hi-Z ✓ I/O port

UPMUX

User-selected I/O (universal port multiplexer)

P34

I/O

Hi-Z ✓ I/O port

UPMUX

User-selected I/O (universal port multiplexer)

P35

I/O

Hi-Z ✓ I/O port

UPMUX

User-selected I/O (universal port multiplexer)

P36

I/O

Hi-Z ✓ I/O port

UPMUX

User-selected I/O (universal port multiplexer)

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P37

I/O

Hi-Z ✓ I/O port

UPMUX

User-selected I/O (universal port multiplexer)

P40

I/O

Hi-Z - I/O port

VREFA

12-bit A/D converter Ch.0 reference voltage input

P41

I/O

Hi-Z ✓ I/O port

P42

I/O

Hi-Z ✓ I/O port

P43

I/O

Hi-Z ✓ I/O port

P44

I/O

Hi-Z ✓ I/O port

P45

I/O

Hi-Z ✓ I/O port

#ADTRG

12-bit A/D converter Ch.0 trigger input

P46

I/O

Hi-Z ✓ I/O port

RTC1S

Real-time clock 1-second cycle pulse output

P47

I/O

Hi-Z ✓ I/O port

P50

SDACOUT_P

I/O

O(L) ✓ SOUND DAC OUTPUT P(Default)

P50

I/O port

P51

SDACOUT_N

I/O

O(L) ✓ SOUND DAC OUTPUT N(Default)

P51

I/O port

P52

I/O

Hi-Z ✓ I/O port

P53

I/O

Hi-Z ✓ I/O port

P54

I/O

Hi-Z ✓ I/O port

P55

I/O

Hi-Z ✓ I/O port

P56

I/O

Hi-Z ✓ I/O port

P57

I/O

Hi-Z ✓ I/O port

P60

I/O

Hi-Z ✓ I/O port

P61

I/O

Hi-Z ✓ I/O port

EXSVD0

Supply voltage detector external voltage detection input 0

P62

I/O

Hi-Z ✓ I/O port

EXSVD1

Supply voltage detector external voltage detection input 1

P63

I/O

Hi-Z ✓ I/O port

P64

I/O

Hi-Z ✓ I/O port

P65

I/O

Hi-Z ✓ I/O port

P66

I/O

Hi-Z ✓ I/O port

P67

I/O

Hi-Z ✓ I/O port

P70

I/O

Hi-Z ✓ I/O port

P71

I/O

Hi-Z ✓ I/O port

P72

I/O

Hi-Z ✓ I/O port

EXCL10

16-bit PWM timer Ch.1 event counter input 0

P73

I/O

Hi-Z ✓ I/O port

EXCL11

16-bit PWM timer Ch.1 event counter input 1

P74

I/O

Hi-Z ✓ I/O port

P75

I/O

Hi-Z ✓ I/O port

P76

I/O

Hi-Z ✓ I/O port

P77

I/O

Hi-Z ✓ I/O port

P80

I/O

Hi-Z ✓ I/O port

P81

I/O

Hi-Z ✓ I/O port

P82

I/O

Hi-Z ✓ I/O port

P83

I/O

Hi-Z ✓ I/O port

EXOSC

Clock generator external clock input

P84

I/O

Hi-Z ✓ I/O port

EXCL00

16-bit PWM timer Ch.0 event counter input 0

P85

I/O

Hi-Z ✓ I/O port

EXCL01

16-bit PWM timer Ch.0 event counter input 1

P86

I/O

Hi-Z ✓ I/O port

P87

I/O

Hi-Z ✓ I/O port

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P90

I/O

Hi-Z ✓ I/O port

QSPICLK0

Quad synchronous serial interface Ch.0 clock input/output

P91

I/O

Hi-Z ✓ I/O port

QSDIO00

Quad synchronous serial interface Ch.0 data input/output

P92

I/O

Hi-Z ✓ I/O port

QSDIO01

Quad synchronous serial interface Ch.0 data input/output

P93

I/O

Hi-Z ✓ I/O port

QSDIO02

Quad synchronous serial interface Ch.0 data input/output

P94

I/O

Hi-Z ✓ I/O port

QSDIO03

Quad synchronous serial interface Ch.0 data input/output

P95

I/O

Hi-Z ✓ I/O port

#QSPISS0

Quad synchronous serial interface Ch.0 slaveselect input/output

PA0

I/O

Hi-Z ✓ I/O port

PA1

I/O

Hi-Z ✓ I/O port

PA2

I/O

Hi-Z ✓ I/O port

PA3

I/O

Hi-Z ✓ I/O port

FOUT

Clock external output

PA4

I/O

Hi-Z ✓ I/O port

PA5

I/O

Hi-Z ✓ I/O port

PA6

I/O

Hi-Z ✓ I/O port

PD0

SWCLK

I/O

(Pull-up)

✓

Serial-wire debugger clock input (default)

PD0

I/O port

PD1

SWD

I/O

(Pull-up)

✓

Serial-wire debugger data input/output (default)

PD1

I/O port

PD2

I/O

Hi-Z - I/O port

OSC3

OSC3 oscillator circuit input

PD3

I/O

Hi-Z - I/O port

OSC4

OSC3 oscillator circuit output

PD4

I/O

Hi-Z ✓ I/O port

PD5

I/O

Hi-Z ✓ I/O port

Note:

In the peripheral circuit descriptions, the assigned signal name is used as the pin name.

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Universal port multiplexer (UPMUX)

The universal port multiplexer (UPMUX) allows software to select the peripheral circuit input/output function to be assigned to each pin from those listed below.

Table 1.3.2.2 Peripheral Circuit Input/output Function Selectable by UPMUX

Peripheral

Signal

I/O

Ch.No.

Function

I2C

SCLn

I/O

n=0,1,2

I2C Ch.n clock input/output

SDAn

I/O

I2C Ch.n data input/output

UART

USINn

n=0,1,2

UART Ch,n data input

USOUTn

O UART Ch,n data output

SPI

SDIn I n=0,1,2

SPIA ch.n data input

SDOn

SPIA ch.n data output

SPICLKn

I/O

SPIA Ch.n clock input/output

#SPISSn

SPIA Ch.n slave-select input

PWM timer

TOUTn0/CAPn0

I/O

n=0,1

16-bit PWM timer Ch.n PWM output / capture input 0

TOUTn1/CAPn1

I/O

16-bit PWM timer Ch.n PWM output / capture input 1

TOUTn2/CAPn2

I/O

16-bit PWM timer Ch.n PWM output / capture input 2

TOUTn3/CAPn3

I/O

16-bit PWM timer Ch.n PWM output / capture input 3

Note: Do not assign a function to two or more pins simultaneously.

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Pin Details

QFP15

-100

TQFP14

-80

QFP13

-64

TQFP12

-48

Pin. No

Pin Name

Function

―

PD4

― ― ―

PD5

PD5 3 2 1 1

P30

P30/RFCLKO0/UPMUX

4 3 2 2 P31

P31/REMO/UPMUX

5 4 3 3 P32

P32/CLPLS/UPMUX

6 5 4 ― P33

P33/UPMUX

7 6 5 ― P34

P34/UPMUX

―

P35

P35/UPMUX

― ― ―

P36

P36/UPMUX

10 8 6 4 VPP

VPP

― ― ―

P37

P37/UPMUX

12 9 7 5 P90

P90/QSPICLK0

10 8 6

P91

P91/QSDIO00

11 9 7

P92

P92/QSDIO01

P93

P93/QSDIO02

P94

P94/QSDIO03

P95

P95/#QSPISS0

VDDQSPI

―

PA0

―

PA1

―

PA2

PA3

PA3/FOUT

―

PA4

― ― ―

PA5

― ― ―

PA6

― ― ―

P00

P00/UPMUX

― ― ―

P01

P01/UPMUX

― ― ―

P02

P02/UPMUX

P03

P03/UPMUX

P04

P04/UPMUX

P05

P05/UPMUX

P06

P06/UPMUX

―

P07

P07/UPMUX

―

P10

P10/UPMUX/ADIN7

―

P11

P11/UPMUX/ADIN6

―

P12

P12/UPMUX/ADIN5

P13

P13/UPMUX/ADIN4

P14

P14/UPMUX/ADIN3

P15

P15/UPMUX/ADIN2

P16

P16/UPMUX/ADIN1

P17

P17/UPMUX/ADIN0

P40

P40/VREFA

―

P41

―

P42

―

P43

―

P44

P45

P45/#ADTRG

P46

P46/RTC1S

― ― ―

P47

― ― ―

P60

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P61

P61/EXSVD0

P62

P62/EXSVD1

―

P63

―

P64

― ― ―

P65

― ― ―

P66

― ― ―

P67

P20

P20/SENB0/UPMUX

P21

P21/SENA0/UPMUX

P22

P22/REF0/UPMUX

P23

P23/RFIN0/UPMUX

―

P24

P24/UPMUX

―

P25

P25/UPMUX

―

P26

P26/UPMUX

―

P27

P27/UPMUX

P50

P50/SDACOUT_P

P51

P51/SDACOUT_N

―

P52

―

P53

― ― ―

P54

― ― ―

P55

PD2

PD2/OSC3

PD3

PD3/OSC2

VD1

VSS

#RESET

VDD

OSC1

OSC2

― ― ―

P56

― ― ―

P57

―

P80

―

P81

―

P82

P83

P83/EXOSC

P84

P84/EXCL00

P85

P85/EXCL01

―

P86

―

P87

―

P70

―

P71

P72

P72/EXCL10

P73

P73/EXCL11

―

P74

― ― ―

P75

PD0

PD0/SWCLK

PD1

PD1/SWD

TEST

― ― ―

P76

100

― ― ―

P77

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2. Power Supply, Reset, and Clocks

The power supply, reset, and clocks in this IC are managed by the embedded power generator, system reset controller, and clock generator, respectively.

2.1. Power Generator (PWGA)

2.1.1. Overview

PWGA is the power generator that controls the internal power supply system to drive this IC with stability and low power. The main features of PWGA are outlined below.

• Embedded VD1 regulator

- The VD1 regulator generates the VD1 voltage to drive internal circuits, this makes it possible to

keep current consumption constant independent of the VDD voltage level.

- The VD1 regulator supports two operation modes, normal mode and economy mode, and

setting the VD1 regulator into economy mode at light loads helps achieve low-power operations.

- The VD1 regulator supports two voltage modes, mode0 and mode1, and setting the VD1

regulator into mode1 during low-speed operation helps achieve low-power operations.

• VDDQSPI

- VDDQSPI is the dedicate power supply for SPI-Flash interface and P9x PORT.

Figure 2.1.1.1 shows the PWGA configuration.

Figure 2.1.1.1 PWGA Configuration

VD1

regulator

Internal circuits

REGMODE[1:0]

REGSEL

REGDIS

QSPI Interface

VD1

VDD

VD1

VSS

VDDQSPI

CPW1

CPW2

PWGA

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2.1.2.

Pins

Table 2.1.2.1 lists the PWGA pins.

Table 2.1.2.1 List of PWGA Pins

I/O Initial status

Function

VDD P –

Power supply (+)

VSS P –

GND

VD1 A –

VD1 regulator output pin

VDDQSPI P –

Power supply (+) for SPI-Flash

For the VDD/VDDQSPI operating voltage ranges and recommended external parts, refer to

“Recommended Operating Conditions, Power supply voltage VDD/VDDQSPI” in the “Electrical Characteristics” chapter and the “Basic External Connection Diagram” chapter, respectively.

2.1.3. VD1 Regulator Operation Mode

The VD1 regulator supports two operation modes, normal mode and economy mode. Setting the VD1 regulator into economy mode at light loads helps achieve low-power operations. Table 2.1.3.1 lists examples of light load conditions in which economy mode can be set.

Table 2.1.3.1 Examples of Light Load Conditions in which Economy Mode Can be Set

Light load condition

Exceptions

SLEEP mode (when all oscillators are stopped, or OSC1 only is active)

When a clock source except for OSC1 is active HALT mode (when OSC1 only is active)

RUN mode (when OSC1 only is active)

The VD1 regulator also supports automatic mode in which the hardware detects a light load condition and automatically switches between normal mode and economy mode. Use the VD1 regulator in automatic mode when no special control is required.

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2.1.4. VD1 Regulator Voltage Mode

The VD1 regulator supports two voltage modes, mode0 and mode1. When the IC runs with a low-speed clock, setting the VD1 regulator into mode1 reduces power consumption. When the voltage mode is switched, the system clock source automatically stops operating and it resumes operating after the voltage has stabilized. Table 2.1.4.1 shows the stop period of the system clock.

Table 2.1.4.1 System Clock Stop Period After Switching Voltage Mode

System clock

Stop period

IOSC

4,096 cycles

OSC1

Number of cycles set using the CLGOSC1.OSC1WT[1:0] bits

Procedure to switch from mode0 to mode1

1. Set the MODEN bits of the peripheral circuits to 0. (Stop using peripheral circuits)

2. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)

3. Switch the system clock to a low-speed clock (OSC1, IOSC 1.8 MHz or 0.9 MHz).

4. Stop OSC3 and EXOSC.

5. Configure the following PWGACTL register bits.

- Set the PWGACTL.REGSEL bit to 0. (Switch to mode1)

- Set the PWGACTL.REGDIS bit to 1. (Discharge)

- Set the PWGACTL.REGMODE[1:0] bits to 0x2. (Set to normal mode)

6. Configure the following PWGACTL register bits after the system clock supply has resumed.

- Set the PWGACTL.REGDIS bit to 0. (Stop discharging)

- Set the PWGACTL.REGMODE[1:0] bits to 0x0. (Set to automatic mode)

7. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection)

Procedure to switch from mode1 to mode0

1. Set the MODEN bits of the peripheral circuits to 0. (Stop using peripheral circuits)

2. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)

3. Configure the following PWGACTL register bits.

- Set the PWGACTL.REGSEL bit to 1. (Switch to mode0)

- Set the PWGACTL.REGMODE[1:0] bits to 0x2. (Set to normal mode)

4. Set the PWGACTL.REGMODE[1:0] bits to 0x0after the system clock supply has resumed. (Set to automatic mode)

5. Switch the system clock to a high-speed clock.

6. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection)

Notes:

• After the voltage mode has been switched, correct the RTC, as the RTC operating clock

is also stopped for the period set using the CLGOSC1.OSC1WT[1:0] bits.

• Always use the IC in mode0 when VDD is 3.6 V or higher.

• If you use two voltage mode, set mode1 before sleep or halt mode.

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2.2. System Reset Controller (SRC)

2.2.1. Overview

SRC is the system reset controller that resets the internal circuits according to the requests from the reset sources to archive steady IC operations. The main features of SRC are outlined below.

• Embedded reset hold circuit maintains reset state to boot the system safely while the internal

power supply is un- stable after power on or the oscillation frequency is unstable after the clock source is initiated.

• Supports reset requests from multiple reset sources.

- #RESET pin

- POR and BOR

- Reset request from the CPU

- Key-entry reset

- Watchdog timer reset

- Supply voltage detector reset

- Peripheral circuit software reset (supports some peripheral circuits only)

• The CPU registers and peripheral circuit control bits will be reset with an appropriate initialization

condition ac- cording to changes in status.

Figure 2.2.1.1 shows the SRC configuration.

Figure 2.2.1.1 SRC Configuration

2.2.2. Input Pin

Table 2.2.2.1 shows the SRC pin.

Table 2.2.2.1 SRC Pin

Pin name

I/O

Initial status

Function

#RESET I I (Pull-up)

Reset input

The #RESET pin is connected to the noise filter that removes pulses not conforming to the requirements. An internal pull-up resistor is connected to the #RESET pin, so the pin can be left open. For the #RESET pin characteristics, refer to “#RESET pin characteristics” in the “Electrical Characteristics” chapter.

Reset

hold

circuit

Noise filter

Reset

decoder

POR

Clock

generato

BOR

Internal reset signals

(Reset group)

SYSRST_H0

SYSRST_H1

SYSRST_S0_0

SYSRST_S0_n

To CPU and peripheral circuits

To peripheral circuit 0

To peripheral circuit 1

Boot clock IOSCCLK

Reset request

signal

VDD

VSS

#RESET

Reset request from CPU

Key-entry reset

Watchdog timer reset

Supply voltage detector reset

Software reset 0

Software reset n

SRC

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2.2.3. Reset Sources

The reset source refers to causes that request system initialization. The following shows the reset sources.

#RESET pin

Inputting a reset signal with a certain low level period to the #RESET pin issues a reset request.

POR and BOR

POR (Power On Reset) issues a reset request when the rise of VDD is detected. BOR (Brown-out Reset) issues a reset request when a certain VDD voltage level is detected. Reset requests from these circuits ensure that the system will be reset properly when the power is turned on and the supply voltage is out of the operating voltage range. Figure 2.2.3.1 shows an example of POR and BOR internal reset operation according to variations in VDD.

Figure 2.2.3.1 Example of Internal Reset by POR and BOR

For the POR and BOR electrical specifications, refer to “POR/BOR characteristics” in the “Electrical Characteristics” chapter.

Reset request from the CPU

The CPU issues a reset request by writing 1 to the AIRCR.SYSRESETREQ bit in the system control register. For more information, refer to the “Cortex®-M0+ Technical Reference Manual.”

Key-entry reset

Inputting a low level signal of a certain period to the I/O port pins configured to a reset input issues a reset re- quest. This function must be enabled using an I/O port register. For more information, refer to the “I/O Ports” chapter.

Watchdog timer reset

Setting the watchdog timer into reset mode will issue a reset request when the counter overflows. This helps re- turn the runaway CPU to a normal operating state. For more information, refer to the “Watchdog timer” chapter.

Supply voltage detector reset

By enabling the low power supply voltage detection reset function, the supply voltage detector will issue a reset request when a drop in the power supply voltage is detected. This makes it possible to put the system into reset state if the IC must be stopped under a low voltage condition. For more information, refer to the “Supply Volt- age Detector” chapter.

Peripheral circuit software reset

Some peripheral circuits provide a control bit for software reset (MODEN or SFTRST). Setting this bit initializes the peripheral circuit control bits. Note, however, that the software reset operations depend on the peripheral circuit. For more information, refer to “Control Registers” in each peripheral circuit chapter.

Note:

The MODEN bit of some peripheral circuits does not issue software reset.

X X X

RST

RUN

VDD

VSS

VRST-

VRST+

Internal state

VRST-: Reset detection voltage VRST+: Reset canceling voltage

RUN

RST

Indefinite (operating limit)

RESET state

CPU RUN state

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2.2.4. Initialization Conditions (Reset Groups)

A different initialization condition is set for the CPU registers and peripheral circuit control bits, individually. The reset group refers to an initialization condition. Initialization is performed when a reset source included in a reset group issues a reset request. Table 2.2.4.1 lists the reset groups. For the reset group to initialize the registers and control bits, refer to the “CPU and Debugger” chapter or “Control Registers” in each peripheral circuit chapter.

Table 2.2.4.1 List of Reset Groups

Reset group

Reset source

Reset cancelation timing

#RESET pin POR and BOR Reset request from the CPU Key-entry reset Supply voltage detector reset Watchdog timer reset

Reset state is maintained for the reset hold time tRSTR after the reset request is canceled.

#RESET pin POR and BOR Reset request from the CPU

Peripheral circuit software reset (MODEN and SFTRST bits. The software reset operations de- pend on the peripheral circuit.

Reset state is canceled immediately after the reset request is canceled.

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2.3. Clock Generator (CLG)

2.3.1. Overview

CLG is the clock generator that controls the clock sources and manages clock supply to the CPU and the peripheral circuits. The main features of CLG are outlined below.

• Supports multiple clock sources.

- IOSC oscillator circuit that oscillates with a fast startup and no external parts required

- Low-power OSC1 oscillator circuit in which the oscillator type can be specified from high-

precision 32.768 kHz crystal oscillator (an external resonator is required) and internal oscillator

- OSC oscillator circuit can be specified max 16MHz crystal/ceramic oscillator or max 16MHz

internal oscillator.

- EXOSC clock input circuit that allows input of square wave and sine wave clock signals up to 16

MHz

• The system clock (SYSCLK), which is used as the operating clock for the CPU and bus, and the

peripheral circuit operating clocks can be configured individually by selecting the suitable clock source and division ratio.

• Controls the oscillator and clock input circuits to enable/disable according to the operating

mode, RUN or SLEEP mode.

• Provides a flexible system clock switching function at SLEEP mode cancelation.

- The clock sources to be stopped in SLEEP mode can be selected.

- SYSCLK to be used at SLEEP mode cancelation can be selected from all clock sources.

- The oscillator and clock input circuit on/off state can be maintained or changed at SLEEP mode

cancelation.

• Provides the FOUT function to output an internal clock for driving external ICs or for

monitoring the internal state.

Figure 2.3.1.1 shows the CLG configuration.

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Figure 2.3.1.1 CLG Configuration

2.3.2. Input/Output Pins

Table 2.3.2.1 lists the CLG pins.

Table 2.3.2.1 List of CLG Pins

* Indicates the status when the pin is configured for CLG.

If the port is shared with the CLG input/output function and other functions, the CLG function must be assigned to the port. For more information, refer to the “I/O Ports” chapter.

Pin name

I/O* Initial status*

Function

OSC1

Ａ –

OSC1 oscillator circuit input

OSC2

A –

OSC1 oscillator circuit output

OSC3

A –

OSC3 oscillator circuit input

OSC4

A –

OSC3 oscillator circuit output

EXOSC

I I

EXOSC clock input

FOUT

O O (L)

FOUT clock output

Peripheral circuit n

Peripheral circuit 1

IOSCEN

CLKSRC[1:0]

CLKDIV[1:0]

WUPMD

WUPSRC[1:0]

WUPDIV[1:0]

FOUTDIV[2:0]

IOSC

oscillator

circuit

Divider

Clock

selector

System

clock

controller

OSC1EN

OSC1

oscillator

circuit

Divider

OSC3EN

OSC3

oscillator

circuit

Divider

EXOSCEN

EXOSC

clock input

circuit

FOUTEN

CLKSRC[x:0]

CLKDIV[x:0]

FOUT

output

circuit

Clock

selector

CLKSRC[x:0]

CLKDIV[x:0]

Clock

selector

To CPU and bus

FOUT

EXOSC

OSC4

OSC3

OSC2

OSC1

X’tal3/ Ceramic3

X’tal1

IOSCCLK

OSC1CLK

OSC3CLK

EXOSCCLK

SLEEP, WAKE-UP

SYSCLK

Internal data bus

CLG

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2.3.3. Clock Sources

IOSC oscillator circuit

The IOSC oscillator circuit features a fast startup and no external parts are required for oscillating. Figure 2.3.3.1 shows the configuration of the IOSC oscillator circuit.

Figure 2.3.3.1 IOSC Oscillator Circuit Configuration

The IOSC oscillator circuit output clock IOSCCLK is used as SYSCLK at booting. The IOSCCLK frequency can be selected using the CLGIOSC.IOSCFQ[1:0] bits. For more information for the oscillation characteristics, refer to “IOSC oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respectively.

OSC1 oscillator circuit

The OSC1 oscillator circuit is a low-power oscillator circuit that allows software to select the oscillator type from two different types shown below. Figure 2.3.3.2 shows the configuration of the OSC1 oscillator circuit.

Figure 2.3.3.2 OSC1 Oscillator Circuit Configuration

IOSCEN

Clock

oscillator

Oscillation

stabilization

waiting circuit

Interrupt

control circuit

CPU core

IOSCSTAIE

IOSCSTAIF

IOSCFQ[1:0]

IOSCCLK

IOSC oscillator circuit

Internal data bus

Oscillation startup

control circuit

OSC1 oscillator circuit

voltage regulator

Oscillation

stabilization

waiting

circuit

Oscillation

stop

detector

Noise

filter

Interrupt

control

circuit

OSC1WT[1:0]

CGI1[2:0]

OSC1STAIF

OSC1STPIF

Interrupt

controller

QOSC1EN

Selector OSC1SELCR

Clock

oscillator

OSC1BUP

INV1N[1:0]

INV1B[1:0]

OSDRB

OSDEN

External gate capacitor CG1

OSC1 oscillator circuit

External drain capacitor CD1

OSC1

OSC2

Internal variable gate capacitor CGI1

Internal drain capacitor CDI1

Feedback resistor RF1

Drain resistor RD1

Gain-controlled oscillation inverter

Restart

signal

Crystal oscillator

OSC1CLK

OSC1STAIE

OSC1STPIE

Internal data bus

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Crystal oscillator

This oscillator circuit includes a gain-controlled oscillation inverter and a variable gate capacitor allowing use of various crystal resonators (32.768 kHz typ.) with ranges from cylinder type through surface-mount type. The oscillator circuit also includes a feedback resistor and a drain resistor, so no external parts are required except for a crystal resonator. The embedded oscillation stop detector, which detects oscillation stop and restarts the oscillator, allows the system to operate in safety under adverse environments that may stop the oscillation. The oscillation startup control circuit operates for a set period of time after the oscillation is enabled to assist the oscillator in initiating, this makes it possible to use a low-power resonator that is difficult to start up.

Note:

Depending on the circuit board or the crystal resonator type used, an external gate capacitor CG1 and a drain capacitor CD1 may be required.

Internal oscillator

This 32 kHz oscillator circuit operates without any external parts. When the internal oscillator circuit is used, set the OSC1 pin level to VSS and leave the OSC3 pin open.

For the recommended parts and the oscillation characteristics, refer to the “Basic External Connection Diagram” chapter and “OSC1 oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respectively.

OSC3 oscillator circuit

The OSC3 oscillator circuit is a crystal/ceramic oscillator, internal oscillator that generates a highspeed clock. Figure 2.3.3.3 shows the configuration of the OSC3 oscillator circuit.

Figure 2.3.3.3 OSC3 Oscillator Circuit Configuration

Crystal/Ceramic Mode

This oscillator circuit includes a feedback resistor and a drain resistor, so no external part is required except for a crystal/ceramic resonator. The embedded gain-controlled inverter allows selection of the resonator from a wide frequency range. For the recommended parts and the oscillation characteristics, refer to the “Basic External Connection Diagram” chapter and the “Electrical Characteristics” chapter, respectively.

OSC3EN

Oscillation

stabilization

waiting

circuit

Noise

filter

OSC3INV[1:0]

OSC3WT[2:0]

CPU core

I/O

port

External gate capacitor CG3

External drain capacitor CD3

OSC3

OSC4

Peripheral I/O function 4

Internal gate capacitor CGI3C

Internal drain capacitor CDI3C

VSS

Feedback resistor RF3

Gain-

controlled

inverter

Drain resistor

RD3

OSC3CLK

X’tal3/ Ceramic3

OSC3 oscillator circuit

Internal data bus

Interrupt

control circuit

Auto-

trimming

circuit

OSC3STM

OSC1

oscillator

circuit

OSC3STAIE

OSC3STAIF

OSC3TEDIF

OSC3TEDIE

OSC3TERIF

OSC3TERIE

OSC1CLK

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Internal Oscillator Mode

The OSC3 oscillator circuit is equipped with an auto- trimming function that automatically adjusts the frequency. This helps reduce frequency deviation due to unevenness in manufacturing quality, temperature, and changes in voltage. For more information on the auto- trimming function and the

oscillation characteristics, refer to “OSC3 oscillation auto-trimming function” in this chapter and “OSC3 oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respectively.

EXOSC clock input

EXOSC is an external clock input circuit that supports square wave and sine wave clocks. Figure

2.3.3.4 shows the configuration of the EXOSC clock input circuit

Figure 2.3.3.4 EXOSC Clock Input Circuit

EXOSC has no oscillation stabilization waiting circuit included, therefore, it must be enabled when a stabilized clock is being supplied. For the input clock characteristics, refer to “EXOSC external clock input characteristics” in the “Electrical Characteristics” chapter.

Input

control

EXOSC clock input circuit

EXOSC

EXOSCCLK

Internal data bus

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2.3.4. Operations

Oscillation start time and oscillation stabilization waiting time

The oscillation start time refers to the time after the oscillator circuit is enabled until the oscillation signal is actually sent to the internal circuits. The oscillation stabilization waiting time refers to the time it takes the clock to stabilize after the oscillation starts. To avoid malfunctions of the internal circuits due to an unstable clock during this period, the oscillator circuit includes an oscillation stabilization waiting circuit that can disable sup- plying the clock to the system until the designated time has elapsed. Figure 2.3.4.1 shows the relationship between the oscillation start time and the oscillation stabilization waiting time.

Figure 2.3.4.1 Oscillation Start Time and Oscillation Stabilization Waiting Time

The oscillation stabilization waiting times for the OSC1 and OSC3 oscillator circuits can be set using the CLGOSC1.OSC1WT[1:0] bits and CLGOSC3.OSC3WT[2:0] bits, respectively. To check whether the oscillation stabilization waiting time is set properly and the clock is stabilized immediately after the oscillation starts or not, monitor the oscillation clock using the FOUT output function. The oscillation stabilization waiting time for the IOSC oscillator circuit is fixed at 16 IOSCCLK clocks. The oscillation stabilization waiting time for the OSC1 oscillator circuit should be set to 16,384 OSC1CLK clocks or more when crystal oscillator is selected, or 4,096 OSC1CLK clocks or more when internal oscillator is selected. The oscillation stabilization waiting time for the OSC3 oscillator circuit should be set to 1,024 OSC3CLK clocks or more. When the oscillation stabilization waiting operation has completed, the oscillator circuit sets the oscillation stabilization waiting completion flag and starts clock supply to the internal circuits.

Note:

The oscillation stabilization waiting time is always expended at start of oscillation even if the oscillation stabilization waiting completion flag has not be cleared to 0.

System supply waiting time

Oscillation start time

Oscillator circuit enable

(OSCEN)

Oscillation waveform

Digitized oscillation waveform

Oscillator circuit output clock

(OSCCLK)

Oscillation stabilization waiting completion flag

(OSCSTAIF)

Oscillation stabilization waiting time

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When the oscillation startup control circuit in the OSC1 oscillator circuit is enabled by setting the CLGOSC1.OS- C1BUP bit to 1, it uses the high-gain oscillation inverter for a set period of time (startup boosting operation) after the oscillator circuit is enabled (by setting the CLGOSC.OSC1EN bit to 1) to reduce oscillation start time. Note, however, that the oscillation operation may become unstable if there is a large gain differential between normal operation and startup boosting operation. Furthermore, the oscillation start time being actually reduced depends on the characteristics of the resonator used. Figure 2.3.4.2 shows an operation example when the oscillation start-up control circuit is used.

(1)

CLGOSC1.OSC1BUP bit = 0 (startup boosting operation disabled)

(2)

CLGOSC1.OSC1BUP bit = 1 (startup boosting operation enabled)

Figure 2.3.4.2 Operation Example when the Oscillation Startup Control Circuit is Used

Oscillator circuit enable

(CLGOSC.OSC1EN)

Oscillation inverter

INV1N[1:0] setting gain

Oscillation waveform

Normal operation

Oscillator circuit enable

(CLGOSC.OSC1EN)

Oscillation inverter

INV1N[1:0] setting gain

Oscillation waveform

Normal operation

INV1B[1:0] setting gain

Startup boosting

operation

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Oscillation start procedure for the IOSC oscillator circuit

Follow the procedure shown below to start oscillation of the IOSC oscillator circuit.

1. Write 1 to the CLGINTF.IOSCSTAIF bit. (Clear interrupt flag)

2. Write 1 to the CLGINTE.IOSCSTAIE bit. (Enable interrupt)

3. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)

4. Configure the CLGIOSC.IOSCFQ[1:0] bits. (Select frequency)

5. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection)

6. Write 1 to the CLGOSC.IOSCEN bit. (Start oscillation)

7. IOSCCLK can be used if the CLGINTF.IOSCSTAIF bit = 1 after an interrupt occurs.

Oscillation start procedure for the OSC1 oscillator circuit

Follow the procedure shown below to start oscillation of the OSC1 oscillator circuit.

1. Write 1 to the CLGINTF.OSC1STAIF bit. (Clear interrupt flag)

2. Write 1 to the CLGINTE.OSC1STAIE bit. (Enable interrupt)

3. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)

4. Configure the following CLGOSC1 register bits:

- CLGOSC1.OSC1SELCR bit (Select oscillator type)

- CLGOSC1.OSC1WT[1:0] bits (Set oscillation stabilization waiting time)

In addition to the above, configure the following bits when using the crystal oscillator:

- CLGOSC1.INV1N[1:0] bits (Set oscillation inverter gain)

- CLGOSC1.CGI1[2:0] bits (Set internal gate capacitor)

- CLGOSC1.INV1B[1:0] bits (Set oscillation inverter gain for

startup boosting period)

- CLGOSC1.OSC1BUP bit (Enable/disable oscillation

startup control circuit)

5. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection)

6. Write 1 to the CLGOSC.OSC1EN bit. (Start oscillation)

7. OSC1CLK can be used if the CLGINTF.OSC1STAIF bit = 1 after an interrupt occurs.

The setting values of the CLGOSC1.INV1N[1:0], CLGOSC1.CGI1[2:0], CLGOSC1.OSC1WT[1:0] and CLGOSC1.INV1B[1:0] bits should be determined after performing evaluation using the populated circuit board.

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Oscillation start procedure for the OSC3 oscillator circuit

Crystal/ceramic mode

Follow the procedure shown below to start oscillation of the OSC3 oscillator circuit.

1. Write 1 to the CLGINTF.OSC3STAIF bit. (Clear interrupt flag)

2. Write 1 to the CLGINTE.OSC3STAIE bit. (Enable interrupt)

3. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)

4. Configure the following CLGOSC3 register bits.

- CLGOSC3.OSC3WT[2:0] bits (Set oscillation stabilization waiting time)

- CLGOSC3.OSC3INV[1:0] bits (Set oscillation inverter gain)

- CLGOSC3.OSC3MD bits (Set crystal/ceramic oscillation mode)

5. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits.

(Set system protection)

6. Assign the OSC3 oscillator input/output functions to the ports.

(Refer to the “I/O Ports” chapter.)

7. Write 1 to the CLGOSC.OSC3EN bit. (Start oscillation)

8. OSC3CLK can be used if the CLGINTF.OSC3STAIF bit = 1 after an interrupt occurs.

The setting values of the CLGOSC3.OSC3INV[1:0] and CLGOSC3.OSC3WT[2:0] bits should be determined after performing evaluation using the populated circuit board.

Internal Oscillation

Follow the procedure shown below to start oscillation of the OSC3 oscillator circuit.

1. Write 1 to the CLGINTF.OSC3STAIF bit. (Clear interrupt flag)

2. Write 1 to the CLGINTE.OSC3STAIE bit. (Enable interrupt)

3. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)

4. Configure the following CLGOSC3 register bits.

- CLGOSC3.OSC3WT[2:0] bits (Set oscillation stabilization waiting time)

- CLGOSC3.OSC3MD bits (Set CR oscillation mode)

5. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits.

(Set system protection)

6. Write 1 to the CLGOSC.OSC3EN bit. (Start oscillation)

7. OSC3CLK can be used if the CLGINTF.OSC3STAIF bit = 1 after an interrupt occurs.

System clock switching

The CPU boots using IOSCCLK as SYSCLK. After booting, the clock source of SYSCLK can be switched ac- cording to the processing speed required. The SYSCLK frequency can also be set by selecting the clock source division ratio, this makes it possible to run the CPU at the most suitable performance for the process to be executed. The CLGSCLK.CLKSRC[1:0] and CLGSCLK.CLKDIV[1:0] bits are used for this control. The CLGSCLK register bits are protected against writings by the system protect function, therefore, the system protection must be removed by writing 0x0096 to the SYSPROT.PROT[15:0] bits before the register setting can be altered. For the transition between the operating modes including the system clock switching, refer to “Operating Mode.”

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Clock control in SLEEP mode

Whether the clock sources being operated are stopped or not when the CPU enters SLEEP mode (deep sleep mode) can be selected in each source individually. This allows the CPU to fast switch between SLEEP mode and RUN mode, and the peripheral circuits to continue operating without disabling the clock in SLEEP mode. The CLGOSC.IOSCSLPC, CLGOSC.OSC1SLPC, CLGOSC.OSC3SLPC, and CLGOSC.EXOSCSLPC bits are used for this control. Figure 2.3.4.3 shows a control example.

(1)

When the CLGOSC.OSC1SLPC bit = 1

(2)

When the CLGOSC.OSC1SLPC bit = 0

Figure 2.3.4.3 Clock Control Example in SLEEP Mode

The SYSCLK condition (clock source and division ratio) at wake-up from SLEEP mode to RUN mode can also be configured. This allows flexible clock control according to the wake-up process. Configure the clock using the CLGSCLK.WUPSRC[1:0] and CLGSCLK.WUPDIV[1:0] bits, and write 1 to the CLGSCLK.WUPMD bit to enable this function.

(1)

When the CLGSCLK.WUPMD bit = 0

(2)

When the CLGSCLK.WUPMD bit = 1 and the CLGSCLK.WUPSRC[1:0] bits = 0x0

Figure 2.3.4.4 Clock Control Example in SLEEP Mode

SLEEP mode

(CPU stop, CLK stop)

IOSCCLK (Unstable)

IOSCCLK

SYSCLK

(CPU operating clock)

IOSCCLK

(CLK stop)

OSC1CLK (Unstable)

OSC1CLK

Real-time clock

operating clock

OSC1CLK

Executing the WFI/WFE instruction

(SLEEPDEEP bit = 1)

Executing the WFI/WFE instruction

(SLEEPDEEP bit = 1)

* The real-time clock is turned off in

SLEEP mode as the clock stops.

SLEEP mode

(CPU stop, CLK stop)

IOSCCLK (Unstable

IOSCCLK

SYSCLK

(CPU operating clock)

IOSCCLK

OSC1CLK

Real-time clock

operating clock

Executing the WFI/WFE instruction

(SLEEPDEEP bit = 1)

Executing the WFI/WFE instruction

(SLEEPDEEP bit = 1)

* The real-time clock keeps operating in SLEEP mode as the clock is being supplied..

SLEEP mode

(CPU stop, CLK stop)

IOSCCLK (Unstable)

IOSCCLK

SYSCLK

(CPU operating clock)

IOSCCLK

(CLK stop)

OSC1CLK (Unstable)

OSC1CLK

Real-time clock

operating clock

OSC1CLK

Executing the WFI/WFE instruction

(SLEEPDEEP bit = 1)

Executing the WFI/WFE instruction

(SLEEPDEEP bit = 1)

* The real-time clock is turned off in

SLEEP mode as the clock stops.

SLEEP mode

(CPU stop, CLK stop)

IOSCCL

(Unstable

IOSCCLK

SYSCLK

(CPU operating clock)

IOSCCLK

OSC1CLK

Real-time clock

operating clock

Executing the WFI/WFE instruction

(SLEEPDEEP bit = 1)

Executing the WFI/WFE instruction

(SLEEPDEEP bit = 1)

* The real-time clock keeps operating in SLEEP mode as the clock is being supplied..

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Clock external output (FOUT)

The FOUT pin can output the clock generated by a clock source or its divided clock to outside the IC. This al- lows monitoring the oscillation frequency of the oscillator circuit or supplying an operating clock to external ICs. Follow the procedure shown below to start clock external output.

1. Assign the FOUT function to the port. (Refer to the “I/O Ports” chapter.)

2. Configure the following CLGFOUT register bits:

- CLGFOUT.FOUTSRC[1:0] bits (Select clock source)

- CLGFOUT.FOUTDIV[2:0] bits (Set clock division ratio)

- Set the CLGFOUT.FOUTEN bit to 1. (Enable clock external output)

OSC3 oscillation auto-trimming function

The auto-trimming function adjusts the 16MHz OSC3CLK clock frequency selected using the CLGOSC3.OSC3FQ[1:0] bits by trimming the clock with reference to the high precision OSC1CLK clock generated by the OSC1 oscillator circuit (crystal oscillator). Follow the procedure shown below to enable the auto-trimming function.

1. After enabling the OSC1 oscillation, check if the stabilized clock is supplied.

(CLGINTF.OSC1STAIF bit = 1).

2. After enabling the OSC3 oscillation, check if the stabilized clock is supplied

(CLGINTF.OSC3STAIF bit = 1).

3. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)

4. Configure the following CLGINTF register bits:

- Write 1 to the CLGINTF.OSC3TEDIF bit. (Clear interrupt flag)

- Write 1 to the CLGINTF.OSC3TERIF bit. (Clear interrupt flag)

5. Configure the following CLGINTF register bits:

- Set the CLGINTE.OSC3TEDIE bit to 1. (Enable interrupt)

- Set the CLGINTE.OSC3TERIE bit to 1. (Enable interrupt)

6. Write 1 to the CLGOSC3.OSC3STM bit. (Enable OSC3 oscillation auto-trimming)

7. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits.

(Set system protection)

After the trimming operation has completed, the CLGIOSC.OSC3STM bit automatically reverts to 0. Although the trimming time depends on the temperature, an average of several 10 ms is required.

OSC1 oscillation stop detection function

The oscillation stop detection function restarts the OSC1 oscillator circuit when it detects oscillation stop under adverse environments that may stop the oscillation. Follow the procedure shown below to enable the oscillation stop detection function.

1. After enabling the OSC1 oscillation, check if the stabilized clock is supplied (CLGINTF.OSC1STAIF

bit = 1).

2. Write 1 to the CLGINTF.OSC1STPIF bit. (Clear interrupt flag)

3. Write 1 to the CLGINTE.OSC1STPIE bit. (Enable interrupt)

4. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)

5. Set the following CLGOSC1 register bits:

- Set the CLGOSC1.OSDRB bit to 1. (Enable OSC1 restart function)

- Set the CLGOSC1.OSDEN bit to 1. (Enable oscillation stop detection function)

6. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection)

7. The OSC1 oscillation stops if the CLGINTF.OSC1STPIF bit = 1 after an interrupt occurs.

If the CLGOSC1.OSDRB bit = 1, the hardware restarts the OSC1 oscillator circuit.

Note:

Enabling the oscillation stop detection function increase the oscillation stop detector current (IOSD1).

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2.4. Operating Mode

2.4.1. Initial Boot Sequence

Figure 2.4.1.1 shows the initial boot sequence after power is turned on.

Figure 2.4.1.1 Initial Boot Sequence

Note:

The reset cancelation time at power-on varies according to the power rise time and reset request cancelation time. For the reset hold time tRSTR, refer to “Reset hold circuit characteristics” in the “Electrical Characteristics” chapter.

2.4.2. Transition between Operating Modes

State transitions between operating modes shown in Figure 2.4.2.1 take place in this IC.

RUN mode

RUN mode refers to the state in which the CPU is executing the program. A transition to this mode takes place when the system reset request from the system reset controller is canceled. RUN mode is classified into “IOSC RUN,” “OSC1 RUN,” “OSC3 RUN,” and “EXOSC RUN” by the SYSCLK clock source.

HALT mode

When the Cortex®-M0+ core executes the WFI or WFE instruction with the SLEEPDEEP bit of the system control register set to 0, it suspends program execution and stops operating. This state is referred to HALT mode in this IC. In this mode, the clock sources and peripheral circuits keep operating. This mode can be set while no software processing is required and it reduces power consumption as compared with RUN mode. HALT mode is classified into “IOSC HALT,” “OSC1 HALT,” “OSC3 HALT,” and “EXOSC HALT” by the SYSCLK clock source.

Undefined

Reset request from POR

IOSCCLK

Internal reset signal

Cortex®-M0+ core

(Initial SYSCLK)

SYSRST, H0, H1

program counter (PC)

Cancel reset request

Reset hold time tRSTR

Cancel reset request

*1: Reset vector (reset handler start address)

*2: Address (reset vector + 2)

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SLEEP mode

When the Cortex®-M0+ core executes the WFI or WFE instruction with the SLEEPDEEP bit of the system control register set to 1, it suspends program execution and stops operating. This state is referred to SLEEP mode in this IC. In this mode, the clock sources stop operating as well. However, the clock source in which the CLGOSC.IOSCSLPC/OSC1SLPC/OSC3SLPC/EXOSCSLPC bit is set to 0 keeps operating, so the peripheral circuits with the clock being supplied can also operate. By setting this mode when no software processing and peripheral circuit operations are required, power consumption can be less than HALT mode.

Figure 2.4.2.1 Operating Mode-to-Mode State Transition Diagram

Canceling HALT or SLEEP mode

The conditions listed below generate the HALT/SLEEP cancelation signal to cancel HALT or SLEEP mode and put the CPU into RUN mode.

• Interrupt request from a peripheral circuit

• NMI from the watchdog timer

• Reset request

IOSC RUN

IOSC

HALT

RESET

(Initial state)

OSC1 RUN

OSC3

HALT

OSC3 RUN

EXOSC

RUN

OSC1 HALT

EXOSC

HALT

RUN

SLEEP

CLGSCLK.CLKSRC[1:0] = 0x3

CLGSCLK.CLKSRC[1:0] = 0x1

CLGSCLK.CLKSRC[1:0] = 0x2

CLGSCLK.CLKSRC[1:0] = 0x0

WFI/WFE instruction

(SLEEPDEEP = 1)

HALT/SLEEP

cancelation signal

(wake-up)

Transition takes place automatically by the initial boot sequence after a request from the reset source is canceled.

In RUN and HALT modes, the clock sources not used as SYSCLK can be all disabled.

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2.5. Interrupts

CLG has a function to generate the interrupts shown in Table 2.5.1.

Table 2.5.1 CLG Interrupt Functions

Interrupt

Interrupt flag

Set condition

Clear

IOSC oscillation stabilization waiting completion

CLGINTF.IOSCSTAIF

When the IOSC oscillation stabilization waiting operation has completed after the oscillation starts

Writing 1

OSC1 oscillation stabilization waiting completion

CLGINTF.OSC1STAIF

When the OSC1 oscillation stabilization waiting operation has completed after the oscillation starts

Writing 1

OSC3 oscillation stabilization waiting completion

CLGINTF.OSC3STAIF

When the OSC3 oscillation stabilization waiting operation has completed after the oscillation starts

Writing 1

OSC3 oscillation autotrimming error

CLGINTF.OSC3TERIF

When the OSC3 oscillation auto-trimming operation has terminated due to an error

Writing 1

OSC1 oscillation stop

CLGINTF.OSC1STPIF

When OSC1CLK is stopped, or when the CLGOSC. OSC1EN or CLGOSC1.OSDEN bit setting is altered from 1 to 0.

Writing 1

OSC3 oscillation autotrimming completion

CLGINTF.OSC3TEDIF

When the OSC3 oscillation auto-trimming operation has completed

Writing 1

CLG provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter.

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2.6. Control Registers

PWGA Control Register

Bit

Bit name

Initial

Reset

R/W

Remarks

PWGACTL

15–8 –

0x00 – R

–

7–6 –

0x0 – R

REGDIS

R/WP 4 REGSEL

R/WP

3–2 –

0x0 – R

1–0 REGMODE[1:0]

0x0

R/WP

Bits 15–6 Reserved

Bit 5 REGDIS

This bit enables the VD1 regulator discharge function.

1 (R/WP): Enable 0 (R/WP): Disable

Bit 4 REGSEL

This bit controls the VD1 regulator voltage mode.

1 (R/WP): mode0 0 (R/WP): mode1

Bits 3–2 Reserved

Bits 1–0 REGMODE[1:0]

These bits control the VD1 regulator operating mode.

Table 2.6.1 Internal Regulator Operating Mode

PWGACTL.REGMODE[1:0] bits

Operating mode

0x3

Economy mode

0x2

Normal mode

0x1

Reserved

0x0

Automatic mode

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CLG System Clock Control Register

Bit

Bit name

Initial

Reset

R/W

Remarks

CLGSCLK

WUPMD

R/WP

–

0 – R

13–12 WUPDIV[1:0]

0x0

R/WP

11–10 –

0x0 – R

9–8 WUPSRC[1:0]

0x0

R/WP

7–6 –

0x0 – R

5–4 CLKDIV[1:0]

0x2

R/WP

3–2 –

0x0 – R

1–0 CLKSRC[1:0]

0x0

R/WP

Bit 15 WUPMD

This bit enables the SYSCLK switching function at wake-up.

1 (R/WP): Enable

0(R/WP): Disable When the CLGSCLK.WUPMD bit = 1, setting values of the CLGSCLK.WUPSRC[1:0] bits and the CLGSCLK.WUPDIV[1:0] bits are loaded to the CLGSCLK.CLKSRC[1:0] bits and the CLGSCLK. CLKDIV[1:0] bits, respectively, at wake-up from SLEEP mode to switch SYSCLK. When the CLG- SCLK.WUPMD bit = 0, the CLGSCLK.CLKSRC[1:0] and CLGSCLK.CLKDIV[1:0] bits are not altered at wake-up.

Bit 14 Reserved Bits 13–12 WUPDIV[1:0]

These bits select the SYSCLK division ratio for resetting the CLGSCLK.CLKDIV[1:0] bits at wake-up. This setting is ineffective when the CLGSCLK.WUPMD bit = 0.

Bits 11–10 Reserved Bits 9–8 WUPSRC[1:0]

These bits select the SYSCLK clock source for resetting the CLGSCLK.CLKSRC[1:0] bits at wake-up. When a currently stopped clock source is selected, it will automatically start oscillating or clock input at wake-up. However, this setting is ineffective when the CLGSCLK.WUPMD bit = 0.

Table 2.6.2 SYSCLK Clock Source and Division Ratio Settings at Wake-up

CLGSCLK.

WUPDIV[1:0] bits

CLGSCLK.WUPSRC[1:0] bits

0x0

0x1

0x2

0x3

IOSCCLK

OSC1CLK

OSC3CLK

EXOSCCLK

0x3

1/8

Reserved

1/16

Reserved

0x2

1/4

Reserved

1/8

Reserved

0x1

1/2 1/2 1/2

Reserved

0x0

1/1 1/1 1/1 1/1

Bits 7–6 Reserved Bits 5–4 CLKDIV[1:0]

These bits set the division ratio of the clock source to determine the SYSCLK frequency.

Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0]

These bits select the SYSCLK clock source. When a currently stopped clock source is selected, it will automatically start oscillating or clock input.

Table 2.6.3 SYSCLK Clock Source and Division Ratio Settings

CLGSCLK.

CLKDIV[1:0] bits

CLGSCLK.CLKSRC[1:0] bits

0x0

0x1

0x2

0x3

IOSCCLK

OSC1CLK

OSC3CLK

EXOSCCLK

0x3

1/8

Reserved

1/16

Reserved

0x2

1/4

Reserved

1/8

Reserved

0x1

1/2 1/2 1/2

Reserved

0x0

1/1 1/1 1/1 1/1

CLG Oscillation Control Register

Bit

Bit name

Initial

Reset

R/W

Remarks

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CLGOSC

15–12 –

0x0 – R

–

EXOSCSLPC

R/W

OSC3SLPC

R/W 9 OSC1SLPC

R/W 8 IOSCSLPC

R/W

7–4 –

0x0 – R

EXOSCEN

R/W

OSC3EN

R/W

OSC1EN

R/W 0 IOSCEN

R/W

Bits 15–12 Reserved

Bit 11 EXOSCSLPC Bit 10 OSC3SLPC Bit 9 OSC1SLPC Bit 8 IOSCSLPC

These bits control the clock source operations in SLEEP mode.

1 (R/W): Stop clock source in SLEEP mode

0 (R/W): Continue operation state before SLEEP Each bit corresponds to the clock source as follows:

CLGOSC.EXOSCSLPC bit: EXOSC clock input

CLGOSC.OSC3SLPC bit: OSC3 oscillator circuit

CLGOSC.OSC1SLPC bit: OSC1 oscillator circuit

CLGOSC.IOSCSLPC bit: IOSC oscillator circuit

Bits 7–4 Reserved

Bit 3 EXOSCEN Bit 2 OSC3EN Bit 1 OSC1EN Bit 0 IOSCEN

These bits control the clock source operation.

1(R/W): Start oscillating or clock input

0(R/W): Stop oscillating or clock input Each bit corresponds to the clock source as follows:

CLGOSC.EXOSCEN bit: EXOSC clock input

CLGOSC.OSC3EN bit: OSC3 oscillator circuit

CLGOSC.OSC1EN bit: OSC1 oscillator circuit

CLGOSC.IOSCEN bit: IOSC oscillator circuit

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CLG IOSC Control Register

Bit

Bit name

Initial

Reset

R/W

Remarks

CLGIOSC

15–8 –

0x00 – R

–

7–5 –

0x0 – R

–

0 – R

3-2

–

0 – R

1–0 IOSCFQ[1:0]

0x2

R/WP

Bits 15–5 Reserved Bit 4 Reserved Bits 3-2 Reserved

Bits 1–0 IOSCFQ[1:0]

These bits select the IOSCCLK frequency.

Table 2.6.4 IOSCCLK Frequency Selection

CLGIOSC.

IOSCFQ[1:0] bits

IOSCCLK frequency

VD1 voltage mode =

mode0

VD1 voltage mode =

mode1

0x3

Setting prohibited

0x2

8 MHz

0x1

2.0 MHz

1.8 MHz

0x0

1.0 MHz

0.9 MHz

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CLG OSC1 Control Register

Bit

Bit name

Initial

Reset

R/W

Remarks

CLGOSC1

–

0 – R

–

OSDRB

R/WP

OSDEN

R/WP

OSC1BUP

R/WP

OSC1SELCR

R/WP

10–8 CGI1[2:0]

0x0

R/WP

7–6 INV1B[1:0]

0x2

R/WP

5–4 INV1N[1:0]

0x1

R/WP

3–2 –

0x0 – R

1–0 OSC1WT[1:0]

0x2

R/WP

Bit 15 Reserved Bit 14 OSDRB

This bit enables the OSC1 oscillator circuit restart function by the oscillation stop detector when OSC1 oscillation stop is detected.

1 (R/WP): Enable

(Restart the OSC1 oscillator circuit when oscillation stop is detected.)

0 (R/WP): Disable

Bit 13 OSDEN

This bit controls the oscillation stop detector in the OSC1 oscillator circuit.

1 (R/WP): OSC1 oscillation stop detector on

0 (R/WP): OSC1 oscillation stop detector off

Note:

Do not write 1 to the CLGOSC1.OSDEN bit before stabilized OSC1CLK is supplied. Furthermore, the CLGOSC1.OSDEN bit should be set to 0 when the CLGOSC.OSC1EN bit is set to 0.

Bit 12 OSC1BUP

This bit enables the oscillation startup control circuit in the OSC1 oscillator circuit.

1 (R/WP): Enable (Activate booster operation at startup.)

0 (R/WP): Disable

Bit 11 OSC1SELCR

This bit selects an oscillator type of the OSC1 oscillator circuit.

1 (R/WP): Internal oscillator

0 (R/WP): Crystal oscillator

Bits 10–8 CGI1[2:0]

These bits set the internal gate capacitance in the OSC1 oscillator circuit.

Table 2.6.5 OSC1 Internal Gate Capacitance Setting

CLGOSC1.CGI1[2:0] bits

Capacitance

0x7

Max.

↑

↓

Min.

0x6

0x5

0x4

0x3

0x2

0x1

0x0

For more information, refer to “OSC1 oscillator circuit characteristics, Internal gate capacitance CGI1” in the “Electrical Characteristics” chapter.

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Bits 7–6 INV1B[1:0]

These bits set the oscillation inverter gain that will be applied at boost startup of the OSC1 oscillator circuit.

Table 2.6.6 Setting Oscillation Inverter Gain at OSC1 Boost Startup

CLGOSC1.INV1B[1:0] bits

Inverter gain

0x3

Max.

↑ ↓

Min.

0x2

0x1

0x0

Note:

The CLGOSC1.INV1B[1:0] bits must be set to a value equal to or larger than the CLGOSC1, INV1N[1:0] bits.

Bits 5–4 INV1N[1:0]

These bits set the oscillation inverter gain applied at normal operation of the OSC1 oscillator circuit.

Table 2.6.7 Setting Oscillation Inverter Gain at OSC1 Normal Operation

CLGOSC1.INV1N[1:0] bits

Inverter gain

0x3

Max.

↑ ↓

Min.

0x2

0x1

0x0

Bits 3–2 Reserved

Bits 1–0 OSC1WT[1:0]

These bits set the oscillation stabilization waiting time for the OSC1 oscillator circuit.

Table 2.6.8 OSC1 Oscillation Stabilization Waiting Time Setting

CLGOSC1.OSC1WT[1:0] bits

Oscillation stabilization waiting time

0x3

65,536 clocks

0x2

16,384 clocks

0x1

4,096 clocks

0x0

Reserved

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CLG OSC3 Control Register

Bit

Bit name

Initial

Reset

R/W

Remarks

CLGOSC3

15–12 –

0x00 – R

–

11-10

OSC3FQ[1:0]

0x1 H0

R/WP 9

OSC3MD

0x0 H0

R/WP 8–6 –

0x0 – R

5–4 OSC3INV[1:0]

0x3

R/WP 3 OSC3STM

R/WP

2–0 OSC3WT[2:0]

0x6

R/WP

Bits 15–12 Reserved

Bits 11–10 OSC3FQ[1:0]

These bits set OSC3 CR(Int) mode freqency select.

Table 2.6.9 OSC3 frequency

OSC3FQ [1:0] bits

OSC3 frequency

0x3

16 MHz

0x2

0x1

8 MHz

0x0

4 MHz

Bit 9 OSC3MD

This bit set OSC3 mode select.

Table 2.6.10 mode select

OSC3MD

Mode

0x1

X'tal

0x0

CR(Int)

Bits 8-6 Reserved Bits 5–4 OSC3INV[1:0]

These bits set the oscillation inverter gain when crystal/ceramic oscillator is selected as the OSC3 oscillator type.

Table 2.6.11 OSC3 Oscillation Inverter Gain Setting

CLGOSC3.OSC3INV[1:0] bits

Inverter gain

0x3

Max.

↑ ↓

Min.

0x2

0x1

0x0

Bit 3 OSC3STM

This bit controls the OSC3CLK auto-trimming function.

1 (WP): Start trimming

0 (WP): Stop trimming

1 (R): Trimming is executing.

0 (R): Trimming has finished. (Trimming operation inactivated.) This bit is automatically cleared to 0 when trimming has finished.

Notes

: • The auto-trimming function does not work if the OSC1 oscillator circuit is stopped. Make sure the CLGINTF.OSC1STAIF bit is set to 1 before starting the trimming operation. Be sure to avoid altering the CLGIOSC.OSC3FQ[1:0] bits while the auto-trimming is being executed.

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Bits 2–0 OSC3WT[2:0]

These bits set the oscillation stabilization waiting time for the OSC3 oscillator circuit.

Table 2.6.12 OSC3 Oscillation Stabilization Waiting Time Setting

CLGOSC3.OSC3WT[2:0] bits

Oscillation stabilization waiting time

0x7

65,536 clocks

0x6

16,384 clocks

0x5

4,096 clocks

0x4

1,024 clocks

0x3

256 clocks

0x2

64 clocks

0x1

16 clocks

0x0

4 clocks

CLG Interrupt Flag Register

Bit

Bit name

Initial

Reset

R/W

Remarks

CLGINTF

15–9 –

0x00 – R

–

OSC3TERIF

R/W

Cleared by writing 1.

–

0 – R

–

0 – R 5 OSC1STPIF

R/W

Cleared by writing 1.

OSC3TEDIF

R/W

–

0 – R

–

OSC3STAIF

R/W

Cleared by writing 1.

OSC1STAIF

R/W 0 IOSCSTAIF

R/W

Bits 15–9, 7, 6, 3 Reserved

Bit 8 OSC3TERIF Bit 5 OSC1STPIF Bit 4 OSC3TEDIF Bit 2 OSC3STAIF Bit 1 OSC1STAIF Bit 0 IOSCSTAIF

These bits indicate the CLG interrupt cause occurrence statuses.

1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective

Each bit corresponds to the interrupt as follows:

CLGINTF.OSC3TERIF bit: OSC3 oscillation auto-trimming error interrupt CLGINTF.OSC1STPIF bit: OSC1 oscillation stop interrupt CLGINTF.OSC3TEDIF bit: OSC3 oscillation auto-trimming completion interrupt CLGINTF.OSC3STAIF bit: OSC3 oscillation stabilization waiting completion interrupt CLGINTF.OSC1STAIF bit: OSC1 oscillation stabilization waiting completion interrupt CLGINTF.IOSCSTAIF bit: IOSC oscillation stabilization waiting completion interrupt

Note:

The CLGINTF.IOSCSTAIF bit is 0 after system reset is canceled, but IOSCCLK has already been stabilized.

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CLG Interrupt Enable Register

Bit

Bit name

Initial

Reset

R/W

Remarks

CLGINTE

15–9 –

0x00 – R

–

OSC3TERIE

R/W 7 –

0 – R 6 –

0 –

OSC1STPIE

R/W

OSC3TEDIE

R/W

–

0 – R

OSC3STAIE

R/W 1 OSC1STAIE

R/W

IOSCSTAIE

R/W

Bits 15–9, 7, 6, 3 Reserved Bit 8 OSC3TERIE Bit 5 OSC1STPIE Bit 4 OSC3TEDIE Bit 2 OSC3STAIE Bit 1 OSC1STAIE Bit 0 IOSCSTAIE

These bits enable the OSC1 oscillation stop and OSC3 oscillation auto-trimming completion interrupts.

1 (R/W): Enable interrupts 0 (R/W): Disable interrupts

Each bit corresponds to the interrupt as follows:

CLGINTE.OSC3TERIE bit: OSC3 oscillation auto-trimming error interrupt CLGINTE.OSC1STPIE bit: OSC1 oscillation stop interrupt CLGINTE.OSC3TEDIE bit: OSC3 oscillation auto-trimming completion interrupt CLGINTE.OSC3STAIE bit: OSC3 oscillation stabilization waiting completion interrupt CLGINTE.OSC1STAIE bit: OSC1 oscillation stabilization waiting completion interrupt CLGINTE.IOSCSTAIE bit: IOSC oscillation stabilization waiting completion interrupt

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CLG FOUT Control Register

Bit

Bit name

Initial

Reset

R/W

Remarks

CLGFOUT

15–8 –

0x00 – R

–

0 – R

6–4 FOUTDIV[2:0]

0x0

R/W

3–2 FOUTSRC[1:0]

0x0

R/W

–

0 – R

FOUTEN

R/W

Bits 15–7 Reserved

Bits 6–4 FOUTDIV[2:0]

These bits set the FOUT clock division ratio.

Bits 3–2 FOUTSRC[1:0]

These bits select the FOUT clock source.

Table 2.6.13 FOUT Clock Source and Division Ratio Settings

CLGFOUT.

FOUTDIV[2:0] bits

CLGFOUT.FOUTSRC[1:0] bits

0x0

0x1

0x2

0x3

IOSCCLK

OSC1CLK

OSC3CLK

SYSCLK

0x7

1/128

1/32,768

1/128

Reserved

0x6

1/64

1/4,096

1/64

Reserved

0x5

1/32

1/1,024

1/32

Reserved

0x4

1/16

1/256

1/16

Reserved

0x3

1/8 1/8 1/8

Reserved

0x2

1/4 1/4 1/4

Reserved

0x1

1/2 1/2 1/2

Reserved

0x0

1/1 1/1 1/1 1/1

Note: When the CLGFOUT.FOUTSRC[1:0] bits are set to 0x3, the FOUT output will be stopped in SLEEP/HALT mode as SYSCLK is stopped.

Bit 1 Reserved

Bit 0 FOUTEN

This bit controls the FOUT clock external output.

1 (R/W): Enable external output 0 (R/W): Disable external output

Note:

Since the FOUT signal generated is out of sync with writings to the CLGFOUT.FOUTEN bit, a glitch may occur when the FOUT output is enabled or disabled.

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3. CPU AND DEBUGGER

3.1. Overview

This IC incorporates a Cortex®-M0+ CPU core manufactured by U.K.-based ARM Ltd.

3.2. CPU Core

The following shows the system configuration of the Cortex®-M0+ CPU core embedded in this IC:

• Cortex

-M0+ core

• 32-bit single-cycle multiplier

• Nested vectored interrupt controller (NVIC)

• System timer (Systick)

• Serial-wire debug port (SW-DP)

• Micro trace buffer (MTB)

• Number of hardware break points: 4

• Number of watch points: 2

For detailed information on the Cortex®-M0+ CPU core, refer to the “Cortex®-M0+ Technical Reference Manual.”

3.3. Debugger

This IC includes a serial-wire debug port (SW-DP). For detailed information on the debug functions, refer to the “Cortex®-M0+ Technical Reference Manual.”

3.3.1. List of debugger input/output pins

Table 3.3.3.1 lists the debug pins.

Table 3.3.1.1 List of Debug Pins

Pin name

I/O

Initial state

Function

SWCLK I I

On-chip debugger clock input pin Input a clock from a debugging tool.

SWD I/O I

On-chip debugger data input/output pin Used to input/output debugging data.

The debugger input/output pins are shared with general-purpose I/O ports and are initially set as the debug pins. If the debugging function is not used, these pins can be switched to general-purpose I/O port pins. For details, refer to the “I/O Ports” chapter.

3.3.2. External Connection

Figure 3.3.2.1 shows a connection example between this IC and a debugging tool when performing debugging.

Figure 3.3.2.1 External Connection

For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, Debug pin pull-up resistors RDBG1–2” in the “Electrical Characteristics” chapter. RDBG1 and RDBG2 are not required when using the debug pins as general-purpose I/O port pins.

SWCLK

S1C31 MCU

SWD

SWCLK

SWD

VDD

RDBG2

RDBG1

Debugging Tool

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4. Memory and Bus

4.1. Overview

This IC supports up to 4G bytes of accessible memory space for both instructions and data. The features are listed below.

• Embedded Flash memory that supports on-board programming

• Write-protect function to protect system control registers

Figure 4.1.1 shows the memory map.

0xffff_ffff

Reserved

0xf024_0000

0xf022_1fff

MTB SRAM area 8KB

(Device size: 32 bits)

0xf022_0000

0xf021_ffff

Reserved

0xf020_1000

0xf020_0fff

MTB SFR area (4K bytes)

(Device size: 32 bits)

0xf020_0000

0xf01f_ffff

Reserved

0xf000_1000

0xf000_0fff

System ROM table (4K bytes)

(Device size: 32 bits)

0xf000_0000

0xefff_ffff

Cortex-M0+ private peripherals

0xe000_0000

0xdfff_ffff

Reserved

0x0020_4000

0x0020_3fff

Peripherals(12KB) 32bit

0x0020_1000

0x0020_0fff

Peripherals(4KB) 16bit

0x0020_0000

0x001f_ffff

Reserved

0x0015_6800

0x0015_67ff

Voice-RAM area (14K bytes)

(Device size: 32 bits)

0x0015_3000

0x0015_2fff

Reserved

0x0015_2000

0x0015_1fff

RAM area (8K bytes) (Device size: 32 bits)

0x0015_0000

0x0014_ffff

Reserved

0x0014_0000

0x0013_ffff

Memory mapped access area

for external Flash memory (1M bytes) (Device size: 32 bits)

0x0004_0000

0x0003_ffff

Reserved

0x0003_0000

0x0002_ffff

Flash ROM192KB(for Program & Voice Data)

(Device size: 32 bits)

0x0000_0000

Figure 4.1.1 Memory Map

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4.2. Bus Access Cycle

The CPU uses the system clock for bus access operations. First, “Bus access cycle,” “Device size,” and “Access size” are defined as follows:

• Bus access cycle: One system clock period = 1 cycle

• Device size: Bit width of the memory and peripheral circuits that can be accessed in one

cycle

• Access size: Access size designated by the CPU instructions (e.g., LDR Rt, [Rn] → 32-bit data

transfer)

Table 4.2.1 lists numbers of bus access cycles by different device size and access size. The peripheral circuits can be accessed with an 8- or 16-bit instruction.

Table 4.2.1 Number of Bus Access Cycles

Device size

Access size

Number of bus access

cycles

8 bits

16 bits

32 bits

16 bits

8 bits

16 bits

32 bits

8 bits

16 bits

32 bits

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4.3. Flash Memory

The Flash memory is used to store application programs and data. Address 0x0 in the Flash area is defined as the vector table base address by default, therefore a vector table must be located beginning from this address. For more information on the vector table, refer to “Vector Table” in the “Interrupt” chapter.

4.3.1. Flash Memory Pin

Table 4.3.1.1 shows the Flash memory pin.

Table 4.3.1.1 Flash Memory Pin

Pin name

I/O

Initial status

Function

VPP P –

Flash programming power supply

For the VPP voltage, refer to “Recommended Operating Conditions, Flash programming voltage VPP” in the “Electrical Characteristics” chapter.

Note:

Always leave the VPP pin open except when programming the Flash memory.

4.3.2. Flash Bus Access Cycle Setting

There is a limit of frequency to access the Flash memory with no wait cycle, therefore, the number of bus access cycles for reading must be changed according to the system clock frequency. The number of bus access cycles for reading can be configured using the FLASHCWAIT.RDWAIT[1:0] bits. Select a setting for higher frequency than the system clock.

4.3.3. Flash Programming

The Flash memory supports on-board programming, so it can be programmed using a flash loader. The VPP voltage can be supplied from either an external power supply or the internal voltage booster. Choose the flash loader ac- cording to the VPP power supply to be used.

Notes:

•

When the V

voltage is supplied externally, 2.4 V or more V

voltage is required.

• When the VPP voltage is generated internally, 2.7 V or more VDD voltage is required.

4.4. RAM

The RAM can be used to execute the instruction codes copied from another memory as well as storing variables or other data. This allows higher speed processing and lower power consumption than Flash memory.

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4.5. Peripheral Circuit Control Registers

The control registers for the peripheral circuits are located in the peripheral circuit area beginning with address 0x0020 0000.

4.5.1. System-Protect Function

The system-protect function protects control registers and bits from writings. They cannot be rewritten unless write protection is removed by writing 0x0096 to the SYSPROT.PROT[15:0] bits. This function is provided to prevent deadlock that may occur when a system-related register is altered by a runaway CPU. See “Control Registers” in each peripheral circuit to identify the registers and bits with write protection.

Note:

Once write protection is removed using the SYSPROT.PROT[15:0] bits, write enabled status is maintained until write protection is applied again. After the registers/bits required have been altered, apply write protection.

4.6. Instruction Cache

This IC includes an instruction cache. Enabling the cache function translates into reduced current consumption, as the Flash memory access frequency is decreased. This function is enabled by setting the CASHECTL.CACHEEN bit to 1. Setting this bit to 0 clears the instruction codes stored in the cache.

4.7. Memory Mapped Access Area For External Flash Memory

This area is used to read data from the external Flash memory via the quad synchronous serial interface. For more information, refer to the “Quad Synchronous Serial Interface” chapter.

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4.8. Control Registers

System Protect Register

Bit

Bit name

Initial

Reset

R/W

Remarks

SYSPROT

15–0 PROT[15:0]

0x0000

R/W

–

Bits 15–0 PROT[15:0]

These bits protect the control registers related to the system against writings.

0x0096 (R/W): Disable system protection Other than 0x0096 (R/W): Enable system protection

While the system protection is enabled, any data will not be written to the affected control bits (bits with “WP” or “R/WP” appearing in the R/W column).

CACHE Control Register

Bit

Bit name

Initial

Reset

R/W

Remarks

CACHECTL

15–8 –

0x00 – R

–

7–2 –

0x00 – R 1 reserved

1 – R 0 CACHEEN

R/W

Bits 15–1 Reserved

Bit 0 CACHEEN

This bit enables the instruction cache function.

1 (R/W): Enable instruction cache 0 (R/W): Disable instruction cache

FLASHC Flash Read Cycle Register

Bit

Bit name

Initial

Reset

R/W

Remarks

FLASHCWAIT

15–9 –

0x00 – R

–

(reserved)

R/WP

7–2 –

0x00 – R

1–0 RDWAIT[1:0]

0x1

R/WP

Bits 15–2 Reserved

Bits 1–0 RDWAIT[1:0]

These bits set the number of bus access cycles for reading from the Flash memory.

Table 4.8.1 Setting Number of Bus Access Cycles for Flash Read

FLASHCWAIT.

RDWAIT[1:0] bits

Number of bus

access cycles

System clock frequency

PWGACTL.

REGSEL bit = 0

PWGACTL.

REGSEL bit = 1

0x3

2.1 MHz (max.)

16.6 MHz (max.) 0x2

0x1 2 0x0

1.05 MHz (max.)

8.4 MHz (max.)

Note:

Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured.

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5. Interrupt

5.1. Overview

This IC includes a nested vectored interrupt controller (NVIC). For detailed information on the NVIC, refer to the “Cortex®-M0+ Technical Reference Manual.”

Figure 5.1.1 shows the configuration of the interrupt system.

Figure 5.1.1 Configuration of Interrupt System

CPU core

Clock

Generator

NVIC

Watchdog timer

Peripheral circuit

Interrupt request

Peripheral circuit

Interrupt request

NMI

IRQn

IRQ0

HALT/SLEEP

cancelation signal

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5.2. Vector Table

The vector table contains the vectors to the interrupt handler routines (handler routine start address) that will be read by the CPU to execute the handler when an interrupt occurs. Table 5.2.1 shows the vector table.

Table 5.2.1 Vector Table

VTOR initial value = 0x0

Interrupt

number

IRQ

number

Vector

address

offset

Source

Hardware interrupt name

Cause of hardware interrupt

Priority

0 - 0x00

Stack pointer initial value

1 - 0x04

Reset

• Low input to the #RESET pin

• Power-on reset

• Key reset

• Watchdog timer overﬂow *1

• Supply voltage detector reset

NMI

0x08

WDT

NMI

Watchdog timer overﬂow *1

3 - 0x0c

CPU

Hard fault

• Bus error

• Undefined instruction

• Unaligned address etc

4 - 0x10

System Reserved

- - 5 - 0x14

System Reserved

- - 6 - 0x18

System Reserved

- - 7 - 0x1c

System Reserved

- - 8 - 0x20

System Reserved

- - 9 - 0x24

System Reserved

- - 10 - 0x28

System Reserved

- - 11 - 0x2c

CPU

SV call

SVC instruction

Configurable

12 - 0x30

System Reserved

- - 13 - 0x34

System Reserved

- - 14 - 0x38

CPU

PendSV

Configurable

15 - 0x3c

Sys Tick

SysTick timer underﬂow

16 0 0x40

DMA

DMA controller interrupt

Transfer complete Transfer error

17 1 0x44

SVD

Supply voltage detector interrupt

Power supply voltage drop detection

18 2 0x48

PORT01

Port01 interrupt

Port01 input

19 3 0x4c

PORT23

Port23 interrupt

Port23 input

20 4 0x50

PPORTothers

PortOthers interrupt

PortOthers input

21 5 0x54

CLG

Clock generator interrupt

IOSC oscillation stabilization waiting completion OSC1 oscillation stabilization waiting completion OSC3 oscillation stabilization waiting completion OSC1 oscillation stop detection OSC3 oscillation auto-trimming completion

22 6 0x58

RTC

Real-time clock interrupt

• 1-day, 1-hour, 1-minute, and 1second

• 1/32-second, 1/8-second, 1/4second, and 1/2-second

• Stopwatch 1 Hz, 10 Hz, and 100

• Alarm

• Theoretical regulation

completion

23 7 0x5c

Proceesor

HW Proceesor interrupt

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24 8 0x60

Sound

DAC

Sound DAC interrupt

End of transmission Receive buffer full Transmit buffer empty Overrun error

Configurable

25 9 0x64

UART CH0

UART Ch.0 interrupt

• End of transmission

• Framing error

• Parity error

• Overrun error

• Receive buﬀer two bytes full

• Receive buﬀer one byte full

• Transmit buﬀer empty

0x68

T16 CH1

16-bit timer Ch.1 interrupt

Underﬂow

0x6c

SPI CH0

Synchronous serial interface Ch.0 interrupt

• End of transmission

• Receive buﬀer full

• Transmit buﬀer empty

• Overrun error

0x70

I2C CH0

I2C Ch.0 interrupt

• End of data transfer

• General call address reception

• NACK reception

• STOP condition

• START condition

• Error detection

• Receive buﬀer full

• Transmit buﬀer empty

0x74

T16B CH0

16-bit PWM timer Ch.0 interrupt

• Capture overwrite

• Compare/capture

• Counter MAX

• Counter zero

0x78

T16B CH1

16-bit PWM timer Ch.1 interrupt

• Capture overwrite

• Compare/capture

• Counter MAX

• Counter zero

0x7c

UART CH1

UART Ch.1 interrupt

• End of transmission

• Framing error

• Parity error

• Overrun error

• Receive buﬀer two bytes full

• Receive buﬀer one byte full

• Transmit buﬀer empty

0x80

T16 CH2

16-bit timer Ch.2 interrupt

Underﬂow

0x84

QSPI

Quad synchronous serial interface Ch.0 interrupt

• End of transmission

• Receive buﬀer full

• Transmit buﬀer empty

• Overrun error

0x88

I2C CH1

I2C Ch.1 interrupt

• End of data transfer

• General call address reception

• NACK reception

• STOP condition

• START condition

• Error detection

• Receive buﬀer full

• Transmit buﬀer empty

0x8c

UART CH2

UART Ch.2 interrupt

• End of transmission

• Framing error

• Parity error

• Overrun error

• Receive buﬀer two bytes full

• Receive buﬀer one byte full

• Transmit buﬀer empty

T16 CH0

16-bit timer Ch.0 interrupt

Underﬂow

0x90

T16 CH3

16-bit timer Ch.3 interrupt

Underﬂow

0x94

SPI CH1

Synchronous serial interface Ch.1 interrupt

• End of transmission

• Receive buﬀer full

• Transmit buﬀer empty

• Overrun error

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0x98

T16 CH4

16-bit timer Ch.4 interrupt

Underﬂow

Configurable

0x9c

T16 CH5

16-bit timer Ch.5 interrupt

Underﬂow

0xa0

T16 CH6

16-bit timer Ch.6 interrupt

Underﬂow

0xa4

RFC

R/F converter Ch.0 interrupt

• Reference oscillation completion

• Sensor A oscillation completion

• Sensor B oscillation completion

• Measurement counter overflow

error

• Time base counter overflow error

0xa8

ADC

12-bit A/D converter interrupt

• Analog input signal m A/D

conversion completion

• Analog input signal m A/D

conversion result overwrite error

0xac

SPI CH2

Synchronous serial interface Ch.2 interrupt

• End of transmission

• Receive buﬀer full

• Transmit buﬀer empty

• Overrun error

T16_CH7

16-bit timer Ch.7 interrupt

Underﬂow

0xb0

I2C CH2

I2C Ch.2 interrupt

• End of data transfer

• General call address reception

• NACK reception

• STOP condition

• START condition

• Error detection

• Receive buﬀer full

• Transmit buﬀer empty

0xb4

REMC

IR remote controller interrupt

• Compare AP

• Compare DB

46-

0xb8

System Reserved

*1 Either reset or NMI can be selected as the watchdog timer interrupt via software.

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5.2.1. Vector Table Offset Address (VTOR)

The CPU core provides the vector table offset register to set the offset (start) address of the vector table in which interrupt vectors are programmed. “VTOR” described in Table 5.2.1 means the value set to this register. After an initial reset, VTOR is set to address 0x0. Therefore, even when the vector table location is changed, it is necessary that at least the reset vector be written to this address. For more information on VTOR, refer to the “Cortex®-M0+ Technical Reference Manual.”

5.2.2. Priority of Interrupts

The priorities of SVCall, PendSV, and SysTick are configurable to the desired levels using the System Handler Priority Registers (SHPR2 and SHPR3). The priorities of the interrupt number 16 or later are configurable to the desired levels using the Interrupt Priority Registers (NVIC_IPR0–7). The priority value can be set within a range of 0 to 192 (a lower value has a higher priority). The priorities of reset, NMI, and HardFault are fixed at the predefined values. For more information, refer to the “Cortex®-M0+ Technical Reference Manual.”

5.3. Peripheral Circuit Interrupt Control

The peripheral circuit that generates interrupts includes an interrupt enable bit and an interrupt flag for each interrupt cause. Interrupt flag: The flag is set to 1 when the interrupt cause occurs. The clear condition

depends on the peripheral circuit.

Interrupt enable bit: By setting this bit to 1 (interrupt enabled), an interrupt request will be sent to

the CPU core when the interrupt flag is set to 1. When this bit is set to 0 (interrupt disabled), no interrupt request will be sent to the CPU core even if the interrupt flag is set to 1. An interrupt request is also sent to the CPU core if the status is changed to interrupt enabled when the interrupt flag is 1.

For specific information on causes of interrupts, interrupt flags, and interrupt enable bits, refer to the respective peripheral circuit descriptions.

Note:

To prevent occurrence of unnecessary interrupts, the corresponding interrupt flag should be cleared before setting the interrupt enable bit to 1 (interrupt enabled) and before terminating the interrupt handler routine.

5.4.

NMI

The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This interrupt takes precedence over other interrupts and is unconditionally accepted by the CPU. For detailed information on generating NMI, refer to the “Watchdog Timer” chapter.

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6. DMA Controller (DMAC)

6.1. Overview

The main features of the DMAC are outlined below.

• Supports byte, halfword, and word transfers.

• Each DMAC channel can be configured to different transfer conditions independently.

• Supports memory-to-memory, memory-to-peripheral circuit, and peripheral circuit-to-memory

transfers.

• Supports hardware DMA requests from peripheral circuits and software DMA requests.

• Priority level for each channel is selectable from two levels.

• DMA transfers are allowed even if the CPU is placed into HALT mode. Figure 6.1.1 shows the

configuration of the DMAC.

Table 6.1.1 DMAC Channel Configuration of S1C31D50

Item

S1C31D50

Number of channels

4 channels (Ch.0 to Ch.3)

Transfer source memories

Internal Flash memory, external Flash memory, RAM

Transfer destination memories

RAM

Transfer source peripheral circuits

UART3, SPIA, QSPI, I2C, T16B, ADC12A

Transfer destination peripheral circuits

UART3, SPIA, QSPI, I2C, T16B

Figure 6.1.1 DMAC Configuration

DMA transfer control circuit

Peripheral circuit

DMA transfer request

Bus matrix

Flash memory,

RAM, etc.

MSTEN

Interrupt

control circuit

CPTRn

ENDIESETn

ENDIECLR

ERRIESET

ENDIFn

ERRIF

ERRIECLR

ACPTRn

CHNLS[4:0]

STATE[3:0]

MSTENSTA

RMSETn

RMCLRn

ENSETn

ENCLRn

PASETn

PACLRn

PRSETn

SWREQn

PRCLRn

CPU core

Peripheral circuit

DMA transfer request

• •

DMAC

Internal data bus

Ch.n

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6.2. Operations

6.2.1.

Initialization

The DMAC should be initialized with the procedure shown below.

1. Set the data structure base address to the DMACCPTR register.

2. Configure the data structure for the channels to be used.

- Set the control data.

- Set the transfer source end pointer.

- Set the transfer destination end pointer.

3. Set the DMACCFG.MSTEN bit to 1. (Enable DMAC)

4. Configure the DMACRMSET and DMACRMCLR registers.

(Configure masks for DMA transfer requests from peripheral circuits)

5. Configure the DMACENSET and DMACENCLR registers. (Enable channels used)

6. Configure the DMACPASET and DMACPACLR registers. (Select data structure used)

7. Configure the DMACPRSET and DMACPRCLR registers. (Set priorities)

8. Set the following registers when using the interrupt:

- Write 1 to the interrupt flags in the DMACENDIF and DMACERRIF registers. (Clear interrupt flags)

- Configures the DMACENDIESET/DMACENDIECLR and DMACERRIESET/DMACERRIECLR registers.

(Enable/disable interrupts)

9. Set the DMA request enable bits of the peripheral circuits that use DMA transfer to 1.

10. To issue a software DMA request to Ch.n, write 1 to the DMACSWREQ.SWREQn bit.

6.3.

Priority

If DMA requests are issued to two or more channels, the DMA transfers are performed in order from the highest- priority channel. The channel of which the priority level is set to 1 by the DMACPRSET.PRSETn bit has the highest priority. If two or more channels have been set to the same priority level, the smaller channel number takes precedence.

6.4. Data Structure

To perform DMA transfers, a data structure that contains basic transfer control information must be provided. The data structure consists of two blocks, primary data structure and alternate data structure, and one of them is used according to the DMA transfer mode. The data structure can be located at an arbitrary address in the RAM area by setting the base address to the DMAC- CPTR.CPTR[31:0] bits. The data structure for each channel consists of a transfer source end pointer, a transfer destination end pointer, and control data. An area of 16 bytes × 2 is allocated in the RAM for each channel. The whole size of the data structure and the alternate data structure base address depend on the number of channels implemented.

Table 6.4.1 Data Structure Size According to Number of Channels Implemented

Number of

channels

implemented

Data

structure

size

Primary data structure

base address

Alternate data structure

base address

32 bytes

DMACCPTR.CPTR[31:0] (CPTR[4:0] = 0x00)

DMACCPTR.CPTR[31:0] + 0x010

64 bytes

DMACCPTR.CPTR[31:0] (CPTR[5:0] = 0x00)

DMACCPTR.CPTR[31:0] + 0x020

3 to 4

128 bytes

DMACCPTR.CPTR[31:0] (CPTR[6:0] = 0x00)

DMACCPTR.CPTR[31:0] + 0x040

5 to 8

256 bytes

DMACCPTR.CPTR[31:0] (CPTR[7:0] = 0x00)

DMACCPTR.CPTR[31:0] + 0x080

9 to 16

512 bytes

DMACCPTR.CPTR[31:0] (CPTR[8:0] = 0x000)

DMACCPTR.CPTR[31:0] + 0x100

16 to 32

1,024 bytes

DMACCPTR.CPTR[31:0] (CPTR[9:0] = 0x000)

DMACCPTR.CPTR[31:0] + 0x200

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Alternate data structure Alternate data structure

Offset

Ch.31 (alternate)

Ch.31 (primary)

0x3f0

0x1f0

Ch.30 (alternate)

Ch.30 (primary)

0x3e0

0x1e0

Ch.29 (alternate)

Ch.29 (primary)

0x3d0

0x1d0

Ch.28 (alternate)

Ch.28 (primary)

0x3c0

0x1c0

Ch.27 (alternate)

Ch.27 (primary)

0x3b0

0x1b0

Ch.26 (alternate)

Ch.26 (primary)

0x3a0

0x1a0

Ch.25 (alternate)

Ch.25 (primary)

0x390

0x190

Ch.24 (alternate)

Ch.24 (primary)

0x380

0x180

Ch.23 (alternate)

Ch.23 (primary)

0x370

0x170

Ch.22 (alternate)

Ch.22 (primary)

0x360

0x160

Ch.21 (alternate)

Ch.21 (primary)

0x350

0x150

Ch.20 (alternate)

Ch.20 (primary)

0x340

0x140

Ch.19 (alternate)

Ch.19 (primary)

0x330

0x130

Ch.18 (alternate)

Ch.18 (primary)

0x320

0x120

Ch.17 (alternate)

Ch.17 (primary)

0x310

0x110

Ch.16 (alternate)

Ch.16 (primary)

0x300

0x100

Ch.15 (alternate)

Ch.15 (primary)

0x2f0

0x0f0

Ch.14 (alternate)

Ch.14 (primary)

0x2e0

0x0e0

Ch.13 (alternate)

Ch.13 (primary)

0x2d0

0x0d0

Ch.12 (alternate)

Ch.12 (primary)

0x2c0

0x0c0

Ch.11 (alternate)

Ch.11 (primary)

0x2b0

0x0b0

Ch.10 (alternate)

Ch.10 (primary)

0x2a0

0x0a0

Ch.9 (alternate)

Ch.9 (primary)

0x290

0x090

Ch.8 (alternate)

Ch.8 (primary)

0x280

0x080

Ch.7 (alternate)

Ch.7 (primary)

0x270

0x070

0x240

0x040

Ch.3 (alternate)

Ch.3 (primary)

Reserved

0x230

0x030

Ch.6 (alternate)

Ch.6 (primary)

0x260

0x060

Ch.5 (alternate)

Ch.5 (primary)

0x250

0x050

Ch.4 (alternate)

Ch.4 (primary)

Ch.2 (alternate)

Ch.2 (primary)

Control data

0x220

0x020

Ch.1 (alternate)

Ch.1 (primary)

Transfer destination end pointer

0x210

0x010

Ch.0 (alternate)

Ch.0 (primary)

Transfer source end pointer

0x200

0x000

Figure 6.4.1 Data Structure Address Map (when 32 channels are implemented)

Alternate data structure Alternate data structure

Transfer source end pointer

0x040

0x000

Offset

0x020

0x008

Ch.1 (alternate)

Ch.1 (primary)

0x050

0x010

0x004

Ch.0 (alternate)

Ch.0 (primary)

Ch.3 (alternate)

Ch.3 (primary)

Reserved

0x070

0x030

0x00c

Ch.2 (alternate)

Ch.2 (primary)

Control data

0x060

Base address set with the DMACCPTR register

Figure 6.4.2 Data Structure Address Map (when 4 channels are implemented)

The alternate data structure base address can be determined from the DMACACPTR.ACPTR[31:0] bits.

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6.4.1. Transfer Source End Pointer

Set the source data end address. The address of data to be transferred should be set as it is if the transfer source ad- dress is not incremented.

6.4.2. Transfer Destination End Pointer

Set the address to which the last transfer data is written. The address for writing transfer data should be set as it is if the transfer destination address is not incremented.

6.4.3. Control Data

Set the DMA transfer information. Figure 6.4.3.1 shows the constituent elements of the control data.

31 30 29 28

27 26 25 24

23 22 21 20

19 18 17 16

15 14 13 12

11 10 9 8

7 6 5 4

3 2 1 0

dst_inc

dst_size

src_inc

src_size

R_power n_minus_1

cycle_ctrl

Reserved

Figure 6.4.3.1 Constituent Elements of Control Data

dst_inc

Set the increment value of the transfer destination address. The setting value must be equal to or larger than the transfer data size when the address is incremented.

Table 6.4.3.1 Increment Value of Transfer Destination Address

dst_inc

Increment value

0x3

No increment

0x2

0x1

0x0

dst_size

Set the size of the data to be written to the transfer destination. It should be the same value as the src_size.

Table 6.4.3.2 Size of Data Written to Transfer Destination

dst_size

Data size

0x3

Reserved

0x2

Word

0x1

Halfword

0x0

Byte

src_inc

Set the increment value of the transfer source address. The setting value must be equal to or larger than the transfer data size when the address is incremented.

Table 6.4.3.3 Increment Value of Transfer Source Address

src_inc

Increment value

0x3

No increment

0x2

0x1

0x0

src_size

Set the size of the data to be read from the transfer source. It should be the same value as the dst_size.

Table 6.4.3.4 Size of Data Read from Transfer Source

src_size

Data size

0x3

Reserved

0x2

Word

0x1

Halfword

0x0

Byte

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R_power

Set the arbitration cycle during successive data transfer.

Arbitration cycle (2R) = 2

R_power

When the DMAC is performing a successive transfer, it suspends the data transfer at the cycle set with R_power. If DMA requests have been issued at that point, the DMAC re-arbitrates them according to their priorities and then performs a DMA transfer for the channel with the highest priority.

If the arbitration cycle setting value is larger than the number of successive data transfers, successive data transfers will not be suspended.

n_minus_1

Set the number of DMA transfers to be executed successively.

Number of successive transfers (N) = n_minus_1 + 1

When the set number of successive transfers has completed, a transfer completion interrupt occurs.

cycle_ctrl

Set the DMA transfer mode. For detailed information on each transfer mode, refer to Section 6.5, “DMA Transfer Mode.”

Table 6.4.3.5 DMA Transfer Mode

cycle_ctrl

DMA transfer mode

0x7

Peripheral scatter-gather transfer (for alternate data structure)

0x6

Peripheral scatter-gather transfer (for primary data structure)

0x5

Memory scatter-gather transfer (for alternate data structure)

0x4

Memory scatter-gather transfer (for primary data structure)

0x3

Ping-pong transfer

0x2

Auto-request transfer

0x1

Basic transfer

0x0

Stop

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6.5. DMA Transfer Mode

6.5.1. Basic Transfer

This is the basic DMA transfer mode. In this mode, DMA transfer starts when a DMA transfer request from a peripheral circuit or a software DMA request is issued, and it continues until it is completed for the set number of successive transfers or it is suspended at the arbitration cycle. To resume the DMA transfer suspended at the arbitration cycle, a DMA transfer request must be reissued. When the set number of successive transfers has completed, a transfer completion interrupt occurs.

Figure 6.5.1.1 Basic Transfer Operation Example (N = 8, 2R = 2)

6.5.2. Auto-Request Transfer

Similar to the basic transfer, DMA transfer starts when a DMA transfer request from a peripheral circuit or a soft- ware DMA request is issued, and it continues until it is completed for the set number of successive transfers or it is suspended at the arbitration cycle. The DMAC resumes the DMA transfer suspended at the arbitration cycle with- out a DMA transfer request being reissued. When the set number of successive transfers has completed, a transfer completion interrupt occurs

Figure 6.5.2.1 Auto-Request Transfer Operation Example (N = 8, 2R = 2)

DMA transfer 1

DMA transfer 2

DMA transfer request

DMA transfer 3

DMA transfer 4

DMA transfer 7

DMA transfer 8

DMA transfer operation

DMACENDIF.ENDIFn

DMA transfer request

DMA transfer 1

DMA transfer 2

DMA transfer request

DMA transfer 3

DMA transfer 4

DMA transfer 7

DMA transfer 8

DMA transfer operation

DMACENDIF.ENDIFn

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6.5.3. Ping-Pong Transfer

In ping-pong transfer mode, the DMAC performs basic transfers repeatedly while switching between the primary data structure and alternate data structure. The data structures are referred alternately, and DMA transfer is terminated when the control data with cycle_ctrl set to 0x0 is referred. A transfer completion interrupt occurs each time a transfer using a data structure is completed.

Transfer using primary data structure Transfer using alternate data structure

(cycle_ctrl = 0x3, 2R = 4, N = 6)

Task A

Task B

Task C

Task D

Task E

Termination

DMA transfer request

DMA transfer

completion interrupt

DMA transfer completion interrupt

DMA transfer

completion interrupt

(cycle_ctrl = 0x3, 2R = 4, N = 12)

(cycle_ctrl = 0x3, 2R = 4, N = 5)

(cycle_ctrl = 0x3, 2R = 2, N = 2)

(cycle_ctrl = 0x3, 2R = 4, N = 7)

(cycle_ctrl = 0x0)

Figure 6.5.3.1 Ping-Pong Transfer Operation Example

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DMA transfer procedure

1. Start data transfer by following the procedure shown in Section 6.2.1, “Initialization.” In Step 2 of

the initialization procedure, set Task A and Task B to the primary data structure and the alternate data structure, respectively.

2. Set Task C to the primary data structure after a DMA transfer completion interrupt has occurred

by Task A.

3. Set Task D to the alternate data structure when a DMA transfer completion interrupt has occurred

by Task B.

4. Repeat Steps 2 and 3.

5. Set cycle_ctrl to 0x0 after a DMA transfer completion interrupt has occurred by the next to last

task.

6. The DMA transfer is completed when a DMA transfer completion interrupt occurs by the last task.

6.5.4. Memory Scatter-Gather Transfer

In scatter-gather transfer mode, first the DMAC, using the primary data structure, copies a data structure from the data structure table, which has been prepared with multiple data structures included in advance, to the alternate data structure, and then it performs DMA transfer using the alternate data structure. The DMAC performs this operation repeatedly. By programming the transfer mode of the data structure located at the end of the table as a basic transfer, the DMA transfer can be terminated with a transfer completion interrupt. This mode requires a DMA transfer request only for starting the first data transfer. Subsequent data transfers are performed by auto-requests.

Reserved

Control data

Transfer destination end pointer

Transfer source end pointer

Reserved

Control data

Transfer destination end pointer

Transfer source end pointer

Reserved

Control data

Transfer destination end pointer

Transfer source end pointer

Reserved

Control data

Transfer destination end pointer

Transfer source end pointer

Data structure for Task A

Data structure for Task D

Data structure for Task C

Data structure for Task B

Figure 6.5.4.1 Example of Data Structure Table for Scatter-Gather Transfer

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Transfer using primary data structure Transfer using alternate data structure

(cycle_ctrl = 0x4, 2R = 4, N = 16)

Task A setting

Task A

Task B setting

Task B

Task C setting

Task C

Task D setting

Termination

DMA transfer request

Auto-request

Copy the data structure for

Task A to the alternate data structure.

DMA transfer

completion interrupt

(cycle_ctrl = 0x5, 2R = 4, N = 3)

(cycle_ctrl = 0x5, 2R = 2, N = 8)

(cycle_ctrl = 0x5, 2R = 8, N = 5)

Copy the data structure for

Task B to the alternate data structure.

(cycle_ctrl = 0x1, 2R = 4, N = 4)

Auto-request

Copy the data structure for Task C to the alternate data structure

Copy the data structure for Task D to the alternate data structure.

Figure 6.5.4.2 Memory Scatter-Gather Transfer Operation Example

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DMA transfer procedure

1. Configure the data structure table for scatter-gather transfer.

Set the cycle_ctrl for the last task to 0x1 and those for other tasks to 0x5.

2. Start data transfer by following the procedure shown in Section 6.2.1, “Initialization.” In Step 2 of

the initialization procedure, configure the primary data structure with the control data shown below.

Transfer source end pointer = Data structure table end address Transfer destination end pointer = Alternate data structure end address dst_inc = 0x2 dst_size = 0x2 src_inc = 0x2 src_size = 0x2 R_power = 0x2 n_minus_1 = Number of tasks × 4 - 1 cycle_ctrl = 0x4

3. The DMA transfer is completed when a DMA transfer completion interrupt occurs.

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6.5.5. Peripheral Scatter-Gather Transfer

In memory scatter-gather transfer mode, the second and subsequent DMA transfers are performed by auto-requests. On the other hand, in peripheral scatter-gather transfer mode, all DMA transfers are performed by a DMA transfer request issued by a peripheral circuit or a software DMA request.

Transfer using primary data structure

Transfer using alternate data structure

(cycle_ctrl = 0x6, 2R = 4, N = 16)

Task A setting

Task A

Task B setting

Task B

Task C setting

Task C

Task D setting

Task D

DMA transfer request

Copy the data structure for

Task A to the alternate data structure..

DMA transfer

completion interrupt

(cycle_ctrl = 0x7, 2R = 4, N = 3)

(cycle_ctrl = 0x7, 2R = 2, N = 8)

(cycle_ctrl = 0x7, 2R = 8, N = 5)

Copy the data structure for Task B to the alternate data structure.

(cycle_ctrl = 0x1, 2R = 4, N = 4)

DMA transfer request

Copy the data structure for

Task C to the alternate data structure

Copy the data structure for Task D to the alternate data structure.

Data transfer using the alternate data structure starts

immediately after data transfer using the primary data structure has completed without arbitration.

DMA transfer request

Figure 6.5.5.1 Peripheral Scatter-Gather Transfer Operation Example

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DMA transfer procedure

1. Configure the data structure table for scatter-gather transfer.

Set the cycle_ctrl for the last task to 0x1 and those for other tasks to 0x7.

2. Start data transfer by following the procedure shown in Section 6.2.1, “Initialization.” In Step 2 of

the initialization procedure, configure the primary data structure with the control data shown below.

3. Issue a DMA transfer request in each task using a peripheral circuit or via software.

4. The DMA transfer is completed when a DMA transfer completion interrupt occurs.

6.6. DMA Transfer Cycle

A DMA transfer requires several clock cycles to execute. Figure 6.6.1 shows a detailed DAM transfer cycle. Note that the number of clock cycles for a DMA transfer may be increased due to a conflict with an access from the CPU or the Flash bus access cycle setting.

Figure 6.6.1 DMA Transfer Cycle

6.7. Interrupts

The DMAC has a function to generate the interrupts shown in Table 6.7.1.

Table 6.7.1 DMAC Interrupt Function

Interrupt

Interrupt flag

Set condition

Clear condition

DMA transfer completion

DMACENDIF.ENDIFn

When DMA transfers for a set number of successive transfers have completed

Writing 1 DMA transfer error

DMACERRIF.ERRIF

When an AHB bus error has occurred

Writing 1

The DMAC provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter.

IDLE

rsp

rdp

IDLE

rsp

SYSCLK

Transfer cycle

DMA transfer request

rc: Read control data

rsp: Read transfer source end pointer

rdp: Read transfer destination end pointer

RD: Read data from transfer source

WD: Write data to transfer destination wc: Write control data

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6.8. Control Registers

DMAC Status Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACSTAT

31–24 –

0x00 – R

–

23–21 –

0x0 – R

20–16 CHNLS[4:0]

* H0 R

* Number of channels implemented - 1

15–8 –

0x00 – R

–

7–4 STATE[3:0]

0x0

H0 R

3–1 –

0x0 – R 0 MSTENSTAT

H0 R

Bits 31–21 Reserved

Bits 20–16 CHNLS[4:0]

These bits show the number of DMAC channels implemented in this IC.

Number of channels implemented = CHNLS + 1

Bits 15–8 Reserved

Bits 7–4 STATE[3:0]

These bits indicates the DMA transfer status.

Table 6.8.1 DMA Transfer Status

DMACSTAT.STATE[3:0] bits

DMA transfer status

0xf–0xbf

Reserved

0xa

Peripheral scatter-gather transfer is in progress.

0x9

Transfer has completed.

0x8

Transfer has been suspended.

0x7

Control data is being written.

0x6

Standby for transfer request to be cleared.

0x5

Transfer data is being written.

0x4

Transfer data is being read.

0x3

Transfer destination end pointer is being read.

0x2

Transfer source end pointer is being read.

0x1

Control data is being read.

0x0

Idle

Bits 3–1 Reserved

Bit 0 MSTENSTAT

This bit indicates the DMA controller status.

1 (R): DMA controller is operating. 0 (R): DMA controller is idle.

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DMAC Configuration Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACCFG

31–24 –

0x00 – R

–

23–16 –

0x00 – R

15–8 –

0x00 – R

–

7–1 –

0x00 – R 0 MSTEN

– – W

Bits 31–1 Reserved

Bit 0 MSTEN

This bit enables the DMA controller.

1 (W): Enable 0 (W): Disable

DMAC Control Data Base Pointer Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACCPTR

31–0 CPTR[31:0]

0x0000

0000

R/W

–

Bits 31–0 CPTR[31:0]

These bits set the leading address of the data structure. Depending on the number of channels implemented, low-order bits are configured for read only.

Table 6.8.2 CPTR Writable/Read-Only Bits Depending On Number of Channel Implemented

Number of channel

implemented

Writable bits

Read-only bits

CPTR[31:5]

CPTR[4:0]

CPTR[31:6]

CPTR[5:0]

3–4

CPTR[31:7]

CPTR[6:0]

5–8

CPTR[31:8]

CPTR[7:0]

9–16

CPTR[31:9]

CPTR[8:0]

17–32

CPTR[31:10]

CPTR[9:0]

DMAC Alternate Control Data Base Pointer Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACACPTR

31–0 ACPTR[31:0]

– H0 R

–

Bits 31–0 ACPTR[31:0]

These bits show the alternate data structure base address.

DMAC Software Request Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACSWREQ

31–0 SWREQ[31:0]

– – W

–

Bits 31–0 SWREQ [31:0]

These bits issue a software DMA transfer request to each channel.

1 (W): Issue a software DMA transfer request 0 (W): Ineffective

Each bit corresponds to a DMAC channel (e.g. bit n corresponds to Ch.n). The high-order bits for the unimplemented channels are ineffective.

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DMAC Request Mask Set Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACRMSET

31–0 RMSET[31:0]

0x0000

0000

R/W

–

Bits 31–0 RMSET[31:0]

These bits mask DMA transfer requests from peripheral circuits.

1 (W): Mask DMA transfer requests from peripheral circuits 0 (W): Ineffective 1 (R): DMA transfer requests from peripheral circuits have been disabled. 0 (R): DMA transfer requests from peripheral circuits have been enabled.

Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective.

DMAC Request Mask Clear Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACRMCLR

31–0 RMCLR[31:0]

– – W

–

Bits 31–0 RMCLR[31:0]

These bits cancel the mask state of DMA transfer requests from peripheral circuits

1 (W): Cancel mask state of DMA transfer requests from peripheral circuits

(The DMACRMSET register is cleared to 0.)

0 (W): Ineffective

Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective.

DMAC Enable Set Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACENSET

31–0 ENSET[31:0]

0x0000

0000

R/W

–

Bits 31–0 ENSET[31:0]

These bits enable each DMAC channel.

1 (W): Enable DMAC channel 0 (W): Ineffective 1 (R): Enabled 0 (R): Disabled

These bits are cleared after the DMA transfer has completed. Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective.

DMAC Enable Clear Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACENCLR

31–0 ENCLR[31:0]

– – W

–

Bits 31–0 ENCLR[31:0]

These bits disable each DMAC channel.

1 (W): Disable DMAC channel (The DMACENSET register is cleared to 0.) 0 (W): Ineffective

Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective.

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DMAC Primary-Alternate Set Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACPASET

31–0 PASET[31:0]

0x0000

0000

R/W

–

Bits 31–0 PASET[31:0]

These bits enable the alternate data structures.

1 (W): Enable alternate data structure 0 (W): Ineffective 1 (R): The alternate data structure has been enabled. 0 (R): The primary data structure has been enabled.

Each bit corresponds to a DMAC channel. The high-order bits for the

unimplemented channels are ineffective.

DMAC Primary-Alternate Clear Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACPACLR

31–0 PACLR[31:0]

– – W

–

Bits 31–0 PACLR[31:0]

These bits disable the alternate data structures.

1 (W): Disable alternate data structure (The DMACPASET register is cleared to 0.) 0 (W): Ineffective

Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective.

DMAC Priority Set Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACPRSET

31–0 PRSET[31:0]

0x0000

0000

R/W

–

Bits 31–0 PRSET[31:0]

These bits increase the priority of each channel.

1 (W): Increase priority 0 (W): Ineffective 1 (R): Priority = High 0 (R): Priority = Normal

Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective.

DMAC Priority Clear Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACPRCLR

31–0 PRCLR[31:0]

– – W

–

Bits 31–0 PRCLR[31:0]

These bits decrease the priority of each channel.

1(W): Decrease priority (The DMACPRSET register is cleared to 0.) 0 (W): Ineffective

Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective.

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DMAC Error Interrupt Flag Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACERRIF

31–24 –

0x00 – R

–

23–16 –

0x00 – R

15–8 –

0x00 – R

7–1 –

0x00 – R 0 ERRIF

R/W

Cleared by writing 1.

Bits 31–1 Reserved

Bit 0 ERRIF

This bit indicates the DMAC error interrupt cause occurrence status.

1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective

DMAC Transfer Completion Interrupt Flag Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACENDIF

31–0 ENDIF[31:0]

0x0000

0000

R/W

Cleared by writing 1.

Bits 31–0 ENDIF[31:0]

These bits indicate the DMA transfer completion interrupt cause occurrence status of each DMAC channel.

1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective

Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective.

DMAC Transfer Completion Interrupt Enable Set Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACENDIESET

31–0 ENDIESET[31:0]

0x0000

0000

R/W

–

Bits 31–0 ENDIESET[31:0]

These bits enable DMA transfer completion interrupts to be generated from each DMAC channel.

1 (W): Enable interrupt 0 (W): Ineffective 1 (R): Interrupt has been enabled. 0 (R): Interrupt has been disabled.

Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective.

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DMAC Transfer Completion Interrupt Enable Clear Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACENDIECLR

31–0 ENDIECLR[31:0]

– – W

–

Bits 31–0 ENDIECLR[31:0]

These bits disable DMA transfer completion interrupts to be generated from each DMAC channel.

1 (W): Disable interrupt (The DMACENDIESET register is cleared to 0.) 0 (W): Ineffective

Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective.

DMAC Error Interrupt Enable Set Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACERRIESET

31–24 –

0x00 – R

–

23–16 –

0x00 – R

15–8 –

0x00 – R

7–1 –

0x00 – R 0 ERRIESET

R/W

Bits 31–1 Reserved

Bit 0 ERRIESET

This bit enables DMA error interrupts.

1 (W): Enable interrupt 0 (W): Ineffective 1 (R): Interrupt has been enabled. 0 (R): Interrupt has been disabled.

DMAC Error Interrupt Enable Clear Register

Bit

Bit name

Initial

Reset

R/W

Remarks

DMACERRIECLR

31–24 –

0x00 – R

–

23–16 –

0x00 – R

15–8 –

0x00 – R

7–1 –

0x00 – R 0 ERRIECLR

– – W

Bits 31–1 Reserved

Bit 0 ERRIECLR

This bit disables DMA error interrupts.

1 (W): Disable interrupt (The DMACERRIESET register is cleared to 0.) 0 (W): Ineffective

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7. I/O Ports (PPORT)

7.1. Overview

PPORT controls the I/O ports. The main features are outlined below.

• Allows port-by-port function configurations.

- Each port can be configured with or without a pull-up or pull-down resistor.

- Each port can be configured with or without a chattering filter.

- Allows selection of the function (general-purpose I/O port (GPIO) function, up to four peripheral

I/O functions) to be assigned to each port.

• Ports, except for those shared with debug pins, are initially placed into Hi-Z state. (No current passes

through the pin during this Hi-Z state.)

Note: ‘x’, which is used in the port names Pxy, register names, and bit names, refers to a port group (x= 0, 1, 2, ··· , d) and ‘y’ refers to a port number (y = 0, 1, 2, ··· , 7).

Figure 7.1.1 shows the configuration of PPORT.

Table 7.1.1 Port Configuration of S1C31D50

Item S1C31D50

Port groups included

Ports with general-purpose I/O function (GPIO)

P0[7:0], P1[7:0], P2[7:0], P3[7:0], P4[7:0], P5[7:0], P6[7:0], P7[7:0] P8[7:0],P9[5:0],PA[6:0],PD[5:0]

Ports with interrupt function

P0[7:0], P1[7:0], P2[7:0], P3[7:0], P4[7:0], P5[7:0], P6[7:0].P7[7:0] P8[7:0],P9[5:0],PA[6:0]

Ports for debug function

PD[1:0]

Figure 7.1.1 PPORT Configuration

KRSTCFG[1:0]

CLKSRC[1:0]

CLKDIV[3:0]

Clock

generator

CPU core

System reset

controller

DBRUN

I/O

cell

Chattering

filter

Interrupt

control circuit

Key-entry

reset control

circuit

Pxy

PPORT

GPIO/

peripheral I/O

function

switching

circuit

Internal data bus

Pxy

I/O cell

control signal

Output signal

General-purpose I/O control

GPIO function

Input signal

Key-entry

reset signal

Peripheral I/O function 0 I/O control

Peripheral I/O function 1 I/O control

Peripheral I/O function 2 I/O control

Peripheral I/O function 3 I/O control

Exist only in the ports that supports the interrupt function.

PxOUTy

PxyMUX[1:0]

PxOENy

PxIENy

PxPDPUy

PxRENy

PxINy

PxSELy

PxCHATENy

PxEDGEy

PxIFy

PxIEy

PxINT

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7.2. I/O Cell Structure and Functions

Figure 7.2.1 shows the I/O cell Configuration.

Figure 7.2.1 I/O Cell Configuration

Refer to “Pin Descriptions” in the “Overview” chapter for the cell type, either the over voltage tolerant fail-safe type I/O cell or the Bold I/O cell, included in each port.

7.2.1. Schmitt Input

The input functions are all configured with the Schmitt interface level. When a port is set to input disable status (PPORTPxIOEN.PxIENy bit = 0), unnecessary current is not consumed if the Pxy pin is placed into floating status.

7.2.2. Over Voltage Tolerant Fail-Safe Type I/O Cell

The over voltage tolerant fail-safe type I/O cell allows interfacing without passing unnecessary current even if a voltage exceeding VDD is applied to the port. Also unnecessary current is not consumed when the port is externally biased without supplying VDD. However, be sure to avoid applying a voltage exceeding the recommended maxi- mum operating power supply voltage to the port.

7.2.3. Pull-Up/Pull-Down

The GPIO port has a pull-up/pull-down function. Either pull-up or pull-down may be selected for each port individually. This function may also be disabled for the port that does not require pulling up/down. When the port level is switched from low to high through the pull-up resistor included in the I/O cell or from high to low through the pull-down resistor, a delay will occur in the waveform rising/falling edge depending on the time constant by the pull-up/pull-down resistance and the pin load capacitance. The rising/falling time is commonly determined by the following equation:

tPR = -RINU × (CIN + CBOARD) × ln(1 - VT+/VDD) (Eq. 7.1) tPF = -RIND × (CIN + CBOARD) × ln(1 - VT-/VDD)

Where

tPR: Rising time (port level = low → high) [second] tPF: Falling time (port level = high → low) [second] VT+: High level Schmitt input threshold voltage [V] VT-: Low level Schmitt input threshold voltage [V] RINU/RIND: Pull-up/pull-down resistance [W] CIN: Pin capacitance [F] CBOARD: Parasitic capacitance on the board [F]

Pull-up/down

control

Analog signal

control

Pull-

up/down

Analog signal

control

Pull-up/down

Control signal

Input signal

Input control signal

Output signal

Output control signal

Analog signal

Analog control signal

INU

IND

* No diode is connected at the VDD

Pull-up/down

Control signal

Input signal

Input control signal

Output signal

Output control signal

Analog signal

Analog control signal

INU

IND

Over voltage tolerant fail-safe type I/O cell

Standard I/O cell

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7.2.4. CMOS Output and High Impedance State

The I/O cells except for analog output can output signals in the VDD and VSS levels. Also the GPIO ports may be put into high-impedance (Hi-Z) state.

7.3. Clock Settings

7.3.1. PPORT Operating Clock

When using the chattering filter for entering external signals to PPORT, the PPORT operating clock CLK_PPORT must be supplied to PPORT from the clock generator. The CLK_PPORT supply should be controlled as in the procedure shown below.

1. Enable the clock source in the clock generator if it is stopped (refer to “Clock Generator” in the

“Power Supply, Reset, and Clocks” chapter).

2. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)

3. Set the following PPORTCLK register bits:

- PPORTCLK.CLKSRC[1:0] bits (Clock source selection)

- PPORTCLK.CLKDIV[3:0] bits (Clock division ratio selection = Clock frequency setting)

4. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection)

Settings in Step 3 determine the input sampling time of the chattering filter.

7.3.2. Clock Supply in SLEEP Mode

When using the chattering filter function during SLEEP mode, the PPORT operating clock CLK_PPORT must be configured so that it will keep suppling by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_PPORT clock source. If the CLGOSC.xxxxSLPC bit for the CLK_PPORT clock source is 1, the CLK_PPORT clock source is deactivated during SLEEP mode and it disables the chattering filter function regardless of the PPORTPxCHATEN.Px- CHATENy bit setting (chattering filter enabled/disabled).

7.3.3. Clock Supply During Debugging

The CLK_PPORT supply during debugging should be controlled using the PPORTCLK.DBRUN bit. The CLK_PPORT supply to PPORT is suspended when the CPU enters debug state if the PPORTCLK.DBRUN bit = 0. After the CPU returns to normal operation, the CLK_PPORT supply resumes. The PPORT chattering filter stops operating when the CLK_PPORT supply is suspended. If the chattering filter is enabled in PPORT, the input port function is also deactivated. However, the control registers can be altered. If the PPORTCLK.DBRUN bit = 1, the CLK_PPORT supply is not suspended and the chattering filter will keep operating in a debug state.

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7.4.

Operations

7.4.1.

Initialization

After a reset, the ports except for the debugging function are configured as shown below.

• Port input: Disabled

• Port output: Disabled

• Pull-up: Off

• Pull-down: Off

• Port pins: High impedance state

• Port function: Configured to GPIO

This status continues until the ports are configured via software. The debugging function ports are configured for debug signal input/output.

Initial settings when using a port for a peripheral I/O function

When using the Pxy port for a peripheral I/O function, perform the following software initial settings:

1. Set the following PPORTPxIOEN register bits:

- Set the PPORTPxIOEN.PxIENy bit to 0. (Disable input)

- Set the PPORTPxIOEN.PxOENy bit to 0. (Disable output)

2. Set the PPORTPxMODSEL.PxSELy bit to 0. (Disable peripheral I/O function)

3. Initialize the peripheral circuit that uses the pin.

4. Set the PPORTPxFNCSEL.PxyMUX[1:0] bits. (Select peripheral I/O function)

5. Set the PPORTPxMODSEL.PxSELy bit to 1. (Enable peripheral I/O function)

For the list of the peripheral I/O functions that can be assigned to each port of this IC, refer to “Control Register and Port Function Configuration of this IC.” For the specific information on the peripheral I/O functions, refer to the respective peripheral circuit chapter.

Initial settings when using a port as a general-purpose output port (only for the ports with GPIO function)

When using the Pxy port pin as a general-purpose output pin, perform the following software initial settings:

1. Set the PPORTPxIOEN.PxOENy bit to 1. (Enable output)

2. Set the PPORTPxMODSEL.PxSELy bit to 0. (Enable GPIO function)

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Initial settings when using a port as a general-purpose input port (only for the ports with GPIO function)

When using the Pxy port pin as a general-purpose input pin, perform the following software initial settings:

1. Write 0 to the PPORTPxINTCTL.PxIEy bit. * (Disable interrupt)

2. When using the chattering filter, configure the PPORT operating clock (see “PPORT Operating

Clock”) and set the PPORTPxCHATEN.PxCHATENy bit to 1. * When the chattering filter is not used, set the PPORTPxCHATEN.PxCHATENy bit to 0 (supply of the PPORT operating clock is not required).

3. Configure the following PPORTPxRCTL register bits when pulling up/down the port using the

internal pull-up or down resistor:

- PPORTPxRCTL.PxPDPUy bit (Select pull-up or pull-down resistor)

- Set the PPORTPxRCTL.PxRENy bit to 1. (Enable pull-up/down)

Set the PPORTPxRCTL.PxRENy bit to 0 if the internal pull-up/down resistors are not used.

4. Set the PPORTPxMODSEL.PxSELy bit to 0. (Enable GPIO function)

5. Configure the following bits when using the port input interrupt: *

- Write 1 to the PPORTPxINTF.PxIFy bit. (Clear interrupt flag)

- PPORTPxINTCTL.PxEDGEy bit (Select interrupt edge

(input rising edge/falling edge))

- Set the PPORTPxINTCTL.PxIEy bit to 1. (Enable interrupt)

6. Set the following PPORTPxIOEN register bits:

- Set the PPORTPxIOEN.PxOENy bit to 0. (Disable output)

- Set the PPORTPxIOEN.PxIENy bit to 1. (Enable input)

* Steps 1 and 5 are required for the ports with an interrupt function. Step 2 is required for the ports with a chattering filter function.

Table 7.4.1.1 lists the port status according to the combination of data input/output control and pull-up/down control.

Table 7.4.1.1 GPIO Port Control List

PPORTPxIOEN.

PxIENy bit

PPORTPxIOEN.

PxOENy bit

PPORTPxRCTL.

PxRENy bit

PPORTPxRCTL.

PxPDPUy bit

Input

Output

Pull-up/pull-down

condition

0 0 0 ×

Disabled

Off (Hi-Z) *1

0 0 1 0 Disabled

Pulled down

0 0 1 1 Disabled

Pulled up

1 0 0 ×

Enabled

Disabled

Off (Hi-Z) *2

1 0 1 0 Enabled

Disabled

Pulled down

1 0 1 1 Enabled

Disabled

Pulled up

0 1 0 ×

Disabled

Enabled

Off

0 1 1

Disabled

Enabled

Off

0 1 1

Disabled

Enabled

Off

1 1 1 0 Enabled

Enabled

Off

1 1 1 1 Enabled

Enabled

Off

*1: Initial status. Current does not flow if the pin is placed into floating status. *2: Use of the pull-up or pull-down function is recommended, as undesired current will flow if the port input is set to floating status.

Note:

If the PPORTPxMODSEL.PxSELy bit for the port without a GPIO function is set to 0, the port goes into initial status (refer to “Initial Settings”). The GPIO control bits are configured to a read- only bit always read out as 0.

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7.4.2. Port Input/Output Control

Peripheral I/O function control

The port for which a peripheral I/O function is selected is controlled by the peripheral circuit. For more information, refer to the respective peripheral circuit chapter.

Setting output data to a GPIO port

Write data (1 = high output, 0 = low output) to be output from the Pxy pin to the PPORTPxDAT.PxOUTy bit.

Reading input data from a GPIO port

The data (1 = high input, 0 = low input) input from the Pxy pin can be read out from the PPORTPxDAT.PxINy bit.

Chattering filter function

Some ports have a chattering filter function and it can be controlled in each port. This function is enabled by setting the PPORTPxCHATEN.PxCHATENy bit to 1. The input sampling time to remove chattering is deter- mined by the CLK_PPORT frequency configured using the PPORTCLK register in common to all ports. The chattering filter removes pulses with a shorter width than the input sampling time.

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Make sure the Pxy port interrupt is disabled before altering the PPORTCLK register and PPORTPxCHATEN. PxCHATENy bit settings. A Pxy port interrupt may erroneously occur if these settings are altered in an interrupt enabled status. Furthermore, enable the interrupt after a lapse of four or more CLK_PPORT cycles from enabling the chattering filter function. If the clock generator is configured so that it will supply CLK_PPORT to PPORT in SLEEP mode, the chattering filter of the port will function even in SLEEP mode. If CLK_PPORT is configured to stop in SLEEP mode, PPORT inactivates the chattering filter during SLEEP mode to input pin status transitions directly to itself.

Key-entry reset function

This function issues a reset request when low-level pulses are input to all the specified ports simultaneously. Make the following settings when using this function:

1. Configure the ports to be used for key-entry reset as general-purpose input ports (refer to

“Initial settings when using a port as a general-purpose input port (only for the ports with GPIO function)”).

2. Configure the input pin combination for key-entry reset using the PPORTCLK.KRSTCFG[1:0] bits.

Note:

When enabling the key-entry reset function, be sure to configure the port pins to be used for it as general-purpose input pins before setting the PPORTCLK.KRSTCFG[1:0] bits.

PPORT issues a reset request immediately after all the input pins specified by the PPORTCLK.KRSTCFG[1:0] are set to a low level if the chattering filter function is disabled (initial status). To issue a reset request only when low-level signals longer than the time configured are input, enable the chattering filter function for all the ports used for key-entry reset. The pins configured for key-entry reset can also be used as general-purpose input pins.

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7.5. Interrupts

When the GPIO function is selected for the port with an interrupt function, the port input interrupt function can be used.

Table 7.5.1 Port Input Interrupt Function

Interrupt

Interrupt flag

Set condition

Clear condition

Port input

interrupt

PPORTPxINTF.PxIFy

Rising or falling edge of the input signal

Writing 1

PPORTINTFGRP.PxINT

Setting an interrupt ﬂag in the port group

Clearing PPORTPxINTF.PxIFy

Interrupt edge selection

Port input interrupts will occur at the falling edge of the input signal when setting the PPORTPxINTCTL. PxEDGEy bit to 1, or the rising edge when setting to 0.

Interrupt enable

PPORT provides interrupt enable bits (PPORTPxINTCTL.PxIEy bit) corresponding to each interrupt flag. An interrupt request is sent to the CPU core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter.

Interrupt check in port group unit

When interrupts are enabled in two or more port groups, check the PPORTINTFGRP.PxINT bit in the interrupt handler first. It helps minimize the handler codes for finding the port that has generated an interrupt. If this bit is set to 1, an interrupt has occurred in the port group. Next, check the PPORTPxINTF.PxIFy bit set to 1 in the port group to determine the port that has generated an interrupt. Clearing the PPORTPxINTF.PxIFy bit also clears the PPORTINTFGRP.PxINT bit. If the port is set to interrupt disabled status by the PPORTPxINTCTL. PxIEy bit, the PPORTINTFGRP.PxINT bit will not be set even if the PPORTPxINTF.PxIFy bit is set to 1.

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7.6. Control Registers

This section describes the same control registers of all port groups as a single register. For the register and bit con- figurations in each port group and their initial values, refer to “Control Register and Port Function Configuration of this IC.”

Px Port Data Register

Bit

Bit name

Initial

Reset

R/W

Remarks

PPORTPxDAT

15–8 PxOUT[7:0]

0x00

R/W

–

7–0 PxIN[7:0]

0x00

H0 R

*1: This register is effective when the GPIO function is selected. *2: The bit configuration differs depending on the port group. *3: The initial value may be changed by the port.

Bits 15–8 PxOUT[7:0]

These bits are used to set data to be output from the GPIO port pins.

1 (R/W): Output high level from the port pin 0 (R/W): Output low level from the port pin

When output is enabled (PPORTPxIOEN.PxOENy bit = 1), the port pin outputs the data set here. Al- though data can be written when output is disabled (PPORTPxIOEN.PxOENy bit =

0), it does not affect the pin status. These bits do not affect the outputs when the port is used as a peripheral I/O function.

Bits 7–0 PxIN[7:0]

The GPIO port pin status can be read out from these bits.

1 (R): Port pin = High level 0 (R): Port pin = Low level

The port pin status can be read out when input is enabled (PPORTPxIOEN.PxIENy bit = 1). When in- put is disabled (PPORTPxIOEN.PxIENy bit = 0), these bits are always read as 0. When the port is used for a peripheral I/O function, the input value cannot be read out from these bits.

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Px Port Enable Register

Bit

Bit name

Initial

Reset

R/W

Remarks

PPORTPxIOEN

15–8 PxIEN[7:0]

0x00

R/W

–

7–0 PxOEN[7:0]

0x00

R/W

*1: This register is effective when the GPIO function is selected. *2: The bit configuration differs depending on the port group.

Bits 15–8 PxIEN[7:0]

These bits enable/disable the GPIO port input.

1 (R/W): Enable (The port pin status is input.) 0 (R/W): Disable (Input data is fixed at 0.)

When both data output and data input are enabled, the pin output status controlled by this IC can be read. These bits do not affect the input control when the port is used as a peripheral I/O function.

Bits 7–0 PxOEN[7:0]

These bits enable/disable the GPIO port output.

1 (R/W): Enable (Data is output from the port pin.) 0 (R/W): Disable (The port is placed into Hi-Z.)

These bits do not affect the output control when the port is used as a peripheral I/O function.

Px Port Pull-up/down Control Register

Bit

Bit name

Initial

Reset

R/W

Remarks

PPORTPxRCTL

15–8 PxPDPU[7:0]

0x00

R/W

–

7–0 PxREN[7:0]

0x00

R/W

*1: This register is effective when the GPIO function is selected. *2: The bit configuration differs depending on the port group.

Bits 15–8 PxPDPU[7:0]

These bits select either the pull-up resistor or the pull-down resistor when using a resistor built into the port.

1 (R/W): Pull-up resistor 0 (R/W): Pull-down resistor

The selected pull-up/down resistor is enabled when the PPORTPxRCTL.PxRENy bit = 1.

Bits 7–0 PxREN[7:0]

These bits enable/disable the port pull-up/down control.

1 (R/W): Enable (The built-in pull-up/down resistor is used.) 0 (R/W): Disable (No pull-up/down control is performed.)

Enabling this function pulls up or down the port when output is disabled (PPORTPxIOEN.PxOENy bit = 0). When output is enabled (PPORTPxIOEN.PxOENy bit = 1), the PPORTPxRCTL.PxRENy bit setting is ineffective regardless of how the PPORTPxIOEN.PxIENy bit is set and the port is not pulled up/down. These bits do not affect the pull-up/down control when the port is used as a peripheral I/O function.

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Px Port Interrupt Flag Register

Bit

Bit name

Initial

Reset

R/W

Remarks

PPORTPxINTF

15–8 –

0x00 – R

–

7–0 PxIF[7:0]

0x00

R/W

Cleared by writing 1.

*1: This register is effective when the GPIO function is selected. *2: The bit configuration differs depending on the port group.

Bits 15–8 Reserved

Bits 7–0 PxIF[7:0]

These bits indicate the port input interrupt cause occurrence status.

1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective

Px Port Interrupt Control Register

Bit

Bit name

Initial

Reset

R/W

Remarks

PPORTPxINTCTL

15–8 PxEDGE[7:0]

0x00

R/W

–

7–0 PxIE[7:0]

0x00

R/W

*1: This register is effective when the GPIO function is selected. *2: The bit configuration differs depending on the port group.

Bits 15–8 PxEDGE[7:0]

These bits select the input signal edge to generate a port input interrupt.

1 (R/W): An interrupt will occur at a falling edge. 0 (R/W): An interrupt will occur at a rising edge.

Bits 7–0 PxIE[7:0]

These bits enable port input interrupts.

1 (R/W): Enable interrupts 0 (R/W): Disable interrupts

Note:

To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts.

Px Port Chattering Filter Enable Register

Bit

Bit name

Initial

Reset

R/W

Remarks

PPORTPxCHATEN

15–8 –

0x00 – R

–

7–0 PxCHATEN[7:0]

0x00

R/W

*1: The bit configuration differs depending on the port group.

Bits 15–8 Reserved

Bits 7–0 PxCHATEN[7:0]

These bits enable/disable the chattering filter function.

1 (R/W): Enable (The chattering filter is used.) 0 (R/W): Disable (The chattering filter is bypassed.)

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Px Port Mode Select Register

Bit

Bit name

Initial

Reset

R/W

Remarks

PPORTPxMODSEL

15–8 –

0x00 – R

–

7–0 PxSEL[7:0]

0x00

R/W

*1: The bit configuration differs depending on the port group. *2: The initial value may be changed by the port.

Bits 15–8 Reserved Bits 7–0 PxSEL[7:0]

These bits select whether each port is used for the GPIO function or a peripheral I/O function.

1 (R/W): Use peripheral I/O function 0 (R/W): Use GPIO function

Px Port Function Select Register

Bit

Bit name

Initial

Reset

R/W

Remarks

PPORTPxFNCSEL

15–14 Px7MUX[1:0]

0x0

R/W

–

13–12 Px6MUX[1:0]

0x0

R/W

11–10 Px5MUX[1:0]

0x0

R/W

9–8 Px4MUX[1:0]

0x0

R/W

7–6 Px3MUX[1:0]

0x0

R/W

5–4 Px2MUX[1:0]

0x0

R/W

3–2 Px1MUX[1:0]

0x0

R/W

1–0 Px0MUX[1:0]

0x0

R/W

*1: The bit configuration differs depending on the port group. *2: The initial value may be changed by the port.

Bits 15–14 Px7MUX[1:0]

: :

Bits 1–0 Px0MUX[1:0]

These bits select the peripheral I/O function to be assigned to each port pin.

Table 7.6.1 Selecting Peripheral I/O Function

PPORTPxFNCSEL.PxyMUX[1:0] bits

Peripheral I/O function

0x3

Function 3

0x2

Function 2

0x1

Function 1

0x0

Function 0

This selection takes effect when the PPORTPxMODSEL.PxSELy bit = 1.

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P Port Clock Control Register

Bit

Bit name

Initial

Reset

R/W

Remarks

PPORTCLK

15–9 –

0x00 – R

–

DBRUN

R/WP

7–4 CLKDIV[3:0]

0x0

R/WP

3–2 reserved

0x0

H0 R 1–0 CLKSRC[1:0]

0x0

R/WP

Bits 15–9 Reserved

Bit 8 DBRUN

This bit sets whether the PPORT operating clock is supplied during debugging or not.

1 (R/WP): Clock supplied during debugging 0 (R/WP): No clock supplied during debugging

Bits 7–4 CLKDIV[3:0]

These bits select the division ratio of the PPORT operating clock (chattering filter clock).

Bits 3–2 Reserved

Bits 1–0 CLKSRC[1:0]

These bits select the clock source of PPORT (chattering filter). The PPORT operating clock should be configured by selecting the clock source using the PPORT- CLK.CLKSRC[1:0] bits and the clock division ratio using the PPORTCLK.CLKDIV[3:0] bits as shown in Table 7.6.2. These settings determine the input sampling time of the chattering filter.

Table 7.6.2 Clock Source and Division Ratio Settings

PPORTCLK.CLKDIV[3:0]

bits

PPORTCLK.CLKSRC[1:0] bits

0x0

0x1

0x2

0x3

IOSC

OSC1

OSC3

EXOSC

0xf

1/32,768

1/1

0xe

1/16,384

0xd 1/8,192

0xc 1/4,096

0xb 1/2,048

0xa

1/1,024

0x9

1/512

0x8

1/256

0x7

1/128

0x6

1/64

0x5

1/32

0x4

1/16

0x3

1/8

0x2

1/4

0x1

1/2

0x0

1/1

(Note) The oscillation circuits/external input that are not supported in this IC cannot be

selected as the clock source.

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P Port Interrupt Flag Group Register

Bit

Bit name

Initial

Reset

R/W

Remarks

PPORTINTFGRP

15–13 –

0x0 – R

–

PCINT

H0 R

PBINT

H0 R

PAINT

H0 R 9 P9INT

H0 R

P8INT

H0 R

P7INT

H0 R

P6INT

H0 R

P5INT

H0 R 4 P4INT

H0 R

P3INT

H0 R

P2INT

H0 R

P1INT

H0 R

P0INT

H0 R

*1: Only the bits corresponding to the port groups that support interrupts are provided.

Bits 15–11 Reserved

Bits 10–0 PxINT

These bits indicate that Px port group includes a port that has generated an interrupt.

1 (R): A port generated an interrupt 0 (R): No port generated an interrupt

The PPORTINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt is cleared.