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CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
S1C17M20/M21/M22/M23/M24/M25
Technical Manual
Rev. 1.0
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NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability
of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and,
further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation
or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third
party. When exporting the products or technology described in this material, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You are requested not to use, to resell, to
export and/or to otherwise dispose of the products (and any technical information furnished, if any) for the development and/or
manufacture of weapon of mass destruction or for other military purposes.
All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies.
SEIKO EPSON CORPORATION
©
2017, All rights reserved.
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PREFACE
Preface
This is a technical manual for designers and programmers who develop a product using the S1C17M20/M21/
M22/M23/M24/M25. This document describes the functions of the IC, embedded peripheral circuit operations,
and their control methods.
For the CPU functions and instructions, refer to the “S1C17 Family S1C17 Core Manual.” For the functions
and operations of the debugging tools, refer to the respective tool manuals. (Our “Products: Document Downloads” website provides the downloadable manuals.)
Notational conventions and symbols in this manual
Register address
Peripheral circuit chapters do not provide control register addresses. Refer to “Peripheral Circuit Area” in
the “Memory and Bus” chapter or “List of Peripheral Circuit Control Registers” in the Appendix.
Register and control bit names
In this manual, the register and control bit names are described as shown below to distinguish from signal
and pin names.
XXX register: Represents a register including its all bits.
XXX.YYY bit: Represents the one control bit YYY in the XXX register.
XXX.ZZZ[1:0] bits: Represents the two control bits ZZZ1 and ZZZ0 in the XXX register.
Register table contents and symbols
Initial: Value set at initialization
Reset: Initialization condition. The initialization condition depends on the reset group (H0, H1, or S0).
For more information on the reset groups, refer to “Initialization Conditions (Reset Groups)” in the
“Power Supply, Reset, and Clocks” chapter.
R/W: R = Read only bit
W = Write only bit
WP = Write only bit with a write protection using the MSCPROT.PROT[15:0] bits
R/W = Read/write bit
R/WP = Read/write bit with a write protection using the MSCPROT.PROT[15:0] bits
Control bit read/write values
This manual describes control bit values in a hexadecimal notation except for one-bit values (and except
when decimal or binary notation is required in terms of explanation). The values are described as shown
below according to the control bit width.
1 bit: 0 or 1
2 to 4 bits: 0x0 to 0xf
5 to 8 bits: 0x00 to 0xff
9 to 12 bits: 0x000 to 0xfff
13 to 16 bits: 0x0000 to 0xffff
Decimal: 0 to 9999...
Binary: 0b0000... to 0b1111...
Channel number
Multiple channels may be implemented in some peripheral circuits (e.g., 16-bit timer, etc.). The peripheral
circuit chapters use ‘n’ as the value that represents the channel number in the register and pin names regard-
less of the number of channel actually implemented. Normally, the descriptions are applied to all channels.
If there is a channel that has different functions from others, the channel number is specified clearly.
Example) T16_nCTL register of the 16-bit timer
If one channel is implemented (Ch.0 only): T16_nCTL = T16_0CTL only
If two channels are implemented (Ch.0 and Ch.1): T16_nCTL = T16_0CTL and T16_1CTL
For the number of channels implemented in the peripheral circuits of this IC, refer to “Features” in the
“Overview” chapter.
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– Contents –
Preface ......................................................................................................................................i
Notational conventions and symbols in this manual ................................................................i
1 Overview ........................................................................................................................1-1
1.1 Features .......................................................................................................................... 1-1
1.2 Block Diagram ................................................................................................................. 1-3
1.3 Pins ................................................................................................................................. 1-4
1.3.1 S1C17M20/M23 Pin Configuration Diagram .................................................... 1-4
1.3.2 S1C17M21/M24 Pin Configuration Diagram .................................................... 1-6
1.3.3 S1C17M22/M25 Pin Configuration Diagram .................................................... 1-7
1.3.4 Pin Descriptions ................................................................................................ 1-8
2 Power Supply, Reset, and Clocks ...............................................................................2-1
2.1 Power Generator (PWG) .................................................................................................. 2-1
2.1.1 Overview ........................................................................................................... 2-1
2.1.2 Pins ................................................................................................................... 2-1
2.1.3 V
D1 Regulator Operation Mode ......................................................................... 2-1
2.2 System Reset Controller (SRC) ....................................................................................... 2-2
2.2.1 Overview ........................................................................................................... 2-2
2.2.2 Input Pin ............................................................................................................ 2-2
2.2.3 Reset Sources .................................................................................................. 2-3
2.2.4 Initialization Conditions (Reset Groups) ............................................................ 2-3
2.3 Clock Generator (CLG) .................................................................................................... 2-4
2.3.1 Overview ........................................................................................................... 2-4
2.3.2 Input/Output Pins ............................................................................................. 2-5
2.3.3 Clock Sources .................................................................................................. 2-5
2.3.4 Operations ........................................................................................................ 2-8
2.4 Operating Mode ............................................................................................................. 2-12
2.4.1 Initial Boot Sequence ....................................................................................... 2-12
2.4.2 Transition between Operating Modes .............................................................. 2-12
2.5 Interrupts ........................................................................................................................ 2-14
2.6 Control Registers ........................................................................................................... 2-14
PWG VD1 Regulator Control Register ....................................................................................... 2-14
CLG System Clock Control Register ........................................................................................ 2-15
CLG Oscillation Control Register ............................................................................................. 2-16
CLG OSC1 Control Register .................................................................................................... 2-17
CLG OSC3 Control Register .................................................................................................... 2-18
CLG Interrupt Flag Register ..................................................................................................... 2-19
CLG Interrupt Enable Register ................................................................................................. 2-20
CLG FOUT Control Register ..................................................................................................... 2-21
3 CPU and Debugger ......................................................................................................3-1
3.1 Overview ......................................................................................................................... 3-1
3.2 CPU Core ........................................................................................................................ 3-2
3.2.1 CPU Registers .................................................................................................. 3-2
3.2.2 Instruction Set .................................................................................................. 3-2
3.2.3 Reading PSR .................................................................................................... 3-2
3.2.4 I/O Area Reserved for the S1C17 Core ............................................................ 3-2
3.3 Debugger ........................................................................................................................ 3-2
3.3.1 Debugging Functions........................................................................................ 3-2
3.3.2 Resource Requirements and Debugging Tools ................................................ 3-2
3.3.3 List of Debugger Input/Output Pins .................................................................. 3-3
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3.3.4 External Connection ......................................................................................... 3-3
3.3.5 Flash Security Function .................................................................................... 3-3
3.4 Control Register .............................................................................................................. 3-4
MISC PSR Register ................................................................................................................... 3-4
Debug RAM Base Register ....................................................................................................... 3-4
4 Memory and Bus ..........................................................................................................4-1
4.1 Overview ......................................................................................................................... 4-1
4.2 Bus Access Cycle ........................................................................................................... 4-1
4.3 Flash Memory ................................................................................................................. 4-2
4.3.1 Flash Memory Pin ............................................................................................. 4-2
4.3.2 Flash Bus Access Cycle Setting ....................................................................... 4-2
4.3.3 Flash Programming ........................................................................................... 4-3
4.4 RAM ................................................................................................................................ 4-3
4.5 Peripheral Circuit Control Registers ................................................................................ 4-3
4.5.1 System-Protect Function .................................................................................. 4-8
4.6 Control Registers ............................................................................................................ 4-8
MISC System Protect Register ................................................................................................. 4-8
MISC IRAM Size Register.......................................................................................................... 4-8
FLASHC Flash Read Cycle Register ......................................................................................... 4-8
5 Interrupt Controller (ITC) .............................................................................................5-1
5.1 Overview ......................................................................................................................... 5-1
5.2 Vector Table .................................................................................................................... 5-1
5.2.1 Vector Table Base Address (TTBR) ................................................................... 5-3
5.3 Initialization ..................................................................................................................... 5-3
5.4 Maskable Interrupt Control and Operations ................................................................... 5-3
5.4.1 Peripheral Circuit Interrupt Control ................................................................... 5-3
5.4.2 ITC Interrupt Request Processing .................................................................... 5-4
5.4.3 Conditions to Accept Interrupt Requests by the CPU...................................... 5-4
5.5 NMI .................................................................................................................................. 5-4
5.6 Software Interrupts ......................................................................................................... 5-4
5.7 Interrupt Processing by the CPU .................................................................................... 5-5
5.8 Control Registers ............................................................................................................ 5-5
MISC Vector Table Address Low Register ................................................................................ 5-5
MISC Vector Table Address High Register ................................................................................ 5-5
ITC Interrupt Level Setup Register x ......................................................................................... 5-5
6 I/O Ports (PPORT) .........................................................................................................6-1
6.1 Overview ......................................................................................................................... 6-1
6.2 I/O Cell Structure and Functions ..................................................................................... 6-2
6.2.1 Schmitt Input .................................................................................................... 6-3
6.2.2 Over Voltage Tolerant Fail-Safe Type I/O Cell ................................................... 6-3
6.2.3 Pull-Up/Pull-Down ............................................................................................ 6-3
6.2.4 CMOS Output and High Impedance State ....................................................... 6-3
6.3 Clock Settings ................................................................................................................. 6-3
6.3.1 PPORT Operating Clock ................................................................................... 6-3
6.3.2 Clock Supply in SLEEP Mode .......................................................................... 6-4
6.3.3 Clock Supply in DEBUG Mode ......................................................................... 6-4
6.4 Operations ...................................................................................................................... 6-4
6.4.1 Initialization ....................................................................................................... 6-4
6.4.2 Port Input/Output Control ................................................................................. 6-5
6.5 Interrupts ......................................................................................................................... 6-6
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6.6 Control Registers ............................................................................................................ 6-7
Px Port Data Register ................................................................................................................ 6-7
Px Port Enable Register ............................................................................................................ 6-7
Px Port Pull-up/down Control Register ..................................................................................... 6-8
Px Port Interrupt Flag Register .................................................................................................. 6-8
Px Port Interrupt Control Register ............................................................................................. 6-8
Px Port Chattering Filter Enable Register .................................................................................. 6-9
Px Port Mode Select Register ................................................................................................... 6-9
Px Port Function Select Register .............................................................................................. 6-9
P Port Clock Control Register .................................................................................................. 6-10
P Port Interrupt Flag Group Register ........................................................................................ 6-11
6.7 Control Register and Port Function Configuration of this IC ......................................... 6-12
6.7.1 P0 Port Group .................................................................................................. 6-12
6.7.2 P1 Port Group .................................................................................................. 6-14
6.7.3 P2 Port Group .................................................................................................. 6-17
6.7.4 P3 Port Group .................................................................................................. 6-19
6.7.5 P4 Port Group .................................................................................................. 6-21
6.7.6 Pd Port Group .................................................................................................. 6-23
6.7.7 Common Registers between Port Groups....................................................... 6-24
7 Universal Port Multiplexer (UPMUX) ...........................................................................7-1
7.1 Overview ......................................................................................................................... 7-1
7.2 Peripheral Circuit I/O Function Assignment .................................................................... 7-1
7.3 Control Registers ............................................................................................................ 7-2
Pxy–xz Universal Port Multiplexer Setting Register ................................................................... 7-2
8 Watchdog Timer (WDT2) ..............................................................................................8-1
8.1 Overview ......................................................................................................................... 8-1
8.2 Clock Settings ................................................................................................................. 8-1
8.2.1 WDT2 Operating Clock ..................................................................................... 8-1
8.2.2 Clock Supply in DEBUG Mode ......................................................................... 8-1
8.3 Operations ...................................................................................................................... 8-2
8.3.1 WDT2 Control ................................................................................................... 8-2
8.3.2 Operations in HALT and SLEEP Modes............................................................ 8-3
8.4 Control Registers ............................................................................................................ 8-3
WDT2 Clock Control Register ................................................................................................... 8-3
WDT2 Control Register ............................................................................................................. 8-4
WDT2 Counter Compare Match Register ................................................................................. 8-4
9 Real-Time Clock (RTCA) ..............................................................................................9-1
9.1 Overview ......................................................................................................................... 9-1
9.2 Output Pin and External Connection .............................................................................. 9-1
9.2.1 Output Pin ......................................................................................................... 9-1
9.3 Clock Settings ................................................................................................................. 9-2
9.3.1 RTCA Operating Clock ..................................................................................... 9-2
9.3.2 Theoretical Regulation Function ....................................................................... 9-2
9.4 Operations ...................................................................................................................... 9-3
9.4.1 RTCA Control ................................................................................................... 9-3
9.4.2 Real-Time Clock Counter Operations ............................................................... 9-4
9.4.3 Stopwatch Control ............................................................................................ 9-4
9.4.4 Stopwatch Count-up Pattern ........................................................................... 9-4
9.5 Interrupts ......................................................................................................................... 9-5
9.6 Control Registers ............................................................................................................ 9-6
RTC Control Register ................................................................................................................ 9-6
RTC Second Alarm Register ..................................................................................................... 9-7
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RTC Hour/Minute Alarm Register .............................................................................................. 9-8
RTC Stopwatch Control Register .............................................................................................. 9-8
RTC Second/1Hz Register ........................................................................................................ 9-9
RTC Hour/Minute Register ....................................................................................................... 9-10
RTC Month/Day Register ......................................................................................................... 9-11
RTC Year/Week Register .......................................................................................................... 9-11
RTC Interrupt Flag Register ...................................................................................................... 9-12
RTC Interrupt Enable Register ................................................................................................. 9-13
10 Supply Voltage Detector (SVD3) ...............................................................................10-1
10.1 Overview ...................................................................................................................... 10-1
10.2 Input Pins and External Connection ............................................................................ 10-2
10.2.1 Input Pins ....................................................................................................... 10-2
10.2.2 External Connection ...................................................................................... 10-2
10.3 Clock Settings .............................................................................................................. 10-2
10.3.1 SVD3 Operating Clock ................................................................................... 10-2
10.3.2 Clock Supply in SLEEP Mode ....................................................................... 10-2
10.3.3 Clock Supply in DEBUG Mode ...................................................................... 10-3
10.4 Operations ................................................................................................................... 10-3
10.4.1 SVD3 Control ................................................................................................. 10-3
10.4.2 SVD3 Operations ........................................................................................... 10-4
10.5 SVD3 Interrupt and Reset ............................................................................................ 10-4
10.5.1 SVD3 Interrupt ............................................................................................... 10-4
10.5.2 SVD3 Reset .................................................................................................... 10-5
10.6 Control Registers ......................................................................................................... 10-5
SVD3 Clock Control Register ................................................................................................... 10-5
SVD3 Control Register ............................................................................................................. 10-6
SVD3 Status and Interrupt Flag Register ................................................................................. 10-7
SVD3 Interrupt Enable Register ............................................................................................... 10-8
11 16-bit Timers (T16) .....................................................................................................11-1
11.1 Overview ...................................................................................................................... 11-1
11.2 Input Pin ....................................................................................................................... 11-1
11.3 Clock Settings .............................................................................................................. 11-2
11.3.1 T16 Operating Clock ...................................................................................... 11-2
11.3.2 Clock Supply in SLEEP Mode ....................................................................... 11-2
11.3.3 Clock Supply in DEBUG Mode ...................................................................... 11-2
11.3.4 Event Counter Clock ...................................................................................... 11-2
11.4 Operations ................................................................................................................... 11-2
11.4.1 Initialization .................................................................................................... 11-2
11.4.2 Counter Underflow ........................................................................................ 11-3
11.4.3 Operations in Repeat Mode ........................................................................... 11-3
11.4.4 Operations in One-shot Mode ....................................................................... 11-3
11.4.5 Counter Value Read ....................................................................................... 11-4
11.5 Interrupt ........................................................................................................................ 11-4
11.6 Control Registers ......................................................................................................... 11-4
T16 Ch.n Clock Control Register ............................................................................................. 11-4
T16 Ch.n Mode Register .......................................................................................................... 11-5
T16 Ch.n Control Register ........................................................................................................ 11-5
T16 Ch.n Reload Data Register ................................................................................................ 11-6
T16 Ch.n Counter Data Register .............................................................................................. 11-6
T16 Ch.n Interrupt Flag Register .............................................................................................. 11-6
T16 Ch.n Interrupt Enable Register .......................................................................................... 11-7
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12 UART (UART3) ............................................................................................................12-1
12.1 Overview ...................................................................................................................... 12-1
12.2 Input/Output Pins and External Connections .............................................................. 12-2
12.2.1 List of Input/Output Pins ................................................................................ 12-2
12.2.2 External Connections .................................................................................... 12-2
12.2.3 Input Pin Pull-Up Function............................................................................. 12-2
12.2.4 Output Pin Open-Drain Output Function ...................................................... 12-2
12.2.5 Input/Output Signal Inverting Function .......................................................... 12-2
12.3 Clock Settings .............................................................................................................. 12-2
12.3.1 UART3 Operating Clock ................................................................................ 12-2
12.3.2 Clock Supply in SLEEP Mode ....................................................................... 12-3
12.3.3 Clock Supply in DEBUG Mode ...................................................................... 12-3
12.3.4 Baud Rate Generator ..................................................................................... 12-3
12.4 Data Format ................................................................................................................. 12-3
12.5 Operations ................................................................................................................... 12-4
12.5.1 Initialization .................................................................................................... 12-4
12.5.2 Data Transmission ......................................................................................... 12-5
12.5.3 Data Reception .............................................................................................. 12-6
12.5.4 IrDA Interface ................................................................................................. 12-7
12.5.5 Carrier Modulation ......................................................................................... 12-7
12.6 Receive Errors .............................................................................................................. 12-8
12.6.1 Framing Error ................................................................................................. 12-8
12.6.2 Parity Error ..................................................................................................... 12-8
12.6.3 Overrun Error ................................................................................................. 12-9
12.7 Interrupts ...................................................................................................................... 12-9
12.8 Control Registers ......................................................................................................... 12-9
UART3 Ch.n Clock Control Register ........................................................................................ 12-9
UART3 Ch.n Mode Register .................................................................................................... 12-10
UART3 Ch.n Baud–Rate Register ........................................................................................... 12-11
UART3 Ch.n Control Register ................................................................................................. 12-12
UART3 Ch.n Transmit Data Register ....................................................................................... 12-12
UART3 Ch.n Receive Data Register ........................................................................................ 12-12
UART3 Ch.n Status and Interrupt Flag Register ..................................................................... 12-13
UART3 Ch.n Interrupt Enable Register.................................................................................... 12-14
UART3 Ch.n Carrier Waveform Register ................................................................................. 12-14
13 Synchronous Serial Interface (SPIA) ........................................................................13-1
13.1 Overview ...................................................................................................................... 13-1
13.2 Input/Output Pins and External Connections .............................................................. 13-2
13.2.1 List of Input/Output Pins ................................................................................ 13-2
13.2.2 External Connections .................................................................................... 13-2
13.2.3 Pin Functions in Master Mode and Slave Mode ............................................ 13-3
13.2.4 Input Pin Pull-Up/Pull-Down Function .......................................................... 13-3
13.3 Clock Settings .............................................................................................................. 13-3
13.3.1 SPIA Operating Clock .................................................................................... 13-3
13.3.2 Clock Supply in DEBUG Mode ...................................................................... 13-4
13.3.3 SPI Clock (SPICLKn) Phase and Polarity ...................................................... 13-4
13.4 Data Format ................................................................................................................. 13-5
13.5 Operations ................................................................................................................... 13-5
13.5.1 Initialization .................................................................................................... 13-5
13.5.2 Data Transmission in Master Mode ............................................................... 13-5
13.5.3 Data Reception in Master Mode .................................................................... 13-7
13.5.4 Terminating Data Transfer in Master Mode .................................................... 13-8
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13.5.5 Data Transfer in Slave Mode .......................................................................... 13-8
13.5.6 Terminating Data Transfer in Slave Mode ..................................................... 13-10
13.6 Interrupts ..................................................................................................................... 13-10
13.7 Control Registers ........................................................................................................ 13-11
SPIA Ch.n Mode Register ....................................................................................................... 13-11
SPIA Ch.n Control Register ..................................................................................................... 13-12
SPIA Ch.n Transmit Data Register .......................................................................................... 13-13
SPIA Ch.n Receive Data Register ........................................................................................... 13-13
SPIA Ch.n Interrupt Flag Register ........................................................................................... 13-13
SPIA Ch.n Interrupt Enable Register ....................................................................................... 13-14
14 I2C (I2C) .......................................................................................................................14-1
14.1 Overview ...................................................................................................................... 14-1
14.2 Input/Output Pins and External Connections .............................................................. 14-2
14.2.1 List of Input/Output Pins ................................................................................ 14-2
14.2.2 External Connections .................................................................................... 14-2
14.3 Clock Settings .............................................................................................................. 14-3
14.3.1 I2C Operating Clock ...................................................................................... 14-3
14.3.2 Clock Supply in DEBUG Mode ...................................................................... 14-3
14.3.3 Baud Rate Generator ..................................................................................... 14-3
14.4 Operations ................................................................................................................... 14-4
14.4.1 Initialization .................................................................................................... 14-4
14.4.2 Data Transmission in Master Mode ............................................................... 14-5
14.4.3 Data Reception in Master Mode .................................................................... 14-7
14.4.4 10-bit Addressing in Master Mode ................................................................ 14-9
14.4.5 Data Transmission in Slave Mode................................................................. 14-10
14.4.6 Data Reception in Slave Mode ..................................................................... 14-12
14.4.7 Slave Operations in 10-bit Address Mode .................................................... 14-14
14.4.8 Automatic Bus Clearing Operation ............................................................... 14-14
14.4.9 Error Detection .............................................................................................. 14-15
14.5 Interrupts ..................................................................................................................... 14-16
14.6 Control Registers ........................................................................................................ 14-17
I2C Ch.n Clock Control Register ............................................................................................. 14-17
I2C Ch.n Mode Register .......................................................................................................... 14-18
I2C Ch.n Baud-Rate Register .................................................................................................. 14-18
I2C Ch.n Own Address Register ............................................................................................. 14-18
I2C Ch.n Control Register ....................................................................................................... 14-19
I2C Ch.n Transmit Data Register ............................................................................................. 14-20
I2C Ch.n Receive Data Register .............................................................................................. 14-20
I2C Ch.n Status and Interrupt Flag Register ........................................................................... 14-20
I2C Ch.n Interrupt Enable Register ......................................................................................... 14-21
15 16-bit PWM Timers (T16B) ........................................................................................15-1
15.1 Overview ...................................................................................................................... 15-1
15.2 Input/Output Pins ......................................................................................................... 15-2
15.3 Clock Settings .............................................................................................................. 15-3
15.3.1 T16B Operating Clock ................................................................................... 15-3
15.3.2 Clock Supply in SLEEP Mode ....................................................................... 15-3
15.3.3 Clock Supply in DEBUG Mode ...................................................................... 15-3
15.3.4 Event Counter Clock ...................................................................................... 15-3
15.4 Operations ................................................................................................................... 15-4
15.4.1 Initialization .................................................................................................... 15-4
15.4.2 Counter Block Operations ............................................................................. 15-5
15.4.3 Comparator/Capture Block Operations ......................................................... 15-8
15.4.4 TOUT Output Control ................................................................................... 15-16
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15.5 Interrupt ....................................................................................................................... 15-22
15.6 Control Registers ........................................................................................................ 15-22
T16B Ch.n Clock Control Register .......................................................................................... 15-22
T16B Ch.n Counter Control Register ...................................................................................... 15-23
T16B Ch.n Max Counter Data Register ................................................................................... 15-24
T16B Ch.n Timer Counter Data Register................................................................................. 15-24
T16B Ch.n Counter Status Register ........................................................................................ 15-25
T16B Ch.n Interrupt Flag Register........................................................................................... 15-26
T16B Ch.n Interrupt Enable Register ...................................................................................... 15-27
T16B Ch.n Comparator/Capture m Control Register .............................................................. 15-28
T16B Ch.n Compare/Capture m Data Register ....................................................................... 15-30
16 Sound Generator (SNDA) ..........................................................................................16-1
16.1 Overview ...................................................................................................................... 16-1
16.2 Output Pins and External Connections ........................................................................ 16-2
16.2.1 List of Output Pins ......................................................................................... 16-2
16.2.2 Output Pin Drive Mode .................................................................................. 16-2
16.2.3 External Connections .................................................................................... 16-2
16.3 Clock Settings .............................................................................................................. 16-3
16.3.1 SNDA Operating Clock .................................................................................. 16-3
16.3.2 Clock Supply in SLEEP Mode ....................................................................... 16-3
16.3.3 Clock Supply in DEBUG Mode ...................................................................... 16-3
16.4 Operations ................................................................................................................... 16-3
16.4.1 Initialization .................................................................................................... 16-3
16.4.2 Buzzer Output in Normal Buzzer Mode ......................................................... 16-3
16.4.3 Buzzer Output in One-shot Buzzer Mode...................................................... 16-6
16.4.4 Output in Melody Mode ................................................................................. 16-7
16.5 Interrupts ...................................................................................................................... 16-9
16.6 Control Registers ......................................................................................................... 16-9
SNDA Clock Control Register .................................................................................................. 16-9
SNDA Select Register ............................................................................................................. 16-10
SNDA Control Register ............................................................................................................ 16-11
SNDA Data Register ................................................................................................................ 16-11
SNDA Interrupt Flag Register .................................................................................................. 16-12
SNDA Interrupt Enable Register .............................................................................................. 16-13
17 IR Remote Controller (REMC3) ................................................................................17-1
17.1 Overview ...................................................................................................................... 17-1
17.2 Input/Output Pins and External Connections .............................................................. 17-1
17.2.1 Output Pin ...................................................................................................... 17-1
17.2.2 External Connections .................................................................................... 17-2
17.3 Clock Settings .............................................................................................................. 17-2
17.3.1 REMC3 Operating Clock ............................................................................... 17-2
17.3.2 Clock Supply in SLEEP Mode ....................................................................... 17-2
17.3.3 Clock Supply in DEBUG Mode ...................................................................... 17-2
17.4 Operations ................................................................................................................... 17-2
17.4.1 Initialization .................................................................................................... 17-2
17.4.2 Data Transmission Procedures ...................................................................... 17-3
17.4.3 REMO Output Waveform ............................................................................... 17-3
17.4.4 Continuous Data Transmission and Compare Buffers................................... 17-5
17.5 Interrupts ...................................................................................................................... 17-6
17.6 Application Example: Driving EL Lamp ........................................................................ 17-7
17.7 Control Registers ......................................................................................................... 17-7
REMC3 Clock Control Register ................................................................................................ 17-7
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Page 11
CONTENTS
REMC3 Data Bit Counter Control Register .............................................................................. 17-8
REMC3 Data Bit Counter Register ........................................................................................... 17-9
REMC3 Data Bit Active Pulse Length Register ....................................................................... 17-10
REMC3 Data Bit Length Register ............................................................................................ 17-10
REMC3 Status and Interrupt Flag Register ............................................................................. 17-10
REMC3 Interrupt Enable Register ........................................................................................... 17-11
REMC3 Carrier Waveform Register ......................................................................................... 17-11
REMC3 Carrier Modulation Control Register .......................................................................... 17-12
18 R/F Converter (RFC) ..................................................................................................18-1
18.1 Overview ...................................................................................................................... 18-1
18.2 Input/Output Pins and External Connections .............................................................. 18-2
18.2.1 List of Input/Output Pins ................................................................................ 18-2
18.2.2 External Connections .................................................................................... 18-2
18.3 Clock Settings .............................................................................................................. 18-3
18.3.1 RFC Operating Clock ..................................................................................... 18-3
18.3.2 Clock Supply in SLEEP Mode ....................................................................... 18-3
18.3.3 Clock Supply in DEBUG Mode ...................................................................... 18-3
18.4 Operations ................................................................................................................... 18-3
18.4.1 Initialization .................................................................................................... 18-3
18.4.2 Operating Modes ........................................................................................... 18-4
18.4.3 RFC Counters ................................................................................................ 18-4
18.4.4 Converting Operations and Control Procedure ............................................. 18-5
18.4.5 CR Oscillation Frequency Monitoring Function ............................................. 18-7
18.5 Interrupts ...................................................................................................................... 18-7
18.6 Control Registers ......................................................................................................... 18-8
RFC Ch.n Clock Control Register ............................................................................................ 18-8
RFC Ch.n Control Register ....................................................................................................... 18-8
RFC Ch.n Oscillation Trigger Register ...................................................................................... 18-9
RFC Ch.n Measurement Counter Low and High Registers .................................................... 18-10
RFC Ch.n Time Base Counter Low and High Registers ......................................................... 18-10
RFC Ch.n Interrupt Flag Register ............................................................................................ 18-11
RFC Ch.n Interrupt Enable Register ........................................................................................ 18-11
19 12-bit A/D Converter (ADC12A) ................................................................................19-1
19.1 Overview ...................................................................................................................... 19-1
19.2 Input Pins and External Connections ........................................................................... 19-2
19.2.1 List of Input Pins ............................................................................................ 19-2
19.2.2 External Connections .................................................................................... 19-2
19.3 Clock Settings .............................................................................................................. 19-2
19.3.1 ADC12A Operating Clock .............................................................................. 19-2
19.3.2 Sampling Time ............................................................................................... 19-2
19.4 Operations ................................................................................................................... 19-3
19.4.1 Initialization .................................................................................................... 19-3
19.4.2 Conversion Start Trigger Source.................................................................... 19-3
19.4.3 Conversion Mode and Analog Input Pin Settings .......................................... 19-4
19.4.4 A/D Conversion Operations and Control Procedures .................................... 19-4
19.5 Interrupts ...................................................................................................................... 19-6
19.6 Control Registers ......................................................................................................... 19-6
ADC12A Ch.n Control Register ................................................................................................ 19-6
ADC12A Ch.n Trigger/Analog Input Select Register ................................................................ 19-7
ADC12A Ch.n Configuration Register ...................................................................................... 19-8
ADC12A Ch.n Interrupt Flag Register ...................................................................................... 19-9
ADC12A Ch.n Interrupt Enable Register ................................................................................. 19-10
ADC12A Ch.n Result Register m ............................................................................................. 19-10
S1C17M20/M21/M22/M23/M24/M25 Seiko Epson Corporation
TECHNICAL MANUAL (Rev. 1.0)
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CONTENTS
20 Multiplier/Divider (COPRO2) .....................................................................................20-1
20.1 Overview ...................................................................................................................... 20-1
20.2 Operation Mode and Output Mode .............................................................................. 20-1
20.3 Multiplication ................................................................................................................ 20-2
20.4 Division ......................................................................................................................... 20-3
20.5 MAC ............................................................................................................................. 20-5
20.6 Reading Operation Results .......................................................................................... 20-7
21 Electrical Characteristics .........................................................................................21-1
21.1 Absolute Maximum Ratings ......................................................................................... 21-1
21.2 Recommended Operating Conditions ......................................................................... 21-1
21.3 Current Consumption ................................................................................................... 21-2
21.4 System Reset Controller (SRC) Characteristics ........................................................... 21-4
21.5 Clock Generator (CLG) Characteristics........................................................................ 21-4
21.6 Flash Memory Characteristics ..................................................................................... 21-7
21.7 Input/Output Port (PPORT) Characteristics ................................................................. 21-7
21.8 Supply Voltage Detector (SVD3) Characteristics ......................................................... 21-8
21.9 UART (UART3) Characteristics ................................................................................... 21-10
21.10 Synchronous Serial Interface (SPIA) Characteristics ................................................ 21-10
21.11 I2C (I2C) Characteristics ............................................................................................ 21-11
21.12 R/F Converter (RFC) Characteristics......................................................................... 21-12
21.13 12-bit A/D Converter (ADC12A) Characteristics ....................................................... 21-13
22 Basic External Connection Diagram .......................................................................22-1
23 Package ......................................................................................................................23-1
Appendix A List of Peripheral Circuit Control Registers ......................................... AP-A-1
0x4000–0x4008 Misc Registers (MISC) ............................................................... AP-A-1
0x4020 Power Generator (PWG) ............................................................ AP-A-1
0x4040–0x4050 Clock Generator (CLG) .............................................................. AP-A-1
0x4080–0x4094 Interrupt Controller (ITC) ........................................................... AP-A-2
0x40a0–0x40a4 Watchdog Timer (WDT2) ........................................................... AP-A-4
0x40c0–0x40d2 Real-time Clock (RTCA) ............................................................ AP-A-4
0x4100–0x4106 Supply Voltage Detector (SVD3) ............................................... AP-A-6
0x4160–0x416c 16-bit Timer (T16) Ch.0 ............................................................. AP-A-6
0x41b0 Flash Controller (FLASHC) ........................................................ AP-A-7
0x4200–0x42e2 I/O Ports (PPORT) ..................................................................... AP-A-7
0x4300–0x431e Universal Port Multiplexer (UPMUX) ........................................ AP-A-17
0x4380–0x4390 UART (UART3) Ch.0 ................................................................. AP-A-19
0x43a0–0x43ac 16-bit Timer (T16) Ch.1 ............................................................ AP-A-20
0x43b0–0x43ba Synchronous Serial Interface (SPIA) Ch.0 ................................ AP-A-20
0x43c0–0x43d2 I
0x5000–0x501a 16-bit PWM Timer (T16B) Ch.0 ................................................ AP-A-22
0x5040–0x505a 16-bit PWM Timer (T16B) Ch.1 ................................................ AP-A-23
0x5200–0x5210 UART (UART3) Ch.1 ................................................................. AP-A-25
0x5260–0x526c 16-bit Timer (T16) Ch.2 ............................................................ AP-A-26
0x5270–0x527a Synchronous Serial Interface (SPIA) Ch.1 ................................ AP-A-27
0x5300–0x530a Sound Generator (SNDA) ......................................................... AP-A-27
0x5320–0x5332 IR Remote Controller (REMC3) ................................................ AP-A-28
0x5440–0x5450 R/F Converter (RFC) Ch.0 (S1C17M22/M25) ........................... AP-A-29
0x5460–0x5470 R/F Converter (RFC) Ch.1 (S1C17M22/M25) ........................... AP-A-30
0x5480–0x548c 16-bit Timer (T16) Ch.3 ............................................................ AP-A-31
2
C (I2C) Ch.0 ........................................................................... AP-A-21
x
Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
Page 13
CONTENTS
0x54a0–0x54ba 12-bit A/D Converter (ADC12A) ............................................... AP-A-31
0xffff90 Debugger (DBG) ....................................................................... AP-A-33
Appendix B Power Saving .......................................................................................... AP-B-1
B.1 Operating Status Configuration Examples for Power Saving ...................................... AP-B-1
B.2 Other Power Saving Methods ..................................................................................... AP-B-2
Appendix C Mounting Precautions ............................................................................ AP-C-1
Appendix D Measures Against Noise ........................................................................ AP-D-1
Appendix E Initialization Routine ............................................................................... AP-E-1
Revision History
S1C17M20/M21/M22/M23/M24/M25 Seiko Epson Corporation
TECHNICAL MANUAL (Rev. 1.0)
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Page 14
1 OVERVIEW
1 Overview
The S1C17M20/M21/M22/M23/M24/M25 is a 16-bit embedded Flash MCU that features low power consumption. The embedded Flash memory can also be used as an EEPROM emulation data memory via software. The
S1C17M20/M21/M22/M23/M24/M25 includes various serial interfaces, an A/D converter, and various timers as
well as a high-performance 16-bit CPU. It is suitable for applications that require an A/D conversion function, such
as household equipment and FA products.
1.1 Features
Table 1.1.1 Features
Model S1C17M20/M23 S1C17M21/M24 S1C17M22/M25
CPU
CPU core Seiko Epson original 16-bit RISC CPU core S1C17
Other On-chip debugger
Embedded Flash memory
Capacity
(for both instructions and data)
Erase/program count 1,000 times (min.) * Programming by the debugging tool ICDmini
Other Security function to protect from reading/programming by ICDmini
Embedded RAM
Capacity 2K bytes
Clock generator (CLG)
System clock source 4 sources (IOSC/OSC1/OSC3/EXOSC)
System clock frequency
(operating frequency)
IOSC oscillator circuit
(boot clock source)
OSC1 oscillator circuit
OSC3 oscillator circuit – 21 MHz (max.) crystal/ceramic oscillator
EXOSC clock input 21 MHz (max.) square or sine wave input
Other Configurable system clock division ratio
I/O port (PPORT)
Number of
ports
purpose
Number of input interrupt ports 15 bits (max.) 19 bits (max.) 35 bits (max.)
Number of ports that support
universal port multiplexer (UPMUX)
Timers
Watchdog timer (WDT2) Generates NMI or watchdog timer reset.
Real-time clock (RTCA) 128–1 Hz counter, second/minute/hour/day/day of the week/month/year counters
16-bit timer (T16) 4 channels
16-bit PWM timer (T16B) 2 channels
Supply voltage detector (SVD3)
Detection voltage V
Detection level V
Other Intermittent operation mode
I/O port 17 bits (max.) 23 bits (max.) 39 bits (max.)
general-
Output port 1 bit (max.)
Other Pins are shared with the peripheral I/O.
24-pin PKG 32-pin PKG
16K bytes (S1C17M20/M21/M22)
32K bytes (S1C17M23/M24/M25)
On-board programming function using ICDmini
Flash programming voltage can be generated internally.
21 MHz (max.)
700 kHz (typ.) embedded oscillator
23 µs (max.) starting time (time from cancelation of SLEEP state to vector table read by the CPU)
–
32 kHz (typ.) embedded oscillator
12, 16, and 20 MHz-switchable embedded oscillator
Configurable system clock used at wake up from SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
15 bits 19 bits 32 bits
A peripheral circuit I/O function selected via software can be assigned to each port.
Programmable NMI/reset generation cycle
Theoretical regulation function for 1-second correction
Alarm and stopwatch functions
Generates the SPIA master clocks and the ADC12A trigger signal.
Event counter/capture function
PWM waveform generation function
Number of PWM output or capture input ports: 2 ports/channel
DD or external voltage (one external voltage input port is provided and an external voltage level
can be detected even if it exceeds V
DD: 28 levels (1.8 to 5.0 V)/external voltage: 32 levels (1.2 to 5.0 V)
Generates an interrupt or reset according to the detection level evaluation.
32.768 kHz (typ.) crystal oscillator
–
Oscillation stop detection circuit included
– Auto-trimming function for the embedded oscillator
DD.)
S1C17M20/M21/M22/M23/M24/M25 Seiko Epson Corporation
TECHNICAL MANUAL (Rev. 1.0)
1-1
Page 15
1 OVERVIEW
Model S1C17M20/M23 S1C17M21/M24 S1C17M22/M25
24-pin PKG 32-pin PKG
Serial interfaces
UART (UART3) 2 channels
Baud-rate generator included, IrDA1.0 supported
Open drain output, signal polarity, and baud rate division ratio are configurable.
Infrared communication carrier modulation output function
Synchronous serial interface
(SPIA)
2
I
C (I2C) 1 channel
2 channels
2 to 16-bit variable data length
The 16-bit timer (T16) can be used for the baud-rate generator in master mode.
Baud-rate generator included
Sound generator (SNDA)
Buzzer output function 512 Hz to 16 kHz output frequencies
One-shot output function
Melody generation function Pitch: 128 Hz to 16 kHz ≈ C3 to C6
Duration: 7 notes/rests (Half note/rest to thirty-second note/rest)
Tempo: 16 tempos (30 to 480)
Tie/slur may be specified.
IR remote controller (REMC3)
Number of transmitter channels 1 channel
Other EL lamp drive waveform can be generated for an application example.
Output inversion function
R/F converter (RFC)
Conversion method – CR oscillation type
with 24-bit counters
Number of conversion channels 2 channels (Up to two sensors
can be connected to each
channel.)
Supported sensors
DC-bias resistive sensors
12-bit A/D converter (ADC12A)
Conversion method Successive approximation type
Resolution 12 bits
Number of conversion channels 1 channel
Number of analog signal input ports
4 ports 6 ports 8 ports
Multiplier/divider (COPRO2)
Arithmetic functions 16-bit × 16-bit multiplier
16-bit × 16-bit + 32-bit multiply and accumulation unit
32-bit ÷ 32-bit divider
Reset
#RESET pin Reset when the reset pin is set to low.
Power-on reset Reset at power on.
Brownout reset Reset when the power supply voltage drops.
Key entry reset Reset when the P00 to P01/P02/P03 keys are pressed simultaneously (can be enabled/disabled
using a register).
Watchdog timer reset Reset when the watchdog timer overflows (can be enabled/disabled using a register).
Supply voltage detector reset
Reset when
the supply voltage detector
detects the set voltage level (can be enabled/disabled us-
ing a register).
Interrupt
Non-maskable interrupt 4 systems (Reset, address misaligned interrupt, debug, NMI)
Programmable
interrupt
External int. 1 system (8 levels)
Internal int. 17 systems (8 levels) 19 systems (8 levels)
Power supply voltage
V
DD operating voltage 1.8 to 5.5 V
V
DD operating voltage for Flash
programming
2.4 to 5.5 V (When VPP (7.5 V) is supplied externally)
2.7 to 5.5 V (When V
PP is generated internally)
Operating temperature
Operating temperature range -40 to 85°C
Current consumption (typ. value)
SLEEP mode 0.36 µA
IOSC = OFF, OSC1 = OFF, OSC3 = OFF
HALT mode 0.7 µA
OSC1 = 32.768 kHz (crystal oscillator), RTC = ON
RUN mode 5 µA
OSC1 = 32.768 kHz (crystal oscillator), RTC = ON, CPU = OSC1
160 µA
OSC3 = 1 MHz (ceramic oscillator), OSC1 = 32.768 kHz (crystal oscillator), RTC = ON, CPU = OSC3
Shipping form
Package
(Lead pitch)
SQFN4-24
(0.5 mm)
SQFN5-32
(0.5 mm)
TQFP12-32pin
(0.8 mm)
TQFP12-48pin
(0.5 mm)
1-2
Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
Page 16
1.2 Block Diagram
#RESET
1 OVERVIEW
Multiplier/divider
Flash memory
16KB (M20/M21/M22)
32KB (M23/M24/M25)
∗
P00–07
P10–17
P20–27
P30–37
P40–42
PD0–D1
PD2
∗
PD3–D4
RTC1S
EXSVD0
TOUT00–01
TOUT10–11
CAP00–01
CAP10–11
EXCL00–01
EXCL10–11
(COPRO2)
Internal RAM
2KB
Flash
programming
voltage booster
UART
(UART3)
2 Ch.
Synchronous
serial interface
(SPIA)
2 Ch.
I2C
(I2C)
1 Ch.
Sound generator
(SNDA)
IR remote
controller
(REMC3)
R/F converter
(RFC)
2 Ch.
12-bit A/D
converter
(ADC12A)
1 Ch.
VPP
USIN0–1
USOUT0–1
SDI0–1
SDO0–1
SPICLK0–1
#SPISS0–1
SDA0
SCL0
BZOUT
#BZOUT
REMO
CLPLS
RFIN0–1
REF0–1
SENA0–1
SENB0–1
#ADTRG0
ADIN00–07
VREFA0
FOUT
∗
OSC1
OSC2
OSC3
OSC4
EXOSC
VDD
VSS
VD1
DCLK
DSIO
DST2
System clock Interrupt request
Clock generator
(CLG)
IOSC
oscillator
OSC1
oscillator
OSC3
oscillator
EXOSC
input circuit
System reset controller
(SRC)
Power-on reset
(POR)
Brownout reset
(BOR)
Power generator
(PWG)
CPU core & debugger
(S1C17)
16-bit internal bus
Interrupt signal
Interrupt
controller
(ITC)
I/O port
(PPORT)
Watchdog timer
(WDT2)
Real-time clock
(RTCA)
Supply voltage
detector
(SVD3)
16-bit timer
(T16)
4 Ch.
16-bit PWM timer
(T16B)
2Ch.
Coprocessor bus
32-bit RAM bus
Instruction bus
* The pin configuration and peripheral circuit function depends on the model. For detailed information, refer to Section 1.3, “Pins.”
Figure 1.2.1 S1C17M20/M21/M22/M23/M24/M25 Block Diagram
∗
∗
S1C17M20/M21/M22/M23/M24/M25 Seiko Epson Corporation
TECHNICAL MANUAL (Rev. 1.0)
1-3
Page 17
1 OVERVIEW
P14/#ADTRG0/UPMUX
P15/CLPLS/UPMUX
P26/UPMUX/ADIN01
P32/RTC1S/UPMUX/EXSVD0
P03/#BZOUT/UPMUX
1.3 Pins
1.3.1 S1C17M20/M23 Pin Configuration Diagram
SQFN4-24
P00/EXCL00/UPMUX
DCLK/PD2
DSIO/PD1
DST2/PD0
VDD
#RESET
Port function
or signal
assignment
P01/EXCL01/UPMUX
P02/BZOUT/UPMUX
VPP
P12/REMO/UPMUX
P13/FOUT/UPMUX
Figure 1.3.1.1 S1C17M20/M23 Pin Configuration Diagram (SQFN4-24)
Pin
name
P01
P02
P03
PP
V
P12
P13
P00
PD2
PD1
1817161514
19
20
S1C17M20
21
22
S1C17M23
23
(Top View)
24
12345
VSS
P14
P15
VSS
PD0
P24
VDD
#RESET
13
6
P25
P26
12
VSS
11
10
9
8
7
VSS
VD1
VD1
P32
P31
P31/EXOSC/UPMUX
P30
P30/UPMUX/VREFA0
P27
P27/UPMUX/ADIN00
1-4
Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
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SQFN5-32
P14/#ADTRG0/UPMUX
P15/CLPLS/UPMUX
P22/UPMUX/ADIN05
P23/UPMUX/ADIN04
P26/UPMUX/ADIN01
P32/RTC1S/UPMUX/EXSVD0
P03/#BZOUT/UPMUX
P00/EXCL00/UPMUX
DCLK/PD2
DSIO/PD1
DST2/PD0
PD3/OSC3
PD4/OSC4
VDD
1 OVERVIEW
#RESET
Port function
or signal
assignment
P01/EXCL01/UPMUX
P02/BZOUT/UPMUX
P10/UPMUX
P11/UPMUX
VPP
P12/REMO/UPMUX
P13/FOUT/UPMUX
Figure 1.3.1.2 S1C17M20/M23 Pin Configuration Diagram (SQFN5-32)
Pin
name
P01
P02
P03
P10
P11
PP
V
P12
P13
P00
PD2
PD1
24232221201918
25
26
27
S1C17M20
28
29
S1C17M23
30
31
32
(Top View)
1234567
VSS
P14
P15
VSS
PD0
P22
PD3
P23
PD4
P24
VDD
#RESET
17
8
P25
P26
16
15
14
13
12
11
10
9
VSS
VD1
OSC2
OSC1
P32
P31
P30
P27
SS
V
VD1
OSC2
OSC1
P31/EXOSC/UPMUX
P30/UPMUX/VREFA0
P27/UPMUX/ADIN00
S1C17M20/M21/M22/M23/M24/M25 Seiko Epson Corporation
TECHNICAL MANUAL (Rev. 1.0)
1-5
Page 19
1 OVERVIEW
P14/#ADTRG0/UPMUX
P15/CLPLS/UPMUX
P22/UPMUX/ADIN05
P23/UPMUX/ADIN04
P24/EXCL10/UPMUX/ADIN03
P25/EXCL11/UPMUX/ADIN02
P26/UPMUX/ADIN01
P32/RTC1S/UPMUX/EXSVD0
P03/#BZOUT/UPMUX
1.3.2 S1C17M21/M24 Pin Configuration Diagram
TQFP12-32pin
P00/EXCL00/UPMUX
DCLK/PD2
DSIO/PD1
DST2/PD0
PD3/OSC3
PD4/OSC4
VDD
#RESET
P00
PD2
PD1
PD0
PD3
PD4
VDD
#RESET
Port function
or signal
assignment
P01/EXCL01/UPMUX
P02/BZOUT/UPMUX
P10/UPMUX
P11/UPMUX
VPP
P12/REMO/UPMUX
P13/FOUT/UPMUX
Pin name
P01
P02
P03
P10
P11
PP
V
P12
P13
24232221201918
25
26
27
28
29
30
31
32
S1C17M21
S1C17M24
1
2
3
4
17
16
15
14
13
12
11
10
9
5
6
7
8
VSS
VD1
OSC2
OSC1
P32
P31
P30
P27
VSS
VD1
OSC2
OSC1
P31/EXOSC/UPMUX
P30/UPMUX/VREFA0
P27/UPMUX/ADIN00
VSS
P14
P15
P22
P23
P24
P25
P26
VSS
Figure 1.3.2.1 S1C17M21/M24 Pin Configuration Diagram (TQFP12-32pin)
1-6
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TECHNICAL MANUAL (Rev. 1.0)
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1.3.3 S1C17M22/M25 Pin Configuration Diagram
P14/#ADTRG0/UPMUX
P15/CLPLS/UPMUX
P20/UPMUX/ADIN07
P21/UPMUX/ADIN06
P22/UPMUX/ADIN05
P23/UPMUX/ADIN04
P24/EXCL10/UPMUX/ADIN03
P25/EXCL11/UPMUX/ADIN02
P26/UPMUX/ADIN01
P32/RTC1S/UPMUX/EXSVD0
P04/RFCLKO0/UPMUX
P05/RFCLKO1/UPMUX
TQFP12-48pin
P00/EXCL00/UPMUX
DCLK/PD2
DSIO/PD1
DST2/PD0
P42/RFIN1
P41/REF1
P40/SENA1
P37/SENB1/UPMUX
PD3/OSC3
PD4/OSC4
VDD
#RESET
P00
PD2
PD1
PD0
P42
P41
P40
P37
PD3
PD4
VDD
#RESET
Port function
or signal
P01/EXCL01/UPMUX
assignment
P02/BZOUT/UPMUX
P03/#BZOUT/UPMUX
P10/UPMUX
P06/UPMUX
P07/UPMUX
P11/UPMUX
P12/REMO/UPMUX
P13/FOUT/UPMUX
VPP
Pin name
P01
P02
P03
P10
P04
P05
P06
P07
P11
PP
V
P12
P13
3635343332313029282726
37
38
39
40
41
42
43
44
45
46
47
48
S1C17M22
S1C17M25
1234567891011
25
12
24
23
22
21
20
19
18
17
16
15
14
13
VSS
VD1
OSC2
OSC1
P36
P35
P34
P33
P32
P31
P30
P27
1 OVERVIEW
VSS
VD1
OSC2
OSC1
P36/RFIN0/UPMUX
P35/REF0/UPMUX
P34/SENA0/UPMUX
P33/SENB0/UPMUX
P31/EXOSC/UPMUX
P30/UPMUX/VREFA0
P27/UPMUX/ADIN00
VSS
P16
P17
P20
P21
P22
P23
P24
P25
P14
P15
VSS
P16/UPMUX
P17/UPMUX
P26
Figure 1.3.3.1 S1C17M22/M25 Pin Configuration Diagram (TQFP12-48pin)
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1 OVERVIEW
1.3.4 Pin Descriptions
Symbol meanings
Assigned signal: The signal listed at the top of each pin is assigned in the initial state. The pin function must be
switched via software to assign another signal (see the “I/O Ports” chapter).
I/O: I = Input
O = Output
I/O = Input/output
P = Power supply
A = Analog signal
Hi-Z = High impedance state
Initial state: I (Pull-up) = Input with pulled up
I (Pull-down) = Input with pulled down
Hi-Z = High impedance state
O (H) = High level output
O (L) = Low level output
Tolerant fail-safe structure:
✓ = Over voltage tolerant fail-safe type I/O cell included (see the “I/O Ports” chapter)
Table 1.3.4.1 Pin description
Pin/pad
name
VDD VDD P – – Power supply (+) ✓ ✓ ✓
SS VSS P – – GND ✓ ✓ ✓
V
PP VPP P – – Power supply for Flash programming ✓ ✓ ✓
V
D1 VD1 A – – VD1 regulator output ✓ ✓ ✓
V
OSC1 OSC1 A – – OSC1 oscillator circuit input – ✓ ✓
OSC2 OSC2 A – – OSC1 oscillator circuit output – ✓ ✓
#RESET #RESET I I (Pull-up)
P00 P00 I/O Hi-Z ✓ I/O port ✓ ✓ ✓
P01 P01 I/O Hi-Z ✓ I/O port ✓ ✓ ✓
P02 P02 I/O Hi-Z ✓ I/O port ✓ ✓ ✓
P03 P03 I/O Hi-Z ✓ I/O port ✓ ✓ ✓
P04 P04 I/O Hi-Z ✓ I/O port – – ✓
P05 P05 I/O Hi-Z ✓ I/O port – – ✓
P06 P06 I/O Hi-Z ✓ I/O port – – ✓
P07 P07 I/O Hi-Z ✓ I/O port – – ✓
P10 P10 I/O Hi-Z ✓ I/O port – ✓ ✓
P11 P11 I/O Hi-Z ✓ I/O port – ✓ ✓
P12 P12 I/O Hi-Z ✓ I/O port ✓ ✓ ✓
Assigned
signal
EXCL00 I 16-bit PWM timer Ch.0 event counter input 0 ✓ ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓ ✓
EXCL01 I 16-bit PWM timer Ch.0 event counter input 1 ✓ ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓ ✓
BZOUT O Sound generator output ✓ ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓ ✓
#BZOUT O Sound generator inverted output ✓ ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓ ✓
RFCLKO0 O R/F converter Ch.0 clock monitor output – – ✓
UPMUX I/O User-selected I/O (universal port multiplexer) – – ✓
RFCLKO1 O R/F converter Ch.1 clock monitor output – – ✓
UPMUX I/O User-selected I/O (universal port multiplexer) – – ✓
UPMUX I/O User-selected I/O (universal port multiplexer) – – ✓
UPMUX I/O User-selected I/O (universal port multiplexer) – – ✓
UPMUX I/O User-selected I/O (universal port multiplexer) – ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) – ✓ ✓
REMO O IR remote controller transmit data output ✓ ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓ ✓
I/O Initial state
Tolerant
fail-safe
structure
–
Function
Reset input ✓ ✓ ✓
(32-pin)
M20/M23 (24-pin)
M20/M23
M21/M24
M22/M25 (48-pin)
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1 OVERVIEW
Pin/pad
name
P13 P13 I/O Hi-Z ✓ I/O port ✓ ✓ ✓
P14 P14 I/O Hi-Z ✓ I/O port ✓ ✓ ✓
P15 P15 I/O Hi-Z ✓ I/O port ✓ ✓ ✓
P16 P16 I/O Hi-Z ✓ I/O port – – ✓
P17 P17 I/O Hi-Z ✓ I/O port – – ✓
P20 P20 I/O Hi-Z
P21 P21 I/O Hi-Z
P22 P22 I/O Hi-Z
P23 P23 I/O Hi-Z
P24 P24 I/O Hi-Z
P25 P25 I/O Hi-Z
P26 P26 I/O Hi-Z
P27 P27 I/O Hi-Z
P30 P30 I/O Hi-Z
P31 P31 I/O Hi-Z ✓ I/O port ✓ ✓ ✓
P32 P32 I/O Hi-Z ✓ I/O port ✓ ✓ ✓
P33 P33 I/O Hi-Z ✓ I/O port – – ✓
P34 P34 I/O Hi-Z ✓ I/O port – – ✓
P35
Assigned
signal
FOUT O Clock external output ✓ ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓ ✓
#ADTRG0 I 12-bit A/D converter Ch.0 trigger input ✓ ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓ ✓
CLPLS O IR remote controller clear pulse output ✓ ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) – – ✓
UPMUX I/O User-selected I/O (universal port multiplexer) – – ✓
UPMUX I/O User-selected I/O (universal port multiplexer) – – ✓
ADIN07 A 12-bit A/D converter Ch.0 analog signal input 7 – – ✓
UPMUX I/O User-selected I/O (universal port multiplexer) – – ✓
ADIN06 A 12-bit A/D converter Ch.0 analog signal input 6 – – ✓
UPMUX I/O User-selected I/O (universal port multiplexer) – ✓ ✓
ADIN05 A 12-bit A/D converter Ch.0 analog signal input 5 – ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) – ✓ ✓
ADIN04 A 12-bit A/D converter Ch.0 analog signal input 4 – ✓ ✓
EXCL10 I 16-bit PWM timer Ch.1 event counter input 0 ✓ ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓ ✓
ADIN03 A 12-bit A/D converter Ch.0 analog signal input 3 ✓ ✓ ✓
EXCL11 I 16-bit PWM timer Ch.1 event counter input 1 ✓ ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓ ✓
ADIN02 A 12-bit A/D converter Ch.0 analog signal input 2 ✓ ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓ ✓
ADIN01 A 12-bit A/D converter Ch.0 analog signal input 1 ✓ ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓ ✓
ADIN00 A 12-bit A/D converter Ch.0 analog signal input 0 ✓ ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓ ✓
VREFA0 A 12-bit A/D converter Ch.0 reference voltage input ✓ ✓ ✓
EXOSC I Clock generator external clock input ✓ ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓ ✓
RTC1S O Real-time clock 1-second cycle pulse output ✓ ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓ ✓
EXSVD0 A External power supply voltage detection input ✓ ✓ ✓
SENB0 A R/F converter Ch.0 sensor B oscillator pin – – ✓
UPMUX I/O User-selected I/O (universal port multiplexer) – – ✓
SENA0 A R/F converter Ch.0 sensor A oscillator pin – – ✓
UPMUX I/O User-selected I/O (universal port multiplexer) – – ✓
P35 I/O Hi-Z ✓ I/O port – – ✓
REF0 A R/F converter Ch.0 r
UPMUX I/O User-selected I/O (universal port multiplexer) – – ✓
I/O Initial state
Tolerant
fail-safe
structure
–
–
–
–
–
–
–
–
–
Function
I/O port – – ✓
I/O port – – ✓
I/O port – ✓ ✓
I/O port – ✓ ✓
I/O port ✓ ✓ ✓
I/O port ✓ ✓ ✓
I/O port ✓ ✓ ✓
I/O port ✓ ✓ ✓
I/O port ✓ ✓ ✓
eference oscillator pin – – ✓
(32-pin)
M20/M23 (24-pin)
M20/M23
M21/M24
M22/M25 (48-pin)
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1 OVERVIEW
Pin/pad
name
P36 P36 I/O Hi-Z ✓ I/O port – – ✓
P37 P37 I/O Hi-Z ✓ I/O port – – ✓
P40 P40 I/O Hi-Z ✓ I/O port – – ✓
P41 P41 I/O Hi-Z ✓ I/O port – – ✓
P42 P42 I/O Hi-Z ✓ I/O port – – ✓
PD0 DST2 O O (L) ✓ On-chip debugger status output ✓ ✓ ✓
PD1 DSIO I/O I (Pull-up) ✓ On-chip debugger data input/output ✓ ✓ ✓
PD2 DCLK O O (H) – On-chip debugger clock output ✓ ✓ ✓
PD3 PD3 I/O Hi-Z ✓ I/O port – ✓ ✓
PD4 PD4 I/O Hi-Z ✓ I/O port – ✓ ✓
Assigned
signal
RFIN0 A R/F converter Ch.0 oscillation input – – ✓
UPMUX I/O User-selected I/O (universal port multiplexer) – – ✓
SENB1 A R/F converter Ch.1 sensor B oscillator pin – – ✓
UPMUX I/O User-selected I/O (universal port multiplexer) – – ✓
SENA1 A R/F converter Ch.1 sensor A oscillator pin – – ✓
REF1 A R/F converter Ch.1 reference oscillator pin – – ✓
RFIN1 A R/F converter Ch.1 oscillation input – – ✓
PD0 I/O I/O port ✓ ✓ ✓
PD1 I/O I/O port ✓ ✓ ✓
PD2 O Output port ✓ ✓ ✓
OSC3 A OSC3 oscillator circuit input – ✓ ✓
OSC4 A OSC3 oscillator circuit output – ✓ ✓
I/O Initial state
Tolerant
fail-safe
structure
Function
(32-pin)
M20/M23 (24-pin)
M20/M23
M21/M24
Note: In the peripheral circuit descriptions, the assigned signal name is used as the pin name.
M22/M25 (48-pin)
Universal port multiplexer (UPMUX)
The universal port multiplexer (UPMUX) allows software to select the peripheral circuit input/output function
to be assigned to each pin from those listed below.
Table 1.3.4.2 Peripheral Circuit Input/output Function Selectable by UPMUX
Peripheral circuit Signal to be assigned I/O Channel number n Function
Synchronous serial
interface (SPIA)
2
C (I2C) SCLn I/O
I
UART (UART3) USINn I
16-bit PWM timer (T16B) TOUTn0/CAPn0 I/O
SDIn I
SDOn O SPIA Ch.n data output
SPICLKn I/O SPIA Ch.n clock input/output
#SPISSn I SPIA Ch.n slave-select input
SDAn I/O I2C Ch.n data input/output
USOUTn O UART3 Ch.n data output
TOUTn1/CAPn1 I/O T16B Ch.n PWM output/capture input 1
Note: Do not assign a function to two or more pins simultaneously.
n = 0, 1
n = 0
n = 0, 1
n = 0, 1
SPIA Ch.n data input
I2C Ch.n clock input/output
UART3 Ch.n data input
T16B Ch.n PWM output/capture input 0
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2 POWER SUPPLY, RESET, AND CLOCKS
2 Power Supply, Reset, and Clocks
The power supply, reset, and clocks in this IC are managed by the embedded power generator, system reset controller, and clock generator, respectively.
2.1 Power Generator (PWG)
2.1.1 Overview
PWG is the power generator that controls the internal power supply system to drive this IC with stability and low
power. The main features of PWG are outlined below.
• Embedded V
- The V
consumption constant independent of the V
- The V
lator into economy mode at light loads helps achieve low-power operations.
Figure 2.1.1.1 shows the PWG configuration.
D1 regulator
D1 regulator generates the VD1 voltage to drive internal circuits, this makes it possible to keep current
DD voltage level.
D1 regulator supports two operation modes, normal mode and economy mode, and setting the VD1 regu-
PWG
REGMODE[1:0]
CPW1
CPW2
VDD
+
VD1
VSS
Figure 2.1.1.1 PWG Configuration
VD1
regulator
VD1
Internal circuits
2.1.2 Pins
Table 2.1.2.1 lists the PWG pins.
Table 2.1.2.1 List of PWG Pins
Pin name I/O Initial status Function
VDD P – Power supply (+)
V
SS P – GND
V
D1 A – Embedded regulator output pin
For the VDD operating voltage range and recommended external parts, refer to “Recommended Operating Conditions, Power supply voltage V
DD” in the “Electrical Characteristics” chapter and the “Basic External Connection
Diagram” chapter, respectively.
2.1.3 VD1 Regulator Operation Mode
The VD1 regulator supports two operation modes, normal mode and economy mode. Setting the VD1 regulator into
economy mode at light loads helps achieve low-power operations. Table 2.1.3.1 lists examples of light load conditions in which economy mode can be set.
Table 2.1.3.1 Examples of Light Load Conditions in which Economy Mode Can be Set
Light load condition Exceptions
SLEEP mode (when all oscillators are stopped, or OSC1 only is active) When a clock source except for OSC1 is
HALT mode (when OSC1 only is active)
RUN mode (when OSC1 only is active)
active
The VD1 regulator also supports automatic mode in which the hardware detects a light load condition and automatically switches between normal mode and economy mode. Use the V
D1 regulator in automatic mode when no special
control is required.
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Supply v
ipheral circuits
ipheral circuits
2.2 System Reset Controller (SRC)
2.2.1 Overview
SRC is the system reset controller that resets the internal circuits according to the requests from the reset sources to
archive steady IC operations. The main features of SRC are outlined below.
• Embedded reset hold circuit maintains reset state to boot the system safely while the internal power supply is unstable after power on or the oscillation frequency is unstable after the clock source is initiated.
• Supports reset requests from multiple reset sources.
- #RESET pin
- POR and BOR
- Key-entry reset
- Watchdog timer reset
- Supply voltage detector reset
- Peripheral circuit software reset (supports some peripheral circuits only)
• The CPU registers and peripheral circuit control bits will be reset with an appropriate initialization condition according to changes in status.
Figure 2.2.1.1 shows the SRC configuration.
Clock generator
#RESET
Key-entry reset
Watchdog timer reset
oltage detector reset
Software reset 0
Software reset n
SRC
V
VSS
DD
Reset request
signals
Noise filter
POR
BOR
Boot clock
IOSCCLK
Reset hold
circuit
Reset
decoder
Internal reset signals
(Reset group)
SYSRST_H0
SYSRST_H1
SYSRST_S0_0
SYSRST_S0_n
To CPU and per
To CPU and per
To peripheral circuit 0
To peripheral circuit n
Figure 2.2.1.1 SRC Configuration
2.2.2 Input Pin
Table 2.2.2.1 shows the SRC pin.
Table 2.2.2.1 SRC Pin
Pin name I/O Initial status Function
#RESET I I (Pull-up) Reset input
The #RESET pin is connected to the noise filter that removes pulses not conforming to the requirements. An internal pull-up resistor is connected to the #RESET pin, so the pin can be left open. For the #RESET pin characteristics, refer to “#RESET pin characteristics” in the “Electrical Characteristics” chapter.
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2 POWER SUPPLY, RESET, AND CLOCKS
Inter
UN state
X RST RU N
V
2.2.3 Reset Sources
The reset source refers to causes that request system initialization. The following shows the reset sources.
#RESET pin
Inputting a reset signal with a certain low level period to the #RESET pin issues a reset request.
POR and BOR
POR (Power On Reset) issues a reset request when the rise of VDD is detected. BOR (Brownout Reset) issues
a reset request when a certain V
system will be reset properly when the power is turned on and the supply voltage is out of the operating voltage
range. Figure 2.2.3.1 shows an example of POR and BOR internal reset operation according to variations in V
DD voltage level is detected. Reset requests from these circuits ensure that the
DD.
DD
VRST+
VRST- VRST- VRST-
VSS
nal state
X X XRST RSTRSTRST RUN RUN RUN
VRST-: Reset detection voltage VRST+: Reset canceling voltage Indefinite (operating limit) RESET state CPU R
Figure 2.2.3.1 Example of Internal Reset by POR and BOR
VRST+
For the POR and BOR electrical specifications, refer to “POR/BOR characteristics” in the “Electrical Charac-
teristics” chapter.
Key-entry reset
Inputting a low level signal of a certain period to the I/O port pins configured to a reset input issues a reset re-
quest. This function must be enabled using an I/O port register. For more information, refer to the “I/O Ports”
chapter.
Watchdog timer reset
Setting the watchdog timer into reset mode will issue a reset request when the counter overflows. This helps return the runaway CPU to a normal operating state. For more information, refer to the “Watchdog timer” chapter.
Supply voltage detector reset
By enabling the low power supply voltage detection reset function, the supply voltage detector will issue a reset
request when a drop in the power supply voltage is detected. This makes it possible to put the system into reset
state if the IC must be stopped under a low voltage condition. For more information, refer to the “Supply Voltage Detector” chapter.
Peripheral circuit software reset
Some peripheral circuits provide a control bit for software reset (MODEN or SFTRST). Setting this bit initial-
izes the peripheral circuit control bits. Note, however, that the software reset operations depend on the peripheral circuit. For more information, refer to “Control Registers” in each peripheral circuit chapter.
Note: The MODEN bit of some peripheral circuits does not issue software reset.
2.2.4 Initialization Conditions (Reset Groups)
A different initialization condition is set for the CPU registers and peripheral circuit control bits, individually. The
reset group refers to an initialization condition. Initialization is performed when a reset source included in a reset
group issues a reset request. Table 2.2.4.1 lists the reset groups. For the reset group to initialize the registers and control bits, refer to the “CPU and Debugger” chapter or “Control Registers” in each peripheral circuit chapter.
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Table 2.2.4.1 List of Reset Groups
Reset group Reset source Reset cancelation timing
H0 #RESET pin
POR and BOR
Key-entry reset
Supply voltage detector reset
Watchdog timer reset
H1 #RESET pin
POR and BOR
S0 Peripheral circuit software reset
(MODEN and SFTRST bits. The
software reset operations depend on the peripheral circuit.
Reset state is maintained for the reset
hold time t
canceled.
Reset state is canceled immediately
after the reset request is canceled.
RSTR after the reset request is
2.3 Clock Generator (CLG)
2.3.1 Overview
CLG is the clock generator that controls the clock sources and manages clock supply to the CPU and the peripheral
circuits. The main features of CLG are outlined below.
• Supports multiple clock sources.
- IOSC oscillator circuit that oscillates with a fast startup and no external parts required
- Low-power OSC1 oscillator circuit in which the oscillator type can be specified from high-precision 32.768
kHz crystal oscillator (an external resonator is required) and internal oscillator
- High-speed OSC3 oscillator circuit in which the oscillator type can be specified from crystal/ceramic oscillator (an external resonator is required) and internal oscillator
- EXOSC clock input circuit that allows input of square wave and sine wave clock signals
• The system clock (SYSCLK), which is used as the operating clock for the CPU and bus, and the peripheral circuit operating clocks can be configured individually by selecting the suitable clock source and division ratio.
• IOSCCLK output from the IOSC oscillator circuit is used as the boot clock for fast booting.
• Controls the oscillator and clock input circuits to enable/disable according to the operating mode, RUN or
SLEEP mode.
• Provides a flexible system clock switching function at SLEEP mode cancelation.
- The clock sources to be stopped in SLEEP mode can be selected.
- SYSCLK to be used at SLEEP mode cancelation can be selected from all clock sources.
- The oscillator and clock input circuit on/off state can be maintained or changed at SLEEP mode cancelation.
•
Provides the FOUT function to output an internal clock for driving external ICs or for monitoring the internal state.
Figure 2.3.1.1 shows the CLG configuration.
Table 2.3.1.1 CLG Configuration of S1C17M20/M21/M22/M23/M24/M25
Item
IOSC oscillator circuit Available Available Available
OSC1 crystal oscillator circuit Unavailable Available Available
OSC1 internal oscillator circuit Available Available Available
OSC3 crystal/ceramic oscillator circuit Unavailable Available Available
OSC3 internal oscillator circuit Available Available Available
EXOSC clock input Available Available Available
24-pin package 32-pin package
S1C17M20/M23
S1C17M21/M22/M24/M25
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X’tal3/Ceramic3
X’tal1
( )( )
OSC1
OSC2
OSC3
OSC4
CLG
EXOSCEN
IOSCEN
IOSC
oscillator
circuit
OSC1EN
OSC1
oscillator
circuit
OSC3EN
OSC3
oscillator
circuit
IOSCCLK
OSC1CLK
OSC3CLK
Divider
Divider
Divider
2 POWER SUPPLY, RESET, AND CLOCKS
CLKSRC[1:0]
CLKDIV[1:0]
WUPSRC[1:0]
WUPDIV[1:0]
WUPMD
Clock
selector
System
clock
controller
SLEEP, WAKE-UP
SYSCLK
To CPU and bus
Internal data bus
EXOSC
FOUT
EXOSC
clock input
circuit
FOUTEN
FOUT
output
circuit
FOUTDIV[2:0]
EXOSCCLK
Clock
selector
Clock
selector
Peripheral circuit 1
CLKSRC[x:0]
CLKDIV[x:0]
Peripheral circuit n
CLKSRC[x:0]
CLKDIV[x:0]
Figure 2.3.1.1 CLG Configuration
2.3.2 Input/Output Pins
Table 2.3.2.1 lists the CLG pins.
Table 2.3.2.1 List of CLG Pins
Pin name I/O* Initial status* Function
OSC1 A – OSC1 oscillator circuit input
OSC2 A – OSC1 oscillator circuit output
OSC3 A – OSC3 oscillator circuit input
OSC4 A – OSC3 oscillator circuit output
EXOSC I I EXOSC clock input
FOUT O O (L) FOUT clock output
* Indicates the status when the pin is configured for CLG.
If the port is shared with the CLG input/output function and other functions, the CLG function must be assigned to
the port. For more information, refer to the “I/O Ports” chapter.
2.3.3 Clock Sources
IOSC oscillator circuit
The IOSC oscillator circuit features a fast startup and no external parts are required for oscillating. Figure 2.3.3.1
shows the configuration of the IOSC oscillator circuit.
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Internal data bus
IOSC oscillator circuit
IOSCEN
Clock
oscillator
IOSCSTAIE IOSCSTAIF
Oscillation
stabilization
waiting circuit
Interrupt
control circuit
IOSCCLK
Interrupt
controller
Figure 2.3.3.1 IOSC Oscillator Circuit Configuration
The IOSC oscillator circuit output clock IOSCCLK is used as SYSCLK at booting. For the oscillation charac-
teristics, refer to “IOSC oscillator circuit characteristics” in the “Electrical Characteristics” chapter.
OSC1 oscillator circuit
The OSC1 oscillator circuit is a low-power oscillator circuit that allows software to select the oscillator type
from two different types shown below. Figure 2.3.3.2 shows the configuration of the OSC1 oscillator circuit.
Crystal oscillator
This oscillator circuit includes a gain-controlled oscillation inverter and a variable gate capacitor allowing use
of various crystal resonators (32.768 kHz typ.) with ranges from cylinder type through surface-mount type.
The oscillator circuit also includes a feedback resistor and a drain resistor, so no external parts are required
except for a crystal resonator. The embedded oscillation stop detector, which detects oscillation stop and restarts the oscillator, allows the system to operate in safety under adverse environments that may stop the oscillation. The oscillation startup control circuit operates for a set period of time after the oscillation is enabled to
assist the oscillator in initiating, this mak
Note: Depending on the circuit board or the crystal resonator type used, an external gate capacitor C
and a drain capacitor C
D1 may be required.
es it possible to use a low-power resonator that is difficult to start up.
G1
Internal oscillator
This 32 kHz oscillator circuit operates without any external parts.
When the internal oscillator circuit is used, the OSC1 and OSC3 pins must be left open.
OSC1 oscillator circuit
External gate
capacitor C
( )( )
External drain
capacitor C
G1
X’tal1
D1
OSC1
OSC2
Selector
Crystal oscillator
Internal variable
gate capacitor C
Internal drain capacitor CDI1
Internal oscillator
OSC1SELCR
OSC1EN
OSC1BUP
CGI1[2:0]
GI1
Feedback
resistor R
INV1N[1:0]
Oscillation startup
control circuit
F1
Clock
oscillator
OSC1 oscillator circuit
voltage regulator
INV1B[1:0] OSDRB OSDEN
Restart
signal
stop detector
Gain-controlled
oscillation
inverter
resistor R
Drain
Noise filter
D1
Oscillation
OSC1WT[1:0]
Oscillation
stabilization
waiting circuit
OSC1STPIE OSC1STPIF
OSC1STAIE OSC1STAIF
Interrupt
control circuit
Internal data bus
OSC1CLK
Interrupt
controller
Figure 2.3.3.2 OSC1 Oscillator Circuit Configuration
For the recommended parts and the oscillation characteristics, refer to the “Basic External Connection Dia-
gram” chapter and “OSC1 oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respectively.
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2 POWER SUPPLY, RESET, AND CLOCKS
OSC3 oscillator circuit
EXOSCCLK
OSC3 oscillator circuit
The OSC3 oscillator circuit is a high-speed oscillator circuit that allows software to select the oscillator type
from two different types shown below. Figure 2.3.3.3 shows the configuration of the OSC3 oscillator circuit.
Crystal/ceramic oscillator
This oscillator circuit includes a feedback resistor and a drain resistor, so no external part is required except
for a crystal/ceramic resonator. The embedded gain-controlled inverter allows selection of the resonator
from a wide frequency range.
Internal oscillator
This oscillator circuit features a fast startup and no external parts are required for oscillating. The
OSC3CLK frequency can be selected using the CLGOSC3.OSC3FQ[1:0] bits. This oscillator circuit
is equipped with an auto-trimming function that automatically adjusts the frequency. This helps reduce
frequency deviation due to unevenness in manufacturing quality, temperature, and changes in voltage. For
more information on the auto-trimming function, refer to “OSC3 oscillation auto-trimming function” in this
chapter.
OSC3MD
OSC3EN
Crystal/ceramic oscillator
controlled
inverter
Feedback
resistor R
Internal oscillator
OSC3FQ[1:0]
Gain-
F3
Drain resistor
OSC3INV[1:0]
D3
R
oscillator
trimming
OSC3STM
Clock
Auto-
circuit
Noise
filter
OSC3WT[2:0]
Oscillation
stabilization
waiting circuit
OSC3STAIE OSC3STAIF
Interrupt
control
circuit
OSC3TEDIFOSC3TEDIE
Internal data bus
OSC3CLK
Interrupt
controller
External gate
capacitor C
( )( )
External drain
capacitor C
G3
OSC3
X’tal3/
Ceramic3
OSC4
D3
oscillator
OSC1
circuit
Internal gate
capacitor C
Peripheral
I/O
I/O
port
function 4
Internal drain
capacitor C
OSC1CLK
GI3C
Selector
SS
V
VSS
DI3C
Figure 2.3.3.3 OSC3 Oscillator Circuit Configuration
For the recommended parts and the oscillation characteristics, refer to the “Basic External Connection Diagram”
chapter and “OSC3 oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respectively.
EXOSC clock input
EXOSC is an external clock input circuit that supports square wave and sine wave clocks. Figure 2.3.3.4 shows
the configuration of the EXOSC clock input circuit.
EXOSC clock
input circuit
EXOSCEN
EXOSC
Input control
Internal data bus
circuit
Figure 2.3.3.4 EXOSC Clock Input Circuit
EXOSC has no oscillation stabilization waiting circuit included, therefore, it must be enabled when a stabilized
clock is being supplied. For the input clock characteristics, refer to “EXOSC external clock input characteristics” in the “Electrical Characteristics” chapter.
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Oscillation stabilization w
System supply waiting time
Oscillation stabilization waiting time
Normal operation
Oscillator circuit enable
2.3.4 Operations
Oscillation start time and oscillation stabilization waiting time
The oscillation start time refers to the time after the oscillator circuit is enabled until the oscillation signal is ac-
tually sent to the internal circuits. The oscillation stabilization waiting time refers to the time it takes the clock
to stabilize after the oscillation starts. To avoid malfunctions of the internal circuits due to an unstable clock
during this period, the oscillator circuit includes an oscillation stabilization waiting circuit that can disable supplying the clock to the system until the designated time has elapsed. Figure 2.3.4.1 shows the relationship between the oscillation start time and the oscillation stabilization waiting time.
Oscillator circuit enable
(∗OSC∗EN)
Oscillation waveform
Digitized oscillation waveform
Oscillator circuit output clock
(∗OSC∗CLK)
aiting completion flag
(∗OSC∗STAIF)
Figure 2.3.4.1 Oscillation Start Time and Oscillation Stabilization Waiting Time
Oscillation start time
The oscillation stabilization waiting times for the OSC1 and OSC3 oscillator circuits can be set using the
CLGOSC1.OSC1WT[1:0] bits and CLGOSC3.OSC3WT[2:0] bits, respectively. To check whether the oscillation stabilization waiting time is set properly and the clock is stabilized immediately after the oscillation starts
or not, monitor the oscillation clock using the FOUT output function. The oscillation stabilization waiting time
for the IOSC oscillator circuit is fixed at 16 IOSCCLK clocks. The oscillation stabilization waiting time for the
OSC1 oscillator circuit should be set to 16,384 OSC1CLK clocks or more when crystal oscillator is selected, or
4,096 OSC1CLK clocks or more when internal oscillator is selected. The oscillation stabilization waiting time
for the OSC3 oscillator circuit should be set to 1,024 OSC3CLK clocks or more when crystal/ceramic oscillator
is selected, or four OSC3CLK clocks or more when internal oscillator is selected.
When the oscillation stabilization waiting operation has completed, the oscillator circuit sets the oscillation sta-
bilization waiting completion flag and starts clock supply to the internal circuits.
Note: The oscillation stabilization waiting time is always expended at start of oscillation even if the os-
cillation stabilization waiting completion flag has not be cleared to 0.
When the oscillation startup control circuit in the OSC1 crystal oscillator circuit is enabled by setting the
CLGOSC1.OSC1BUP bit to 1, it uses the high-gain oscillation inverter for a set period of time (startup boosting
operation) after the oscillator circuit is enabled (by setting the CLGOSC.OSC1EN bit to 1) to reduce oscillation
start time. Note, however, that the oscillation operation may become unstable if there is a large gain differential
between normal operation and startup boosting operation. Furthermore, the oscillation start time being actually
reduced depends on the characteristics of the resonator used. Figure 2.3.4.2 shows an operation example when the
oscillation startup control circuit is used.
(1) CLGOSC1.OSC1BUP bit = 0 (startup boosting operation disabled)
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(CLGOSC.OSC1EN)
Oscillation inverter
Oscillation waveform
INV1N[1:0] setting gain
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operation
Oscillator circuit enable
(2) CLGOSC1.OSC1BUP bit = 1 (startup boosting operation enabled)
(CLGOSC.OSC1EN)
Oscillation inverter
Oscillation waveform
Figure 2.3.4.2 Operation Example when the OSC1 Crystal Oscillation Startup Control Circuit is Used
INV1N[1:0] setting gainINV1B[1:0] setting gain
Normal operationStartup boosting
Oscillation start procedure for the IOSC oscillator circuit
Follow the procedure shown below to start oscillation of the IOSC oscillator circuit.
1. Write 1 to the CLGINTF.IOSCSTAIF bit. (Clear interrupt flag)
2. Write 1 to the CLGINTE.IOSCSTAIE bit. (Enable interrupt)
3. Write 1 to the CLGOSC.IOSCEN bit. (Start oscillation)
4. IOSCCLK can be used if the CLGINTF.IOSCSTAIF bit = 1 after an interrupt occurs.
Oscillation start procedure for the OSC1 oscillator circuit
Follow the procedure shown below to start oscillation of the OSC1 oscillator circuit.
1. Write 1 to the CLGINTF.OSC1STAIF bit. (Clear interrupt flag)
2. Write 1 to the CLGINTE.OSC1STAIE bit. (Enable interrupt)
3. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
4. Configure the following CLGOSC1 register bits:
- CLGOSC1.OSC1SELCR bit (Select oscillator type)
- CLGOSC1.OSC1WT[1:0] bits (Set oscillation stabilization waiting time)
In addition to the above, configure the following bits when using the crystal oscillator:
- CLGOSC1.INV1N[1:0] bits (Set oscillation inverter gain)
- CLGOSC1.CGI1[2:0] bits (Set internal gate capacitor)
- CLGOSC1.INV1B[1:0] bits (Set oscillation inverter gain for startup boosting period)
- CLGOSC1.OSC1BUP bit (Enable/disable oscillation startup control circuit)
5. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
6. Write 1 to the CLGOSC.OSC1EN bit. (Start oscillation)
7. OSC1CLK can be used if the CLGINTF.OSC1STAIF bit = 1 after an interrupt occurs.
The setting values of the CLGOSC1.INV1N[1:0], CLGOSC1.CGI1[2:0], CLGOSC1.OSC1WT[1:0], and
CLGOSC1.INV1B[1:0] bits should be determined after performing evaluation using the populated circuit board.
Note: Make sure the CLGOSC.OSC1EN bit is set to 0 (while the OSC3 oscillation is halted) when
switching the oscillator within two types.
Oscillation start procedure for the OSC3 oscillator circuit
Follow the procedure shown below to start oscillation of the OSC3 oscillator circuit.
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1. Write 1 to the CLGINTF.OSC3STAIF bit. (Clear interrupt flag)
2. Write 1 to the CLGINTE.OSC3STAIE bit. (Enable interrupt)
3. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
4. Configure the following CLGOSC3 register bits:
- CLGOSC3.OSC3MD bit (Select oscillator type)
- CLGOSC3.OSC3WT[2:0] bits (Set oscillation stabilization waiting time)
In addition to the above, configure the following bits when using the crystal/ceramic oscillator:
- CLGOSC3.OSC3INV[1:0] bits (Set oscillation inverter gain)
Configure the following bits when using the internal oscillator:
- CLGOSC3.OSC3FQ[1:0] bits (Select oscillation frequency)
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(1) When the CLGOSC.OSC1SLPC bit = 1
(2)
SLEEP mode as the clock is being supplied.
5. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
6. When using the crystal/ceramic oscillator, assign the OSC3 oscillator input/output functions to the ports.
(Refer to the “I/O Ports” chapter.)
7. Write 1 to the CLGOSC.OSC3EN bit. (Start oscillation)
8. OSC3CLK can be used if the CLGINTF.OSC3STAIF bit = 1 after an interrupt occurs.
The setting values of the CLGOSC3.OSC3INV[1:0] and CLGOSC3.OSC3WT[2:0] bits should be determined
after performing evaluation using the populated circuit board.
Note: Make sure the CLGOSC.OSC3EN bit is set to 0 (while the OSC3 oscillation is halted) when
switching the oscillator within two types.
System clock switching
The CPU boots using IOSCCLK as SYSCLK. After booting, the clock source of SYSCLK can be switched according to the processing speed required. The SYSCLK frequency can also be set by selecting the clock source
vision ratio, this makes it possible to run the CPU at the most suitable performance for the process to be ex-
di
ecuted. The CLGSCLK.CLKSRC[1:0] and CLGSCLK.CLKDIV[1:0] bits are used for this control.
The CLGSCLK register bits are protected against writings by the system protect function, therefore, the system
protection must be removed by writing 0x0096 to the MSCPROT.PROT[15:0] bits before the register setting can
be altered. For the transition between the operating modes including the system clock switching, refer to “Oper
ating Mode.”
Clock control in SLEEP mode
The CPU enters SLEEP mode when it executes the slp instruction. Whether the clock sources being operated
are stopped or not at this point can be selected in each source individually. This allows the CPU to fast switch
between SLEEP mode and RUN mode, and the peripheral circuits to continue operating without disabling
the clock in SLEEP mode. The CLGOSC.IOSCSLPC, CLGOSC.OSC1SLPC, CLGOSC.OSC3SLPC, and
CLGOSC.EXOSCSLPC bits are used for this control. Figure 2.3.4.3 shows a control example.
(CPU operating clock)
When the CLGOSC.OSC1SLPC bit = 0
(CPU operating clock)
SYSCLK
RTCA
operating clock
SYSCLK
RTCA
operating clock
Oscillation stabilization waiting time
IOSCCLK IOSCCLK
Executing the
slp instruction
OSC1CLK OSC1CLK
IOSCCLK IOSCCLK
Executing the
slp instruction
SLEEP mode
(CPU stop, CLK stop)
(CLK stop)
∗ The RTCA stops counting in
SLEEP mode as the clock stops.
SLEEP mode
(CPU stop, CLK stop)
OSC1CLK
∗ The RTCA continues counting in
IOSCCLK
(Unstable)
Interrupt
(Wake-up)
OSC1CLK
(Unstable)
IOSCCLK
(Unstable)
Interrupt
(Wake-up)
-
Figure 2.3.4.3 Clock Control Example in SLEEP Mode
The SYSCLK condition (clock source and division ratio) at wake-up from SLEEP mode to RUN mode can also
be configured. This allows flexible clock control according to the wake-up process. Configure the clock using
the CLGSCLK.WUPSRC[1:0] and CLGSCLK.WUPDIV[1:0] bits, and write 1 to the CLGSCLK.WUPMD bit
to enable this function.
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(1)
as entered.
(2)
initiation allows high-speed processing.
When the CLGSCLK.WUPMD bit = 0
(CPU operating clock)
SYSCLK
When the CLGSCLK.WUPMD bit = 1 and the CLGSCLK.WUPSRC[1:0] bits = 0x0
SYSCLK
(CPU operating clock)
OSC1CLK OSC1CLK
Executing the
slp instruction
CLGSCLK.CLKSRC[1:0] = 0x1 (OSC1)
CLGSCLK.WUPSRC[1:0] = 0x1 (OSC1)
OSC1CLK IOSCCLK
Executing the
slp instruction
CLGSCLK.CLKSRC[1:0] = 0x1 (OSC1)
CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC)
SLEEP mode
(CPU stop, CLK stop)
Interrupt
(Wake-up)
SLEEP mode
(CPU stop, CLK stop)
Interrupt
(Wake-up)
Oscillation stabilization waiting time
OSC1CLK
(Unstable)
∗ Starting up with the same clock as one
that used before SLEEP mode w
IOSCCLK
(Unstable)
CLGSCLK.CLKSRC[1:0] = 0x0 (IOSC)
CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC)
∗ Switching to IOSC that features fast
Figure 2.3.4.4 Clock Control Example at SLEEP Cancelation
Clock external output (FOUT)
The FOUT pin can output the clock generated by a clock source or its divided clock to outside the IC. This al-
lows monitoring the oscillation frequency of the oscillator circuit or supplying an operating clock to external
ICs. Follow the procedure shown below to start clock external output.
1. Assign the FOUT function to the port. (Refer to the “I/O Ports” chapter.)
2. Configure the following CLGFOUT register bits:
- CLGFOUT.FOUTSRC[1:0] bits (Select clock source)
- CLGFOUT.FOUTDIV[2:0] bits (Set clock division ratio)
- Set the CLGFOUT.FOUTEN bit to 1. (Enable clock external output)
OSC3 oscillation auto-trimming function
The OSC3 internal oscillator circuit has the auto-trimming function that adjusts the OSC3CLK clock frequency
by trimming the clock with reference to the high precision OSC1CLK clock generated by the OSC1 crystal oscillator circuit. Follow the procedure shown below to enable the auto-trimming function.
1.
After enabling the OSC1 oscillation, check if the stabilized clock is supplied (CLGINTF.OSC1STAIF bit = 1).
2.
After enabling the OSC3 oscillation, check if the stabilized clock is supplied (CLGINTF.OSC3STAIF bit = 1).
3. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
4. If the SYSCLK clock source is OSC3, set the CLGSCLK.CLKSRC[1:0] bits to a value other than 0x2
(OSC3).
5. Write 1 to the CLGINTF.OSC3TEDIF bit. (Clear interrupt flag)
6. Write 1 to the CLGINTE.OSC3TEDIE bit. (Enable interrupt)
7. Write 1 to the CLGOSC3.OSC3STM bit. (Enable OSC3 oscillation auto-trimming)
8. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
9. The trimmed OSC3CLK can be used if the CLGINTF.OSC3TEDIF bit = 1 after an interrupt occurs.
After the trimming operation has completed, the CLGOSC3.OSC3STM bit automatically reverts to 0.
the trimming time depends on the temperature, an average of several 10 ms is required.
When OSC3CLK is be-
ing used as the system clock or a peripheral circuit clock, do not use the auto-trimming function.
Although
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Reset request from POR
∗2: Address (reset vector + 2)
OSC1 oscillation stop detection function
The oscillation stop detection function restarts the OSC1 oscillator circuit when it detects oscillation stop under
adverse environments that may stop the oscillation. Follow the procedure shown below to enable the oscillation
stop detection function.
1.
After enabling the OSC1 oscillation, check if the stabilized clock is supplied (CLGINTF.OSC1STAIF bit = 1).
2. Write 1 to the CLGINTF.OSC1STPIF bit. (Clear interrupt flag)
3. Write 1 to the CLGINTE.OSC1STPIE bit. (Enable interrupt)
4. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
5. Set the following CLGOSC1 register bits:
- Set the CLGOSC1.OSDRB bit to 1. (Enable OSC1 restart function)
- Set the CLGOSC1.OSDEN bit to 1. (Enable oscillation stop detection function)
6. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
7. The OSC1 oscillation stops if the CLGINTF.OSC1STPIF bit = 1 after an interrupt occurs.
If the CLGOSC1.OSDRB bit = 1, the hardware restarts the OSC1 oscillator circuit.
Note: Enabling the oscillation stop detection function increase the oscillation stop detector current
(I
OSD1).
2.4 Operating Mode
2.4.1 Initial Boot Sequence
Figure 2.4.1.1 shows the initial boot sequence after power is turned on.
VDD
IOSCCLK
(Initial SYSCLK)
Internal reset signal
SYSRST, H0, H1
S1C17 core
program counter (PC)
Undefined
Undefined
Figure 2.4.1.1 Initial Boot Sequence
Cancel reset request
Cancel reset request
Reset hold time t
RSTR
∗1
∗2
∗1: Reset vector (reset handler start address)
Note: The reset cancelation time at power-on varies according to the power rise time and reset request
cancelation time.
For the reset hold time t
RSTR, refer to “Reset hold circuit characteristics” in the “Electrical Characteristics” chapter.
2.4.2 Transition between Operating Modes
State transitions between operating modes shown in Figure 2.4.2.1 take place in this IC.
RUN mode
RUN mode refers to the state in which the CPU is executing the program. A transition to this mode takes place
when the system reset request from the system reset controller is canceled. RUN mode is classified into “IOSC
RUN,” “OSC1 RUN,” “OSC3 RUN,” and “EXOSC RUN” by the SYSCLK clock source.
HALT mode
When the CPU executes the halt instruction, it suspends program execution and stops operating. This state is
HALT mode. In this mode, the clock sources and peripheral circuits keep operating. This mode can be set while
no software processing is required and it reduces power consumption as compared with RUN mode. HALT
mode is classified into “IOSC HALT,” “OSC1 HALT,” “OSC3 HALT,” and “EXOSC HALT” by the SYSCLK
clock source.
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cancelation signal
SLEEP mode
When the CPU executes the slp instruction, it suspends program execution and stops operating. This state is
SLEEP mode. In this mode, the clock sources stop operating as well. However, the clock source in which the
CLGOSC.IOSCSLPC/OSC1SLPC/OSC3SLPC/EXOSCSLPC bit is set to 0 keeps operating, so the peripheral
circuits with the clock being supplied can also operate. By setting this mode when no software processing and
peripheral circuit operations are required, power consumption can be less than HALT mode.
Note: The current consumption when a clock source is active in SLEEP mode by setting the CLGOSC.
IOSCSLPC/OSC1SLPC/OSC3SLPC/EXOSCSLPC bit to 0 is equivalent to the value in HALT
mode with the same clock source condition (refer to “Current Consumption, Current consumption in HALT mode I
HALT1, IHALT2, and IHALT3” in the “Electrical Characteristics” chapter).
DEBUG mode
When a debug interrupt occurs, the CPU enters DEBUG mode. DEBUG mode is canceled when the retd in-
struction is executed. For more information on DEBUG mode, refer to “Debugger” in the “CPU and Debugger”
chapter.
RESET
(Initial state)
Transition takes place automatically by the
initial boot sequence after a request from
the reset source is canceled.
IOSC
HALT
signal
HALT/SLEEP
cancelation
IOSC
halt instruction
RUN
CLGSCLK.CLKSRC[1:0] = 0x3
CLGSCLK.CLKSRC[1:0] = 0x0
RUN SLEEP
RUN/
HALT/
SLEEP
slp instruction
HALT/SLEEP
cancelation signal
(wake-up)
Debug interrupt
retd instruction
DEBUG
OSC1
HALT
halt instruction
HALT/SLEEP
cancelation signal
CLGSCLK.CLKSRC[1:0] = 0x1
OSC1
CLGSCLK.CLKSRC[1:0] = 0x0
RUN
CLGSCLK.CLKSRC[1:0] = 0x3
CLGSCLK.CLKSRC[1:0] = 0x2
CLGSCLK.CLKSRC[1:0] = 0x1
halt instruction
OSC3
HALT
CLGSCLK.CLKSRC[1:0] = 0x2
CLGSCLK.CLKSRC[1:0] = 0x1
CLGSCLK.CLKSRC[1:0] = 0x0
OSC3
RUN
HALT/SLEEP
CLGSCLK.CLKSRC[1:0] = 0x2
CLGSCLK.CLKSRC[1:0] = 0x3
∗ In RUN and HALT modes, the clock sources not used
as SYSCLK can be all disabled.
Figure 2.4.2.1 Operating Mode-to-Mode State Transition Diagram
EXOSC
RUN
halt instruction
HALT/SLEEP
cancelation
signal
EXOSC
HALT
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Canceling HALT or SLEEP mode
The conditions listed below generate the HALT/SLEEP cancelation signal to cancel HALT or SLEEP mode and
put the CPU into RUN mode. This transition is executed even if the CPU does not accept the interrupt request.
• Interrupt request from a peripheral circuit
• NMI from the watchdog timer
• Debug interrupt
• Reset request
2.5 Interrupts
CLG has a function to generate the interrupts shown in Table 2.5.1.
Table 2.5.1 CLG Interrupt Functions
Interrupt Interrupt flag Set condition Clear condition
IOSC oscillation stabilization waiting completion
OSC1 oscillation stabilization waiting completion
OSC3 oscillation stabilization waiting completion
OSC1 oscillation stop CLGINTF.OSC1STPIF
OSC3 oscillation autotrimming completion
CLGINTF.IOSCSTAIF When the IOSC oscillation stabilization waiting
operation has completed after the oscillation starts
CLGINTF.OSC1STAIF When the OSC1 oscillation stabilization waiting
operation has completed after the oscillation starts
CLGINTF.OSC3STAIF When the OSC3 oscillation stabilization waiting
operation has completed after the oscillation starts
When OSC1CLK is stopped, or when the CLGOSC.
OSC1EN or CLGOSC1.OSDEN bit setting is altered from 1 to 0.
CLGINTF.OSC3TEDIF When the OSC3 oscillation auto-trimming opera-
tion has completed
Writing 1
Writing 1
Writing 1
Writing 1
Writing 1
CLG provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the interrupt
controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For
more information on interrupt control, refer to the “Interrupt Controller” chapter.
2.6 Control Registers
Note: Do not alter the initial values of the control bits for the functions that are not supported in the
model to be used.
PWG VD1 Regulator Control Register
Register name Bit Bit name Initial Reset R/W Remarks
PWGVD1CTL 15–8 – 0x00 – R –
7–2 – 0x00 – R
1–0 REGMODE[1:0] 0x0 H0 R/WP
Bits 15–2 Reserved
Bits 1–0 REGMODE[1:0]
These bits control the internal regulator operating mode.
Table 2.6.1 Internal Regulator Operating Mode
PWGVD1CTL.REGMODE[1:0] bits Operating mode
0x3 Economy mode
0x2 Normal mode
0x1 Reserved
0x0 Automatic mode
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CLG System Clock Control Register
Register name Bit Bit name Initial Reset R/W Remarks
CLGSCLK 15 WUPMD 0 H0 R/WP –
14 – 0 – R
13–12 WUPDIV[1:0] 0x0 H0 R/WP
11–10 – 0x0 – R
9–8 WUPSRC[1:0] 0x0 H0 R/WP
7–6 – 0x0 – R
5–4 CLKDIV[1:0] 0x0 H0 R/WP
3–2 – 0x0 – R
1–0 CLKSRC[1:0] 0x0 H0 R/WP
Bit 15 WUPMD
This bit enables the SYSCLK switching function at wake-up.
1 (R/WP): Enable
0 (R/WP): Disable
When the CLGSCLK.WUPMD bit = 1, setting values of the CLGSCLK.WUPSRC[1:0] bits and the
CLGSCLK.WUPDIV[1:0] bits are loaded to the CLGSCLK.CLKSRC[1:0] bits and the CLGSCLK.
CLKDIV[1:0] bits, respectively, at wake-up from SLEEP mode to switch SYSCLK. When the CLGSCLK.WUPMD bit = 0, the CLGSCLK.CLKSRC[1:0] and CLGSCLK.CLKDIV[1:0] bits are not
altered at wake-up.
Note: When the CLGSCLK.WUPMD bit = 1, the clock source enable bits (CLGOSC.EXOSCEN,
CLGOSC.OSC1EN, CLGOSC.OSC3EN, CLGOSC.IOSCEN) except for the SYSCLK source
selected by the CLGSCLK.CLKSRC[1:0] bits will be cleared to 0 to stop the clocks after a
system wake-up. However, the enable bit of the clock source being operated during SLEEP
mode by setting the CLGOSC.****SLPC bit retains 1 after a wake-up.
Bit 14 Reserved
Bits 13–12 WUPDIV[1:0]
These bits select the SYSCLK division ratio for resetting the CLGSCLK.CLKDIV[1:0] bits at wake-up.
This setting is ineffective when the CLGSCLK.WUPMD bit = 0.
Bits 11–10 Reserved
Bits 9–8 WUPSRC[1:0]
These bits select the SYSCLK clock source for resetting the CLGSCLK.CLKSRC[1:0] bits at wake-up.
When a currently stopped clock source is selected, it will automatically start oscillating or clock input
at wake-up. However, this setting is ineffective when the CLGSCLK.WUPMD bit = 0.
Table 2.6.2 SYSCLK Clock Source and Division Ratio Settings at Wake-up
CLGSCLK.
WUPDIV[1:0] bits
0x3 1/8 Reserved
0x2 1/4 Reserved
0x1 1/2 1/2
0x0 1/1 1/1
0x0 0x1 0x2 0x3
IOSCCLK OSC1CLK OSC3CLK EXOSCCLK
CLGSCLK.WUPSRC[1:0] bits
1/8
1/4
1/2
1/1
Reserved
Reserved
Reserved
1/1
Bits 7–6 Reserved
Bits 5–4 CLKDIV[1:0]
These bits set the division ratio of the clock source to determine the SYSCLK frequency.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the SYSCLK clock source.
When a currently stopped clock source is selected, it will automatically start oscillating or clock input.
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Table 2.6.3 SYSCLK Clock Source and Division Ratio Settings
CLGSCLK.
CLKDIV[1:0] bits
0x3 1/8 Reserved
0x2 1/4 Reserved
0x1 1/2 1/2
0x0 1/1 1/1
0x0 0x1 0x2 0x3
IOSCCLK OSC1CLK OSC3CLK EXOSCCLK
CLGSCLK.CLKSRC[1:0] bits
1/8
1/4
1/2
1/1
Reserved
Reserved
Reserved
1/1
CLG Oscillation Control Register
Register name Bit Bit name Initial Reset R/W Remarks
CLGOSC 15–12 – 0x0 – R –
11 EXOSCSLPC 1 H0 R/W
10 OSC3SLPC 1 H0 R/W
9 OSC1SLPC 1 H0 R/W
8 IOSCSLPC 1 H0 R/W
7–4 – 0x0 – R
3 EXOSCEN 0 H0 R/W
2 OSC3EN 0 H0 R/W
1 OSC1EN 0 H0 R/W
0 IOSCEN 1 H0 R/W
Bits 15–12 Reserved
Bit 11 EXOSCSLPC
Bit 10 OSC3SLPC
Bit 9 OSC1SLPC
Bit 8 IOSCSLPC
These bits control the clock source operations in SLEEP mode.
1 (R/W): Stop clock source in SLEEP mode
0 (R/W): Continue operation state before SLEEP
Each bit corresponds to the clock source as follows:
CLGOSC.EXOSCSLPC bit: EXOSC clock input
CLGOSC.OSC3SLPC bit: OSC3 oscillator circuit
CLGOSC.OSC1SLPC bit: OSC1 oscillator circuit
CLGOSC.IOSCSLPC bit: IOSC oscillator circuit
Bits 7–4 Reserved
Bit 3 EXOSCEN
Bit 2 OSC3EN
Bit 1 OSC1EN
Bit 0 IOSCEN
These bits control the clock source operation.
1(R/W): Start oscillating or clock input
0(R/W): Stop oscillating or clock input
Each bit corresponds to the clock source as follows:
CLGOSC.EXOSCEN bit: EXOSC clock input
CLGOSC.OSC3EN bit: OSC3 oscillator circuit
CLGOSC.OSC1EN bit: OSC1 oscillator circuit
CLGOSC.IOSCEN bit: IOSC oscillator circuit
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CLG OSC1 Control Register
Register name Bit Bit name Initial Reset R/W Remarks
CLGOSC1 15 – 0 – R –
14 OSDRB 1 H0 R/WP
13 OSDEN 0 H0 R/WP
12 OSC1BUP 1 H0 R/WP
11 OSC1SELCR 0 H0 R/WP
10–8 CGI1[2:0] 0x0 H0 R/WP
7–6 INV1B[1:0] 0x2 H0 R/WP
5–4 INV1N[1:0] 0x1 H0 R/WP
3–2 – 0x0 – R
1–0 OSC1WT[1:0] 0x2 H0 R/WP
Bit 15 Reserved
Bit 14 OSDRB
This bit enables the OSC1 oscillator circuit restart function by the oscillation stop detector when
OSC1 crystal oscillation stop is detected.
1 (R/WP): Enable (Restart the OSC1 oscillator circuit when oscillation stop is detected.)
0 (R/WP): Disable
Bit 13 OSDEN
This bit controls the oscillation stop detector in the OSC1 oscillator circuit.
1 (R/WP): OSC1 oscillation stop detector on
0 (R/WP): OSC1 oscillation stop detector off
Note: Do not write 1 to the CLGOSC1.OSDEN bit before stabilized OSC1CLK is supplied. Further-
more, the CLGOSC1.OSDEN bit should be set to 0 when the CLGOSC.OSC1EN bit is set to 0.
Bit 12 OSC1BUP
This bit enables the oscillation startup control circuit in the OSC1 crystal oscillator circuit.
1 (R/WP): Enable (Activate booster operation at startup.)
0 (R/WP): Disable
Bit 11 OSC1SELCR
This bit selects an oscillator type of the OSC1 oscillator circuit.
1 (R/WP): Internal oscillator
0 (R/WP): Crystal oscillator
Bits 10–8 CGI1[2:0]
These bits set the internal gate capacitance in the OSC1 crystal oscillator circuit.
Table 2.6.4 OSC1 Internal Gate Capacitance Setting
CLGOSC1.CGI1[2:0] bits Capacitance
0x7 Max.
0x6 ↑
0x5
0x4
0x3
0x2
0x1 ↓
0x0 Min.
For more information, refer to “OSC1 oscillator circuit characteristics, Crystal oscillator internal gate
capacitance C
GI1C” in the “Electrical Characteristics” chapter.
Bits 7–6 INV1B[1:0]
These bits set the oscillation inverter gain that will be applied at boost startup of the OSC1 crystal os-
cillator circuit.
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Table 2.6.5 Setting Oscillation Inverter Gain at OSC1 Boost Startup
CLGOSC1.INV1B[1:0] bits Inverter gain
0x3 Max.
0x2 ↑
0x1 ↓
0x0 Min.
Note: The CLGOSC1.INV1B[1:0] bits must be set to a value equal to or larger than the CLGOSC1.
INV1N[1:0] bits.
Bits 5–4 INV1N[1:0]
These bits set the oscillation inverter gain applied at normal operation of the OSC1 crystal oscillator
circuit.
Table 2.6.6 Setting Oscillation Inverter Gain at OSC1 Normal Operation
CLGOSC1.INV1N[1:0] bits Inverter gain
0x3 Max.
0x2 ↑
0x1 ↓
0x0 Min.
Bits 3–2 Reserved
Bits 1–0 OSC1WT[1:0]
These bits set the oscillation stabilization waiting time for the OSC1 oscillator circuit.
Table 2.6.7 OSC1 Oscillation Stabilization Waiting Time Setting
CLGOSC1.OSC1WT[1:0] bits Oscillation stabilization waiting time
0x3 65,536 clocks
0x2 16,384 clocks
0x1 4,096 clocks
0x0 Reserved
CLG OSC3 Control Register
Register name Bit Bit name Initial Reset R/W Remarks
CLGOSC3 15–12 – 0x0 – R –
11–10 OSC3FQ[1:0] 0x1 H0 R/WP
9 OSC3MD 0 H0 R/WP
8 – 0 – R
7–6 – 0x0 – R
5–4 OSC3INV[1:0] 0x3 H0 R/WP
3 OSC3STM 0 H0 R/WP
2–0 OSC3WT[2:0] 0x6 H0 R/WP
Bits 15–12 Reserved
Bits 11–10 OSC3FQ[1:0]
These bits set the oscillation frequency of the OSC3 internal oscillator circuit.
Table 2.6.8 Setting Oscillation Frequency of OSC3 Internal Oscillator Circuit
CLGOSC3.OSC3FQ[1:0] bits Oscillation frequency
0x3 Reserved
0x2 20 MHz
0x1 16 MHz
0x0 12 MHz
Bit 9 OSC3MD
This bit selects an oscillator type of the OSC3 oscillator circuit.
1 (R/WP): Crystal/ceramic oscillator
0 (R/WP): Internal oscillator
Bits 8–6 Reserved
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Bits 5–4 OSC3INV[1:0]
These bits set the oscillation inverter gain of the OSC3 crystal/ceramic oscillator circuit.
Table 2.6.9 OSC3 Oscillation Inverter Gain Setting
CLGOSC3.OSC3INV[1:0] bits Inverter gain
0x3 Max.
0x2 ↑
0x1 ↓
0x0 Min.
Bit 3 OSC3STM
This bit controls the OSC3 internal oscillator auto-trimming function.
1 (WP): Start trimming
0 (WP): Stop trimming
1 (R): Trimming is executing.
0 (R): Trimming has finished. (Trimming operation inactivated.)
This bit is automatically cleared to 0 when trimming has finished.
Notes: • Do not use OSC3CLK as the system clock or peripheral circuit clocks while the
CLGOSC3.OSC3STM bit = 1.
• The auto-trimming function does not work if the OSC1 oscillator circuit is stopped. Make
sure the CLGINTF.OSC1STAIF bit is set to 1 before starting the trimming operation.
• Do not alter the CLGOSC3.OSC3FQ[1:0] bits while auto-trimming is being executed.
• Select the 32.768 kHz crystal oscillator for the OSC1 oscillator circuit when using the
auto-trimming function. The clock cannot be adjusted properly by the internal oscillator.
Bits 2–0 OSC3WT[2:0]
These bits set the oscillation stabilization waiting time for the OSC3 oscillator circuit.
Table 2.6.10 OSC3 Oscillation Stabilization Waiting Time Setting
CLGOSC3.OSC3WT[2:0] bits Oscillation stabilization waiting time
0x7 65,536 clocks
0x6 16,384 clocks
0x5 4,096 clocks
0x4 1,024 clocks
0x3 256 clocks
0x2 64 clocks
0x1 16 clocks
0x0 4 clocks
CLG Interrupt Flag Register
Register name Bit Bit name Initial Reset R/W Remarks
CLGINTF 15–8 – 0x00 – R –
7 – 0x0 – R
6 (reserved) 0 H0 R
5 OSC1STPIF 0 H0 R/W Cleared by writing 1.
4 OSC3TEDIF 0 H0 R/W
3 – 0 – R –
2 OSC3STAIF 0 H0 R/W Cleared by writing 1.
1 OSC1STAIF 0 H0 R/W
0 IOSCSTAIF 0 H0 R/W
Bits 15–6, 3 Reserved
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Bit 5 OSC1STPIF
Bit 4 OSC3TEDIF
Bit 2 OSC3STAIF
Bit 1 OSC1STAIF
Bit 0 IOSCSTAIF
These bits indicate the CLG interrupt cause occurrence statuses.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
Each bit corresponds to the interrupt as follows:
CLGINTF.OSC1STPIF bit: OSC1 oscillation stop interrupt
CLGINTF.OSC3TEDIF bit: OSC3 oscillation auto-trimming completion interrupt
CLGINTF.OSC3STAIF bit: OSC3 oscillation stabilization waiting completion interrupt
CLGINTF.OSC1STAIF bit: OSC1 oscillation stabilization waiting completion interrupt
CLGINTF.IOSCSTAIF bit: IOSC oscillation stabilization waiting completion interrupt
Note: The CLGINTF.IOSCSTAIF bit is 0 after system reset is canceled, but IOSCCLK has already
been stabilized.
CLG Interrupt Enable Register
Register name Bit Bit name Initial Reset R/W Remarks
CLGINTE 15–8 – 0x00 – R –
7 – 0 – R
6 (reserved) 0 H0 R
5 OSC1STPIE 0 H0 R/W
4 OSC3TEDIE 0 H0 R/W
3 – 0 – R
2 OSC3STAIE 0 H0 R/W
1 OSC1STAIE 0 H0 R/W
0 IOSCSTAIE 0 H0 R/W
Bits 15–6, 3 Reserved
Bit 5 OSC1STPIE
Bit 4 OSC3TEDIE
Bit 2 OSC3STAIE
Bit 1 OSC1STAIE
Bit 0 IOSCSTAIE
These bits enable the CLG interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Each bit corresponds to the interrupt as follows:
CLGINTE.OSC1STPIE bit: OSC1 oscillation stop interrupt
CLGINTE.OSC3TEDIE bit: OSC3 oscillation auto-trimming completion interrupt
CLGINTE.OSC3STAIE bit: OSC3 oscillation stabilization waiting completion interrupt
CLGINTE.OSC1STAIE bit: OSC1 oscillation stabilization waiting completion interrupt
CLGINTE.IOSCSTAIE bit: IOSC oscillation stabilization waiting completion interrupt
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CLG FOUT Control Register
Register name Bit Bit name Initial Reset R/W Remarks
CLGFOUT 15–8 – 0x00 – R –
7 – 0 – R
6–4 FOUTDIV[2:0] 0x0 H0 R/W
3–2 FOUTSRC[1:0] 0x0 H0 R/W
1 – 0 – R
0 FOUTEN 0 H0 R/W
Bits 15–7 Reserved
Bits 6–4 FOUTDIV[2:0]
These bits set the FOUT clock division ratios.
Bits 3–2 FOUTSRC[1:0]
These bits select the FOUT clock sources.
Table 2.6.11 FOUT Clock Source and Division Ratio Settings
CLGFOUT.
FOUTDIV[2:0] bits
0x7 1/128 1/32,768 1/128 Reserved
0x6 1/64 1/4,096 1/64 Reserved
0x5 1/32 1/1,024 1/32 Reserved
0x4 1/16 1/256 1/16 Reserved
0x3 1/8 1/8 1/8 Reserved
0x2 1/4 1/4 1/4 Reserved
0x1 1/2 1/2 1/2 Reserved
0x0 1/1 1/1 1/1 1/1
0x0 0x1 0x2 0x3
IOSCCLK OSC1CLK OSC3CLK SYSCLK
CLGFOUT.FOUTSRC[1:0] bits
Note: When the CLGFOUT.FOUTSRC[1:0] bits are set to 0x3, the FOUT output will be stopped in
SLEEP/HALT mode as SYSCLK is stopped.
Bit 1 Reserved
Bit 0 FOUTEN
This bit controls the FOUT clock external output.
1 (R/W): Enable external output
0 (R/W): Disable external output
Note: Since the FOUT signal generated is out of sync with writings to the CLGFOUT.FOUTEN bit,
a glitch may occur when the FOUT output is enabled or disabled.
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DCLK
3 CPU and Debugger
3.1 Overview
This IC incorporates the Seiko Epson original 16-bit CPU core (S1C17) with a debugger. The main features of the
CPU core are listed below.
• Seiko Epson original 16-bit RISC processor
- 24-bit general-purpose registers: 8
- 24-bit special registers: 2
- 8-bit special register: 1
- Up to 16M bytes of memory space (24-bit address)
- Harvard architecture using separated instruction bus and data bus
• Compact and fast instruction set optimized for development in C language
- Code length: 16-bit fixed length
- Number of instructions: 111 basic instructions (184 including variations)
- Execution cycle: Main instructions are executed in one cycle.
- Extended immediate instructions: Immediate data can be extended up to 24 bits.
• Supports reset, NMI, address misaligned, debug, and external interrupts.
- Reads a vector from the vector table and branches to the interrupt handler routine directly.
- Can generate software interrupts with a vector number specified (all vector numbers specifiable).
• HALT mode (halt instruction) and SLEEP mode (slp instruction) are provided as the standby function.
• Incorporates a debugger with three-wire communication interface to assist in software development.
SYSCLK
NMI
Interrupt
controller
Flash
memory
RAM
Interrupt request
Interrupt level
Vector number
Instruction bus
RAM bus
Internal bus
CPU core (S1C17)
General-purpose registers
Bit 23 Bit 0
R7
R6
R5
R4
R3
R2
R1
R0
Bus controller
Special registers
Program counter
Bit 23 Bit 0
Stack pointer
Bit 23 Bit 0
Processor status register
Bit 7 Bit 0
IL[2:0] (Bits [7:5]): Interrupt Level
IE (Bit 4): Interrupt Enable
C (Bit 3): Carry
V (Bit 2): Overflow
Z (Bit 1): Zero
N (Bit 0): Negative
PC
SP
PSR
Debugger
DSIO
DST2
Figure 3.1.1 S1C17 Configuration
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3.2 CPU Core
3.2.1 CPU Registers
The CPU includes eight general-purpose registers and three special registers (Table 3.2.1.1).
Table 3.2.1.1 Initialization of CPU Registers
CPU register name Initial Reset
General-purpose registers R0 to R7 0x000000 H0
Special
registers
For details on the CPU registers, refer to the “S1C17 Family S1C17 Core Manual.” For more information on the
reset vector, refer to the “Interrupt Controller” chapter.
3.2.2 Instruction Set
The CPU instruction codes are all fixed to 16 bits in length which, combined with pipelined processing, allows the
most important instructions to be executed in one cycle. For details on the instructions, refer to the “S1C17 Family
S1C17 Core Manual.”
3.2.3 Reading PSR
Program counter PC The reset vector is automatically loaded. H0
Stack pointer SP 0x000000 H0
Processor status register PSR 0x00 H0
The PSR contents can be read through the MSCPSR register. Note, however, that data cannot be written to PSR
through the MSCPSR register.
3.2.4 I/O Area Reserved for the S1C17 Core
The address range from 0xfffc00 to 0xffffff is the I/O area reserved for the S1C17 core. Do not access this area except when it is required.
3.3 Debugger
3.3.1 Debugging Functions
The debugger provides the following functions:
• Instruction break: A debug interrupt is generated immediately before the set instruction address is executed. An
instruction break can be set at up to four addresses.
• Single step: A debug interrupt is generated after each instruction has been executed.
• Forcible break: A debug interrupt is generated using an external input signal.
• Software break: A debug interrupt is generated when the brk instruction is executed.
When a debug interrupt occurs, the CPU enters DEBUG mode. The peripheral circuit operations in DEBUG mode
depend on the setting of the DBRUN bit provided in the clock control register of each peripheral circuit. For more
information on the DBRUN bit, refer to “Clock Supply in DEBUG Mode” in each peripheral circuit chapter. DEBUG mode continues until a cancel command is sent from the personal computer or the CPU executes the retd instruction. Neither hardware interrupts nor NMI are accepted during DEBUG mode.
3.3.2 Resource Requirements and Debugging Tools
Debugging work area
Debugging requires a 64-byte debugging work area. For more information on the work area location, refer to
the “Memory and Bus” chapter. The start address of this debugging work area can be read from the DBRAM
register.
3-2
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(S5U1C17001H)
S1C17
UserEPSON
(6–12 alphanumeric characters (A–Z, a–z, 0–9))
ROM data and password
Debugging tools
To perform debugging, connect ICDmini (S5U1C17001H) to the input/output pin for the debugger embedded
in this IC and control it from the personal computer. This requires the tools shown below.
• S1C17 Family In-Circuit Debugger ICDmini (S5U1C17001H)
• S1C17 Family C Compiler Package (e.g., S5U1C17001C)
3.3.3 List of Debugger Input/Output Pins
Table 3.3.3.1 lists the debug pins.
Table 3.3.3.1 List of Debug Pins
Pin name I/O Initial state Function
DCLK O O On-chip debugger clock output pin
Outputs a clock to the ICDmini (S5U1C17001H).
DSIO I/O I On-chip debugger data input/output pin
Used to input/output debugging data and input the break signal.
DST2 O O On-chip debugger status output pin
Outputs the processor status during debugging.
The debugger input/output pins are shared with general-purpose I/O ports and are initially set as the debug pins. If
the debugging function is not used, these pins can be switched to general-purpose I/O port pins. For details, refer to
the “I/O Ports” chapter.
Note: Do not drive the DCLK pin with a high level from outside (e.g. pulling up with a resistor). Also, do
not connect (short-circuit) between the DCLK pin and another GPIO port. In the both cases, the
IC may not start up normally due to unstable pin input/output status at power on.
3.3.4 External Connection
Figure 3.3.4.1 shows a connection example between this IC and ICDmini when performing debugging.
DCLK
VDD
DSIO
DST2
Figure 3.3.4.1 External Connection
DCLK
ICDmini
RDBG
DSIO
DST2
For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, DSIO pull-up resistor R
DBG” in the “Electrical Characteristics” chapter. RDBG is not required when using the DSIO pin as a general-
purpose I/O port pin.
3.3.5 Flash Security Function
This IC provides a security function to protect the internal Flash memory from unauthorized reading and tampering
by using the debugger through ICDmini. Figure 3.3.5.1 shows a Flash security function setting flow.
Specify the unprotecting password.
ROM data and password are recorded.
Programming with
Factory shipment inspection
process
Development environment
Submission
GNU17 IDE
file.PA
Mask data file
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IC with protected Flash
Shipment
Figure 3.3.5.1 Shipment of IC with ROM Data Programmed and Flash Security Function Setting Flow
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3 CPU AND DEBUGGER
The following shows the status of the IC with protected Flash:
• The Flash memory data is undefined if it is read from the debugger.
• An error occurs if an attempt is made to program the Flash memory through ICDmini.
However, the Flash security function can be disabled by entering the unprotecting password predefined to GNU17
IDE (the security function will take effect again after a reset). For setting the password, refer to the “(S1C17 Family
C Compiler Package) S5U1C17001C Manual.”
Note: Disable the Flash security function before debugging an IC with protected Flash via ICDmini. The
debugging functions may not run normally if the Flash security function is enabled.
3.4 Control Register
MISC PSR Register
Register name Bit Bit name Initial Reset R/W Remarks
MSCPSR 15–8 – 0x00 – R –
7–5 PSRIL[2:0] 0x0 H0 R
4 PSRIE 0 H0 R
3 PSRC 0 H0 R
2 PSRV 0 H0 R
1 PSRZ 0 H0 R
0 PSRN 0 H0 R
Bits 15–8 Reserved
Bits 7–5 PSRIL[2:0]
The value (0 to 7) of the PSR IL[2:0] (interrupt level) bits can be read out with these bits.
Bit 4 PSRIE
The value (0 or 1) of the PSR IE (interrupt enable) bit can be read out with this bit.
Bit 3 PSRC
The value (0 or 1) of the PSR C (carry) flag can be read out with this bit.
Bit 2 PSRV
The value (0 or 1) of the PSR V (overflow) flag can be read out with this bit.
Bit 1 PSRZ
The value (0 or 1) of the PSR Z (zero) flag can be read out with this bit.
Bit 0 PSRN
The value (0 or 1) of the PSR N (negative) flag can be read out with this bit.
Debug RAM Base Register
Register name Bit Bit name Initial Reset R/W Remarks
DBRAM 31–24 – 0x00 – R –
23–0 DBRAM[23:0] *1 H0 R
*1 Debugging work area start address
Bits 31–24 Reserved
Bits 23–0 DBRAM[23:0]
The start address of the debugging work area (64 bytes) can be read out with these bits.
3-4
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4.1 Overview
This IC supports up to 16M bytes of accessible memory space for both instructions and data.
The features are listed below.
• Embedded Flash memory that supports on-board programming
• All memory and control registers are accessible in 16-bit width and one cycle.
• Write-protect function to protect system control registers
Figure 4.1.1 shows the memory map.
4 MEMORY AND BUS
0xff ffff
0xff fc00 0xff fc00
0xff fbff
0x00 c000
0x00 bfff
0x00 8000 0x00 8000
0x00 7fff
0x00 6000 0x00 6000
0x00 5fff
0x00 4000 0x00 4000
0x00 3fff
0x00 0800 0x00 0800
0x00 07ff
0x00 07c0
0x00 07bf
0x00 0000 0x00 0000
S1C17M20/M21/M22 S1C17M23/M24/M25
Reserved for core I/O area
(1K bytes)
(Device size: 32 bits)
Reserved
Flash area
(16K bytes)
(Device size: 16 bits)
Reserved
Peripheral circuit area
(8K bytes)
(Device size: 16 bits)
Reserved
Debug RAM area (64 bytes)
RAM area
(2K bytes)
(Device size: 32 bits)
0xff ffff
0xff fbff
0x01 0000
0x00 ffff
0x00 7fff
0x00 5fff
0x00 3fff
0x00 07ff
0x00 07c0
0x00 07bf
Figure 4.1.1 Memory Map
Reserved for core I/O area
(1K bytes)
(Device size: 32 bits)
Reserved
Flash area
(32K bytes)
(Device size: 16 bits)
Reserved
Peripheral circuit area
(8K bytes)
(Device size: 16 bits)
Reserved
Debug RAM area (64 bytes)
RAM area
(2K bytes)
(Device size: 32 bits)
4.2 Bus Access Cycle
The CPU uses the system clock for bus access operations. First, “Bus access cycle,” “Device size,” and “Access
size” are defined as follows:
• Bus access cycle: One system clock period = 1 cycle
• Device size: Bit width of the memory and peripheral circuits that can be accessed in one cycle
• Access size: Access size designated by the CPU instructions (e.g., ld %rd, [%rb] → 16-bit data transfer)
Table 4.2.1 lists numbers of bus access cycles by different device size and access size. The peripheral circuits can
be accessed with an 8-bit, 16-bit, or 32-bit instruction.
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Table 4.2.1 Number of Bus Access Cycles
Device size Access size
8 bits 8 bits 1
16 bits 2
32 bits 4
16 bits 8 bits 1
16 bits 1
32 bits 2
32 bits 8 bits 1
16 bits 1
32 bits 1
Number of bus access
cycles
Note: When data is transferred to a memory in 32-bit access, the eight high-order bits are written to
the memory as 0x00 since the bit width of the S1C17 core general-purpose registers is 24 bits.
Conversely when sending from a memory to a register, the eight high-order bits are ignored.
The CPU performs 32-bit access for stack operations in an interrupt handling. In this case, the
CPU read/write 32-bit data that consists of the PSR value as the eight high-order bits and the
return address as the 24 low-order bits. For more information, refer to the “S1C17 Family S1C17
Core Manual.”
The CPU adopts Harvard architecture that allows simultaneous processing of an instruction fetch and a data access. However, they are not performed simultaneously under one of the conditions listed below. This prolongs the
instruction fetch cycle for the number of data area bus cycles.
• When the CPU executes an instruction stored in the Flash area and accesses data in the Flash area
• When the CPU executes an instruction stored in the internal RAM area and accesses data in the internal RAM
area
4.3 Flash Memory
The Flash memory is used to store application programs and data. Address 0x8000 in the Flash area is defined as
the vector table base address by default, therefore a vector table must be located beginning from this address. For
more information on the vector table, refer to “Vector Table” in the “Interrupt Controller” chapter.
4.3.1 Flash Memory Pin
Table 4.3.1.1 shows the Flash memory pin.
Table 4.3.1.1 Flash Memory Pin
Pin name I/O Initial status Function
VPP P – Flash programming power supply
For the VPP voltage, refer to “Recommended Operating Conditions, Flash programming voltage VPP” in the “Electrical Characteristics” chapter.
Note: Always leave the V
4.3.2 Flash Bus Access Cycle Setting
There is a limit of frequency to access the Flash memory with no wait cycle, therefore, the number of bus access
cycles for reading must be changed according to the system clock frequency. The number of bus access cycles for
reading can be configured using the FLASHCWAIT.RDWAIT[1:0] bits. Select a setting for higher frequency than
the system clock.
PP pin open except when programming the Flash memory.
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S1C17
(1) When VPP is supplied externally
(S5U1C17001H)
(2) When VPP is generated internally
4.3.3 Flash Programming
The Flash memory supports on-board programming, so it can be programmed with the ROM data by using the debugger through an ICDmini. Figure 4.3.3.1 shows connection diagrams for on-board programming.
DCLK
VDD
DSIO
DST2
VPP
RDBG
CVPP
DCLK
ICDmini
(S5U1C17001H)
DSIO
DST2
CC OUT
Flash V
Figure 4.3.3.1 External Connection
DCLK
S1C17
DSIO
DST2
DCLK
VDD
DBG
R
PP
V
CVPP
ICDmini
DSIO
DST2
The VPP pin must be left open except when programming the Flash memory. However, it is not necessary to disconnect the wire when using ICDmini to supply the V
be supplied during Flash programming only. The V
generating the Flash programming voltage. Be sure to connect C
PP voltage, as ICDmini controls the power supply so that it will
PP voltage can also be generated by the internal power supply for
VPP for stabilizing the voltage when the VPP voltage
is supplied externally or for generating the voltage when the internal power supply is used.
For detailed information on ROM data programming method, refer to the “(S1C17 Family C Compiler Package)
S5U1C17001C Manual.” The IC can also be shipped after being programmed in the factory with the ROM data
developed. Should you desire to ship the IC with ROM data programmed from the factory, please contact our customer support.
Notes: • When programming the Flash memory by supplying the V
V
DD voltage is required.
• When programming the Flash memory by generating the V
V
DD voltage is required.
• Be sure to avoid using the V
PP pin output for driving external circuits when the VPP voltage is
PP voltage externally, 2.4 V or more
PP voltage internally, 2.7 V or more
generated internally.
4.4 RAM
The RAM can be used to execute the instruction codes copied from another memory as well as storing variables or
other data. This allows higher speed processing and lower power consumption than Flash memory.
Note: The 64 bytes at the end of the RAM is reserved as the debug RAM area. When using the debug
functions under application development, do not access this area from the application program.
This area can be used for applications of mass-produced devices that do not need debugging.
The RAM size used by the application can be configured to equal or less than the implemented size using the
MSCIRAMSZ.IRAMSZ[2:0] bits. For example, this function can be used to prevent creating programs that seek
to access areas outside the RAM area of the target model when developing an application for a model in which the
RAM size is smaller than this IC.
in the same operation (undefined value is read out) as when a reserved area is accessed.
4.5 Peripheral Circuit Control Registers
The control registers for the peripheral circuits are located in the 8K-byte area beginning with address 0x4000.
Table 4.5.1 shows the control register map. For details of each control register, refer to “List of Peripheral Circuit
Registers” in the appendix or “Control Registers” in each peripheral circuit chapter.
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After the limitation is applied, accessing an address outside the RAM area results
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Table 4.5.1 Peripheral Circuit Control Register Map
Peripheral circuit Address Register name
MISC registers (MISC) 0x4000 MSCPROT MISC System Protect Register
0x4002 MSCIRAMSZ MISC IRAM Size Register
0x4004 MSCTTBRL MISC Vector Table Address Low Register
0x4006 MSCTTBRH MISC Vector Table Address High Register
0x4008 MSCPSR MISC PSR Register
Power generator (PWG) 0x4020 PWGVD1CTL PWG V
D1 Regulator Control Register
Clock generator (CLG) 0x4040 CLGSCLK CLG System Clock Control Register
0x4042 CLGOSC CLG Oscillation Control Register
0x4046 CLGOSC1 CLG OSC1 Control Register
0x4048 CLGOSC3 CLG OSC3 Control Register
0x404c CLGINTF CLG Interrupt Flag Register
0x404e CLGINTE CLG Interrupt Enable Register
0x4050 CLGFOUT CLG FOUT Control Register
Interrupt controller (ITC) 0x4080 ITCLV0 ITC Interrupt Level Setup Register 0
0x4082 ITCLV1 ITC Interrupt Level Setup Register 1
0x4084 ITCLV2 ITC Interrupt Level Setup Register 2
0x4086 ITCLV3 ITC Interrupt Level Setup Register 3
0x4088 ITCLV4 ITC Interrupt Level Setup Register 4
0x408a ITCLV5 ITC Interrupt Level Setup Register 5
0x408c ITCLV6 ITC Interrupt Level Setup Register 6
0x408e ITCLV7 ITC Interrupt Level Setup Register 7
0x4090 ITCLV8 ITC Interrupt Level Setup Register 8
0x4092 ITCLV9 ITC Interrupt Level Setup Register 9
0x4094 ITCLV10 ITC Interrupt Level Setup Register 10
Watchdog timer (WDT2) 0x40a0 WDTCLK WDT2 Clock Control Register
0x40a2 WDTCTL WDT2 Control Register
0x40a4 WDTCMP WDT2 Counter Compare Match Register
Real-time clock (RTCA) 0x40c0 RTCCTL RTC Control Register
0x40c2 RTCALM1 RTC Second Alarm Register
0x40c4 RTCALM2 RTC Hour/Minute Alarm Register
0x40c6 RTCSWCTL RTC Stopwatch Control Register
0x40c8 RTCSEC RTC Second/1Hz Register
0x40ca RTCHUR RTC Hour/Minute Register
0x40cc RTCMON RTC Month/Day Register
0x40ce RTCYAR RTC Year/Week Register
0x40d0 RTCINTF RTC Interrupt Flag Register
0x40d2 RTCINTE RTC Interrupt Enable Register
Supply voltage detector (SVD3) 0x4100 SVDCLK SVD3 Clock Control Register
0x4102 SVDCTL SVD3 Control Register
0x4104 SVDINTF SVD3 Status and Interrupt Flag Register
0x4106 SVDINTE SVD3 Interrupt Enable Register
16-bit timer (T16) Ch.0 0x4160 T16_0CLK T16 Ch.0 Clock Control Register
0x4162 T16_0MOD T16 Ch.0 Mode Register
0x4164 T16_0CTL T16 Ch.0 Control Register
0x4166 T16_0TR T16 Ch.0 Reload Data Register
0x4168 T16_0TC T16 Ch.0 Counter Data Register
0x416a T16_0INTF T16 Ch.0 Interrupt Flag Register
0x416c T16_0INTE T16 Ch.0 Interrupt Enable Register
Flash controller (FLASHC) 0x41b0 FLASHCWAIT FLASHC Flash Read Cycle Register
I/O ports (PPORT) 0x4200 P0DAT P0 Port Data Register
0x4202 P0IOEN P0 Port Enable Register
0x4204 P0RCTL P0 Port Pull-up/down Control Register
0x4206 P0INTF P0 Port Interrupt Flag Register
0x4208 P0INTCTL P0 Port Interrupt Control Register
0x420a P0CHATEN P0 Port Chattering Filter Enable Register
0x420c P0MODSEL P0 Port Mode Select Register
0x420e P0FNCSEL P0 Port Function Select Register
0x4210 P1DAT P1 Port Data Register
0x4212 P1IOEN P1 Port Enable Register
0x4214 P1RCTL P1 Port Pull-up/down Control Register
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Peripheral circuit Address Register name
I/O ports (PPORT) 0x4216 P1INTF P1 Port Interrupt Flag Register
0x4218 P1INTCTL P1 Port Interrupt Control Register
0x421a P1CHATEN P1 Port Chattering Filter Enable Register
0x421c P1MODSEL P1 Port Mode Select Register
0x421e P1FNCSEL P1 Port Function Select Register
0x4220 P2DAT P2 Port Data Register
0x4222 P2IOEN P2 Port Enable Register
0x4224 P2RCTL P2 Port Pull-up/down Control Register
0x4226 P2INTF P2 Port Interrupt Flag Register
0x4228 P2INTCTL P2 Port Interrupt Control Register
0x422a P2CHATEN P2 Port Chattering Filter Enable Register
0x422c P2MODSEL P2 Port Mode Select Register
0x422e P2FNCSEL P2 Port Function Select Register
0x4230 P3DAT P3 Port Data Register
0x4232 P3IOEN P3 Port Enable Register
0x4234 P3RCTL P3 Port Pull-up/down Control Register
0x4236 P3INTF P3 Port Interrupt Flag Register
0x4238 P3INTCTL P3 Port Interrupt Control Register
0x423a P3CHATEN P3 Port Chattering Filter Enable Register
0x423c P3MODSEL P3 Port Mode Select Register
0x423e P3FNCSEL P3 Port Function Select Register
0x4240 P4DAT P4 Port Data Register
0x4242 P4IOEN P4 Port Enable Register
*1 *2 *3
*1 *2 *3
0x4244 P4RCTL P4 Port Pull-up/down Control Register
0x4246 P4INTF P4 Port Interrupt Flag Register
*1 *2 *3
0x4248 P4INTCTL P4 Port Interrupt Control Register
0x424a P4CHATEN P4 Port Chattering Filter Enable Register
0x424c P4MODSEL P4 Port Mode Select Register
0x424e P4FNCSEL P4 Port Function Select Register
*1 *2 *3
*1 *2 *3
0x42d0 PDDAT Pd Port Data Register
0x42d2 PDIOEN Pd Port Enable Register
0x42d4 PDRCTL Pd Port Pull-up/down Control Register
0x42dc PDMODSEL Pd Port Mode Select Register
0x42de PDFNCSEL Pd Port Function Select Register
0x42e0 PCLK P Port Clock Control Register
0x42e2 PINTFGRP P Port Interrupt Flag Group Register
Universal port multiplexer
(UPMUX)
0x4300 P0UPMUX0
0x4302 P0UPMUX1
0x4304 P0UPMUX2
0x4306 P0UPMUX3
0x4308 P1UPMUX0
0x430a P1UPMUX1
0x430c P1UPMUX2
0x430e P1UPMUX3
0x4310 P2UPMUX0
0x4312 P2UPMUX1
0x4314 P2UPMUX2
0x4316 P2UPMUX3
0x4318 P3UPMUX0
0x431a P3UPMUX1
0x431c P3UPMUX2
0x431e P3UPMUX3
P00–01 Universal Port Multiplexer Setting Register
P02–03 Universal Port Multiplexer Setting Register
P04–05 Universal Port Multiplexer Setting Register
P06–07 Universal Port Multiplexer Setting Register
P10–11 Universal Port Multiplexer Setting Register
P12–13 Universal Port Multiplexer Setting Register
P14–15 Universal Port Multiplexer Setting Register
P16–17 Universal Port Multiplexer Setting Register
P20–21 Universal Port Multiplexer Setting Register
P22–23 Universal Port Multiplexer Setting Register
P24–25 Universal Port Multiplexer Setting Register
P26–27 Universal Port Multiplexer Setting Register
P30–31 Universal Port Multiplexer Setting Register
P32–33 Universal Port Multiplexer Setting Register
P34–35 Universal Port Multiplexer Setting Register
P36–37 Universal Port Multiplexer Setting Register
UART (UART3) Ch.0 0x4380 UA0CLK UART3 Ch.0 Clock Control Register
0x4382 UA0MOD UART3 Ch.0 Mode Register
0x4384 UA0BR UART3 Ch.0 Baud-Rate Register
0x4386 UA0CTL UART3 Ch.0 Control Register
0x4388 UA0TXD UART3 Ch.0 Transmit Data Register
0x438a UA0RXD UART3 Ch.0 Receive Data Register
0x438c UA0INTF UART3 Ch.0 Status and Interrupt Flag Register
0x438e UA0INTE UART3 Ch.0 Interrupt Enable Register
0x4390 UA0CAWF UART3 Ch.0 Carrier Waveform Register
4 MEMORY AND BUS
*1 *2 *3
*1 *2 *3
*1 *2 *3
*1 *2 *3
*1 *2 *3
*1
*1 *2 *3
*1 *2 *3
*1
*1 *2 *3
*1 *2 *3
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Peripheral circuit Address Register name
16-bit timer (T16) Ch.1 0x43a0 T16_1CLK T16 Ch.1 Clock Control Register
0x43a2 T16_1MOD T16 Ch.1 Mode Register
0x43a4 T16_1CTL T16 Ch.1 Control Register
0x43a6 T16_1TR T16 Ch.1 Reload Data Register
0x43a8 T16_1TC T16 Ch.1 Counter Data Register
0x43aa T16_1INTF T16 Ch.1 Interrupt Flag Register
0x43ac T16_1INTE T16 Ch.1 Interrupt Enable Register
Synchronous serial interface
(SPIA) Ch.0
0x43b0 SPI0MOD SPIA Ch.0 Mode Register
0x43b2 SPI0CTL SPIA Ch.0 Control Register
0x43b4 SPI0TXD SPIA Ch.0 Transmit Data Register
0x43b6 SPI0RXD SPIA Ch.0 Receive Data Register
0x43b8 SPI0INTF SPIA Ch.0 Interrupt Flag Register
0x43ba SPI0INTE SPIA Ch.0 Interrupt Enable Register
2
I
C (I2C) 0x43c0 I2C0CLK I2C Ch.0 Clock Control Register
0x43c2 I2C0MOD I2C Ch.0 Mode Register
0x43c4 I2C0BR I2C Ch.0 Baud-Rate Register
0x43c8 I2C0OADR I2C Ch.0 Own Address Register
0x43ca I2C0CTL I2C Ch.0 Control Register
0x43cc I2C0TXD I2C Ch.0 Transmit Data Register
0x43ce I2C0RXD I2C Ch.0 Receive Data Register
0x43d0 I2C0INTF I2C Ch.0 Status and Interrupt Flag Register
0x43d2 I2C0INTE I2C Ch.0 Interrupt Enable Register
16-bit PWM timer (T16B) Ch.0 0x5000 T16B0CLK T16B Ch.0 Clock Control Register
0x5002 T16B0CTL T16B Ch.0 Counter Control Register
0x5004 T16B0MC T16B Ch.0 Max Counter Data Register
0x5006 T16B0TC T16B Ch.0 Timer Counter Data Register
0x5008 T16B0CS T16B Ch.0 Counter Status Register
0x500a T16B0INTF T16B Ch.0 Interrupt Flag Register
0x500c T16B0INTE T16B Ch.0 Interrupt Enable Register
0x5010 T16B0CCCTL0 T16B Ch.0 Compare/Capture 0 Control Register
0x5012 T16B0CCR0 T16B Ch.0 Compare/Capture 0 Data Register
0x5018 T16B0CCCTL1 T16B Ch.0 Compare/Capture 1 Control Register
0x501a T16B0CCR1 T16B Ch.0 Compare/Capture 1 Data Register
16-bit PWM timer (T16B) Ch.1 0x5040 T16B1CLK T16B Ch.1 Clock Control Register
0x5042 T16B1CTL T16B Ch.1 Counter Control Register
0x5044 T16B1MC T16B Ch.1 Max Counter Data Register
0x5046 T16B1TC T16B Ch.1 Timer Counter Data Register
0x5048 T16B1CS T16B Ch.1 Counter Status Register
0x504a T16B1INTF T16B Ch.1 Interrupt Flag Register
0x504c T16B1INTE T16B Ch.1 Interrupt Enable Register
0x5050 T16B1CCCTL0 T16B Ch.1 Compare/Capture 0 Control Register
0x5052 T16B1CCR0 T16B Ch.1 Compare/Capture 0 Data Register
0x5058 T16B1CCCTL1 T16B Ch.1 Compare/Capture 1 Control Register
0x505a T16B1CCR1 T16B Ch.1 Compare/Capture 1 Data Register
UART (UART3) Ch.1 0x5200 UA1CLK UART3 Ch.1 Clock Control Register
0x5202 UA1MOD UART3 Ch.1 Mode Register
0x5204 UA1BR UART3 Ch.1 Baud-Rate Register
0x5206 UA1CTL UART3 Ch.1 Control Register
0x5208 UA1TXD UART3 Ch.1 Transmit Data Register
0x520a UA1RXD UART3 Ch.1 Receive Data Register
0x520c UA1INTF UART3 Ch.1 Status and Interrupt Flag Register
0x520e UA1INTE UART3 Ch.1 Interrupt Enable Register
0x4390 UA1CAWF UART3 Ch.1 Carrier Waveform Register
16-bit timer (T16) Ch.2 0x5260 T16_2CLK T16 Ch.2 Clock Control Register
0x5262 T16_2MOD T16 Ch.2 Mode Register
0x5264 T16_2CTL T16 Ch.2 Control Register
0x5266 T16_2TR T16 Ch.2 Reload Data Register
0x5268 T16_2TC T16 Ch.2 Counter Data Register
0x526a T16_2INTF T16 Ch.2 Interrupt Flag Register
0x526c T16_2INTE T16 Ch.2 Interrupt Enable Register
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Peripheral circuit Address Register name
Synchronous serial interface
(SPIA) Ch.1
0x5270 SPI1MOD SPIA Ch.1 Mode Register
0x5272 SPI1CTL SPIA Ch.1 Control Register
0x5274 SPI1TXD SPIA Ch.1 Transmit Data Register
0x5276 SPI1RXD SPIA Ch.1 Receive Data Register
0x5278 SPI1INTF SPIA Ch.1 Interrupt Flag Register
0x527a SPI1INTE SPIA Ch.1 Interrupt Enable Register
Sound generator (SNDA) 0x5300 SNDCLK SNDA Clock Control Register
0x5302 SNDSEL SNDA Select Register
0x5304 SNDCTL SNDA Control Register
0x5306 SNDDAT SNDA Data Register
0x5308 SNDINTF SNDA Interrupt Flag Register
0x530a SNDINTE SNDA Interrupt Enable Register
IR remote controller (REMC3) 0x5320 REMCLK REMC3 Clock Control Register
0x5322 REMDBCTL REMC3 Data Bit Counter Control Register
0x5324 REMDBCNT REMC3 Data Bit Counter Register
0x5326 REMAPLEN REMC3 Data Bit Active Pulse Length Register
0x5328 REMDBLEN REMC3 Data Bit Length Register
0x532a REMINTF REMC3 Status and Interrupt Flag Register
0x532c REMINTE REMC3 Interrupt Enable Register
0x5330 REMCARR REMC3 Carrier Waveform Register
0x5332 REMCCTL REMC3 Carrier Modulation Control Register
R/F converter (RFC) Ch.0 0x5440 RFC0CLK RFC Ch.0 Clock Control Register
0x5442 RFC0CTL RFC Ch.0 Control Register
*1 *2 *3
0x5444 RFC0TRG RFC Ch.0 Oscillation Trigger Register
0x5446 RFC0MCL RFC Ch.0 Measurement Counter Low Register
0x5448 RFC0MCH RFC Ch.0 Measurement Counter High Register
0x544a RFC0TCL RFC Ch.0 Time Base Counter Low Register
0x544c RFC0TCH RFC Ch.0 Time Base Counter High Register
0x544e RFC0INTF RFC Ch.0 Interrupt Flag Register
0x5450 RFC0INTE RFC Ch.0 Interrupt Enable Register
R/F converter (RFC) Ch.1 0x5460 RFC1CLK RFC Ch.1 Clock Control Register
0x5462 RFC1CTL RFC Ch.1 Control Register
*1 *2 *3
0x5464 RFC1TRG RFC Ch.1 Oscillation Trigger Register
0x5466 RFC1MCL RFC Ch.1 Measurement Counter Low Register
0x5468 RFC1MCH RFC Ch.1 Measurement Counter High Register
0x546a RFC1TCL RFC Ch.1 Time Base Counter Low Register
0x546c RFC1TCH RFC Ch.1 Time Base Counter High Register
0x546e RFC1INTF RFC Ch.1 Interrupt Flag Register
0x5470 RFC1INTE RFC Ch.1 Interrupt Enable Register
16-bit timer (T16) Ch.3 0x5480 T16_3CLK T16 Ch.3 Clock Control Register
0x5482 T16_3MOD T16 Ch.3 Mode Register
0x5484 T16_3CTL T16 Ch.3 Control Register
0x5486 T16_3TR T16 Ch.3 Reload Data Register
0x5488 T16_3TC T16 Ch.3 Counter Data Register
0x548a T16_3INTF T16 Ch.3 Interrupt Flag Register
0x548c T16_3INTE T16 Ch.3 Interrupt Enable Register
12-bit A/D converter (ADC12A) 0x54a2 ADC12_0CTL ADC12A Ch.0 Control Register
0x54a4 ADC12_0TRG
ADC12A Ch.0 Trigger/Analog Input Select Register
0x54a6 ADC12_0CFG ADC12A Ch.0 Configuration Register
0x54a8 ADC12_0INTF ADC12A Ch.0 Interrupt Flag Register
0x54aa ADC12_0INTE ADC12A Ch.0 Interrupt Enable Register
0x54ac ADC12_0AD0D ADC12A Ch.0 Result Register 0
0x54ae ADC12_0AD1D ADC12A Ch.0 Result Register 1
0x54b0 ADC12_0AD2D ADC12A Ch.0 Result Register 2
0x54b2 ADC12_0AD3D ADC12A Ch.0 Result Register 3
0x54b4 ADC12_0AD4D ADC12A Ch.0 Result Register 4
0x54b6 ADC12_0AD5D ADC12A Ch.0 Result Register 5
0x54b8 ADC12_0AD6D ADC12A Ch.0 Result Register 6
0x54ba ADC12_0AD7D ADC12A Ch.0 Result Register 7
*1 Cannot be used in the S1C17M20/M23 (24-pin package).
*2 Cannot be used in the S1C17M20/M23 (32-pin package).
*3 Cannot be used in the S1C17M21/M24.
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TECHNICAL MANUAL (Rev. 1.0)
4 MEMORY AND BUS
*1 *2 *3
*1 *2 *3
*1 *2 *3
*1 *2 *3
*1 *2 *3
*1 *2 *3
*1 *2 *3
*1 *2 *3
*1 *2 *3
*1 *2 *3
*1 *2 *3
*1 *2 *3
*1 *2 *3
*1 *2 *3
*1 *2 *3
*1 *2 *3
*1
*1
*1 *2 *3
*1 *2 *3
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4 MEMORY AND BUS
4.5.1 System-Protect Function
The system-protect function protects control registers and bits from writings. They cannot be rewritten unless write
protection is removed by writing 0x0096 to the MSCPROT.PROT[15:0] bits. This function is provided to prevent
deadlock that may occur when a system-related register is altered by a runaway CPU. See “Control Registers” in
each peripheral circuit to identify the registers and bits with write protection.
Note: Once write protection is removed using the MSCPROT.PROT[15:0] bits, write enabled status is
maintained until write protection is applied again. After the registers/bits required have been altered, apply write protection.
4.6 Control Registers
MISC System Protect Register
Register name Bit Bit name Initial Reset R/W Remarks
MSCPROT 15–0 PROT[15:0] 0x0000 H0 R/W –
Bits 15–0 PROT[15:0]
These bits protect the control registers related to the system against writings.
0x0096 (R/W): Disable system protection
Other than 0x0096 (R/W): Enable system protection
While the system protection is enabled, any data will not be written to the affected control bits (bits
with “WP” or “R/WP” appearing in the R/W column).
MISC IRAM Size Register
Register name Bit Bit name Initial Reset R/W Remarks
MSCIRAMSZ 15–9 – 0x00 – R –
8 (reserved) 0 H0 R/WP Always set to 0.
7–3 – 0x04 – R –
2–0 IRAMSZ[2:0] 0x2 H0 R/WP
Bits 15–3 Reserved
Bits 2–0 IRAMSZ[2:0]
These bits set the internal RAM size that can be used.
Table 4.6.1 Internal RAM Size Selections
MSCIRAMSZ.IRAMSZ[2:0] bits Internal RAM size
0x7–0x3 Reserved
0x2 2KB
0x1 1KB
0x0 512B
FLASHC Flash Read Cycle Register
Register name Bit Bit name Initial Reset R/W Remarks
FLASHCWAIT 15–9 – 0x00 – R –
8 (reserved) 0 H0 R/WP Always set to 0.
7–2 – 0x00 – R
1–0 RDWAIT[1:0] 0x1 H0 R/WP
Bits 15–2 Reserved
–
Bits 1–0 RDWAIT[1:0]
These bits set the number of bus access cycles for reading from the Flash memory.
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Table 4.6.2 Setting Number of Bus Access Cycles for Flash Read
FLASHCWAIT.RDWAIT[1:0] bits Number of bus Access cycles System clock frequency
0x3 4 21.0 MHz (max.)
0x2 3 18.9 MHz (max.)
0x1 2 12.6 MHz (max.)
0x0 1 6.3 MHz (max.)
Note: Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured.
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5 INTERRUPT CONTROLLER (ITC)
Internal reset signal
5 Interrupt Controller (ITC)
5.1 Overview
The features of the ITC are listed below.
• Honors interrupt requests from the peripheral circuits and outputs the interrupt request, interrupt level and vector
number signals to the CPU.
• The interrupt level of each interrupt source is selectable from among eight levels.
• Priorities of the simultaneously generated interrupts are established from the interrupt level.
• Handles the simultaneously generated interrupts with the same interrupt level as smaller vector number has higher priority.
Figure 5.1.1 shows the configuration of the ITC.
Debug interrupt
Peripheral circuit
Interrupt request
Peripheral circuit
Internal data bus
Interrupt request
Watchdog timer
• • •
CPU core
HALT/SLEEP
cancelation signal
Interrupt request
Interrupt level
Vector number
NMI
ITC
ILVx[2:0]
Interrupt
control
circuit
Figure 5.1.1 ITC Configuration
• • •
ILVy[2:0]
5.2 Vector Table
The vector table contains the vectors to the interrupt handler routines (handler routine start address) that will be
read by the CPU to execute the handler when an interrupt occurs.
Table 5.2.1 shows the vector table.
Table 5.2.1 Vector Table
TTBR initial value = 0x8000
Vector number/
Software interrupt
number
0 (0x00) TTBR + 0x00 Reset • Low input to the #RESET pin
1 (0x01) TTBR + 0x04 Address misaligned interrupt Memory access instruction 2
– (0xfffc00) Debugging interrupt brk instruction, etc. 3
2 (0x02) TTBR + 0x08 NMI Watchdog timer overflow
3 (0x03) TTBR + 0x0c Reserved for C compiler – –
Vector address Hardware interrupt name Cause of hardware interrupt Priority
• Power-on reset
• Key reset
• Watchdog timer overflow
• Supply voltage detector reset
*2
*2
1
4
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5 INTERRUPT CONTROLLER (ITC)
Vector number/
Software interrupt
number
4 (0x04) TTBR + 0x10 Supply voltage detector
5 (0x05) TTBR + 0x14 Port interrupt Port input
6 (0x06) TTBR + 0x18 reserved –
7 (0x07) TTBR + 0x1c Clock generator interrupt • IOSC oscillation stabilization waiting completion
8 (0x08) TTBR + 0x20 Real-time clock interrupt • 1-day, 1-hour, 1-minute, and 1-second
9 (0x09) TTBR + 0x24 16-bit timer Ch.0 interrupt Underflow
10 (0x0a) TTBR + 0x28 UART Ch.0 interrupt • End of transmission
11 (0x0b) TTBR + 0x2c 16-bit timer Ch.1 interrupt Underflow
12 (0x0c) TTBR + 0x30 Synchronous serial interface
13 (0x0d) TTBR + 0x34 I
14 (0x0e) TTBR + 0x38 16-bit PWM timer Ch.0
15 (0x0f) TTBR + 0x3c 16-bit PWM timer Ch.1
16 (0x10) TTBR + 0x40 UART Ch.1 interrupt • End of transmission
17 (0x11) TTBR + 0x44 Sound generator interrupt • Sound buffer empty
18 (0x12) TTBR + 0x48
19 (0x13) TTBR + 0x4c reserved –
20 (0x14) TTBR + 0x50 R/F converter Ch.0 interrupt • Reference oscillation completion
21 (0x15) TTBR + 0x54 R/F converter Ch.1 interrupt • Reference oscillation completion
22 (0x16) TTBR + 0x58 16-bit timer Ch.2 interrupt Underflow
Vector address Hardware interrupt name Hardware interrupt flag Priority
Low power supply voltage detection High
interrupt
• OSC1 oscillation stabilization waiting completion
• OSC3 oscillation stabilization waiting completion
• OSC1 oscillation stop
• IOSC oscillation auto-trimming completion
1/32-second, 1/8-second, 1/4-second, and 1/2-second
•
• Stopwatch 1 Hz, 10 Hz, and 100 Hz
• Alarm
• Theoretical regulation completion
• Framing error
• Parity error
• Overrun error
• Receive buffer two bytes full
• Receive buffer one byte full
• Transmit buffer empty
• End of transmission
Ch.0 interrupt
• Receive buffer full
• Transmit buffer empty
2
C interrupt • End of data transfer
• Overrun error
• General call address reception
• NACK reception
• STOP condition
• START condition
• Error detection
• Receive buffer full
• Transmit buffer empty
• Capture overwrite
interrupt
• Compare/capture
• Counter MAX
• Counter zero
• Capture overwrite
interrupt
• Compare/capture
• Counter MAX
• Counter zero
• Framing error
• Parity error
• Overrun error
• Receive buffer two bytes full
• Receive buffer one byte full
• Transmit buffer empty
• Sound output completion
IR remote controller interrupt
• Compare AP
• Compare DB
• Sensor A oscillation completion
• Sensor B oscillation completion
• Measurement counter overflow error
• Time base counter overflow error
• Sensor A oscillation completion
• Sensor B oscillation completion
• Measurement counter overflow error
• Time base counter overflow error
*1
↑
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Vector number/
Software interrupt
number
23 (0x17) TTBR + 0x5c Synchronous serial interface
24 (0x18) TTBR + 0x60 16-bit timer Ch.3 interrupt Underflow
25 (0x19) TTBR + 0x64 12-bit A/D converter
26 (0x1a) TTBR + 0x68 reserved –
: : : : ↓
31 (0x1f) TTBR + 0x7c reserved – Low
*1 When the same interrupt level is set
*2 Either reset or NMI can be selected as the watchdog timer interrupt with software.
Vector address Hardware interrupt name Hardware interrupt flag Priority
Ch.1 interrupt
interrupt
• End of transmission
• Receive buffer full
• Transmit buffer empty
• Overrun error
• Analog input signal m A/D conversion completion
• Analog input signal m A/D conversion result over-
write error
*1
5.2.1 Vector Table Base Address (TTBR)
The MSCTTBRL and MSCTTBRH registers are provided to set the base (start) address of the vector table in which
interrupt vectors are programmed. “TTBR” described in Table 5.2.1 means the value set to these registers. After an
initial reset, the MSCTTBRL and MSCTTBRH registers are set to address 0x8000. Therefore, even when the vector table location is changed, it is necessary that at least the reset vector be written to the above address. Bits 7 to 0
in the MSCTTBRL register are fixed at 0, so the vector table always begins from a 256-byte boundary address.
5.3 Initialization
The following shows an example of the initial setting procedure related to interrupts:
1. Execute the di instruction to set the CPU into interrupt disabled state.
2. If the vector table start address is different from the default address, set it to the MSCTTBRL and MSCTTBRH
registers after removing system protection by writing 0x0096 to the MSCPROT.PROT[15:0] bits. Then, write a
value other than 0x0096 to the MSCPROT.PROT[15:0] bits to set system protection.
3. Set the interrupt enable bit of the peripheral circuit to 0 (interrupt disabled).
4. Set the interrupt level for the peripheral circuit using the ITCLVx.ILVx[2:0] bits in the ITC.
5. Configure the peripheral circuit and start its operation.
6. Clear the interrupt factor flag of the peripheral circuit.
7. Set the interrupt enable bit of the peripheral circuit to 1 (interrupt enabled).
8. Execute the ei instruction to set the CPU into interrupt enabled state.
5.4 Maskable Interrupt Control and Operations
5.4.1 Peripheral Circuit Interrupt Control
The peripheral circuit that generates interrupts includes an interrupt enable bit and an interrupt flag for each interrupt cause.
Interrupt flag: The flag is set to 1 when the interrupt cause occurs. The clear condition depends on the periph-
eral circuit.
Interrupt enable bit: By setting this bit to 1 (interrupt enabled), an interrupt request will be sent to the ITC when the
interrupt flag is set to 1. When this bit is set to 0 (interrupt disabled), no interrupt request will
be sent to the ITC even if the interrupt flag is set to 1. An interrupt request is also sent to the
ITC if the status is changed to interrupt enabled when the interrupt flag is 1.
For specific information on causes of interrupts, interrupt flags, and interrupt enable bits, refer to the respective peripheral circuit descriptions.
Note: To prevent occurrence of unnecessary interrupts, the corresponding interrupt flag should be
cleared before setting the interrupt enable bit to 1 (interrupt enabled) and before terminating the
interrupt handler routine.
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5.4.2 ITC Interrupt Request Processing
On receiving an interrupt signal from a peripheral circuit, the ITC sends an interrupt request, the interrupt level,
and the vector number to the CPU. Vector numbers are determined by the ITC internal hardware for each interrupt
cause, as shown in Table 5.2.1. The interrupt level is a value to configure the priority, and it can be set to between 0
(low) and 7 (high) using the ITCLVx.ILVx[2:0] bits provided for each interrupt source. The default ITC settings are
level 0 for all maskable interrupts. Interrupt requests are not accepted by the CPU if the level is 0.
The ITC outputs the interrupt request with the highest priority to the CPU in accordance with the following conditions if interrupt requests are input to the ITC simultaneously from two or more peripheral circuits.
• The interrupt with the highest interrupt level takes precedence.
• If multiple interrupt requests are input with the same interrupt level, the interrupt with the lowest vector number
takes precedence.
The other interrupts occurring at the same time are held until all interrupts with higher priority levels have been accepted by the CPU.
If an interrupt cause with higher priority occurs while the ITC is outputting an interrupt request signal to the CPU
(before being accepted by the CPU), the ITC alters the vector number and interrupt level signals to the setting information on the more recent interrupt. The previously occurring interrupt is held. The held interrupt is canceled
and no interrupt is generated if the interrupt flag in the peripheral circuit is cleared via software.
Note: Before changing the interrupt level, make sure that no interrupt of which the level is changed can
be generated (the interrupt enable bit of the peripheral circuit is set to 0 or the peripheral circuit
is deactivated).
5.4.3 Conditions to Accept Interrupt Requests by the CPU
The CPU accepts an interrupt request sent from the ITC when all of the following conditions are met:
• The IE (Interrupt Enable) bit of the PSR has been set to 1.
• The interrupt request that has occurred has a higher interrupt level than the value set in the IL[2:0] (Interrupt
Level) bits of the PSR.
• No other interrupt request having higher priority, such as NMI, has occurred.
5.5 NMI
The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This interrupt takes precedence over other interrupts and is unconditionally accepted by the CPU.
For detailed information on generating NMI, refer to the “Watchdog Timer” chapter.
5.6 Software Interrupts
The CPU provides the “int imm5” and “intl imm5, imm3” instructions allowing the software to generate any interrupts. The operand imm5 specifies a vector number (0–31) in the vector table. In addition to this, the intl instruction
has the operand imm3 to specify the interrupt level (0–7) to be set to the IL[2:0] bits in the PSR. The software interrupt cannot be disabled (non-maskable interrupt). The processor performs the same interrupt processing operation
as that of the hardware interrupt.
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5.7 Interrupt Processing by the CPU
The CPU samples interrupt requests for each cycle. On accepting an interrupt request, the CPU switches to interrupt processing immediately after execution of the current instruction has been completed.
Interrupt processing involves the following steps:
1. The PSR and current program counter (PC) values are saved to the stack.
2. The PSR IE bit is cleared to 0 (disabling subsequent maskable interrupts).
3. The PSR IL[2:0] bits are set to the received interrupt level. (The NMI does not affect the IL bits.)
4. The vector for the interrupt occurred is loaded to the PC to execute the interrupt handler routine.
When an interrupt is accepted, Step 2 prevents subsequent maskable interrupts. Setting the IE bit to 1 in the interrupt handler routine allows handling of multiple interrupts. In this case, since the IL[2:0] bits are changed by Step 3,
only an interrupt with a higher level than that of the currently processed interrupt will be accepted.
Ending interrupt handler routines using the reti instruction returns the PSR to the state before the interrupt occurred.
The program resumes processing following the instruction being executed at the time the interrupt occurred.
Note: When HALT or SLEEP mode is canceled, the CPU jumps to the interrupt handler routine after
executing one instruction. To execute the interrupt handler routine immediately after HALT or
SLEEP mode is canceled, place the nop instruction at just behind the halt/slp instruction.
5.8 Control Registers
MISC Vector Table Address Low Register
Register name Bit Bit name Initial Reset R/W Remarks
MSCTTBRL 15–8 TTBR[15:8] 0x80 H0 R/WP –
7–0 TTBR[7:0] 0x00 H0 R
Bits 15–0 TTBR[15:0]
These bits set the vector table base address (16 low-order bits).
MISC Vector Table Address High Register
Register name Bit Bit name Initial Reset R/W Remarks
MSCTTBRH 15–8 – 0x00 – R –
7–0 TTBR[23:16] 0x00 H0 R/WP
Bits 15–8 Reserved
Bits 7–0 TTBR[23:16]
These bits set the vector table base address (eight high-order bits).
ITC Interrupt Level Setup Register x
Register name Bit Bit name Initial Reset R/W Remarks
ITCLVx 15–11 – 0x00 – R –
10–8 I LVy
7–3 – 0x00 – R
2–0 I LVy
Bits 15–11 Reserved
Bits 7–3 Reserved
Bits 10–8 ILVy
Bits 2–0 ILVy
1[2:0] (y1 = 2x +1)
0[2:0] (y0 = 2x)
These bits set the interrupt level of each interrupt.
1[2:0] 0x0 H0 R/W
0[2:0] 0x0 H0 R/W
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Table 5.8.1 Interrupt Level and Priority Settings
ITCLVx.ILVy[2:0] bits Interrupt level Priority
0x7 7 High
0x6 6 ↑
· · · · · ·
0x1 1 ↓
0x0 0 Low
The following shows the ITCLVx register configuration in this IC.
Table 5.8.2 List of ITCLVx Registers
Register name Bit Bit name Initial Reset R/W Remarks
ITCLV0
(ITC Interrupt Level
Setup Register 0)
ITCLV1
(ITC Interrupt Level
Setup Register 1)
ITCLV2
(ITC Interrupt Level
Setup Register 2)
ITCLV3
(ITC Interrupt Level
Setup Register 3)
ITCLV4
(ITC Interrupt Level
Setup Register 4)
ITCLV5
(ITC Interrupt Level
Setup Register 5)
ITCLV6
(ITC Interrupt Level
Setup Register 6)
ITCLV7
(ITC Interrupt Level
Setup Register 7)
ITCLV8
(ITC Interrupt Level
Setup Register 8)
15–11 – 0x00 – R –
10–8 ILV1[2:0] 0x0 H0 R/W Port interrupt (ILVPPORT)
7–3 – 0x00 – R –
2–0 ILV0[2:0] 0x0 H0 R/W Supply voltage detector interrupt
(ILVSVD3)
15–11 – 0x00 – R –
10–8 ILV3[2:0] 0x0 H0 R/W Clock generator interrupt (ILVCLG)
7–0 – 0x00 – R –
15–11 – 0x00 – R –
10–8 ILV5[2:0] 0x0 H0 R/W 16-bit timer Ch.0 interrupt (ILVT16_0)
7–3 – 0x00 – R –
2–0 ILV4[2:0] 0x0 H0 R/W Real-time clock interrupt (ILVRTCA_0)
15–11 – 0x00 – R –
10–8 ILV7[2:0] 0x0 H0 R/W 16-bit timer Ch.1 interrupt (ILVT16_1)
7–3 – 0x00 – R –
2–0 ILV6[2:0] 0x0 H0 R/W UART Ch.0 interrupt (ILVUART3_0)
15–11 – 0x00 – R –
10–8 ILV9[2:0] 0x0 H0 R/W I
2
C interrupt (ILVI2C_0)
7–3 – 0x00 – R –
2–0 ILV8[2:0] 0x0 H0 R/W Synchronous serial interface Ch.0
interrupt (ILVSPIA_0)
15–11 – 0x00 – R –
10–8 ILV11[2:0] 0x0 H0 R/W 16-bit PWM timer Ch.1 interrupt
(ILVT16B_1)
7–3 – 0x00 – R –
2–0 ILV10[2:0] 0x0 H0 R/W 16-bit PWM timer Ch.0 interrupt
(ILVT16B_0)
15–11 – 0x00 – R –
10–8 ILV13[2:0] 0x0 H0 R/W Sound generator interrupt
(ILVSNDA_0)
7–3 – 0x00 – R –
2–0 ILV12[2:0] 0x0 H0 R/W UART Ch.1 interrupt (ILVUART3_1)
15–8 – 0x00 – R –
7–3 – 0x00 – R –
2–0 ILV14[2:0] 0x0 H0 R/W IR remote controller interrupt
(ILVREMC3_0)
15–11 – 0x00 – R –
10–8 ILV17[2:0] 0x0 H0 R/W R/F converter Ch.1 interrupt
(ILVRFC_1)
7–3 – 0x00 – R –
2–0 ILV16[2:0] 0x0 H0 R/W R/F converter Ch.0 interrupt
(ILVRFC_0)
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Register name Bit Bit name Initial Reset R/W Remarks
ITCLV9
(ITC Interrupt Level
Setup Register 9)
15–11 – 0x00 – R –
10–8 ILV19[2:0] 0x0 H0 R/W Synchronous serial interface Ch.1
interrupt (ILVSPIA_1)
7–3 – 0x00 – R –
2–0 ILV18[2:0] 0x0 H0 R/W 16-bit timer Ch.2 interrupt (ILVT16_2)
ITCLV10
(ITC Interrupt Level
Setup Register 10)
15–11 – 0x00 – R –
10–8 ILV21[2:0] 0x0 – R/W 12-bit A/D converter interrupt
(ILVADC12A_0)
7–3 – 0x00 – R –
2–0 ILV20[2:0] 0x0 – R/W 16-bit timer Ch.3 interrupt (ILVT16_3)
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6 I/O Ports (PPORT)
6.1 Overview
PPORT controls the I/O ports. The main features are outlined below.
• Allows port-by-port function configurations.
- Each port can be configured with or without a pull-up or pull-down resistor.
- Each port can be configured with or without a chattering filter.
- Allows selection of the function (general-purpose I/O port (GPIO) function, up to four peripheral I/O functions) to be assigned to each port.
• Ports, except for those shared with debug pins, are initially placed into Hi-Z state.
(No current passes through the pin during this Hi-Z state.)
Note: ‘x’, which is used in the port names Pxy, register names, and bit names, refers to a port group (x
= 0, 1, 2, ··· , d) and ‘y’ refers to a port number (y = 0, 1, 2, ··· , 7).
Figure 6.1.1 shows the configuration of PPORT.
Table 6.1.1 Port Configuration of S1C17M20/M21/M22/M23/M24/M25
Item
24-pin package 32-pin package
Port groups included P0 P0[3:0] (4)
P1
P1[5:2] (4)
P2
P2[7:4] (4)
P3
P3[2:0] (3)
P4
– (0) – (0) – (0) P4[2:0]
Pd
Pd[2:0] (3)
(
Pd2: output only
Total number of ports
Input/output port: 17
Output port: 1
Ports for debug function
Key-entry reset function
*1 Ports with general-purpose I/O function (GPIO)
*2 Ports with interrupt function
S1C17M20/M23
*1, *2
P0[3:0] (4)
*1, *2
P1[5:0] (6)
*1, *2
P2[7:2] (6)
*1, *2
P3[2:0] (3)
*1
Pd[4:0] (5)
)
(
Pd2: output only
Input/output port: 23
Output port: 1
S1C17M21/M24 S1C17M22/M25
*1, *2
P0[3:0] (4)
*1, *2
P1[5:0] (6)
*1, *2
P2[7:2] (6)
*1, *2
P3[2:0] (3)
*1
Pd[4:0] (5)
)
(
Pd2: output only
Input/output port: 23
Output port: 1
Pd[2:0]
Supported (P0[3:0])
*1, *2
P0[7:0] (8)
*1, *2
P1[7:0]
*1, *2
P2[7:0]
*1, *2
P3[7:0]
*1
Pd[4:0] (5)
)
(
Pd2: output only
Input/output port: 39
Output port: 1
*1, *2
*1, *2
(8)
*1, *2
(8)
*1, *2
(8)
*1, *2
(3)
*1
)
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6 I/O PORTS (PPORT)
Pxy
PPORT
Pxy
Pxy
Peripheral I/O function 0 I/O control
Peripheral I/O function 1 I/O control
Peripheral I/O function 2 I/O control
Peripheral I/O function 3 I/O control
General-purpose
I/O control
GPIO function
I/O cell
control signal
Output signal
Input signal
PxOUTy
PxyMUX[1:0]
GPIO/
peripheral I/O
function
switching
circuit
PxOENy
PxIENy
PxPDPUy
PxRENy
PxINy
KRSTCFG[1:0]
CLKSRC[1:0]
CLKDIV[3:0]
PxSELy
Clock
generator
Interrupt
controller
System reset
controller
DBRUN
Px
y
CLK_PPORT
I/O cell
Internal data bus
Exist only in the ports that supports the interrupt function.
Chattering
filter
Interrupt
control circuit
Key-entry
reset control
circuit
PxCHATENy
PxEDGEy
PxIFy
PxIEy
PxINT
Key-entry
reset signal
Over voltage tolerant fail-safe type I/O cell
Analog control signal
Standard I/O cell
6.2 I/O Cell Structure and Functions
Figure 6.2.1 shows the I/O cell Configuration.
Pull-up/down
Control signal
Input signal
Input control signal
Output signal
Output control signal
Analog signal
Refer to “Pin Descriptions” in the “Overview” chapter for the cell type, either the over voltage tolerant fail-safe
type I/O cell or the standard I/O cell, included in each port.
VDD
Pull-up/down
control
VSS
VDD
VDD
Analog signal
control
Figure 6.1.1 PPORT Configuration
Pull-up/down
Control signal
RINU/
R
IND
∗ No diode is
connected at
DD side.
the V
Pxy
V
SS
Output control signal
Input signal
Input control signal
Output signal
Analog signal
Analog control signal
Figure 6.2.1 I/O Cell Configuration
VDD
Pull-up/down
control
VSS
VDD
VDD
Analog signal
control
RINU/
R
IND
VDD
V
Pxy
SS
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6.2.1 Schmitt Input
The input functions are all configured with the Schmitt interface level. When a port is set to input disable status
(PxIOEN.PxIENy bit = 0), unnecessary current is not consumed if the Pxy pin is placed into floating status.
6.2.2 Over Voltage Tolerant Fail-Safe Type I/O Cell
The over voltage tolerant fail-safe type I/O cell allows interfacing without passing unnecessary current even if a
voltage exceeding V
biased without supplying V
DD is applied to the port. Also unnecessary current is not consumed when the port is externally
DD. However, be sure to avoid applying a voltage exceeding the recommended maxi-
mum operating power supply voltage to the port.
6.2.3 Pull-Up/Pull-Down
The GPIO port has a pull-up/pull-down function. Either pull-up or pull-down may be selected for each port individually. This function may also be disabled for the port that does not require pulling up/down.
When the port level is switched from low to high through the pull-up resistor included in the I/O cell or from high
to low through the pull-down resistor, a delay will occur in the waveform rising/falling edge depending on the time
constant by the pull-up/pull-down resistance and the pin load capacitance. The rising/falling time is commonly determined by the following equation:
t
PR = -RINU × (CIN + CBOARD) × ln(1 - VT+/VDD) (Eq. 6.1)
t
PF = -RIND × (CIN + CBOARD) × ln(1 - VT- /VDD)
Where
t
PR: Rising time (port level = low → high) [second]
t
PF: Falling time (port level = high → low) [second]
V
T+: High level Schmitt input threshold voltage [V]
V
T-: Low level Schmitt input threshold voltage [V]
R
INU/RIND: Pull-up/pull-down resistance [W]
C
IN: Pin capacitance [F]
C
BOARD: Parasitic capacitance on the board [F]
6.2.4 CMOS Output and High Impedance State
The I/O cells except for analog output can output signals in the VDD and VSS levels. Also the GPIO ports may be
put into high-impedance (Hi-Z) state.
6.3 Clock Settings
6.3.1 PPORT Operating Clock
When using the chattering filter for entering external signals to PPORT, the PPORT operating clock CLK_PPORT
must be supplied to PPORT from the clock generator.
The CLK_PPORT supply should be controlled as in the procedure shown below.
1. Enable the clock source in the clock generator if it is stopped (refer to “Clock Generator” in the “Power Supply,
Reset, and Clocks” chapter).
2. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
3. Set the following PCLK register bits:
- PCLK.CLKSRC[1:0] bits (Clock source selection)
- PCLK.CLKDIV[3:0] bits (Clock division ratio selection = Clock frequency setting)
4. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
Settings in Step 3 determine the input sampling time of the chattering filter.
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6.3.2 Clock Supply in SLEEP Mode
When using the
configured so that it will keep suppling by writing 0 to the
source.
If the
CLGOSC.xxxxSLPC bit for the CLK_PPORT clock source is 1, the CLK_PPORT clock source is deactivated during SLEEP mode and it disables the
bit setting (chattering filter enabled/disabled).
chattering filter function during SLEEP mode, the PPORT operating clock CLK_PPORT must be
CLGOSC.xxxxSLPC bit for the CLK_PPORT clock
chattering filter function regardless of the PxCHATEN.PxCHATENy
6.3.3 Clock Supply in DEBUG Mode
The CLK_PPORT supply during DEBUG mode should be controlled using the PCLK.DBRUN bit.
The CLK_PPORT supply to PPORT is suspended when the CPU enters DEBUG mode if the PCLK.DBRUN bit
= 0. After the CPU returns to normal mode, the CLK_PPORT supply resumes. The PPORT chattering filter stops
operating when the CLK_PPORT supply is suspended. If the chattering filter is enabled in PPORT, the input port
function is also deactivated. However, the control registers can be altered. If the PCLK.DBRUN bit = 1, the CLK_
PPORT supply is not suspended and the chattering filter will keep operating in DEBUG mode.
6.4 Operations
6.4.1 Initialization
After a reset, the ports except for the debugging function are configured as shown below.
• Port input: Disabled
• Port output: Disabled
• Pull-up: Off
• Pull-down: Off
• Port pins: High impedance state
• Port function: Configured to GPIO
This status continues until the ports are configured via software. The debugging function ports are configured for
debug signal input/output.
Initial settings when using a port for a peripheral I/O function
When using the Pxy port for a peripheral I/O function, perform the following software initial settings:
1. Set the following PxIOEN register bits:
- Set the PxIOEN.PxIENy bit to 0. (Disable input)
- Set the PxIOEN.PxOENy bit to 0. (Disable output)
2. Set the PxMODSEL.PxSELy bit to 0. (Disable peripheral I/O function)
3. Initialize the peripheral circuit that uses the pin.
4. Set the PxFNCSEL.PxyMUX[1:0] bits. (Select peripheral I/O function)
5. Set the PxMODSEL.PxSELy bit to 1. (Enable peripheral I/O function)
For the list of the peripheral I/O functions that can be assigned to each port of this IC, refer to “Control Register
and Port Function Configuration of this IC.” For the specific information on the peripheral I/O functions, refer
to the respective peripheral circuit chapter.
Initial settings when using a port as a general-purpose output port
(only for the ports with GPIO function)
When using the Pxy port pin as a general-purpose output pin, perform the following software initial settings:
1. Set the PxIOEN.PxOENy bit to 1. (Enable output)
2. Set the PxMODSEL.PxSELy bit to 0. (Enable GPIO function)
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Initial settings when using a port as a general-purpose input port
(only for the ports with GPIO function)
When using the Pxy port pin as a general-purpose input pin, perform the following software initial settings:
1. Write 0 to the PxINTCTL.PxIEy bit. * (Disable interrupt)
2. When using the chattering filter, configure the PPORT operating clock (see “PPORT Operating Clock”) and
set the PxCHATEN.PxCHATENy bit to 1. *
When the chattering filter is not used, set the PxCHATEN.PxCHATENy bit to 0 (supply of the PPORT op-
erating clock is not required).
3. Configure the following PxRCTL register bits when pulling up/down the port using the internal pull-up or
down resistor:
- PxRCTL.PxPDPUy bit (Select pull-up or pull-down resistor)
- Set the PxRCTL.PxRENy bit to 1. (Enable pull-up/down)
Set the PxRCTL.PxRENy bit to 0 if the internal pull-up/down resistors are not used.
4. Set the PxMODSEL.PxSELy bit to 0. (Enable GPIO function)
5. Configure the following bits when using the port input interrupt: *
- Write 1 to the PxINTF.PxIFy bit. (Clear interrupt flag)
- PxINTCTL.PxEDGEy bit (Select interrupt edge (input rising edge/falling edge))
- Set the PxINTCTL.PxIEy bit to 1. (Enable interrupt)
6. Set the following PxIOEN register bits:
- Set the PxIOEN.PxOENy bit to 0. (Disable output)
- Set the PxIOEN.PxIENy bit to 1. (Enable input)
* Steps 1 and 5 are required for the ports with an interrupt function. Step 2 is required for the ports with a chat-
tering filter function.
Table 6.4.1.1 lists the port status according to the combination of data input/output control and pull-up/down
control.
Table 6.4.1.1 GPIO Port Control List
PxIOEN.
PxIENy bit
0 0 0 × Disabled Off (Hi-Z) *1
0 0 1 0 Disabled Pulled down
0 0 1 1 Disabled Pulled up
1 0 0 × Enabled Disabled Off (Hi-Z) *2
1 0 1 0 Enabled Disabled Pulled down
1 0 1 1 Enabled Disabled Pulled up
0 1 0 × Disabled Enabled Off
0 1 1 0 Disabled Enabled Off
0 1 1 1 Disabled Enabled Off
1 1 1 0 Enabled Enabled Off
1 1 1 1 Enabled Enabled Off
*1: Initial status. Current does not flow if the pin is placed into floating status.
*2: Use of the pull-up or pull-down function is recommended, as undesired current will flow if the port input is set to floating status.
PxIOEN.
PxOENy bit
PxRCTL.
PxRENy bit
PxRCTL.
PxPDPUy bit
Input Output
Pull-up/pull-down
condition
Note: If the PxMODSEL.PxSELy bit for the port without a GPIO function is set to 0, the port goes into
initial status (refer to “Initial Settings”). The GPIO control bits are configured to a read-only bit always read out as 0.
6.4.2 Port Input/Output Control
Peripheral I/O function control
The port for which a peripheral I/O function is selected is controlled by the peripheral circuit. For more infor-
mation, refer to the respective peripheral circuit chapter.
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Setting output data to a GPIO port
Write data (1 = high output, 0 = low output) to be output from the Pxy pin to the PxD AT. P xOUTy bit.
Reading input data from a GPIO port
The data (1 = high input, 0 = low input) input from the Pxy pin can be read out from the PxD AT. P xINy bit.
Chattering filter function
Some ports have a chattering filter function and it can be controlled in each port. This function is enabled by
setting the PxCHATEN.PxCHATENy bit to 1. The input sampling time to remove chattering is determined by
the CLK_PPORT frequency configured using the PCLK register in common to all ports. The chattering filter
removes pulses with a shorter width than the input sampling time.
2 to 3
Input sampling time = ———————————— [second] (Eq.6.2)
CLK_PPORT frequency [Hz]
Make sure the Pxy port interrupt is disabled before altering the PCLK register and PxCHATEN.PxCHATENy
bit settings. A Pxy port interrupt may erroneously occur if these settings are altered in an interrupt enabled status. Furthermore, enable the interrupt after a lapse of four or more CLK_PPORT cycles from enabling the chattering filter function.
If the clock generator is configured so that it will supply CLK_PPORT to PPORT in SLEEP mode, the chatter-
ing filter of the port will function even in SLEEP mode. If CLK_PPORT is configured to stop in SLEEP mode,
PPORT inactivates the chattering filter during SLEEP mode to input pin status transitions directly to itself.
Key-entry reset function
This function issues a reset request when low-level pulses are input to all the specified ports simultaneously.
Make the following settings when using this function:
1. Configure the ports to be used for key-entry reset as general-purpose input ports (refer to “Initial settings
when using a port as a general-purpose input port (only for the ports with GPIO function)”).
2. Configure the input pin combination for key-entry reset using the PCLK.KRSTCFG[1:0] bits.
Note: When enabling the key-entry reset function, be sure to configure the port pins to be used for it
as general-purpose input pins before setting the PCLK.KRSTCFG[1:0] bits.
PPORT issues a reset request immediately after all the input pins specified by the PCLK.KRSTCFG[1:0] are
set to a low level if the chattering filter function is disabled (initial status). To issue a reset request only when
low-level signals longer than the time configured are input, enable the chattering filter function for all the ports
used for key-entry reset.
The pins configured for key-entry reset can also be used as general-purpose input pins.
6.5 Interrupts
When the GPIO function is selected for the port with an interrupt function, the port input interrupt function can be
used.
Table 6.5.1 Port Input Interrupt Function
Interrupt Interrupt flag Set condition Clear condition
Port input interrupt PxINTF.PxIF
PINTFGRP.PxINT Setting an interrupt flag in the port group Clearing PxINTF.PxIF
y
Rising or falling edge of the input signal Writing 1
y
Interrupt edge selection
Port input interrupts will occur at the falling edge of the input signal when setting the PxINTCTL.PxEDGEy bit
to 1, or the rising edge when setting to 0.
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Interrupt enable
PPORT provides interrupt enable bits (PxINTCTL.PxIEy bit) corresponding to each interrupt flag. An inter-
rupt request is sent to the interrupt controller only when the interrupt flag, of which interrupt has been enabled
by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt Controller”
chapter.
Interrupt check in port group unit
When interrupts are enabled in two or more port groups, check the PINTFGRP.PxINT bit in the interrupt han-
dler first. It helps minimize the handler codes for finding the port that has generated an interrupt. If this bit is
set to 1, an interrupt has occurred in the port group. Next, check the PxINTF.PxIFy bit set to 1 in the port group
to determine the port that has generated an interrupt. Clearing the PxINTF.PxIFy bit also clears the PINTFGRP.
PxINT bit. If the port is set to interrupt disabled status by the PxINTCTL.PxIEy bit, the PINTFGRP.PxINT bit
will not be set even if the PxINTF.PxIFy bit is set to 1.
6.6 Control Registers
This section describes the same control registers of all port groups as a single register. For the register and bit configurations in each port group and their initial values, refer to “Control Register and Port Function Configuration of
this IC.”
Px Port Data Register
Register name Bit Bit name Initial Reset R/W Remarks
PxDAT 15–8 PxOUT[7:0] 0x00 H0 R/W –
7–0 PxIN[7:0] 0x00 H0 R
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
*3: The initial value may be changed by the port.
Bits 15–8 PxOUT[7:0]
These bits are used to set data to be output from the GPIO port pins.
1 (R/W): Output high level from the port pin
0 (R/W): Output low level from the port pin
When output is enabled (PxIOEN.PxOENy bit = 1), the port pin outputs the data set here. Although
data can be written when output is disabled (PxIOEN.PxOENy bit = 0), it does not affect the pin status.
These bits do not affect the outputs when the port is used as a peripheral I/O function.
Bits 7–0 PxIN[7:0]
The GPIO port pin status can be read out from these bits.
1 (R): Port pin = High level
0 (R): Port pin = Low level
The port pin status can be read out when input is enabled (PxIOEN.PxIENy bit = 1). When input is
disabled (PxIOEN.PxIENy bit = 0), these bits are always read as 0.
When the port is used for a peripheral I/O function, the input value cannot be read out from these bits.
Px Port Enable Register
Register name Bit Bit name Initial Reset R/W Remarks
PxIOEN 15–8 PxIEN[7:0] 0x00 H0 R/W –
7–0 PxOEN[7:0] 0x00 H0 R/W
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15–8 PxIEN[7:0]
These bits enable/disable the GPIO port input.
1 (R/W): Enable (The port pin status is input.)
0 (R/W): Disable (Input data is fixed at 0.)
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When both data output and data input are enabled, the pin output status controlled by this IC can be
read.
These bits do not affect the input control when the port is used as a peripheral I/O function.
Bits 7–0 PxOEN[7:0]
These bits enable/disable the GPIO port output.
1 (R/W): Enable (Data is output from the port pin.)
0 (R/W): Disable (The port is placed into Hi-Z.)
These bits do not affect the output control when the port is used as a peripheral I/O function.
Px Port Pull-up/down Control Register
Register name Bit Bit name Initial Reset R/W Remarks
PxRCTL 15–8 PxPDPU[7:0] 0x00 H0 R/W –
7–0 PxREN[7:0] 0x00 H0 R/W
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15–8 PxPDPU[7:0]
These bits select either the pull-up resistor or the pull-down resistor when using a resistor built into
the port.
1 (R/W): Pull-up resistor
0 (R/W): Pull-down resistor
The selected pull-up/down resistor is enabled when the PxRCTL.PxRENy bit = 1.
Bits 7–0 PxREN[7:0]
These bits enable/disable the port pull-up/down control.
1 (R/W): Enable (The built-in pull-up/down resistor is used.)
0 (R/W): Disable (No pull-up/down control is performed.)
Enabling this function pulls up or down the port when output is disabled (PxIOEN.PxOENy bit = 0).
When output is enabled (PxIOEN.PxOENy bit = 1), the PxRCTL.PxRENy bit setting is ineffective re-
gardless of how the PxIOEN.PxIENy bit is set and the port is not pulled up/down.
These bits do not affect the pull-up/down control when the port is used as a peripheral I/O function.
Px Port Interrupt Flag Register
Register name Bit Bit name Initial Reset R/W Remarks
PxINTF 15–8 – 0x00 – R –
7–0 PxIF[7:0] 0x00 H0 R/W Cleared by writing 1.
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15–8 Reserved
Bits 7–0 PxIF[7:0]
These bits indicate the port input interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
Px Port Interrupt Control Register
Register name Bit Bit name Initial Reset R/W Remarks
PxINTCTL 15–8 PxEDGE[7:0] 0x00 H0 R/W –
7–0 PxIE[7:0] 0x00 H0 R/W
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
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Bits 15–8 PxEDGE[7:0]
These bits select the input signal edge to generate a port input interrupt.
1 (R/W): An interrupt will occur at a falling edge.
0 (R/W): An interrupt will occur at a rising edge.
Bits 7–0 PxIE[7:0]
These bits enable port input interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared
before enabling interrupts.
Px Port Chattering Filter Enable Register
Register name Bit Bit name Initial Reset R/W Remarks
PxCHATEN 15–8 – 0x00 – R –
7–0 PxCHATEN[7:0] 0x00 H0 R/W
*1: The bit configuration differs depending on the port group.
Bits 15–8 Reserved
Bits 7–0 PxCHATEN[7:0]
These bits enable/disable the chattering filter function.
1 (R/W): Enable (The chattering filter is used.)
0 (R/W): Disable (The chattering filter is bypassed.)
Px Port Mode Select Register
Register name Bit Bit name Initial Reset R/W Remarks
PxMODSEL 15–8 – 0x00 – R –
7–0 PxSEL[7:0] 0x00 H0 R/W
*1: The bit configuration differs depending on the port group.
*2: The initial value may be changed by the port.
Bits 15–8 Reserved
Bits 7–0 PxSEL[7:0]
These bits select whether each port is used for the GPIO function or a peripheral I/O function.
1 (R/W): Use peripheral I/O function
0 (R/W): Use GPIO function
Px Port Function Select Register
Register name Bit Bit name Initial Reset R/W Remarks
PxFNCSEL 15–14 Px7MUX[1:0] 0x0 H0 R/W –
13–12 Px6MUX[1:0] 0x0 H0 R/W
11–10 Px5MUX[1:0] 0x0 H0 R/W
9–8 Px4MUX[1:0] 0x0 H0 R/W
7–6 Px3MUX[1:0] 0x0 H0 R/W
5–4 Px2MUX[1:0] 0x0 H0 R/W
3–2 Px1MUX[1:0] 0x0 H0 R/W
1–0 Px0MUX[1:0] 0x0 H0 R/W
*1: The bit configuration differs depending on the port group.
*2: The initial value may be changed by the port.
Bits 15–14 Px7MUX[1:0]
: :
Bits 1–0 Px0MUX[1:0]
These bits select the peripheral I/O function to be assigned to each port pin.
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Table 6.6.1 Selecting Peripheral I/O Function
PxFNCSEL.PxyMUX[1:0] bits Peripheral I/O function
0x3 Function 3
0x2 Function 2
0x1 Function 1
0x0 Function 0
This selection takes effect when the PxMODSEL.PxSELy bit = 1.
P Port Clock Control Register
Register name Bit Bit name Initial Reset R/W Remarks
PCLK 15–9 – 0x00 – R –
8 DBRUN 0 H0 R/WP
7–4 CLKDIV[3:0] 0x0 H0 R/WP
3–2 KRSTCFG[1:0] 0x0 H0 R/WP
1–0 CLKSRC[1:0] 0x0 H0 R/WP
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the PPORT operating clock is supplied in DEBUG mode or not.
1 (R/WP): Clock supplied in DEBUG mode
0 (R/WP): No clock supplied in DEBUG mode
Bits 7–4 CLKDIV[3:0]
These bits select the division ratio of the PPORT operating clock (chattering filter clock).
Bits 3–2 KRSTCFG[1:0]
These bits configure the key-entry reset function.
Table 6.6.2 Key-Entry Reset Function Settings
PCLK.KRSTCFG[1:0] bits key-entry reset
0x3 Reset when P0[3:0] inputs = all low
0x2 Reset when P0[2:0] inputs = all low
0x1 Reset when P0[1:0] inputs = all low
0x0 Disable
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of PPORT (chattering filter).
The PPORT operating clock should be configured by selecting the clock source using the PCLK.
CLKSRC[1:0] bits and the clock division ratio using the PCLK.CLKDIV[3:0] bits as shown in Table
6.6.3. These settings determine the input sampling time of the chattering filter.
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Table 6.6.3 Clock Source and Division Ratio Settings
PCLK.CLKDIV[3:0] bits
0xf 1/32,768 1/1
0xe 1/16,384
0xd 1/8,192
0xc 1/4,096
0xb 1/2,048
0xa 1/1,024
0x9 1/512
0x8 1/256
0x7 1/128
0x6 1/64
0x5 1/32
0x4 1/16
0x3 1/8
0x2 1/4
0x1 1/2
0x0 1/1
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
0x0 0x1 0x2 0x3
IOSC OSC1 OSC3 EXOSC
PCLK.CLKSRC[1:0] bits
P Port Interrupt Flag Group Register
Register name Bit Bit name Initial Reset R/W Remarks
PINTFGRP 15–13 – 0x0 – R –
12 PcINT 0 H0 R
11 PbINT 0 H0 R
10 PaINT 0 H0 R
9 P9INT 0 H0 R
8 P8INT 0 H0 R
7 P7INT 0 H0 R
6 P6INT 0 H0 R
5 P5INT 0 H0 R
4 P4INT 0 H0 R
3 P3INT 0 H0 R
2 P2INT 0 H0 R
1 P1INT 0 H0 R
0 P0INT 0 H0 R
*1: Only the bits corresponding to the port groups that support interrupts are provided.
Bits 15–13 Reserved
6 I/O PORTS (PPORT)
Bits 12–0 PxINT
These bits indicate that Px port group includes a port that has generated an interrupt.
1 (R): A port generated an interrupt
0 (R): No port generated an interrupt
The PINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt
is cleared.
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6.7 Control Register and Port Function Configuration of this IC
This section shows the PPORT control register/bit configuration in this IC and the list of peripheral I/O functions
selectable for each port.
Note: The control bits for the ports that are not available in the model are reserved bits. Do not alter
them from the initial value.
6.7.1 P0 Port Group
The P0 port group supports the GPIO and interrupt functions.
Table 6.7.1.1 Control Registers for P0 Port Group
M21/
Register name Bit Bit name Initial Reset R/W Remarks
P0DAT
(P0 Port Data
Register)
15 P0OUT7 0 H0 R/W – – – –
14 P0OUT6 0 H0 R/W – – –
13 P0OUT5 0 H0 R/W – – –
12 P0OUT4 0 H0 R/W – – –
11 P0OUT3 0 H0 R/W
10 P0OUT2 0 H0 R/W
9 P0OUT1 0 H0 R/W
8 P0OUT0 0 H0 R/W
7 P0IN7 0 H0 R – – – –
6 P0IN6 0 H0 R – – –
5 P0IN5 0 H0 R – – –
4 P0IN4 0 H0 R – – –
3 P0IN3 0 H0 R
2 P0IN2 0 H0 R
1 P0IN1 0 H0 R
0 P0IN0 0 H0 R
P0IOEN
(P0 Port Enable
Register)
15 P0IEN7 0 H0 R/W – – – –
14 P0IEN6 0 H0 R/W – – –
13 P0IEN5 0 H0 R/W – – –
12 P0IEN4 0 H0 R/W – – –
11 P0IEN3 0 H0 R/W
10 P0IEN2 0 H0 R/W
9 P0IEN1 0 H0 R/W
8 P0IEN0 0 H0 R/W
7 P0OEN7 0 H0 R/W – – – –
6 P0OEN6 0 H0 R/W – – –
5 P0OEN5 0 H0 R/W – – –
4 P0OEN4 0 H0 R/W – – –
3 P0OEN3 0 H0 R/W
2 P0OEN2 0 H0 R/W
1 P0OEN1 0 H0 R/W
0 P0OEN0 0 H0 R/W
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Register name Bit Bit name Initial Reset R/W Remarks
P0RCTL
(
P0 Port Pull-up/down
Control Register
15 P0PDPU7 0 H0 R/W – – – –
14 P0PDPU6 0 H0 R/W – – –
)
13 P0PDPU5 0 H0 R/W – – –
12 P0PDPU4 0 H0 R/W – – –
11 P0PDPU3 0 H0 R/W
10 P0PDPU2 0 H0 R/W
9 P0PDPU1 0 H0 R/W
8 P0PDPU0 0 H0 R/W
7 P0REN7 0 H0 R/W – – – –
6 P0REN6 0 H0 R/W – – –
5 P0REN5 0 H0 R/W – – –
4 P0REN4 0 H0 R/W – – –
3 P0REN3 0 H0 R/W
2 P0REN2 0 H0 R/W
1 P0REN1 0 H0 R/W
0 P0REN0 0 H0 R/W
P0INTF
(P0 Port Interrupt
Flag Register)
15–8 – 0x00 – R – – – – –
7 P0IF7 0 H0 R/W Cleared by writing 1.– – –
6 P0IF6 0 H0 R/W – – –
5 P0IF5 0 H0 R/W – – –
4 P0IF4 0 H0 R/W – – –
3 P0IF3 0 H0 R/W
2 P0IF2 0 H0 R/W
1 P0IF1 0 H0 R/W
0 P0IF0 0 H0 R/W
P0INTCTL
(P0 Port Interrupt
Control Register)
15 P0EDGE7 0 H0 R/W – – – –
14 P0EDGE6 0 H0 R/W – – –
13 P0EDGE5 0 H0 R/W – – –
12 P0EDGE4 0 H0 R/W – – –
11 P0EDGE3 0 H0 R/W
10 P0EDGE2 0 H0 R/W
9 P0EDGE1 0 H0 R/W
8 P0EDGE0 0 H0 R/W
7 P0IE7 0 H0 R/W – – – –
6 P0IE6 0 H0 R/W – – –
5 P0IE5 0 H0 R/W – – –
4 P0IE4 0 H0 R/W – – –
3 P0IE3 0 H0 R/W
2 P0IE2 0 H0 R/W
1 P0IE1 0 H0 R/W
0 P0IE0 0 H0 R/W
P0CHATEN
(P0 Port Chattering
Filter Enable Register)
15–8 – 0x00 – R – – – – –
7 P0CHATEN7 0 H0 R/W – – – –
6 P0CHATEN6 0 H0 R/W – – –
5 P0CHATEN5 0 H0 R/W – – –
4 P0CHATEN4 0 H0 R/W – – –
3 P0CHATEN3 0 H0 R/W
2 P0CHATEN2 0 H0 R/W
1 P0CHATEN1 0 H0 R/W
0 P0CHATEN0 0 H0 R/W
6 I/O PORTS (PPORT)
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Register name Bit Bit name Initial Reset R/W Remarks
P0MODSEL
(P0 Port Mode Select
Register)
15–8 – 0x00 – R – – – – –
7 P0SEL7 0 H0 R/W – – – –
6 P0SEL6 0 H0 R/W – – –
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5 P0SEL5 0 H0 R/W – – –
4 P0SEL4 0 H0 R/W – – –
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
P0FNCSEL
(P0 Port Function
Select Register)
3 P0SEL3 0 H0 R/W
2 P0SEL2 0 H0 R/W
1 P0SEL1 0 H0 R/W
0 P0SEL0 0 H0 R/W
15–14 P07MUX[1:0] 0x0 H0 R/W – – – –
13–12 P06MUX[1:0] 0x0 H0 R/W – – –
11–10 P05MUX[1:0] 0x0 H0 R/W – – –
9–8 P04MUX[1:0] 0x0 H0 R/W – – –
7–6 P03MUX[1:0] 0x0 H0 R/W
5–4 P02MUX[1:0] 0x0 H0 R/W
3–2 P01MUX[1:0] 0x0 H0 R/W
1–0 P00MUX[1:0] 0x0 H0 R/W
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
Table 6.7.1.2 P0 Port Group Function Assignment
P0SELy = 0 P0SELy = 1
Port
name
P00 P00 T16B Ch.0 EXCL00 UPMUX *1 – – – – ✓ ✓ ✓ ✓
P01 P01 T16B Ch.0 EXCL01 UPMUX *1 – – – – ✓ ✓ ✓ ✓
P02 P02 SNDA BZOUT UPMUX *1 – – – – ✓ ✓ ✓ ✓
P03 P03 SNDA #BZOUT UPMUX *1 – – – – ✓ ✓ ✓ ✓
P04 P04 RFC Ch.0 RFCLKO0 UPMUX *1 – – – – – – – ✓
P05 P05 RFC Ch.1 RFCLKO1 UPMUX *1 – – – – – – – ✓
P06 P06 – – UPMUX *1 – – – – – – – ✓
P07 P07 – – UPMUX *1 – – – – – – – ✓
*1: Refer to the “Universal Port Multiplexer” chapter.
GPIO
P0yMUX = 0x0
(Function 0)
Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin
P0yMUX = 0x1
(Function 1)
P0yMUX = 0x2
(Function 2)
P0yMUX = 0x3
(Function 3)
M20/M23
24pin 32pin
M21/
M24
M21/
M24
M22/
M25
✓
✓
✓
✓
✓
✓
✓
✓
M22/
M25
6.7.2 P1 Port Group
The P1 port group supports the GPIO and interrupt functions.
Table 6.7.2.1 Control Registers for P1 Port Group
M21/
Register name Bit Bit name Initial Reset R/W Remarks
P1DAT
(P1 Port Data
Register)
15 P1OUT7 0 H0 R/W – – – –
14 P1OUT6 0 H0 R/W – – –
13 P1OUT5 0 H0 R/W
12 P1OUT4 0 H0 R/W
11 P1OUT3 0 H0 R/W
10 P1OUT2 0 H0 R/W
M20/M23
24pin 32pin
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
9 P1OUT1 0 H0 R/W –
8 P1OUT0 0 H0 R/W –
7 P1IN7 0 H0 R – – – –
6 P1IN6 0 H0 R – – –
5 P1IN5 0 H0 R
4 P1IN4 0 H0 R
3 P1IN3 0 H0 R
2 P1IN2 0 H0 R
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
1 P1IN1 0 H0 R –
0 P1IN0 0 H0 R –
6-14
Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
M22/
M24
M25
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓
✓
✓
✓
Page 79
Register name Bit Bit name Initial Reset R/W Remarks
P1IOEN
(P1 Port Enable
Register)
15 P1IEN7 0 H0 R/W – – – –
14 P1IEN6 0 H0 R/W – – –
13 P1IEN5 0 H0 R/W
12 P1IEN4 0 H0 R/W
11 P1IEN3 0 H0 R/W
10 P1IEN2 0 H0 R/W
9 P1IEN1 0 H0 R/W –
8 P1IEN0 0 H0 R/W –
7 P1OEN7 0 H0 R/W – – – –
6 P1OEN6 0 H0 R/W – – –
5 P1OEN5 0 H0 R/W
4 P1OEN4 0 H0 R/W
3 P1OEN3 0 H0 R/W
2 P1OEN2 0 H0 R/W
1 P1OEN1 0 H0 R/W –
0 P1OEN0 0 H0 R/W –
P1RCTL
(
P1 Port Pull-up/down
Control Register
15 P1PDPU7 0 H0 R/W – – – –
14 P1PDPU6 0 H0 R/W – – –
)
13 P1PDPU5 0 H0 R/W
12 P1PDPU4 0 H0 R/W
11 P1PDPU3 0 H0 R/W
10 P1PDPU2 0 H0 R/W
9 P1PDPU1 0 H0 R/W –
8 P1PDPU0 0 H0 R/W –
7 P1REN7 0 H0 R/W – – – –
6 P1REN6 0 H0 R/W – – –
5 P1REN5 0 H0 R/W
4 P1REN4 0 H0 R/W
3 P1REN3 0 H0 R/W
2 P1REN2 0 H0 R/W
1 P1REN1 0 H0 R/W –
0 P1REN0 0 H0 R/W –
P1INTF
(P1 Port Interrupt
Flag Register)
15–8 – 0x00 – R – – – – –
7 P1IF7 0 H0 R/W Cleared by writing 1.– – –
6 P1IF6 0 H0 R/W – – –
5 P1IF5 0 H0 R/W
4 P1IF4 0 H0 R/W
3 P1IF3 0 H0 R/W
2 P1IF2 0 H0 R/W
1 P1IF1 0 H0 R/W –
0 P1IF0 0 H0 R/W –
P1INTCTL
(P1 Port Interrupt
Control Register)
15 P1EDGE7 0 H0 R/W – – – –
14 P1EDGE6 0 H0 R/W – – –
13 P1EDGE5 0 H0 R/W
12 P1EDGE4 0 H0 R/W
11 P1EDGE3 0 H0 R/W
10 P1EDGE2 0 H0 R/W
9 P1EDGE1 0 H0 R/W –
8 P1EDGE0 0 H0 R/W –
7 P1IE7 0 H0 R/W – – – –
6 P1IE6 0 H0 R/W – – –
5 P1IE5 0 H0 R/W
4 P1IE4 0 H0 R/W
3 P1IE3 0 H0 R/W
2 P1IE2 0 H0 R/W
1 P1IE1 0 H0 R/W –
0 P1IE0 0 H0 R/W –
S1C17M20/M21/M22/M23/M24/M25 Seiko Epson Corporation
TECHNICAL MANUAL (Rev. 1.0)
6 I/O PORTS (PPORT)
M21/
M20/M23
24pin 32pin
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
M24
M22/
M25
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
6-15
Page 80
6 I/O PORTS (PPORT)
Register name Bit Bit name Initial Reset R/W Remarks
P1CHATEN
(P1 Port Chattering
Filter Enable Register)
15–8 – 0x00 – R – – – – –
7 P1CHATEN7 0 H0 R/W – – – –
6 P1CHATEN6 0 H0 R/W – – –
5 P1CHATEN5 0 H0 R/W
4 P1CHATEN4 0 H0 R/W
3 P1CHATEN3 0 H0 R/W
2 P1CHATEN2 0 H0 R/W
1 P1CHATEN1 0 H0 R/W –
0 P1CHATEN0 0 H0 R/W –
P1MODSEL
(P1 Port Mode Select
Register)
15–8 – 0x00 – R – – – – –
7 P1SEL7 0 H0 R/W – – – –
6 P1SEL6 0 H0 R/W – – –
5 P1SEL5 0 H0 R/W
4 P1SEL4 0 H0 R/W
3 P1SEL3 0 H0 R/W
2 P1SEL2 0 H0 R/W
1 P1SEL1 0 H0 R/W –
0 P1SEL0 0 H0 R/W –
P1FNCSEL
(P1 Port Function
Select Register)
15–14 P17MUX[1:0] 0x0 H0 R/W – – – –
13–12 P16MUX[1:0] 0x0 H0 R/W – – –
11–10 P15MUX[1:0] 0x0 H0 R/W
9–8 P14MUX[1:0] 0x0 H0 R/W
7–6 P13MUX[1:0] 0x0 H0 R/W
5–4 P12MUX[1:0] 0x0 H0 R/W
3–2 P11MUX[1:0] 0x0 H0 R/W –
1–0 P10MUX[1:0] 0x0 H0 R/W –
M20/M23
24pin 32pin
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
M21/
M24
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
M22/
M25
✓
✓
✓
✓
✓
✓
Table 6.7.2.2 P1 Port Group Function Assignment
P1SELy = 0 P1SELy = 1
Port
name
P10 P10 – – UPMUX *1 – – – – – ✓ ✓ ✓
P11 P11 – – UPMUX *1 – – – – – ✓ ✓ ✓
P12 P12 REMC3 REMO UPMUX *1 – – – – ✓ ✓ ✓ ✓
P13 P13 CLG FOUT UPMUX *1 – – – – ✓ ✓ ✓ ✓
P14 P14 ADC12A #ADTRG0 UPMUX *1 – – – – ✓ ✓ ✓ ✓
P15 P15 REMC3 CLPLS UPMUX *1 – – – – ✓ ✓ ✓ ✓
P16 P16 – – UPMUX *1 – – – – – – – ✓
P17 P17 – – UPMUX *1 – – – – – – – ✓
*1: Refer to the “Universal Port Multiplexer” chapter.
GPIO
P1yMUX = 0x0
(Function 0)
Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin
P1yMUX = 0x1
(Function 1)
P1yMUX = 0x2
(Function 2)
P1yMUX = 0x3
(Function 3)
M20/M23
24pin 32pin
M21/
M24
M22/
M25
6-16
Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
Page 81
6.7.3 P2 Port Group
The P2 port group support the GPIO and interrupt functions.
Table 6.7.3.1 Control Registers for P2 Port Group
Register name Bit Bit name Initial Reset R/W Remarks
P2DAT
(P2 Port Data
Register)
P2IOEN
(P2 Port Enable
Register)
P2RCTL
(
P2 Port Pull-up/down
Control Register
15 P2OUT7 0 H0 R/W –
14 P2OUT6 0 H0 R/W
13 P2OUT5 0 H0 R/W
12 P2OUT4 0 H0 R/W
11 P2OUT3 0 H0 R/W –
10 P2OUT2 0 H0 R/W –
9 P2OUT1 0 H0 R/W – – –
8 P2OUT0 0 H0 R/W – – –
7 P2IN7 0 H0 R –
6 P2IN6 0 H0 R
5 P2IN5 0 H0 R
4 P2IN4 0 H0 R
3 P2IN3 0 H0 R –
2 P2IN2 0 H0 R –
1 P2IN1 0 H0 R – – –
0 P2IN0 0 H0 R – – –
15 P2IEN7 0 H0 R/W –
14 P2IEN6 0 H0 R/W
13 P2IEN5 0 H0 R/W
12 P2IEN4 0 H0 R/W
11 P2IEN3 0 H0 R/W –
10 P2IEN2 0 H0 R/W –
9 P2IEN1 0 H0 R/W – – –
8 P2IEN0 0 H0 R/W – – –
7 P2OEN7 0 H0 R/W –
6 P2OEN6 0 H0 R/W
5 P2OEN5 0 H0 R/W
4 P2OEN4 0 H0 R/W
3 P2OEN3 0 H0 R/W –
2 P2OEN2 0 H0 R/W –
1 P2OEN1 0 H0 R/W – – –
0 P2OEN0 0 H0 R/W – – –
15 P2PDPU7 0 H0 R/W –
14 P2PDPU6 0 H0 R/W
)
13 P2PDPU5 0 H0 R/W
12 P2PDPU4 0 H0 R/W
11 P2PDPU3 0 H0 R/W –
10 P2PDPU2 0 H0 R/W –
9 P2PDPU1 0 H0 R/W – – –
8 P2PDPU0 0 H0 R/W – – –
7 P2REN7 0 H0 R/W –
6 P2REN6 0 H0 R/W
5 P2REN5 0 H0 R/W
4 P2REN4 0 H0 R/W
3 P2REN3 0 H0 R/W –
2 P2REN2 0 H0 R/W –
1 P2REN1 0 H0 R/W – – –
0 P2REN0 0 H0 R/W – – –
6 I/O PORTS (PPORT)
M21/
M20/M23
24pin 32pin
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
M24
M22/
M25
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
S1C17M20/M21/M22/M23/M24/M25 Seiko Epson Corporation
TECHNICAL MANUAL (Rev. 1.0)
6-17
Page 82
6 I/O PORTS (PPORT)
Register name Bit Bit name Initial Reset R/W Remarks
P2INTF
(P2 Port Interrupt
Flag Register)
15–8 – 0x00 – R – – – – –
7 P2IF7 0 H0 R/W Cleared by writing
6 P2IF6 0 H0 R/W
1.
5 P2IF5 0 H0 R/W
4 P2IF4 0 H0 R/W
3 P2IF3 0 H0 R/W –
2 P2IF2 0 H0 R/W –
1 P2IF1 0 H0 R/W – – –
0 P2IF0 0 H0 R/W – – –
P2INTCTL
(P2 Port Interrupt
Control Register)
15 P2EDGE7 0 H0 R/W –
14 P2EDGE6 0 H0 R/W
13 P2EDGE5 0 H0 R/W
12 P2EDGE4 0 H0 R/W
11 P2EDGE3 0 H0 R/W –
10 P2EDGE2 0 H0 R/W –
9 P2EDGE1 0 H0 R/W – – –
8 P2EDGE0 0 H0 R/W – – –
7 P2IE7 0 H0 R/W –
6 P2IE6 0 H0 R/W
5 P2IE5 0 H0 R/W
4 P2IE4 0 H0 R/W
3 P2IE3 0 H0 R/W –
2 P2IE2 0 H0 R/W –
1 P2IE1 0 H0 R/W – – –
0 P2IE0 0 H0 R/W – – –
P2CHATEN
(P2 Port Chattering
Filter Enable Register)
15–8 – 0x00 – R – – – – –
7 P2CHATEN7 0 H0 R/W –
6 P2CHATEN6 0 H0 R/W
5 P2CHATEN5 0 H0 R/W
4 P2CHATEN4 0 H0 R/W
3 P2CHATEN3 0 H0 R/W –
2 P2CHATEN2 0 H0 R/W –
1 P2CHATEN1 0 H0 R/W – – –
0 P2CHATEN0 0 H0 R/W – – –
P2MODSEL
(P2 Port Mode Select
Register)
15–8 – 0x00 – R – – – – –
7 P2SEL7 0 H0 R/W –
6 P2SEL6 0 H0 R/W
5 P2SEL5 0 H0 R/W
4 P2SEL4 0 H0 R/W
3 P2SEL3 0 H0 R/W –
2 P2SEL2 0 H0 R/W –
1 P2SEL1 0 H0 R/W – – –
0 P2SEL0 0 H0 R/W – – –
P2FNCSEL
(P2 Port Function
Select Register)
15–14 P27MUX[1:0] 0x0 H0 R/W –
13–12 P26MUX[1:0] 0x0 H0 R/W
11–10 P25MUX[1:0] 0x0 H0 R/W
9–8 P24MUX[1:0] 0x0 H0 R/W
7–6 P23MUX[1:0] 0x0 H0 R/W –
5–4 P22MUX[1:0] 0x0 H0 R/W –
3–2 P21MUX[1:0] 0x0 H0 R/W – – –
1–0 P20MUX[1:0] 0x0 H0 R/W – – –
M20/M23
24pin 32pin
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
M21/
M24
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
M22/
M25
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
6-18
Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
Page 83
6 I/O PORTS (PPORT)
Table 6.7.3.2 P2 Port Group Function Assignment
P2SELy = 0 P2SELy = 1
Port
name
P20 P20 – – UPMUX *1 ADC12A ADIN07 – – – – – ✓
P21 P21 – – UPMUX *1 ADC12A ADIN06 – – – – – ✓
P22 P22 – – UPMUX *1 ADC12A ADIN05 – – – ✓ ✓ ✓
P23 P23 – – UPMUX *1 ADC12A ADIN04 – – – ✓ ✓ ✓
P24 P24 T16B Ch.1 EXCL10 UPMUX *1 ADC12A ADIN03 – – ✓ ✓ ✓ ✓
P25 P25 T16B Ch.1 EXCL11 UPMUX *1 ADC12A ADIN02 – – ✓ ✓ ✓ ✓
P26 P26 – – UPMUX *1 ADC12A ADIN01 – – ✓ ✓ ✓ ✓
P27 P27 – – UPMUX *1 ADC12A ADIN00 – – ✓ ✓ ✓ ✓
*1: Refer to the “Universal Port Multiplexer” chapter.
GPIO
P2yMUX = 0x0
(Function 0)
Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin
P2yMUX = 0x1
(Function 1)
P2yMUX = 0x2
(Function 2)
P2yMUX = 0x3
(Function 3)
M20/M23
24pin 32pin
6.7.4 P3 Port Group
The P3 port group supports the GPIO and interrupt functions.
Table 6.7.4.1 Control Registers for P3 Port Group
Register name Bit Bit name Initial Reset R/W Remarks
P3DAT
(P3 Port Data
Register)
15 P3OUT7 0 H0 R/W – – – –
14 P3OUT6 0 H0 R/W – – –
13 P3OUT5 0 H0 R/W – – –
12 P3OUT4 0 H0 R/W – – –
11 P3OUT3 0 H0 R/W – – –
10 P3OUT2 0 H0 R/W
9 P3OUT1 0 H0 R/W
8 P3OUT0 0 H0 R/W
7 P3IN7 0 H0 R – – – –
6 P3IN6 0 H0 R – – –
5 P3IN5 0 H0 R – – –
4 P3IN4 0 H0 R – – –
3 P3IN3 0 H0 R – – –
2 P3IN2 0 H0 R
1 P3IN1 0 H0 R
0 P3IN0 0 H0 R
P3IOEN
(P3 Port Enable
Register)
15 P3IEN7 0 H0 R/W – – – –
14 P3IEN6 0 H0 R/W – – –
13 P3IEN5 0 H0 R/W – – –
12 P3IEN4 0 H0 R/W – – –
11 P3IEN3 0 H0 R/W – – –
10 P3IEN2 0 H0 R/W
9 P3IEN1 0 H0 R/W
8 P3IEN0 0 H0 R/W
7 P3OEN7 0 H0 R/W – – – –
6 P3OEN6 0 H0 R/W – – –
5 P3OEN5 0 H0 R/W – – –
4 P3OEN4 0 H0 R/W – – –
3 P3OEN3 0 H0 R/W – – –
2 P3OEN2 0 H0 R/W
1 P3OEN1 0 H0 R/W
0 P3OEN0 0 H0 R/W
M20/M23
24pin 32pin
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
M21/
M24
M21/
M24
M22/
M25
M22/
M25
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
S1C17M20/M21/M22/M23/M24/M25 Seiko Epson Corporation
TECHNICAL MANUAL (Rev. 1.0)
6-19
Page 84
6 I/O PORTS (PPORT)
Register name Bit Bit name Initial Reset R/W Remarks
P3RCTL
(
P3 Port Pull-up/down
Control Register
15 P3PDPU7 0 H0 R/W – – – –
14 P3PDPU6 0 H0 R/W – – –
)
13 P3PDPU5 0 H0 R/W – – –
12 P3PDPU4 0 H0 R/W – – –
11 P3PDPU3 0 H0 R/W – – –
10 P3PDPU2 0 H0 R/W
9 P3PDPU1 0 H0 R/W
8 P3PDPU0 0 H0 R/W
7 P3REN7 0 H0 R/W – – – –
6 P3REN6 0 H0 R/W – – –
5 P3REN5 0 H0 R/W – – –
4 P3REN4 0 H0 R/W – – –
3 P3REN3 0 H0 R/W – – –
2 P3REN2 0 H0 R/W
1 P3REN1 0 H0 R/W
0 P3REN0 0 H0 R/W
P3INTF
(P3 Port Interrupt
Flag Register)
15–8 – 0x00 – R – – – – –
7 P3IF7 0 H0 R/W Cleared by writing 1.– – –
6 P3IF6 0 H0 R/W – – –
5 P3IF5 0 H0 R/W – – –
4 P3IF4 0 H0 R/W – – –
3 P3IF3 0 H0 R/W – – –
2 P3IF2 0 H0 R/W
1 P3IF1 0 H0 R/W
0 P3IF0 0 H0 R/W
P3INTCTL
(P3 Port Interrupt
Control Register)
15 P3EDGE7 0 H0 R/W – – – –
14 P3EDGE6 0 H0 R/W – – –
13 P3EDGE5 0 H0 R/W – – –
12 P3EDGE4 0 H0 R/W – – –
11 P3EDGE3 0 H0 R/W – – –
10 P3EDGE2 0 H0 R/W
9 P3EDGE1 0 H0 R/W
8 P3EDGE0 0 H0 R/W
7 P3IE7 0 H0 R/W – – – –
6 P3IE6 0 H0 R/W – – –
5 P3IE5 0 H0 R/W – – –
4 P3IE4 0 H0 R/W – – –
3 P3IE3 0 H0 R/W – – –
2 P3IE2 0 H0 R/W
1 P3IE1 0 H0 R/W
0 P3IE0 0 H0 R/W
P3CHATEN
(P3 Port Chattering
Filter Enable Register)
15–8 – 0x00 – R – – – – –
7 P3CHATEN7 0 H0 R/W – – – –
6 P3CHATEN6 0 H0 R/W – – –
5 P3CHATEN5 0 H0 R/W – – –
4 P3CHATEN4 0 H0 R/W – – –
3 P3CHATEN3 0 H0 R/W – – –
2 P3CHATEN2 0 H0 R/W
1 P3CHATEN1 0 H0 R/W
0 P3CHATEN0 0 H0 R/W
M20/M23
24pin 32pin
✓ ✓ ✓ ✓
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✓ ✓ ✓ ✓
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✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
M21/
M24
M22/
M25
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
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✓
✓
6-20
Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
Page 85
6 I/O PORTS (PPORT)
Register name Bit Bit name Initial Reset R/W Remarks
P3MODSEL
(P3 Port Mode Select
Register)
15–8 – 0x00 – R – – – – –
7 P3SEL7 0 H0 R/W – – – –
6 P3SEL6 0 H0 R/W – – –
M20/M23
24pin 32pin
5 P3SEL5 0 H0 R/W – – –
4 P3SEL4 0 H0 R/W – – –
3 P3SEL3 0 H0 R/W – – –
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
P3FNCSEL
(P3 Port Function
Select Register)
2 P3SEL2 0 H0 R/W
1 P3SEL1 0 H0 R/W
0 P3SEL0 0 H0 R/W
15–14 P37MUX[1:0] 0x0 H0 R/W – – – –
13–12 P36MUX[1:0] 0x0 H0 R/W – – –
11–10 P35MUX[1:0] 0x0 H0 R/W – – –
9–8 P34MUX[1:0] 0x0 H0 R/W – – –
7–6 P33MUX[1:0] 0x0 H0 R/W – – –
5–4 P32MUX[1:0] 0x0 H0 R/W
3–2 P31MUX[1:0] 0x0 H0 R/W
1–0 P30MUX[1:0] 0x0 H0 R/W
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
Table 6.7.4.2 P3 Port Group Function Assignment
P3SELy = 0 P3SELy = 1
Port
name
P30 P30 – – UPMUX *1 ADC12A VREFA0 – – ✓ ✓ ✓ ✓
P31 P31 CLG EXOSC UPMUX *1 – – – – ✓ ✓ ✓ ✓
P32 P32 RTCA RTC1S UPMUX *1 SVD3 EXSVD0 – – ✓ ✓ ✓ ✓
P33 P33 RFC Ch.0 SENB0 UPMUX *1 – – – – – – – ✓
P34 P34 RFC Ch.0 SENA0 UPMUX *1 – – – – – – – ✓
P35 P35 RFC Ch.0 REF0 UPMUX *1 – – – – – – – ✓
P36 P36 RFC Ch.0 RFIN0 UPMUX *1 – – – – – – – ✓
P37 P37 RFC Ch.1 SENB1 UPMUX *1 – – – – – – – ✓
*1: Refer to the “Universal Port Multiplexer” chapter.
GPIO
P3yMUX = 0x0
(Function 0)
Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin
P3yMUX = 0x1
(Function 1)
P3yMUX = 0x2
(Function 2)
P3yMUX = 0x3
(Function 3)
M20/M23
24pin 32pin
M21/
M24
M21/
M24
M22/
M25
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
M22/
M25
6.7.5 P4 Port Group
The P4 port group supports the GPIO and interrupt functions.
Table 6.7.5.1 Control Registers for P4 Port Group
Register name Bit Bit name Initial Reset R/W Remarks
P4DAT
(P4 Port Data
Register)
P4IOEN
(P4 Port Enable
Register)
S1C17M20/M21/M22/M23/M24/M25 Seiko Epson Corporation
TECHNICAL MANUAL (Rev. 1.0)
15–11 – 0x00 – R – – – – –
10 P4OUT2 0 H0 R/W
–
9 P4OUT1 0 H0 R/W – – –
8 P4OUT0 0 H0 R/W – – –
7–3 – 0x00 – R – – – – –
2 P4IN2 0 H0 R – – – –
1 P4IN1 0 H0 R – – –
0 P4IN0 0 H0 R – – –
15–11 – 0x00 – R – – – – –
10 P4IEN2 0 H0 R/W
–
9 P4IEN1 0 H0 R/W – – –
8 P4IEN0 0 H0 R/W – – –
7–3 – 0x00 – R – – – – –
2 P4OEN2 0 H0 R/W – – – –
1 P4OEN1 0 H0 R/W – – –
0 P4OEN0 0 H0 R/W – – –
M20/M23
24pin 32pin
– – –
– – –
M21/
M24
M22/
M25
✓
✓
✓
✓
✓
✓
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6-21
Page 86
6 I/O PORTS (PPORT)
Register name Bit Bit name Initial Reset R/W Remarks
P4RCTL
(
P4 Port Pull-up/down
Control Register
15–11 – 0x00 – R – – – – –
10 P4PDPU2 0 H0 R/W
)
9 P4PDPU1 0 H0 R/W – – –
–
8 P4PDPU0 0 H0 R/W – – –
7–3 – 0x00 – R – – – – –
2 P4REN2 0 H0 R/W – – – –
1 P4REN1 0 H0 R/W – – –
0 P4REN0 0 H0 R/W – – –
P4INTF
(P4 Port Interrupt
Flag Register)
15–8 – 0x00 – R – – – – –
7–3 – 0x00 – R – – – –
2 P4IF2 0 H0 R/W Cleared by writing 1.– – –
1 P4IF1 0 H0 R/W – – –
0 P4IF0 0 H0 R/W – – –
P4INTCTL
(P4 Port Interrupt
Control Register)
15–11 – 0x00 – R – – – – –
10 P4EDGE2 0 H0 R/W
–
9 P4EDGE1 0 H0 R/W – – –
8 P4EDGE0 0 H0 R/W – – –
7–3 – 0x00 – R – – – – –
2 P4IE2 0 H0 R/W – – – –
1 P4IE1 0 H0 R/W – – –
0 P4IE0 0 H0 R/W – – –
P4CHATEN
(P4 Port Chattering
Filter Enable Register)
15–8 – 0x00 – R – – – – –
7–3 – 0x00 – R – – – –
2 P4CHATEN2 0 H0 R/W – – – –
1 P4CHATEN1 0 H0 R/W – – –
0 P4CHATEN0 0 H0 R/W – – –
P4MODSEL
(P4 Port Mode Select
Register)
15–8 – 0x00 – R – – – – –
7–3 – 0x00 – R – – – –
2 P4SEL2 0 H0 R/W – – – –
1 P4SEL1 0 H0 R/W – – –
0 P4SEL0 0 H0 R/W – – –
P4FNCSEL
(P4 Port Function
Select Register)
15–8 – 0x00 – R – – – – –
7–6 – 0x0 – R – – – –
5–4 P42MUX[1:0] 0x0 H0 R/W – – – –
3–2 P41MUX[1:0] 0x0 H0 R/W – – –
1–0 P40MUX[1:0] 0x0 H0 R/W – – –
M20/M23
24pin 32pin
– – –
– – –
M21/
M24
M22/
M25
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
Table 6.7.5.2 P4 Port Group Function Assignment
P4SELy = 0 P4SELy = 1
Port
name
P40 P40 RFC Ch.1 SENA1 – – – – – – – – – ✓
P41 P41 RFC Ch.1 REF1 – – – – – – – – – ✓
P42 P42 RFC Ch.1 RFIN1 – – – – – – – – – ✓
6-22
Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
GPIO
P4yMUX = 0x0
(Function 0)
Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin
P4yMUX = 0x1
(Function 1)
P4yMUX = 0x2
(Function 2)
P4yMUX = 0x3
(Function 3)
M20/M23
24pin 32pin
M21/
M24
M22/
M25
Page 87
6 I/O PORTS (PPORT)
6.7.6 Pd Port Group
The Pd0–Pd2 ports are configured as a debugging function port at initialization. The Pd port group supports the
GPIO functions. The GPIO function of the Pd2 port supports output only, therefore, the pull-up/down function cannot be used.
Table 6.7.6.1 Control Registers for Pd Port Group
M21/
Register name Bit Bit name Initial Reset R/W Remarks
PDDAT
(Pd Port Data
Register)
15–13 – 0x0 – R – – – – –
12 PDOUT4 0 H0 R/W – –
11 PDOUT3 0 H0 R/W –
10 PDOUT2 0 H0 R/W
9 PDOUT1 0 H0 R/W
8 PDOUT0 0 H0 R/W
7–5 – 0 – R – – – – –
4 PDIN4 X H0 R – –
3 PDIN3 X H0 R –
2 – 0 – R – – – –
1 PDIN1 X H0 R
0 PDIN0 X H0 R
PDIOEN
(Pd Port Enable
Register)
15–13 – 0x0 – R – – – – –
12 PDIEN4 0 H0 R/W – –
11 PDIEN3 0 H0 R/W –
10 (reserved) 0 H0 R/W
9 PDIEN1 0 H0 R/W
8 PDIEN0 0 H0 R/W
7–5 – 0 – R – – – – –
4 PDOEN4 0 H0 R/W – –
3 PDOEN3 0 H0 R/W –
2 PDOEN2 0 H0 R/W
1 PDOEN1 0 H0 R/W
0 PDOEN0 0 H0 R/W
PDRCTL
(
Pd Port Pull-up/down
Control Register
15–13 – 0x0 – R – – – – –
12 PDPDPU4 0 H0 R/W – –
)
11 PDPDPU3 0 H0 R/W –
10 (reserved) 0 H0 R/W
9 PDPDPU1 0 H0 R/W
8 PDPDPU0 0 H0 R/W
7–5 – 0 – R – – – – –
4 PDREN4 0 H0 R/W – –
3 PDREN3 0 H0 R/W –
2 (reserved) 0 H0 R/W
1 PDREN1 0 H0 R/W
0 PDREN0 0 H0 R/W
PDINTF
15–0 – 0x0000 – R – – – – –
PDINTCTL
PDCHATEN
PDMODSEL
(Pd Port Mode Select
Register)
15–8 – 0x00 – R – – – – –
7–5 – 0 – R – – – – –
4 PDSEL4 0 H0 R/W – –
3 PDSEL3 0 H0 R/W –
2 PDSEL2 1 H0 R/W
1 PDSEL1 1 H0 R/W
0 PDSEL0 1 H0 R/W
M20/M23
24pin 32pin
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M24
M22/
M25
S1C17M20/M21/M22/M23/M24/M25 Seiko Epson Corporation
TECHNICAL MANUAL (Rev. 1.0)
6-23
Page 88
6 I/O PORTS (PPORT)
Register name Bit Bit name Initial Reset R/W Remarks
PDFNCSEL
(Pd Port Function
Select Register)
15–10 – 0x00 – R – – – – –
9–8 PD4MUX[1:0] 0x0 H0 R/W – –
7–6 PD3MUX[1:0] 0x0 H0 R/W –
5–4 PD2MUX[1:0] 0x0 H0 R/W
3–2 PD1MUX[1:0] 0x0 H0 R/W
1–0 PD0MUX[1:0] 0x0 H0 R/W
M20/M23
24pin 32pin
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
Table 6.7.6.2 Pd Port Group Function Assignment
PDSELy = 0 PDSELy = 1
Port
name
Pd0 PD0 DBG DST2 – – – – – – ✓ ✓ ✓ ✓
Pd1 PD1 DBG DSIO – – – – – – ✓ ✓ ✓ ✓
Pd2 PD2 DBG DCLK – – – – – – ✓ ✓ ✓ ✓
Pd3 PD3 – – – – CLG OSC3 – –
Pd4 PD4 – – – – CLG OSC4 – –
GPIO
PDyMUX = 0x0
(Function 0)
Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin
PDyMUX = 0x1
(Function 1)
PDyMUX = 0x2
(Function 2)
PDyMUX = 0x3
(Function 3)
M20/M23
24pin 32pin
✓ ✓ ✓
–
✓ ✓ ✓
–
6.7.7 Common Registers between Port Groups
Table 6.7.7.1 Control Registers for Common Use with Port Groups
Register name Bit Bit name Initial Reset R/W Remarks
PCLK
(P Port Clock Control
Register)
15–9 – 0x00 – R – – – – –
8 DBRUN 0 H0 R/WP –
7–4 CLKDIV[3:0] 0x0 H0 R/WP
3–2 KRSTCFG[1:0] 0x0 H0 R/WP
1–0 CLKSRC[1:0] 0x0 H0 R/WP
PINTFGRP
(P Port Interrupt Flag
Group Register)
15–8 – 0x00 – R – – – – –
7–5 – 0x0 – R – – – –
4 P4INT 0 H0 R – – – –
3 P3INT 0 H0 R
2 P2INT 0 H0 R
1 P1INT 0 H0 R
0 P0INT 0 H0 R
M20/M23
24pin 32pin
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
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✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
M21/
M24
M21/
M24
M21/
M24
M22/
M25
M22/
M25
M22/
M25
✓
6-24
Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
Page 89
7 UNIVERSAL PORT MULTIPLEXER (UPMUX)
Internal data bus
7 Universal Port Multiplexer (UPMUX)
7.1 Overview
UPMUX is a multiplexer that allows software to assign the desired peripheral I/O function to an I/O port. The main
features are outlined below.
• Allows programmable assignment of the synchronous serial interface, I
eral I/O functions to the P0, P1, P2, and P3 port groups.
• The peripheral I/O function assigned via
UPMUX is enabled by setting the PxFNCSEL.PxyMUX[1:0] bits to 0x1.
Note: ‘x’, which is used in the port names Pxy, register names, and bit names, refers to a port group (x
= 0, 1, 2, 3) and ‘y’ refers to a port number (y = 0, 1, 2, ··· , 7).
Figure 7.1.1 shows the configuration of UPMUX.
UPMUX
PxyPPFNC[2:0]
PxyPERICH[1:0]
PxyPERISEL[2:0]
Input data
selector
2
C,
UART, and 16-bit PWM timer
Peripheral circuit
periph-
Output data
selector
Data, I/O control
Function 1 selection
Figure 7.1.1 UPMUX Configuration
I/O port
Pxy
7.2 Peripheral Circuit I/O Function Assignment
An I/O function of a peripheral circuit supported may be assigned to peripheral I/O function 1 of an I/O port listed
above. The following shows the procedure to assign a peripheral I/O function and enable it in the I/O port:
1. Configure the PxIOEN register of the I/O port.
- Set the PxIOEN.PxIENy bit to 0. (Disable input)
- Set the PxIOEN.PxOENy bit to 0. (Disable output)
2. Set the PxMODSEL.PxSELy bit of the I/O port to 0. (Disable peripheral I/O function)
3. Set the following PxUPMUXn register bits (n = 0 to 3).
- PxUPMUXn.PxyPERISEL[2:0] bits (Select peripheral circuit)
- PxUPMUXn.PxyPERICH[1:0] bits (Select peripheral circuit channel)
- PxUPMUXn.PxyPPFNC[2:0] bits (Select function to assign)
4. Initialize the peripheral circuit.
5. Set the PxFNCSEL.PxyMUX[1:0] bits of the I/O port to 0x1. (Select peripheral I/O function 1)
6. Set the PxMODSEL.PxSELy bit of the I/O port to 1. (Enable peripheral I/O function)
S1C17M20/M21/M22/M23/M24/M25 Seiko Epson Corporation
TECHNICAL MANUAL (Rev. 1.0)
7-1
Page 90
7 UNIVERSAL PORT MULTIPLEXER (UPMUX)
7.3 Control Registers
Pxy–xz Universal Port Multiplexer Setting Register
Register name Bit Bit name Initial Reset R/W Remarks
PxUPMUXn 15–13 PxzPPFNC[2:0] 0x0 H0 R/W –
12–11 PxzPERICH[1:0] 0x0 H0 R/W
10–8 PxzPERISEL[2:0] 0x0 H0 R/W
7–5 PxyPPFNC[2:0] 0x0 H0 R/W
4–3 PxyPERICH[1:0] 0x0 H0 R/W
2–0 PxyPERISEL[2:0] 0x0 H0 R/W
*1: ‘x’ in the register name refers to a port group number and ‘n’ refers to a register number (0–3).
*2: ‘x’ in the bit name refers to a port group number, ‘y’ refers to an even port number (0, 2, 4, 6), and ‘z’ refers to an
odd port number (z = y + 1).
Bits 15–13 PxzPPFNC[2:0]
Bits 7–5 PxyPPFNC[2:0]
These bits specify the peripheral I/O function to be assigned to the port. (See Table 7.3.1.)
Bits 12–11 PxzPERICH[1:0]
Bits 4–3 PxyPERICH[1:0]
These bits specify a peripheral circuit channel number. (See Table 7.3.1.)
Bits 10–8 PxzPERISEL[2:0]
Bits 2–0 PxyPERISEL[2:0]
These bits specify a peripheral circuit. (See Table 7.3.1.)
Table 7.3.1 Peripheral I/O Function Selections
PxUPMUXn.
PxyPPFNC[2:0]
bits
(Peripheral I/O
function)
0x0 None * None * None * None * None * None * None * None *
0x1
0x2 SDAn SDOn USOUTn
0x3
0x4 #SPISSn
0x5
0x7
0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
None * I2C SPIA UART3 T16B Reserved Reserved Reserved
– 0x0 0x0, 0x1 0x0, 0x1 0x0, 0x1 – – –
– Ch.0 Ch.0, 1 Ch.0, 1 Ch.0, 1 – – –
SCLn SDIn USINn
Reserved
Reserved
* “None” means no assignment. Selecting this will put the Pxy pin into Hi-Z status when peripheral I/O function 1 is
selected and enabled in the I/O port.
PxUPMUXn.PxyPERISEL[2:0] bits (Peripheral circuit)
PxUPMUXn.PxyPERICH[1:0] bits (Peripheral circuit channel)
TOUTn0/
CAPn0
TOUTn1/
SPICLKn
Reserved Reserved
Reserved0x6
CAPn1
Reserved Reserved Reserved
Note: Do not assign a peripheral input function to two or more I/O ports. Although the I/O ports output
the same waveforms when an output function is assigned to two or more I/O port, a skew occurs due to the internal delay.
7-2
Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
Page 91
8 WATCHDOG TIMER (WDT2)
WDT2
request
8 Watchdog Timer (WDT2)
8.1 Overview
WDT2 restarts the system if a problem occurs, such as when the program cannot be executed normally.
The features of WDT2 are listed below.
• Includes a 10-bit up counter to count NMI/reset generation cycle.
• A counter clock source and clock division ratio are selectable.
• Can generate a reset or NMI in a cycle given via software.
• Can generate a reset at the next NMI generation cycle after an NMI is generated.
Figure 8.1.1 shows the configuration of WDT2.
Clock generator
Internal data bus
MOD[1:0]
WDTRUN[3:0]
WDTCNTRST
CLK_WDT2
CLKSRC[1:0]
CLKDIV[1:0] CMP[9:0]
DBRUN
Mode setting circuit
10-bit counter
Figure 8.1.1 WDT2 Configuration
Comparator
NMI
STATNMI
Reset
8.2 Clock Settings
8.2.1 WDT2 Operating Clock
When using WDT2, the WDT2 operating clock CLK_WDT2 must be supplied to WDT2 from the clock generator.
The CLK_WDT2 supply should be controlled as in the procedure shown below.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
2. Enable the clock source in the clock generator if it is stopped (refer to “Clock Generator” in the “Power Supply,
Reset, and Clocks” chapter).
3. Set the following WDTCLK register bits:
WDTCLK.CLKSRC[1:0] bits (Clock source selection)
WDTCLK.CLKDIV[1:0] bits (Clock division ratio selection = Clock frequency setting)
4. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
8.2.2 Clock Supply in DEBUG Mode
The CLK_WDT2 supply during DEBUG mode should be controlled using the WDTCLK.DBRUN bit.
The CLK_WDT2 supply to WDT2 is suspended when the CPU enters DEBUG mode if the WDTCLK.DBRUN
bit = 0. After the CPU returns to normal mode, the CLK_WDT2 supply resumes. Although WDT2 stops operating
when the CLK_WDT2 supply is suspended, the register retains the status before DEBUG mode was entered.
If the WDTCLK.DBRUN bit = 1, the CLK_WDT2 supply is not suspended and WDT2 will keep operating in DEBUG mode.
S1C17M20/M21/M22/M23/M24/M25 Seiko Epson Corporation
TECHNICAL MANUAL (Rev. 1.0)
8-1
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8 WATCHDOG TIMER (WDT2)
8.3 Operations
8.3.1 WDT2 Control
Activating WDT2
WDT2 should be initialized and started up with the procedure listed below.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
2. Configure the WDT2 operating clock.
3. Set the WDTCTL.MOD[1:0] bits. (Select WDT2 operating mode)
4. Set the WDTCMP.CMP[9:0] bits. (Set NMI/reset generation cycle)
5. Write 1 to the WDTCTL.WDTCNTRST bit. (Reset WDT2 counter)
6. Write a value other than 0xa to the WDTCTL.WDTRUN[3:0] bits. (Start up WDT2)
7. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
NMI/reset generation cycle
Use the following equation to calculate the WDT2 NMI/reset generation cycle.
CMP + 1
tWDT = —————— (Eq. 8.1)
CLK_WDT2
Where
tWDT: NMI/reset generation cycle [second]
CLK_WDT2: WDT2 operating clock frequency [Hz]
CMP: Setting value of the WDTCMP.CMP[9:0] bits
Example)
tWDT = 2.5 seconds when CLK_WDT2 = 256 Hz and the WDTCMP.CMP[9:0] bits = 639
Resetting WDT2 counter
To prevent an unexpected NMI/reset to be generated by WDT2, its embedded counter must be reset periodically
via software while WDT2 is running.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
2. Write 1 to the WDTCTL.WDTCNTRST bit. (Reset WDT2 counter)
3. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
A location should be provided for periodically processing this routine. Process this routine within the t
cycle. After resetting, WDT2 starts counting with a new NMI/reset generation cycle.
WDT
Occurrence of counter compare match
If WDT2 is not reset within the tWDT cycle for any reason and the counter reaches the setting value of the
WDTCMP.CMP[9:0] bits, a compare match occurs to cause WDT2 to issue an NMI or reset according to the
setting of the WDTCTL.MOD[1:0] bits.
If an NMI is issued, the WDTCTL.STATNMI bit is set to 1. This bit can be cleared to 0 by writing 1 to the
WDTCTL.WDTCNTRST bit. Be sure to clear the WDTCTL.STATNMI bit in the NMI handler routine,
If a compare match occurs, the counter is automatically reset to 0 and it continues counting.
Deactivating WDT2
WDT2 should be stopped with the procedure listed below.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
2. Write 0xa to the WDTCTL.WDTRUN[3:0] bits. (Stop WDT2)
3. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
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8 WATCHDOG TIMER (WDT2)
8.3.2 Operations in HALT and SLEEP Modes
During HALT mode
WDT2
operates in HALT mode. HALT mode is therefore cleared by an NMI or reset if it continues for more than the
NMI/reset generation cycle and the CPU executes the interrupt handler. To disable
by writing 0xa to the
WDTCTL.WDTRUN[3:0] bits
before executing the halt instruction. Reset
WDT2
in HALT mode, stop
WDT2
WDT2
before re-
suming operations after HALT mode is cleared.
During SLEEP mode
WDT2 operates in SLEEP mode if the selected clock source is running. SLEEP mode is cleared by an NMI or reset if
it continues for more than the NMI/reset generation cycle and the CPU executes the interrupt handler. Therefore, stop
WDT2
by setting the
If the clock source stops in SLEEP mode, WDT2 stops. To prevent generation of an unnecessary NMI or reset after
clearing SLEEP mode, reset
ing the
WDTCTL.WDTRUN[3:0] bits
WDTCTL.WDTRUN[3:0] bits
WDT2
before executing the slp instruction.
.
before executing the slp instruction.
WDT2
should also be stopped as required us-
8.4 Control Registers
WDT2 Clock Control Register
Register name Bit Bit name Initial Reset R/W Remarks
WDTCLK 15–9 – 0x00 – R –
8 DBRUN 0 H0 R/WP
7–6 – 0x0 – R
5–4 CLKDIV[1:0] 0x0 H0 R/WP
3–2 – 0x0 – R
1–0 CLKSRC[1:0] 0x0 H0 R/WP
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the WDT2 operating clock is supplied in DEBUG mode or not.
1 (R/WP): Clock supplied in DEBUG mode
0 (R/WP): No clock supplied in DEBUG mode
Bits 7–6 Reserved
Bits 5–4 CLKDIV[1:0]
These bits select the division ratio of the WDT2 operating clock (counter clock). The clock frequency
should be set to around 256 Hz.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of WDT2.
Table 8.4.1 Clock Source and Division Ratio Settings
WDTCLK.
CLKDIV[1:0] bits
0x3 1/65,536 1/128 1/65,536 1/1
0x2 1/32,768 1/32,768
0x1 1/16,384 1/16,384
0x0 1/8,192 1/8,192
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
0x0 0x1 0x2 0x3
IOSC OSC1 OSC3 EXOSC
WDTCLK.CLKSRC[1:0] bits
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8 WATCHDOG TIMER (WDT2)
WDT2 Control Register
Register name Bit Bit name Initial Reset R/W Remarks
WDTCTL 15–11 – 0x00 – R –
10–9 MOD[1:0] 0x0 H0 R/WP
8 STATNMI 0 H0 R
7–5 – 0x0 – R
4 WDTCNTRST 0 H0 WP Always read as 0.
3–0 WDTRUN[3:0] 0xa H0 R/WP –
Bits 15–11 Reserved
Bits 10–9 MOD[1:0]
These bits set the WDT2 operating mode.
Table 8.4.2 Operating Mode Setting
WDTCTL.
MOD[1:0] bits
0x3 Reserved –
0x2 RESET after NMI mode If the WDTCTL.STATNMI bit is not cleared to 0 after an NMI
0x1 NMI mode WDT2 issues an NMI when a counter compare match occurs.
0x0 RESET mode WDT2 issues a reset when a counter compare match occurs.
Bit 8 STATNMI
This bit indicates that a counter compare match and NMI have occurred.
1 (R): NMI (counter compare match) occurred
0 (R): NMI not occurred
Operating mode Description
has occurred due to a counter compare match, WDT2 issues
a reset when the next compare match occurs.
When the NMI generation function of WDT2 is used, read this bit in the NMI handler routine to con-
firm that WDT2 was the source of the NMI.
The WDTCTL.STATNMI bit set to 1 is cleared to 0 by writing 1 to the WDTCTL.WDTCNTRST bit.
Bits 7–5 Reserved
Bit 4 WDTCNTRST
This bit resets the 10-bit counter and the WDTCTL.STATNMI bit.
1 (WP): Reset
0 (WP): Ignored
0 (R): Always 0 when being read
Bits 3–0 WDTRUN[3:0]
These bits control WDT2 to run and stop.
0xa (WP): Stop
Values other than 0xa (WP): Run
0xa (R): Idle
0x0 (R): Running
Always 0x0 is read if a value other than 0xa is written.
Since an NMI or reset may be generated immediately after running depending on the counter value,
WDT2 should also be reset concurrently when running WDT2.
WDT2 Counter Compare Match Register
Register name Bit Bit name Initial Reset R/W Remarks
WDTCMP 15–10 – 0x00 – R –
9–0 CMP[9:0] 0x3ff H0 R/WP
Bits 15–10 Reserved
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8 WATCHDOG TIMER (WDT2)
Bits 9–0 CMP[9:0]
These bits set the NMI/reset generation cycle.
The value set in this register is compared with the 10-bit counter value while WDT2 is running, and
an NMI or reset is generated when they are matched.
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9 REAL-TIME CLOCK (RTCA)
RTCA
TC1S
9 Real-Time Clock (RTCA)
9.1 Overview
RTCA is a real-time clock with a perpetual calendar function. The main features of RTCA are outlined below.
• Includes a BCD real-time clock counter to implement a time-of-day clock (second, minute, and hour) and calendar (day, day of the week, month, and year with leap year supported).
• Provides a hold function for reading correct counter values by suspending the real-time clock counter operation.
• 24-hour or 12-hour mode is selectable.
• Capable of controlling the starting and stopping of the time-of-day clock.
• Provides a 30-second correction function to adjust time using a time signal.
• Includes a 1 Hz counter to count 128 to 1 Hz.
• Includes a BCD stopwatch counter with 1/100-second counting supported.
• Provides a theoretical regulation function to correct clock error due to frequency tolerance with no external parts
required.
Figure 9.1.1 shows the configuration of RTCA.
Clock generator
fOSC1
OSC1
oscillator
Interrupt controller
1/128
Internal data bus
RTCTRM[6:0]
RTCTRMBSY
RTCHLD
RTCRST
RTCRUN
RTCBSY
SWRST
SWRUN
SW1IE
SW10IE
SW100IE
ALARMIE
1DAYIE
1HURIE
1MINIE
1SECIE
1_2SECIE
1_4SECIE
1_8SECIE
1_32SECIE
RTC
count
control
circuit
Stopwatch
count
control
circuit
Interrupt
control
circuit
RTC
RTC
RTC
128HZ
64HZ
128
64
Hz
Hz
BCD
100[3:0]
1/100
s
Stopwatch counter
SW1IF
SW10IF
SW100IF
ALARMIF
1DAYIF
1HURIF
1MINIF
1SECIF
1_2SECIF
1_4SECIF
1_8SECIF
1_32SECIF
Stopwatch counter interrupt
1 Hz counter interrupt
Alarm interrupt
Real-time clock counter interrupt
32HZ
BCD
10[3:0]
1/10
s
32
Hz
RTC
16HZ
1 Hz counter
16
Hz
RTC
8HZ
8
Hz
RTCAPA
RTCHHA[1:0]
/RTCHLA[3:0]
RTCMIHA[2:0]
/RTCMILA[3:0]
RTCSHA[2:0]
/RTCSLA[3:0]
RTC
4HZ
RTC
RTC
2HZ
1HZ
4
2
Hz
1
Hz
RTC24H
RTCADJ
Comparator
Hz
1-second
signal
Real-time
clock
counter
Day of
week
Year
Month
Day
A.M./
P.M.
Hour
Minute
Second
RTCWK[2:0]
RTCYH[3:0]
/RTCYL[3:0]
RTCMOH
/RTCMOL[3:0]
RTCDH[1:0]
/RTCDL[3:0]
RTCHH[1:0]
/RTCHL[3:0]
RTCMIH[2:0]
/RTCMIL[3:0]
RTCSH[2:0]
/RTCSL[3:0]
RTCAP
R
Figure 9.1.1 RTCA Configuration
9.2 Output Pin and External Connection
9.2.1 Output Pin
Table 9.2.1.1 shows the RTCA pin.
Table 9.2.1.1 RTCA Pin
Pin name I/O* Initial status* Function
RTC1S O O (L) 1-second signal monitor output pin
* Indicates the status when the pin is configured for RTCA.
If the port is shared with the RTCA output function and other functions, the RTCA function must be assigned to the
port. For more information, refer to the “I/O Ports” chapter.
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9 REAL-TIME CLOCK (RTCA)
R
Theoretical regulation execution cycle time n [s]
∗ ∆
Theoretical regulation
9.3 Clock Settings
9.3.1 RTCA Operating Clock
RTCA uses CLK_RTCA, which is generated by the clock generator from OSC1 as the clock source, as its operating clock. RTCA is operable when OSC1 is enabled.
To continue the RTCA operation during SLEEP mode with OSC1 being activated, the CLGOSC.OSC1SLPC bit
must be set to 0.
9.3.2 Theoretical Regulation Function
The time-of-day clock loses accuracy if the OSC1 frequency fOSC1 has a frequency tolerance from 32.768 kHz. To
correct this error without changing any external part, RTCA provides a theoretical regulation function. Follow the
procedure below to perform theoretical regulation.
1. Measure the frequency tolerance “m [ppm]” of f
2. Determine the theoretical regulation execution cycle time “n seconds.”
3. Determine the value to be written to the RTCCTL.RTCTRM[6:0] bits from the results in Steps 1 and 2.
4. Write the value determined in Step 3 to the RTCCTL.RTCTRM[6:0] bits periodically in n-second cycles using
an RTCA alarm or second interrupt.
5. Monitor the RTC1S signal to check that every n-second cycle has no error included.
The correction value for theoretical regulation can be specified within the range from -64 to +63 and it should be
written to the RTCCTL.RTCTRM[6:0] bits as a two’s-complement number. Use Eq. 9.1 to calculate the correction
value.
m
RTCTRM[6:0] = —— × 256 × n
10
6
(However, RTCTRM[6:0] is an integer after rounding off to -64 to +63.) (Eq. 9.1)
Where
n: Theoretical regulation execution cycle time [second] (time interval to write the correct value to the RTCCTL.
RTCTRM[6:0] bits periodically via software)
m: OSC1 frequency tolerance [ppm]
Figure 9.3.2.1 shows the RTC1S signal waveform.
OSC1.
32,768/fOSC1 [s]
RTC1S
TCCTL.RTCTRMBSY
Writing to the RTCCTL.RTCTRM[6:0] bits
T = correction time set in the RTCCTL.RTCTRM[6:0] bits
Figure 9.3.2.1 RTC1S Signal Waveform
32,768/fOSC1 ± ∆T [s]
completion interrupt
Table 9.3.2.1 lists the frequency tolerance correction rates when the theoretical regulation execution cycle time n is
4,096 seconds as an example.
Table 9.3.2.1 Correction Rates when Theoretical Regulation Execution Cycle Time n = 4,096 Seconds
RTCCTL.RTCTRM[6:0]
bits (two’s-complement)
0x00 0 0.0 0x40 -64 -61.0
0x01 1 1.0 0x41 -63 -60.1
0x02 2 1.9 0x42 -62 -59.1
0x03 3 2.9 0x43 -61 -58.2
· · · · · · · · · · · · · · · · · ·
0x3e 62 59.1 0x7e -2 -1.9
0x3f 63 60.1 0x7f -1 -1.0
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Correction
value (decimal)
Correction rate
[ppm]
Minimum resolution: 1 ppm, Correction rate range: -61.0 to 60.1 ppm
RTCCTL.RTCTRM[6:0]
bits (two’s-complement)
Correction
value (decimal)
Correction rate
[ppm]
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9 REAL-TIME CLOCK (RTCA)
Notes: • The theoretical regulation affects only the real-time clock counter and 1 Hz counter. It does
not affect the stopwatch counter.
• After a value is written to the RTCCTL.RTCTRM[6:0] bits, the theoretical regulation correction
takes effect on the 1 Hz counter value at the same timing as when the 1 Hz counter changes
to 0x7f. Also an interrupt occurs depending on the counter value at this time.
9.4 Operations
9.4.1 RTCA Control
Follow the sequences shown below to set time to RTCA, to read the current time and to set alarm.
Time setting
1. Set RTCA to 12H or 24H mode using the RTCCTL.RTC24H bit.
2. Write 1 to the RTCCTL.RTCRUN bit to enable for the real-time clock counter to start counting up.
3. Check to see if the RTCCTL.RTCBSY bit = 0 that indicates the counter is ready to rewrite. If the RTCCTL.
RTCBSY bit = 1, wait until it is set to 0.
4. Write the current date and time in BCD code to the control bits listed below.
RTCSEC.RTCSH[2:0]/RTCSL[3:0] bits (second)
RTCHUR.RTCMIH[2:0]/RTCMIL[3:0] bits (minute)
RTCHUR.RTCHH[1:0]/RTCHL[3:0] bits (hour)
RTCHUR.RTCAP bit (AM/PM) (effective when RTCCTL.RTC24H bit = 0)
RTCMON.RTCDH[1:0]/RTCDL[3:0] bits (day)
RTCMON.RTCMOH/RTCMOL[3:0] bits (month)
RTCYAR.RTCYH[3:0]/RTCYL[3:0] bits (year)
RTCYAR.RTCWK[2:0] bits (day of the week)
5 Write 1 to the RTCCTL.RTCADJ bit (execute 30-second correction) using a time signal to adjust the time.
(For more information on the 30-second correction, refer to “Real-Time Clock Counter Operations.”)
6. Write 1 to the real-time clock counter interrupt flags in the RTCINTF register to clear them.
7. Write 1 to the interrupt enable bits in the RTCINTE register to enable real-time clock counter interrupts.
Time read
1. Check to see if the RTCCTL.RTCBSY bit = 0. If the RTCCTL.RTCBSY bit = 1, wait until it is set to 0.
2. Write 1 to the RTCCTL.RTCHLD bit to suspend count-up operation of the real-time clock counter.
3. Read the date and time from the control bits listed in “Time setting, Step 4” above.
4. Write 0 to the RTCCTL.RTCHLD bit to resume count-up operation of the real-time clock counter. If a
second count-up timing has occurred in the count hold state, the hardware corrects the second counter for
+1 second (for more information on the +1 second correction, refer to “Real-Time Clock Counter Operations”).
Alarm setting
1. Write 0 to the RTCINTE.ALARMIE bit to 0 to disable alarm interrupts.
2. Write the alarm time in BCD code to the control bits listed below (a time within 24 hours from the current
time can be specified).
RTCALM1.RTCSHA[2:0]/RTCSLA[3:0] bits (second)
RTCALM2.RTCMIHA[2:0]/RTCMILA[3:0] bits (minute)
RTCALM2.RTCHHA[1:0]/RTCHLA[3:0] bits (hour)
RTCALM2.RTCAPA bit (AM/PM) (effective when RTCCTL.RTC24H bit = 0)
3. Write 1 to the RTCINTF.ALARMIF bit to clear the alarm interrupt flag.
4. Write 1 to the RTCINTE.ALARMIE bit to enable alarm interrupts.
When the real-time clock counter reaches the alarm time set in Step 2, an alarm interrupt occurs.
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9 REAL-TIME CLOCK (RTCA)
9.4.2 Real-Time Clock Counter Operations
The real-time clock counter consists of second, minute, hour, AM/PM, day, month, year, and day of the week counters and it performs counting up using the RTC1S signal. It has the following functions as well.
Recognizing leap years
The leap year recognizing algorithm used in RTCA is effective only for Christian Era years. Years within 0 to
99 that can be divided by four without a remainder are recognized as leap years. If the year counter = 0x00,
RTCA assumes it as a common year. If a leap year is recognized, the count range of the day counter changes
when the month counter is set to February.
Corrective operation when a value out of the effective range is set
When a value out of the effective range is set to the year, day of the week, or hour (in 24H mode) counter, the
counter will be cleared to 0 at the next count-up timing. When a such value is set to the month, day, or hour (in
12H mode) counter, the counter will be set to 1 at the next count-up timing.
30-second correction
This function is provided to set the time-of-day clock by the time signal. Writing 1 to the RTCCTL.RTCADJ
bit adds 1 to the minute counter if the second counter represents 30 to 59 seconds, or clears the second counter
with the minute counter left unchanged if the second counter represents 0 to 29 seconds.
+1 second correction
If a second count-up timing occurred while the RTCCTL.RTCHLD bit = 1 (count hold state), the real-time
clock counter counts up by +1 second (performs +1 second correction) after the counting has resumed by writing 0 to the RTCCTL.RTCHLD bit.
Note: If two or more second count-up timings occurred while the RTCCTL.RTCHLD bit = 1, the coun-
ter is always corrected for +1 second only.
9.4.3 Stopwatch Control
Follow the sequences shown below to start counting of the stopwatch and to read the counter.
Count start
1. Write 1 to the RTCSWCTL.SWRST bit to reset the stopwatch counter.
2. Write 1 to the stopwatch interrupt flags in the RTCINTF register to clear them.
3. Write 1 to the interrupt enable bits in the RTCINTE register to enable stopwatch interrupts.
4. Write 1 to the RTCSWCTL.SWRUN bit to start stopwatch count up operation.
Counter read
1. Read the count value from the RTCSWCTL.BCD10[3:0] and BCD100[3:0] bits.
2. Read again.
i. If the two read values are the same, assume that the count values are read correctly.
ii.
If different values are read, perform reading once more and compare the read value with the previous one.
9.4.4 Stopwatch Count-up Pattern
The stopwatch consists of 1/100-second and 1/10-second counters and these counters perform counting up in increments of approximate 1/100 and 1/10 seconds with the count-up patterns shown in Figure 9.4.4.1.
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9 REAL-TIME CLOCK (RTCA)
26/256 × 6 + 25/256 × 4 = 1 second
1/100-second
counter
26/256 seconds25/256 seconds
1/10-second
counter
1 Hz counter
1/32-second interrupt
0
1
2
3
4
5
6
7
3/256
2/256
3/256
2/256
3/256
2/256
s
s
s
s
26/256 s026/256 s125/256 s225/256 s326/256 s426/256 s525/256 s625/256 s726/256 s826/256 s
3/256
s
s
s
2/256
s
8
3/256
s
9
2/256
s
0
3/256
s
1
3/256
2
3
4
5
6
7
3/256
2/256
3/256
2/256
s
s
s
3/256
s
s
s
2/256
s
8
3/256
s
Figure 9.4.4.1 Stopwatch Count-Up Patterns
9.5 Interrupts
RTCA has a function to generate the interrupts shown in Table 9.5.1.
Table 9.5.1 RTCA Interrupt Function
Interrupt Interrupt flag Set condition Clear condition
Alarm RTCINTF.ALARMIF Matching between the RTCALM1–2 register contents
and the real-time clock counter contents
1-day RTCINTF.1DAYIF Day counter count up Writing 1
1-hour RTCINTF.1HURIF Hour counter count up Writing 1
1-minute RTCINTF.1MINIF Minute counter count up Writing 1
1-second RTCINTF.1SECIF Second counter count up Writing 1
1/2-second RTCINTF.1_2SECIF See Figure 9.5.1. Writing 1
1/4-second RTCINTF.1_4SECIF See Figure 9.5.1. Writing 1
1/8-second RTCINTF.1_8SECIF See Figure 9.5.1. Writing 1
1/32-second RTCINTF.1_32SECIF See Figure 9.5.1. Writing 1
Stopwatch 1 Hz RTCINTF.SW1IF 1/10-second counter overflow Writing 1
Stopwatch 10 Hz RTCINTF.SW10IF 1/10-second counter count up Writing 1
Stopwatch 100 Hz RTCINTF.SW100IF 1/100-second counter count up Writing 1
Theoretical regulation
RTCINTF.RTCTRMIF At the end of theoretical regulation operation Writing 1
completion
Writing 1
9
9
2/256
s
256 Hz
128 Hz
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
1 Hz
Interrupt flags
1/8-second interrupt
1/4-second interrupt
1/2-second interrupt
1-second interrupt
1-minute interrupt
1-hour interrupt
1-day interrupt
At counter count-up timing
Figure 9.5.1 RTCA Interrupt Timings
Notes: • 1-second to 1/32-second interrupts occur after a lapse of 1/256 second from change of the
1 Hz counter value.
• An alarm interrupt occurs after a lapse of 1/256 second from matching between the AM/PM (in
12H mode), hour, minute, and second counter value and the alarm setting value.
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