Page 1
CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
S1C17F13
Technical Manual
Rev. 1.0
Page 2
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability
of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and,
further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation
or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third
party. When exporting the products or technology described in this material, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You are requested not to use, to resell, to
export and/or to otherwise dispose of the products (and any technical information furnished, if any) for the development and/or
manufacture of weapon of mass destruction or for other military purposes.
All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies.
SEIKO EPSON CORPORATION
©
2012, All rights reserved.
Page 3
Devices
S1
C 17xxx F 00E1
Packing specifications
00 : Besides tape & reel
0A : TCP BL 2 directions
0B : Tape & reel BACK
0C : TCP BR 2 directions
0D : TCP BT 2 directions
0E : TCP BD 2 directions
0F : Tape & reel FRONT
0G : TCP BT 4 directions
0H : TCP BD 4 directions
0J : TCP SL 2 directions
0K : TCP SR 2 directions
0L : Tape & reel LEFT
0M : TCP ST 2 directions
0N : TCP SD 2 directions
0P : TCP ST 4 directions
0Q : TCP SD 4 directions
0R : Tape & reel RIGHT
99 : Specs not fixed
Specification
Package
D: die form; F: QFP, B: BGA, WCSP
Model number
Model name
C: microcomputer, digital products
Product classification
S1: semiconductor
Development tools
S5U1
C 17000 H2 1
Packing specifications
00: standard packing
Version
1: Version 1
Tool type
Hx : ICE
Dx : Evaluation board
Ex : ROM emulation board
Mx : Emulation memory for external ROM
Tx : A socket for mounting
Cx : Compiler package
Sx : Middleware package
Yx : Writer software
Corresponding model number
17xxx: for S1C17xxx
Tool classification
C: microcomputer use
Product classification
S5U1: development tool for semiconductor products
00
00
Configuration of product number
Configuration of product number
CONFIGURATION OF PRODUCT NUMBER
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
(Rev. 1.0)
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PREFACE
Preface
This is a technical manual for designers and programmers who develop a product using the S1C17F13. This
document describes the functions of the IC, embedded peripheral circuit operations, and their control methods.
For the CPU functions and instructions, refer to the “S1C17 Family S1C17 Core Manual.” For the functions
and operations of the debugging tools, refer to the respective tool
loads” website provides the downloadable manuals.)
manuals. (Our “Products: Document Down-
Notational conventions and symbols in this manual
Register address
Peripheral circuit chapters do not provide control register addresses. Refer to “Peripheral Circuit Area” in
the “Memory and Bus” chapter or “List of Peripheral Circuit Control Registers” in the Appendix.
Register and control bit names
In this
Register table contents and symbols
manual, the register and control bit names are described as shown below to distinguish from signal
and pin names.
XXX register: Represents a register including its all bits.
XXX.YYY bit: Represents the one control bit YYY in the XXX register.
XXX.ZZZ[1:0] bits: Represents the two control bits ZZZ1 and ZZZ0 in the XXX register.
Initial: Value set at initialization
Re
set: Initialization condition. The initialization condition depends on the reset group (H0, H1, or S0).
For more information on the reset groups, refer to “Initialization Conditions (Reset Groups)” in the
“Power Supply, Reset, and Clocks” chapter.
R/W: R = Read only bit
W = Write only bit
WP = Write only bit with a write protection using the MSCPROT.PROT[15:0] bits
R/W = Read/write bit
R/WP = Read/
Control bit read/write values
This manual describes control bit values in a hexadecimal notation except for one-bit values (and except
when decimal or binary notation is required in terms of explanation). The values are described as shown
below according to the control bit width.
1 bit: 0 or 1
2 to 4 bits: 0x0 to 0xf
5 to 8 bits:
9 to 12 bits: 0x000 to 0xfff
13 to 16 bits: 0x0000 to 0xffff
Decimal: 0 to 9999...
Binary: 0b0000... to 0b1111...
Channel number
Multiple channels may be implemented in some peripheral circuits (e.g., 16-bit timer, etc.). The peripheral
circuit chapters use ‘n’ as the value that represents the channel number in the register and pin names regard-
less of the number of channel actually i
If there is a channel that has different functions from others, the channel number is specified clearly.
Example) T16_nCTL register of the 16-bit timer
If one channel is implemented (Ch.0 only): T16_nCTL = T16_0CTL only
If two channels are implemented (Ch.0 and Ch.1): T16_nCTL = T16_0CTL and T16_1CTL
0x00 to 0xff
write bit with a write protection using the MSCPROT.PROT[15:0] bits
mplemented. Normally, the descriptions are applied to all channels.
For the number of channels impl
“Overview” chapter.
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emented in the peripheral circuits of this IC, refer to “Features” in the
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CONTENTS
– Contents –
Configuration of product number..............................................................................................i
Preface ..................................................................................................................................... ii
Notational conventions and symbols in this manual ............................................................... ii
1 Overview ........................................................................................................................1-1
1.1 Features .......................................................................................................................... 1-1
1.2 Block Diagram ................................................................................................................. 1-3
1.3 Pins ................................................................................................................................. 1-4
1.3.1 Pin Configuration Diagram (TQFP13-64pin) ..................................................... 1-4
1.3.2 Pad Configuration Diagram (Chip) .................................................................... 1-5
1.3.3 Pin Descriptions ..........
...................................................................................... 1-6
2 Power Supply, Reset, and Clocks ...............................................................................2-1
2.1 Power Generator (PWG) .................................................................................................. 2-1
2.1.1 Overview ..................................................
2.1.2 Pins ................................................................................................................... 2-2
2.1.3 V
2.1.4 V
D1 Regulator .................................................................................................... 2-2
OSC Regulator .................................................................................................. 2-2
2.1.5 Flash Programming Power Supply (V
2.2 System Reset Controller (SRC) ....................................................................................... 2-2
2.2.1 Overview ........................................................................................................... 2-2
2.2.2
Input Pin ............................................................................................................ 2-3
2.2.3 Reset Sources .................................................................................................. 2-3
2.2.4 Initialization Conditions (Reset Groups) ............................................................ 2-4
2.3 Clock Generator (CLG) ..................
.................................................................................. 2-5
2.3.1 Overview ........................................................................................................... 2-5
2.3.2 Input/Output Pins ............................................................................................. 2-6
2.3.3 Clock Sources ...............................................
2.3.4 Operations ........................................................................................................ 2-8
2.4 Operating Mode ............................................................................................................. 2-11
2.4.1 Initial Boot Sequence ...........................................................
2.4.2 Transition between Operating Modes .............................................................. 2-11
2.5 Interrupts ........................................................................................................................ 2-12
2.6 Control Registers .................................................................................................
PWG VD1 Regulator Control Register ....................................................................................... 2-13
CLG System Clock Control Register ........................................................................................ 2-13
CLG Oscillation Control Register ............................................................................................. 2-14
CLG OSC3B Control Register .................................................................................................. 2-15
CLG OSC1 Control Register .................................................................................................... 2-15
CLG OSC3A Control Register .................................................................................................. 2-16
CLG Interrupt Flag Register ..................................................................................................... 2-16
CLG Interrupt Enable Register ................................................................................................. 2-17
CLG FOUT Control Register ..................................................................................................... 2-17
......................................................... 2-1
PP) ........................................................... 2-2
................................................... 2-6
............................ 2-11
.......... 2-13
3 CPU and Debugger ......................................................................................................3-1
3.1 Overview ......................................................................................................................... 3-1
3.2 CPU Core ........................................................................................................................ 3-2
3.2.1 CPU Registers
3.2.2 Instruction Set .................................................................................................. 3-2
3.2.3 Reading PSR .................................................................................................... 3-2
3.2.4 I/O Area Reserved for the S1C17 Core .........
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3.3 Debugger ........................................................................................................................ 3-2
3.3.1 Debugging Functions........................................................................................ 3-2
3.3.2 Resource Requirements and Debugging Tools ................................................ 3-2
3.3.3 List of debugger input/output pins ....
............................................................... 3-3
3.3.4 External Connection ......................................................................................... 3-3
3.4 Control Register .............................................................................................................. 3-3
MISC PSR Register ................................................................................................................... 3-3
Debug RAM Base Register ....................................................................................................... 3-4
4 Memory and Bus ..........................................................................................................4-1
4.1 Overview ......................................................................................................................... 4-1
4.2 Bus Access Cycle ........................................................................................................... 4-1
4.3 Flash Memory ................................................................................................................. 4-2
4.3.1 Flash Bus Access Cycle Setting .............................................
4.3.2 Flash Programming ........................................................................................... 4-2
4.3.3 Flash Security Function .................................................................................... 4-3
4.4 RAM1 ............................................................................................................................
4.5 RAM2 .............................................................................................................................. 4-3
4.6 Peripheral Circuit Control Registers ................................................................................ 4-3
4.6.1 System-Protect Function .................................................................................. 4-7
4.7 Control Re
gisters ............................................................................................................ 4-7
MISC System Protect Register ................................................................................................. 4-7
MISC IRAM Size Register.......................................................................................................... 4-7
FLASHC Flash Read Cycle Register ......................................................................................... 4-8
.......................... 4-2
.. 4-3
5 Interrupt Controller (ITC) .............................................................................................5-1
5.1 Overview ......................................................................................................................... 5-1
5.2 Vector Table .................................................................................................................... 5-1
5.2.1 Vector Table Base Address (TTBR) ................................................................... 5-3
5.3 Initialization ..................................................................................................................... 5-3
5.4 Maskable Interrupt Control and Operatio
ns ................................................................... 5-3
5.4.1 Peripheral Circuit Interrupt Control ................................................................... 5-3
5.4.2 ITC Interrupt Request Processing .................................................................... 5-4
5.4.3 Conditions to Accept Interrupt Requests by the CPU...................................... 5-4
5.5
NMI .................................................................................................................................. 5-4
5.6 Software Interrupts ......................................................................................................... 5-4
5.7 Interrupt Processing by the CPU .................................................................................... 5-5
5.8 Control Registers ............................................................................................................ 5-5
MISC Vector Table Address Low Register ................................................................................ 5-5
MISC Vector Table Address High Register ................................................................................ 5-5
ITC Interrupt Level Setup Register x ......................................................................................... 5-5
6 I/O Ports (PPORT) .........................................................................................................6-1
6.1 Overview ......................................................................................................................... 6-1
6.2 I/O Cell Structure and Functions ..................................................................................... 6-2
6.2.1 Schmitt Input .................................................................................................... 6-2
6.2.2 Over Voltage Tolerant Fail-Safe Type I/O Cell ................................................... 6-2
6.2.3 Pull-Up/Pull-Down ................................................
6.2.4 CMOS Output and High Impedance State ....................................................... 6-3
6.3 Clock Settings ................................................................................................................. 6-3
6.3.1 PPORT Operating Clock ................................................................................... 6-3
6.3.2 Clock Supply in SLEEP Mode .......................................................................... 6-3
6.3.3 Clock Supply in DEBUG Mode ......................................................................... 6-3
............................................ 6-2
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6.4 Operations ...................................................................................................................... 6-3
6.4.1 Initialization ....................................................................................................... 6-3
6.4.2 Port Input/Output Control ................................................................................. 6-5
6.5 Interrupts ..
....................................................................................................................... 6-6
6.6 Control Registers ............................................................................................................ 6-6
Px Port Data Register ................................................................................................................ 6-6
Px Port Enable Register ............................................................................................................ 6-7
Px Port Pull-up/down Control Register ..................................................................................... 6-7
Px Port Interrupt Flag Register .................................................................................................. 6-8
Px Port Interrupt Control Register ............................................................................................. 6-8
Px Port Chattering Filter Enable Register .................................................................................. 6-8
Px Port Mode Select Register ................................................................................................... 6-8
Px Port Function Select Register .............................................................................................. 6-9
P Port Clock Control Register ................................................................................................... 6-9
P Port Interrupt Flag Group Register ........................................................................................ 6-10
6.7 Control Register and Port Function Configuration of this IC ......................................... 6-11
6.7.1 P0 Port Group .................................................................................................. 6-11
6.7.2 P1 Port Group .................................................................................................. 6-12
6.7.3 P2 Port Group ........................................................
.......................................... 6-12
6.7.4 P3 Port Group .................................................................................................. 6-13
6.7.5 P4 Port Group .................................................................................................. 6-14
6.7.6 Pd Port Group .......................................................................................
........... 6-15
6.7.7 Common Registers between Port Groups....................................................... 6-15
7 Watchdog Timer (WDT) ................................................................................................7-1
7.1 Overview ......................................................................................................................... 7-1
7.2 Clock Settings ................................................................................................................. 7-1
7.2.1 WDT Operating Clock ....................................................................................... 7-1
7.2.2 Clock Supply in DEBUG Mode ......................................................................... 7-2
7.3 Operations ...........................................
........................................................................... 7-2
7.3.1 WDT Control ..................................................................................................... 7-2
7.3.2 Operations in HALT and SLEEP Modes............................................................ 7-2
7.4 Control Registers ........................................................................
WDT Clock Control Register ..................................................................................................... 7-3
WDT Control Register ............................................................................................................... 7-3
.................................... 7-3
8 Supply Voltage Detector (SVD) ....................................................................................8-1
8.1 Overview ......................................................................................................................... 8-1
8.2 Input Pin and External Connection ................................................................................. 8-2
8.2.1 Input Pin .................................................................................................
8.2.2 External Connection ......................................................................................... 8-2
8.3 Clock Settings ................................................................................................................. 8-2
8.3.1 SVD Operating Clock ........................................................................................ 8-2
8.3.2 Clock
Supply in SLEEP Mode .......................................................................... 8-2
8.3.3 Clock Supply in DEBUG Mode ......................................................................... 8-3
8.4 Operations ...................................................................................................................... 8-3
8.4.1 SVD Control ....................................
.................................................................. 8-3
8.4.2 SVD Operations ................................................................................................ 8-4
8.5 SVD Interrupt and Reset ................................................................................................. 8-4
8.5.1 SVD Interrupt ............................................................
........................................ 8-4
8.5.2 SVD Reset ......................................................................................................... 8-5
8.6 Control Registers ............................................................................................................ 8-5
SVD Clock Control Register ...................................................................................................... 8-5
SVD Control Register ................................................................................................................ 8-6
........... 8-2
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SVD Status and Interrupt Flag Register .................................................................................... 8-7
SVD Interrupt Enable Register .................................................................................................. 8-8
9 16-bit Timers (T16) ........................................................................................................9-1
9.1 Overview ......................................................................................................................... 9-1
9.2 Input Pin .......................................................................................................................... 9-1
9.3 Clock Settings ................................................................................................................. 9-2
9.3.1 T16 Operating Clock ......................................................................................... 9-2
9.3.2 Clock Supply in SLEEP Mode .......................................................................... 9-2
9.3.3 Clock Supply in DEBUG Mode ......................................................................... 9-2
9.3.4 Event Counter Clock ................................
9.4 Operations ...................................................................................................................... 9-2
9.4.1 Initialization ....................................................................................................... 9-2
9.4.2 Counter Underflow ..................................................
9.4.3 Operations in Repeat Mode .............................................................................. 9-3
9.4.4 Operations in One-shot Mode .......................................................................... 9-3
9.4.5 Counter Value Read .......................................................................................... 9-4
9.5 Interr
upt ........................................................................................................................... 9-4
9.6 Control Registers ............................................................................................................ 9-4
T16 Ch.n Clock Control Register .............................................................................................. 9-4
T16 Ch.n Mode Register ........................................................................................................... 9-5
T16 Ch.n Control Register ......................................................................................................... 9-5
T16 Ch.n Reload Data Register ................................................................................................. 9-6
T16 Ch.n Counter Data Register ............................................................................................... 9-6
T16 Ch.n Interrupt Flag Register ............................................................................................... 9-6
T16 Ch.n Interrupt Enable Register ........................................................................................... 9-7
......................................................... 9-2
......................................... 9-3
10 UART (UART) ..............................................................................................................10-1
10.1 Overview ...................................................................................................................... 10-1
10.2 Input/Output Pins and External Connections .............................................................. 10-2
10.2.1 List of Input/Output Pins .....
10.2.2 External Connections .................................................................................... 10-2
10.2.3 Input Pin Pull-Up Function............................................................................. 10-2
10.2.4 Output Pin Open-Drain Output Function ..........................................
10.3 Clock Settings .............................................................................................................. 10-2
10.3.1 UART Operating Clock .................................................................................. 10-2
10.3.2 Clock Supply in SLEEP Mode ....................................................................... 10-2
10.3.3 Clock Supply in
DEBUG Mode ...................................................................... 10-3
10.3.4 Baud Rate Generator ..................................................................................... 10-3
10.4 Data Format ................................................................................................................. 10-3
10.5 Operations ..............................................
10.5.1 Initialization .................................................................................................... 10-4
10.5.2 Data Transmission ......................................................................................... 10-4
10.5.3 Data Reception ..........................................................
10.5.4 IrDA Interface ................................................................................................. 10-6
10.6 Receive Errors .............................................................................................................. 10-7
10.6.1 Framing Error ...............................................................................
10.6.2 Parity Error ..................................................................................................... 10-8
10.6.3 Overrun Error ................................................................................................. 10-8
10.7 Interrupts ................................................................................................................
10.8 Control Registers ......................................................................................................... 10-8
UART Ch.n Clock Control Register .......................................................................................... 10-8
UART Ch.n Mode Register ....................................................................................................... 10-9
UART Ch.n Baud–Rate Register ............................................................................................. 10-10
........................................................................... 10-2
............ 10-2
..................................................................... 10-4
.................................... 10-5
.................. 10-7
...... 10-8
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UART Ch.n Control Register ................................................................................................... 10-10
UART Ch.n Transmit Data Register ......................................................................................... 10-11
UART Ch.n Receive Data Register .......................................................................................... 10-11
UART Ch.n Status and Interrupt Flag Register ....................................................................... 10-11
UART Ch.n Interrupt Enable Register...................................................................................... 10-12
11 Synchronous Serial Interface (SPI) ..........................................................................11-1
11.1 Overview ...................................................................................................................... 11-1
11.2 Input/Output Pins and External Connections .............................................................. 11-2
11.2.1 List of Input/Output Pins ................................................................................ 11-2
11.2.2 External Connections ....................................................
11.2.3 Pin Functions in Master Mode and Slave Mode ............................................ 11-3
11.2.4 Input Pin Pull-Up/Pull-Down Function .......................................................... 11-3
11.3 Clock Settings .............................................................................................................. 11-3
11.3.1 SPI Operating
Clock ...................................................................................... 11-3
11.3.2 Clock Supply in DEBUG Mode ...................................................................... 11-4
11.3.3 SPI Clock (SPICLKn) Phase and Polarity ...................................................... 11-4
11.4 Data Format .......................................................................
11.5 Operations ................................................................................................................... 11-5
11.5.1 Initialization .................................................................................................... 11-5
11.5.2 Data Transmission in Master Mode ..................................................
11.5.3 Data Reception in Master Mode .................................................................... 11-7
11.5.4 Terminating Data Transfer in Master Mode .................................................... 11-8
11.5.5 Data Transfer in Slave Mode .......................................................................... 11-8
11.5.6 Terminating Data Transfer in Slave Mode ......
............................................... 11-10
11.6 Interrupts ..................................................................................................................... 11-10
11.7 Control Registers ........................................................................................................ 11-11
SPI Ch.n Mode Register .......................................................................................................... 11-11
SPI Ch.n Control Register ....................................................................................................... 11-11
SPI Ch.n Transmit Data Register ............................................................................................. 11-12
SPI Ch.n Receive Data Register .............................................................................................. 11-12
SPI Ch.n Interrupt Flag Register ............................................................................................. 11-12
SPI Ch.n Interrupt Enable Register ......................................................................................... 11-13
................................ 11-2
.......................................... 11-5
............. 11-5
12 I2C (I2C) .......................................................................................................................12-1
12.1 Overview ...................................................................................................................... 12-1
12.2 Input/Output Pins and External Connections .............................................................. 12-2
12.2.1 List of Input/Output Pins .................................................................
12.2.2 External Connections .................................................................................... 12-2
12.3 Clock Settings .............................................................................................................. 12-3
12.3.1 I2C Operating Clock ...................................................................................... 12-3
12.3.2 Clo
ck Supply in DEBUG Mode ...................................................................... 12-3
12.3.3 Baud Rate Generator ..................................................................................... 12-3
12.4 Operations ................................................................................................................... 12-4
12.4.1 Initialization ..........................
.......................................................................... 12-4
12.4.2 Data Transmission in Master Mode ............................................................... 12-5
12.4.3 Data Reception in Master Mode .................................................................... 12-7
12.4.4 10-bit Addressing in Master Mode ...............................................................
12.4.5 Data Transmission in Slave Mode................................................................. 12-10
12.4.6 Data Reception in Slave Mode ..................................................................... 12-12
12.4.7 Slave Operations in 10-bit Address Mode .................................................... 12-14
12.4.8 Automatic Bus Clearing Operation .............................
.................................. 12-14
12.4.9 Error Detection .............................................................................................. 12-15
12.5 Interrupts ..................................................................................................................... 12-16
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12.6 Control Registers ........................................................................................................ 12-17
I2C Ch.n Clock Control Register ............................................................................................. 12-17
I2C Ch.n Mode Register .......................................................................................................... 12-18
I2C Ch.n Baud-Rate Register .................................................................................................. 12-18
I2C Ch.n Own Address Register ............................................................................................. 12-18
I2C Ch.n Control Register ....................................................................................................... 12-19
I2C Ch.n Transmit Data Register ............................................................................................. 12-20
I2C Ch.n Receive Data Register .............................................................................................. 12-20
I2C Ch.n Status and Interrupt Flag Register ........................................................................... 12-20
I2C Ch.n Interrupt Enable Register ......................................................................................... 12-21
13 Clock Timer (CT) ........................................................................................................13-1
13.1 Overview ...................................................................................................................... 13-1
13.2 Clock Settings .............................................................................................................. 13-1
13.3 Operations ................................................................................................................... 13-1
13.4 Interrupts ...................................................................................................................... 13-2
13.5 Control Registers ......................................................................................................... 13-3
CT Control Register .................................................................................................................. 13-3
CT Counter Data Register ........................................................................................................ 13-3
CT Interrupt Flag Register ........................................................................................................ 13-4
CT Interrupt Enable Register .................................................................................................... 13-4
14 Real-Time Clock (RTC)..............................................................................................14-1
14.1 Overview ...................................................................................................................... 14-1
14.2 Clock Settings .............................................................................................................. 14-1
14.3 RTC Counters .............................................................................................................. 14-1
14.4 Operations ................................................................................................................... 14-3
14.4.1 Time Setting ................................................................................................... 14-3
14.4.2 Time Read ...................................................................................................... 14-4
14.5 Interrupts ....................
14.6 Control Registers ......................................................................................................... 14-5
RTC Control Register ............................................................................................................... 14-5
RTC Interrupt Enable Register ................................................................................................. 14-6
RTC Interrupt Flag Register ...................................................................................................... 14-6
RTC Minute/Second Register................................................................................................... 14-7
RTC Hour Register ................................................................................................................... 14-7
.................................................................................................. 14-4
15 Theoretical Regulation (TR) ......................................................................................15-1
15.1 Overview ...................................................................................................................... 15-1
15.2 Output Pin .................................................................................................................... 15-1
15.3 Operations ................................................................................................................... 15-1
15.3.1 Executing Theoretical Regulation .................................................................. 15-1
15.3.2 Regulated Clock External Monitor ..............
................................................... 15-3
15.4 Control Register ........................................................................................................... 15-3
Theoretical Regulation Control Register .................................................................................. 15-3
16 16-bit PWM Timers (T16A3) ......................................................................................16-1
16.1 Overview ...................................................................................................................... 16-1
16.2 Input/Output Pins ......................................................................................................... 16-2
16.3 Clock Settings .............................................................................................................. 16-2
16.3.1 T16A3 Operating Clock ................................................................................. 16-2
16.3.2 Clock Supply in SLEEP Mode ....................................................................... 16-3
16.3.3 Clock Supply in DEBUG Mode ...................................................................... 16-3
16.3.4 Event Counter Cloc
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16.4 Operations ................................................................................................................... 16-3
16.4.1 Initialization .................................................................................................... 16-3
16.4.2 Counter Block Operations ............................................................................. 16-4
16.4.3 Comparator/Capt
ure Block Operations ......................................................... 16-5
16.4.4 TOUT Output Control .................................................................................... 16-9
16.5 Interrupt ....................................................................................................................... 16-11
16.6 Control Registers ......................................
T16A3 Ch.n Clock Control Register ........................................................................................ 16-11
T16A3 Counter Ch.n Control Register .................................................................................... 16-12
T16A3 Counter Ch.n Data Register ......................................................................................... 16-13
T16A3 Comparator/Capture Ch.n Control Register ................................................................ 16-14
T16A3 Comparator/Capture Ch.n A Data Register ................................................................. 16-15
T16A3 Comparator/Capture Ch.n B Data Register ................................................................. 16-15
T16A3 Ch.n Interrupt Flag Register ......................................................................................... 16-16
T16A3 Ch.n Interrupt Enable Register..................................................................................... 16-16
.................................................................. 16-11
17 Parallel Interface (PIO) ..............................................................................................17-1
17.1 Overview ...................................................................................................................... 17-1
17.2 Input/Output Pins and External Connections .............................................................. 17-1
17.2.1 List of Input/Output Pins ................................................................................ 17-1
17.2.2 External Connections .....................
17.2.3 Pin Pull-Up Function ...................................................................................... 17-2
17.3 Clock Settings .............................................................................................................. 17-2
17.3.1 PIO Operating Clock ...................................................
17.3.2 Clock Supply in SLEEP Mode ....................................................................... 17-2
17.3.3 Clock Supply in DEBUG Mode ...................................................................... 17-2
17.4 Operations ................................................................................................................... 17-2
17.4.1
Initialization .................................................................................................... 17-2
17.4.2 Operations in SRAM Mode ............................................................................ 17-3
17.4.3 Operations in GPIO Mode ............................................................................. 17-4
17.5 Control Registers ..............................
PIO Clock Control Register ...................................................................................................... 17-5
PIO Mode Register ................................................................................................................... 17-5
PIO Control Register ................................................................................................................ 17-6
PIO Address/Write Data Register ............................................................................................. 17-6
PIO Read Data Register ........................................................................................................... 17-6
PIO Status Register .................................................................................................................. 17-7
........................................................................... 17-5
............................................................... 17-2
................................... 17-2
18 EPD Timing Controller (EPD Tcon) ...........................................................................18-1
18.1 Overview ...................................................................................................................... 18-1
18.2 Interrupt ........................................................................................................................ 18-1
18.3 Control Registers ......................................................................................................... 18-2
EPD Tcon Control Register ....................................................................................................... 18-2
EPD Tcon Interrupt Flag and Status Register ........................................................................... 18-2
EPD Tcon Interrupt Enable Register ......................................................................................... 18-2
19 R/F Converter (RFC) ..................................................................................................19-1
19.1 Overview ...................................................................................................................... 19-1
19.2 Input/Output Pins and External Connections .............................................................. 19-2
19.2.1 List of Input/Output Pins ................................................................................ 19-2
19.2.2 External Connections ..............................................................................
19.3 Clock Settings .............................................................................................................. 19-3
19.3.1 RFC Operating Clock ..................................................................................... 19-3
19.3.2 Clock Supply in SLEEP Mode ....................................................................... 19-3
19.3.3 Clock Supply in DEBU
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
(Rev. 1.0)
G Mode ...................................................................... 19-3
...... 19-2
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CONTENTS
19.4 Operations ................................................................................................................... 19-3
19.4.1 Initialization .................................................................................................... 19-3
19.4.2 Operating Modes ........................................................................................... 19-4
19.4.3 RFC Counte
rs ................................................................................................ 19-4
19.4.4 Converting Operations and Control Procedure ............................................. 19-5
19.4.5 CR Oscillation Frequency Monitoring Function ............................................. 19-7
19.5 Interrupts .............................................................................
......................................... 19-7
19.6 Control Registers ......................................................................................................... 19-8
RFC Ch.n Clock Control Register ............................................................................................ 19-8
RFC Ch.n Control Register ....................................................................................................... 19-8
RFC Ch.n Oscillation Trigger Register ...................................................................................... 19-9
RFC Ch.n Measurement Counter Low and High Registers .................................................... 19-10
RFC Ch.n Time Base Counter Low and High Registers ......................................................... 19-10
RFC Ch.n Interrupt Flag Register ............................................................................................ 19-11
RFC Ch.n Interrupt Enable Register ........................................................................................ 19-11
20 Temperature Detection Circuit (TEM) ......................................................................20-1
20.1 Overview ...................................................................................................................... 20-1
20.2 Clock Settings .............................................................................................................. 20-2
20.2.1 TEM Operating Clock .................................................................................... 20-2
20.2.2 Clock Supply in SLEEP Mode .................
20.2.3 Clock Supply in DEBUG Mode ...................................................................... 20-2
20.3 Operations ................................................................................................................... 20-2
20.3.1 Initialization ..........................................................................
20.3.2 Comparison Time Setting .............................................................................. 20-2
20.3.3 Temperature Detection ................................................................................. 20-3
20.4 Interrupt ........................................................................................................................ 20-5
20.5 Control Registers ......................................................................................................... 20-5
TEM Clock Control Register ..................................................................................................... 20-5
TEM Timing Register ................................................................................................................ 20-5
TEM Control Register ............................................................................................................... 20-6
TEM Conversion Result Register ............................................................................................. 20-6
TEM Interrupt Flag and Status Register ................................................................................... 20-6
TEM Interrupt Enable Register ................................................................................................. 20-7
...................................................... 20-2
.......................... 20-2
21 Multiplier/Divider (COPRO) .......................................................................................21-1
21.1 Overview ...................................................................................................................... 21-1
21.2 Operation Mode and Output Mode .............................................................................. 21-1
21.3 Multiplication ................................................................................................................ 21-2
21.4 Division ......................................................................................................................... 21-3
21.5 MAC ............................................................................................................................. 21-4
21.6 Reading Operation Results .......................................................................................... 21-6
22 Electrical Characteristics .........................................................................................22-1
22.1 Absolute Maximum Ratings ......................................................................................... 22-1
22.2 Recommended Operating Conditions ......................................................................... 22-1
22.3 Current Consumption ................................................................................................... 22-2
22.4 System Reset Controller (SRC) Characteristics ........................................................... 22-4
22.5 Clock Generator (CLG) Characteristics........................................................................ 22-5
22.6 Flash Memory Characteristics ..................................................................................... 22-6
22.7 Input/Output Port (PPORT) Characteristics ................................................................. 22-7
22.8 Supply Voltage Detector (SVD) Characteristics ........................................................... 22-8
22.9 UART (UART) Characteristics ...................................................................................... 22-9
22.10 Synchronous Serial Interface (SPIA) Characteristics ................................................. 22-9
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Seiko Epson Corporation S1C17F13 TECHNICAL MANUAL
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22.11 I2C (I2C) Characteristics ............................................................................................ 22-10
22.12 Parallel Interface (PIO) Characteristics ..................................................................... 22-10
22.13 EPD Timing Controller (EPD Tcon) Characteristics ................................................... 22-11
22.14 R/F Converter (RFC) Characteristics......................................................................... 22-11
22.15 Temperature Detection Circuit Characteristics ......................................................... 22-12
23 Basic External Connection Diagram .......................................................................23-1
24 Package ............................................................................
..........................................24-1
Appendix A List of Peripheral Circuit Control Registers ......................................... AP-A-1
0x4000–0x4008 Misc Registers (MISC) ........................................................... AP-A-1
0x4020 Power Generator (PWG) ........................................................ AP-A-1
0x4040–0x404e Clock Generator (CLG) ......................
0x4052 Theoretical Regulation (TR) .................................................... AP-A-2
0x4080–0x4092 Interrupt Controller (ITC) ........................................................ AP-A-2
0x40a0–0x40a2 Watchdog Timer (WDT) .......................................................... AP-A-3
0x40c0–0x40c8 Real-time Clock (RTC) ...........................
0x4100–0x4106 Supply Voltage Detector (SVD) .............................................. AP-A-4
0x4160–0x416c 16-bit Timer (T16) Ch.0 .......................................................... AP-A-5
0x41b0 Flash Controller (FLASHC) ..................................................... AP-A-5
0x4200–0x42e2 I/O Ports (PPORT) ........................................
0x4380–0x438e UART (UART) ......................................................................... AP-A-8
0x43a0–0x43ac 16-bit Timer (T16) Ch.1 .......................................................... AP-A-9
0x43b0–0x43ba SPI (SPI) Ch.0 ....................................................................... AP-A-10
0x43c0–0x43d2 I
0x5000–0x500e 16-bit PWM Timer (T16A3) Ch.0 ........................................... AP-A-11
0x5020–0x502e 16-bit PWM Timer (T16A3) Ch.1 ........................................... AP-A-12
0x5180–0x5186 Clock Timer (CT) ................................................................... AP-A-13
0x5260–0x526c 16-bit Timer (T16) Ch.2 ...........
0x5270–0x527a SPI (SPI) Ch.1 ....................................................................... AP-A-14
0x5280–0x528c 16-bit Timer (T16) Ch.3 ......................................................... AP-A-15
0x5290–0x529a SPI (SPI) Ch.2 ....................................................................... AP-A-15
0x52e0–0x52ea Parallel Interfac
0x5380–0x5384 EPD Timing Controller (EPD Tcon) ........................................ AP-A-16
0x5440–0x5450 R/F Converter (RFC) Ch.0 ..................................................... AP-A-17
0x5460–0x5470 R/F Converter (RFC) Ch.1 ..................................................... AP-A-18
0x54c0–0x54ca Temperature Detection
0xffff90 Debugger (DBG) ................................................................... AP-A-19
2
C (I2C) ................................................................................. AP-A-10
e (PIO) .......................................................... AP-A-16
Circuit (TEM) .................................... AP-A-19
.................................... AP-A-1
................................ AP-A-4
.......................... AP-A-5
.............................................. AP-A-14
Appendix B Power Saving .......................................................................................... AP-B-1
B.1 Operating Status Configuration Examples for Power Saving ...................................... AP-B-1
B.2 Other Power Saving Methods ..................................................................................... AP-B-2
Appendix C Mounting Precautions ............................................................................ AP-C-1
Appendix D Measures Against Noise ........................................................................ AP-D-1
Appendix E Initialization Routine ...............................
................................................ AP-E-1
Revision History
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
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1 OVERVIEW
Overview1
The S1C17F13 is an ultra low-power MCU equipped with a display memory and an EPD timing controller to send
display data for using the active EPD panels. This IC includes the synchronous serial interface, parallel interface,
UART, and I
ronmental conditions such as a temperature and humidity
age measurement using the supply voltage detector and brownout reset circuits.
Model S1C17F13
CPU
CPU core Seiko Epson original 16-bit RISC CPU core S1C17
Multiplier/Divider (COPRO) 16-bit × 16-bit multiplier
Other On-chip debugger
Embedded Flash memory
Capacity 128K bytes (for both instructions and data) *1
Erase/program count 50 times (min.) * Programming by the debugging tool ICDmini
Other Security function
Embedded RAM
Capacity 6K bytes (area accessed by CPU only)
Clock generator (CLG)
System clock source 5 sources (OSC3B, OSC3A, OSC1B, OSC1A, and EXOSC)
System clock frequency (operating frequency)
OSC3B internal high-speed oscillator circuit
(boot clock source)
OSC1B internal low-speed oscillator circuit 32 kHz (typ.)
OSC3A high-speed oscillator circuit 20 MHz (max.) crystal or ceramic oscillator circuit
OSC1A low-speed oscillator circuit 32.768 kHz (typ.) crystal oscillator circuit
EXOSC clock input 20 MHz (max.) square or sine wave i
Other Configurable system clock division ratio
I/O port (PPORT)
Number of
Number of input interrupt ports 8 bits
Other All pins contain a pull-up/down re
Display control
EPD timing controller (EPD Tcon) Controls display on the active-matrix EPD via the embedded SPI or PIO.
Communication interfa
UART (UART) 1 channel
Synchronous serial interface (SPI) 3 channels
2
I
C (I2C) 1 channel
Parallel interface (PIO) Address length: 8 bits (max.)
2
C to communicate with an EPD panel and other devices. This IC allows measurement of various envi-
measurement using the R/F converter, and a supply volt-
Features1.1
1.1 FeaturesTable 1.
16-bit × 16-bit + 32-bit multiply and accumulation unit
16-bit ÷ 16-bit divider
to protect from reading/programming by ICDmini
nput
(Pins are shared with the peripheral I/O.)
sistor that can be enabled/disabled via software.
ion interface for EPD Tcon
general-purpose I/O
ces
ports 37
On-board programming function using ICDmini
Embedded Flash voltage booster to generate the Flash erasing/programming voltage
14K bytes (area accessed by CPU and EPD Tcon)
20 MHz (max.)
20/16/12/8 MHz (typ.) selectable via software
Configurable system clock (except for OSC1A and OSC1B) used at wake up from
SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
bits (max.)
16 bits contain an interrupt function and a chattering filter function.
Includes a display data read function from the embedded RAM (area for both CPU
and EPD Tcon).
Can be controlled with the dedicated API library.
IrDA1.0 supported
Embedded baud-rate generator
Configurable as the communication interface for EPD Tcon (SPI Ch.1)
Master and slave operations supported
Embedded baud-rate generator
Data width: 8 bits (max.)
Control signals: #CE, #RD, #WR
Configurable as the communicat
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
(Rev. 1.0)
1-1
Page 15
1 OVERVIEW
Timers
Watchdog timer (WDT) 1 channel
16-bit timer (T16) 4 channels
Clock timer (CT) 1 channel
Real-time clock (RTC) Hour, minute, and second counters
Theoretical regulation function (TR) Time adjustment function in -31/32,768 to +32/32,768 second units (applied to T16A3,
16-bit PWM timer (T16A3) 2 channels
Supply voltage detector (SVD)
Detection level 19 values (1.8 to 3.6 V)
Other Intermittent operation mode
R/F converter (RFC)
Conversion method CR oscillation type with 24-bit counters
Numb
er of conversion channels 2 channels (Up to four sensors can be connected.)
Supported sensors DC-bias resistive sensors and AC-bias resistive sensors
Temperature detection circuit (TEM)
Resolution/accuracy 1 °C steps, ±5 °C accuracy
Reset
#RESET pin Reset when the reset pin is set to low.
Power-on reset Reset at power-on.
Brownout reset Reset when brownout (V
Key entry reset Reset whe
Watchdog timer reset Reset when the watchdog timer overflows (can be enabled/disabled using a register).
Supply voltage detector reset
Interrupt
Non-maskable interrupt 4 systems (Reset, addres
Programmable interrupt External interrupt: 1 system (8 levels)
Power supply voltage
V
DD operating voltage 2.0 to 3.6 V
Operating temperature
Operating temperature range -20 to 70 °C
Current consumption
SLEEP mode 0.35 µA
HALT mode 0.78 µA
RUN mode 11.9 µA
Shipping form
1 TQFP13-64pin (Lead pitch: 0.5 mm)
2 Chip (Pad pitch: 90 µm)
*1
When using the EPD timing controller (EPD Tcon), an area for storing the timing parameters must be allocated in the Flash memory.
When using the internal Flash voltage booster as the Flash programing power supply, an area for storing the control program
must be allocated
in the Flash memory.
Generates NMI or watchdog timer reset.
Generates the SPI master clocks. (Ch.1 to Ch.3)
128–1 Hz counter
CT, and RTC clocks)
Supports correcti
on value alteration according to temperature variations.
PWM output, event counter, and count capture functions
Generates an interrupt or reset according to the detection level evaluation.
n the P00 to P01/P02/P03 keys are pressed simultaneously (can be en-
DD = 1.45 V typ.) is detected.
abled/disabled using a register).
Reset when
the supply voltage detector
detects the set voltage level (can be enabled/
disabled using a register).
s misaligned interrupt, debug, NMI)
Internal interrupt: 19 systems (8 levels)
OSC1 = OFF, RTC = OFF, OSC3B = OFF, OSC3A = OFF
OSC1 = 32 kHz (OSC1A), RTC = OFF, OSC3B = OFF, OS
C3A = OFF
0.80 µA
OSC1 = 32 kHz (OSC1A), RTC = ON, OSC3B = OFF, OSC3A = OFF
OSC1 = 32 kHz (OSC1A), RTC = OFF, OSC3B = OFF, OSC3A = OFF
5.43 mA
OSC1 = OFF, RTC = OFF, OSC3B = OFF, OSC3A = 20 MHz ceramic
5.50 mA
OSC1 = OFF, RTC = OFF, OSC3B = 20 MHz, OSC3A = OFF
1-2
Seiko Epson Corporation S1C17F13 TECHNICAL MANUAL
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1 OVERVIEW
OSC3B
oscillator
OSC1B
oscillator
OSC1A
oscillator
EXOSC
input circuit
Clock generator
(CLG)
Power-on reset
(POR)
Brownout reset
(BOR)
Power generator
(PWG)
System reset controller
(SRC)
V
DD
V
SS
V
D1
V
OSC
V
PP
C1N, C1P, C
1H
C2N, C
2P
IREF_M
FOUT
OSC1
OSC2
OSC3
OSC4
EXOSC
#RESET
OSC3A
oscillator
CPU core & debugger
(S1C17)
Internal RAM
6K bytes
System clock Interrupt request
Interrupt signal
DCLK
DSIO
DST2
32-bit RAM bus
Internal RAM
14K bytes
32-bit RAM bus
Instruction bus
16-bit internal bus
SDA0
SCL0
EXSVD
P00–07,
P10–17,
P20–27,
P30–37,
P40–41,
PD0–D2
Interrupt
controller
(ITC)
I/O port
(PPORT)
Watchdog timer
(WDT)
Clock timer
(CT)
Real-time clock
(RTC)
Theoretical
Regulation
(TR)
I2C
(I2C)
Temperature
detection circuit
(TEM)
R/F converter
(RFC)
Ch.0–1
Supply voltage
detector
(SVD)
16-bit timer
(T16)
Ch.0–3
EXCL0–1
TOUTA0/CAPA0–1
TOUTB0/CAPB0–1
SDI0, 2
SDO0, 2
SPICLK0, 2
#SPISS0, 2
RFIN0–1
REF0–1
SENA0–1
SENB0–1
RFCLKO0–1
VM1–2
Synchronous
serial interface
(SPI)
Ch.0, 2
SDI1
SDO1
SPICLK1
#SPISS1
REGMON
Synchro-
nous serial
interface
(SPI) Ch.1
PIOA[7:0]
PIOD[7:0]
#PIOCE
#PIORD
#PIOWR
Parallel
interface
(PIO)
16-bit PWM timer
(T16A3)
Ch.0–1
USIN0
USOUT0
UART
(UART)
EPD timing
controller
(EPD Tcon)
Flash memory
128K bytes
Block Diagram1.2
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
(Rev. 1.0)
2.1 S1C17F13 Block DiagramFigure 1.
1-3
Page 17
1 OVERVIEW
123456789101112131415
16
484746454443424140393837363534
33
P31
P32
P33
V
DD
VSS
P34
P35
P36
P37
P40
P41
PD0
PD1
PD2
P00
P01
P32/TOUTB1/CAPB1/PIOA0
P33/TOUTA1/CAPA1/PIOA1
V
DD
VSS
P34/USIN0/PIOA2
P35/USOUT0/PIOA3
P36/SCL0/PIOD0
P37/SDA0/PIOD1
P40/USIN0/PIOD2
P41/USOUT0/PIOD3
DST2/PD0
DSIO/PD1
DCLK/PD2
P00/TOUTA0/CAPA0/FOUT
P01/TOUTB0/CAPB0/#PIOWR
V
SS
TEST
P13
P12
P11
P10
IREF_M
V
OSC
VM1
VM2
OSC2
OSC1
OSC4
OSC3
VDD#RESET
V
SS
TEST
P13/RFIN0/PIOA7
P12/REF0/PIOA6
P11/SENA0/PIOA5
P10/SENB0/PIOA4
IREF_M
V
OSC
VM1
VM2
OSC2
OSC1
OSC4
OSC3
VDD#RESET
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin name
P14
P15
P16
P17
V
SS
P20
P21
P22
P23
V
DD
P24
P25
P26
P27
P30
V
SS
Port function or signal assignment
P14/SENB1/PIOD0
P15/SENA1/PIOD1
P16/REF1/PIOD2
P17/RFIN1/PIOD3
V
SS
P20/SDO1/PIOD4
P21/SDI1/PIOD5
P22/SPICLK1/PIOD6
P23/#SPISS1/PIOD7
V
DD
P24/#SPISS2
P25/SPICLK2
P26/SDI2
P27/SDO2
P30/EXCL1/RFCLKO0
V
SS
VSS
VD1
P07
P06
P05
P04
P03
P02
V
PP
C
2P
C2N
C1H
C1P
C1N
VDD
VSS
VSS
VD1
P07/SDO0/PIOA3
P06/SDI0/PIOA2
P05/SPICLK0/PIOA1
P04/#SPISS0/PIOA0
P03/EXOSC/#PIOCE
P02/EXCL0/#PIORD
V
PP
C
2P
C2N
C1H
C1P
C1N
VDD
VSS
Pins1.3
Pin Configuration Diagram (TQFP13-64pin)1.3.1
3.1.1 S1C17F13 Pin Configuration Diagram (TQFP13-64pin)Figure 1.
1-4
Seiko Epson Corporation S1C17F13 TECHNICAL MANUAL
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1 OVERVIEW
Die No. CJF13Dxxx
1
234567891011121314151617181920
21
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
57565554535251
5049484746454443424140
39
Pad
name
P14
P15
P16
P17
V
SS
VSS
N.C.
P20
P21
P22
P23
V
DD
P24
P25
P26
P27
N.C.
P30
N.C.
V
SS
VSS
Port function or
signal assignment
P14/SENB1/PIOD0
P15/SENA1/PIOD1
P16/REF1/PIOD2
P17/RFIN1/PIOD3
V
SS
VSS
–
P20/SDO1/PIOD4
P21/SDI1/PIOD5
P22/SPICLK1/PIOD6
P23/#SPISS1/PIOD7
V
DD
P24/#SPISS2
P25/SPICLK2
P26/SDI2
P27/SDO2
–
P30/EXCL1/RFCLKO0
–
V
SS
VSS
P31
P32
P33
V
DD
VSS
P34
P35
P36
N.C.
P37
P40
P41
PD0
PD1
N.C.
PD2
N.C.
N.C.
N.C.
P00
P01
P31/REGMON/RFCLKO1/EXSVD
P32/TOUTB1/CAPB1/PIOA0
P33/TOUTA1/CAPA1/PIOA1
VDD
VSS
P34/USIN0/PIOA2
P35/USOUT0/PIOA3
P36/SCL0/PIOD0
–
P37/SDA0/PIOD1
P40/USIN0/PIOD2
P41/USOUT0/PIOD3
DST2/PD0
DSIO/PD1
–
DCLK/PD2
–––
P00/TOUTA0/CAPA0/FOUT
P01/TOUTB0/CAPB0/#PIOWR
VSS
V
D1
N.C.
P07
P06
P05
P04
P03
P02
V
PP
C2P
C2N
C1H
C1P
C1N
VDD
VSS
VSS
V
D1
–
P07/SDO0/PIOA3
P06/SDI0/PIOA2
P05/SPICLK0/PIOA1
P04/#SPISS0/PIOA0
P03/EXOSC/#PIOCE
P02/EXCL0/#PIORD
V
PP
C2P
C2N
C1H
C1P
C1N
VDD
VSS
VSSTEST
N.C.
P13
P12
P11
P10
IREF_M
V
OSC
VM1
VM2
OSC2
OSC1
VSSOSC4
OSC3
N.C.
VDD#RESET
V
SS
TEST–P13/RFIN0/PIOA7
P12/REF0/PIOA6
P11/SENA0/PIOA5
P10/SENB0/PIOA4
IREF_M
V
OSC
VM1
VM2
OSC2
OSC1
VSSOSC4
OSC3–VDD#RESET
Y
X
(0, 0)
3.279 mm
3.339 mm
Pad Configuration Diagram (Chip)1.3.2
3.2.1 S1C17F13 Pad Configuration Diagram (Chip)Figure 1.
Pad opening No. 1–21, 39–57: X = 76 µm, Y = 90 µm
No. 22–29: X = 85 µm, Y = 122 µm
No. 30–38, 58–78: X = 90 µm, Y = 76 µm
Chip thickness 400 µm
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
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1 OVERVIEW
3.2.1 Pad CoordinatesTable 1.
No. X [µm] Y [µm] No. X [µm] Y [µm] No. X [µm] Y [µm] No. X [µm] Y [µm]
1 -1275.0 -1548.6 22 1581.1 -1126.7 39 1201.3 1548.6 58 -1578.6 1070.0
2 -690.0 -1548.6 23 1581.1 -986.7 40 1101.3 1548.6 59 -1578.6 970.0
3 -600.0 -1548.6 24 1581.1 -846.7 41 1006.3 1548.6 60 -1578.6 870.0
4 -510.0 -1548.6 25 1581.1 -706.7 42 826.3 1548.6 61 -1578.6 770.0
5 -420.0 -1548.6 26 1581.1 -566.7 43 736.3 1548.6 62 -1578.6 680.0
6 -330.0 -1548.6 27 1
7 -240.0 -1548.6 28 1581.1 -286.7 45 556.3 1548.6 64 -1578.6 500.0
8 -150.0 -1548.6 29 1581.1 -146.7 46 466.3 1548.6 65 -1578.6 410.0
9 -60.0 -1548.6 30 1578.6 75.0 47 376.3 1548.6 66 -1578.6 320.0
10 30.0 -1548.6 31 1578.6 165.0 48 286.3 1548.6 67 -1578.6 230.0
11 120.0 -1548.6 32 1578.6 255.0 49 196.3 1548.6 68 -1578.6 140.0
12 210.0 -1548.6 33 1578.6 345.0 50 106.3 1548.6 6
13 300.0 -1548.6 34 1578.6 435.0 51 -630.0 1548.6 70 -1578.6 -130.0
14 480.0 -1548.6 35 1578.6 525.0 52 -730.0 1548.6 71 -1578.6 -220.0
15 660.0 -1548.6 36 1578.6 615.0 53 -830.0 1548.6 72 -1578.6 -310.0
16 750.0 -1548.6 37 1578.6 1071.3 54 -930.0 1548.6 73 -1578.6 -400.0
17 840.0 -1548.6 38 1578.6 1171.3 55 -1020.0 1548.6 74 -1578.6 -580.0
18 930.0 -1548.6 – – – 56 -1110.0 1548.6 75 -1578.6 -670.0
19 1020.0 20 1110.0 -1548.6 – – – – – – 77 -1578.6 -850.0
21 1200.0 -1548.6 – – – – – – 78 -1578.6 -940.0
1548.6 – – – 57 -1290.0 1548.6 76 -1578.6 -760.0
581.1 -426.7 44 646.3 1548.6 63 -1578.6 590.0
9 -1578.6 50.0
Pin Descriptions1.3.3
Symbol meanings
Assigned signal: The signal listed at the top of each pin is assigned in the initial state. The pin function must be
switched via software to assign another signal (see the “I/O Ports” chapter).
I/O: I = Input
O = Output
I/O = Input/output
P = Power supply
A = Analog signal
Hi-Z = High impedance state
Initial state: I (Pull-up) = Input with pulled up
I (Pull-down) = Input with pulled down
Hi-Z = High impedance state
O (H) = High level output
O (L) = Low level output
3.3.1 Pin descriptionTable 1.
Pin/pad
name
Assigned signal I/O Initial state
VDD VDD P – – Power supply (+)
V
SS VSS P – – GND
V
D1 VD1 A – –
VOSC VOSC A – –
VPP VPP P – –
C1N C1N A – – Capacitor connect pin for Flash voltage booster
C
1P C1P A – – Capacitor connect pin for Flash voltage booster
C
1H C1H A – – Capacitor connect pin for Flash voltage booster
C
2N C2N A – – Capacitor connect pin for Flash voltage booster
C
2P C2P A – – Capacitor connect pin for Flash voltage booster
IREF_M IREF_M A – – IREF constant current monitor pin
VM1 VM1 A – – Temperature sensor voltage monitor pin
VM2 VM2 A – – Temperature sensor voltage monitor pin
OSC1 OSC1 A – – OSC1A oscillator circuit input
Tolerant
fail-safe
structure
Function
Embedded regulator output (internal circuit operating voltage)
Embedded regulator output (oscillator circuit operating voltage)
Flash programming power supply
(Leave the pin open during normal operation.)
(Leave the pin open during normal operation.)
(Leave the pin open during normal operation.)
(Leave the pin open during normal operation.)
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1 OVERVIEW
Pin/pad
name
Assigned signal I/O Initial state
Tolerant
fail-safe
structure
Function
OSC2 OSC2 A – – OSC1A oscillator circuit output
OSC3 OSC3 A – – OSC3A oscillator circuit input
OSC4 OSC4 A – – OSC3A oscillator circuit output
#RESET #RESET I I (Pull-up) – Reset input
TEST TEST I I (Pull-down) – Test input
P00 P00 I/O Hi-Z
TOUTA0/CAPA0 I/O
(TBD)
General-purpose I/O port
✓
16-bit PWM timer Ch.0 TOUTA signal output/capture A trigger
(Connect to VSS during normal operation.)
signal input
FOUT O Clock generator clock output
P01 P01 I/O Hi-Z
TOUTB0/CAPB0 I/O
(TBD)
General-purpose I/O port
✓
16-bit PWM timer Ch.0 TOUTB signal output/capture B trigger
signal input
#PIOWR O Parallel interface write signal output
P02 P02 I/O Hi-Z
EXCL0 I 16-bit PWM timer Ch.0 external clock input
(TBD)
General-purpose I/O port
✓
#PIORD O Parallel interface read signal output
P03 P03 I/O Hi-
EXOSC I Clock generator external clock input
(TBD)
Z
General-purpose I/O port
✓
#PIOCE O Parallel interface chip enable signal output
P04 P04 I/O Hi-Z
#SPISS0 I Synchronous serial interface Ch.0 slave select input
(TBD)
General-purpose I/O port
✓
PIOA0 O Parallel interface address output
P05 P05 I/O Hi-Z
General-purpose I/O port
✓
SPICLK0 I/O Synchronous serial interface Ch.0 clock input/output
PIOA1 O Parallel interface address o
P06 P06 I/O Hi-Z
General-purpose I/O port
✓
utput
SDI0 I Synchronous serial interface Ch.0 data input
PIOA2 O Parallel interface address output
P07 P07 I/O Hi-Z
General-purpose I/O port
✓
SDO0 O Synchronous serial interface Ch.0 data output
PIOA3 O Parallel interface address output
P10 P10 I/O Hi-Z
General-purpose I/O port
–
SENB0 A R/F converter Ch.0 sensor B oscillation control
PIOA4 O Parallel interface address output
P11 P11 I/O Hi
-Z
General-purpose I/O port
–
SENA0 A R/F converter Ch.0 sensor A oscillation control
PIOA5 O Parallel interface address output
P12 P12 I/O Hi-Z
General-purpose I/O port
–
REF0 A R/F converter Ch.0 reference oscillation control
PIOA6 O Parallel interface address output
P13 P13 I/O Hi-Z
General-purpose I/O port
–
RFIN0 A R/F converter Ch.0 oscillation input
PIOA7 O Parallel interface address output
P14 P14 I/O Hi-Z
General-purpose I/O port
–
SENB1 A R/F converter Ch.1 sensor B oscillation control
PIOD0 I/O Parallel interface data input/output
P15 P15 I/O Hi-Z
General-purpose I/O port
–
SENA1 A R/F converter Ch.1 sensor A oscillation control
PIOD1 I/O Parallel interface data input/output
P16 P16 I/O Hi-Z
General-purpose I/O port
–
REF1 A R/F converter Ch.1 reference oscillation control
PIOD2 I/O Parallel interface data input/output
P17 P17 I/O Hi-Z
General-purpose I/O port
–
RFIN1 A R/F converter Ch.1 oscillation input
PIOD3 I/O Parallel interface data input/output
P20 P20 I/O Hi-Z
General-purpose I/O port
✓
SDO1 O Synchronous serial interface Ch.1 data output
PIOD4 I/O Parallel interface data input/output
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1 OVERVIEW
Pin/pad
name
Assigned signal I/O Initial state
P21 P21 I/O Hi-Z
SDI1 I Synchronous serial interface Ch.1 data input
PIOD5 I/O Parallel interface data input/output
P22 P22 I/O Hi-Z
SPICLK1 I/O Synchronous serial interface Ch.1 clock input/output
PIOD6 I/O Parallel interface data input/output
P23 P23 I/O Hi-Z
#SPISS1 I
PIOD7 I/O Parallel interface data input/output
P24 P24 I/O Hi-Z
#SPISS2 I Synchronous serial interface Ch.2 slave select input
P25 P25 I/O Hi-Z
SPICLK2 I/O Synchronous serial interface Ch.2 clock input/output
P26 P26 I/O Hi-Z
SDI2 I Synchronous serial interface Ch.2 data input
P27 P27 I/O Hi-Z
SDO2 O Synchronous serial interface Ch.2 data output
P30 P30 I/O Hi-Z
EXCL1 I 16-bit PWM timer Ch.1 external clock input
RFCLKO0 O R/F converter Ch.0 clock monitor output
P31 P31 I/O Hi-Z
REGMON O Theoretical regulation clock monitor output
RFCLKO1 O R/F converter Ch.1 clock monitor output
EXSVD A External power supply voltage detection input
P32 P32 I/O Hi-
Z
TOUTB1/CAPB1 I/O
PIOA0 O Parallel interface address output
P33 P33 I/O Hi-Z
TOUTA1/CAPA1 I/O
PIOA1 O Parallel interface address output
P34 P34 I/O Hi-Z
USIN0 I UART Ch.0 data input
PIOA2 O Parallel inter
P35 P35 I/O Hi-Z
USOUT0 O UART Ch.0 data output
PIOA3 O Parallel interface address output
P36 P36 I/O Hi-Z
SCL0 I/O I
PIOD0 I/O Parallel interface data input/output
P37 P37 I/O Hi-Z
SDA0 I/O I
PIOD1 I/O Parallel interface data input/output
P40 P40 I/O Hi-Z
USIN0 I U
PIOD2 I/O Parallel interface data input/output
P41 P41 I/O Hi-Z
USOUT0 O UART Ch.0 data output
PIOD3 I/O Parallel interface data input/output
PD0 DST2 O O (L)
PD0 I/O General-purpose I/O port
PD1 DSIO I/O I (pull-up)
PD1 I/O General-purpose I/O port
PD2 DCLK O O (H)
PD2 O General-purpose I/O
Tolerant
fail-safe
structure
✓
✓
✓
✓
✓
✓
✓
✓
–
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
Function
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
Synchronous serial interface Ch.1 slave select input
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
16-bit PWM timer Ch.1 TOUTB signal output/capture B trigger
signal input
General-purpose I/O port
16-bit PWM timer Ch.1 TOUTA signal output/capture A trigger
signal input
General-purpose I/O port
face address output
General-purpose I/O port
General-purpose I/O port
2
C Ch.0 clock input/output
General-purpose I/O port
2
C Ch.0 data input/output
General-purpose I/O port
ART Ch.0 data input
General-purpose I/O port
On-chip debugger status output
On-chip debugger data input/output
On-chip debugger clock output
port
Note: In the peripheral circuit descriptions, the assigned signal name is used as the pin name.
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2 POWER SUPPLY, RESET, AND CLOCKS
PWG
Internal logic and
high-speed oscillator
circuits
Low-speed
oscillator circuit
VD1
regulator
VDD
VD1
VD1
VSS
VD1ECO
VOSC
regulator
VOSC
VOSC
Flash voltage
booster
C1P
VPP
C1N
C1H
C2P
C2N
Flash memory
CPW1
CPW2
CPW3
CPW4
CPW5
CPW6
VSS
VDD
VSS
VPP
CPW7
Power Supply, Reset, and Clocks2
The power supply, reset, and clocks in this IC are managed by the embedded power generator, system reset controller, and clock generator, respectively.
Power Generator (PWG)2.1
Overview2.1.1
PWG is the power generator that controls the internal power supply system to drive this IC with stability and low
power. The main features of PWG are outlined below.
• Embed
• Embedded V
• Embedded voltage booster for generating the Flash erasing/programming voltage
ded VD1 regulator
- The V
- The V
D1 regulator generates the VD1 voltage to drive internal circuits, this makes it possible to keep current
consumption constant independent of the V
D1 regulator supports two operation modes, normal mode and economy mode, and setting the VD1 regu-
DD voltage level.
lator into economy mode at light loads helps achieve low-power operations.
OSC regulator
- The V
OSC regulator drives the low-speed oscillator circuit in low power consumption and achieves stabilized
low-speed clock that is used for timers such as RTC.
Figure 2.1.1.1 shows the PWG configuration.
1.1.1 PWG ConfigurationFigure 2.
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2 POWER SUPPLY, RESET, AND CLOCKS
Pins2.1.2
Table 2.1.2.1 lists the PWG pins.
1.2.1 List of PWG PinsTable 2.
Pin name I/O Initial status Function
VDD P – Power supply (+)
V
SS P – GND
V
D1 A –
VOSC A –
VPP P –
C1P, C1N, C1H, C2P, C2N A – Capacitor connect pins for Flash voltage booster
Embedded regulator output (internal circuit operating voltage)
Embedded regulator output (oscillator circuit operating voltage)
Flash programming power supply
(Leave the pin open during normal operation.)
For the VDD operating voltage range and recommended external parts, refer to “Recommended Operating Conditions, Power supply voltage V
DD” in the “Electrical Characteristics” chapter and the “Basic External Connection
Diagram” chapter, respectively.
V2.1.3 D1 Regulator
The VD1 regulator generates the operating voltage for the internal logic and high-speed oscillator circuits. This
regulator always operates. The V
Setting the V
D1 regulator into economy mode at light loads helps achieve low-power operations. Table 2.1.3.1 lists
examples of light load conditions in which economy mode can be set.
1.3.1 Examples of Light Load Conditions in which Economy Mode Can be Set Table 2.
SLEEP mode (when all oscillators are stopped, or OSC1 only is active) When a clock source except for
HALT mode (when OSC1 only is active)
RUN mode (when OSC1 only is active)
D1 regulator supports two operation modes, normal mode and economy mode.
Light load condition Exceptions
OSC1 is active
The VD1 regulator also supports automatic mode in which the hardware detects a light load condition and automatically switches between normal mode and economy mode. Use the V
D1 regulator in automatic mode when no special
control is required.
V2.1.4 OSC Regulator
The VOSC regulator generates the operating voltage for the low-speed oscillator circuit. This regulator always operates.
Flash Programming Power Supply (V2.1.5 PP)
VPP is the power supply for erasing/programming the embedded Flash memory. The VPP voltage may be applied
from an external power supply to the V
PP pin or internally generated by the embedded Flash voltage booster (con-
trolled from the Flash programming function of the debugger or self-programming module).
For the V
internally, refer to “Recommended Operating Conditions, Flash programming voltage V
age V
Note: Leave the V
PP voltage value to be applied from an external power supply or the VDD requirements for generating VPP
PP and Power supply volt-
DD” in the “Electrical Characteristics” chapter.
PP pin open during normal operation.
System Reset Controller (SRC)2.2
Overview2.2.1
SRC is the system reset controller that resets the internal circuits according to the requests from the reset sources to
archive steady IC operations. The main features of SRC are outlined below.
• Embedded reset hold circuit maintains reset state to boot the system safely while
stable after power on or the oscillation frequency is unstable after the clock source is initiated.
the internal power supply is un-
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2 POWER SUPPLY, RESET, AND CLOCKS
Reset hold
circuit
SRC
#RESET
Key-entry reset
Watchdog timer reset
Supply voltage detector reset
Software reset 0
Software reset n
Internal reset signals
(Reset group)
SYSRST_H0
SYSRST_H1
SYSRST_S0_0
SYSRST_S0_n
To CPU and peripheral circuits
To CPU and peripheral circuits
To peripheral circuit 0
To peripheral circuit n
Noise filter
Reset
decoder
POR
BOR
Clock generator
Boot clock
OSC3BCLK
Reset request
signals
V
DD
VSS
• Supports reset requests from multiple reset sources.
- #RESET pin
- POR and BOR
- Key-entry reset
- Watchdog timer reset
- Supply voltage detector reset
- Peripheral circuit software reset (supports some peripheral circuits only)
• The CPU registers and peripheral circuit control bits will be reset with an appropriate initialization condition according to changes in status.
Figure 2.2.1.1 shows the SRC
configuration.
2.1.1 SRC ConfigurationFigure 2.
Input Pin2.2.2
Table 2.2.2.1 shows the SRC pin.
2.2.1 SRC PinTable 2.
Pin name I/O Initial status Function
#RESET I I (Pull-up) Reset input
The #RESET pin is connected to the noise filter that removes pulses not conforming to the requirements. An internal pull-up resistor is connected to the #RESET pin, so the pin can be left open. For the #RESET pin characteristics, refer to “#RESET pin characteristics” in the “Electrical Characteristics” chapter.
The reset source refers to causes that request system initialization. The following shows the reset sources.
#RESET pin
Inputting a reset signal with a certain low level period to the #RESET pin issues a reset request.
POR and BOR
POR (Power On Reset) issues a reset request when the rise of VDD is detected. BOR (Brownout Reset) issues
a reset request when a certain V
system will be reset properly when the power is turned on and the supply voltage is out of the operating voltage
range. Figure 2.2.3.1 shows an example of POR and BOR internal reset operation according to variations in V
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
(Rev. 1.0)
Reset Sources2.2.3
DD voltage level is detected. Reset requests from these circuits ensure that the
DD.
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2 POWER SUPPLY, RESET, AND CLOCKS
Internal state
VRST-: Reset detection voltage VRST+: Reset canceling voltage Indefinite (operating limit) RESET state CPU RUN state
X RST RU N
VDD
VSS
VRST- VRST- VRST-
VRST+
VRST+
X X XRST RSTRSTRST RU N RU N RUN
2.3.1 Example of Internal Reset by POR and BORFigure 2.
For the POR and BOR electrical specifications, refer to “POR/BOR characteristics” in the “Electrical Charac-
teristics” chapter.
Key-entry reset
Inputting a low level signal of a certain period to the I/O port pins configured to a reset input issues a reset re-
quest. This function must be enabled using an I/O port register. For more informatio
n, refer to the “I/O Ports”
chapter.
Watchdog timer reset
Setting the watchdog timer into reset mode will issue a reset request when the counter overflows. This helps return the runaway CPU to a normal operating state. For more information, refer to the “Watchdog timer” chapter.
Supply voltage detector reset
By enabling the low power supply voltage detection reset function, the supply voltage detector will issue a reset
request when a drop in the power supply voltage is detected. This makes it possible to put the system into reset
state if the IC must be stopped under a low voltage condition. For more information, refer to the “Supply Voltage Detector” chapter.
Peripheral circuit software reset
Some peripheral circuits provide a control bit for software reset (MODEN or SFTRST). Setting this bit initial-
izes the peripheral circuit control bits. Note, however, that the software reset operations depend on the peripheral circuit. For more information, refer to “Control Registers” in each peripheral circuit chapter.
Note: The MODEN bit of some peripheral circuits does not issue software reset.
Initialization Conditions (Reset Groups)2.2.4
A different initialization condition is set for the CPU registers and peripheral circuit control bits, individually. The
reset group refers to an initialization condition. Initialization is performed when a reset source included in a reset
group issues a reset request. Table 2.2.4.1 lists the reset groups. For the reset group to initialize the registers and
control bits, refer to the “CPU and Debugger” chapter or “Control Registers” in each periph
2.4.1 List of Reset GroupsTable 2.
Reset group Reset source Reset cancelation timing
H0 #RESET pin
POR and BOR
Supply voltage detector reset
Key-entry reset
Watchdog timer reset
H1 #RESET pin
POR and BOR
S0 Peripheral circuit software reset
(MODEN and SFTRST bits. The
software reset operations depend on the peripheral circuit.
Reset state is maintained for the reset
hold time t
canceled.
Reset state is canceled imme
after the reset request is canceled.
RSTR after the reset request is
eral circuit chapter.
diately
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2 POWER SUPPLY, RESET, AND CLOCKS
CLG
Internal data bus
OSC1BCLK
SYSCLK
SLEEP, WAKEUP
OSC1
OSC2
EXOSC
FOUT
OSC1EN OSC1SEL
CLKSRC[1:0]
CLKDIV[1:0]
WUPMD
CLKSRC[x:0]
CLKDIV[x:0]
WUPSRC[1:0]
WUPDIV[1:0]
FOUTDIV[2:0]
OSC1B
oscillator
circuit
Divider
Clock
selector
System
clock
controller
OSC1ACLK
F1 (1 [Hz])
F256 (1/256 [Hz])
OSC1CLK
X’tal1
OSC3BCLK
OSC3BEN
OSC3B
oscillator
circuit
OSC1A
oscillator
circuit
Divider
OSC3ACLK
OSC3AEN
OSC3A
oscillator
circuit
Divider
Divider
EXOSCCLK
EXOSCEN
EXOSC
clock input
circuit
FOUTEN
EXOSC
clock input
circuit
Clock
selector
Peripheral circuit 1
CLKSRC[x:0]
CLKDIV[x:0]
Clock
selector
Peripheral circuit n
To CPU and bu s
To some
p
eripheral circuits
OSC3
OSC4
X’tal3/Ceramic3
Theoretical regulation RTC reset
Clock Generator (CLG)2.3
Overview2.3.1
CLG is the clock generator that controls the clock sources and manages clock supply to the CPU and the peripheral
circuits. The main features of CLG are outlined below.
• Supports multiple clock sources.
- OSC3B oscillator circuit that oscillates with a fast startup and no external parts required
- Low-power OSC1B oscillator circuit that oscillates with no ext
- High-precision and low-power OSC1A oscillator circuit that uses a 32.768 kHz crystal resonator
- OSC3A oscillator circuit that supports high-speed crystal and ceramic resonators up to 20 MHz
- EXOSC clock input circuit that allows input of square wave and sine wave clock signals
• The system clock (SYSCLK), which is used as the operating clock for the CPU and bus, and the periph
cuit operating clocks can be configured individually by selecting the suitable clock source and division ratio.
• OSC3BCLK output from the OSC3B oscillator circuit is used as the boot clock for fast booting.
• Controls the oscillator and clock input circuits to enable/disable according to the operating mode, RUN or
SLEEP mode.
• Provides a flexible system clock switching function at SLEEP mo
- The clock sources to be stopped in SLEEP mode can be selected.
- SYSCLK to be used at SLEEP mode cancelation can be selected from all clock sources (OSC3B, OSC3A,
and EXOSC).
- The oscillator and clock input circuit on/off state can be maintained or changed at SLEEP mode cancelation.
• Provides the FOUT function to output an internal clock for driving external ICs or for monitoring t
state.
ernal parts required
eral cir-
de cancelation.
he internal
Figure 2.3.1.1 shows the CLG configuration.
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
(Rev. 1.0)
3.1.1 CLG ConfigurationFigure 2.
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2 POWER SUPPLY, RESET, AND CLOCKS
OSC3B oscillator circuit
Internal data bus
OSC3BEN
Clock
oscillator
Oscillation
stabilization
waiting circuit
Interrupt
control circuit
OSC3BSTAIE
OSC3BSTAIF
Interrupt
controller
OSC3BCLK
OSC3BFREQ[1:0]
OSC3A oscillator circuit
Gain-
controlled
oscillation
inverter
Feedback
resistor R
F3
Drain resistor RD3
OSC3AEN
Oscillation
stabilization
waiting circuit
Noise filter
Interrupt
control circuit
INVN[1:0]
OSC3AWT[1:0]
OSC3
OSC4
Interrupt
controller
OSC3ACLK
X’tal3/
Ceramic3
Internal data bus
OSC3ASTAIE OSC3ASTAIF
VSS
VDD
VDD
VSS
Gate capacitor
C
G3
Drain capacitor
C
D3
Input/Output Pins2.3.2
Table 2.3.2.1 lists the CLG pins.
3.2.1 List of CLG PinsTable 2.
Pin name I/O* Initial status* Function
OSC1 A – OSC1A oscillator circuit input
OSC2 A – OSC1A oscillator circuit output
OSC3 A – OSC3A oscillator circuit input
OSC4 A – OSC3A oscillator circuit output
EXOSC I I EXOSC clock input
FOUT O O (L) FOUT clock output
* Indicates the status when the pin is configured for CLG.
If the port is shared with the CLG input/output function and other functions, the CLG function must be assigned to
the port. For more information, refer to the “I/O Ports” chapter.
Clock Sources2.3.3
OSC3B oscillator circuit
The OSC3B oscillator circuit features a fast startup and no external parts are required for oscillating. Figure
2.3.3.1 shows the configuration of the OSC3B oscillator circuit.
The OSC3B oscillator circuit output clock OSC3BCLK is used as SYSCLK at booting.
The OSC3BCLK frequency can be selected using the CLGOSC3B.OSC3BFREQ[1:0] bits.
For more information on the oscillation characteristics, refer to “OSC3B oscillator circuit characteristics” in the
“Electrical Characteristics” chapter.
OSC3A oscillator circuit
The OSC3A oscillator circuit is a high-speed oscillator circuit that uses a crystal or ceramic resonator. Figure
2.3.3.2 shows the configuration of the OSC3A oscillator circuit.
A crystal resonator (X’tal3) or ceramic resonator (Ceramic3) should be connected between the OSC3 and OSC4
pins. Additionally, two capacitors (C
The embedded gain-controlled oscillation inverter allows selection of the resonator from a wide frequency range.
For the recommended
chapter and “OSC3A oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respectively.
2-6
Seiko Epson Corporation S1C17F13 TECHNICAL MANUAL
(Rev. 1.0)
parts and the oscillation characteristics, refer to the “Basic External Connection Diagram”
3.3.1 OSC3B Oscillator Circuit ConfigurationFigure 2.
3.3.2 OSC3A Oscillator Circuit ConfigurationFigure 2.
G3 and CD3) should be connected between the OSC3/OSC4 pins and VSS.
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2 POWER SUPPLY, RESET, AND CLOCKS
OSC1A oscillator circuit
OSC1 oscillator circuit
External gate
capacitor C
G1
Internal
gate capacitor C
GI1
Feedback
resistor R
F1
Drain
resistor R
D1
External drain
capacitor C
D1
Internal
drain capacitor C
DI1
V
SS
V
SS
OSC1EN
Oscillation
stabilization
waiting circuit
Interrupt
control circuit
OSC1WT[1:0]
OSC1WT[1:0]
OSC1
OSC2
X’tal1
OSC1STAIE
OSC1STAIF
Interrupt
controller
OSC1CLK
Internal data bus
OSC1B oscillator circuit
Clock
oscillator
Oscillation
stabilization
waiting circuit
OSC1BCLK
OSC1ACLK
OSC1SEL
Regulated
clock
generation
V
SS
V
DD
V
DD
V
SS
EXOSC clock
input circuit
Input control
circuit
EXOSCEN
EXOSC
EXOSCCLK
Internal data bus
OSC1 oscillator circuit
OSC1 is a low-power oscillator circuit that generates the timer operating clock and the system clock for low-
speed operations. The OSC1 oscillator circuit consists of two oscillators, OSC1A and OSC1B, and the oscillator to be used should be selected using the CLGOSC1.OSC1SEL bit. Figure 2.3.3.3 shows the configuration of
the OSC1 oscillator circuit.
3.3.3 OSC1 Oscillator Circuit ConfigurationFigure 2.
OSC1A oscillator circuit
The OSC1A oscillator circuit is a high-precision and low-power oscillator circuit that uses a 32.768 kHz
crystal resonator. A crystal resonator (X’tal1) should be connected between the OSC1 and OSC2 pins. Additionally, two capacitors (C
the recomme
nded parts and the oscillation characteristics, refer to the “Basic External Connection Dia-
G1 and CD1) should be connected between the OSC1/OSC2 pins and VSS. For
gram” chapter and “OSC1A oscillator circuit characteristics” in the “Electrical Characteristics” chapter,
respectively.
OSC1B oscillator circuit
The OSC1B oscillator circuit generates about 32 kHz clock without external components.
EXOSC clock input
EXOSC is an external clock input circuit that supports square wave and sine wave clocks. Figure 2.3.3.4 shows
the configuration of the EXOSC clock input circuit.
EXOSC has no oscillation stabilization waiting circuit included, therefore, it must be enabled when a stabilized
clock is being supplied. For the input clock characteristics, refer to “EXOSC external clock input characteristics” in the “Electrical Characteristics” chapter.
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
(Rev. 1.0)
3.3.4 EXOSC Clock Input CircuitFigure 2.
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Oscillator circuit enable
(∗OSC∗EN)
Oscillation waveform
Digitized oscillation waveform
Oscillator circuit output clock
(∗OSC∗CLK)
Oscillation stabilization waiting completion flag
(∗OSC∗STAIF)
System supply waiting time
Oscillation start time
Oscillation stabilization waiting time
Operations2.3.4
Oscillation start time and oscillation stabilization waiting time
The oscillation start time refers to the time after the oscillator circuit is enabled until the oscillation signal is ac-
tually sent to the internal circuits. The oscillation stabilization waiting time refers to the time it takes the clock
to stabilize after the oscillation starts. To avoid malfunctions of the inter
during this period, the oscillator circuit includes an oscillation stabilization waiting circuit that can disable supplying the clock to the system until the designated time has elapsed. Figure 2.3.4.1 shows the relationship between the oscillation start time and the oscillation stabilization waiting time.
3.4.1 Oscillation Start Time and Oscillation Stabilization Waiting TimeFigure 2.
nal circuits due to an unstable clock
The oscillation stabilization waiting times for the OSC1 (OSC1A and OSC1B) and OSC3A oscillator circuits
can be set using the CLGOSC1.OSC1WT[1:0] and CLGOSC3A.OSC3AWT[1:0] bits, respectively. Allow an
ample margin for the setting value according to the resonator type used. To check whether the oscillation stabiliza
tion waiting time is set properly and the clock is stabilized immediately after the oscillation starts or not,
monitor the oscillation clock using the FOUT output function. The oscillation stabilization waiting time for the
OSC3B oscillator circuit is fixed at 128 OSC3BCLK clocks.
When the oscillation stabilization waiting operation has completed, the oscillator circuit sets the oscillation sta-
bi
lization waiting completion flag and starts clock supply to the internal circuits.
Note: The oscillation stabilization waiting time is always expended at start of oscillation even if the os-
cillation stabilization waiting completion flag has not be cleared to 0.
Oscillation start procedure for the OSC3B oscillator circuit
Follow the procedure shown below to start oscillation of the OSC3B oscillator circuit.
1. Write 1 to the CLGINTF.OSC3BSTAIF bit. (Clear interrupt flag)
2. Write 1 to the CLGINTE.OSC3BSTAIE bit. (Enable interrupt)
3. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
4. Configure the CLGOSC3B.OSC3BFREQ bit. (Select frequency)
5. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
6. Write 1 to the CLGOSC.OSC3BEN bit. (Start osc
7. OSC3BCLK can be used if the CLGINTF.OSC3BSTAIF bit = 1 after an interrupt occurs.
Oscillation start procedure for the OSC3A oscillator circuit
Follow the procedure shown below to start oscillation of the OSC3A oscillator circuit.
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(Rev. 1.0)
1. Write 1 to the CLGINTF.OSC3ASTAIF bit. (Clear interrupt flag)
2. Write 1 to the CLGINTE.OSC3ASTAIE bit. (Enable interrupt)
3. Write 0x0096 to the MSCPROT.PROT[
4. Configure the following CLGOSC3A register bits according to the resonator used.
- CLGOSC3A.INVN[1:0] bits (Set oscillation inverter gain)
- CLGOSC3A.OSC3AWT[1:0] bits (Set oscillation stabilization waiting time)
Seiko Epson Corporation S1C17F13 TECHNICAL MANUAL
illation)
15:0] bits. (Remove system protection)
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2 POWER SUPPLY, RESET, AND CLOCKS
5. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
6. Write 1 to the CLGOSC.OSC3AEN bit. (Start oscillation)
7. OSC3ACLK can be used if the CLGINTF.OSC3ASTAIF bit = 1 after an interrupt occurs.
The setting values of the CLGOSC3A.INVN[1:0] and CLGOSC3A.OSC3AWT[1:0] bits should be determined
after performing evaluation using the populated circuit board.
Oscillation start procedure for the OSC1B oscillator circuit
Follow the procedure shown below to start oscillation of the OSC1B oscillator circuit.
1. Write 1 to the CLGINTF.OSC1STAIF bit. (Clear interrupt flag)
2. Write 1 to the CLGINTE.OSC1STAIE bit. (Enable interrupt)
3. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
4. Configure the following CLGOSC1 register bits:
- CLGOSC1.OSC1WT[
1:0] bits (Set oscillation stabilization waiting time)
- Set the CLGOSC1.OSC1SEL bit to 1. (Select OSC1B)
5. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
6. Write 1 to the CLGOSC.OSC1EN bit. (Start oscillation)
7. OSC1CLK can be used if the CLGINTF.OSC1STAIF bit = 1 after an interrupt occurs.
Oscillation start procedure for the OSC1A oscillator circuit
Follow the procedure shown below to start oscillation of the OSC1A oscillator circuit.
1. Write 1 to the CLGINTF.OSC1STAIF bit. (Clear interrupt flag)
2. Write 1 to the CLGINTE.OSC1STAIE bit. (Enable interrupt)
3. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
4. Configure the following CLGOSC1 register bits according to the resonator used:
- CLGOSC1.OSC1WT[1:0] bits (Set oscillation
- Set the CLGOSC1.OSC1SEL bit to 0. (Select OSC1A)
5. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
6. Write 1 to the CLGOSC.OSC1EN bit. (Start oscillation)
7. OSC1CLK can be used if the CLGINTF.OSC1STAIF bit = 1 after an interrupt occurs.
stabilization waiting time)
The setting value of the CLGOSC1.OSC1WT[1:0] bits should be determined after performing evalua
tion using
the populated circuit board.
System clock switching
The CPU boots using OSC3BCLK as SYSCLK. After booting, the clock source of SYSCLK can be switched
according to the processing speed required
. The SYSCLK frequency can also be set by selecting the clock
source division ratio, this makes it possible to run the CPU at the most suitable performance for the process to
be executed. The CLGSCL
K.CLKSRC[1:0] and CLGSCLK.CLKDIV[1:0] bits are used for this control. The
CLGSCLK register bits are protected against writings by the system protect function, therefore, the system protection must be removed by writing 0x0096 to the MSCPROT.PROT[15:0] bits before the register setting can
be altered. For the transition between the operating modes including the system clock switching, refer to “Ope
r-
ating Mode.”
Clock control in SLEEP mode
The CPU enters SLEEP mode when it executes the slp instruction. Whether the clock sources being operated
are stopped or not at this point can be selected in each source individually. This allows the CPU to fast switch
between SLEEP mode and RUN mode, and the peripheral circuits to continue operating without disabling the
clock in SLEEP mode. The CLGOSC.OSC
CLGOSC.EXOSCSLPC bits are used for this control. Figure 2.3.4.2 shows a control example.
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
(Rev. 1.0)
3BSLPC, CLGOSC.OSC1SLPC, CLGOSC.OSC3ASLPC, and
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OSC3BCLK
(Unstable)
OSC1CLK
(Unstable)
(1) When the CLGOSC.OSC1SLPC bit = 1
SYSCLK
(CPU operating clock)
SLEEP mode
(CPU stop, CLK stop)
Executing the
slp instruction
Interrupt
(Wake-up)
Oscillation stabilization waiting time
OSC3BCLK OSC3BCLK
OSC3BCLK
(Unstable)
Timer
operating clock
(CLK stop)
∗ The timer is turned off in
SLEEP mode as the clock stops.
OSC1CLK OSC1CLK
(2) When the CLGOSC.OSC1SLPC bit = 0
SYSCLK
(CPU operating clock)
SLEEP mode
(CPU stop, CLK stop)
Executing the
slp instruction
Interrupt
(Wake-up)
OSC3BCLK OSC3BCLK
Timer
operating clock
∗ The timer continues operating in
SLEEP mode as the clock is being supplied.
OSC1CLK
(1) When the CLGSCLK.WUPMD bit = 0
SYSCLK
(CPU operating clock)
SLEEP mode
(CPU stop, CLK stop)
Executing the
slp instruction
Interrupt
(Wake-up)
OSC3BCLK OSC3BCLK
∗ Starting up with the same clock as one
that used before SLEEP mode was entered.
(2) When the CLGSCLK.WUPMD bit = 1 and the CLGSCLK.WUPSRC[1:0] bits = 0x0
SYSCLK
(CPU operating clock)
SLEEP mode
(CPU stop, CLK stop)
Executing the
slp instruction
Interrupt
(Wake-up)
OSC1CLK OSC3BCLK
∗ Switching to OSC3B that features fast
initiation allows high-speed processing.
OSC3BCLK
(Unstable)
Oscillation stabilization waiting time
OSC3BCLK
(Unstable)
CLGSCLK.CLKSRC[1:0] = 0x1 (OSC1)
CLGSCLK.WUPSRC[1:0] = 0x0 (OSC3B)
CLGSCLK.CLKSRC[1:0] = 0x0 (OSC3B)
CLGSCLK.WUPSRC[1:0] = 0x0 (OSC3B)
CLGSCLK.CLKSRC[1:0] = 0x0 (OSC3B)
CLGSCLK.WUPSRC[1:0] = 0x0 (OSC3B)
3.4.2 Clock Control Example in SLEEP ModeFigure 2.
The SYSCLK condition (clock source and division ratio) at wake-up from SLEEP mode to RUN mode can also
be configured. This allows flexible clock control according to the wake-up process. Configure the clock using
the CLGSCLK.WUPSRC[1:0] and CLGSCLK.WUPDIV[1:0] bits, and write 1 to the CLGSCLK.WUPMD bit
to enable this function.
3.4.3 Clock Control Example at SLEEP CancelationFigure 2.
Note: When OSC1 (OSC1A or OSC1B) is configured to stop in SLEEP mode (CLGOSC.OSC1SLPC
bit = 1), executing the slp instruction while a timer is running with OSC1 as the clock source will
destabilize the timer operation at restarting from SLEEP mode. When switching to SLEEP mode
with CLGOSC.OSC1SLPC bit set to 1, stop the timer before executing
not necessary to stop the timer when OSC1 is configured to operate in SLEEP mode.
Clock external output (FOUT)
The FOUT pin can output the clock generated by a clock source or its divided clock to outside the IC. This al-
lows monitoring the oscillation frequency of the oscillator circuit or supplying an operating clock to external
ICs. Follow the procedure shown below to
1. Assign the FOUT function to the port. (Refer to the “I/O Ports” chapter.)
2. Configure the following CLGFOUT register bits:
- CLGFOUT.FOUTSRC[1:0] bits (Select clock source)
- CLGFOUT.FOUTDIV[2:0] bits (Set clock division ratio)
- Set the CLGFOUT.FOUTEN bit to 1. (Enable clock external output)
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start clock external output.
the slp instruction. It is
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2 POWER SUPPLY, RESET, AND CLOCKS
VDD
Reset request from POR and BOR
OSC3BCLK
(Initial SYSCLK)
Internal reset signal
SYSRST, H0, H1
S1C17 core
program counter (PC)
Cancel reset request
Undefined
Undefined
∗1
∗1: Reset vector (reset handler start address)
∗2: Address (reset vector + 2)
∗2
Cancel reset request
Reset hold time t
RSTR
Operating Mode2.4
Initial Boot Sequence2.4.1
Figure 2.4.1.1 shows the initial boot sequence after power is turned on.
4.1.1 Initial Boot SequenceFigure 2.
Note: The reset cancelation time at power-on varies according to the power rise time and reset request
cancelation time.
For the reset hold time t
Transition between Operating Modes2.4.2
State transitions between operating modes shown in Figure 2.4.2.1 take place in this IC.
RUN mode
RUN mode refers to the state in which the CPU is executing the program. A transition to this mode takes place
when the system reset request from the system reset controller is canceled. RUN mode is classified into “OSC3B
RUN,” “OSC1 RUN,” “OSC3A RUN,” and “EXOSC RUN” by the SYSCLK clock source.
HALT mode
When the CPU executes the halt instruction, it suspends program execution and stops operating. This state is
HALT mode. In this mode, the clock sources and peripheral circuits keep operating. This mode can be set while
no software processing is required and it reduces power consumption as compared with RUN mode. HALT
mode is classified into “OSC3B HALT,” “OSC1 HALT,” “OSC3A HALT,” and “EXOSC HALT” by the SYSCLK clock source.
SLEEP mode
When the CPU executes the slp instruction, it suspends program execution and stops operating. This state is
SLEEP mode. In this mode, the clock sources stop operating as well. However, the clock source in which the
CLGOSC.OSC3BSLPC/OSC1SLPC/OSC3ASLPC/EXOSCSLPC bit is set to 0 keeps operating, so the peripheral circuits with the clock being supplied can also operate. By setting this mode when no software processing
and peripheral circuit
Note: The current consumption when a clock source is active in SLEEP mode by setting the CLGOSC.
OSC3BSLPC/OSC1SLPC/OSC3ASLPC/EXOSCSLPC bit to 0 is equivalent to the value in HALT
mode with the same clock source condition (refer to “Current Consumption, Current consumption in HALT mode I
DEBUG mode
When a debug interrupt occurs, the CPU enters DEBUG mode. DEBUG mode is canceled when the retd in-
struction is executed. For more information on DEBUG mode, refer to “Debugger” in the “CPU and Debugger”
chapter.
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
(Rev. 1.0)
RSTR, refer to “Reset hold circuit characteristics” in the “Electrical Characteristics” chapter.
operations are required, power consumption can be less than HALT mode.
HALT1– IHALT4” in the “Electrical Characteristics” chapter).
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2 POWER SUPPLY, RESET, AND CLOCKS
OSC3B
RUN
OSC1
RUN
OSC3B
HALT
OSC3A
HALT
OSC3A
RUN
RESET
(Initial state)
RUN/
HALT/
SLEEP
DEBUG
Tr ansition takes place automatically by the
initial boot sequence after a request from
the reset source is canceled.
∗ In RUN and HALT modes, the clock sources not used
as SYSCLK can be all disabled.
Interrupt
halt instruction
Debug interrupt
retd instruction
RUN SLEEP
slp instruction
Interrupt
(wake-up)
halt instruction
Interrupt
CLGSCLK.CLKSRC[1:0] = 0x1
CLGSCLK.CLKSRC[1:0] = 0x0
EXOSC
RUN
CLGSCLK.CLKSRC[1:0] = 0x2
CLGSCLK.CLKSRC[1:0] = 0x3
CLGSCLK.CLKSRC[1:0] = 0x1
CLGSCLK.CLKSRC[1:0] = 0x3
OSC1
HALT
halt instruction
Interrupt
EXOSC
HALT
Interrupt
halt instruction
CLGSCLK.CLKSRC[1:0] = 0x2
CLGSCLK.CLKSRC[1:0] = 0x0
CLGSCLK.CLKSRC[1:0] = 0x0
CLGSCLK.CLKSRC[1:0] = 0x3
CLGSCLK.CLKSRC[1:0] = 0x1
CLGSCLK.CLKSRC[1:0] = 0x2
4.2.1 Operating Mode-to-Mode State Transition Diagram Figure 2.
Canceling HALT or SLEEP mode
The conditions listed below cancel HALT or SLEEP mode and put the CPU into RUN mode.
• Interrupt request from the interrupt controller
• NMI from the watchdog timer
• Debug interrupt or address misaligned interrupt
• Reset request
Interrupts2.5
CLG has a function to generate the interrupts shown in Table 2.5.1.
5.1 CLG Interrupt FunctionTable 2.
Interrupt Interrupt flag Set condition Clear condition
OSC3B oscillation stabilization
waiting completion
OSC1 oscillation stabilization
waiting completion
OSC3A oscillation stabilization
waiting completion
CLGINTF.
OSC3BSTAIF
CLGINTF.
OSC1STAIF
CLGINTF.
OSC3ASTAIF
When the OSC3B oscillation stabilization waiting
operation has completed after the oscillation starts
When the OSC1 oscillation stabilization waiting operation has completed after the oscillation starts
When the OSC3A oscillation stabilization waiting
operation has completed after the oscillation starts
Writing 1
Writ
ing 1
Writing 1
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2 POWER SUPPLY, RESET, AND CLOCKS
CLG provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the interrupt
controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For
more information on interrupt control, refer to the “Interrupt Controller” chapter.
Control Registers2.6
PWG VD1 Regulator Control Register
Register name Bit Bit name Initial Reset R/W Remarks
PWGVD1CTL 15–8 – 0x00 – R –
7–2 – 0x00 – R
1–0 REGMODE[1:0] 0x0 H0 R/WP
Bits 15–2 Reserved
Bits 1–0 REGMODE[1:0]
These bits control the internal regulator operating mode.
6.1 Internal Regulator Operating ModeTable 2.
PWGVD1CTL.REGMODE[1:0] bits Operating mode
0x3 Economy mode
0x2 Normal mode
0x1 Reserved
0x0 Automatic mode
CLG System Clock Control Register
Register name Bit Bit name Initial Reset R/W Remarks
CLGSCLK 15 WUPMD 0 H0 R/WP –
14 – 0 – R
13–12 WUPDIV[1:0] 0x0 H0 R/WP
11–10 – 0x0 – R
9–8 WUPSRC[1:0] 0x0 H0 R/WP
7–6 – 0x0 – R
5–4 CLKDIV[1:0] 0x0 H0 R/WP
3–2 – 0x0 – R
1–0 CLKSRC[1:0] 0x0 H0 R/WP
Bit 15 WUPMD
This bit enables the SYSCLK switching function at wake-up.
1 (R/WP): Enable
0 (R/WP): Disable
When the CLGSCLK.WUPMD bit = 1, setting values of the CLGSCLK.WUPSRC[1:0] bits and the
CLGSCLK.WUPDIV[1:0] bits are loaded to the CLGSCLK.CLKSRC[1:0] bit
CLKDIV[1:0] bits, respectively, at wake-up from SLEEP mode to switch SYSCLK. When the CLGSCLK.WUPMD bit = 0, the CLGSCLK.CLKSRC[1:0] and CLGSCLK.CLKDIV[1:0] bits are not
altered at wake-up.
Note: When the CLGSCLK.WUPMD bit = 1, the clock source enable bits (CLGOSC.EXOSCEN, CL-
GOSC.OSC3AEN, CLGOSC.OSC1EN, CLGOSC.OSC3BEN) except for the SYSCLK source
selected by the CLGSCLK.CLKSRC[1:0] bits wil
l be cleared to 0 to stop the clocks after a
system wake-up. However, the enable bit of the clock source being operated during SLEEP
mode by setting the CLGOSC.****SLPC bit retains 1 after a wake-up.
Bit 14 Reserved
s and the CLGSCLK.
Bits 13–12 WUPDIV[1:0]
These bits select the SYSCLK division ratio for resetting the CLGSCLK.CLKDIV[1:0] bits at wake-up.
This setting is ineffective when the CLGSCLK.WUPMD bit = 0.
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Bits 11–10 Reserved
Bits 9–8 WUPSRC[1:0]
These bits select the SYSCLK clock source for resetting the CLGSCLK.CLKSRC[1:0] bits at wake-up.
When a currently stopped clock source is selected, it will automatically start oscillating or clock input
at wake-up. However, this setting is ineffective when the CLGSCLK.WUPMD bit = 0.
6.2 SYSCLK Clock Source and Division Ratio Settings at Wake-upTable 2.
CLGSCLK.
WUPDIV[1:0] bits
0x3 Reserved Reserved 1/8 Reserved
0x2 Reserved Reserved 1/4 Reserved
0x1 1/2 Reserved 1/2 Reserved
0x0 1/1 Reserved 1/1 1/1
0x0 0x1 0x2 0x3
OSC3BCLK – OSC3ACLK EXOSCCLK
CLGSCLK.WUPSRC[1:0] bits
Bits 7–6 Reserved
Bits 5–4 CLKDIV[1:0]
These bits set the division ratio of the clock source to determine the SYSCLK frequency.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the SYSCLK clock source.
When a currently stopped clock source is selected, it will automatically
6.3 SYSCLK Clock Source and Division Ratio SettingsTable 2.
CLGSCLK.
CLKDIV[1:0] bits
0x3 Reserved Reserved 1/8 Reserved
0x2 Reserved Reserved 1/4 Reserved
0x1 1/2 1/2 1/2 Reserved
0x0 1/1 1/1 1/1 1/1
0x0 0x1 0x2 0x3
OSC3BCLK OSC1CLK OSC3ACLK EXOSCCLK
CLGSCLK.CLKSRC[1:0] bits
start oscillating or clock input.
CLG Oscillation Control Register
Register name Bit Bit name Initial Reset R/W Remarks
CLGOSC 15–12 – 0x0 – R –
11 EXOSCSLPC 1 H0 R/W
10 OSC3ASLPC 1 H0 R/W
9 OSC1SLPC 1 H0 R/W
8 OSC3BSLPC 1 H0 R/W
7–4 – 0x0 – R
3 EXOSCEN 0 H0 R/W
2 OSC3AEN 0 H0 R/W
1 OSC1EN 0 H0 R/W
0 OSC3BEN 1 H0 R/W
Bits 15–12 Reserved
Bit 11 EXOSCSLPC
Bit 10 OSC3ASLPC
Bit 9 OSC1SLPC
Bit 8 OSC3BSLPC
These bits control the clock source operations in SLEEP mode.
1 (R/W): Stop clock source in SLEEP mode
0 (R/W): Continue operation state before SLEEP
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Each bit corresponds to the clock source as follows:
CLGOSC.EXOSCSLPC bit: EXOSC clock input
CLGOSC.OSC3ASLPC bit: OSC3A oscillator circuit
CLGOSC.OSC1SLPC bit: OSC1 oscillator circuit
CLGOSC.OSC3BSLPC bit: OSC3B oscillator circuit
Bits 7–4 Reserved
Bit 3 EXOSCEN
Bit 2 OSC3AEN
Bit 1 OSC1EN
Bit 0 OSC3BEN
These bits control the clock source operation.
1(R/W): Start oscillating or clock input
0(R/W): Stop oscillating or clock input
2 POWER SUPPLY, RESET, AND CLOCKS
Each bit corresponds to the clock
source as follows:
CLGOSC.EXOSCEN bit: EXOSC clock input
CLGOSC.OSC3AEN bit: OSC3A oscillator circuit
CLGOSC.OSC1EN bit: OSC1 oscillator circuit
CLGOSC.OSC3BEN bit: OSC3B oscillator circuit
CLG OSC3B Control Register
Register name Bit Bit name Initial Reset R/W Remarks
CLGOSC3B 15–8 – 0x00 – R –
7–2 – 0x00 – R
1–0 OSC3BFREQ[1:0] 0x0 H0 R/WP
Bits 15–2 Reserved
Bits 1–0 OSC3BFREQ[1:0]
These bits select the OSC3BCLK frequency.
6.4 OSC3BCLK Frequency SelectionTable 2.
CLGOSC3B.OSC3BFREQ[1:0] bits OSC3BCLK frequency MHz
0x3 20
0x2 16
0x1 12
0x0 8
CLG OSC1 Control Register
Register name Bit Bit name Initial Reset R/W Remarks
CLGOSC1 15–8 – 0x1a – R –
7–4 – 0xc – R
3 – 0 – R
2 OSC1SEL 1 H0 R/WP
1–0 OSC1WT[1:0] 0x2 H0 R/WP
Bits 15–3 Reserved
Bit 2 OSC1SEL
This bit selects the OSC1 clock source.
1 (R/WP): OSC1B oscillator circuit
0 (R/WP): OSC1A oscillator circuit
Bits 1–0 OSC1WT[1:0]
These bits set the oscillation stabilization waiting time for the OSC1 oscillator circuit.
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6.5 OSC1 Oscillation Stabilization Waiting Time SettingTable 2.
CLGOSC1A.OSC1WT[1:0] bits
0x3 32 clocks 65,536 clocks
0x2 16 clocks 16,384 clocks
0x1 8 clocks 4,096 clocks
0x0 Reserved Reserved
Oscillation stabilization waiting time
OSC1B OSC1A
CLG OSC3A Control Register
Register name Bit Bit name Initial Reset R/W Remarks
CLGOSC3A 15–8 – 0x00 – R –
7–6 – 0x0 – R
5–4 INVN[1:0] 0x1 H0 R/WP
3–2 – 0x0 – R
1–0 OSC3AWT[1:0] 0x2 H0 R/WP
Bits 15–6 Reserved
Bits 5–4 INVN[1:0]
These bits set the oscillation inverter gain of the OSC3A oscillator circuit.
6.6 OSC3A Oscillation Inverter Gain SettingTable 2.
CLGOSC3A.INVN[1:0] bits Inverter gain
0x3 Max.
0x2 ↑
0x1 ↓
0x0 Min.
Bits 3–2 Reserved
Bits 1–0 OSC3AWT[1:0]
These bits set the oscillation stabilization waiting time for the OSC3A oscillator circuit.
6.7 OSC3A Oscillation Stabilization Waiting Time SettingTable 2.
CLGOSC3A.OSC3AWT[1:0] bits Oscillation stabilization waiting time
0x3 4,096 clocks
0x2 1,024 clocks
0x1 256 clocks
0x0 Reserved
CLG Interrupt Flag Register
Register name Bit Bit name Initial Reset R/W Remarks
CLGINTF 15–8 – 0x00 – R –
7–3 – 0x0 – R
2 OSC3ASTAIF 0 H0 R/W Cleared by writing 1.
1 OSC1STAIF 0 H0 R/W
0 OSC3BSTAIF 0 H0 R/W
Bits 15–3 Reserved
Bit 2 OSC3ASTAIF
Bit 1 OSC1STAIF
Bit 0 OSC3BSTAIF
These bits indicate the oscillation stabilization waiting completion interrupt cause occurrence status in
each clock source.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
2-16
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Each bit corresponds to the clock source as follows:
CLGINTF.OSC3ASTAIF bit: OSC3A oscillator circuit
CLGINTF.OSC1STAIF bit: OSC1 oscillator circuit
CLGINTF.OSC3BSTAIF bit: OSC3B oscillator circuit
Note: The CLGINTF.OSC3BSTAIF bit is 0 after system reset is canceled, but OSC3BCLK has al-
ready been stabilized.
CLG Interrupt Enable Register
Register name Bit Bit name Initial Reset R/W Remarks
CLGINTE 15–8 – 0x00 – R –
7–3 – 0x0 – R
2 OSC3ASTAIE 0 H0 R/W
1 OSC1STAIE 0 H0 R/W
0 OSC3BSTAIE 0 H0 R/W
Bits 15–3 Reserved
Bit 2 OSC3ASTAIE
Bit 1 OSC1STAIE
Bit 0 OSC3BSTAIE
These bits enable the oscillation stabilization waiting completion interrupt of each clock source.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Each bit corresponds to the clock source as follows:
CLGINTE.OSC3ASTAIE bit: OSC3A oscillator circuit
CLGINTE.OSC1STAIE bit: OSC1 oscillator circuit
CLGINTE.OSC3BS
TAIE bit: OSC3B oscillator circuit
CLG FOUT Control Register
Register name Bit Bit name Initial Reset R/W Remarks
CLGFOUT 15–8 – 0x00 – R –
7 – 0 – R
6–4 FOUTDIV[2:0] 0x0 H0 R/W
3–2 FOUTSRC[1:0] 0x0 H0 R/W
1 – 0 – R
0 FOUTEN 0 H0 R/W
Bits 15–7 Reserved
Bits 6–4 FOUTDIV[2:0]
These bits set the FOUT clock division ratio.
Bits 3–2 FOUTSRC[1:0]
These bits select the FOUT clock source.
6.8 FOUT Clock Source and Division Ratio SettingsTable 2.
CLGFOUT.
FOUTDIV[2:0] bits
0x7 1/128 1/32,768 1/128 Reserved
0x6 1/64 1/4,096 1/64 Reserved
0x5 1/32 1/1,024 1/32 Reserved
0x4 1/16 1/256 1/16 Reserved
0x3 1/8 1/8 1/8 Reserved
0x2 1/4 1/4 1/4 Reserved
0x1 1/2 1/2 1/2 Reserved
0x0 1/1 1/1 1/1 1/1
0x0 0x1 0x2 0x3
OSC3BCLK OSC1CLK OSC3ACLK SYSCLK
CLGFOUT.FOUTSRC[1:0] bits
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2 POWER SUPPLY, RESET, AND CLOCKS
Note: When the CLGFOUT.FOUTSRC[1:0] bits are set to 0x3, the FOUT output will be stopped in
SLEEP/HALT mode as SYSCLK is stopped.
Bit 1 Reserved
Bit 0 FOUTEN
This bit controls the FOUT clock external output.
1 (R/W): Enable external output
0 (R/W): Disable external output
Note: Since the FOUT signal generated is out of sync with writings to the CLGFOUT.FOUTEN bit, a
glitch may occur when the FOUT output is enabled or disabled.
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3 CPU AND DEBUGGER
Interrupt
controller
Flash
memory
Interrupt request
Interrupt level
Vector number
Instruction bus
RAM
RAM bus
Debugger
Bus controller
Internal bus
General-purpose registers
CPU core (S1C17)
Bit 23 Bit 0
R7
Processor status register
IL[2:0] (Bits [7:5]): Interrupt Level
IE (Bit 4): Interrupt Enable
C (Bit 3): Carry
V (Bit 2): Overflow
Z (Bit 1): Zero
N (Bit 0): Negative
NMI
SYSCLK
DCLK
DSIO
DST2
Bit 7 Bit 0
PSR
Special registers
Program counter
Bit 23 Bit 0
PC
Stack pointer
Bit 23 Bit 0
SP
R6
R5
R4
R3
R2
R1
R0
CPU and Debugger3
Overview3.1
This IC incorporates the Seiko Epson original 16-bit CPU core (S1C17) with a debugger. The main features of the
CPU core are listed below.
• Seiko Epson original 16-bit RISC processor
- 24-bit general-purpose registers: 8
- 24-bit special registers: 2
- 8-bit special register: 1
- Up to 16M bytes of memory space (24-bit address)
- Harvard architecture using separated inst
• Compact and fast instruction set optimized for development in C language
- Code length: 16-bit fixed length
- Number of instructions: 111 basic instructions (184 including variations)
- Execution cycle: Main instructions are executed in one cycle.
- Extended immediate instructions: Immediate data can be extended up to 24 bits.
ruction bus and data bus
• Supports reset, NMI, address misaligned, debug,
and external interrupts.
- Reads a vector from the vector table and branches to the interrupt handler routine directly.
- Can generate software interrupts with a vector number specified (all vector numbers specifiable).
• HALT mode (halt instruction) and SLEEP mode (slp instruction) are provided as the standby function.
• Incorporates a debugger with three-wire communication interface to assist in sof
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1.1 S1C17 ConfigurationFigure 3.
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3 CPU AND DEBUGGER
CPU Core3.2
CPU Registers3.2.1
The CPU includes eight general-purpose registers and three special registers (Table 3.2.1.1).
2.1.1 Initialization of CPU RegistersTable 3.
CPU register name Initial Reset
General-purpose registers R0 to R7 0x000000 H0
Special
registers
For details on the CPU registers, refer to the “S1C17 Family S1C17 Core Manual.” For more information on the
reset vector, refer to the “Interrupt Controller” chapter.
The CPU instruction codes are all fixed to 16 bits in length which, combined with pipelined processing, allows the
most important instructions to be executed in one cycle. For details on the instructions, refer to the “S1C17 Family
S1C17 Core Manual.”
Program counter PC The reset vector is automatically loaded. H0
Stack pointer SP 0x000000 H0
Processor status register PSR 0x00 H0
Instruction Set3.2.2
Reading PSR3.2.3
The PSR contents can be read through the MSCPSR register. Note, however, that data cannot be written to PSR
through the MSCPSR registe
r.
I/O Area Reserved for the S1C17 Core3.2.4
The address range from 0xfffc00 to 0xffffff is the I/O area reserved for the S1C17 core. Do not access this area except when it is required.
Debugger3.3
Debugging Functions3.3.1
The debugger provides the following functions:
• Instruction break: A debug interrupt is generated immediately before the set instruction address is executed. An
instruction br
• Single step: A debug interrupt is generated after each instruction has been executed.
• Forcible break: A debug interrupt is generated using an external input signal.
• Software break: A debug interrupt is generated when the brk instruction is executed.
When a debug interrupt occurs, the CPU enters DEBUG mode. The peripheral circuit operations in DEBUG mode
de
pend on the setting of the DBRUN bit provided in the clock control register of each peripheral circuit. For more
information on the DBRUN bit, refer to “Clock Supply in DEBUG Mode” in each peripheral circuit chapter. DEBUG mode continues until a cancel command is sent from the personal computer or the CPU executes the retd instruction. Neither hardware interrupts nor NMI are accepted during DEBU
eak can be set at up to four addresses.
G mode.
Resource Requirements and Debugging Tools3.3.2
Debugging work area
Debugging requires a 64-byte debugging work area. For more information on the work area location, refer to
the “Memory and Bus” chapter. The start address of this debugging work area can be read from the DBRAM
register.
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3 CPU AND DEBUGGER
DCLK
DSIO
DST2
DCLK
DSIO
DST2
VDD
ICDmini
(S5U1C17001H)
S1C17
R
DBG
Debugging tools
To perform debugging, connect ICDmini (S5U1C17001H) to the input/output pin for the debugger embedded
in this IC and control it from the personal computer. This requires the tools shown below.
• S1C17 Family In-Circuit Debugger ICDmini (S5U1C17001H)
• S1C17 Family C Compiler Package (e.g., S5U1C17001C)
List of debugger input/output pins3.3.3
Table 3.3.3.1 lists the debug pins.
3.3.1 List of Debug PinsTable 3.
Pin name I/O Initial state Function
DCLK O O On-chip debugger clock output pin
Outputs a clock to the ICDmini (S5U1C17001H).
DSIO I/O I On-chip debugger data input/output pin
Used to input/output debugging data and input the break signal.
DST2 O O On-chip debugger status output pin
Outputs the processor status during debugging.
The debugger input/output pins are shared with general-purpose I/O ports and are initially set as the debug pins. If
the debugging function is not used, these pins can be switched to general-purpose I/O port pins. For details, refer to
the “I/O Ports” chapter.
External Connection3.3.4
Figure 3.3.4.1 shows a connection example between this IC and ICDmini when performing debugging.
3.4.1 External ConnectionFigure 3.
For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, DSIO pull-up resistor R
DBG” in the “Electrical Characteristics” chapter. RDBG is not required when using the DSIO pin as a general-
purpose I/O port pin.
Control Register3.4
MISC PSR Register
Register name Bit Bit name Initial Reset R/W Remarks
MSCPSR 15–8 – 0x00 – R –
7–5 PSRIL[2:0] 0x0 H0 R
4 PSRIE 0 H0 R
3 PSRC 0 H0 R
2 PSRV 0 H0 R
1 PSRZ 0 H0 R
0 PSRN 0 H0 R
Bits 15–8 Reserved
Bits 7–5 PSRIL[2:0]
The value (0 to 7) of the PSR IL[2:0] (interrupt level) bits can be read out with these bits.
Bit 4 PSRIE
The value (0 or 1) of the PSR IE (interrupt enable) bit can be read out with this bit.
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Bit 3 PSRC
The value (0 or 1) of the PSR C (carry) flag can be read out with this bit.
Bit 2 PSRV
The value (0 or 1) of the PSR V (overflow) flag can be read out with this bit.
Bit 1 PSRZ
The value (0 or 1) of the PSR Z (zero) flag can be read out with this bit.
Bit 0 PSRN
The value (0 or 1) of the PSR N (negative) flag can be read out with this bit.
Debug RAM Base Register
Register name Bit Bit name Initial Reset R/W Remarks
DBRAM 31–24 – 0x00 – R –
23–0 DBRAM[23:0] *1 H0 R
*1 Debugging work area start address
Bits 31–24 Reserved
Bits 23–0 DBRAM[23:0]
The start address of the debugging work area (64 bytes) can be read out with these bits.
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Memory and Bus4
Overview4.1
This IC supports up to 16M bytes of accessible memory space for both instructions and data.
The features are listed below.
• Embedded Flash memory that supports on-board programming
• Almost all memory and control registers are accessible in 16-bit width and one cycle.
• Write-protect function to protect system control registers
Figure 4.1.1 shows the memory map.
0xff ffff
0xff ff80
0xff ff7f
0x08 3800
0x08 37ff
0x08 0000
0x07 ffff
0x02 8000
0x02 7fff
Reserved for core I/O area (1K bytes)
(Device size: 32 bits)
Reserved
RAM area 2 (14K bytes)
(Device size: 32 bits)
Reserved
*1
*1
4 MEMORY AND BUS
Flash area (128K bytes)
(Device size: 16 bits)
0x00 8000
0x00 7fff
0x00 6000
0x00 5fff
Peripheral circuit area (8K bytes)
0x00 4000
0x00 3fff
0x00 1000
0x00 17ff
0x00 17c0
0x00 17bf
0x00 0000
*1 RAM area 2 is a shared area for the CPU and EPD timing controller, and
CPU access cycle (two-cycle access) if this area is accessed from both simultaneously.
Debug RAM area (64 bytes)
Reserved
(Device size: 16 bits)
Reserved
RAM area 1 (6K bytes)
(Device size: 32 bits)
one wait cycle will be inserted to the
1.1 Memory MapFigure 4.
Note: Be sure to avoid data writing operations to the Reserved areas.
Bus Access Cycle4.2
The CPU uses the system clock for bus access operations. First, “Bus access cycle,” “Device size,” and “Access
size” are defined as follows:
• Bus access cycle: On
• Device size: Bit width of the memory and peripheral circuits that can be accessed in one cycle
• Access size: Access size designated by the CPU instructions (e.g., ld %rd, [%rb] → 16-bit data transfer)
e system clock period = 1 cycle
Table 4.2.1 lists numbers of bus access cycles by different device size and access size. The peripheral circuits can
be accessed with an 8-bit, 16-bit, or 32-bit inst
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4 MEMORY AND BUS
DCLK
DSIO
DST2
DCLK
DSIO
DST2
VDD
ICDmini
(S5U1C17001H)
S1C17
R
DBG
2.1 Number of Bus Access CyclesTable 4.
Device size Access size
8 bits 8 bits 1
16 bits 2
32 bits 4
16 bits 8 bits 1
16 bits 1
32 bits 2
32 bits 8 bits 1
16 bits 1
32 bits 1
Number of bus access
cycles
Note: When data is transferred to a memory in 32-bit access, the eight high-order bits are written to
the memory as 0x00 since the bit width of the S1C17 core general-purpose registers is 24 bits.
Conversely when sending from a memory to a register, the eight
high-order bits are ignored.
The CPU performs 32-bit access for stack operations in an interrupt handling. In this case, the
CPU read/write 32-bit data that consists of the PSR value as the eight high-order bits and the
return address as the 24 low-order bits. For more information, refer to the “S1C17 Family S1C17
Core Manual.”
The CPU adopts Harvard architecture that allows simultaneous processin
g of an instruction fetch and a data access. However, they are not performed simultaneously under one of the conditions listed below. This prolongs the
instruction fetch cycle for the number of data area bus cycles.
• When the CPU executes an instruction stored in the Flash area and accesses data in the Flash area
• When the CPU executes an instruction stored in the internal RAM area and accesses d
ata in the internal RAM
area
Flash Memory4.3
The Flash memory is used to store application programs and data. Address 0x8000 in the Flash area is defined as
the vector table base address by default, therefore a vector table must be located beginning from this address. For
more information on the vector table, refer to “Vector Table” in the “Interrupt Controller” chapter.
Flash Bus Access Cycle Setting4.3.1
There is a limit of frequency to access the Flash memory with no wait cycle, therefore, the number of bus access
cycles for reading must be changed according to the system clock frequency. The number of bus access cycles for
reading can be configured using the FLASHCWAIT.RDWAIT[1:0] bits. Select a setting for higher frequency than
the system clock.
Flash Programming4.3.2
The Flash memory supports on-board programming, so it can be programmed with the ROM data by using the debugger through an ICDmini. Figure 4.3.2.1 shows a connection diagram for on-board programming.
3.2.1 External ConnectionFigure 4.
For detailed information on ROM data programming method, refer to the “(S1C17 Family C Compiler Package)
S5U1C17001C Manual.” The IC can also be shipped after being programmed in the factory with the ROM data
developed. Should you desire to ship the IC with ROM data programmed from the factory, please contact our customer support.
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4 MEMORY AND BUS
Development environment
GNU17 IDE
Factory shipment inspection
process
UserEPSON
file.PA
Mask data file
Specify the unprotecting password.
(6–12 alphanumeric characters (A–Z, a–z, 0–9))
ROM data and password are recorded.
Programming with
ROM data and password
IC with protected Flash
Shipment
Submission
Flash Security Function4.3.3
This IC provides a security function to protect the internal Flash memory from unauthorized reading and tampering
by using the debugger through ICDmini. Figure 4.3.3.1 shows a Flash security function setting flow.
3.3.1 Shipment of IC with ROM Data Programmed and Flash Security Function Setting FlowFigure 4.
The following shows the status of the IC with protected Flash:
• The Flash memory data is undefined if it is read from the debugger.
• An error occurs if an attempt is made to program the Flash memory through ICDmini.
However, the Flash security function can be disabled by entering the unprotecting passwor
d predefined to GNU17
IDE (the security function will take effect again after a reset). For setting the password, refer to the “(S1C17 Family
C Compiler Package) S5U1C17001C Manual.”
Note: Disable the Flash security function before debugging an IC with protected Flash via ICDmini. The
debugging functions may not run normally if the Flash security function is enabled.
RAM14.4
RAM1 can be used to execute the instruction codes copied from another memory as well as storing variables or
other data. This allows higher speed processing and lower power consumption than Flash memory. RAM1 can only
be accessed by the CPU.
Note: The 64 bytes at the end of RAM1 is reserved as the debug RAM area. When using the debug
functions under application development, do not access this area from the application program.
This area can be used for applications of mass-produced devices that do not need debugging.
The RAM1 size used by the application can be configured to equal or less than the implemented size using the
MSCIRAMSZ.IRAMSZ[2:0] bits. For example, this function can be used to prevent creating programs that seek
to access areas outside the RAM area of the target model when developing an application for a
RAM size is smaller than this IC.
After the limitation is applied, accessing an address outside the RAM1 area results
model in which the
in the same operation (undefined value is read out) as when a reserved area is accessed.
RAM24.5
The embedded RAM2 is used to store display data for the EPD. RAM2 allows the EPD timing controller to read
data as well as accesses from the CPU.
The entire RAM2 area
or the area unused for display data can be used as a general-purpose RAM.
The control registers for the peripheral circuits are located in the 8K-byte area beginning with address 0x4000.
Table 4.6.1 shows the control register map. For details of each control register, refer to “List of Peripheral Circuit
Registers” in the Appendix or “Control Registers” in
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(Rev. 1.0)
Peripheral Circuit Control Registers4.6
each peripheral circuit chapter.
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4 MEMORY AND BUS
6.1 Peripheral Circuit Control Register MapTable 4.
Peripheral circuit Address Register name
MISC registers (MISC) 0x4000 MSCPROT MISC System Protect Register
0x4002 MSCIRAMSZ MISC IRAM Size Register
0x4004 MSCTTBRL MISC Vector Table Address Low Register
0x4006 MSCTTBRH MISC Vector Table Address High Register
0x4008 MSCPSR MISC PSR Register
Power generator (PWG) 0x4020 PWGVD1CTL PWG V
Clock generator (CLG) 0x4040 CLGSCLK CLG System Clock Control
D1 Regulator Control Register
Register
0x4042 CLGOSC CLG Oscillation Control Register
0x4044 CLGOSC3B CLG OSC3B Control Register
0x4046 CLGOSC1 CLG OSC1 Control Register
0x4048 CLGOSC3A CLG OSC3A Control Register
0x404a CLGINTF CLG Interrupt Flag Register
0x404c CLGINTE CLG Interrupt Enable Register
0x404e CLGFOUT CLG FOUT Control Register
Theoretical regulation (TR) 0x4052 TRCTL Theoretical Regulation Control Register
Interrupt controller (ITC) 0x4080
ITCLV0 ITC Interrupt Level Setup Register 0
0x4082 ITCLV1 ITC Interrupt Level Setup Register 1
0x4084 ITCLV2 ITC Interrupt Level Setup Register 2
0x4086 ITCLV3 ITC Interrupt Level Setup Register 3
0x4088 ITCLV4 ITC Interrupt Level Setup Register 4
0x408a ITCLV5 ITC Interrupt Level Setup Register 5
0x408c ITCLV6 ITC Interrupt Level Setup Register 6
0x408e ITCLV7 ITC Interrupt Level Setup Register 7
0x4090 ITCLV8 ITC Interr
upt Level Setup Register 8
0x4092 ITCLV9 ITC Interrupt Level Setup Register 9
Watchdog timer (WDT) 0x40a0 WDTCLK WDT Clock Control Register
0x40a2 WDTCTL WDT Control Register
Real-time clock (RTC) 0x40c0 RTCCTL RTC Control Register
0x40c2 RTCINTE RTC Interrupt Enable Register
0x40c4 RTCINTF RTC Interrupt Flag Register
0x40c6 RTCMIN RTC Minute/Second Register
0x40c8 RTCHUR RTC Hour Register
Supply voltage detector (SVD) 0x410
0 SVDCLK SVD Clock Control Register
0x4102 SVDCTL SVD Control Register
0x4104 SVDINTF SVD Status and Interrupt Flag Register
0x4106 SVDINTE SVD Interrupt Enable Register
16-bit timer (T16) Ch.0 0x4160 T16_0CLK T16 Ch.0 Clock Control Register
0x4162 T16_0MOD T16 Ch.0 Mode Register
0x4164 T16_0CTL T16 Ch.0 Control Register
0x4166 T16_0TR T16 Ch.0 Reload Data Register
0x4168 T16_0TC T16 Ch.0 Counter Data Register
0x416a T16_0INT
F T16 Ch.0 Interrupt Flag Register
0x416c T16_0INTE T16 Ch.0 Interrupt Enable Register
Flash controller (FLASHC) 0x41b0 FLASHCWAIT FLASHC Flash Read Cycle Register
I/O ports (PPORT) 0x4200 P0DAT P0 Port Data Register
0x4202 P0IOEN P0 Port Enable Register
0x4204 P0RCTL P0 Port Pull-up/down Control Register
0x4206 P0INTF P0 Port Interrupt Flag Register
0x4208 P0INTCTL P0 Port Interrupt Control Register
0x420a P0CHATEN P0 Port
Chattering Filter Enable Register
0x420c P0MODSEL P0 Port Mode Select Register
0x420e P0FNCSEL P0 Port Function Select Register
0x4210 P1DAT P1 Port Data Register
0x4212 P1IOEN P1 Port Enable Register
0x4214 P1RCTL P1 Port Pull-up/down Control Register
0x4216 P1INTF P1 Port Interrupt Flag Register
0x4218 P1INTCTL P1 Port Interrupt Control Register
0x421a P1CHATEN P1 Port Chattering Filter Enable Register
0x421c P1MODSEL P1
Port Mode Select Register
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Peripheral circuit Address Register name
I/O ports (PPORT) 0x421e P1FNCSEL P1 Port Function Select Register
0x4220 P2DAT P2 Port Data Register
0x4222 P2IOEN P2 Port Enable Register
0x4224 P2RCTL P2 Port Pull-up/down Control Register
0x422c P2MODSEL P2 Port Mode Select Register
0x422e P2FNCSEL P2 Port Function Select Register
0x4230 P3DAT P3 Port Data Register
0x4232 P3IOEN P3 Port Enable Register
0x4234 P3RCTL P3 Port Pull-up/
down Control Register
0x423c P3MODSEL P3 Port Mode Select Register
0x423e P3FNCSEL P3 Port Function Select Register
0x4240 P4DAT P4 Port Data Register
0x4242 P4IOEN P4 Port Enable Register
0x4244 P4RCTL P4 Port Pull-up/down Control Register
0x424c P4MODSEL P4 Port Mode Select Register
0x424e P4FNCSEL P4 Port Function Select Register
0x42d0 PDDAT Pd Port Data Register
0x42d2 PDIOEN Pd Port Enable Register
0x42d4 PDRCTL Pd Port
Pull-up/down Control Register
0x42dc PDMODSEL Pd Port Mode Select Register
0x42de PDFNCSEL Pd Port Function Select Register
0x42e0 PCLK P Port Clock Control Register
0x42e2 PINTFGRP P Port Interrupt Flag Group Register
UART (UART) 0x4380 UA0CLK UART Ch.0 Clock Control Register
0x4382 UA0MOD UART Ch.0 Mode Register
0x4384 UA0BR UART Ch.0 Baud-Rate Register
0x4386 UA0CTL UART Ch.0 Control Register
0x4388 UA0TXD UART Ch.0 Trans
mit Data Register
0x438a UA0RXD UART Ch.0 Receive Data Register
0x438c UA0INTF UART Ch.0 Status and Interrupt Flag Register
0x438e UA0INTE UART Ch.0 Interrupt Enable Register
16-bit timer (T16) Ch.1 0x43a0 T16_1CLK T16 Ch.1 Clock Control Register
0x43a2 T16_1MOD T16 Ch.1 Mode Register
0x43a4 T16_1CTL T16 Ch.1 Control Register
0x43a6 T16_1TR T16 Ch.1 Reload Data Register
0x43a8 T16_1TC T16 Ch.1 Counter Data Register
0x43aa T
16_1INTF T16 Ch.1 Interrupt Flag Register
0x43ac T16_1INTE T16 Ch.1 Interrupt Enable Register
SPI (SPI) Ch.0 0x43b0 SPI0MOD SPI Ch.0 Mode Register
0x43b2 SPI0CTL SPI Ch.0 Control Register
0x43b4 SPI0TXD SPI Ch.0 Transmit Data Register
0x43b6 SPI0RXD SPI Ch.0 Receive Data Register
0x43b8 SPI0INTF SPI Ch.0 Interrupt Flag Register
0x43ba SPI0INTE SPI Ch.0 Interrupt Enable Register
2
C (I2C) 0x43c0 I2C0CLK I2C Ch.0 Clock Control Register
I
0x43c2 I2C0MOD I2C Ch.0 Mode Register
0x43c4 I2C0BR I2C Ch.0 Baud-Rate Register
0x43c8 I2C0OADR I2C Ch.0 Own Address Register
0x43ca I2C0CTL I2C Ch.0 Control Register
0x43cc I2C0TXD I2C Ch.0 Transmit Data Register
0x43ce I2C0RXD I2C Ch.0 Receive Data Register
0x43d0 I2C0INTF I2C Ch.0 Status and Interrupt Flag Register
0x43d2 I2C0INTE I2C Ch.0 Interrupt Enable Register
16-bit PWM timer (T16A3) Ch.0 0x5000 T16A0CLK
T16A3 Ch.0 Clock Control Register
0x5002 T16A0CTL T16A3 Counter Ch.0 Control Register
0x5004 T16A0TC T16A3 Counter Ch.0 Data Register
0x5006 T16A0CCCTL
T16A3 Comparator/Capture Ch.0 Control Register
0x5008 T16A0CCA T16A3 Comparator/Capture Ch.0 A Data Register
0x500a T16A0CCB T16A3 Comparator/Capture Ch.0 B Data Register
0x500c T16A0INTF T16A3 Ch.0 Interrupt Flag Register
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Peripheral circuit Address Register name
16-bit PWM timer (T16A3) Ch.0 0x500e T16A0INTE T16A3 Ch.0 Interrupt Enable Register
16-bit PWM timer (T16A3) Ch.1 0x5020 T16A1CLK T16A3 Ch.1 Clock Control Register
0x5022 T16A1CTL T16A3 Counter Ch.1 Control Register
0x5024 T16A1TC T16A3 Counter Ch.1 Data Register
0x5026 T16A1CCCTL
T16A3 Comparator/Capture Ch.1 Control Register
0x5028 T16A1CCA T16A3 Comparator/Capture Ch.1 A Data Register
0x502a T16A1CCB T16A3 Comparator/Capture Ch.1 B Data Register
0x502c T16A1INTF T16A3 Ch.1 Interrupt Flag Register
0x502e T16A1INTE T16A3 Ch.1 Interrupt Enable Register
Clock timer (CT) 0x5180 CTCTL CT Control Register
0x5182 CTDAT CT Counter Data Register
0x5184 CTINTF CT Interrupt Flag Register
0x5186 CTINTE CT Interrupt Enable Register
16-bit timer (T16) Ch.2 0x5260 T16_2CLK T16 Ch.2 Clock Control Regi
ster
0x5262 T16_2MOD T16 Ch.2 Mode Register
0x5264 T16_2CTL T16 Ch.2 Control Register
0x5266 T16_2TR T16 Ch.2 Reload Data Register
0x5268 T16_2TC T16 Ch.2 Counter Data Register
0x526a T16_2INTF T16 Ch.2 Interrupt Flag Register
0x526c T16_2INTE T16 Ch.2 Interrupt Enable Register
SPI (SPI) Ch.1 0x5270 SPI1MOD SPI Ch.1 Mode Register
0x5272 SPI1CTL SPI Ch.1 Control Register
0x5274 SPI1TXD SPI Ch.1 Transmit Data Register
0x5276 SPI
1RXD SPI Ch.1 Receive Data Register
0x5278 SPI1INTF SPI Ch.1 Interrupt Flag Register
0x527a SPI1INTE SPI Ch.1 Interrupt Enable Register
16-bit timer (T16) Ch.3 0x5280 T16_3CLK T16 Ch.3 Clock Control Register
0x5282 T16_3MOD T16 Ch.3 Mode Register
0x5284 T16_3CTL T16 Ch.3 Control Register
0x5286 T16_3TR T16 Ch.3 Reload Data Register
0x5288 T16_3TC T16 Ch.3 Counter Data Register
0x528a T16_3INTF T16 Ch.3 Interrupt Flag Regis
ter
0x528c T16_3INTE T16 Ch.3 Interrupt Enable Register
SPI (SPI) Ch.2 0x5290 SPI2MOD SPI Ch.2 Mode Register
0x5292 SPI2CTL SPI Ch.2 Control Register
0x5294 SPI2TXD SPI Ch.2 Transmit Data Register
0x5296 SPI2RXD SPI Ch.2 Receive Data Register
0x5298 SPI2INTF SPI Ch.2 Interrupt Flag Register
0x529a SPI2INTE SPI Ch.2 Interrupt Enable Register
Parallel interface (PIO) 0x52e0 PIOCLK PIO Clock Control Register
0x52e2 PIOMOD PIO Mo
de Register
0x52e4 PIOCTL PIO Control Register
0x52e6 PIOWRDAT PIO Address/Write Data Register
0x52e8 PIORDDAT PIO Read Data Register
0x52ea PIOSTAT PIO Status Register
EPD timing controller (EPD Tcon) 0x5380 EPDCTL EPD Tcon Control Register
0x5382 EPDINTF EPD Tcon Interrupt Flag and Status Register
0x5384 EPDINTE EPD Tcon Interrupt Enable Register
R/F converter (RFC) Ch.0 0x5440 RFC0CLK RFC Ch.0 Clock Control Register
42 RFC0CTL RFC Ch.0 Control Register
0x54
0x5444 RFC0TRG RFC Ch.0 Oscillation Trigger Register
0x5446 RFC0MCL RFC Ch.0 Measurement Counter Low Register
0x5448 RFC0MCH RFC Ch.0 Measurement Counter High Register
0x544a RFC0TCL RFC Ch.0 Time Base Counter Low Register
0x544c RFC0TCH RFC Ch.0 Time Base Counter High Register
0x544e RFC0INTF RFC Ch.0 Interrupt Flag Register
0x5450 RFC0INTE RFC Ch.0 Interrupt Enable Register
R/F conv
erter (RFC) Ch.1 0x5460 RFC1CLK RFC Ch.1 Clock Control Register
0x5462 RFC1CTL RFC Ch.1 Control Register
0x5464 RFC1TRG RFC Ch.1 Oscillation Trigger Register
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Peripheral circuit Address Register name
R/F converter (RFC) Ch.1 0x5466 RFC1MCL RFC Ch.1 Measurement Counter Low Register
0x5468 RFC1MCH RFC Ch.1 Measurement Counter High Register
0x546a RFC1TCL RFC Ch.1 Time Base Counter Low Register
0x546c RFC1TCH RFC Ch.1 Time Base Counter High Register
0x546e RFC1INTF RFC Ch.1 Interrupt Flag Register
0x5470 RFC1INTE RFC Ch.1 Interrupt Enable Register
Temperature detection circuit
(TEM) 0x54c0 TEMCLK TEM Clock Control Register
0x54c2 TEMTMG TEM Timing Register
0x54c4 TEMCTL TEM Control Register
0x54c6 TEMRSLT TEM Conversion Result Register
0x54c8 TEMINTF TEM Interrupt Flag and Status Register
0x54ca TEMINTE TEM Interrupt Enable Register
System-Protect Function4.6.1
The system-protect function protects control registers and bits from writings. They cannot be rewritten unless write
protection
deadlock that may occur when a system-related register is altered by a runaway CPU. See “Control Registers” in
each peripheral circuit to identify the registers and bits with write protection.
Note: Once write protection is removed using the MSCPROT.PROT[15:0] bits, write enabled status is
is removed by writing 0x0096 to the MSCPROT.PROT[15:0] bits. This function is provided to prevent
maintained unt
il write protection is applied again. After the registers/bits required have been al-
tered, apply write protection.
Control Registers4.7
MISC System Protect Register
Register name Bit Bit name Initial Reset R/W Remarks
MSCPROT 15–0 PROT[15:0] 0x0000 H0 R/W –
Bits 15–0 PROT[15:0]
These bits protect the control registers related to the system against writings.
0x0096 (R/W): Disable system protection
Other than 0x0096 (R/W): Enable system protection
While the system protection is enabled, any data will not be written to the affected control bits (bits
with “WP” or “R/WP” appearing in the R/W column).
MISC IRAM Size Register
Register name Bit Bit name Initial Reset R/W Remarks
MSCIRAMSZ 15–9 – 0x00 – R –
8 (reserved) 0 H0 R/WP Always set to 0.
7
– 0 – R
6–4 (reserved) 0x4 – R
3 – 0 – R
2–0 IRAMSZ[2:0] 0x4 H0 R/WP
Bits 15–3 Reserved
Bits 2–0 IRAMSZ[2:0]
These bits set the internal RAM size that can be used.
–
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7.1 Internal RAM Size SelectionsTable 4.
MSCIRAMSZ.IRAMSZ[2:0] bits Internal RAM size
0x7 Reserved
0x6 (16KB)*
0x5 (12KB)*
0x4 6KB
0x3 4KB
0x2 2KB
0x1 1KB
0x0 512B
* Setting prohibited in this IC
FLASHC Flash Read Cycle Register
Register name Bit Bit name Initial Reset R/W Remarks
FLASHCWAIT 15–8 – 0x00 – R –
7 XBUSY 0 H0 R
6–2 – 0x00 – R
1–0 RDWAIT[1:0] 0x0 H0 R/WP
Bits 15–8 Reserved
Bit 7 XBUSY
This bit indicates whether the Flash memory can be accessed or not.
1 (R): Flash memory ready to access
0 (R): Flash access prohibited
The Flash memory can always be accessed during normal operation.
Bits 6–2 Reserved
Bits 1–0 RDWAIT[1:0]
These bits set the number of bus access cycles for reading from the Flash memory.
7.2 Setting Number of Bus Access Cycles for Flash Read Table 4.
FLASHCWAIT.RDWAIT[1:0] bits Number of bus access cycles System clock frequency
0x3 4 20.0 MHz (max.)
0x2 3 20.0 MHz (max.)
0x1 2 16.3 MHz (max.)
0x0 1 8.2 MHz (max.)
Note: Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured.
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CPU core
ITC
Watchdog timer
Interrupt request
Interrupt level
Vector number
Interrupt request
NMI
ILVx[2:0]
Interrupt
control
circuit
ILVy[2:0]
Interrupt request
• • •
• • •
Peripheral circuit
Peripheral circuit
Internal data bus
Interrupt Controller (ITC)5
Overview5.1
The features of the ITC are listed below.
• Honors interrupt requests from the peripheral circuits and outputs the interrupt request, interrupt level and vector
number signals to the CPU.
• The interrupt level of each interrupt source is selectable from among eight levels.
• Priorities of the simultaneously generated interrupts are established from the interr
• Handles the simultaneously generated interrupts with the same interrupt level as smaller vector number has high-
er priority.
Figure 5.1.1 shows the configuration of the ITC.
upt level.
1.1 ITC ConfigurationFigure 5.
Vector Table5.2
The vector table contains the vectors to the interrupt handler routines (handler routine start address) that will be
read by the CPU to execute the handler when an interrupt occurs.
Table 5.2.1 shows the vector table.
2.1 Vector TableTable 5.
TTBR initial value = 0x8000
Vector number/
Software interrupt
number
0 (0x00) TTBR + 0x00 Reset • Low input to the #RESET pin
1 (0x01) TTBR + 0x04 Address misaligned interrupt Memory access instruction 2
– (0xfffc00) Debugging interrupt brk instruction, etc. 3
(0x02) TTBR + 0x08 NMI Watchdog timer overflow
2
3 (0x03) TTBR + 0x0c Reserved for C compiler – –
Vector address Hardware interrupt name Cause of hardware interrupt Priority
1
4
• Power-on reset
• Brownout reset
• Key entry reset
• Watchdog timer overflow
• Supply voltage detector reset
*2
*2
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Vector number/
Software interrupt
number
4 (0x04) TTBR + 0x10 Supply voltage detector
5 (0x05) TTBR + 0x14 Port interrupt Port input
6 (0x06) TTBR + 0x18 Clock generator interrupt • OSC3A oscillation stabilization waiting completion
7 (0x07) TTBR + 0x1c Real-time clock interrupt • 1 day
8 (0x08) TTBR + 0x20 16-bit timer Ch.0 interrupt Underflow
9 (0x09) TTBR + 0x24 UART interrupt • End of transmission
10 (0x0a) TTBR + 0x28 16-bit timer Ch.1 interrupt Underflow
11 (0x0b) TTBR + 0x2c SPI Ch.0 interrupt • End of transmission
12 (0x0c) TTBR + 0x30 I
13 (0x0d) TTBR + 0x34 Clock timer in
14 (0x0e) TTBR + 0x38 16-bit timer Ch.2 interrupt Underflow
15 (0x0f) TTBR + 0x3c SPI Ch.1 interrupt • End of transmission
16 (0x10) TTBR + 0x40 16-bit timer Ch.3 interrupt Underflow
17 (0x11) TTBR + 0x44 SPI Ch.2 interrupt • End of transmission
18 (0x12) TTBR + 0x48 16-bit PWM timer Ch.0
19 (0x13) TTBR + 0x4c 16-bit PWM timer Ch.1
20 (0x14) TTBR + 0x50 R/F Ch.0 converter interrupt • Reference oscillation completion
Vector address Hardware interrupt name Hardware interrupt flag Priority
Low power supply voltage detection High
interrupt
• OSC1 oscillation stabilization waiting completion
oscillation stabilization waiting completion
• OSC3B
• Half day
• 1 hour
• 10 minutes
• 1 minute
• 10 seconds
• 1 Hz
• 4 Hz
• 8 Hz
• 32 Hz
• Framing error
• Parity error
• Overrun error
• Receive buffer two bytes full
• Receive buffer one byte full
• Transmit bu
ffer empty
• Receive buffer full
2
C interrupt • End of data transfer
• Transmit buffer empty
• General call address reception
• NACK reception
• STOP condition
• START condition
• Error detection
• Receive buffer full
• Transmit buffer empty
terrupt • 32 Hz
• 8 Hz
• 2 Hz
• 1 Hz
• Receive buffer full
• Transmit buffer empty
• Receive buffer full
• Transmit buffer empty
• Capture B overwrite
interrup
t
• Capture A overwrite
• Capture B
• Capture A
• Compare B
• Compare A
• Capture B overwrite
interrupt
• Capture A overwrite
• Capture B
• Capture A
• Compare B
• Compare A
• Sensor A oscillation completion
• Sensor B oscillation completion
• Measurement counter overfl
ow error
• Time base counter overflow error
*1
↑
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5 INTERRUPT CONTROLLER (ITC)
Vector number/
Software interrupt
number
21 (0x15) TTBR + 0x54 R/F Ch.1 converter interrupt • Reference oscillation completion
22 (0x16) TTBR + 0x58 EPD timing controller
23 (0x17) TTBR + 0x5c Temperature detection circuit
24 (0x18) TTBR + 0x60 reserved –
: : : : ↓
31 (0x1f) TTBR + 0x7c reserved – Low
*1 When the same interrupt level is set
*2 Either reset or NMI can be selected as the watchdog timer interrupt with software.
Vector address Hardware interrupt name Hardware interrupt flag Priority
• Sensor A oscillation completion
• Sensor B oscillation completion
• Measurement counter overflow error
• Time base counter overflow error
Display refresh completi
interrupt
Conversion completion
interrupt
on
*1
Vector Table Base Address (TTBR)5.2.1
The MSCTTBRL and MSCTTBRH registers are provided to set the base (start) address of the vector table in which
interrupt vectors are programmed. “TTBR” described in Table 5.2.1 means the value set to these registers. After an
initial reset, the MSCTTBRL and MSCTTBRH registers are set to address 0x8000. Therefore, even when the vector table location is changed, it is necessary that at least the reset vector be written to the above address. Bits 7 to 0
in the MSCTTBRL register are
fixed at 0, so the vector table always begins from a 256-byte boundary address.
Initialization5.3
The following shows an example of the initial setting procedure related to interrupts:
1. Execute the di instruction to set the CPU into interrupt disabled state.
2. If the vector table start address is different from the default address, set it to the MSCTTBRL and MSCTTBRH
registers after removing syst
em protection by writing 0x0096 to the MSCPROT.PROT[15:0] bits. Then, write a
value other than 0x0096 to the MSCPROT.PROT[15:0] bits to set system protection.
3. Set the interrupt enable bit of the peripheral circuit to 0 (interrupt disabled).
4. Set the interrupt level for the peripheral circuit using the ITCLVx.ILVx[2:0] bits in the ITC.
5. Configure the peripheral circuit and start its operation.
6
. Clear the interrupt factor flag of the peripheral circuit.
7. Set the interrupt enable bit of the peripheral circuit to 1 (interrupt enabled).
8. Execute the ei instruction to set the CPU into interrupt enabled state.
Maskable Interrupt Control and Operations5.4
Peripheral Circuit Interrupt Control5.4.1
The peripheral circuit that generates interrupts includes an interrupt enable bit and an interrupt flag for each interrupt cause.
Interrupt flag: The flag is set to 1 when the interrupt cause occurs. The clear condition depends on the periph-
eral circuit.
Interrupt enable bit: By setting this bit to 1 (interrupt enabled), an interrupt request will be sent to the ITC when the
interrupt flag is set to 1. When this bit is set to 0 (interrupt disabled), no interrupt request will
be sent to the
ITC if the status is changed to interrupt enabled when the interrupt flag is 1.
ITC even if the interrupt flag is set to 1. An interrupt request is also sent to the
For specific information on causes of interrupts, interrupt flags, and interrupt enable bits, refer to the respective peripheral circuit descriptions.
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Note: To prevent occurrence of unnecessary interrupts, always clear the corresponding interrupt flag
before setting the interrupt enable bit to 1 (interrupt enabled) and before terminating the interrupt
handler routine.
ITC Interrupt Request Processing5.4.2
On receiving an interrupt signal from a peripheral circuit, the ITC sends an interrupt request, the interrupt level,
and the vector number to the
cause, as shown in Table 5.2.1. The interrupt level is a value to configure the priority, and it can be set to between 0
(low) and 7 (high) using the ITCLVx.ILVx[2:0] bits provided for each interrupt source. The default ITC settings are
level 0 for all maskable interrupts. Interrupt requests are not accepted by the
Note: Wake-up operations (SLEEP/HALT cancellation) by an interrupt cannot be disabled even if the
interrupt level is set to 0.
The ITC outputs the interrupt request with the highest priority to the CPU in accordance with the following conditions if interrupt requests are input to the ITC simultaneously from two or more peripheral circuits.
• The interrupt with the highest interr
• If multiple interrupt requests are input with the same interrupt level, the interrupt with the lowest vector number
takes precedence.
The other interrupts occurring at the same time are held until all interrupts with higher priority levels have been accepted by the CPU.
If an interrupt cause with higher priority occurs while the ITC is outputting an interrupt request si
(before being accepted by the CPU), the ITC alters the vector number and interrupt level signals to the setting information on the more recent interrupt. The previously occurring interrupt is held. The held interrupt is canceled
and no interrupt is generated if the interrupt flag in the peripheral circuit is cleared via software.
CPU. Vector numbers are determined by the ITC internal hardware for each interrupt
CPU if the level is 0.
upt level takes precedence.
gnal to the CPU
Note: Before changing the interrupt level, make sure th
be generated (the interrupt enable bit of the peripheral circuit is set to 0 or the peripheral circuit
is deactivated).
at no interrupt of which the level is changed can
Conditions to Accept Interrupt Requests by the CPU5.4.3
The CPU accepts an interrupt request sent from the ITC when all of the following conditions are met:
• The IE (Interrupt Enable) bit of the PSR has been set to 1.
• The interru
Level) bits of the PSR.
• No other interrupt request having higher priority, such as NMI, has occurred.
pt request that has occurred has a higher interrupt level than the value set in the IL[2:0] (Interrupt
NMI5.5
The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This interrupt takes precedence over other interrupts and is unconditionally accepted by the CPU.
Fo
r detailed information on generating NMI, refer to the “Watchdog Timer” chapter.
Software Interrupts5.6
The CPU provides the “int imm5” and “intl imm5, imm3” instructions allowing the software to generate any interrupts. The operand imm5 specifies a vector number (0–31) in the vector table. In addition to this, the intl instruction
has the operand imm3 to specify the interrupt level (0–7) to be set to the IL[2:
rupt cannot be disabled (non-maskable interrupt). The processor performs the same interrupt processing operation
as that of the hardware interrupt.
0] bits in the PSR. The software inter-
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5 INTERRUPT CONTROLLER (ITC)
Interrupt Processing by the CPU5.7
The CPU samples interrupt requests for each cycle. On accepting an interrupt request, the CPU switches to interrupt processing immediately after execution of the current instruction has been completed.
Interrupt processing involves the following steps:
1. The PSR and current program counter (PC) values are saved to the stack.
2. The PSR IE bit is cleared to 0 (dis
abling subsequent maskable interrupts).
3. The PSR IL[2:0] bits are set to the received interrupt level. (The NMI does not affect the IL bits.)
4. The vector for the interrupt occurred is loaded to the PC to execute the interrupt handler routine.
When an interrupt is accepted, Step 2 prevents subsequent maskable interrupts. Setting the IE bit to 1 in the interrupt handler routine allows handling of
multiple interrupts. In this case, since the IL[2:0] bits are changed by Step 3,
only an interrupt with a higher level than that of the currently processed interrupt will be accepted.
Ending interrupt handler routines using the reti instruction returns the PSR to the state before the interrupt occurred.
The program resumes processing following the instruction being executed at the time the interrup
t occurred.
Note: At wake-up from HALT or SLEEP mode, the CPU jumps to the interrupt handler routine after
executing one instruction. To execute the interrupt handler routine immediately after wake-up,
place the nop instruction at just behind the halt/slp instruction.
Control Registers5.8
MISC Vector Table Address Low Register
Register name Bit Bit name Initial Reset R/W Remarks
MSCTTBRL 15–8 TTBR[15:8] 0x80 H0 R/WP –
7–0 TTBR[7:0] 0x00 H0 R
Bits 15–0 TTBR[15:0]
These bits set the vector table base address (16 low-order bits).
MISC Vector Table Address High Register
Register name Bit Bit name Initial Reset R/W Remarks
MSCTTBRH 15–8 – 0x00 – R –
7–0 TTBR[23:16] 0x00 H0 R/WP
Bits 15–8 Reserved
Bits 7–0 TTBR[23:16]
These bits set the vector table base address (eight high-order bits).
ITC Interrupt Level Setup Register x
Register name Bit Bit name Initial Reset R/W Remarks
ITCLVx 15–11 – 0x00 – R –
10–8 ILVy
7–3 – 0x00 – R
2–0 ILVy
Bits 15–11 Reserved
Bits 7–3 Reserved
Bits 10–8 ILVy
Bits 2–0 ILVy
1[2:0] (y1 = 2x +1)
0[2:0] (y0 = 2x)
These bits set the interrupt level of each interrupt.
1[2:0] 0x0 H0 R/W
0[2:0] 0x0 H0 R/W
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5 INTERRUPT CONTROLLER (ITC)
8.1 Interrupt Level and Priority SettingsTable 5.
ITCLVx.ILVy[2:0] bits Interrupt level Priority
0x7 7 High
0x6 6 ↑
· · · · · ·
0x1 1 ↓
0x0 0 Low
The following shows the ITCLVx register configuration in this IC.
8.2 List of ITCLVTable 5.
Register name Bit Bit name Initial Reset R/W Remarks
ITCLV0
(ITC Interrupt Level
Setup Register 0)
15–11 – 0x00 – R –
10–8 ILV1[2:0] 0x0 H0 R/W Port interrupt (ILVPPORT)
7–3 – 0x00 – R –
2–0 ILV0[2:0] 0x0 H0 R/W Supply voltage detector interrupt
ITCLV1
(ITC Interrupt Level
Setup Register 1)
15–11 – 0x00 – R –
10–8 ILV3[2:0] 0x0 H0 R/W Real-time clock interrupt (ILVRTC)
7–3 – 0x00 – R –
2–0 ILV2[2:0] 0x0 H0 R/W Clock generator interrupt (ILVCLG)
ITCLV2
(ITC Interrupt Level
Setup Register 2)
15–11 – 0x00 – R –
10–8 ILV5[2:0] 0x0 H0 R/W UART interrupt (ILVUART_0)
7–3 – 0x00 – R –
2–0 ILV4[2:0] 0x0 H0 R/W 16-bit timer Ch.0 interrupt (ILVT16_0)
ITCLV3
(ITC Interrupt Level
Setup Register 3)
15–11 – 0x00 – R –
10–8 ILV7[2:0] 0x0 H0 R/W SPI Ch.0 interrupt (ILVSPI_0)
7–3 – 0x00 – R –
2–0 ILV6[2:0] 0x0 H0 R/W 16-bit timer Ch.1 interrupt (ILVT16_1)
ITCLV4
(ITC Interrupt Level
Setup Register 4)
15–11 – 0x00 – R –
10–8 ILV9[2:0] 0x0 H0 R/W Clock timer interrupt (ILVCT)
7–3 – 0x00 – R –
2–0 ILV8[2:0] 0x0 H0 R/W I
ITCLV5
(ITC Interrupt Level
Setup Register 5)
15–11 – 0x00 – R –
10–8 ILV11[2:0] 0x0 H0 R/W SPI Ch.1 interrupt (ILVSPI_1)
7–3 – 0x00 – R –
2–0 ILV10[2:0] 0x0 H0 R/W 16-bit timer Ch.2 interrupt (ILVT16_2)
ITCLV6
(ITC Interrupt Level
Setup Register 6)
15–11 – 0x00 – R –
10–8 ILV13[2:0] 0x0 H0 R/W SPI Ch.2 interrupt (ILVSPI_2)
7–3 – 0x00 – R –
2–0 ILV12[2:0] 0x0 H0 R/W 16-bit timer Ch.3 interrupt (ILVT16_3)
ITCLV7
(ITC Interrupt Level
Setup Register 7)
15–11 – 0x00 – R –
10–8 ILV15[2:0] 0x0 H0 R/W 16-bit PWM timer Ch.1 interrupt
7–3 – 0x00 – R –
2–0 ILV14[2:0] 0x0 H0 R/W 16-bit PWM timer Ch.0 interrupt
ITCLV8
(ITC Interrupt Level
Setup Register 8)
15–11 – 0x00 – R –
10–8 ILV17[2:0] 0x0 H0 R/W
7–3 – 0x00 – R –
2–0 ILV16[2:0] 0x0 H0 R/W
ITCLV9
(ITC Interrupt Level
Setup Register 9)
15–11 – 0x00 – R –
10–8 ILV19[2:0] 0x0 H0 R/W Temperature detection circuit interrupt
7–3 – 0x00 – R –
2–0 ILV18[2:0] 0x0 H0 R/W EPD timing controller interrupt
x
Registers
(ILVSVD)
2
C interrupt (ILVI2C_0)
(ILVT16A3_1)
(ILVT16A3_0)
R/F converter Ch.1 interrupt (ILVRFC_1)
R/F converter Ch.0 interrupt (ILVRFC_0)
(ILVTEM)
(ILVEPD_Tcon)
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Pxy
PPORT
Pxy
Pxy
Peripheral I/O function 0 I/O control
Peripheral I/O function 1 I/O control
Peripheral I/O function 2 I/O control
Peripheral I/O function 3 I/O control
General-purpose
I/O control
GPIO function
I/O cell
control signal
Output signal
Input signal
PxOUTy
PxyMUX[1:0]
GPIO/
peripheral I/O
function
switching
circuit
PxOENy
PxIENy
PxPDPUy
PxRENy
PxINy
KRSTCFG[1:0]
CLKSRC[1:0]
CLKDIV[3:0]
PxSELy
Clock
generator
Interrupt
controller
System reset
controller
DBRUN
Pxy
CLK_PPORT
I/O cell
Internal data bus
Exist only in the ports that supports the interrupt function.
Chattering
filter
Interrupt
control circuit
Key-entry
reset control
circuit
PxCHATENy
PxEDGEy
PxIFy
PxIEy
PxINT
Key-entry
reset signal
I/O Ports (PPORT)6
Overview6.1
PPORT controls the I/O ports. The main features are outlined below.
• Allows port-by-port function configurations.
- Each port can be configured with or without a pull-up or pull-down resistor.
- Each port can be configured with or without a chattering filter.
- Allows selection of the function (general-purpose I/O port (GPIO) function, up to four peripheral I/O functions) to be assigned to each port.
• Ports, except for those shared with debug pins, are initially placed into Hi-Z state.
(No current passes through the pin during this Hi-Z state.)
• Over voltage tolerant fail-safe design allowing interface with the signal without passing unnecessary current even
if a voltage exceeding V
Note: ‘x’, which is used in the port names Pxy, register names, an
= 0, 1, 2, ··· , d) and ‘y’ refers to a port number (y = 0, 1, 2, ··· , 7).
Figure 6.1.1 shows the configuration of PPORT.
Port configuration in this IC
• Port groups included: P0[7:0], P1[7:0], P2[7:0], P3[7:0], P4[1:0], Pd[2:0]
• Ports with general-purpose I/O function (GPIO): P0[7:0], P1[7:0], P2[7:0], P3[7:0], P4[1:0], Pd[2:0]
(Pd2: output only)
• Ports with i
nterrupt function: P0[7:0], P1[7:0]
• Ports for debug function: Pd[2:0]
• Key-entry reset function: Supported (P0[3:0])
DD is applied.
d bit names, refers to a port group (x
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6 I/O PORTS (PPORT)
Pull-up/down
Control signal
Over voltage tolerant fail-safe type I/O cell
Input signal
Input control signal
Output signal
Output control signal
Analog signal
Analog control signal
Pull-up/down
Control signal
Input signal
Input control signal
Output signal
Output control signal
Analog signal
Analog control signal
Pull-up/down
control
Analog signal
control
VDD
VDD
VDD
VSS
Pxy
V
SS
Standard I/O cell
Pull-up/down
control
Analog signal
control
VDD
VDD
VDD
VDD
VSS
Pxy
V
SS
∗ No diode is
connected at
the V
DD side.
R
INU/
R
IND
RINU/
R
IND
I/O Cell Structure and Functions6.2
Figure 6.2.1 shows the I/O cell Configuration.
2.1 I/O Cell ConfigurationFigure 6.
Refer to “Pin Descriptions” in the “Overview” chapter for the cell type, either the over voltage tolerant fail-safe
type I/O cell or the standard I/O cell, included in each port.
Schmitt Input6.2.1
The input functions are all configured with the Schmitt interface level. When a port is set to input disable status
(PxIOEN.PxIENy bit = 0), unnecessary current is n
Over Voltage Tolerant Fail-Safe Type I/O Cell6.2.2
The over voltage tolerant fail-safe type I/O cell allows interfacing without passing unnecessary current even if a
voltage exceeding V
ased without supplying V
operating power supply voltage to the port.
Pull-Up/Pull-Down6.2.3
The GPIO port has a pull-up/pull-down function. Either pull-up or pull-down may be selected for each port individually. This function may also be disabled for the port that does not require pulling up/down.
When the port level is switched from low to high through the pull-up resistor in
to low through the pull-down resistor, a delay will occur in the waveform rising/falling edge depending on the time
constant by the pull-up/pull-down resistance and the pin load capacitance. The rising/falling time is commonly determined by the following equation:
t
PR = -RINU × (CIN + CBOARD) × ln(1 - VT+/VDD) (Eq. 6.1)
t
PF = -RIND × (CIN + CBOARD) × ln(1 - VT-/VDD)
Where
t
t
V
V
R
C
C
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PR: Rising time (port level = low → high) [second]
PF: Falling time (port level = high → low) [second]
T+: High level Schmitt input threshold voltage [V]
T-: Low level Schmitt input threshold voltage [V]
INU/RIND: Pull-up/pull-down resistance [W]
IN: Pin capacitance [F]
BOARD: Parasitic capacitance on the board [F]
ot consumed if the Pxy pin is placed into floating status.
DD is applied to the port. Also unnecessary current is consumed when the port is externally bi-
DD. However, be sure to avoid applying a voltage exceeding the recommended maximum
cluded in the I/O cell or from high
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6 I/O PORTS (PPORT)
CMOS Output and High Impedance State6.2.4
The I/O cells except for analog output can output signals in the VDD and VSS levels. Also the GPIO ports may be
put into high-impedance (Hi-Z) state.
Clock Settings6.3
PPORT Operating Clock6.3.1
When using the chattering filter for entering external signals to PPORT, the PPORT operating clock CLK_PPORT
must be supplied to PPORT from the clock generator.
T
he CLK_PPORT supply should be controlled as in the procedure shown below.
1. Enable the clock source in the clock generator if it is stopped (refer to “Clock Generator” in the “Power Supply,
Reset, and Clocks” chapter).
2. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
3. Set the following PCLK register bits:
- PCLK.CLKSRC[1:0] bits (Clock source selection)
- PCLK.CLKDIV[3:0] b
4. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
Settings in Step 3 determine the input sampling time of the chattering filter.
its (Clock division ratio selection = Clock frequency setting)
Clock Supply in SLEEP Mode6.3.2
When using the
configured so that it will keep
source.
If the
CLGOSC.xxxxSLPC bit for the CLK_PPORT clock source is 1, the CLK_PPORT clock source is deactivated during SLEEP mode and it disables the
bit setting (chattering filter enabled/disabled).
chattering filter function during SLEEP mode, the PPORT operating clock CLK_PPORT must be
suppling by writing 0 to the
chattering filter function regardless of the PxCHATEN.PxCHATENy
CLGOSC.xxxxSLPC bit for the CLK_PPORT clock
Clock Supply in DEBUG Mode6.3.3
The CLK_PPORT supply during DEBUG mode should be controlled using the PCLK.DBRUN bit.
The CLK_PPORT supply to PPORT is suspended when the CPU enters DEBUG mode if the PCLK.DBRUN bit
= 0. After the CPU returns to normal mode, the CLK_PPORT supply resumes. The PPORT chattering filter stops
operating when the CLK_PPORT supply is suspended. If the chattering filter is enabled in PPORT, the input port
function is also deactivated. Howeve
PPORT supply is not suspended and the chattering filter will keep operating in DEBUG mode.
r, the control registers can be altered. If the PCLK.DBRUN bit = 1, the CLK_
Operations6.4
Initialization6.4.1
After a reset, the ports except for the debugging function are configured as shown below.
• Port input: Disabled
• Port output: Disabled
• Pull-up: Off
• Pull-down: Off
• Port pins: High impedance state
Port function: Configured to GPIO
•
This status continues until the ports are configured via software. The debugging function ports are configured for
debug signal input/output.
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Initial settings when using a port for a peripheral I/O function
When using the Pxy port for a peripheral I/O function, perform the following software initial settings:
1. Set the following PxIOEN register bits:
Set the PxIOEN.PxIENy bit to 0. (Disable input)
Set the PxIOEN.PxOENy bit to 0. (Disable output)
2. Set the PxMODSEL.PxSELy bit to 0. (Disable peripheral I/O function)
3. Initialize the periph
eral circuit that uses the pin.
4. Set the PxFNCSEL.PxyMUX[1:0] bits. (Select peripheral I/O function)
5. Set the PxMODSEL.PxSELy bit to 1. (Enable peripheral I/O function)
For the list of the peripheral I/O functions that can be assigned to each port of this IC, refer to “Control Register
and Port Function Configuration of this IC.” For the specific information on the peripheral I/O functions, refer
to the respective peripheral circuit chapter.
Initial settings when using a port as a general-purpose output port
(only for the ports with GPIO function)
When using the Pxy port pin as a general-purpose output pin, perform the following software initial settings:
1. Set the PxIOEN.PxOENy bit to 1. (Enable output)
2. Set the PxMODSEL.PxSELy bit to 0. (Enable GPIO function)
Initial settings when using a port as a general-purpose input port
(only for the ports with GPIO function)
When using the Pxy port pin as a general-purpose input pin, perform the following software initial settings:
1. Write 0 to the PxINTCTL.PxIEy bit. * (Disable interrupt)
2. When using the chattering filter, configure the PPORT operating clock (see “PPORT Operating Clock”) and
set the PxCHATEN.PxCHATENy bit to 1. *
When the
erating clock is not required).
3. Configure the following PxRCTL register bits when pulling up/down the port using the internal pull-up or
down resistor:
- PxRCTL.PxPDPUy bit (Select pull-up or pull-down resistor)
- Set the PxRCTL.PxRENy bit to 1. (Enable pull-up/down)
Set the PxRCTL.PxRENy bit to 0 if the in
4. Set the PxMODSEL.PxSELy bit to 0. (Enable GPIO function)
5. Configure the following bits when using the port input interrupt: *
- Write 1 to the PxINTF.PxIFy bit. (Clear interrupt flag)
- PxINTCTL.PxEDGEy bit (Select interrupt edge (input rising edge/falling edge))
- Set the PxINTCTL.PxIEy bit to 1. (Enable interrupt)
6. Set the following PxIOEN register b
- Set the PxIOEN.PxOENy bit to 0. (Disable output)
- Set the PxIOEN.PxIENy bit to 1. (Enable input)
* Steps 1 and 5 are required for the ports with an interrupt function. Step 2 is required for the ports with a chat-
tering filter function.
chattering filter is not used, set the PxCHATEN.PxCHATENy bit to 0 (supply of the PPORT op-
ternal pull-up/down resistors are not used.
its:
Table 6.4.1.1 lists the port status according to the combination of data input/output control and pull-up/down
control.
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4.1.1 GPIO Port Control ListTable 6.
PxIOEN.
PxIENy bit
0 0 0 × Disabled Off (Hi-Z) *1
0 0 1 0 Disabled Pulled down
0 0 1 1 Disabled Pulled up
1 0 0 × Enabled Disabled Off (Hi-Z) *2
1 0 1 0 Enabled Disabled Pulled down
1 0 1 1 Enabled Disabled Pulled up
0 1 0 × Disabled Enabled Off
0 1 1 0 Disabled Enabled Off
0 1 1 1 Disabled Enabled Off
1 1 1 0 Enabled Enabled Off
1 1 1 1 Enabled Enabled Off
*1: Initial status. Curren
*2: Use of the pull-up or pull-down function is recommended, as undesired current will flow if the port input is set to floating status.
PxIOEN.
PxOENy bit
t does not flow if the pin is placed into floating status.
PxRCTL.
PxRENy bit
PxRCTL.
PxPDPUy bit
Input Output
Pull-up/pull-down
condition
Note: If the PxMODSEL.PxSELy bit for the port without a GPIO function is set to 0, the port goes into
initial status (refer to “Initial Settings”). The GPIO control bits are configured to a read-only bit alwa
ys read out as 0.
Port Input/Output Control6.4.2
Peripheral I/O function control
The port for which a peripheral I/O function is selected is controlled by the peripheral circuit. For more infor-
mation, refer to the respective peripheral circuit chapter.
Setting output data to a GPIO port
Write data (1 = high output, 0 = low output) to be output from the Pxy pin to the PxDAT.PxOUTy bit.
Reading input data from a GPIO port
The data (1 = high input, 0 = low input) input from the Pxy pin can be read out from the PxDAT.PxINy bit.
Chattering filter function
Some GPIO ports have a chattering filter function and it can be controlled in each port. This function is enabled
by setting the PxCHATEN.PxCHATENy bit to 1. The input sampling time to remove chattering is determined
by the CLK_PPORT frequency co
nfigured using the PCLK register in common to all ports. The chattering filter
removes pulses with a shorter width than the input sampling time.
3
Input sampling time = ———————————— [second] (Eq.6.2)
CLK_PPORT frequency [Hz]
Make sure the Pxy port interrupt is disabled before altering the PCLK register and PxCHATEN.PxCHATENy
bit settings. A Pxy port interrupt may erroneously occur if these settings are altere
d in an interrupt enabled status. Furthermore, enable the interrupt after a lapse of four or more CLK_PPORT cycles from enabling the chattering filter function.
If the clock generator is configured so that it will supply CLK_PPORT to PPORT in SLEEP mode, the chatter-
ing filter of the port will function even in SLEEP mode. If CLK_PPORT is configured to stop in SLEEP mode,
PPORT inactivates the ch
attering filter during SLEEP mode to input pin status transitions directly to itself.
Key-entry reset function
This function issues a reset request when low-level pulses are input to all the specified ports simultaneously.
Make the following settings when using this function:
1. Configure the ports to be used for key-entry reset as general-purpose input ports (refer to “Initial settings
when using a
2. Configure the input pin combination for key-entry reset using the PCLK.KRSTCFG[1:0] bits.
Note: When enabling the key-entry reset function, be sure to configure the port pins to be used for it
as general-purpose input pins before setting the PCLK.KRSTCFG[1:0] bits.
port as a general-purpose input port (only for the ports with GPIO function)”).
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PPORT issues a reset request immediately after all the input pins specified by the PCLK.KRSTCFG[1:0] are
set to a low level if the chattering filter function is disabled (initial status). To issue a reset request only when
low-level signals longer than the time configured are input, enable the chattering filter function for all the ports
used for key-entry reset.
The pins configured for key-entry
reset can also be used as general-purpose input pins.
Interrupts6.5
When the GPIO function is selected for the port with an interrupt function, the port input interrupt function can be
used.
5.1 Port Input Interrupt FunctionTable 6.
Interrupt Interrupt flag Set condition Clear condition
Port input interrupt PxINTF.PxIF
PINTFGRP.PxINT Setting an interrupt flag in the port group Clearing PxINTF.PxIF
Interrupt edge selection
Port input interrupts will occur at the falling edge of the input signal when setting the PxINTCTL.PxEDGEy bit
to 1, or the rising edge when setting to 0.
Interrupt enable
PPORT provides interrupt enable bits (PxINTCTL.PxIEy bit) corresponding to each interrupt flag. An inter-
rupt request is sent to the interrupt controller only when the interrupt flag, of which interrupt has been enabled
by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt Controller”
chapter.
y
Rising or falling edge of the input signal Writing 1
y
Interrupt check in port group unit
When interrupts are enabled in two or more port groups, check the PINTFGRP.PxINT bit in the interrupt han-
dler first. It helps minimize the handler codes for finding the port that has generated an interrupt. If this bit is
set to 1, an interrupt has occurred in the port group. Next, check the PxINTF.PxIFy bit set to 1 in the port group
to determine the port that has generated an interrupt. Clearing the PxINTF.
PxIFy bit also clears the PINTFGRP.
PxINT bit. If the port is set to interrupt disabled status by the PxINTCTL.PxIEy bit, the PINTFGRP.PxINT bit
will not be set even if the PxINTF.PxIFy bit is set to 1.
Control Registers6.6
This section describes the same control registers of all port groups as a single register. For the register and bit configurations in each port group and their initial values,
this IC.”
Px Port Data Register
Register name Bit Bit name Initial Reset R/W Remarks
PxDAT 15–8 PxOUT[7:0] 0x00 H0 R/W –
7–0 PxIN[7:0] 0x00 H0 R
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
*3: The initial value may be changed by the port.
Bits 15–8 PxOUT[7:0]
These bits are used to set data to be output from the GPIO port pins.
1 (R/W): Output high level from the port pin
0 (R/W): Output low level from the port pin
refer to “Control Register and Port Function Configuration of
When output is enabled (PxIOEN.PxOENy bit = 1), the port pin outputs the data set here. Although
data can be written when output is disabled (PxIOEN.PxOENy bit = 0), it does not affect the pin status.
These bits do not affect the outputs when the port is used as a peripheral I/O function.
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Bits 7–0 PxIN[7:0]
The GPIO port pin status can be read out from these bits.
1 (R): Port pin = High level
0 (R): Port pin = Low level
The port pin status can be read out when input is enabled (PxIOEN.PxIENy bit = 1). When input is
disabled (PxIOEN.PxIENy bit = 0), these bits are always read as 0.
When the port is used for a peripheral I/O function, the input value cannot be read out from these bits.
Px Port Enable Register
Register name Bit Bit name Initial Reset R/W Remarks
PxIOEN 15–8 PxIEN[7:0] 0x00 H0 R/W –
7–0 PxOEN[7:0] 0x00 H0 R/W
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15–8 PxIEN[7:0]
These bits enable/disable the GPIO port input.
1 (R/W): Enable (The port pin status is input.)
0 (R/W): Disable (Input data is fixed at 0.)
When both data output and data input are enabled, the pin output status cont
rolled by this IC can be
read.
These bits do not affect the input control when the port is used as a peripheral I/O function.
Bits 7–0 PxOEN[7:0]
These bits enable/disable the GPIO port output.
1 (R/W): Enable (Data is output from the port pin.)
0 (R/W): Disable (The port is placed into Hi-Z.)
These bits do not affect the output control when the port is used as a peripheral I/O function.
Px Port Pull-up/down Control Register
Register name Bit Bit name Initial Reset R/W Remarks
PxRCTL 15–8 PxPDPU[7:0] 0x00 H0 R/W –
7–0 PxREN[7:0] 0x00 H0 R/W
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15–8 PxPDPU[7:0]
These bits select either the pull-up resistor or the pull-down resistor when using a resistor built into
the port.
1 (R/W): Pull-up resistor
0 (R/W): Pull-down resistor
The selected pull-up/down resistor is enabled
Bits 7–0 PxREN[7:0]
These bits enable/disable the port pull-up/down control.
1 (R/W): Enable (The built-in pull-up/down resistor is used.)
0 (R/W): Disable (No pull-up/down control is performed.)
when the PxRCTL.PxRENy bit = 1.
Enabling this function pulls up or down the port when output is disabled (PxIOEN.PxOENy bit = 0).
When output is enabled (PxIOEN.PxOENy bit = 1), the PxRCTL.PxRENy bit setting is ineffectiv
e re-
gardless of how the PxIOEN.PxIENy bit is set and the port is not pulled up/down.
These bits do not affect the pull-up/down control when the port is used as a peripheral I/O function.
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Px Port Interrupt Flag Register
Register name Bit Bit name Initial Reset R/W Remarks
PxINTF 15–8 – 0x00 – R –
7–0 PxIF[7:0] 0x00 H0 R/W Cleared by writing 1.
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15–8 Reserved
Bits 7–0 PxIF[7:0]
These bits indicate the port input interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
Px Port Interrupt Control Register
Register name Bit Bit name Initial Reset R/W Remarks
PxINTCTL 15–8 PxEDGE[7:0] 0x00 H0 R/W –
7–0 PxIE[7:0] 0x00 H0 R/W
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15–8 PxEDGE[7:0]
These bits select the input signal edge to generate a port input interrupt.
1 (R/W): An interrupt will occur at a falling edge.
0 (R/W): An interrupt will occur at a rising edge.
Bits 7–0 PxIE[7:0]
These bits enable port input int
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Note: To prevent generating unnecessary interrupts, clear the corresponding interrupt flag before en-
abling interrupts.
errupts.
Px Port Chattering Filter Enable Register
Register name Bit Bit name Initial Reset R/W Remarks
PxCHATEN 15–8 – 0x00 – R –
7–0 PxCHATEN[7:0] 0x00 H0 R/W
*1: The bit configuration differs depending on the port group.
Bits 15–8 Reserved
Bits 7–0 PxCHATEN[7:0]
These bits enable/disable the chattering filter function.
1 (R/W): Enable (The chattering filter is used.)
0 (R/W): Disable (The chattering filter is bypassed.)
Px Port Mode Select Register
Register name Bit Bit name Initial Reset R/W Remarks
PxMODSEL 15–8 – 0x00 – R –
7–0 PxSEL[7:0] 0x00 H0 R/W
*1: The bit configuration differs depending on the port group.
*2: The initial value may be changed by the port.
Bits 15–8 Reserved
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Bits 7–0 PxSEL[7:0]
These bits select whether each port is used for the GPIO function or a peripheral I/O function.
1 (R/W): Use peripheral I/O function
0 (R/W): Use GPIO function
Px Port Function Select Register
Register name Bit Bit name Initial Reset R/W Remarks
PxFNCSEL 15–14 Px7MUX[1:0] 0x0 H0 R/W –
13–12 Px6MUX[1:0] 0x0 H0 R/W
11–10 Px5MUX[1:0] 0x0 H0 R/W
9–8 Px4MUX[1:0] 0x0 H0 R/W
7–6 Px3MUX[1:0] 0x0 H0 R/W
5–4 Px2MUX[1:0] 0x0 H0 R/W
3–2 Px1MUX[1:0] 0x0 H0 R/W
1–0 Px0MUX[1:0] 0x0 H0 R/W
*1: The bit configuration differs depending on the port group.
*2: The initial value may be changed by the port.
Bits 15–14 Px7MUX[1:0]
: :
Bits 1–0 Px0MUX[1:0]
These bits select the peripheral I/O function to be assigned to each port pin.
6.1 Selecting Peripheral I/O FunctionTable 6.
PxFNCSEL.PxyMUX[1:0] bits Peripheral I/O function
0x3 Function 3
0x2 Function 2
0x1 Function 1
0x0 Function 0
This selection takes effect when the PxMODSEL.PxSELy bit = 1.
P Port Clock Control Register
Register name Bit Bit name Initial Reset R/W Remarks
PCLK 15–9 – 0x00 – R –
8 DBRUN 0 H0 R/WP
7–4 CLKDIV[3:0] 0x0 H0 R/WP
3–2 KRSTCFG[1:0] 0x0 H0 R/WP
1–0 CLKSRC[1:0] 0x0 H0 R/WP
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the PPORT operating clock is supplied in DEBUG mode or not.
1 (R/WP): Clock supplied in DEBUG mode
0 (R/WP): No clock supplied in DEBUG mode
Bits 7–4 CLKDIV[3:0]
These bits select the division ratio of the PPORT operating clock (chattering filter clock).
Bits 3–2 KRSTCFG[1:0]
These bits configure the key-entry rese
6.2 Key-Entry Reset Function SettingsTable 6.
PCLK.KRSTCFG[1:0] bits key-entry reset
0x3 Reset when P0[3:0] inputs = all low
0x2 Reset when P0[2:0] inputs = all low
0x1 Reset when P0[1:0] inputs = all low
0x0 Disable
t function.
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Bits 1–0 CLKSRC[1:0]
These bits select the clock source of PPORT (chattering filter).
The PPORT operating clock should be configured by selecting the clock source using the PCLK.
CLKSRC[1:0] bits and the clock division ratio using the PCLK.CLKDIV[3:0] bits as shown in Table
6.6.3. These settings determine the input sampling time of the chattering filter.
6.3 Clock Source and Division Ratio SettingsTable 6.
PCLK.CLKDIV[3:0] bits
0xf 1/32,768 1/1
0xe 1/16,384
0xd 1/8,192
0xc 1/4,096
0xb 1/2,048
0xa 1/1,024
0x9 1/512
0x8 1/256
0x7 1/128
0x6 1/64
0x5 1/32
0x4 1/16
0x3 1/8
0x2 1/4
0x1 1/2
0x0 1/1
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
0x0 0x1 0x2 0x3
OSC3B OSC1 OSC3A EXOSC
PCLK.CLKSRC[1:0] bits
P Port Interrupt Flag Group Register
Register name Bit Bit name Initial Reset R/W Remarks
PINTFGRP 15–13 – 0x0 – R –
12 PcINT 0 H0 R
11 PbINT 0 H0 R
10 PaINT 0 H0 R
9 P9INT 0 H0 R
8 P8INT 0 H0 R
7 P7INT 0 H0 R
6 P6INT 0 H0 R
5 P5INT 0 H0 R
4 P4INT 0 H0 R
3 P3INT 0 H0 R
2 P2INT 0 H0 R
1 P1INT 0 H0 R
0 P0INT 0 H0 R
*1: Only the bits corresponding to the port groups that support interrupts are provided.
Bits 15–13 Reserved
Bits 12–0 PxINT
1 (R): A port generated an interrupt
0 (R): No port generated an i
These bits indicate that Px port group includes a port that has generated an interrupt.
nterrupt
The PINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt
is cleared.
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Control Register and Port Function Configuration of this IC6.7
This section shows the PPORT control register/bit configuration in this IC and the list of peripheral I/O functions
selectable for each port.
P0 Port Group6.7.1
The P0 port group supports the GPIO, interrupt, and chattering filter functions.
7.1.1 Control Registers for P0 Port GroupTable 6.
Register name Bit Bit name Initial Reset R/W Remarks
P0DAT
(P0 Port Data
Register)
P0IOEN
(P0 Port Enable
Register)
P0RCTL
(
P0 Port Pull-up/down
Control Register)
P0INTF
(P0 Port Interrupt
Flag Register)
P0INTCTL
(P0 Port Interrupt
Control Register)
P0CHATEN
(P0 Port Chattering
Filter Enable
Register)
P0MODSEL
(P0 Port Mode Select
Register)
P0FNCSEL
(P0 Port Function
Select Register)
P0SELy = 0 P0SELy = 1
Port name
P00 P00 T16A3 Ch.0 TOUTA0/CAPA0 CLG FOUT – – – –
P01 P01 T16A3 Ch.0 TOUTB0/CAPB0 PIO #PIOWR – – – –
P02 P02 T16A3 Ch.0 EXCL0 PIO #PIORD – – – –
P03 P03 CLG EXOSC PIO #PIOCE – – – –
P04 P04 SPI Ch.0 #SPISS0 PIO PIOA0 – – – –
P05 P05 SPI Ch.0 SPICLK0 PIO PIOA1 – – – –
P06 P06 SP
P07 P07 SPI Ch.0 SDO0 PIO PIOA3 – – – –
15–8 P0OUT[7:0] 0x00 H0 R/W –
7–0 P0IN[7:0] 0x00 H0 R
15–8 P0IEN[7:0] 0x00 H0 R/W –
7–0 P0OEN[7:0] 0x00 H0 R/W
15–8 P0PDPU[7:0] 0x00 H0 R/W –
7–0 P0REN[7:0] 0x00 H0 R/W
15–8 – 0x00 – R –
7–0 P0IF[7:0] 0x00 H0 R/W Cleared by writing 1.
15–8 P0EDGE[7:0] 0x00 H0 R/W –
7–0 P0IE[7:0] 0x00 H0 R/W
15–8 – 0x00 – R –
7–0 P0CHATEN[7:0] 0x00 H0 R/W
15–8 – 0x00 – R –
7–0 P0SEL[7:0] 0x00 H0 R/W
15–14 P07MUX[1:0] 0x0 H0 R/W Valid settings: 0x0, 0x1
13–12 P06MUX[1:0] 0x0 H0 R/W
11–10 P05MUX[1:0] 0x0 H0 R/W
9–8 P04MUX[1:0] 0x0 H0 R/W
7–6 P03MUX[1:0] 0x0 H0 R/W
5–4 P02MUX[1:0] 0x0 H0 R/W
3–2 P01MUX[1:0] 0x0 H0 R/W
1–0 P00MUX[1:0] 0x0 H0 R/W
7.1.2 P0 Port Group Function AssignmentTable 6.
GPIO
P0yMUX = 0x0
(Function 0)
Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin
I Ch.0 SDI0 PIO PIOA2 – – – –
P0yMUX = 0x1
(Function 1)
P0yMUX = 0x2
(Function 2)
P0yMUX = 0x3
(Function 3)
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
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6-11
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6 I/O PORTS (PPORT)
P1 Port Group6.7.2
The P1 port group supports the GPIO, interrupt, and chattering filter functions.
7.2.1 Control Registers for P1 Port GroupTable 6.
Register name Bit Bit name Initial Reset R/W Remarks
P1DAT
(P1 Port Data
Register)
P1IOEN
(P1 Port Enable
Register)
P1RCTL
(
P1 Port Pull-up/down
Control Register)
P1INTF
(P1 Port Interrupt
Flag Register)
P1INTCTL
(P1 Port Interrupt
Control Register)
P1CHATEN
(P1 Port Chattering
Filter Enable
Register)
P1MODSEL
(P1 Port Mode Select
Register)
P1FNCSEL
(P1 Port Function
Select Register)
P1SELy = 0 P1SELy = 1
Port name
P10 P10 RFC Ch.0 SENB0 PIO PIOA4 – – – –
P11 P11 RFC Ch.0 SENA0 PIO PIOA5 – – – –
P12 P12 RFC Ch.0 REF0 PIO PIOA6 – – – –
P13 P13 RFC Ch.0 RFIN0 PIO PIOA7 – – – –
P14 P14 RFC Ch.1 SENB1 PIO PIOD0 – – – –
P15 P15 RFC Ch.1 SENA1 PIO PIOD1 – – – –
P16 P16 RFC Ch.1 REF1 PIO PIOD2 – – – –
P17
15–8 P1OUT[7:0] 0x00 H0 R/W –
7–0 P1IN[7:0] x H0 R
15–8 P1IEN[7:0] 0x00 H0 R/W –
7–0 P1OEN[7:0] 0x00 H0 R/W
15–8 P1PDPU[7:0] 0x00 H0 R/W –
7–0 P1REN[7:0] 0x00 H0 R/W
15–8 – 0x00 – R –
7–0 P1IF[7:0] 0x00 H0 R/W Cleared by writing 1.
15–8 P1EDGE[7:0] 0x00 H0 R/W –
7–0 P1IE[7:0] 0x00 H0 R/W
15–8 – 0x00 – R –
7–0 P1CHATEN[7:0] 0x00 H0 R/W
15–8 – 0x00 – R –
7–0 P1SEL[7:0] 0x00 H0 R/W
15–14 P17MUX[1:0] 0x0 H0 R/W Valid settings: 0x0, 0x1
13–12 P16MUX[1:0] 0x0 H0 R/W
11–10 P15MUX[1:0] 0x0 H0 R/W
9–8 P14MUX[1:0] 0x0 H0 R/W
7–6 P13MUX[1:0] 0x0 H0 R/W
5–4 P12MUX[1:0] 0x0 H0 R/W
3–2 P11MUX[1:0] 0x0 H0 R/W
1–0 P10MUX[1:0] 0x0 H0 R/W
7.2.2 P1 Port Group Function AssignmentTable 6.
GPIO
P17 RFC Ch.1 RFIN1 PIO PIOD3 – – – –
P1yMUX = 0x0
(Function 0)
Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin
P1yMUX = 0x1
(Function 1)
P1yMUX = 0x2
(Function 2)
P1yMUX = 0x3
(Function 3)
P2 Port Group6.7.3
The P2 port group supports the GPIO function.
7.3.1 Control Registers for P2 Port GroupTable 6.
Register name Bit Bit name Initial Reset R/W Remarks
P2DAT
(P2 Port Data
Register)
P2IOEN
(P2 Port Enable
Register)
6-12
Seiko Epson Corporation S1C17F13 TECHNICAL MANUAL
(Rev. 1.0)
15–8 P2OUT[7:0] 0x00 H0 R/W –
7–0 P2IN[7:0] x H0 R
15–8 P2IEN[7:0] 0x00 H0 R/W –
7–0 P2OEN[7:0] 0x00 H0 R/W
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6 I/O PORTS (PPORT)
Register name Bit Bit name Initial Reset R/W Remarks
P2RCTL
(
P2 Port Pull-up/down
Control Register)
P2INTF
15–8 P2PDPU[7:0] 0x00 H0 R/W –
7–0 P2REN[7:0] 0x00 H0 R/W
15–0 – 0x0000 – R –
P2INTCTL
P2CHATEN
P2MODSEL
(P2 Port Mode Select
Register)
P2FNCSEL
(P2 Port Function
Select Register)
15–8 – 0x00 – R –
7–0 P2SEL[7:0] 0x00 H0 R/W
15–14 P27MUX[1:0] 0x0 H0 R Valid settings: 0x0
13–12 P26MUX[1:0] 0x0 H0 R
11–10 P25MUX[1:0] 0x0 H0 R
9–8 P24MUX[1:0] 0x0 H0 R
7–6 P23MUX[1:0] 0x0 H0 R Valid settings: 0x0, 0x1
5–4 P22MUX[1:0] 0x0 H0 R
3–2 P21MUX[1:0] 0x0 H0 R/W
1–0 P20MUX[1:0] 0x0 H0 R/W
7.3.2 P2 Port Group Function AssignmentTable 6.
P2SELy = 0 P2SELy = 1
Port name
P20 P20 SPI Ch.1 SDO1 PIO PIOD4 – – – –
P21 P21 SPI Ch.1 SDI1 PIO PIOD5 – – – –
P22 P22 SPI Ch.1 SPICLK1 PIO PIOD6 – – – –
P23 P23 SPI Ch.1 #SPISS1 PIO PIOD7 – – – –
P24 P24 SPI Ch.2 #SPISS2 – – – – – –
P25 P25 SPI Ch.2 SPICLK2 – – – – – –
P26 P26 SPI Ch.2 SDI2 – – – – – –
P27 P27 SPI Ch.2
GPIO
P2yMUX = 0x0
(Function 0)
Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin
SDO2 – – – – – –
P2yMUX = 0x1
(Function 1)
P2yMUX = 0x2
(Function 2)
P2yMUX = 0x3
(Function 3)
P3 Port Group6.7.4
The P3 port group supports the GPIO function.
7.4.1 Control Registers for P3 Port GroupTable 6.
Register name Bit Bit name Initial Reset R/W Remarks
P3DAT
(P3 Port Data
Register)
P3IOEN
(P3 Port Enable
Register)
P3RCTL
(
P3 Port Pull-up/down
Control Register)
P3INTF
P3INTCTL
P3CHATEN
P3MODSEL
(P3 Port Mode Select
Register)
15–8 P3OUT[7:0] 0x00 H0 R/W –
7–0 P3IN[7:0] x H0 R
15–8 P3IEN[7:0] 0x00 H0 R/W –
7–0 P3OEN[7:0] 0x00 H0 R/W
15–8 P3PDPU[7:0] 0x00 H0 R/W –
7–0 P3REN[7:0] 0x00 H0 R/W
15–0 – 0x0000 – R –
15–8 – 0x00 – R –
7–0 P3SEL[7:0] 0x00 H0 R/W
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
(Rev. 1.0)
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6 I/O PORTS (PPORT)
Register name Bit Bit name Initial Reset R/W Remarks
P3FNCSEL
(P3 Port Function
Select Register)
15–14 P37MUX[1:0] 0x0 H0 R Valid settings: 0x0, 0x1
13–12 P36MUX[1:0] 0x0 H0 R/W
11–10 P35MUX[1:0] 0x0 H0 R/W
9–8 P34MUX[1:0] 0x0 H0 R/W
7–6 P33MUX[1:0] 0x0 H0 R/W
5–4 P32MUX[1:0] 0x0 H0 R/W
3–2 P31MUX[1:0] 0x0 H0 R/W Valid settings: 0x0, 0x1, 0x2
1–0 P30MUX[1:0] 0x0 H0 R/W Valid settings: 0x0, 0x1
7.4.2 P3 Port Group Function AssignmentTable 6.
P3SELy = 0 P3SELy = 1
Port name
P30 P30 T16A3 Ch.1 EXCL1 RFC Ch.0 RFCLKO0 – – – –
P31 P31 TR REGMON RFC Ch.1 RFCLKO1 SVD EXSVD – –
P32 P32 T16A3 Ch.1 TOUTB1/CAPB1 PIO PIOA0 – – – –
P33 P33 T16A3 Ch.1 TOUTA1/CAPA1 PIO PIOA1 – – – –
P34 P34 UART USIN0 PIO PIOA2 – – – –
P35 P35 UART USOUT0 PIO PIOA3 – – – –
36 P36 I2C SCL0 PIO PIOD0 – – – –
P
P37 P37 I2C SDA0 PIO PIOD1 – – – –
GPIO
P3yMUX = 0x0
(Function 0)
Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin
P3yMUX = 0x1
(Function 1)
P3yMUX = 0x2
(Function 2)
P3yMUX = 0x3
(Function 3)
P4 Port Group6.7.5
The P4 port group supports the GPIO function.
7.5.1 Control Registers for P4 Port GroupTable 6.
Register name Bit Bit name Initial Reset R/W Remarks
P4DAT
(P4 Port Data
Register)
P4IOEN
(P4 Port Enable
Register)
P4RCTL
(
P4 Port Pull-up/down
Control Register
P4INTF
P4INTCTL
P4CHATEN
P4MODSEL
(P4 Port Mode Select
Register)
P4FNCSEL
(P4 Port Function
Select Register)
15–10 – 0x00 – R –
9–8 P4OUT[1:0] 0x0 H0 R/W
7–2 – 0x00 – R
1–0 P4IN[1:0] x H0 R
15–10 – 0x00 – R –
9–8 P4IEN[1:0] 0x0 H0 R/W
7–2 – 0x00 – R
1–0 P4OEN[1:0] 0x0 H0 R/W
15–10 – 0x00 – R –
9–8 P4PDPU[1:0] 0x0 H0 R/W
)
7–2 – 0x00 – R
1–0 P4REN[1:0] 0x0 H0 R/W
15–0 – 0x0000 – R –
15–8 – 0x00 – R –
7–2 – 0x00 – R
1–0 P4SEL[1:0] 0x0 H0 R/W
15–8 – 0x00 – R –
7–4 – 0x0 – R
3–2 P41MUX[1:0] 0x0 H0 R/W Valid settings: 0x0, 0x1
1–0 P40MUX[1:0] 0x0 H0 R/W
7.5.2 P4 Port Group Function AssignmentTable 6.
P4SELy = 0 P4SELy = 1
Port name
P40 P40 UART USIN0 PIO PIOD2 – – – –
P41 P41 UART USOUT0 PIO PIOD3 – – – –
6-14
Seiko Epson Corporation S1C17F13 TECHNICAL MANUAL
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GPIO
P4yMUX = 0x0
(Function 0)
Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin
P4yMUX = 0x1
(Function 1)
P4yMUX = 0x2
(Function 2)
P4yMUX = 0x3
(Function 3)
Page 72
6 I/O PORTS (PPORT)
Pd Port Group6.7.6
The Pd port group consists of three ports Pd0–Pd2 and they are configured as a debugging function port at initialization. These three ports support the GPIO function. The GPIO function of the Pd2 port supports output only,
therefore, the pull-up/down function cannot be used.
7.6.1 Control Registers for Pd Port GroupTable 6.
Register name Bit Bit name Initial Reset R/W Remarks
PDDAT
(Pd Port Data
Register)
PDIOEN
(Pd Port Enable
Register)
PDRCTL
(Pd Port Pull-up/
down Control Register)
PDINTF
PDINTCTL
PDCHATEN
PDMODSEL
(Pd Port Mode Select
Register)
PDFNCSEL
(Pd Port Function
Select Register)
PdSELy = 0 PdSELy = 1
Port name
Pd0 Pd0 DBG DST2 – – – – – –
Pd1 Pd1 DBG DSIO – – – – – –
Pd2 Pd2 DBG DCLK – – – – – –
15–11 – 0x00 – R –
10–8 PDOUT[2:0] 0x0 H0 R/W
7–2 – 0x00 – R
1–0 PDIN[1:0] x H0 R
15–11 – 0x00 – R –
10 reserved 0 H0 R/W
9–8 PDIEN[1:0] 0x0 H0 R/W
7–3 – 0x00 – R
2 reserved 0 H0 R/W
1–0 PDOEN[1:0] 0x0 H0 R/W
15–11 – 0x00 – R –
10 reserved 0 H0 R/W
9–8 PDPDPU[1:0] 0x0 H0 R/W
7–3 – 0x00 – R
2 reserved 0 H0 R/W
1–0 PDREN[1:0] 0x0 H0 R/W
15–0 – 0x0000 – R –
15–8 – 0x00 – R –
7–3 – 0x00 – R
2–0 PDSEL[2:0] 0x7 H0 R/W
15–8 – 0x00 – R –
7–6 – 0x0 – R
5–4 PD2MUX[1:0] 0x0 H0 R/W Valid settings: 0x0
3–2 PD1MUX[1:0] 0x0 H0 R/W
1–0 PD0MUX[1:0] 0x0 H0 R/W
7.6.2 Pd Port Group Function AssignmentTable 6.
GPIO
PdyMUX = 0x0
(Function 0)
Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin
PdyMUX = 0x1
(Function 1)
PdyMUX = 0x2
(Function 2)
PdyMUX = 0x3
(Function 3)
Common Registers between Port Groups6.7.7
7.7.1 Control Registers for Common Use with Port GroupsTable 6.
Register name Bit Bit name Initial Reset R/W Remarks
PCLK
(P Port Clock Control
Register)
PINTFGRP
(P Port Interrupt Flag
Group Register)
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
(Rev. 1.0)
15–9 – 0x00 – R –
8 DBRUN 0 H0 R/WP
7–4 CLKDIV[3:0] 0x0 H0 R/WP
3–2 KRSTCFG[1:0] 0x0 H0 R/WP
1–0 CLKSRC[1:0] 0x0 H0 R/WP
15–8 – 0x00 – R –
7–2 – 0x00 – R
1 P1INT 0 H0 R
0 P0INT 0 H0 R
6-15
Page 73
7 WATCHDOG TIMER (WDT)
WDT
CLK_WDT
NMI
Reset
request
10-bit counter
STATNMI
NMIXRST
Clock generator
Internal data bus
WDTCNTRST
WDTRUN[3:0]
CLKSRC[1:0]
CLKDIV[1:0]
DBRUN
Watchdog Timer (WDT)7
Overview7.1
WDT restarts the system if a problem occurs, such as when the program cannot be executed normally.
The features of WDT are listed below.
• Includes a 10-bit up counter to count NMI/reset generation cycle.
• A counter clock source and clock division ratio are selectable.
• Counter overflow generates a reset or NMI.
Figure 7.1.1 shows the configuration of WDT.
1.1 WDT ConfigurationFigure 7.
Clock Settings7.2
WDT Operating Clock7.2.1
When using WDT, the WDT operating clock CLK_WDT must be supplied to WDT from the clock generator.
The CLK_WDT supply should be controlled as in the procedure shown below.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
2. Enable the clock source in the clock generator if it is stopped (refer to “Clo
Reset, and Clocks” chapter).
3. Set the following WDTCLK register bits:
WDTCLK.CLKSRC[1:0] bits (Clock source selection)
WDTCLK.CLKDIV[1:0] bits (Clock division ratio selection = Clock frequency setting)
4. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
Use the following equation to calculate the WDT counter overflow cycle (
1,024
tWDT = —————— (Eq. 7.1)
CLK_WDT
Where
tWDT: Counter overflow cycle [second]
CLK_WDT: WDT operating clock frequency [Hz]
Example)
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
(Rev. 1.0)
tWDT = 4 seconds when CLK_WDT = 256 Hz
ck Generator” in the “Power Supply,
NMI/reset generation cycle).
7-1
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7 WATCHDOG TIMER (WDT)
Clock Supply in DEBUG Mode7.2.2
The CLK_WDT supply during DEBUG mode should be controlled using the WDTCLK.DBRUN bit.
The CLK_WDT supply to WDT is suspended when the CPU enters DEBUG mode if the WDTCLK.DBRUN bit = 0.
After the CPU returns to normal mode, the CLK_WDT supply resumes. Although WDT stops operating when the
CLK_WDT supply is suspended, the register retains the status before DEBUG mode
If the WDTCLK.DBRUN bit = 1, the CLK_WDT supply is not suspended and WDT will keep operating in DEBUG mode.
was entered.
Operations7.3
WDT Control7.3.1
Starting up WDT
WDT should be initialized and started up with the procedure listed below.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
2. Configure the WDT operating clock.
3. Configure the WDTCTL.NMIXRST bit. (Select
4. Write 1 to the WDTCTL.WDTCNTRST bit. (Reset WDT counter)
5. Write a value other than 0xa to the WDTCTL.WDTRUN[3:0] bits. (Start up WDT)
6. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
NMI or reset mode)
Resetting WDT
WDT generates a system reset (WDTCTL.NMIXRST bit = 0) or NMI (WDTCTL.NMIXRST bit = 1) when the
counter overflows. To avert system restart by
ware while WDT is running.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
2. Write 1 to the WDTCTL.WDTCNTRST bit. (Reset WDT counter)
3. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
A location should be provided for periodically processing this routine. Process this ro
cycle. After resetting, WDT starts counting with a new NMI/reset generation cycle.
If WDT is not reset within the t
or reset, the interrupt vector is read out, and the interrupt handler routine is executed.
If the counter overflows and generates an NMI without WDT being reset, the WDTCTL.STATNMI bit
WDT cycle for any reason, the CPU is switched to interrupt processing by NMI
WDT, its embedded counter must be reset periodically via soft-
utine within the tWDT
is set to 1.
Operations in HALT and SLEEP Modes7.3.2
During HALT mode
WDT
operates in HALT mode. HALT mode is therefore cleared by an NMI or reset if it continues for more than the
NMI/reset generation cycle and the NMI or reset handler is executed. To disable
writing 0xa to the
o
perations after HALT mode is cleared.
WDTCTL.WDTRUN[3:0] bits
before executing the halt instruction. Reset
During SLEEP mode
WDT operates in SLEEP mode if the selected clock source is running. In this case SLEEP mode is cleared by an NMI
or reset if it continues for more than the NMI/reset generation cycle and the NMI or reset handler is executed. Therefore, stop
If the clock source s
clearing SLEEP mode, reset
the
WDT
by setting the
tops in SLEEP mode, WDT stops. To prevent generation of an unnecessary NMI or reset after
WDTCTL.WDTRUN[3:0] bits
WDTCTL.WDTRUN[3:0] bits
WDT
before executing the slp instruction.
before executing the slp instruction.
.
WDT
WDT
in HALT mode, stop
WDT
should also be stopped as required using
WDT
by
before resuming
7-2
Seiko Epson Corporation S1C17F13 TECHNICAL MANUAL
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Page 75
7 WATCHDOG TIMER (WDT)
Control Registers7.4
WDT Clock Control Register
Register name Bit Bit name Initial Reset R/W Remarks
WDTCLK 15–9 – 0x00 – R –
8 DBRUN 0 H0 R/WP
7–6 – 0x0 – R
5–4 CLKDIV[1:0] 0x0 H0 R/WP
3–2 – 0x0 – R
1–0 CLKSRC[1:0] 0x0 H0 R/WP
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the WDT operating clock is supplied in DEBUG mode or not.
1 (R/WP): Clock supplied in DEBUG mode
0 (R/WP): No clock supplied in DEBUG mode
Bits 7–6 Reserved
Bits 5–4 CLKDIV[1:0]
These bits select the division ratio of the WDT operating clock (counter clock). The clock frequency
should be set to around 256 Hz.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
Thes
e bits select the clock source of WDT.
4.1 Clock Source and Division Ratio SettingsTable 7.
WDTCLK.
CLKDIV[1:0] bits
0x3 1/65,536 1/128 1/65,536 1/1
0x2 1/32,768 1/32,768
0x1 1/16,384 1/16,384
0x0 1/8,192 1/8,192
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
0x0 0x1 0x2 0x3
OSC3B OSC1 OSC3A EXOSC
WDTCLK.CLKSRC[1:0] bits
WDT Control Register
Register name Bit Bit name Initial Reset R/W Remarks
WDTCTL 15–10 – 0x00 – R –
9 NMIXRST 0 H0 R/WP
8 STATNMI 0 H0 R
7–5 – 0x0 – R
4 WDTCNTRST 0 H0 WP Always read as 0.
3–0 WDTRUN[3:0] 0xa H0 R/WP –
Bits 15–10 Reserved
Bit 9 NMIXRST
This bit sets the WDT operating mode.
1 (R/WP): NMI mode
0 (R/WP): Reset mode
This bit is used to select whether an NMI signal or a reset signal is output when WDT has not been
reset within the NMI/reset generation cycle.
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7 WATCHDOG TIMER (WDT)
Bit 8 STATNMI
This bit indicates that a counter overflow and NMI have occurred.
1 (R): NMI (counter overflow) occurred
0 (R): NMI not occurred
When the NMI generation function of WDT is used, read this bit in the NMI handler routine to con-
firm that WDT was the source of the NMI.
The STATNMI set to 1 is cleared to 0 by resetting WDT.
Bits 7–5 Reserved
Bit 4 WDTCNTRST
This bit resets WDT.
1 (WP): Reset
0 (WP): Ignored
0 (R): Always 0 w
hen being read
Bits 3–0 WDTRUN[3:0]
These bits control WDT to run and stop.
0xa (R/WP): Stop
Values other than 0xa (R/WP): Run
Always 0x0 is read if a value other than 0xa is written.
Since an NMI or reset may be generated immediately after running depending on the counter value,
WDT should also be reset concurrently when running WDT.
7-4
Seiko Epson Corporation S1C17F13 TECHNICAL MANUAL
(Rev. 1.0)
Page 77
8 SUPPLY VOLTAGE DETECTOR (SVD)
SVD
To system reset circuit
To interrupt controller
SVDMD[1:0]
Sampling timing
generator
Voltage
comparator
circuit
Interrupt/reset
control circuit
Detection
result counter
MODEN
SVDC[4:0]
VDSEL
SVDSC[1:0]
SVDIE
SVDIF
SVDDT
SVDRE[3:0]
CLKSRC[1:0]
CLKDIV[2:0]
Clock generator
CLK_SVD
V
DD
EXSVD
DBRUN
Internal data bus
Supply Voltage Detector (SVD)8
Overview8.1
SVD is a supply voltage detector to monitor the power supply voltage on the VDD pin or the voltage applied to an
external pin. The main features are listed below.
• Power supply voltage to be detected: Selectable from V
• Detectable voltage level: Selectable from among 19 levels (1.8 to 3.6 V)
• Detection results: - C
an be read whether the power supply voltage is lower than the detection
voltage level or not.
- Can generate an interrupt or a reset when low power supply voltage is detected.
• Interrupt: 1 system (Low power supply voltage detection interrupt)
• Supports intermittent operations: - Three detection cycles are selectable.
- Low power supply voltage detection count function to generate an interrup
t/reset when low power supply voltage is successively detected the
number of times specified.
- Continuous operation is also possible.
DD and an external power supply (EXSVD)
Figure 8.1.1 shows the configuration of SVD.
1.1 SVD ConfigurationFigure 8.
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
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8 SUPPLY VOLTAGE DETECTOR (SVD)
SVD
External power
supply/regulator
etc.
SVD
analog block
EXSVD
Input Pin and External Connection8.2
Input Pin8.2.1
Table 8.2.1.1 shows the SVD input pin.
2.1.1 SVD Input PinTable 8.
Pin name I/O* Initial status* Function
EXSVD A A (Hi-Z) External power supply voltage detection pin
* Indicates the status when the pin is configured for SVD.
If the port is shared with the EXSVD pin and other functions, the EXSVD function must be assigned to the port before SVD can be activated. For more information, refer to the “I/O Ports” chapter.
External Connection8.2.2
For the EXSVD pin input voltage range, refer to “Supply Voltage Detector Characteristics, EXSVD pin input voltage range V
When using SVD, the SVD operating clock CLK_SVD must be supplied to SVD from the clock generator.
The CLK_SVD sup
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
2. Enable the clock source in the clock generator if it is stopped (refer to “Clock Generator” in the “Power Supply,
3. Set the following SVDCLK register bits:
4. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
The CLK_SVD frequency should be set to around 32 kHz.
When using SVD
keep supplying by writing 0 to the
If the
ing SLEEP mode and
the CPU returns to normal mode, CLK_SVD is supplied and the SVD operation resumes.
2.2.1 Connection between EXSVD Pin and External Power SupplyFigure 8.
EXSVD” in the “Electrical Characteristics” chapter.
Clock Settings8.3
SVD Operating Clock8.3.1
ply should be controlled as in the procedure shown below.
Reset, and Clocks” chapter).
- SVDCLK.CLKSRC[1:0] bits (Clock source selection)
- SVDCLK.CLKDIV[2:0] bits (Clock
Clock Supply in SLEEP Mode8.3.2
during SLEEP mode, the SVD operating clock CLK_SVD must be configured so that it will
CLGOSC.xxxxSLPC bit for the CLK_
CLGOSC.xxxxSLPC bit for the CLK_
SVD stops with the register settings maintained at those before entering SLEEP mode. After
SVD
clock source is 1, the CLK_
division ratio selection = Clock frequency setting)
SVD
clock source.
SVD
clock source is deactivated dur-
8-2
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8 SUPPLY VOLTAGE DETECTOR (SVD)
Clock Supply in DEBUG Mode8.3.3
The CLK_SVD supply during DEBUG mode should be controlled using the SVDCLK.DBRUN bit.
The CLK_SVD supply to SVD is suspended when the CPU enters DEBUG mode if the SVDCLK.DBRUN bit =
0. After the CPU returns to normal mode, the CLK_SVD supply resumes. Although SVD stops operating when the
CLK_SVD supply is suspended, the registers retain the status before DEBUG mode
was entered.
If the SVDCLK.DBRUN bit = 1, the CLK_SVD supply is not suspended and SVD will keep operating in DEBUG
mode.
Operations8.4
SVD Control8.4.1
Starting detection
SVD should be initialized and activated with the procedure listed below.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
2. Configure the operating clock using the SVDCLK.CLKSRC[1:0] and SVDCLK.CLKDIV[
3. Set the following SVDCTL register bits:
- SVDCTL.VDSEL bit (Select detection voltage (V
DD or EXSVD))
- SVDCTL.SVDSC[1:0] bits (Set low power supply voltage detection counter)
- SVDCTL.SVDC[4:0] bits (Set comparison voltage)
- SVDCTL.SVDRE[3:0] bits (Select reset/interrupt mode)
- SVDCTL.SVDMD[1:0] bits (Set intermittent operation mode)
4. Set the following bits when using the interrupt:
- Wr
ite 1 to the SVDINTF.SVDIF bit. (Clear interrupt flag)
- Set the SVDINTE.SDVIE bit to 1. (Enable SVD interrupt)
5. Set the SVDCTL.MODEN bit to 1. (Enable SVD detection)
6. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
2:0] bits.
Terminating detection
Follow the procedure shown below to stop SVD operation.
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system prot
ection)
2. Write 0 to the SVDCTL.MODEN bit. (Disable SVD detection)
3. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
Reading detection results
The following two detection results can be obtained by reading the SVDINTF.SVDDT bit:
• Power supply voltage (V
• Power supply voltage (V
Before reading the SVDINTF.SVDDT bit, wait for at least SVD circuit enable response time after 1 is written
to the SVDCTL.MODEN bit (refer to “Supply Voltage Detector Characteristics, SVD circuit enable response
time t
SVDEN” in the “Electrical Characteristics” chapter).
After the SVDCTL.SVDC[4:0] bits setting value is altered to change the comparison voltage
SVDCTL.MODEN bit = 1, wait for at least SVD circuit response time before reading the SVDINTF.SVDDT
bit (refer to “Supply Voltage Detector Characteristics, SVD circuit response time t
acteristics” chapter).
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
(Rev. 1.0)
DD or EXSVD) ≥ Comparison voltage when SVDINTF.SVDDT bit = 0
DD or EXSVD) < Comparison voltage when SVDINTF.SVDDT bit = 1
when the
SVD” in the “Electrical Char-
8-3
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8 SUPPLY VOLTAGE DETECTOR (SVD)
VSVDVSVD
VDD
SVDCTL.MODEN
SVD operating status
SVDINTF.SVDDT
Low power supply voltage
detection interrupt
DET
VSVD : Level set using the SVDCTL.SVDC[4:0] bits
: Voltage detection masking time
: Voltage detection operation
DET
VSVDVSVD
VDD
SVDCTL.MODEN
SVD operating status
SVDINTF.SVDDT
Low power supply voltage
detection interrupt
DET
DET
SVD Operations8.4.2
Continuous operation mode
SVD operates in continuous operation mode by default (SVDCTL.SVDMD[1:0] bits = 0x0). In this mode,
SVD operates continuously while the SVDCTL.MODEN bit is set to 1 and it keeps loading the detection results to the SVDINTF.SVDDT bit. During this period, the current detection results can be obtained by reading
the SVDINTF.SVDDT bit as necessary. Furthe
a reset (if the SVDCTL.SVDRE[3:0] bits = 0xa) can be generated when the SVDINTF.SVDDT bit is set to 1 (low
power supply voltage is detected).
Intermittent operation mode
SVD operates in intermittent operation mode when the SVDCTL.SVDMD[1:0] bits are set to 0x1 to 0x3. In
this mode, SVD turns on at an interval set using the SVDCTL.SVDMD[1:
and then it turns off while the SVDCTL.MODEN bit is set to 1. During this period, the latest detection results
can be obtained by reading the SVDINTF.SVDDT bit as necessary. Furthermore, an interrupt or a reset can be
generated when SVD has successively detected low power supply voltage the number of times specified by the
SVDCTL.SVDSC[1:0] bits.
(1) When the SVDCTL.SVDMD[1:0] bits = 0x0 (continuous operation mode)
rmore, an interrupt (if the SVDCTL.SVDRE[3:0] bits ≠ 0xa) or
0] bits to perform detection operation
(2) When the SVDCTL.SVDMD[1:0] bits ≠ 0x0 (intermittent operation mode)
SVD Interrupt and Reset8.5
SVD Interrupt8.5.1
Setting the SVDCTL.SVDRE[3:0] bits to a value other than 0xa allows use of the low power supply voltage detection interrupt function.
Interrupt Interrupt flag Set condition Clear condition
Low power supply
voltage detection
SVD provides the interrupt enable bit (
SVDIF bit
the interrupt is enabled by the
Controller” chapter.
8-4
(Rev. 1.0)
). An interrupt request is sent to the interrupt controller only when the
Seiko Epson Corporation S1C17F13 TECHNICAL MANUAL
4.2.1 SVD OperationsFigure 8.
5.1.1 Low Power Supply Voltage Detection Interrupt FunctionTable 8.
SVDINTF.SVDIF In continuous operation mode
When the SVDINTF.SVDDT bit is 1
In intermittent operation mode
When low power supply voltage is successively detected the specified number of times
SVDINTE.SVDIE
SVDINTE.SVDIE
bit. For more information on interrupt control, refer to the “Interrupt
bit) corresponding to the interrupt flag (
Writing 1
SVDINTF.
SVDINTF.SVDIF bit is set
while
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8 SUPPLY VOLTAGE DETECTOR (SVD)
Once the SVDINTF.SVDIF bit is set, it will not be cleared even if the power supply voltage subsequently returns to
a value exceeding the comparison voltage value. An interrupt may occur due to a temporary power supply voltage
drop, check the power supply voltage status by reading the SVDINTF.SVDDT bit in the interrupt handler routine.
SVD Reset8.5.2
Setting the SVDCTL.SVDRE[3:0] bits to 0xa allows use of the SVD reset issuance function.
The reset issuing timing is the same as that of the
After a reset has been issued, SVD enters continuous operation mode even if it was operating in intermittent operation mode, and continues operating. Issuing an SVD reset initializes the port assignment. However, when EXSVD
is being detected, the i
nput of the port for the EXSVD pin is sent to SVD so that SVD will continue the EXSVD
detection operation.
If the power supply voltage reverts to the normal level, the SVDINTF.SVDDT bit goes 0 and the reset state is canceled. After that, SVD resumes operating in the operation mode set previously via the initialization routine.
During reset state, the SVD control bits are set as shown in Table 8.5.
5.2.1 SVD Control Bits During Reset StateTable 8.
Control register Control bit Setting
SVDCLK DBRUN Reset to the initial values.
CLKDIV[2:0]
CLKSRC[1:0]
SVDCTL VDSEL The set value is retained.
SVDSC[1:0] Cleared to 0. (The set value becomes invalid as SVD en-
SVDC[4:0] The set value is retained.
SVDRE[3:0] The set value (0xa) is retained.
SVDMD[1:0] Cleared to 0 to set continuous operation mode.
MODEN The set value (1) is retained.
SVD
INTF SVDIF The status (1) before being reset is retained.
SVDINTE SVDIE Cleared to 0.
SVDINTF.SVDIF bit being set when a low voltage is detected.
2.1.
ters continuous operation mode.)
Control Registers8.6
SVD Clock Control Register
Register name Bit Bit name Initial Reset R/W Remarks
SVDCLK 15–9 – 0x00 – R –
8 DBRUN 1 H0 R/WP
7 – 0 – R
6–4 CLKDIV[2:0] 0x0 H0 R/WP
3–2 – 0x0 – R
1–0 CLKSRC[1:0] 0x0 H0 R/WP
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the SVD operating clock is supplied in DEBUG mode or not.
1 (R/WP): Clock supplied in DEBUG mode
0 (R/WP): No clock supplied in DEBUG mode
Bit 7 Reserved
Bits 6–4 CLKDIV[2:0]
These bits select the division ratio of the SVD operating clock.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of SVD.
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8 SUPPLY VOLTAGE DETECTOR (SVD)
6.1 Clock Source and Division Ratio SettingsTable 8.
SVDCLK.
CLKDIV[2:0] bits
0x6, 0x7 Reserved 1/1 Reserved 1/1
0x5 1/512 1/512
0x4 1/256 1/256
0x3 1/128 1/128
0x2 1/64 1/64
0x1 1/32 1/32
0x0 1/16 1/16
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
0x0 0x1 0x2 0x3
OSC3B OSC1 OSC3A EXOSC
SVDCLK.CLKSRC[1:0] bits
Note: The clock frequency should be set to around 32 kHz.
SVD Control Register
Register name Bit Bit name Initial Reset R/W Remarks
SVDCTL 15 VDSEL 0 H1 R/WP –
14–13 SVDSC[1:0] 0x0 H0 R/WP
12–8 SVDC[4:0] 0x00 H1 R/WP –
7–4 SVDRE[3:0] 0x0 H1 R/WP
3 – 0 – R
2–1 SVDMD[1:0] 0x0 H0 R/WP
0 MODEN 0 H1 R/WP
Writing takes effect when the SVDCTL.
SVDMD[1:0] bits are not 0x0.
Bit 15 VDSEL
This bit selects the power supply voltage to be detected by SVD.
1 (R/WP): Voltage applied to the EXSVD pin
0 (R/WP): V
DD
Bits 14–13 SVDSC[1:0]
These bits set the condition to generate an interrupt/reset (number of successi
ve low voltage detec-
tions) in intermittent operation mode (SVDCTL.SVDMD[1:0] bits = 0x1 to 0x3).
6.2 Interrupt/Reset Generating Condition in Intermittent Operation ModeTable 8.
SVDCTL.SVDSC[1:0] bits Interrupt/reset generating condition
0x3 Low power supply voltage is successively detected eight times.
0x2 Low power supply voltage is successively detected four times.
0x1 Low power supply voltage is successively detected twice.
0x0 Low power supply voltage is successively detected once.
This setting is ineffective in continuous operation mode (SVDCTL.SVDMD[1:0] bits = 0x0).
Bits 12–8 SVDC[4:0]
Thes
e bits select a comparison voltage for detecting low voltage.
6.3 Comparison Voltage SettingTable 8.
SVDCTL.SVDC[4:0] bits Comparison voltage [V]
0x1f High
0x1e ↑
:
0x0d ↓
0x0c Low
0x0b–0x00 Use prohibited
For more information, refer to “Supply Voltage Detector Characteristics, SVD detection voltage
V
SVD” in the “Electrical Characteristics” chapter.
8-6
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8 SUPPLY VOLTAGE DETECTOR (SVD)
Bits 7–4 SVDRE[3:0]
These bits enable/disable the reset issuance function when a low power supply voltage is detected.
0xa (R/WP): Enable (Issue reset)
Other than 0xa (R/WP): Disable (Generate interrupt)
For more information on the SVD reset issuance function, refer to “SVD Reset.”
Bit 3 Reserved
Bits 2–1 SVDMD[1:0]
These bits select intermittent operation mode and its detection cycle.
6.4 Intermittent Operation Mode Detection Cycle SelectionTable 8.
SVDCTL.SVDMD[1:0] bits Operation mode (detection cycle)
0x3 Intermittent operation mode (CLK_SVD/512)
0x2 Intermittent operation mode (CLK_SVD/256)
0x1 Intermittent operation mode (CLK_SVD/128)
0x0 Continuous operation mode
For more information on intermittent and continuous operation modes, refer to “SVD Operations.”
Bit 0 MODEN
This bit enables/disables for the SVD circuit to operate.
1 (R/WP): Enable (Start detect
ion operations)
0 (R/WP): Disable (Stop detection operations)
After this bit has been altered, wait until the value written is read out from this bit without subsequent
operations being performed.
Notes: • Writing 0 to the SVDCTL.MODEN bit resets the SVD hardware. However, the register values
set and the interrupt flag are not cleared. The SVDCTL.MODEN bit is actually set to 0 after
this processing has
finished. If 1 is written to the SVDCTL.MODEN bit continuously without
waiting for the bit being read as 0 at this time, writing 0 may be ignored and a malfunction
may occur as the hardware restarts without resetting.
• The SVD internal circuit is initialized if the SVDCTL.SVDSC[1:0] bits, SVDCTL.SVDRE[3:0]
bits, or SVDCTL.SVDMD[1:0] bits are altered while SVD is in operation after 1 is written t
o the
SVDCTL.MODEN bit.
SVD Status and Interrupt Flag Register
Register name Bit Bit name Initial Reset R/W Remarks
SVDINTF 15–9 – 0x00 – R –
8 SVDDT x – R
7–1 – 0x00 – R
0 SVDIF 0 H1 R/W Cleared by writing 1.
Bits 15–9 Reserved
Bit 8 SVDDT
The power supply voltage detection results can be read out from this bit.
1 (R): Power supply voltage (V
0 (R): Power supply voltage (V
Bits 7–1 Reserved
Bit 0 SVDIF
This bit indicates the low power supply voltage detection interrupt cause occurrence status.
1 (R): Cause of interrupt occ
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
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DD or EXSVD) < comparison voltage
DD or EXSVD) ≥ comparison voltage
urred
8-7
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8 SUPPLY VOLTAGE DETECTOR (SVD)
Note:
The SVD internal circuit is initialized if the interrupt flag is cleared while SVD is in operation
after 1 is written to the SVDCTL.MODEN bit.
SVD Interrupt Enable Register
Register name Bit Bit name Initial Reset R/W Remarks
SVDINTE 15–8 – 0x00 – R –
7–1 – 0x00 – R
0 SVDIE 0 H0 R/W
Bits 15–1 Reserved
Bit 0 SVDIE
This bit enables low power supply voltage detection interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Notes: • If the SVDCTL.SVDRE[3:0] bits are set to 0xa, no low power supply voltage detection in-
terrupt will occur, as a reset is issued at the same timing as an interrupt.
• To prevent generating unnecessary interrupts, clear the correspondi
enabling interrupts.
ng interrupt flag before
8-8
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16-bit Timers (T16)9
T16 Ch.n
To interrupt controller
(To peripheral circuit)
Underflow
PRESET
Timer control
circuit
Interrupt control
circuit
Chattering filter
PRUN
TRMD
CLKSRC[1:0]
CLKDIV[3:0]
Clock generator
I/O port
UFIE
UFIF
DBRUN
MODEN
CLK_T16_n
EXCLm
Timer counter
TC[15:0]
Reload register
TR[15:0]
Internal data bus
Overview9.1
T16 is a 16-bit timer. The features of T16 are listed below.
• 16-bit presettable down counter
• Provides a reload data register for setting the preset value.
• A clock source and clock division ratio for generating the count clock are selectable.
• Repeat mode or one-shot mode is selectable.
• Can generate counter underflow interrupts.
9 16-BIT TIMERS (T16)
Figure 9.1.1 shows the configura
tion of a T16 channel.
Channel configuration in this IC
• Number of channels: 4 channels (Ch.0 to Ch.3)
• Event counter function: Unavailable
• Peripheral clock output: Ch.1 → SPI Ch.0 master clock
Ch.2 → SPI Ch.1 master clock
Ch.3 → SPI Ch.2 master clock
(Outputs the counter underflow signal)
Input Pin9.2
1.1 Configuration of a T16 ChannelFigure 9.
Table 9.2.1 shows the T16 input pin.
Pin name I/O* Initial status* Function
EXCLm I I (Hi-Z) External event signal input pin
If the port is shared with the EXCLm pin and other functions, the EXCLm input function must be assigned to the
port before using the event counter function. The EXCLm signal can be input through the chattering filter. For more
information, refer to the “I/O Por
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
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ts” chapter.
2.1 T16 Input PinTable 9.
* Indicates the status when the pin is configured for T16.
9-1
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9 16-BIT TIMERS (T16)
EXCLm pin input
Counter
xx - 1 x - 2 x - 3
Clock Settings9.3
T16 Operating Clock9.3.1
When using T16 Ch.n, the T16 Ch.n operating clock CLK_T16_n must be supplied to T16 Ch.n from the clock
generator. The CLK_T16_n supply should be controlled as in the procedure shown below.
1. Enable the clock source in the clock generator if it is stopped (refer to “Clock Generator” in the “Power Supply,
Reset, and Clocks” chapter).
2. Set the following
- T16_nCLK.CLKSRC[1:0] bits (Clock source selection)
- T16_nCLK.CLKDIV[3:0] bits (Clock division ratio selection = Clock frequency setting)
Clock Supply in SLEEP Mode9.3.2
T16_nCLK register bits:
When using T16
supplying by writing 0 to the
If the
CLGOSC.xxxxSLPC bit for the
during SLEEP mode and
SLEEP mode. After the CPU returns to normal mode, CLK_T16_n is supplied and the T16 operation resumes.
during SLEEP mode, the T16 operating clock CLK_T16_n must be configured so that it will keep
CLGOSC.xxxxSLPC bit for the
CLK_T16_n
T16 stops with the register settings and counter value maintained at those before entering
clock source is 1, the
CLK_T16_n
clock source.
CLK_T16_n
clock source is deactivated
Clock Supply in DEBUG Mode9.3.3
The CLK_T16_n supply during DEBUG mode should be controlled using the T16_nCLK.DBRUN bit.
The CLK_T16_n supply to T16 Ch.n is suspended when the CPU enters DEBUG mode if the T16_nCLK.DBRUN
bit = 0. After the CPU returns to normal mode, the CLK_T16_n supply resumes. Although T16 Ch.n stops operating when the CLK_T16_n supply is suspended, the counter and registers retain the status before DEBUG mode
was entered. If the T16_nCLK.DBRUN bit = 1, the CLK_T16_n supply is
operating in DEBUG mode.
not suspended and T16 Ch.n will keep
Event Counter Clock9.3.4
The channel that supports the event counter function counts down at the rising edge of the EXCLm pin input signal
when the T16_nCLK.CLKSRC[1:0] bits are set to 0x3.
3.3.1 Count Down TimingFigure 9.
Note that the EXOSC clock is selected for the channel that does not support the event counter function.
T16 Ch.n should be initialized and started counting with the procedure shown below.
1. Configure the T16 Ch.n operating clock (see “T16 Operating Clock”).
2. Set the T16_nCTL.MODEN bit to 1. (Enable count operation clock)
3. Set
4. Set the T16_nTR register. (Set reload data (counter preset data))
5. Set the following bits when using the interrupt:
9-2
(Rev. 1.0)
Operations9.4
Initialization9.4.1
the T16_nMOD.TRMD bit. (Select operation mode (Repeat mode or One-shot mode)).
- Write 1 to the T16_nINTF.UFIF bit. (Clear interrupt flag)
- Set the T16_nINTE.UFIE bit to 1. (Enable underflow interrupt)
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9 16-BIT TIMERS (T16)
Counter
0xffff
0x0000
Software control
Underflow interrupt
Underflow cycle
Time
T16_nTR
register setting
PRESET = 1
PRUN = 1 PRUN = 1
PRUN = 0
6. Set the following T16_nCTL register bits:
- Set the T16_nCTL.PRESET bit to 1. (Preset reload data to counter)
- Set the T16_nCTL.PRUN bit to 1. (Start counting)
Counter Underflow9.4.2
Normally, the T16 counter starts counting down from the reload data value preset and generates an underflow signal
when an underflow occurs. This signal is used to generate an interrupt and may be output to a specif
ic peripheral
circuit as a clock (T16 Ch.n must be set to repeat mode to generate a clock). The underflow cycle is determined by
the T16 Ch.n operating clock setting and reload data (counter initial value) set in the T16_nTR register.
The following shows the equations to calculate the underflow cycle and frequency:
TR + 1 f
T = ————— fT = ————— (Eq. 9.1)
CLK_T16_n TR + 1
f
CLK_T16_n
Where
T: Und
f
T: Underflow frequency [Hz]
erflow cycle [s]
TR: T16_nTR register setting
f
CLK_T16_n: T16 Ch.n operating clock frequency [Hz]
Operations in Repeat Mode9.4.3
T16 Ch.n enters repeat mode by setting T16_nMOD.TRMD bit to 0.
In repeat mode, the count operation starts by writing 1 to the T16_nCTL.PRUN bit and continues until 0 is written.
A counter underflow presets the T16_nTR register value to the coun
this mode to generate periodic underflow interrupts or when using the timer to output a trigger/clock to the peripheral circuit.
ter, so underflow occurs periodically. Select
T16 Ch.n enters one-shot mode by setting the T16_nMOD.TRMD bit to 1.
In one-shot mode, the count operation starts by writing 1 to the T16_nCTL.PRUN bit and stops after the T16_nTR
register value is preset to the counter when an underflow has occurred. At the same time the counter stops, the T16_
nCTL.PRUN bit is cleared
such as for checking a specific lapse of time.
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
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Operations in One-shot Mode9.4.4
4.3.1 Count Operations in Repeat ModeFigure 9.
automatically. Select this mode to stop the counter after an interrupt has occurred once,
9-3
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9 16-BIT TIMERS (T16)
0xffff
0x0000
PRESET = 1
PRUN = 1
PRUN = 1
PRUN = 0
PRUN = 1 PRUN = 1
Counter
Software control
Underflow interrupt
Underflow cycle
Time
T16_nTR
register setting
4.4.1 Count Operations in One-shot ModeFigure 9.
Counter Value Read9.4.5
The counter value can be read out from the T16_nTC.TC[15:0] bits. However, since T16 operates on CLK_T16_n,
one of the operations shown below is required to read correctly by the CPU.
- Read the counter value twice or more and check to see if the same value is read.
- Stop the timer and then read the counter value.
Interrupt9.5
Each T16 channel has a function to generate the interrupt shown in Table 9.5.1.
5.1 T16 Interrupt FunctionTable 9.
Interrupt Interrupt flag Set condition Clear condition
Underflow T16_nINTF.UFIF When the counter underflows Writing 1
T16 provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the interrupt
controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For
more information on interrupt control, refer to the “
Interrupt Controller” chapter.
Control Registers9.6
T16 Ch.n Clock Control Register
Register name Bit Bit name Initial Reset R/W Remarks
T16_nCLK 15–9 – 0x00 – R –
8 DBRUN 0 H0 R/W
7–4 CLKDIV[3:0] 0x0 H0 R/W
3–2 – 0x0 – R
1–0 CLKSRC[1:0] 0x0 H0 R/W
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the T16 Ch.n operating clock is supplied in DEBUG mode or not.
1 (R/W): Clock supplied in DEBUG mode
0 (R/W): No clock supplied in DEBUG mode
Bits 7–4 CLKDIV[3:0]
These bits select the division ratio of the T16 Ch.n operating clock (counter clock).
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of T16 Ch.n.
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9 16-BIT TIMERS (T16)
6.1 Clock Source and Division Ratio SettingsTable 9.
T16_nCLK.
CLKDIV[3:0] bits
0xf 1/32,768 1/1 1/32,768 1/1
0xe 1/16,384 1/16,384
0xd 1/8,192 1/8,192
0xc 1/4,096 1/4,096
0xb 1/2,048 1/2,048
0xa 1/1,024 1/1,024
0x9 1/512 1/512
0x8 1/256 1/256 1/256
0x7 1/128 1/128 1/128
0x6 1/64 1/64 1/64
0x5 1/32 1/32 1/32
0x4 1/16 1/16 1/16
0x3 1/8 1/8 1/8
0x2 1/4 1/4 1/4
0x1 1/2 1/2 1/2
0x0 1/1 1/1 1/1
(Note 1) The oscillation circuits/external input that are n
selected as the clock source.
(Note 2) When the T16_nCLK.CLKSRC[1:0] bits are set to 0x3, EXCLm is selected for the
channel with an event counter function or EXOSC is selected for other channels.
0x0 0x1 0x2 0x3
OSC3B OSC1 OSC3A EXOSC/EXCLm
T16_nCLK.CLKSRC[1:0] bits
ot supported in this IC cannot be
T16 Ch.n Mode Register
Register name Bit Bit name Initial Reset R/W Remarks
T16_nMOD 15–8 – 0x00 – R –
7–1 – 0x00 – R
0 TRMD 0 H0 R/W
Bits 15–1 Reserved
Bit 0 TRMD
This bit selects the T16 operation mode.
1 (R/W): One-shot mode
0 (R/W): Repeat mode
For detailed information on the operation mode, refer to “Operations in One-shot Mode” and
“Operations in Repeat Mode.”
T16 Ch.n Control Register
Register name Bit Bit name Initial Reset R/W Remarks
T16_nCTL 15–9 – 0x00 – R –
8 PRUN 0 H0 R/W
7–2 – 0x00 – R
1 PRESET 0 H0 R/W
0 MODEN 0 H0 R/W
Bits 15–9 Reserved
Bit 8 PRUN
This bit starts/stops the timer.
1 (W): Start timer
0 (W): Stop timer
1 (R): Timer is running
0 (R): Timer is idle
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9 16-BIT TIMERS (T16)
By writing 1 to this bit, the timer starts count operations. However, the T16_nCTL.MODEN bit must
be set to 1 in conjunction with this bit or it must be set in advance. While the timer is running, writing
0 to this bit stops count operations. When the counter stops due to a counter underflow in one-shot
mode, this bit is automatically cleared to 0.
Bits 7–2 Reserved
Bit 1 PRESET
This bit presets the reload data stored in the
T16_nTR register to the counter.
1 (W): Preset
0 (W): Ineffective
1 (R): Presetting in progress
0 (R): Presetting finished or normal operation
By writing 1 to this bit, the timer presets the T16_nTR register value to the counter. However, the
T16_nCTL.MODEN bit must be set to 1 in conjunction with this bit or it must be set in advance. This
bit retains 1 during presetting and is automatically cle
ared to 0 after presetting has finished.
Bit 0 MODEN
This bit enables the T16 Ch.n operations.
1 (R/W): Enable (Start supplying operating clock)
0 (R/W): Disable (Stop supplying operating clock)
T16 Ch.n Reload Data Register
Register name Bit Bit name Initial Reset R/W Remarks
T16_nTR 15–0 TR[15:0] 0xffff H0 R/W –
Bits 15–0 TR[15:0]
These bits are used to set the initial value to be preset to the counter.
The value set to this register will be preset to the counter when 1 is written to the T16_nCTL.PRESET
bit or when the counter underflows.
Note: The T16_nTR register cannot be altered while the timer is running (T16_nCTL.PRUN bit = 1), as
an incorrect initial value may be preset to the counter.
T16 Ch.n Counter Data Register
Register name Bit Bit name Initial Reset R/W Remarks
T16_nTC 15–0 TC[15:0] 0xffff H0 R –
Bits 15–0 TC[15:0]
The current counter value can be read out from these bits.
T16 Ch.n Interrupt Flag Register
Register name Bit Bit name Initial Reset R/W Remarks
T16_nINTF 15–8 – 0x00 – R –
7–1 – 0x00 – R
0 UFIF 0 H0 R/W Cleared by writing 1.
Bits 15–1 Reserved
Bit 0 UFIF
This bit indicates the T16 Ch.n underflow interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
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9 16-BIT TIMERS (T16)
T16 Ch.n Interrupt Enable Register
Register name Bit Bit name Initial Reset R/W Remarks
T16_nINTE 15–8 – 0x00 – R –
7–1 – 0x00 – R
0 UFIE 0 H0 R/W
Bits 15–1 Reserved
Bit 0 UFIE
This bit enables T16 Ch.n underflow interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Note: To prevent generating unnecessary interrupts, clear the corresponding interrupt flag before
enabling interrupts.
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10 UART (UART)
UART Ch.n
Interrupt
control circuit
Baud rate
generator
Transmit/receive
control circuit
Receive data buffer
RXD[7:0]
Clock generator
Interrupt
controller
CLK_UARTn
Shift register RZI demodulator
Transmit data buffer
TXD[7:0]
Shift register RZI modulator
PUEN
OUTMD
IRMD
FMD[3:0]
BRT[7:0]
USINn
USOUTn
CLKSRC[1:0]
CLKDIV[1:0]
DBRUN
MODEN
TENDIE
FEIE
PEIE
OEIE
RB2FIE
RB1FIE
TBEIE
TENDIF
FEIF
PEIF
OEIF
RB2FIF
RB1FIF
TBEIF
STPB
SFTRST
RBSY
TBSY
PRMD
PREN
CHLN
Internal data bus
INVIRTX
INVIRRX
UART (UART)10
Overview10.1
The UART is an asynchronous serial interface. The features of the UART are listed below.
• Includes a baud rate generator for generating the transfer clock.
• Supports 7- and 8-bit data length (LSB first).
• Odd parity, even parity, or non-parity mode is selectable.
• The start bit length is fixed at 1 bit.
• The stop bit length is selectable from 1 bit and 2 bits.
• Support
• Includes a 2-byte receive data buffer and a 1-byte transmit data buffer.
• Includes an RZI modulator/demodulator circuit to support IrDA 1.0-compatible infrared communications.
• Can detect parity error, framing error, and overrun error.
• Can generate receive buffer full (1 byte/2 bytes), transmit buffer empty, end of transmission, parity error, framing
• Input pin can be pulled up with an internal resistor.
• The output pin is configurable as an open-drain output.
s full-duplex communications.
error, and over
run error interrupts.
Figure 10.1.1 shows the UART configuration.
Channel configuration in this IC
• 1 channel (Ch.0)
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1.1 UART ConfigurationFigure 10.
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10 UART (UART)
USINn
USOUTn
OUT
IN
S1C17 UART External UART
Input/Output Pins and External Connections10.2
List of Input/Output Pins10.2.1
Table 10.2.1.1 lists the UART pins.
2.1.1 List of UART PinsTable 10.
Pin name I/O* Initial status* Function
USINn I I (Hi-Z) UART Ch.n data input pin
USOUTn O O (High) UART Ch.n data output pin
* Indicates the status when the pin is configured for the UART.
If the port is shared with the UART pin and other functions, the UART input/output function must be assigned to
the port before activating the UART. For more information, refer to the “I/O Ports” chapter.
External Connections10.2.2
Figure 10.2.2.1 shows a connection diagram between the UART in this IC and an external UART device.
2.2.1 Connections between UART and an External UART DeviceFigure 10.
Input Pin Pull-Up Function10.2.3
The UART includes a pull-up resistor for the USINn pin. Setting the UAnMOD.PUEN bit to 1 enables the resistor
to pull up the USINn pin.
Output Pin Open-Drain Output Function 10.2.4
The USOUTn pin supports the open-drain output function. Default configuration is a push-pull output and it is
switch
ed to an open-drain output by setting the UAnMOD.OUTMD bit to 1.
Clock Settings10.3
UART Operating Clock10.3.1
When using the UART Ch.n, the UART Ch.n operating clock CLK_UARTn must be supplied to the UART Ch.n
from the clock generator. The CLK_UARTn supply should be controlled as in the procedure shown below.
1. Enable the clock source in the clock generator if it is stopped (refer to “Clock Gene
Reset, and Clocks” chapter).
2. Set the following UAnCLK register bits:
- UAnCLK.CLKSRC[1:0] bits (Clock source selection)
- UAnCLK.CLKDIV[1:0] bits (Clock division ratio selection = Clock frequency setting)
The UART operating clock should be selected so that the baud rate generator will be configured easily.
rator” in the “Power Supply,
Clock Supply in SLEEP Mode10.3.2
When using the UART
will keep supplying by writing 0 to the
10-2
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(Rev. 1.0)
during SLEEP mode, the UART operating clock CLK_UARTn must be configured so that it
CLGOSC.xxxxSLPC bit for the
CLK_UARTn
clock source.
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10 UART (UART)
Clock Supply in DEBUG Mode10.3.3
The CLK_UARTn supply during DEBUG mode should be controlled using the UAnCLK.DBRUN bit.
The CLK_UARTn supply to the UART Ch.n is suspended when the CPU enters DEBUG mode if the UAnCLK.
DBRUN bit = 0. After the CPU returns to normal mode, the CLK_UARTn supply resumes. Although the UART
Ch.n stops operating when the CLK_UARTn supply is suspended, the output pin and re
fore DEBUG mode was entered. If the UAnCLK.DBRUN bit = 1, the CLK_UARTn supply is not suspended and
the UART Ch.n will keep operating in DEBUG mode.
gisters retain the status be-
Baud Rate Generator10.3.4
The UART includes a baud rate generator to generate the transfer (sampling) clock. The transfer rate is determined
by the UAnBR.BRT[7:0] and UAnBR.FMD[3:0] bit settings. Use the following equation
values for obtaining the desired transfer rate.
CLK_UART CLK_UART
bps = ——————————— BRT =
{(BRT + 1) × 16 + FMD} bps
Where
CLK_UART: UART operating clock frequency [Hz]
bps: Transfer rate [bit/s]
BRT: UAnBR.BRT[7:0] setting value (0 to 255)
FMD: UAnBR.FMD[3:0] setting value (0 to 15)
—————— - FMD - 16) ÷ 16 (Eq. 10.1)
(
s to calculate the setting
For the transfer rate range configurable in the UART, refer to “UART Cha
and U
BRT2” in the “Electrical Characteristics” chapter.
racteristics, Transfer baud rates UBRT1
Data Format10.4
The UART allows setting of the data length, stop bit length, and parity function. The start bit length is fixed at one
bit.
Data length
With the UAnMOD.CHLN bit, the data length can be set to seven bits (UAnMOD.CHLN bit = 0) or eight bits
(UAnMOD.CHLN bit = 1).
Stop bit length
With the UAnMOD.STPB bit, the stop bit length can be set to one bit (UAnMOD.STPB bit = 0) or two bits
(UAnMOD.STPB bit = 1).
Parity function
The parity function is configured using the UAnMOD.PREN and UAnMOD.PRMD bits.
4.1 Parity Function SettingTable 10.
UAnMOD.PREN bit UAnMOD.PRMD bit Parity function
1 1 Odd parity
1 0 Even parity
0 * Non parity
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UAnMOD register
PREN bit
0
1
0
1
0
1
0
1
STPB bit
0
0
1
1
0
0
1
1
CHLN bit
0
0
0
0
1
1
1
1
st: start bit, sp: stop bit, p: parity bit
st
D0 D1 D2 D3 D4 D5 D6 sp
st D0 D1 D2 D3 D4 D5 D6 p sp
st D0 D1 D2 D3 D4 D5 D6 sp sp
st D0 D1 D2 D3 D4 D5 D6 p sp sp
st
D0 D1 D2 D3 D4 D5 D6 D7 sp
st D0 D1 D2 D3 D4 D5 D6 D7 p sp
st D0 D1 D2 D3 D4 D5 D6 D7 sp sp
st D0 D1 D2 D3 D4 D5 D6 D7 p sp sp
10 UART (UART)
4.1 Data FormatFigure 10.
Operations10.5
Initialization10.5.1
The UART Ch.n should be initialized with the procedure shown below.
1. Assign the UART Ch.n input/output function to the ports. (Refer to the “I/O Ports” chapter.)
2. Set the UAnCLK.CLKSRC[1:0] and UAnCLK.CLKDIV[1:0] bits. (Configure operating clock)
3. Configure the following UAnMOD register bits:
- UAnMOD.PUEN bit (Enable/disable USIN
- UAnMOD.OUTMD bit (Enable/disable USOUTn pin open-drain output)
- UAnMOD.IRMD bit (Enable/disable IrDA interface)
- UAnMOD.CHLN bit (Set 7/8-bit data length)
- UAnMOD.PREN bit (Enable/disable parity function)
- UAnMOD.PRMD bit (Even/odd parity selection)
- UAnMOD.STPB bit (Set 1/2-bit stop bit length)
4. Set the UAnBR.BRT[7:0] and UAnBR.FMD[3:0] bits. (Set transfer rate)
5. Set the follow
ing UAnCTL register bits:
- Set the UAnCTL.SFTRST bit to 1. (Execute software reset)
- Set the UAnCTL.MODEN bit to 1. (Enable UART Ch.n operations)
6. Set the following bits when using the interrupt:
- Write 1 to the interrupt flags in the UAnINTF register. (Clear interrupt flags)
- Set the interrupt enable bits in the UAnINTE register to 1. * (Enable interrupts)
* The initial value of the UAnINTF.TBEIF
UAnINTE.TBEIE bit is set to 1.
A data sending procedure and the UART Ch.n operations are shown below. Figures 10.5.2.1 and 10.5.2.2 show a
timing chart and a flowchart, respectively.
Data sending procedure
10-4
(Rev. 1.0)
1. Check to see if the UAnINTF.TBEIF bit is set to 1 (transmit buffer empty).
2. Write transmit data to t
3. Wait for a UART interrupt when using the interrupt.
4. Repeat Steps 1 to 3 (or 1 and 2) until the end of transmit data.
Seiko Epson Corporation S1C17F13 TECHNICAL MANUAL
Data Transmission10.5.2
he UAnTXD register.
n pin pull-up)
bit is 1, therefore, an interrupt will occur immediately after the
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10 UART (UART)
USOUTn
UAnINTF.TBEIF
UAnINTF.TBSY
UAnINTF.TENDIF
Software operations
st D0 D1 D2 D3 D4 D5 D6 D7 p sp st D0 D1 D7 p sp st D0 D1 D7 p sp
(st: start bit, sp: stop bit, p: parity bit)
Data (W) → UAnTXD Data (W) → UAnTXD
1 (W) → UAnINTF.TENDIFData (W) → UAnTXD
Data transmission
End
Read the UAnINTF.TBEIF bit
Write transmit data to
the UAnTXD register
YES
NO
NO
YES
Tr ansmit data remained?
UAnINTF.TBEIF = 1 ?
Wait for an interrupt request
(UAnINTF.TBEIF = 1)
UART data sending operations
The UART Ch.n starts data sending operations when transmit data is written to the UAnTXD register.
The transmit data in the UAnTXD register is automatically transferred to the shift register and the UAnINTF.
TBEIF bit is set to 1 (transmit buffer empty).
The USOUTn pin outputs a start bit and the UAnINTF.TBSY bit is set to 1 (transmit busy). The shift register
data bit
s are then output successively from the LSB. Following output of MSB, the parity bit (if parity is en-
abled) and the stop bit are output.
Even if transmit data is being output from the USOUTn pin, the next transmit data can be written to the
UAnTXD register after making sure the UAnINTF.TBEIF bit is set to 1.
If no transmit data remains in the UAnTXD register after the stop bit has been output fro
m the USOUTn pin,
the UAnINTF.TBSY bit is cleared to 0 and the UAnINTF.TENDIF bit is set to 1 (transmission completed).
5.2.1 Example of Data Sending OperationsFigure 10.
A data receiving procedure and the UART Ch.n operations are shown below. Figures 10.5.3.1 and 10.5.3.2 show a
timing chart and flowcharts, respectively.
Data receiving procedure (read by one byte)
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
(Rev. 1.0)
5.2.2 Data Transmission FlowchartFigure 10.
Data Reception10.5.3
1. Wait for a UART interrupt when using the interrupt.
2. Check to see if the UAnINTF.RB1FIF bit is set to 1 (receive buffer one byte full).
3. Read the received data from the UAnRXD register.
4. Repeat Steps 1 to 3 (or 2 and 3) until the end of data reception.
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10 UART (UART)
USINn
UAnINTF.RB1FIF
UAnINTF.RB2FIF
UAnINTF.RBSY
Software operations
st D0 ··· p sp st D0 ··· p sp st D0 ··· p sp st D0 ··· psp
(st: start bit, sp: stop bit, p: parity bit)
data 1 data 2 data 3 data 4
UAnRXD → data 1 (R) UAnRXD → data 3 (R)
UAnRXD → data 2 (R)
Data reception (1 byte read)
End
Wait for an interrupt request
(UAnINTF.RB1FIF = 1)
Read receive data (1 byte) from
the UAnRXD register
NO
YES
Receive data remained?
Data reception (2 bytes read)
End
Wait for an interrupt request
(UAnINTF.RB2FIF = 1)
Read receive data (1 byte) from
the UAnRXD register
Read receive data (1 byte) from
the UAnRXD register
NO
YES
Receive data remained?
Data receiving procedure (read by two bytes)
1. Wait for a UART interrupt when using the interrupt.
2. Check to see if the UAnINTF.RB2FIF bit is set to 1 (receive buffer two bytes full).
3. Read the received data from the UAnRXD register twice.
4. Repeat Steps 1 to 3 (or 2 and 3) until the end of data reception.
UART data receiving operations
The UART Ch.n starts data receiving operations when a start bit is input to the USINn pin.
After the receive circuit has detected a low level as a start bit, it starts sampling the following data bits and
loads the received data into the receive shift register. The UAnINTF.RBSY bit is set to 1 when the start bit is
detected.
The UAnINTF.RBSY bit is cleared to 0 and the receive shift register data is transferred to the receive data buf-
fer at the stop bit r
The receive data buffer consists of a 2-byte FIFO and receives data until it becomes full. When the receive data
buffer receives the first data, it sets the UAnINTF.RB1FIF bit to 1 (receive buffer one byte full). If the second
data is received without reading the first data, the UAnINTF.RB2FIF bit is set to 1 (receive buffer two bytes
full).
eceive timing.
This UART includes an RZI modulator/demodulator circuit enabling implementation of IrDA 1.0-compatible infrared communication function simply by adding simple external circuits.
Set the UAnMOD.IRMD bit to 1 to use the IrDA interface.
Data transfer control is identical to that for normal interface even if the IrDA interface function is
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IrDA Interface10.5.4
Seiko Epson Corporation S1C17F13 TECHNICAL MANUAL
5.3.1 Example of Data Receiving OperationsFigure 10.
5.3.2 Data Reception FlowchartsFigure 10.
enabled.
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10 UART (UART)
USINn
VDD
VSS
USOUTn
RXD
VCC
GND
TXD
LEDA
S1C17 UART Infrared communication module
AMP
GND
VCC
Modulator input (shift register output)
Modulator output (USOUTn)
UAnMOD.INVIRTX bit = 0
UAnMOD.INVIRTX bit = 1
T
1
T
1
3
16
T
1
3
16
Demodulator input (USINn)
UAnMOD.INVIRRX bit = 0
UAnMOD.INVIRRX bit = 1
Demodulator output (shift register input)
T
2
5.4.1 Example of Connections with an Infrared Communication ModuleFigure 10.
The transmit data output from the UART Ch.n transmit shift register is output from the USOUTn pin after the low
pulse width is converted into 3/16 by the RZI modulator in SIR method and inverted. The USOUTn pin output signal can be inverted by setting the UAnMOD.INVIRTX bit to 1.
5.4.2 IrDA Transmission Signal WaveformFigure 10.
The received IrDA signal is input to the RZI demodulator and the low pulse width is converted into the normal
width before input to the receive shift register. The USINn pin input signal can be inverted prior to being demodulated by setting the UAnMOD.INVIRRX bit to 1.
5.4.3 IrDA Receive Signal WaveformFigure 10.
Note: The low pulse width (T2) of the IrDA signal input must be CLK_UART × 3 cycles or longer.
Receive Errors10.6
Three different receive errors, framing error, parity error, and overrun error, may be detected while receiving data.
Since receive errors are interrupt causes, they can be processed by generating interrupts.
Framing Error10.6.1
The UART determines loss of sync if a stop bit is not detected (when the stop bit is received as 0) and assumes that
a framing error has occurred. The received data that encountered an error is still transferred to the receive data buf-
fer and the UAnINTF.FEIF bit (framing error interrupt flag) is set to 1 when the data becomes ready to read from
the UAnRXD register.
Note: Framing error/parity error interrupt flag set timings
These interrupt flags will be set after the data that encountered an error is transferred to the re-
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
(Rev. 1.0)
ceive data buffer. Note, however, that the set timing depends on the buffer status at that point.
• When the receive data buffer is empty
The interrupt flag will be set when the data that encountered an error is transferred to the re-
ceive data buffer.
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10 UART (UART)
• When the receive data buffer has a one-byte free space
The interrupt flag will be set when the first data byte already loaded is read out after the data
that encountered an error is transferred to the second byte entry of the receive data buffer.
Parity Error10.6.2
If the parity function is enabled, a parity check is performed when data is received. The UART checks matching
between the data rece
ived in the shift register and its parity bit, and issues a parity error if the result is a non-match.
The received data that encountered an error is still transferred to the receive data buffer and the UAnINTF.PEIF
bit (parity error interrupt flag) is set to 1 when the data becomes ready to read from the UAnRXD register (see the
Note on framing error).
Overrun Error10.6.3
If the receive data buffer is still full (two bytes of received data have not been read) when a data reception to the
shift register has completed, an overrun error occurs as the data cannot be transferred to the receive data buffer.
When an overrun error occurs, the UAnINTF.OEIF bit (overrun error interrupt flag) is set to 1.
Interrupts10.7
The UART has a function to generate the interrupts shown in Table 10.7.1.
7.1 UART Interrupt FunctionTable 10.
Interrupt Interrupt flag Set condition Clear condition
End of transmission UAnINTF.TENDIF When the UAnINTF.TBEIF bit = 1 after
the stop bit has been sent
Framing error UAnINTF.FEIF Refer to “Receive Errors.” Writing 1, reading received
Parity error UAnINTF.PEIF Refer to “Receive Errors.” Writing 1, reading received
Overrun error UAnINTF.OEIF Refer to “Receive Errors.” Writing 1 or software reset
Receive buffer two bytes full UAnINTF.RB2FIF When the second received data byte is
loaded to the receive data buffer in which
the first byte is already received
Receive buffer one byte full UAnINTF.RB1FIF When the first received data byte is load-
ed to the em
Transmit buffer empty UAnINTF.TBEIF When transmit data written to the trans-
mit data buffer is transferred to the shift
register
ptied receive data buffer
Writing 1 or software reset
data that encountered an
error, or software reset
data that encountere
error, or software reset
Reading received data or
software reset
Reading data to empty
the receive data buffer or
software reset
Writing transmit data
d an
The UART provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the
interrupt controller only when the interrupt flag,
of which interrupt has been enabled by the interrupt enable bit, is
set. For more information on interrupt control, refer to the “Interrupt Controller” chapter.
Control Registers10.8
UART Ch.n Clock Control Register
Register name Bit Bit name Initial Reset R/W Remarks
UAnCLK 15–9 – 0x00 – R –
8 DBRUN 0 H0 R/W
7–6 – 0x0 – R
5–4 CLKDIV[1:0] 0x0 H0 R/W
3–2 – 0x0 – R
1–0 CLKSRC[1:0] 0x0 H0 R/W
10-8
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10 UART (UART)
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the UART operating clock is supplied in DEBUG mode or not.
1 (R/W): Clock supplied in DEBUG mode
0 (R/W): No clock supplied in DEBUG mode
Bits 7–6 Reserved
Bits 5–4 CLKDIV[1:0]
These bits select the division ratio of the UART operating clock.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of the UART.
8.1 Clock Source and Division Ratio SettingsTable 10.
UAnCLK.
CLKDIV[1:0] bits
0x3 1/8 1/1 1/8 1/1
0x2 1/4 1/4
0x1 1/2 1/2
0x0 1/1 1/1
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
0x0 0x1 0x2 0x3
OSC3B OSC1 OSC3A EXOSC
UAnCLK.CLKSRC[1:0] bits
Note: The UAnCLK register settings can be altered only when the UAnCTL.MODEN bit = 0.
UART Ch.n Mode Register
Register name Bit Bit name Initial Reset R/W Remarks
UAnMOD 15–10 – 0x00 – R –
9 INVIRRX 0 H0 R/W
8 INVIRTX 0 H0 R/W
7 – 0 – R
6 PUEN 0 H0 R/W
5 OUTMD 0 H0 R/W
4 IRMD 0 H0 R/W
3 CHLN 0 H0 R/W
2 PREN 0 H0 R/W
1 PRMD 0 H0 R/W
0 STPB 0 H0 R/W
Bits 15–10 Reserved
Bit 9 INVIRRX
1 (R/W): Enable input inverting function
0 (R/W): Disable input inverting function
Bit 8 INVIRTX
1 (R/W): Enable output inverting function
0 (R/W): Disable output inverting function
Bit 7 Reserved
Bit 6 PUEN
This bit enables pull-up of the USINn pin.
1 (R/W): Enable pull-up
0 (R/W): Disable pull-up
This bit enables the USINn input inverting function when the IrDA interface function is enabled.
This bit enables the USOUTn output inverting function when the IrDA interface function is enabled.
S1C17F13 TECHNICAL MANUAL Seiko Epson Corporation
(Rev. 1.0)
10-9
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