Epson S1C17704 Technical Manual

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CMOS 16-BIT SINGLE CHIP MICROCOMPUTER

S1C17704

TECHNICAL MANUAL

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NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of Economy, Trade and Industry or other approval from another government agency.

All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies.

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S1C17704 Technical Manual Revision History

Code No. Page Chapter/Section Contents

411511901 1-2 1.1 Features Descriptions modified.

1-4 1.3.1 Pin Arrangement Part number added.

Shipping form

Part number for plastic package modified. Part number for package modified. Descriptions added.

• VFBGA10H-144 package

(10 mm  10 mm  1.0 mm, ball pitch: 0.8 mm)

TQFP24-144-pin

Figure 1.3.1.1

Part number modified.

QFP24-144-pin→TQFP24-144-pin

1-6 Part number modified.

1-7 Figure 1.3.1.4 added.

1-8 1.3.2 Pin Descriptions Table 1.3.2.1 modified.

1-9 Descriptions modified.

6-15 6.7 Details of Control Registers Description deleted.

10-11 10.8 Details of Control Registers Description modified.

11-9 11.7 16-bit Timer Output Signal Numerical value modified.

22-3 22.3.2 Frame Signal Description deleted.

22-9 22.6.1 Turning Display On and Off Table 22.6.1.1 modified.

22-15 22.8 Details of Control Registers Table 22.8.2 modified.

26-7 26.6.3 External Clock

Input AC Characteristics

27-1 27 Package Part number modified.

27-3 Part number modified.

27-4 Figure added.

28-2 28.2 Pad Coordinates Table modified.

AP-36 Appendix D Precautions on

Mounting

VFBGA7HX161→VFBGA7H-161

Figure 1.3.1.3

Part number modified.

VFBGA7HX161→VFBGA7H-161

Numbers and names of pins

(The interrupts can be used to clear standby mode even if the corresponding interrupt enable bit is set to disable interrupt.)

The PxIN[7:0] bits correspond to the Px[7:0] ports respectivel and the voltage level on the port pin is read out in the input mode...In the output mode, an indefinite value is read out.

Expression for I

(see Table 22.3.1.)

Description modified.

Table modified.

QFP24-144-pin package→TQFP24-144-pin package

VFBGA7HX161 Package→VFBGA7H-161 Package

VFBGA10H-144 Package

Coordinates modified.

Description for Noise-Induced Erratic Operations modified.

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Configuration of product number

Devices

C 17xxx F 00E1

Packing specifications

00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape & reel FRONT 0G: TCP BT 4 directions 0H : TCP BD 4 directions 0J : TCP SL 2 directions 0K : TCP SR 2 directions 0L : Tape & reel LEFT 0M: TCP ST 2 directions 0N : TCP SD 2 directions 0P : TCP ST 4 directions 0Q: TCP SD 4 directions 0R : Tape & reel RIGHT 99 : Specs not fixed

Specification

Package

D: die form; F: QFP, B: BGA

Model number

Model name

C: microcomputer, digital products

Product classification

S1: semiconductor

Development tools

S5U1

C 17000 H2 1

Packing specifications

00: standard packing

Version

1: Version 1

Tool type

Hx : ICE Dx : Evaluation board Ex : ROM emulation board Mx: Emulation memory for external ROM Tx : A socket for mounting

Cx : Compiler package Sx : Middleware package

Corresponding model number

17xxx: for S1C17xxx

Tool classification

C: microcomputer use

Product classification

S5U1: development tool for semiconductor products

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CONTENTS

– Contents –

1 Overview ........................................................................................................................1-1

1.1 Features ...........................................................................................................................1-2

1.2 Block Diagram ..................................................................................................................1-3

1.3 Pins ..................................................................................................................................1-4

1.3.1 Pin Arrangement ................................................................................................1-4

1.3.2 Pin Description ...................................................................................................1-8

2 CPU ................................................................................................................................2-1

2.1 Features of the S1C17 Core ............................................................................................2-1

2.2 CPU Registers .................................................................................................................2-2

2.3 Instruction Set ..................................................................................................................2-3

2.4 Vector Table .....................................................................................................................2-7

2.5 Processor Information ......................................................................................................2-8

3 Memory Map, Bus Control ...........................................................................................3-1

3.1 Bus Cycle .........................................................................................................................3-2

3.1.1 Restrictions on Access Size ...............................................................................3-2

3.1.2 Restrictions on Instruction Execution Cycles .....................................................3-2

3.2 Flash Area ........................................................................................................................3-3

3.2.1 Internal Flash Memory .......................................................................................3-3

3.2.2 Flash Programming ..........................................................................................3-3

3.2.3 Protect Bits ........................................................................................................3-3

0x17ffc–0x17ffe: Flash Protect Bits ........................................................................................... 3-3

3.2.4 Access Control for the Flash Controller ............................................................3-4

0x5320: FLASHC Control Register (MISC_FL) ......................................................................... 3-4

3.3 Internal RAM Area ............................................................................................................3-5

3.3.1 Internal RAM ......................................................................................................3-5

3.4 Display RAM Area ............................................................................................................3-6

3.4.1 Display RAM ......................................................................................................3-6

3.4.2 Access Control for the SRAM Controller ...........................................................3-6

0x5321: SRAMC Control Register (MISC_SR) ......................................................................... 3-6

3.5 Internal Peripheral Area ...................................................................................................3-7

3.5.1 Internal Peripheral Area 1 (0x4000–) .................................................................3-7

3.5.2 Internal Peripheral Area 2 (0x5000–) .................................................................3-7

3.5.3 I/O Map ..............................................................................................................3-8

3.6 S1C17 Core I/O Area ......................................................................................................3-11

4 Power Supply ................................................................................................................4-1

4.1 Power Supply Voltage ......................................................................................................4-1

4.2 Internal Power Supply Circuit ...........................................................................................4-2

4.3 Controlling the Power Supply Circuit ................................................................................4-3

4.4 Heavy Load Protection Function ......................................................................................4-5

4.5 Details of Control Registers .............................................................................................4-6

0x5120: VD1 Control Register (VD1_CTL) ................................................................................. 4-7

0x50a3: LCD Voltage Regulator Control Register (LCD_VREG) .............................................. 4-8

0x50a4: LCD Power Voltage Booster Control Register (LCD_PWR) ........................................ 4-9

4.6 Precautions .....................................................................................................................4-10

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5 Initial Reset ...................................................................................................................5-1

5.1 Initial Reset Sources ........................................................................................................5-1

5.1.1 #RESET Pin .......................................................................................................5-1

5.1.2 P0 Port Key-Entry Reset ...................................................................................5-2

5.1.3 Resetting by the Watchdog Timer ......................................................................5-2

5.2 Initial Reset Sequence .....................................................................................................5-3

5.3 Initial Settings After an Initial Reset .................................................................................5-4

6 Interrupt Controller (ITC) .............................................................................................6-1

6.1 Configuration of ITC .........................................................................................................6-1

6.2 Vector Table .....................................................................................................................6-2

6.3 Control of Maskable Interrupts .........................................................................................6-3

6.3.1 Enabling ITC ......................................................................................................6-3

6.3.2 Interrupt Request from Peripheral Module and Interrupt Flag ...........................6-3

6.3.3 Enabling/Disabling Interrupts .............................................................................6-4

6.3.4 Processing when Multiple Interrupts Occur .......................................................6-5

6.3.5 Interrupt Trigger Mode .......................................................................................6-6

6.3.6 Interrupt Processing by the S1C17 Core ...........................................................6-8

6.4 NMI ...................................................................................................................................6-9

6.5 Software Interrupts ..........................................................................................................6-10

6.6 Clearing HALT and SLEEP Modes by Interrupt Causes .................................................6-11

6.7 Details of Control Registers ............................................................................................6-12

0x4300: Interrupt Flag Register (ITC_IFLG) ............................................................................. 6-13

0x4302: Interrupt Enable Register (ITC_EN) ........................................................................... 6-15

0x4304: ITC Control Register (ITC_CTL) ................................................................................. 6-16

0x4306: External Interrupt Level Setup Register 0 (ITC_ELV0) ............................................... 6-17

0x4308: External Interrupt Level Setup Register 1 (ITC_ELV1) ............................................... 6-18

0x430a: External Interrupt Level Setup Register 2 (ITC_ELV2) ............................................... 6-19

0x430c: External Interrupt Level Setup Register 3 (ITC_ELV3) ............................................... 6-20

0x430e: Internal Interrupt Level Setup Register 0 (ITC_ILV0) .................................................. 6-21

0x4310: Internal Interrupt Level Setup Register 1 (ITC_ILV1) .................................................. 6-22

0x4312: Internal Interrupt Level Setup Register 2 (ITC_ILV2) .................................................. 6-23

0x4314: Internal Interrupt Level Setup Register 3 (ITC_ILV3) .................................................. 6-24

6.8 Precautions .....................................................................................................................6-25

7 Oscillator (OSC) ............................................................................................................7-1

7.1 Configuration of OSC Module ..........................................................................................7-1

7.2 OSC3 Oscillator ...............................................................................................................7-2

7.3 OSC1 Oscillator ...............................................................................................................7-4

7.4 Switching the System Clock .............................................................................................7-5

7.5 Controlling the LCD Clock ................................................................................................7-6

7.6 Controlling the 8-bit OSC1 Timer Clock ...........................................................................7-7

7.7 External Output Clock (FOUT3, FOUT1) .........................................................................7-8

7.8 Noise Filters for RESET and NMI Inputs .........................................................................7-10

7.9 Details of Control Registers ............................................................................................7-11

0x5060: Clock Source Select Register (OSC_SRC) ................................................................ 7-12

0x5061: Oscillation Control Register (OSC_CTL) .................................................................... 7-13

0x5062: Noise Filter Enable Register (OSC_NFEN) ................................................................ 7-14

0x5063: LCD Clock Setup Register (OSC_LCLK) ................................................................... 7-15

0x5064: FOUT Control Register (OSC_FOUT) ........................................................................ 7-16

0x5065: T8OSC1 Clock Control Register (OSC_T8OSC1) ...................................................... 7-17

7.10 Precautions ...................................................................................................................7-18

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8 Clock Generator (CLG) .................................................................................................8-1

8.1 Configuration of Clock Generator .....................................................................................8-1

8.2 Controlling the CPU Core Clock (CCLK) ..........................................................................8-2

8.3 Controlling the Peripheral Module Clock (PCLK) .............................................................8-3

8.4 Details of Control Registers .............................................................................................8-4

0x5080: PCLK Control Register (CLG_PCLK) .......................................................................... 8-5

0x5081: CCLK Control Register (CLG_CCLK) .......................................................................... 8-6

8.5 Precautions ......................................................................................................................8-7

9 Prescaler (PSC) .............................................................................................................9-1

9.1 Configuration of the Prescaler ..........................................................................................9-1

9.2 Details of Control Register ...............................................................................................9-2

0x4020: Prescaler Control Register (PSC_CTL) ....................................................................... 9-2

9.3 Precaution ........................................................................................................................9-3

10 I/O Ports (P) ................................................................................................................10-1

10.1 Structure of I/O Port ......................................................................................................10-1

10.2 Selecting I/O Pin Functions (Port MUX) .......................................................................10-2

10.3 Data Input/Output ..........................................................................................................10-3

10.4 Pull-Up Control ..............................................................................................................10-4

10.5 Input Interface Level .....................................................................................................10-5

10.6

Chattering Filter for P0 Ports .........................................................................................10-6

10.7 Port Input Interrupt ........................................................................................................10-7

10.8 Details of Control Registers .........................................................................................10-10

0x5200/0x5210/0x5220/0x5230: Px Port Input Data Registers (Px_IN) ................................. 10-11

0x5201/0x5211/0x5221/0x5231: Px Port Output Data Registers (Px_OUT) ........................... 10-12

0x5202/0x5212/0x5222/0x5232: Px Port I/O Direction Control Registers (Px_IO) ................. 10-13

0x5203/0x5213/0x5223/0x5233: Px Port Pull-up Control Registers (Px_PU) ......................... 10-14

0x5204/0x5214/0x5224/0x5234: Px Port Schmitt Trigger Control Registers (Px_SM) ............ 10-15

0x5205/5215: Px Port Interrupt Mask Registers (Px_IMSK) ................................................... 10-16

0x5206/5216: Px Port Interrupt Edge Select Registers (Px_EDGE) ....................................... 10-17

0x5207/5217: Px Port Interrupt Flag Registers (Px_IFLG) ...................................................... 10-18

0x5208: P0 Port Chattering Filter Control Register (P0_CHAT) .............................................. 10-19

0x5209: P0 Port Key-Entry Reset Configuration Register (P0_KRST) ................................... 10-20

0x52a0: P0 Port Function Select Register (P0_PMUX) .......................................................... 10-21

0x52a1: P1 Port Function Select Register (P1_PMUX) .......................................................... 10-22

0x52a2: P2 Port Function Select Register (P2_PMUX) .......................................................... 10-23

0x52a3: P3 Port Function Select Register (P3_PMUX) .......................................................... 10-24

10.9 Precautions ..................................................................................................................10-25

11 16-bit Timers (T16) .....................................................................................................11-1

11.1 Outline of the 16-bit Timers ...........................................................................................11-1

11.2 16-bit Timer Operating Mode .........................................................................................11-2

11.2.1 Internal Clock Mode ........................................................................................11-2

11.2.2 External Clock Mode .......................................................................................11-3

11.2.3 Pulse Width Measurement Mode ....................................................................11-4

11.3 Count Mode ...................................................................................................................11-5

11.4 16-bit Timer Reload Register and Underflow Period .....................................................11-6

11.5 Resetting the 16-bit Timer .............................................................................................11-7

11.6 16-bit Timer Run/Stop Control .......................................................................................11-8

11.7 16-bit Timer Output Signal .............................................................................................11-9

11.8 16-bit Timer Interrupt ....................................................................................................11-10

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11.9 Details of Control Registers ..........................................................................................11-11

0x4220/0x4240/0x4260: 16-bit Timer Ch.x Input Clock Select Registers (T16_CLKx) ........... 11-12

0x4222/0x4242/0x4262: 16-bit Timer Ch.x Reload Data Registers (T16_TRx) ...................... 11-13

0x4224/0x4244/0x4264: 16-bit Timer Ch.x Counter Data Registers (T16_TCx) ..................... 11-14

0x4226/0x4246/0x4266: 16-bit Timer Ch.x Control Registers (T16_CTLx) ............................. 11-15

11.10 Precautions ................................................................................................................11-17

12 8-bit Timer (T8F) .........................................................................................................12-1

12.1 Outline of the 8-bit Timer ...............................................................................................12-1

12.2 Count Mode of the 8-bit Timer .......................................................................................12-2

12.3 Count Clock ...................................................................................................................12-3

12.4 8-bit Timer Reload Register and Underflow Period .......................................................12-4

12.5 Resetting the 8-bit Timer ...............................................................................................12-5

12.6 8-bit Timer Run/Stop Control .........................................................................................12-6

12.7 8-bit Timer Output Signal ..............................................................................................12-7

12.8 Fine Mode .....................................................................................................................12-8

12.9 8-bit Timer Interrupt .......................................................................................................12-9

12.10 Details of Control Registers .......................................................................................12-10

0x4200: 8-bit Timer Input Clock Select Register (T8F_CLK) ................................................... 12-11

0x4202: 8-bit Timer Reload Data Register (T8F_TR) .............................................................. 12-12

0x4204: 8-bit Timer Counter Data Register (T8F_TC) ............................................................ 12-13

0x4206: 8-bit Timer Control Register (T8F_CTL) .................................................................... 12-14

12.11 Precautions ................................................................................................................12-16

13 PWM & Capture Timer (T16E) ...................................................................................13-1

13.1 Outline of the PWM & Capture Timer ............................................................................13-1

13.2 PWM & Capture Timer Operating Mode .......................................................................13-2

13.3 Setting/Resetting the Counter Value .............................................................................13-3

13.4 Setting Compare Data ...................................................................................................13-4

13.5 PWM & Capture Timer Run/Stop Control ......................................................................13-5

13.6 Controlling Clock Output ...............................................................................................13-6

13.7 PWM & Capture Timer Interrupt ....................................................................................13-9

13.8 Details of Control Registers .........................................................................................13-11

0x5300: PWM Timer Compare Data A Register (T16E_CA) ................................................... 13-12

0x5302: PWM Timer Compare Data B Register (T16E_CB) ................................................... 13-13

0x5304: PWM Timer Counter Data Register (T16E_TC) ........................................................ 13-14

0x5306: PWM Timer Control Register (T16E_CTL) ................................................................ 13-15

0x5308: PWM Timer Input Clock Select Register (T16E_CLK) ............................................... 13-17

0x530a: PWM Timer Interrupt Mask Register (T16E_IMSK) ................................................... 13-18

0x530c: PWM Timer Interrupt Flag Register (T16E_IFLG) ..................................................... 13-19

13.9 Precautions ..................................................................................................................13-20

14 8-bit OSC1 Timer (T8OSC1) ......................................................................................14-1

14.1 Outline of the 8-bit OSC1 Timer ....................................................................................14-1

14.2 Count Mode of the 8-bit OSC1 Timer ............................................................................14-2

14.3 Count Clock ...................................................................................................................14-3

14.4 Resetting the 8-bit OSC1 Timer ....................................................................................14-4

14.5 Setting Compare Data ...................................................................................................14-5

14.6 8-bit OSC1 Timer Run/Stop Control ..............................................................................14-6

14.7 8-bit OSC1 Timer Interrupt ............................................................................................14-7

14.8 Details of Control Registers ..........................................................................................14-9

0x50c0: 8-bit OSC1 Timer Control Register (T8OSC1_CTL) .................................................. 14-10

0x50c1: 8-bit OSC1 Timer Counter Data Register (T8OSC1_CNT) ........................................ 14-11

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0x50c2: 8-bit OSC1 Timer Compare Data Register (T8OSC1_CMP) ..................................... 14-12

0x50c3: 8-bit OSC1 Timer Interrupt Mask Register (T8OSC1_IMSK) ..................................... 14-13

0x50c4: 8-bit OSC1 Timer Interrupt Flag Register (T8OSC1_IFLG) ....................................... 14-14

14.9 Precautions ..................................................................................................................14-15

15 Clock Timer (CT) ........................................................................................................15-1

15.1 Outline of the Clock Timer .............................................................................................15-1

15.2 Operating Clock ............................................................................................................15-2

15.3 Resetting the Clock Timer .............................................................................................15-3

15.4 Clock Timer Run/Stop Control .......................................................................................15-4

15.5 Clock Timer Interrupt .....................................................................................................15-5

15.6 Details of Control Registers ..........................................................................................15-7

0x5000: Clock Timer Control Register (CT_CTL) ..................................................................... 15-8

0x5001: Clock Timer Counter Register (CT_CNT) ................................................................... 15-9

0x5002: Clock Timer Interrupt Mask Register (CT_IMSK) ...................................................... 15-10

0x5003: Clock Timer Interrupt Flag Register (CT_IFLG) ......................................................... 15-11

15.7 Precautions ..................................................................................................................15-12

16 Stopwatch Timer (SWT) .............................................................................................16-1

16.1 Outline of the Stopwatch Timer .....................................................................................16-1

16.2 BCD Counters ...............................................................................................................16-2

16.3 Operating Clock ............................................................................................................16-3

16.4 Resetting the Stopwatch Timer .....................................................................................16-4

16.5 Stopwatch Timer Run/Stop Control ...............................................................................16-5

16.6 Stopwatch Timer Interrupt .............................................................................................16-6

16.7 Details of Control Registers ..........................................................................................16-8

0x5020: Stopwatch Timer Control Register (SWT_CTL) .......................................................... 16-9

0x5021: Stopwatch Timer BCD Counter Register (SWT_BCNT) ............................................ 16-10

0x5022: Stopwatch Timer Interrupt Mask Register (SWT_IMSK) ........................................... 16-11

0x5023: Stopwatch Timer Interrupt Flag Register (SWT_IFLG) .............................................. 16-12

16.8 Precautions ..................................................................................................................16-13

17 Watchdog Timer (WDT) ..............................................................................................17-1

17.1 Outline of the Watchdog Timer ......................................................................................17-1

17.2 Operating Clock ............................................................................................................17-2

17.3 Controlling the Watchdog Timer ....................................................................................17-3

17.3.1 Selecting NMI/Reset Mode .............................................................................17-3

17.3.2 Watchdog Timer Run/Stop Control .................................................................17-3

17.3.3 Resetting the Watchdog Timer ........................................................................17-3

17.3.4 Operation in Standby Mode ............................................................................17-3

17.4 Details of Control Registers ..........................................................................................17-4

0x5040: Watchdog Timer Control Register (WDT_CTL) .......................................................... 17-5

0x5041: Watchdog Timer Status Register (WDT_ST) .............................................................. 17-6

17.5 Precautions ...................................................................................................................17-7

18 UART ...........................................................................................................................18-1

18.1 Outline of the UART ......................................................................................................18-1

18.2 UART Pins .....................................................................................................................18-2

18.3 Transfer Clock ...............................................................................................................18-3

18.4 Setting Transfer Data Conditions ..................................................................................18-4

18.5 Data Transmit/Receive Control .....................................................................................18-5

18.6 Receive Errors ..............................................................................................................18-8

18.7 UART Interrupt ..............................................................................................................18-9

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18.8 IrDA Interface ...............................................................................................................18-11

18.9 Details of Control Registers .........................................................................................18-13

0x4100: UART Status Register (UART_ST) ............................................................................ 18-14

0x4101: UART Transmit Data Register (UART_TXD) ............................................................. 18-16

0x4102: UART Receive Data Register (UART_RXD) ............................................................. 18-17

0x4103: UART Mode Register (UART_MOD) ......................................................................... 18-18

0x4104: UART Control Register (UART_CTL) ........................................................................ 18-19

0x4105: UART Expansion Register (UART_EXP) .................................................................. 18-20

18.10 Precautions ................................................................................................................18-21

19 SPI ...............................................................................................................................19-1

19.1 Configuration of the SPI ................................................................................................19-1

19.2 SPI I/O Pins ...................................................................................................................19-2

19.3 SPI Clock ......................................................................................................................19-3

19.4 Setting the Data Transfer Conditions ............................................................................19-4

19.5 Data Transmit/Receive Control .....................................................................................19-5

19.6 SPI Interrupt ..................................................................................................................19-8

19.7 Details of Control Registers .........................................................................................19-10

0x4320: SPI Status Register (SPI_ST) ................................................................................... 19-11

0x4322: SPI Transmit Data Register (SPI_TXD) ..................................................................... 19-12

0x4324: SPI Receive Data Register (SPI_RXD) ..................................................................... 19-13

0x4326: SPI Control Register (SPI_CTL) ................................................................................ 19-14

19.8 Precautions ..................................................................................................................19-16

20 I2C ................................................................................................................................20-1

20.1 Configuration of the I2C .................................................................................................20-1

20.2 I2C I/O Pins ...................................................................................................................20-2

20.3 I2C Clock .......................................................................................................................20-3

20.4 Setting before Starting Data Transfer ............................................................................20-4

20.5 Data Transmit/Receive Control .....................................................................................20-5

20.6 I2C Interrupt ..................................................................................................................20-11

20.7 Details of Control Registers .........................................................................................20-13

0x4340: I2C Enable Register (I2C_EN) ................................................................................... 20-14

0x4342: I2C Control Register (I2C_CTL) ................................................................................. 20-15

0x4344: I2C Data Register (I2C_DAT) ..................................................................................... 20-17

0x4346: I2C Interrupt Control Register (I2C_ICTL) ................................................................. 20-19

21 Remote Controller (REMC) .......................................................................................21-1

21.1 Outline of the REMC ....................................................................................................21-1

21.2 REMC I/O Pins ..............................................................................................................21-2

21.3 Carrier Generator ..........................................................................................................21-3

21.4 Setting Clock for Data Length Counter .........................................................................21-4

21.5 Controlling Data Transmission/Reception .....................................................................21-5

21.6 REMC Interrupt .............................................................................................................21-8

21.7 Details of Control Registers .........................................................................................21-10

0x5340: REMC Configuration Register (REMC_CFG) ............................................................ 21-11

0x5341: REMC Prescaler Clock Select Register (REMC_PSC) ............................................. 21-12

0x5342: REMC H Carrier Length Setup Register (REMC_CARH) .......................................... 21-13

0x5343: REMC L Carrier Length Setup Register (REMC_CARL) ........................................... 21-14

0x5344: REMC Status Register (REMC_ST) .......................................................................... 21-15

0x5345: REMC Length Counter Register (REMC_LCNT) ....................................................... 21-16

0x5346: REMC Interrupt Mask Register (REMC_IMSK) ......................................................... 21-17

0x5347: REMC Interrupt Flag Register (REMC_IFLG) ........................................................... 21-18

21.8 Precaution ....................................................................................................................21-19

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22 LCD Driver (LCD) .......................................................................................................22-1

22.1 Configuration of LCD Driver ..........................................................................................22-1

22.2 LCD Power Supply ........................................................................................................22-2

22.3 LCD Clock .....................................................................................................................22-3

22.3.1 LCD Operating Clock .....................................................................................22-3

22.3.2 Frame Signal ..................................................................................................22-3

22.4 Switching Drive Duty .....................................................................................................22-4

22.5 Display Memory ............................................................................................................22-7

22.6 Display Control ..............................................................................................................22-9

22.6.1 Turning Display On and Off .............................................................................22-9

22.6.2 LCD Contrast Adjustment ..............................................................................22-9

22.6.3 Reverse Display ..............................................................................................22-9

22.6.4 Controlling Gray Scale Display .....................................................................22-10

22.7 LCD Interrupt ................................................................................................................22-11

22.8 Details of Control Registers .........................................................................................22-13

0x50a0: LCD Display Control Register (LCD_DCTL) .............................................................. 22-14

0x50a1: LCD Contrast Adjust Register (LCD_CADJ) .............................................................. 22-16

0x50a2: LCD Clock Control Register (LCD_CCTL) ................................................................. 22-17

0x50a3: LCD Voltage Regulator Control Register (LCD_VREG) ............................................ 22-18

0x50a4: LCD Power Voltage Booster Control Register (LCD_PWR) ...................................... 22-19

0x50a5: LCD Interrupt Mask Register (LCD_IMSK) ................................................................ 22-20

0x50a6: LCD Interrupt Flag Register (LCD_IFLG) .................................................................. 22-21

22.9 Precautions ..................................................................................................................22-22

23 Supply Voltage Detector (SVD) .................................................................................23-1

23.1 Outline of the SVD module ............................................................................................23-1

23.2 Setting a Compare Voltage ..........................................................................................23-2

23.3 Controlling the SVD Operation ......................................................................................23-3

23.4 SVD Interrupt ................................................................................................................23-4

23.5 Details of Control Registers ..........................................................................................23-6

0x5100: SVD Enable Register (SVD_EN) ................................................................................ 23-7

0x5101: SVD Compare Voltage Register (SVD_CMP) ............................................................ 23-8

0x5102: SVD Detection Result Register (SVD_RSLT) ............................................................. 23-9

0x5103: SVD Interrupt Mask Register (SVD_IMSK) ............................................................... 23-10

0x5104: SVD Interrupt Flag Register (SVD_IFLG) .................................................................. 23-11

23.6 Precautions ..................................................................................................................23-12

24 On-chip Debugger (DBG) ..........................................................................................24-1

24.1 Resource Requirements and Debugging Tools .............................................................24-1

24.2 Operating Status after Debugging Break Occurs ..........................................................24-2

24.3 Details of Control Registers ..........................................................................................24-3

0x5322: OSC1 Peripheral Control Register (MISC_OSC1) ..................................................... 24-4

0xffff90: Debug RAM Base Register (DBRAM) ........................................................................ 24-5

25 Basic External Wiring Diagram ................................................................................25-1

26 Electrical Characteristics ..........................................................................................26-1

26.1 Absolute Maximum Rating ............................................................................................26-1

26.2 Recommended Operating Conditions ...........................................................................26-1

26.3 DC Characteristics ........................................................................................................26-2

26.4 Analog Circuit Characteristics .......................................................................................26-3

26.5 Current Consumption ....................................................................................................26-5

S1C17704 TECHNICAL MANUAL

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CONTENTS

26.6 AC Characteristics .........................................................................................................26-6

26.6.1 SPI AC Characteristics ...................................................................................26-6

26.6.2 I

C AC Characteristics ....................................................................................26-6

26.6.3 External Clock Input AC Characteristics .........................................................26-7

26.6.4 System AC Characteristics .............................................................................26-7

26.7 Oscillation Characteristics .............................................................................................26-8

26.8 Characteristic Plots (reference values) .........................................................................26-9

27 Package ......................................................................................................................27-1

28 Pad Layout .................................................................................................................28-1

28.1 Diagram of Pad Layout .................................................................................................28-1

28.2 Pad Coordinates ...........................................................................................................28-2

Appendix A List of I/O Registers .................................................................................. AP-1

0x4020 Prescaler .................................................................................. AP-4

0x4100–0x4105 UART (with IrDA) ..................................................................... AP-5

0x4200–0x4206 8-bit Timer (with Fine Mode) .................................................... AP-6

0x4220–0x4266 16-bit Timer .............................................................................. AP-7

0x4300–0x4314 Interrupt Controller ................................................................... AP-9

0x4320–0x4326 SPI .......................................................................................... AP-11

0x4340–0x4346 I

C ........................................................................................... AP-12

0x5000–0x5003 Clock Timer ............................................................................. AP-13

0x5020–0x5023 Stopwatch Timer ..................................................................... AP-14

0x5040–0x5041 Watchdog Timer ...................................................................... AP-15

0x5060–0x5065 Oscillator ................................................................................. AP-16

0x5080–0x5081 Clock Generator ...................................................................... AP-17

0x50a0–0x50a6 LCD Driver .............................................................................. AP-18

0x50c0–0x50c4 8-bit OSC1 Timer .................................................................... AP-19

0x5100–0x5104 SVD Circuit ............................................................................. AP-20

0x5120 Power Generator .................................................................... AP-21

0x5200–0x52a3 P Port & Port MUX .................................................................. AP-22

0x5300–0x530c PWM & Capture Timer ............................................................ AP-24

0x5320–0x5322 MISC Registers ....................................................................... AP-25

0x5340–0x5347 Remote Controller ................................................................... AP-26

0xffff80–0xffff90 S1C17 Core I/O ......................................................................AP-27

Appendix B Flash Programming ................................................................................. AP-28

B.1 Programming from Debugger ....................................................................................... AP-28

B.2 Self-Programming by Application Program ................................................................... AP-29

Appendix C Power Saving ........................................................................................... AP-30

C.1 Power Saving by Clock Control ................................................................................... AP-30

C.2 Power Saving by Power Supply Control ....................................................................... AP-33

Appendix D Precautions on Mounting ....................................................................... AP-34

Appendix E Initialize Routine ...................................................................................... AP-38

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S1C17704 TECHNICAL MANUAL

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1 OVERVIEW

1 Overview

The S1C17704 is a 16-bit MCU that features high-speed operation, low power consumption, small size, large address space, and on-chip ICE. The S1C17704 consists of an S1C17 CPU Core, a 64K-byte Flash memory, a 4K-byte RAM, serial interface modules (UART that supports high bit rate and IrDA 1.0, SPI and I connecting various sensor modules, 8-bit timers, 16-bit timers, a PWM & capture timer, a clock timer, a stopwatch timer, a watchdog timer, 28 GPIO ports, an LCD driver with 56-segment × 32-common outputs and a voltage booster, a supply voltage detector, 32 kHz (typ.) and 8.2 MHz (max.) oscillators, and a voltage regulator for generating the 1.8 V internal voltage. The S1C17704 is capable of high-speed operation (8.2 MHz) with low operating voltage (1.8 V). Its 16-bit RISC processor executes one instruction in 1 clock cycles. The S1C17704 also provides an on-chip ICE function that allows on-board erasing/programming of the embedded Flash memory, on-board debugging and evaluating the program by connecting the S1C17704 to the ICD Mini (S5U1C17001H) with only three wires. The S1C17704 is suitable for battery driven applications with sensor interfaces and up to 56 × 32-dot LCD display, such as remote controllers and sports watches. The product lineup offers two S1C17704 models with a different main oscillator.

Main (OSC3) oscillator • Crystal/ceramic oscillator 8.2 MHz (max.)

• CR oscillator 2.2 MHz (max.)

∗ This product uses SuperFlash® Technology licensed from Silicon Storage Technology, Inc.

C) for

S1C17704 TECHNICAL MANUAL EPSON

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Page 14

1 OVERVIEW

1.1 Features

The main functions and features of the S1C17704 are outlined below.

CPU • Seiko Epson original 16-bit RISC CPU core S1C17

Main (OSC3) oscillator • Crystal/ceramic oscillator 8.2 MHz (max.)

• CR oscillator 2.2 MHz (max.)

Sub (OSC1) oscillator • Crystal oscillator 32.786 kHz (typ.)

On-chip Flash memory • 64K bytes (for instructions and data)

• 1,000 erase/program cycles

• Read/program protection

• On-board programming by a debugging tool such as ICD Mini (S5U1C17704H) and self-programming by software control

On-chip RAM • 4K bytes

On-chip display RAM • 576 bytes

I/O ports • Max. 28 general-purpose I/O ports (Pins are shared with the peripheral I/O.)

Serial interfaces • SPI (master/slave) 1 ch.

• I2C (master) 1 ch.

• UART (115200 bps, IrDA 1.0) 1 ch.

• Remote controller (REMC) 1 ch.

Timers • 8-bit timer (T8F) 1 ch.

• 16-bit timer (T16) 3 ch.

• PWM & capture timer (T16E) 1 ch.

• Clock timer (CT) 1 ch.

• Stopwatch timer (SWT) 1 ch.

• Watchdog timer (WDT) 1 ch.

• 8-bit OSC1 timer (T8OSC1) 1 ch.

LCD driver • 56 SEG × 32 COM or 72 SEG × 16 COM (1/5 bias)

• Built-in voltage booster

Supply voltage detector (SVD) • 13 programmable detection levels (1.8 V to 2.7 V)

Interrupts • Reset

• NMI

• 16 programmable interrupts (8 levels)

Power supply voltage • 1.8 V to 3.6 V (for normal (low-power) operation with the 1.8 V internal voltage)

• 2.7 V to 3.6 V (for Flash erasing/programming with the 2.5 V internal voltage)

Operating temperature • -20°C to 70°C

Current consumption • SLEEP state: 1 µA typ.

• HALT state: 2.6 µA typ. (32 kHz OSC1 crystal oscillator, LCD off)

• Run state: 17 µA typ. (32 kHz OSC1 crystal oscillator, LCD off)

1950 µA typ. (8 MHz OSC3 ceramic oscillator, LCD off)

Shipping form • TQFP24-144pin plastic package (16 mm × 16 mm × 1.0 mm, lead pitch: 0.4 mm)

• PFBGA6U96 package*

(6 mm × 6 mm × 1.0 mm, ball pitch: 0.5 mm)

• VFBGA7H-161 package

(7 mm × 7 mm × 1.0 mm, ball pitch: 0.5 mm)

• VFBGA10H-144 package

(10 mm × 10 mm × 1.0 mm, ball pitch: 0.8 mm)

• Chip

Note: The LCD driver cannot be used with the PFBGA6U96 package. It should be used with COM31 to

16 left open.

1-2

EPSON S1C17704 TECHNICAL MANUAL

Page 15

1.2 Block Diagram

1 OVERVIEW

TEST1–3

#TEST Test circuit

#RESET

EXCL0–2

(P16, P07, P06)

SIN, SOUT, SCLK

(P23–25)

SDI, SDO, SPICLK

(P20–22)

SDA, SCL

(P14–15)

RD: 1 cycle, WR: 1 cycle

32 bits

Internal RAM

(4K bytes)

Flash memory

(64K bytes)

Display RAM

(576 bytes)

Reset circuit

I/O 1 (0x4000–)

Interrupt controller

8-bit timer

16-bit timer

Prescaler

UART

SPI

I2C

CPU Core S1C17

16 bits

1–5

cycles

8 bits

2–5 cycles

8/16 bits

1 cycle

8/16 bits 3 cycles

Interrupt system

I/O 2 (0x5000–)

Power generator

SVD circuit

LCD driver

MISC register

Oscillator/

Clock generator

8-bit OSC1 timer

Clock timer

Stopwatch timer

Watchdog timer

PWM & capture

timer

Remote controller

I/O port/ I/O MUX

DCLK, DST2, DSIO(P31–33)

DD, VSS, D1, VD2,

V V

C1–VC5,

CA–CG

SEG0–55/71, COM0–31/15

OSC1–2, OSC3–4 FOUT1(P13), FOUT3(P30)

EXCL3(P27), TOUT(P26)

REMI(P04), REMO(P05)

P00–07, P10–17, P20–27, P30–33

Figure 1.2.1 Block Diagram

S1C17704 TECHNICAL MANUAL EPSON

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Page 16

1 OVERVIEW

1.3 Pins

1.3.1 Pin Arrangement

TQFP24-144-pin

P02 P01

P00 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9

COM10 COM11 COM12 COM13 COM14 COM15

SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8

SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16

VDD

P03

P10

P11

P12

P13/FOUT1

P04/REMI

P05/REMO

P06/EXCL2

P07/EXCL1

P14/SDA

P15/SCL

P16/EXCL0

P17/#SPISS

P20/SDI

P21/SDO

P22/SPICLK

P23/SIN

P24/SOUT

P25/SCLK

P26/TOUT

P27/EXCL3

P30/FOUT3

DCLK/P31

DST2/P32

DSIO/P33

#RESET

#TEST

108

107

106

105

104 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144

1234567891011121314151617181920212223242526272829303132333435

103

999897969594939291908988878685848382818079787776757473

102

101

100

OSC2

OSC1

VD1VSS

OSC4

OSC3

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37

VC2 VC3 VC4 VC5 CA CB CC CD CE CF CG V

TEST3 TEST2 TEST1 V

COM16/SEG71 COM17/SEG70 COM18/SEG69 COM19/SEG68 COM20/SEG67 COM21/SEG66 COM22/SEG65 COM23/SEG64 COM24/SEG63 COM25/SEG62 COM26/SEG61 COM27/SEG60 COM28/SEG59 COM29/SEG58 COM30/SEG57 COM31/SEG56 SEG55 SEG54 SEG53

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

Figure 1.3.1.1 Pin Arrangement (TQFP24-144-pin)

1-4

EPSON S1C17704 TECHNICAL MANUAL

Page 17

PFBGA6U96

A1 Corner A1 Corner

1 OVERVIEW

Top View Bottom View

234567891011

N.C. N.C. N.C.

CB VC5 VC4

TEST2 CG CC

COM16

SEG71

COM21

SEG66

COM30

SEG57

VSS

COM20

SEG67

COM27

SEG60

N.C.

COM28

SEG59

COM29

SEG58

N.C.

COM31

SEG56

N.C.

2345678

A B C D E F G H J K L

TEST1

COM19

SEG68

COM25

SEG62

COM26

SEG61

Index

11109876543211234567891011

DSIO

P33

#RESET

#TEST

P24

SOUT

P27

EXCL3

DST2

P32

P21

SDO

P22

SPICLK

P23

SIN

P00

P16

EXCL0

P17

#SPISS

Top View

COM24

SEG63

COM23

SEG64

N.C.

COM22

SEG65

N.C.

Figure 1.3.1.2 Pin Arrangement （PFBGA6U96）

COM17

SEG70

COM18

SEG69

N.C.

TEST3

N.C.

VD2

N.C.

P02

P01

P15

SCL

A B C D E F G H J K L

P12

P05

REMO

P14

SDA

P26

TOUT

DCLK

P31

VSS

VC1

VC3

P03

P11

P04

REMI

P07

EXCL1

N.C. N.C.

P25

SCLK

P30

FOUT3

OSC2 OSC1

OSC4

VC2

VDDVSS

P10

P13

FOUT1

P06

EXCL2

P20

SDI

VD1

N.C.

OSC3

VDD

91011

N.C.

Note: The LCD driver cannot be used with the PFBGA6U96 package. It should be used with COM31 to

16 left open.

S1C17704 TECHNICAL MANUAL EPSON

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Page 18

1 OVERVIEW

VFBGA7H-161

A1 Corner A1 Corner

Top View Bottom View

SEG17

SEG20

SEG23

SEG27

Index

B C D E F G H

J K L M N

123456789

234567891011

SEG16

SEG12

SEG10

SEG7

10 11 1213

SEG3

COM15

13 12 1110

COM12

987654321

COM6

COM4 COM0

A B C D E F G H J K L M N

P01

N.C.

SEG15

SEG13

SEG8

SEG6

SEG2

COM14

COM9

COM7

COM3

P00

P02

N.C.

P03

SEG18

SEG14

SEG11

SEG9

SEG4

COM13

COM11

COM8

COM2

P12

P11

P10

SEG22

SEG26

SEG21

SEG25

SEG19

SEG24

SEG5

VSS

SEG1 SEG0

VSS VSS VSS

COM10

COM5

VDD

COM1

P06

EXCL2

P13

FOUT1

P07

EXCL1

P04

REMI

P14

SDA

P05

REMO

P15

SCL

SEG30

SEG33

SEG37

SEG40

SEG29

SEG32

SEG36

SEG41

SEG28

SEG34

SEG38

SEG42

SEG31

SEG35

SEG39

SEG43

VSS VSS

VSS

Top View

VSS

VSS VSS VSS

TEST3

VDD

VSS

VDD

P16

EXCL0

P17

#SPISS

P27

EXCL3

VC4

SEG44

SEG45

SEG46

SEG48

SEG47

SEG49

SEG52

SEG51

SEG53

N.C. N.C.

SEG50

SEG54

SEG55

COM31

SEG56

COM30

SEG57

COM29

SEG58

2345678

COM28

SEG59

COM27

SEG60

COM26

SEG61

COM25

SEG62

COM24

SEG63

COM23

SEG64

COM22

SEG65

COM21

SEG66

TEST2

COM20

SEG67

COM19

SEG68

COM18

SEG69

TEST1

COM17

SEG70

SEG71

VD2

VC5

CCCOM16

910111212

P20

SDI

P23

SIN

P26

TOUT

DST2

P32

#TEST

VC1

VC3

Figure 1.3.1.3 Pin Arrangement （VFBGA7H-161）

P21

SDO

P24

SOUT

P30

FOUT3

#RESET

OSC2 OSC1

VD1

OSC4VC2

OSC3

P22

SPICLK

P25

SCLK

DCLK

P31

DSIO

P33

VSS

VDD

1-6

EPSON S1C17704 TECHNICAL MANUAL

Page 19

VFBGA10H-144

A1 Corner A1 Corner

1 OVERVIEW

Top View Bottom View

SEG17

SEG18

SEG20

SEG23

SEG27

Index

B C D E F G H J K L M

123456789

234567891011

SEG14

SEG11

SEG06

10 11 12

SEG03

COM14

COM10

12 11 10

987654321

COM06

COM02

P00 P02

A B C D E F G H J K L

VSS

SEG16

SEG13

SEG10

SEG04

COM15

COM09

COM07

COM01

P01

P03

P10

SEG19

SEG22

SEG26

SEG15

SEG21

SEG25

SEG09

SEG12

SEG24

SEG05

SEG07

SEG08

SEG00

SEG01 COM11

SEG02 COM12 COM03

COM08

COM05

COM04

COM00

P06

EXCL2

P07

EXCL1

P12

P13

FOUT1

P17

SPISS

P11

P05

REMO

P16

EXCL0

P04

REMI

P14

SDA

P15

SCL

SEG30

SEG34

SEG38

SEG43

SEG47

SEG50

SEG52

SEG29

SEG28

SEG31

SEG32 TEST2

COM13

VDD

P23

SIN

Top View

SEG33

SEG42

SEG45

SEG49

SEG51

SEG53

SEG35

SEG41

SEG44

SEG48

SEG54

SEG55

SEG36

SEG40

SEG46

COM31

SEG56

COM30

SEG57

COM29

SEG58

SEG37

SEG39

COM28

SEG59

COM27

SEG60

COM26

SEG61

COM25

SEG62

TEST1

COM24

SEG63

COM23

SEG64

COM22

SEG65

COM21

SEG66

COM20

SEG67

TEST3

VSS

COM19

SEG68

SEG69

COM16

SEG71

COM17

SEG70

P24

SOUT

VDD

TEST

2345678910111212

P26

TOUT

P30

FOUT3

P20

SDI

P27

EXCL3

DST2

P32

VSS

VC5COM18

VC3VD2

P21

SDO

P25

SCLK

RESET

OSC2

OSC4

VC1VC4

VC2

P22

SPICLK

DCLK

P31

DSIO

P33

OSC1

VD1

OSC3

VDD

Figure 1.3.1.4 Pin Arrangement （VFBGA10H-144）

S1C17704 TECHNICAL MANUAL EPSON

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1 OVERVIEW

1.3.2 Pin Descriptions

Pin No.

QFP PFBGA

VFBGA7

1 to 39 – ∗1 ∗2

40 to 55 ∗3 ∗4 ∗5

56 F2 ∗6 ∗7 57 F3 K8 G6 58 E1 K7 F6 59 J7 J8 G7 60 K7 N8 M8 61 E2 L9 L8 62 J8 M9 K8 63 L8 N9 J8 64 K8 K9 J9 65 E3 M10 K9 66 D1 N10 L9 67 L9 L10 M9 68 D2 K10 K10 69 D3 J10 L10 70 K9 N11 M10 71 L10 M11 M11 72 J9 L11 L11 73 L11 ∗8 ∗9 74 K11 N12 L12 75 K10 M12 K11 76 H9 ∗6 ∗7 77 J11 L12 K12

78 H11 K13 J12 79 H10 K12 J11 80 C4 K11 H8

81 B4 J12 H11 82 A4 J13 H12

83 C5 J11 H10

84 G9 H13 G12

85 G10 H12 H9

86 B5 H10 G10

87 F9 H11 G9 88 F10 G13 G11 89 A5 G12 G8 90 C6 G11 F9 91 B6 F13 F12 92 A6 F12 F11 93 E11 F11 F10 94 C7 G10 E10

95 B7 F10 E11

VFBGA10

Table 1.3.2.1 Pin Descriptions

Name I/O

SEG17 to 55 COM31 to 16/

Default

status

OO（L） LCD segment output pin OO（L） LCD common output pin*/LCD segment output pin

SEG56 to 71

TEST1 TEST2 TEST3 V

CG CF CE CD CC CB CA V

OSC3 OSC4 V

OSC1 OSC2 #TEST

(PFBGA, VFBGA7)

– – Power supply pin (GND) – – Flash test pin (open in normal operation) – – Flash test pin (fixed at High in normal operation) – – Flash test pin (open in normal operation) – – LCD circuit power supply booster output pin – – Power supply booster capacitor connector pin – – Power supply booster capacitor connector pin – – LCD booster capacitor connector pin – – LCD booster capacitor connector pin – – LCD booster capacitor connector pin – – LCD booster capacitor connector pin – – LCD booster capacitor connector pin – – LCD circuit drive voltage output pin – – LCD circuit drive voltage output pin – – LCD circuit drive voltage output pin – – LCD circuit drive voltage output pin – – LCD circuit drive voltage output pin – – Power supply pin (+)

I I OSC3 oscillator input pin

O O OSC3 oscillator output pin

– – Power supply pin (GND) – – Internal logic and oscillator circuit constant-voltage

I I OSC1 oscillator input pin

O O OSC1 oscillator output pin

II（Pull-UP）Test pin (fixed at High in normal operation)

VDD/#TEST

(VFBGA10)

#RESET DSIO/P33

DST2/P32

DCLK/P31

P30/FOUT3

P27/EXCL3

P26/TOUT P25/SCLK P24/SOUT P23/SIN P22/SPICLK P21/SDO P20/SDI P17/#SPISS

P16/EXCL0

II（Pull-UP）Initial set input pin

I/O I（Pull-UP）

I/O O（L）

I/O O（H） On-chip debugger clock output pin*/ input/output

I/O I（Pull-UP）Input/output port pin*/ OSC3 dividing clock output

I/O I（Pull-UP）Input/output port pin*/T16E external clock input

I/O I（Pull-UP）Input/output port pin*/T16E PWM signal output pin I/O I（Pull-UP）Input/output port pin*/UART clock input pin I/O I（Pull-UP）Input/output port pin*/UART data output pin I/O I（Pull-UP）Input/output port pin*/UART data input pin I/O I（Pull-UP）Input/output port pin*/SPI clock input/output pin I/O I（Pull-UP）Input/output port pin*/SPI data output pin I/O I（Pull-UP）Input/output port pin*/SPI data input pin I/O I（Pull-UP）Input/output port pin (with interrupt)*/SPI slave

I/O I（Pull-UP）Input/output port pin (with interrupt)*/T16 Ch.0

Function

circuit output pin

On-chip debugger data input/output pin*/ input/output port pin On-chip debugger status output pin*/ input/output port pin

port pin

select input pin

external clock input pin

1-8

EPSON S1C17704 TECHNICAL MANUAL

Page 21

1 OVERVIEW

Pin No.

QFP PFBGA

VFBGA7

VFBGA10

96 C8 E13 E12

Name I/O

P15/SCL

Default

status

Function

I/O I（Pull-UP）Input/output port pin (with interrupt)*/I2C clock

output pin

97 D9 E12 D12

P14/SDA

I/O I（Pull-UP）Input/output port pin (with interrupt)*/I

C data

input/output pin

98 D10 E11 E9

P07/EXCL1

I/O I（Pull-UP）Input/output port pin (with interrupt)*/T16 Ch.1

external clock input pin

99 D11 E10 D9

P06/EXCL2

I/O I（Pull-UP）Input/output port pin (with interrupt)*/T16 Ch.2

external clock input pin

100 C9 D13 D11

P05/REMO

I/O I（Pull-UP）Input/output port pin (with interrupt)*/Remote out-

put pin

101 C10 D12 C12

P04/REMI

I/O I（Pull-UP）Input/output port pin (with interrupt)*/Remote input

102 C11 D11 D10

P13/FOUT1

I/O I（Pull-UP）

Input/output port pin (with interrupt)*/OSC1 clock

output pin 103 B9 C11 C10 104 B10 C12 C11 105 B11 C13 B12 106 A10 B13 B11 107 A11 ∗8 ∗9 108 A9 ∗6 ∗7 109 A8 B12 A11 110 B8 A12 B10

111 A7 B11 A10

112 to 127

128 to 144

– ∗10 ∗11 – ∗12 ∗13

P12 P11 P10 P03 V

P02 P01 P00 COM0 to 15 SEG0 to 16

I/O I（Pull-UP）Input/output port pin (with interrupt) I/O I（Pull-UP）Input/output port pin (with interrupt) I/O I（Pull-UP）Input/output port pin (with interrupt) I/O I（Pull-UP）Input/output port pin (with interrupt)

– – Power supply (+) – – Power supply (GND)

I/O I（Pull-UP）Input/output port pin (with interrupt) I/O I（Pull-UP）Input/output port pin (with interrupt) I/O I（Pull-UP）Input/output port pin (with interrupt)

OO（L） LCD common output pin OO（L） LCD segment output pin

∗1: SEG17 to SEG55（VFBGA7） B1, C2, D4, C1, D3, D2, D1, E4, E3, E2, E1, F3, F2, F1, F4, G2, G1, G3, G4, H2, H1, H3, H4, J1, J2, J3, J4, K1,

K2, K3, L1, K4, L2, L3, M2, M1, N2, M3, N3

∗2: SEG17 to SEG55（VFBGA10） A1, B1, C2, C1, D3, D2, D1, E4, E3, E2, E1, F3, F2, F1, F4, F5, G2, G1, G3, G4, G5, H1, H5, H4, H3, H2, J1, J3,

J2, J4, K1, K3, K2, L1, L2, M1, M2, L3, M3

∗3: COM31 to 16/SEG56 to 71（PFBGA） L2, J1, K2, J2, H2, J3, H3, J4, K4, L4, G1, G2, G3, K5, J5, F1 ∗4: COM31 to 16/SEG56 to 71（VFBGA7） L4, M4, N4, K5, L5, M5, N5, K6, L6, M6, N6, L7, M7, N7, L8, M8 ∗5: COM31 to 16/SEG56 to 71（VFBGA10） K4, L4, M4, J5, K5, L5, M5, H6, J6, K6, L6, M6, J7, K7, M7, L7 ∗6: VSS（VFBGA7） E5, E6, E7, E8, F5, F6, G5, G9, H5, H9, J5, J6, J7, L13 ∗7: VSS（VFBGA10） A12, H7, J10 ∗8: VDD（VFBGA7） E9, F9, J9, M13 ∗9: VDD（VFBGA10） F8, M12 ∗ 10: COM0 to 15（VFBGA7） A11, D10, C10, B10, A10, D9, A9, B9, C9, B8, D8, C8, A8, C7, B7, A7 ∗ 11: COM0 to 15（VFBGA10） C9, B9, A9, E8, D8, C8, A8, B8, C7, B7, A7, D7, E7, F7, A6, B6 ∗ 12: SEG0 to 16（VFBGA7） D7, D6, B6, A6, C6, D5, B5, A5, B4, C5, A4, C4, A3, B3, C3, B2, A2 ∗ 13: SEG0 to 16（VFBGA10） C6, D6, E6, A5, B5, C5, A4, D5, E5, C4, B4, A3, D4, B3, A2, C3, B2

Note: Bold text (for pins) and an asterisk (for functions) indicate default settings.

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1 OVERVIEW

THIS PAGE IS BLANK.

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The S1C17704 contains the S1C17 Core as its core processor. The S1C17 Core is a Seiko Epson original 16-bit RISC-type processor. It features low power consumption, high-speed operation, large address space, main instructions executable in one clock cycle, and a small sized design. The S1C17 Core is suitable for embedded applications such as controllers and sequencers for which an eight-bit CPU is commonly used. For details of the S1C17 Core, refer to the “S1C17 Family S1C17 Core Manual.”

2.1 Features of the S1C17 Core

Processor type

• Seiko Epson original 16-bit RISC processor

• 0.35–0.15 µm low power CMOS process technology

Instruction set

• Code length: 16-bit fixed length

• Number of instructions: 111 basic instructions (184 including variations)

• Execution cycle: Main instructions executed in one cycles

• Extended immediate instructions: Immediate extended up to 24 bits

• Compact and fast instruction set optimized for development in C language

• Eight 24-bit general-purpose registers

• Two 24-bit special registers

• One 8-bit special register

Memory space and bus

• Up to 16M bytes of memory space (24-bit address)

• Harvard architecture using separated instruction bus (16 bits) and data bus (32 bits)

Interrupts

• Reset, NMI, and 32 external interrupts supported

• Address misaligned interrupt

• Debug interrupt

• Direct branching from vector table to interrupt handler routine

• Programmable software interrupts with a vector number specified (all vector numbers specifiable)

Power saving

• HALT (halt instruction)

• SLEEP (slp instruction)

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2.2 CPU Registers

The S1C17 Core contains eight general-purpose registers and three special registers.

Special registers

bit 23

PC SP

765IE4C3V2Z1N0

IL[2:0]

bit 0

PSR

Figure 2.2.1 Registers

General-purpose registers

bit 23 bit 0

7 6 5 4 3 2 1 0

R7 R6 R5 R4 R3 R2 R1 R0

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2.3 Instruction Set

The S1C17 Core instruction codes are all fixed to 16 bits in length which, combined with pipelined processing, allows most important instructions to be executed in one cycle. For details, refer to the “S1C17 Family S1C17 Core Manual.”

Table 2.3.1 List of S1C17 Core Instructions

Classification Mnemonic Function

Data transfer

ld.b %rd,%rs

ld.ub %rd,%rs

ld %rd,%rs

ld.a %rd,

%rd,[%rb]

%rd,[%rb]+

%rd,[%rb]-

%rd,-[%rb]

%rd,[%sp+imm7]

%rd,[imm7]

[%rb],%rs

[%rb]+,%rs

[%rb]-,%rs

-[%rb],%rs

[%sp+imm7],%rs

[imm7],%rs

%rd,[%rb]

%rd,[%rb]+

%rd,[%rb]-

,-[%rb]

%rd

%rd,[%sp+imm7]

%rd,[imm7]

%rd,sign7

%rd,[%rb]

%rd,[%rb]+

%rd,[%rb]-

%rd,-[%rb]

%rd,[%sp+imm7]

%rd,[imm7]

[%rb],%rs

[%rb]+,%rs

[%rb]-,%rs

-[%rb],%rs

[%sp+imm7],%rs

[imm7],%rs

%rs

%rd,imm7

%rd,[%rb]

%rd,[%rb]+

%rd,[%rb]-

%rd,-[%rb]

%rd,[%sp+imm7]

%rd,[imm7]

[%rb],%rs

[%rb]+,%rs

[%rb]-,%rs

-[%rb],%rs

[%sp+imm7],%rs

[imm7],%rs

%rd,%sp

%rd,%pc

,[%sp]

%rd

%rd,[%sp]+

%rd,[%sp]-

%rd,-[%sp]

General-purpose register (byte) → general-purpose register (sign-extended) Memory (byte) → general-purpose register (sign-extended) Memory address post-increment, post-decrement, and pre-decrement functions can be used.

Stack (byte) → general-purpose register (sign-extended) Memory (byte) → general-purpose register (sign-extended) General-purpose register (byte) → memory Memory address post-increment, post-decrement, and pre-decrement functions can be used.

General-purpose register (byte) → stack General-purpose register (byte) → memory General-purpose register (byte) → general-purpose register (zero-extended) Memory (byte) → general-purpose register (zero-extended) Memory address post-increment, post-decrement, and pre-decrement functions can be used.

Stack (byte) → general-purpose register (zero-extended) Memory (byte) → general-purpose register (zero-extended) General-purpose register (16 bits) → general-purpose register Immediate → general-purpose register (sign-extended) Memory (16 bits) → general-purpose register Memory address post-increment, post-decrement, and pre-decrement functions can be used.

Stack (16 bits) → general-purpose register Memory (16 bits) → general-purpose register General-purpose register (16 bits) → memory Memory address post-increment, post-decrement, and pre-decrement functions can be used.

General-purpose register (16 bits) → stack General-purpose register (16 bits) → memory General-purpose register (24 bits) → general-purpose register Immediate → general-purpose register (zero-extended) Memory (32 bits) → general-purpose register (∗1) Memory address post-increment, post-decrement, and pre-decrement functions can be used.

Stack (32 bits) → general-purpose register (∗1) Memory (32 bits) → general-purpose register (∗1) General-purpose register (32 bits, zero-extended) → memory (∗1) Memory address post-increment, post-decrement, and pre-decrement functions can be used.

General-purpose register (32 bits, zero-extended) → stack (∗1) General-purpose register (32 bits, zero-extended) → memory (∗1) SP → general-purpose register PC → general-purpose register Stack (32 bits) → general-purpose register (∗1) Stack pointer post-increment, post-decrement, and pre-decrement functions can be used.

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Classification Mnemonic Function

Data transfer

Integer arithmetic operation

Logical operation

ld.a [%sp],%rs

add %rd,%rs

add/c

add/nc

add %rd,imm7

add.a %rd,%rs

add.a/c

add.a/nc

add.a %sp,%rs

adc %rd,%rs

adc/c

adc/nc

adc %rd,imm7

sub %rd,%rs

sub/c

sub/nc

sub %rd,imm7

sub.a %rd,%rs

sub.a/c

sub.a/nc

sub.a %sp,%rs

sbc %rd,%rs

sbc/c

sbc/nc

sbc %rd,imm7

cmp %rd,%rs

cmp/c

cmp/nc

cmp %rd,sign7

cmp.a %rd,%rs

cmp.a/c

cmp.a/nc

cmp.a %rd,imm7

cmc %rd,%rs

cmc/c

cmc/nc

cmc %rd,sign7

and %rd,%rs

and/c

and/nc

and %rd,sign7

or %rd,%rs

or/c

or/nc

or %rd,sign7

xor %rd,%rs

xor/c

xor/nc

xor %rd,sign7

not %rd,%rs

not/c

not/nc

not %rd,

[%sp]+,%rs

[%sp]-,%rs

-[%sp],%rs

%sp,%rs

%sp,imm7

%rd,imm7

%sp,imm7

%rd,imm7

%sp,imm7

sign7

General-purpose register (32 bits, zero-extended) → stack (∗1) Stack pointer post-increment, post-decrement, and pre-decrement functions can be used.

General-purpose register (24 bits) → SP Immediate → SP 16-bit addition between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

16-bit addition of general-purpose register and immediate 24-bit addition between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

24-bit addition of SP and general-purpose register 24-bit addition of general-purpose register and immediate 24-bit addition of SP and immediate 16-bit addition with carry between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

16-bit addition of general-purpose register and immediate with carry 16-bit subtraction between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

16-bit subtraction of general-purpose register and immediate 24-bit subtraction between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

24-bit subtraction of SP and general-purpose register 24-bit subtraction of general-purpose register and immediate 24-bit subtraction of SP and immediate 16-bit subtraction with carry between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

16-bit subtraction of general-purpose register and immediate with carry 16-bit comparison between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

16-bit comparison of general-purpose register and immediate 24-bit comparison between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

24-bit comparison of general-purpose register and immediate 16-bit comparison with carry between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

16-bit comparison of general-purpose register and immediate with carry Logical AND between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

Logical AND of general-purpose register and immediate Logical OR between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

Logical OR of general-purpose register and immediate Exclusive OR between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

Exclusive OR of general-purpose register and immediate Logical inversion between general-purpose registers (1's complement) Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

Logical inversion of general-purpose register and immediate (1's complement)

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Classification Mnemonic Function

Shift and swap

Immediate extension Conversion

Branch

System control

ld.a

∗1 The

sr %rd,%rs

sa %rd,%rs

sl %rd,%rs

swap %rd,%rs

ext imm13

cv.ab %rd,%rs

cv.as %rd,%rs

cv.al %rd,%rs

cv.la %rd,%rs

cv.ls %rd,%rs

jpr

jpr.d

jpa

ipa.d

jrgt

jrgt.d

jrge

jrge.d

jrlt

jrlt.d

jrle

jrle.d

jrugt

jrugt.d

jruge

jruge.d

jrult

jrult.d

jrule

jrule.d

jreq

jreq.d

jrne

jrne.d

call

call.d

calla

calla.d

ret

ret.d

int imm5

intl imm5,imm3

reti

reti.d

brk

retd

nop

halt slp

%rd,imm7

sign10

%rb

imm7

%rb

sign7

sign10

%rb

imm7

%rb

Logical shift to the right with the number of bits speciﬁ ed by the register Logical shift to the right with the number of bits speciﬁ ed by immediate Arithmetic shift to the right with the number of bits speciﬁ ed by the register Arithmetic shift to the right with the number of bits speciﬁ ed by immediate Logical shift to the left with the number of bits speciﬁ ed by the register Logical shift to the left with the number of bits speciﬁ ed by immediate Bytewise swap on byte boundary in 16 bits Extend operand in the following instruction Convert signed 8-bit data into 24 bits Convert signed 16-bit data into 24 bits Convert 32-bit data into 24 bits Converts 24-bit data into 32 bits Converts 16-bit data into 32 bits PC relative jump Delayed branching possible Absolute jump Delayed branching possible PC relative conditional jump Branch condition: !Z & !(N ^ V) Delayed branching possible PC relative conditional jump Branch condition: !(N ^ V) Delayed branching possible PC relative conditional jump Branch condition: N ^ V Delayed branching possible PC relative conditional jump Branch condition: Z | N ^ V Delayed branching possible PC relative conditional jump Branch condition: !Z & !C Delayed branching possible PC relative conditional jump Branch condition: !C Delayed branching possible PC relative conditional jump Branch condition: C Delayed branching possible PC relative conditional jump Branch condition: Z | C Delayed branching possible PC relative conditional jump Branch condition: Z Delayed branching possible PC relative conditional jump Branch condition: !Z Delayed branching possible PC relative subroutine call Delayed call possible Absolute subroutine call Delayed call possible Return from subroutine Delayed return possible Software interrupt Software interrupt with interrupt level setting Return from interrupt handling Delayed call possible Debug interrupt Return from debug processing No operation

T mode

HAL SLEEP mode Enable interrupts Disable interrupts

instruction accesses memories in 32-bit length. During data transfer from a register to a memory, the 32-bit data in which the eight high-order bits are set to 0 is written to the memory. During reading from a memory, the eight high-order bits of the read data are ignored.

∗2 The S1C17704 does not include a coprocessor. Therefore, the coprocessor instructions are not available.

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The symbols in the above table each have the meanings specified below.

Table 2.3.2 Symbol Meanings

%rs

%rd

[%rb] [%rb]+ [%rb]-

-[%rb] %sp [%sp],[%sp+imm7] [%sp]+ [%sp]-

-[%sp]

imm3,imm5,imm7,imm13 sign7,sign10

Symbol Description

General-purpose register, source General-purpose register, destination Memory addressed by general-purpose register Memory addressed by general-purpose register with address post-incremented Memory addressed by general-purpose register with address post-decremented Memory addressed by general-purpose register with address pre-decremented Stack pointer Stack Stack with address post-incremented Stack with address post-decremented Stack with address pre-decremented Unsigned immediate (numerals indicating bit length) Signed immediate (numerals indicating bit length)

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2.4 Vector Table

The vector table contains the vectors to the interrupt handler routines (handler routine start address) that will be read by the S1C17 Core to execute the handler when an interrupt occurs. The boot address from which the program starts running after a reset must be written to the top of the vector table. The vector table is located at address 0x8000 in the S1C17704. The vector table base address can be read out from TTBR (Vector Table Base Register) located at address 0xffff80. Table 2.4.1 shows the vector table of the S1C17704.

Table 2.4.1 Vector Table

Vector No.

Software interrupt No.

0 (0x00) 0x8000 Reset • Low input to the #RESET pin

1 (0x01) 0x8004 Address misaligned interrupt Memory access instruction 2

– (0xfffc00) Debugging interrupt 2 (0x02) 0x8008 NMI Watchdog timer overﬂ ow 3 (0x03) 0x800c reserved – – 4 (0x04) 0x8010 P0 port interrupt P00–P07 port inputs High 5 (0x05) 0x8014 P1 port interrupt P10–P17 port inputs ↑ 6 (0x06) 0x8018 Stopwatch timer interrupt • 100 Hz timer signal

7 (0x07) 0x801c Clock timer interrupt • 32 Hz timer signal

8 (0x08) 0x8020 8-bit OSC1 timer interrupt Compare match 9 (0x09) 0x8024 SVD interrupt Low supply voltage detected

10 (0x0a) 0x8028 LCD interrupt Frame signal 11 (0x0b) 0x802c PWM & capture timer interrupt • Compare match A

12 (0x0c) 0x8030 8-bit timer interrupt Timer underﬂ ow 13 (0x0d) 0x8034 16-bit timer Ch. 0 interrupt Timer underﬂ ow 14 (0x0e) 0x8038 16-bit timer Ch. 1 interrupt Timer underﬂ ow

15 (0x0f) 0x803c 16-bit timer Ch. 2 interrupt Timer underﬂ ow

16 (0x10) 0x8040 UART interrupt • Transmit buffer empty

17 (0x11) 0x8044 Remote controller interrupt • Data length counter underﬂ ow

18 (0x12) 0x8048 SPI interrupt • Transmit buffer empty

19 (0x13) 0x804c I

20 (0x14) 0x8050 reserved –

:: : : ↓

31 (0x1f) 0x807c reserved – Low

∗1 When the same interrupt level is set ∗2 Either reset or NMI can be selected as the watchdog timer interrupt with software.

Vector address Hardware interrupt name Cause of hardware interrupt Priority

• Watchdog timer overﬂ ow

brk

instruction, etc. 3

• 10 Hz timer signal

• 1 Hz timer signal

• 8 Hz timer signal

• 2 Hz timer signal

• 1 Hz timer signal

• Compare match B

• Receive buffer full

• Receive error

• Input rising edge detected

• Input falling edge detected

C interrupt • Transmit buffer empty

• Receive buffer full

∗2

∗1

0xffff80: Vector Table Base Register (TTBR)

Vector Table Base Register (TTBR)

S1C17704 TECHNICAL MANUAL EPSON

0xffff80

(32 bits)

D31–24

D23–0

– TTBR[23:0]

Unused (fixed at 0) 0x0 0x0 R Vector table base address 0x8000 0x8000R

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2.5 Processor Information

The S1C17704 has the Processor ID Register (0xffff84) shown below that allow the application software to identify CPU core type.

0xffff84: Processor ID Register (IDIR)

Processor ID Register (IDIR)

0xffff84

(8 bits)

This is a read-only register that contains the ID code to represent a processor model. The S1C17 Core’s ID code is 0x10.

D7–0

IDIR[7:0]

Processor ID 0x10: S1C17 Core

0x10 0x10 R

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3 Memory Map, Bus Control

Figure 3.1 shows the S1C17704 memory map.

0xff ffff

0xff fc00 0xff fbff

0x08 0560 0x08 055f

0x08 0000 0x07 ffff

0x01 8000 0x01 7fff

0x00 8000 0x00 7fff

0x00 6000 0x00 5fff

0x00 5000 0x00 4fff

0x00 4400 0x00 43ff

0x00 4000 0x00 3fff

0x00 1000 0x00 0fff

0x00 0fc0

0x00 0000

Reserved for core I/O area

(1K bytes, 1 cycle)

reserved

Display RAM area

(576 bytes, 2–5 cycles)

(Device size: 8 bits)

reserved

Flash area

(64K bytes, 1–5 cycles)

(Device size: 16 bits)

Vector table

reserved

Internal peripheral area 2

(4K bytes, 3 cycles)

reserved

Internal peripheral area 1

(1K bytes, 1 cycle)

reserved

Debug RAM area (64 bytes)

Internal RAM area (4K bytes, 1 cycle)

(Device size: 32 bits)

Figure 3.1 S1C17704 Memory Map

0x5360–0x5fff 0x5340–0x535f 0x5320–0x533f 0x5300–0x531f 0x52c0–0x52ff 0x52a0–0x52bf 0x5280–0x529f 0x5200–0x527f 0x5140–0x51ff 0x5120–0x513f 0x5100–0x511f 0x50e0–0x50ff 0x50c0–0x50df 0x50a0–0x50bf 0x5080–0x509f 0x5060–0x507f 0x5040–0x505f 0x5020–0x503f 0x5000–0x501f

0x4360–0x43ff 0x4340–0x435f 0x4320–0x433f 0x4300–0x431f 0x4280–0x42ff 0x4260–0x427f 0x4240–0x425f 0x4220–0x423f 0x4200–0x421f 0x4120–0x41ff 0x4100–0x411f 0x4040–0x40ff 0x4020–0x403f 0x4000–0x401f

Peripheral function (Device size) reserved

Remote controller MISC registers PWM & capture timer reserved Port MUX reserved P ports reserved Power controller SVD circuit reserved 8-bit OSC1 timer LCD driver Clock generator Oscillator Watchdog timer Stopwatch timer Clock timer

reserved I SPI Interrupt controller reserved 16-bit timer Ch. 2 16-bit timer Ch. 1 16-bit timer Ch. 0 8-bit timer reserved UART reserved Prescaler reserved

– (8 bits) (8 bits) (16 bits) – (8 bits) – (8 bits) – (8 bits) (8 bits) (8 bits) (8 bits) (8 bits) (8 bits) (8 bits) (8 bits) (8 bits) (8 bits)

(16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (8 bits) (8 bits) (8 bits) (8 bits) (8 bits)

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3.1 Bus Cycle

The CPU operates with CCLK as the operating clock. For CCLK, see Section 8.2, “Controlling the CPU Core Clock (CCLK).” The period between a CCLK rising edge and the next rising edge is assumed to be one CCLK (= one bus cycle). As shown in Figure 3.1, the number of cycles required for one bus access depends on the peripheral or memory module. Furthermore, the number of bus accesses depends on the CPU instruction (access size) and device size.

Table 3.1.1 Number of Bus Accesses

Device size CPU access size Number of bus accesses

8 bits 8 bits 1

16 bits 2 32 bits* 4

16 bits 8 bits 1

16 bits 1 32 bits* 2

32 bits 8 bits 1

16 bits 1 32 bits* 1

∗ Handling the eight high-order bits during 32-bit accesses During writing, the eight high-order bits are written as 0. During reading from a memory, the eight high-order

bits are ignored. However, the stack operation in an interrupt handling reads/writes 32-bit data that consists of the PSR value as the high-order 8 bits and the return address as the low order 24 bits.

Number of bus cycles calculation example

Number of bus cycles when the CPU accesses the display RAM area (eight-bit device, set to two access cycles)

by a 16-bit read or write instruction.

2 [cycles] × 2 [bus accesses] = 4 [CCLK cycles]

3.1.1 Restrictions on Access Size

The modules shown below have a restriction on the access size. Appropriate instructions should be used in programming.

Flash memory

The Flash memory allows only 16-bit write instructions for programming. Reading data from the Flash memory

has no such restriction.

SPI, I2C

The SPI and I2C registers allow only 16-bit read/write instructions for accessing.

Other modules can be accessed with an 8-bit, 16-bit, or 32-bit instruction. However, reading for an unnecessary register may change the peripheral module status and it may cause a problem. Therefore, use the appropriate instructions according to the device size.

3.1.2 Restrictions on Instruction Execution Cycles

An instruction fetch and a data access are not performed simultaneously under one of the conditions listed below. This prolongs the instruction fetch cycle for the number of data area access cycles.

• When the S1C17704 executes the instruction stored in the Flash area and accesses data in the Flash area, display RAM area or internal peripheral area 2 (0x5000–)

• When the S1C17704 executes the instruction stored in the internal RAM area and accesses data in the internal RAM area

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3.2 Flash Area

3.2.1 Internal Flash Memory

The 64K-byte area from address 0x8000 to address 0x17fff contains a Flash memory (4K bytes × 16 sectors) for storing application programs and data. Address 0x8000 is defined as the vector table base address, therefore a vector table (see Section 2.4, “Vector Table”) must be placed from the beginning of the area. The Flash memory can be read in 1 to 5 cycles.

3.2.2 Flash Programming

The S1C17704 supports on-board programming of the Flash memory, it makes it possible to program the Flash memory with the application programs/data by using the debugger through the ICD Mini. Furthermore, the S1C17704 supports self-programming by the application program stored in the Flash memory. The Flash memory can be programmed in 16-bit units. For programming of the Flash memory, see Appendix B, “Flash Programming.” The Flash memory supports two erase methods, chip erase and sector erase. The table below lists the correspondence between addresses and sectors required for sector erase.

Note: The debugger supports chip erase only and does not allow erasing in sector units.

Table 3.2.2.1 Correspondence Between Memory Address and Flash Sector

S1C17704 address Flash sector number S1C17704 address Flash sector number

0x0f000–0x0ffff 0x0e000–0x0efff 0x0d000–0x0dfff 0x0c000–0x0cfff 0x0b000–0x0bfff 0x0a000–0x0afff 0x09000–0x09fff 0x08000–0x08fff

7 6 5 4 3 2 1 0

0x17000–0x17fff 0x16000–0x16fff 0x15000–0x15fff 0x14000–0x14fff 0x13000–0x13fff 0x12000–0x12fff 0x11000–0x11fff 0x10000–0x10fff

15 14 13 12

9 8

Note: The 32 bits (0x17ffc–0x17fff) at the end of Sector 15 are reserved for the system as the protect

bits. Do not program this area with data other than protect settings.

3.2.3 Protect Bits

In order to protect the memory contents, the Flash memory provides two protection features, write protection and data read protection, that can be configured for every 16K-byte areas. The write protection disables writing data to the configured area. The data-read protection disables reading data from the configured area (the read value is always 0x0000). However, it does not disable the instruction fetch operation by the CPU. The Flash memory provides the protect bits listed below. Program the protect bit corresponding to the area to be protected to 0.

0x17ffc–0x17ffe: Flash Protect Bits

Address Bit Function Setting Init. R/W Remarks

0x17ffc

(16 bits)

Notes: • Be sure not to locate the area with data-read protection into the .data and .rodata sections.

• Be sure to set D0 of address 0x17ffe to 1. If it is set to 0, the program cannot be booted.

D15–4 reserved – – –

D3 Flash write-protect bit for 0x14000–0x17fff 1 Writable 0 Protected 1 R/W D2 Flash write-protect bit for 0x10000–0x13fff 1 Writable 0 Protected 1 R/W D1 Flash write-protect bit for 0x0c000–0x0ffff 1 Writable 0 Protected 1 R/W

0x17ffe

D0 Flash write-protect bit for 0x08000–0x0bfff 1 Writable 0 Protected 1 R/W

D15–4 reserved – – –

D3 Flash data-read-protect bit for 0x14000–0x17fff 1 Readable 0 Protected 1 R/W D2 Flash data-read-protect bit for 0x10000–0x13fff 1 Readable 0 Protected 1 R/W D1 Flash data-read-protect bit for 0x0c000–0x0ffff 1 Readable 0 Protected 1 R/W D0 reserved 1 1 R/W Always set to 1.

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3.2.4 Access Control for the Flash Controller

The S1C17704 on-chip Flash memory is accessed via the exclusive Flash controller. A MISC register is used to set the access condition for the Flash controller.

Setting number of read access cycles for the Flash controller

In order to read data from the Flash memory properly, set the appropriate number of read access cycles

according to the CCLK frequency using the FLCYC[2:0] bits (D[2:0]/MISC_FL register).

0x5320: FLASHC Control Register (MISC_FL)

FLASHC Control Register (MISC_FL)

0x5320

(8 bits)

D[7:3] Reserved

D[2:0] FLCYC[2:0]: FLASHC Read Access Cycle Setup Bits

Sets the number of read access cycles for the Flash controller.

–

D7–3 D2–0

FLCYC[2:0]

reserved – – – 0 when being read. FLASHC read access cycle FLCYC[2:0] Read cycle 0x3 R/W

0x7–0x5

0x4 0x3 0x2 0x1 0x0

reserved 1 cycles 5 cycles 4 cycles 3 cycles 2 cycles

Table 3.2.4.1 Setting Read Access Cycles for the Flash Controller

FLCYC[2:0] Number of read access cycles CCLK frequency

0x7–0x5 Reserved –

0x4 1 cycles 6 MHz max. 0x3 5 cycles 8.2 MHz max. 0x2 4 cycles 8.2 MHz max. 0x1 3 cycles 8.2 MHz max. 0x0 2 cycles 8.2 MHz max.

(Default: 0x3)

Note: Be sure to avoid setting a number of read access cycles that exceeds the maximum allowable

CCLK frequency, as it may cause a malfunction.

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3.3 Internal RAM Area

3.3.1 Internal RAM

The S1C17704 contains a RAM in the 4K-byte area from address 0x0 to address 0xfff. The RAM is accessed in one cycle for both reading and writing and allows high-speed execution of the instruction codes copied into it as well as storing variables and other data.

Note: The 64-byte area at the end of the RAM (0xfc0–0xfff) is reserved for the on-chip debugger. When

using the debug functions under application development, do not access this area from the application program.

This area can be used for applications of mass-produced devices that do not need debugging.

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3.4 Display RAM Area

3.4.1 Display RAM

The display RAM for the on-chip LCD driver is located in the 576-byte area from address 0x80000 to address 0x8055f. The display RAM is accessed in two to five cycles as an eight-bit device. It can be used as a generalpurpose RAM when it is not used for display. See Section 22.5, “Display Memory,” for details of the display memory.

3.4.2 Access Control for the SRAM Controller

The S1C17704 display RAM is accessed via the exclusive SRAM controller. A MISC register is used to set the access condition for the SRAM controller.

Setting number of access cycles for the SRAM controller

In order to read/write data from/to the display RAM properly, set the appropriate number of access cycles

according to the CCLK frequency using the SRCYC[1:0] bits (D[1:0]/ MISC_SR register).

0x5321: SRAMC Control Register (MISC_SR)

SRAMC Control Register (MISC_SR)

0x5321

(8 bits)

D7–2 D1–0

– SRCYC[1:0]

reserved – – – 0 when being read. SRAMC access cycle SRCYC[1:0] Access cycle 0x3 R/W

0x3 0x2 0x1 0x0

5 cycles 4 cycles 3 cycles 2 cycles

D[7:2] Reserved

D[1:0] SRCYC[1:0]: SRAMC Access Cycle Setup Bits

Sets the number of SRAM (display RAM) controller access cycle.

Table 3.4.2.1 Setting Access Cycles for the SRAM Controller

SRCYC[1:0] Number of access cycles CCLK frequency

0x3 5 cycles 8.2 MHz max. 0x2 4 cycles 8.2 MHz max. 0x1 3 cycles 8.2 MHz max. 0x0 2 cycles 6 MHz max.

(Default: 0x3)

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3.5 Internal Peripheral Area

The I/O and control registers for the internal peripheral modules are located in the 1K-byte area beginning with address 0x4000 and the 4K-byte area beginning with address 0x5000.

3.5.1 Internal Peripheral Area 1 (0x4000–)

The internal peripheral area 1 beginning with address 0x4000 contains the I/O memory for the peripheral functions listed below and this area can be accessed in one cycle.

• Prescaler (PSC, 8-bit device)

• UART (UART, 8-bit device)

• 8-bit timer (T8F, 16-bit device)

• 16-bit timers (T16, 16-bit device)

• Interrupt controller (ITC, 16-bit device)

• SPI (SPI, 16-bit device)

• I

C (I2C, 16-bit device)

3.5.2 Internal Peripheral Area 2 (0x5000–)

The internal peripheral area 2 beginning with address 0x5000 contains the I/O memory for the peripheral functions listed below and this area can be accessed in three cycles.

• Clock timer (CT, 8-bit device)

• Stopwatch timer (SWT, 8-bit device)

• Watchdog timer (WDT, 8-bit device)

• Oscillator (OSC, 8-bit device)

• Clock generator (CLG, 8-bit device)

• LCD driver (LCD, 8-bit device)

• 8-bit OSC1 timer (T8OSC1, 8-bit device)

• SVD circuit (SVD, 8-bit device)

• Power supply circuit (VD1, 8-bit device)

• I/O port & port MUX (P, 8-bit device)

• PWM & capture timer (T16E, 16-bit device)

• MISC register (MISC, 8-bit device)

• Remote controller (REMC, 8-bit device)

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3.5.3 I/O Map

This section shows the I/O map table for the internal peripheral area. For details of each control register, see the I/O register list in Appendix or description for each peripheral module.

Table 3.5.3.1 I/O Map (Internal Peripheral Area 1)

Peripheral Address Register name Function

Prescaler (8-bit device)

UART (with IrDA) (8-bit device)

8-bit timer (with fine mode) (16-bit device)

16-bit timer Ch. 0 (16-bit device)

16-bit timer Ch. 1 (16-bit device)

16-bit timer Ch. 2 (16-bit device)

Interrupt controller (16-bit device)

SPI (16-bit device)

I (16-bit device)

0x4020 PSC_CTL Prescaler Control Register Starts/stops the prescaler. 0x4021–0x403f – – Reserved 0x4100 UART_ST UART Status Register Indicates transfer, buffer and error statuses. 0x4101 UART_TXD UART Transmit Data Register Transmit data 0x4102 UART_RXD UART Receive Data Register Receive data 0x4103 UART_MOD UART Mode Register Sets transfer data format. 0x4104 UART_CTL UART Control Register Controls data transfer. 0x4105 UART_EXP UART Expansion Register Sets IrDA mode. 0x4106–0x411f – – Reserved 0x4200 T8F_CLK 8-bit Timer Input Clock Select Register Selects a prescaler output clock. 0x4202 T8F_TR 8-bit Timer Reload Data Register Sets reload data. 0x4204 T8F_TC 8-bit Timer Counter Data Register Counter data 0x4206 T8F_CTL 8-bit Timer Control Register 0x4208–0x421f – – Reserved 0x4220 T16_CLK0 16-bit Timer Ch.0 Input Clock Select Register Selects a prescaler output clock. 0x4222 T16_TR0 16-bit Timer Ch.0 Reload Data Register Sets reload data. 0x4224 T16_TC0 16-bit Timer Ch.0 Counter Data Register Counter data 0x4226 T16_CTL0 16-bit Timer Ch.0 Control Register 0x4228–0x423f – – Reserved 0x4240 T16_CLK1 16-bit Timer Ch.1 Input Clock Select Register Selects a prescaler output clock. 0x4242 T16_TR1 16-bit Timer Ch.1 Reload Data Register Sets reload data. 0x4244 T16_TC1 16-bit Timer Ch.1 Counter Data Register Counter data 0x4246 T16_CTL1 16-bit Timer Ch.1 Control Register 0x4248–0x425f – – Reserved 0x4260 T16_CLK2 16-bit Timer Ch.2 Input Clock Select Register Selects a prescaler output clock. 0x4262 T16_TR2 16-bit Timer Ch.2 Reload Data Register Sets reload data. 0x4264 T16_TC2 16-bit Timer Ch.2 Counter Data Register Counter data 0x4266 T16_CTL2 16-bit Timer Ch.2 Control Register 0x4268–0x427f – – Reserved 0x4300 ITC_IFLG Interrupt Flag Register Indicates/resets interrupt occurrence status. 0x4302 ITC_EN Interrupt Enable Register Enables/disables each maskable interrupt. 0x4304 ITC_CTL ITC Control Register Enables/disables the ITC. 0x4306 ITC_ELV0 External Interrupt Level Setup Register 0 Sets the P0 and P1 interrupt levels and

0x4308 ITC_ELV1 External Interrupt Level Setup Register 1 Sets the stopwatch timer and clock timer

0x430a ITC_ELV2 External Interrupt Level Setup Register 2 Sets the 8-bit OSC1 timer and SVD interrupt

0x430c ITC_ELV3 External Interrupt Level Setup Register 3 Sets the LCD and PWM & capture timer

0x430e ITC_ILV0 Internal Interrupt Level Setup Register 0 Sets the 8-bit timer and 16-bit timer Ch. 0

0x4310 ITC_ILV1 Internal Interrupt Level Setup Register 1 Sets the 16-bit timer Ch. 1 and 16-bit timer

0x4312 ITC_ILV2 Internal Interrupt Level Setup Register 2 Sets the UART and remote controller inter-

0x4314 ITC_ILV3 Internal Interrupt Level Setup Register 3 Sets the SPI and I 0x4316–0x431f – – Reserved 0x4320 SPI_ST SPI Status Register Indicates transfer and buffer statuses. 0x4322 SPI_TXD SPI Transmit Data Register Transmit data 0x4324 SPI_RXD SPI Receive Data Register Receive data 0x4326 SPI_CTL SPI Control Register 0x4328–0x433f – – Reserved 0x4340 I2C_EN I2C Enable Register Enables the I2C module. 0x4342 I2C_CTL I

0x4344 I2C_DAT I 0x4346 I2C_ICTL I 0x4348–0x435f – – Reserved

C Control Register Controls the I2C operation and indicates

C Data Register Transmit/receive data

C Interrupt Control Register Controls the I2C interrupt.

Sets the timer mode and starts/stops the timer.

trigger modes.

interrupt levels and trigger modes.

levels and trigger modes.

interrupt levels and trigger modes.

interrupt levels.

Ch. 2 interrupt levels.

rupt levels.

Sets the SPI mode and enables data transfer.

transfer status.

C interrupt levels.

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Table 3.5.3.2 I/O Map (Internal Peripheral Area 2)

Peripheral Address Register name Function

Clock timer (8-bit device)

Stopwatch timer (8-bit device)

Watchdog timer (8-bit device)

Oscillator (8-bit device)

Clock generator (8-bit device)

LCD driver (8-bit device)

8-bit OSC1 timer (8-bit device)

SVD circuit (8-bit device)

Power supply circuit (8-bit device)

P port & port MUX (8-bit device)

0x5000 CT_CTL Clock Timer Control Register Resets and starts/stops the timer. 0x5001 CT_CNT Clock Timer Counter Register Counter data 0x5002 CT_IMSK Clock Timer Interrupt Mask Register Enables/disables interrupt. 0x5003 CT_IFLG Clock Timer Interrupt Flag Register Indicates/resets interrupt occurrence status. 0x5004–0x501f – – Reserved 0x5020 SWT_CTL Stopwatch Timer Control Register Resets and starts/stops the timer. 0x5021 SWT_BCNT Stopwatch Timer BCD Counter Register BCD counter data 0x5022 SWT_IMSK Stopwatch Timer Interrupt Mask Register Enables/disables interrupt. 0x5023 SWT_IFLG Stopwatch Timer Interrupt Flag Register Indicates/resets interrupt occurrence status. 0x5024–0x503f – – Reserved 0x5040 WDT_CTL Watchdog Timer Control Register Resets and starts/stops the timer. 0x5041 WDT_ST Watchdog Timer Status Register 0x5042–0x505f – – Reserved 0x5060 OSC_SRC Clock Source Select Register Selects a clock source. 0x5061 OSC_CTL Oscillation Control Register Controls oscillation. 0x5062 OSC_NFEN Noise Filter Enable Register Enables/disables noise filters. 0x5063 OSC_LCLK LCD Clock Setup Register Sets up the LCD clock. 0x5064 OSC_FOUT FOUT Control Register Controls clock output. 0x5065 OSC_T8OSC1 T8OSC1 Clock Control Register Sets up the 8-bit OSC1 timer clock. 0x5066–0x507f – – Reserved 0x5080 CLG_PCLK PCLK Control Register Controls the PCLK output. 0x5081 CLG_CCLK CCLK Control Register Configures the CCLK division ratio. 0x5082–0x509f – – Reserved 0x50a0 LCD_DCTL LCD Display Control Register Controls the LCD display. 0x50a1 LCD_CADJ LCD Contrast Adjust Register Controls the contrast. 0x50a2 LCD_CCTL LCD Clock Control Register Controls the LCD clock duty. 0x50a3 LCD_VREG LCD Voltage Regulator Control Register Controls the LCD drive voltage regulator. 0x50a4 LCD_PWR LCD Power Voltage Booster Control Register Controls the LCD voltage booster. 0x50a5 LCD_IMSK LCD Interrupt Mask Register Enables/disables interrupt. 0x50a6 LCD_IFLG LCD Interrupt Flag Register Indicates/resets interrupt occurrence status. 0x50a7–0x50bf – – Reserved 0x50c0 T8OSC1_CTL 8-bit OSC1 Timer Control Register 0x50c1 T8OSC1_CNT 8-bit OSC1 Timer Counter Data Register Counter data 0x50c2 T8OSC1_CMP 8-bit OSC1 Timer Compare Data Register Sets compare data. 0x50c3 T8OSC1_IMSK 8-bit OSC1 Timer Interrupt Mask Register Enables/disables interrupt. 0x50c4 T8OSC1_IFLG 8-bit OSC1 Timer Interrupt Flag Register Indicates/resets interrupt occurrence status. 0x50c5–0x50df – – Reserved 0x5100 SVD_EN SVD Enable Register Enables/disables the SVD operation. 0x5101 SVD_CMP SVD Compare Voltage Register Sets compare voltage. 0x5102 SVD_RSLT SVD Detection Result Register Voltage detection results 0x5103 SVD_IMSK SVD Interrupt Mask Register Enables/disables interrupt. 0x5104 SVD_IFLG SVD Interrupt Flag Register Indicates/resets interrupt occurrence status. 0x5105–0x511f – – Reserved 0x5120 VD1_CTL V

0x5121–0x513f – – Reserved 0x5200 P0_IN P0 Port Input Data Register P0 port input data 0x5201 P0_OUT P0 Port Output Data Register P0 port output data 0x5202 P0_IO P0 Port I/O Direction Control Register Selects the P0 port I/O direction. 0x5203 P0_PU P0 Port Pull-up Control Register Controls the P0 port pull-up resistor. 0x5204 P0_SM P0 Port Schmitt Trigger Control Register Controls the P0 port Schmitt trigger input. 0x5205 P0_IMSK P0 Port Interrupt Mask Register Enables/disables the P0 port interrupt. 0x5206 P0_EDGE P0 Port Interrupt Edge Select Register Selects the signal edge for generating P0

0x5207 P0_IFLG P0 Port Interrupt Flag Register Indicates/resets the P0 port interrupt occur-

0x5208 P0_CHAT P0 Port Chattering Filter Control Register Controls the P0 port chattering filter. 0x5209 P0_KRST 0x520a–0x520f – – Reserved 0x5210 P1_IN P1 Port Input Data Register P1 port input data 0x5211 P1_OUT P1 Port Output Data Register P1 port output data 0x5212 P1_IO P1 Port I/O Direction Control Register Selects the P1 port I/O direction. 0x5213 P1_PU P1 Port Pull-up Control Register Controls the P1 port pull-up resistor. 0x5214 P1_SM P1 Port Schmitt Trigger Control Register Controls the P1 port Schmitt trigger input. 0x5215 P1_IMSK P1 Port Interrupt Mask Register Enables/disables the P1 port interrupt.

D1 Control Register Controls the VD1 voltage and heavy load

P0 Port Key-Entry Reset Configuration Register

Sets the timer mode and indicates NMI status.

Sets the timer mode and starts/stops the timer.

protection mode.

port interrupts.

rence status.

Configures the P0 port key-entry reset function.

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Peripheral Address Register name Function

P port & port MUX (8-bit device)

PWM & timer (16-bit device)

MISC register (8-bit device)

Remote controller (8-bit device)

0x5216 P1_EDGE P1 Port Interrupt Edge Select Register Selects the signal edge for generating P1

0x5217 P1_IFLG P1 Port Interrupt Flag Register Indicates/resets the P1 port interrupt occur-

0x5218–0x521f – – Reserved 0x5220 P2_IN P2 Port Input Data Register P2 port input data 0x5221 P2_OUT P2 Port Output Data Register P2 port output data 0x5222 P2_IO P2 Port I/O Direction Control Register Selects the P2 port I/O direction. 0x5223 P2_PU P2 Port Pull-up Control Register Controls the P2 port pull-up resistor. 0x5224 P2_SM P2 Port Schmitt Trigger Control Register Controls the P2 port Schmitt trigger input. 0x5225–0x522f – – Reserved 0x5230 P3_IN P3 Port Input Data Register P3 port input data 0x5231 P3_OUT P3 Port Output Data Register P3 port output data 0x5232 P3_IO P3 Port I/O Direction Control Register Selects the P3 port I/O direction. 0x5233 P3_PU P3 Port Pull-up Control Register Controls the P3 port pull-up resistor. 0x5234 P3_SM P3 Port Schmitt Trigger Control Register Controls the P3 port Schmitt trigger input. 0x5235–0x527f – – Reserved 0x52a0 P0_PMUX P0 Port Function Select Register Selects the P0 port function. 0x52a1 P1_PMUX P1 Port Function Select Register Selects the P1 port function. 0x52a2 P2_PMUX P2 Port Function Select Register Selects the P2 port function. 0x52a3 P3_PMUX P3 Port Function Select Register Selects the P3 port function. 0x52a4–0x52bf – – Reserved

capture

0x5300 T16E_CA PWM Timer Compare Data A Register Sets compare data A. 0x5302 T16E_CB PWM Timer Compare Data B Register Sets compare data B. 0x5304 T16E_TC PWM Timer Counter Data Register Counter data 0x5306 T16E_CTL PWM Timer Control Register 0x5308 T16E_CLK PWM Timer Input Clock Select Register Selects a prescaler output clock. 0x530a T16E_IMSK PWM Timer Interrupt Mask Register Enables/disables interrupt. 0x530c T16E_IFLG PWM Timer Interrupt Flag Register Indicates/resets interrupt occurrence status. 0x530e–0x531f – – Reserved 0x5320 MISC_FL FLASHC Control Register Sets FLASHC access condition. 0x5321 MISC_SR SRAMC Control Register Sets SRAMC access condition. 0x5322 MISC_OSC1 OSC1 Peripheral Control Register Selects the OSC1 peripheral operation in

0x5323–0x533f – – Reserved 0x5340 REMC_CFG REMC Configuration Register Selects/enables transmission/reception 0x5341 REMC_PSC REMC Prescaler Clock Select Register Selects a prescaler output clock. 0x5342 REMC_CARH REMC H Carrier Length Setup Register Sets up the H period of the carrier. 0x5343 REMC_CARL REMC L Carrier Length Setup Register Sets up the L period of the carrier. 0x5344 REMC_ST REMC Status Register Transmit/receive bit 0x5345 REMC_LCNT REMC Length Counter Register Sets the transmit/receive data length. 0x5346 REMC_IMSK REMC Interrupt Mask Register Enables/disables interrupt. 0x5347 REMC_IFLG REMC Interrupt Flag Register Indicates/resets interrupt occurrence status. 0x5348–0x535f – – Reserved

port interrupts.

rence status.

Sets the timer mode and starts/stops the timer.

debug mode.

Note: Do not access the “Reserved” address in the table above and unused areas in the peripheral area

that are not described in the table from the application program.

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3.6 S1C17 Core I/O Area

The 1K-byte area from address 0xfffc00 to address 0xffffff is the I/O area for the CPU core in which the I/O registers listed in the table below are located.

Table 3.6.1 I/O Map (S1C17 Core I/O Area)

Peripheral Address Register name Function

S1C17 Core I/O 0xffff80 TTBR Vector Table Base Register Indicates the vector table base address.

See Section 2.4, “Vector Table,” and Section 2.5, “Processor Information,” for TTBR and IDIR, respectively. For DBRAM, see Chapter 24, “On-chip Debugger (DBG).”

0xffff84 IDIR Processor ID Register Indicates the processor ID. 0xffff90 DBRAM Debug RAM Base Register Indicates the debug RAM base address.

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4.1 Power Supply Voltage

The operating voltage range of the S1C17704 is as follows:

For normal operation: 1.8 V to 3.6 V For Flash programming: 2.7 V to 3.6 V

4 POWER SUPPLY

Supply a voltage within the range to the V V

DD pins and three VSS pins. Do not leave any pins open and be sure to connect them to + power source and GND.

DD pins with the VSS pins as the GND level. The S1C17704 provides two

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4.2 Internal Power Supply Circuit

The S1C17704 has a built-in power supply circuit shown in Figure 4.2.1 to generate all the power voltages required for the internal circuits. The power supply module consists of three circuits.

Table 4.2.1 Power Supply Circuit

Circuit Power supply circuit Output voltage

Oscillator and internal logic circuits Internal logic voltage regulator VD1 LCD system voltage regulator Power voltage booster VDD or VD2 LCD driver LCD system voltage regulator VC1 to VC5

External power supply

VDD

VD1

VD2

VC1 VC2 VC3 VC4 VC5

CB CC CD

VSS

VD1MD

Internal logic

voltage regulator

Power

voltage booster

LCD system

voltage regulator

HVLD

VD2VDD

VD1

VC1~VC5

PBON

VDSEL

LHVLD

Oscillation circuit

Internal circuit

LCD driver

OSC1, OSC2

OSC3, OSC4

COM0–COM31

SEG0–SEG55

Figure 4.2.1 Configuration of Power Supply Circuit

Note: Be sure to avoid using the VD1, VD2, and VC1–VC5 pin outputs to drive external circuits.

Internal logic voltage regulator

The internal logic voltage regulator generates the VD1 operating voltage for the internal logic circuits and

oscillators. The V V for Flash programming.

D1 voltage value can be switched in the program; set it to 1.8 V for normal operation and 2.5

Power voltage booster

The power voltage booster generates the VD2 operating voltage for the LCD system voltage regulator. Either

DD or VD2 can be selected as the power source for the LCD system voltage regulator according to the VDD

supply voltage value.

Table 4.2.2 Power Source for LCD System Voltage Regulator

Power supply voltage VDD Power source for the LCD system voltage regulator

1.8 to 2.5 V VD2 (≅ VDD × 2)

2.5 to 3.6 V V

LCD system voltage regulator

The LCD system voltage regulator generates the 1/5-bias LCD drive voltages VC1, VC2, VC3, VC4, and VC5.

In the S1C17704, the LCD drive voltage is supplied to the built-in LCD driver that drives the LCD panel connected to the SEG and COM pins.

Note: If V

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DD is used as the power source for the LCD system voltage regulator when VDD is 2.5 V or

less, the V

C1 to VC5 voltages cannot be generated within the specifications.

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4 POWER SUPPLY

4.3 Controlling the Power Supply Circuit

In order to generate the internal operating voltage properly according to the power supply voltage and operating mode, or to reduce current consumption, the power supply circuit is designed to be controlled with software.

Switching the operating mode

The S1C17704 has two kinds of operating modes.

1. Normal operation mode This mode is provided for running the application program. V

DD = 1.8 to 3.6 V, internal operating voltage VD1 = 1.8 V

2. Flash erase/program mode This mode is provided for erasing and programming the Flash memory. V

DD = 2.7 to 3.6 V, internal operating voltage VD1 = 2.5 V

The V

Note: When the operating mode is switched, the internal operating voltage requires 5 ms (max.) to

D1 voltage value must be switched according to the operating mode as shown above using the VD1MD bit

(D0/VD1_CTL register). Normally set VD1MD to 0 (V

D1 = 1.8 V, default setting). It should be set to 1 before

erasing/programming the Flash memory.

∗ VD1MD: Flash Erase/Program Mode Bit in the VD1 Control (VD1_CTL) Register (D0/0x5120)

stabilize. Flash memory programming should be started after the stabilization time has elapsed.

Controlling the LCD power source

The LCD system voltage regulator must be driven with a 2.5 V or more power voltage to generate appropriate

LCD drive voltages V use the power voltage booster to generate double the V with the V

D2 output voltage. Set the PBON bit (D0/LCD_PWR register) to 1 to turn the power voltage booster

on. In addition, set the VDSEL bit (D1/LCD_PWR register) to 1 to drive the LCD system voltage regulator with the V

D2 voltage output from the power voltage booster. PBON must be set to 1 before the drive voltage can

be switched to V

∗ PBON: Power Voltage Booster Control Bit in the LCD Power Voltage Booster Control (LCD_PWR) Register

∗ VDSEL: Regulator Power Source Select Bit in the LCD Power Voltage Booster Control (LCD_PWR) Register

When the power supply voltage (VDD) is 2.5 V or more, drive the LCD system voltage regulator with VDD. The

power voltage booster should be turned off to reduce current consumption. In this case, PBON and VDSEL are both set to 0 (default).

Note: When the power voltage booster is turned on, the V

stabilize. Do not switch the power source for the LCD system voltage regulator to V stabilization time has elapsed.

The LCD drive voltages V

LCD_DCTL register) to a value other than 0x0 (display off).

∗ DSPC[1:0]: LCD Display Control Bits in the LCD Display Control (LCD_DCTL) Register (D[1:0]/0x50a0)

When the internal LCD driver is not used, the power voltage booster and LCD system voltage regulator should

be turned off to reduce current consumption. Set PBON, VDSEL, and DSPC[1:0] to 0 (default).

C1 to VC5. When the power supply voltage (VDD) is within the range from 1.8 V to 2.5 V,

DD voltage and drive the LCD system voltage regulator

D2.

(D0/0x50a4)

(D1/0x50a4)

D2 output voltage requires about 1 ms to

D2 until the

C1 to VC5 will be supplied to the LCD driver by setting the DSPC[1:0] bits (D[1:0]/

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Power control bit settings

Table 4.3.1 lists the power control bit settings in different operating conditions.

Table 4.3.1 Power Control Bit Settings

Condition Control bits

Operating mode V

Normal

operation

Flash erase/

program

For the DSPC[1:0] settings, see “0x50a0: LCD Display Control Register (LCD_DCTL)” in Section 22.8.

DD LCD driver VD1MD PBON VDSEL DSPC[1:0]

1.8 to 2.5 V Used 0 1 1 Other than 0x0

2.5 to 3.6 V Used 0 0 0 Other than 0x0

1.8 to 3.6 V Not used 0 0 0 0x0

1.8 to 2.7 V – (use prohibited)

2.7 to 3.6 V Used 1 0 0 Other than 0x0

2.7 to 3.6 V Not used 1 0 0 0x0

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4.4 Heavy Load Protection Function

In order to ensure a stable circuit behavior and LCD display quality even if the power supply voltage fluctuates due to driving an external load, the internal logic voltage regulator and the LCD system voltage regulator have a heavy load protection function. The internal logic voltage regulator enters heavy load protection mode by writing 1 to the HVLD bit (D4/VD1_CTL register) and it ensures stable V or buzzer is driven with a port output.

∗ HVLD: VD1 Heavy Load Protection Mode Bit in the VD1 Control (VD1_CTL) Register (D4/0x5120)

The LCD system voltage regulator enters heavy load protection mode by writing 1 to the LHVLD bit (D4/ LCD_VREG register) and it ensures stable V display has inconsistencies in density.

∗ LHVLD: LCD Heavy Load Protection Mode Bit in the LCD Voltage Regulator Control (LCD_VREG) Register

(D4/0x50a3)

Note: Current consumption increases in heavy load protection mode, therefore do not set heavy load

protection mode with software if unnecessary.

D1 output. Use the heavy load protection function when a heavy load such as a lamp

C1–VC5 outputs. Use the heavy load protection function when the LCD

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4.5 Details of Control Registers

Table 4.5.1 List of Power Control Registers

Address Register name Function

0x5120 VD1_CTL VD1 Control Register Controls the VD1 voltage and heavy load protection mode. 0x50a3 LCD_VREG LCD Voltage Regulator Control Register Controls the LCD drive voltage regulator. 0x50a4 LCD_PWR LCD Power Voltage Booster Control Register Controls the LCD voltage booster.

The following describes each power control register. These are all 8-bit registers.

Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.”

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0x5120: VD1 Control Register (VD1_CTL)

D1 Control

D[7:5] Reserved

D4 HVLD: V

Sets the internal logic voltage regulator into heavy load protection mode. 1 (R/W): Heavy load protection On 0 (R/W): Heavy load protection Off (default)

The internal logic voltage regulator enters heavy load protection mode by writing 1 to HVLD and it

D[3:1] Reserved

D0 VD1MD: Flash Erase/Program Mode Bit

Selects the V 1 (R/W): V 0 (R/W): V

0x5120

(8 bits)

ensures stable V

–

D7–5

HVLD

–

D3–1

VD1MD

D1 Heavy Load Protection Mode Bit

D1 output. Use the heavy load protection function when a heavy load such as a lamp

reserved – – – 0 when being read.

D1 heavy load protection mode 1 On 0 Off 0 R/W

V reserved – – – 0 when being read. Flash erase/program mode 1

Flash (2.5 V)0Norm.(1.8 V)

0 R/W

or buzzer is driven with a port output. Current consumption increases in heavy load protection mode, therefore do not set if unnecessary.

D1 internal operating voltage value (operating mode). D1 = 2.5 V, Flash erase/program mode D1 = 1.8 V, Normal operation mode (default)

Normally set VD1MD to 0 (VD1 = 1.8 V, default setting). It should be set to 1 before erasing/

programming the Flash memory.

Note: When the operating mode is switched, the internal operating voltage requires 5 ms (max.)

to stabilize. Flash memory programming should be started after the stabilization time has elapsed.

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0x50a3: LCD Voltage Regulator Control Register (LCD_VREG)

LCD Voltage Regulator Control Register (LCD_VREG)

D[7:5] Reserved

D4 LHVLD: LCD Heavy Load Protection Mode Bit

Sets the LCD system voltage regulator into heavy load protection mode. 1 (R/W): Heavy load protection On 0 (R/W): Heavy load protection Off (default)

The LCD system voltage regulator enters heavy load protection mode by writing 1 to LHVLD and it

D[3:0] Reserved

0x50a3

(8 bits)

ensures stable V

–

D7–5

LHVLD

–

D3–0

C1–VC5 outputs. Use the heavy load protection function when the LCD display has

reserved – – – 0 when being read. LCD heavy load protection mode reserved – – – 0 when being read.

1 On 0 Off 0 R/W

inconsistencies in density. Current consumption increases in heavy load protection mode, therefore do not set if unnecessary.

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0x50a4: LCD Power Voltage Booster Control Register (LCD_PWR)

LCD Power Voltage Booster Control Register (LCD_PWR)

D[7:2] Reserved

D1 VDSEL: Regulator Power Source Select Bit

Selects the power source voltage for the LCD system voltage regulator. 1 (R/W): VD2 0 (R/W): VDD (default)

When the power supply voltage (V

D0 PBON: Power Voltage Booster Control Bit

Controls the power voltage booster. 1 (R/W): On 0 (R/W): Off (default)

0x50a4

(8 bits)

drive the LCD system voltage regulator with the V

D7–2

D1 D0

–

VDSEL PBON

reserved – – – 0 when being read.

Regulator power source select Power voltage booster control 1 On 0 Off 0 R/W

DD) is within the range from 1.8 V to 2.5 V, write 1 to VDSEL to

1VD2 0VDD 0 R/W

D2 voltage output from the power voltage booster.

Before this setting though, write 1 to PBON (D0) to turn the power voltage booster on.

DD) is 2.5 V or more, write 0 to VDSEL to drive the LCD system

voltage regulator with V

DD. In this case, the power voltage booster should be turned off to reduce

current consumption.

When the power supply voltage (V

the power voltage booster on. The power voltage booster doubles the V

DD) is within the range from 1.8 V to 2.5 V, write 1 to PBON to turn

DD voltage to generate VD2 for

driving the LCD system voltage regulator. In addition, set VDSEL (D1) to 1 to drive the LCD system voltage regulator with V

D2. It is not necessary to generate VD2 when the power supply voltage (VDD) is 2.5

V or more. In this case, the power voltage booster should be turned off to reduce current consumption.

Note: When the power voltage booster is turned on, the V

D2 output voltage requires about 1 ms to

stabilize. Do not switch the power source for the LCD system voltage regulator to V stabilization time has elapsed.

D2 until the

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4.6 Precautions

• Be sure to avoid using the VD1, VD2, and VC1–VC5 pin outputs to drive external circuits.

DD is used as the power source for the LCD system voltage regulator when VDD is 2.5 V or less, the VC1 to

• If V V

C5 voltages cannot be generated within the specifications.

• When the operating mode is switched, the internal operating voltage requires 5 ms (max.) to stabilize. Flash memory programming should be started after the stabilization time has elapsed.

• When the power voltage booster is turned on, the V switch the power source for the LCD system voltage regulator to V

D2 output voltage requires about 1 ms to stabilize. Do not

D2 until the stabilization time has elapsed.

• Current consumption increases in heavy load protection mode, therefore do not set heavy load protection mode with software if unnecessary.

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5 Initial Reset

5.1 Initial Reset Sources

The S1C17704 has three initial reset sources that initialize the internal circuits.

(1) #RESET pin (external initial reset) (2) Key-entry reset using the P0 ports (P00–P03 pins) (software selectable external initial reset) (3) Watchdog timer (software selectable internal initial reset)

Figure 5.1.1 shows the configuration of the initial reset circuit.

Oscillator

stabilization

wait circuit

#RESET

SRQ

5 INITIAL RESET

Internal reset

P00 P01 P02 P03

Chattering filter

Key-entry reset

control circuit

P0KRST

Watchdog

timer

WDTMD

Figure 5.1.1 Configuration of Initial Reset Circuit

Digital

noise filter

The CPU and peripheral circuits are initialized by the active signal from an initial reset source. When the reset signal is negated, the CPU starts reset handling. The reset handling reads the reset vector (reset handler start address) from the beginning of the vector table and starts executing the program (initial routine) beginning with the read address.

5.1.1 #RESET Pin

By setting the #RESET pin to low level, the S1C17704 enters initial reset state. In order to initialize the S1C17704 for sure, the #RESET pin must be held at low for more than the prescribed time (see Section 26.6, “AC Characteristics”) after the power supply voltage is supplied. Initial reset state is canceled when the #RESET pin at low level is set to high level and the CPU starts executing the reset interrupt handler. The #RESET pin is equipped with a pull-up resistor.

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5.1.2 P0 Port Key-Entry Reset

Entering low level simultaneously to the ports (P00–P03) selected with software triggers an initial reset. The ports used for the reset function can be selected with the P0KRST[1:0] bits (D[1:0]/P0_KRST register).

∗ P0KRST[1:0]: P0 Port Key-Entry Reset Configuration Bits in the P0 Port Key-Entry Reset Configuration

For example, if P0KRST[1:0] is set to 0x3, an initial reset will take place when the four ports P00–P03 are set to low level at the same time.

Notes: • When using the P0 port key-entry reset function, make sure that the designated input ports

will not be simultaneously set to low level while the application program is running.

• The P0 port key-entry reset function cannot be used for power-on reset as it must be enabled

with software.

• The P0 port key-entry reset function cannot be used in SLEEP mode.

(P0_KRST) Register (D[1:0]/0x5209)

Table 5.1.2.1 Configuration of P0 Port Key-Entry Reset

P0KRST[1:0] Port used for resetting

0x3 P00, P01, P02, P03 0x2 P00, P01, P02 0x1 P00, P01 0x0 Not used

5.1.3 Resetting by the Watchdog Timer

The S1C17704 has a built-in watchdog timer to detect runaway of the CPU. The watchdog timer overflows if it is not reset with software (due to CPU runaway) in four-second cycles. The overflow signal can generate either NMI or reset. Write 1 to the WDTMD bit (D1/WDT_ST register) to generate reset (NMI occurs when WDTMD = 0).

∗ WDTMD: NMI/Reset Mode Select Bit in the Watchdog Timer Status (WDT_ST) Register (D1/0x5041)

For details of the watchdog timer, see Chapter 17, “Watchdog Timer (WDT).”

Notes: • When using the reset function of the watchdog timer, program the watchdog timer so that it

will be reset within four-second cycles to avoid occurrence of an unnecessary reset.

• The reset function of the watchdog timer cannot be used for power-on reset as it must be

enabled with software.

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5 INITIAL RESET

5.2 Initial Reset Sequence

Even if the #RESET pin input negates the reset signal after power is turned on, the CPU cannot boot up until the oscillation stabilization waiting time (1024/f Figure 5.2.1 shows the operating sequence following cancellation of initial reset. The CPU starts operating in synchronization with the OSC3 clock after reset state is canceled.

∗ f

OSC3: OSC3 clock frequency

Note: The oscillation stabilization time described in this section does not include oscillation start time.

Therefore the time interval until the CPU starts executing instructions after power is turned on or SLEEP mode is canceled may be longer than that indicated in the figure below.

OSC3 clock

OSC3 seconds*) has elapsed.

#RESET

Internal reset

Internal data request

Internal data address

Figure 5.2.1 Operation Sequence Following Cancellation of Initial Reset

Reset canceled

Oscillation stabilization

waiting time

Internal reset canceled

Boot vector

Booting

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5.3 Initial Settings After an Initial Reset

The CPU internal registers are initialized as follows at initial reset.

R0–R7: 0x0 PSR: 0x0 (interrupt level = 0, interrupt disabled) SP: 0x0 PC: Reset vector stored at the beginning of the vector table is loaded by the reset handling.

The internal RAM and display memory should be initialized with software as they are not initialized at initial reset.

The internal peripheral modules are initialized to the default values (except some undefined registers). Change the settings with software if necessary. For the default values set at initial reset, see the list of I/O registers in Appendix or descriptions for each peripheral module.

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6 INTERRUPT CONTROLLER (ITC)

6 Interrupt Controller (ITC)

6.1 Configuration of ITC

The S1C17704 provides 16 interrupt systems listed below.

1. P00–P07 input interrupt (8 types)

2. P10–P17 input interrupt (8 types)

3. Stopwatch timer interrupt (3 types)

4. Clock timer interrupt (4 types)

5. 8-bit OSC1 timer interrupt (1 type)

6. SVD interrupt (1 type)

7. LCD interrupt (1 type)

8. PWM & capture timer interrupt (2 types)

9. 8-bit timer interrupt (1 type)

10. 16-bit timer Ch.0 interrupt (1 type)

11. 16-bit timer Ch.1 interrupt (1 type)

12. 16-bit timer Ch.2 interrupt (1 type)

13. UART interrupt (3 types)

14. Remote controller interrupt (3 types)

15. SPI interrupt (2 types)

16. I

C interrupt (2 types)

Each interrupt system provides an interrupt flag that indicates the occurrence of an interrupt request from the peripheral module and an interrupt enable bit that enables/disables interrupts. In addition, the ITC allows the application program to set the interrupt level (priority) of each interrupt system that determines the order of handling when two or more interrupts occur at the same time. ( ) in the list above represents the number of interrupt causes supported in each interrupt system. Use the control register in the peripheral module to select the interrupt causes for generating an interrupt request. For more information on interrupt causes and control, see the description for each peripheral module. Figure 6.1.1 shows the structure of the interrupt system.

S1C17 Core

Interrupt request

Interrupt level

Vector number

NMI

Interrupt controller

Interrupt

control

Watchdog timer

Debug signal Reset signal

Interrupt

Interrupt flag

Interrupt enable bit

Interrupt level

Vector number

• • • • •

Interrupt flag

Interrupt enable bit

Interrupt level

Vector number

request

Interrupt request

Figure 6.1.1 Interrupt System

Peripheral module

• •

Peripheral module

• •

Interrupt flag

Interrupt enable

Interrupt flag

Interrupt enable

• • • • • • •

Interrupt flag

Interrupt enable

Interrupt flag

Interrupt enable

Cause of interrupt 1

Cause of interrupt n

Cause of interrupt 1

Cause of interrupt n

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6.2 Vector Table

The vector table contains the vectors to the interrupt handler routines (handler routine start address) that will be read by the S1C17 Core to execute the handler when an interrupt occurs. The vector table is located at address 0x8000 in the S1C17704. The vector table base address can be read out from TTBR (Vector Table Base Register) located at address 0xffff80. Table 6.2.1 shows the vector table of the S1C17704.

Table 6.2.1 Vector Table

Vector No.

Software interrupt No.

0 (0x00) 0x8000 Reset • Low input to the #RESET pin

1 (0x01) 0x8004 Address misaligned interrupt Memory access instruction 2

7 (0x07) 0x801c Clock timer interrupt • 32 Hz timer signal

8 (0x08) 0x8020 8-bit OSC1 timer interrupt Compare match 9 (0x09) 0x8024 SVD interrupt Low supply voltage detected

10 (0x0a) 0x8028 LCD interrupt Frame signal 11 (0x0b) 0x802c PWM & capture timer interrupt • Compare match A

12 (0x0c) 0x8030 8-bit timer interrupt Timer underﬂ ow 13 (0x0d) 0x8034 16-bit timer Ch.0 interrupt Timer underﬂ ow 14 (0x0e) 0x8038 16-bit timer Ch.1 interrupt Timer underﬂ ow

15 (0x0f) 0x803c 16-bit timer Ch.2 interrupt Timer underﬂ ow

16 (0x10) 0x8040 UART interrupt • Transmit buffer empty

17 (0x11) 0x8044 Remote controller interrupt • Data length counter underﬂ ow

18 (0x12) 0x8048 SPI interrupt • Transmit buffer empty

19 (0x13) 0x804c I

20 (0x14) 0x8050 reserved –

:: : : ↓

31 (0x1f) 0x807c reserved – Low

∗1 When the same interrupt level is set ∗2 Either reset or NMI can be selected as the watchdog timer interrupt with software.

Vector numbers 4 to 19 are assigned to the maskable interrupts supported by the S1C17704.

Vector address Hardware interrupt name Cause of hardware interrupt Priority

• Watchdog timer overﬂ ow

brk

instruction, etc. 3

• 10 Hz timer signal

• 1 Hz timer signal

• 8 Hz timer signal

• 2 Hz timer signal

• 1 Hz timer signal

• Compare match B

• Receive buffer full

• Receive error

• Input rising edge detected

• Input falling edge detected

C interrupt • Transmit buffer empty

• Receive buffer full

∗2

∗

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6 INTERRUPT CONTROLLER (ITC)

6.3 Control of Maskable Interrupts

6.3.1 Enabling ITC

Before the ITC can be used, set the ITEN bit (D0/ITC_CTL register) to 1.

∗ ITEN: ITC Enable Bit in the ITC Control (ITC_CTL) Register (D0/0x4304)

6.3.2 Interrupt Request from Peripheral Module and Interrupt Flag

When an enabled interrupt cause occurs in a peripheral module, the module sends an interrupt request signal to the ITC. The interrupt request signal sets the interrupt flag in the ITC corresponding to the cause of interrupt to 1. The interrupt flag holds 1 until it is reset to 0 to indicate that an interrupt request has sent from the peripheral module. The flag status can be read from the ITC_IFLG register (0x4300). Table 6.3.2.1 lists the relationship between the causes of interrupt and the interrupt flags.

Table 6.3.2.1 Causes of Hardware Interrupt and Interrupt Flags

Vector No. Cause of hardware interrupt Interrupt flag

4 P0 port interrupt: P00–P07 port inputs EIFT0 (D0/ITC_IFLG register)

5 P1 port interrupt: P10–P17 port inputs EIFT1 (D1/ITC_IFLG register)

6 Stopwatch timer interrupt: 100 Hz/10 Hz/1 Hz signal EIFT2 (D2/ITC_IFLG register)

7 Clock timer interrupt: 32 Hz/8 Hz/2 Hz/1 Hz signal EIFT3 (D3/ITC_IFLG register)

8 8-bit OSC1 timer interrupt: compare match EIFT4 (D4/ITC_IFLG register)

9 SVD interrupt: low supply voltage detection EIFT5 (D5/ITC_IFLG register)

10 LCD interrupt: frame signal EIFT6 (D6/ITC_IFLG register) 11 PWM & capture timer interrupt: compare A/compare B match EIFT7 (D7/ITC_IFLG register) 12 8-bit timer interrupt: timer underflow IIFT0 (D8/ITC_IFLG register) 13 16-bit timer Ch.0 interrupt: timer underflow IIFT1 (D9/ITC_IFLG register) 14 16-bit timer Ch.1 interrupt: timer underflow IIFT2 (D10/ITC_IFLG register) 15 16-bit timer Ch.2 interrupt: timer underflow IIFT3 (D11/ITC_IFLG register) 16

UART interrupt:

17 Remote controller interrupt: data length counter underflow/input rising

edge/input falling edge

18 SPI interrupt: transmit buffer empty/receive buffer full IIFT6 (D14/ITC_IFLG register)

19 I

C interrupt: transmit buffer empty/receive buffer full IIFT7 (D15/ITC_IFLG register)

transmit buffer empty/receive buffer full/receive error IIFT4 (D12/ITC_IFLG register)

IIFT5 (D13/ITC_IFLG register)

The ITC uses the interrupt flags to generate an interrupt to the S1C17 Core. When an interrupt flag is set to 1, the ITC sends the interrupt request, interrupt level and vector number signals to the S1C17 Core if the interrupt has been enabled (see the next section).

The interrupt flag that has been set to 1 can be reset by writing 1. Reset the interrupt flag to 0 in the interrupt handler. If the interrupt handler does not reset the interrupt flag, the same interrupt will be generated again when the interrupt handling has finished (interrupts are disabled during interrupt handling and enabled by executing the reti instruction placed at the end of the interrupt handler).

Note, however, that the interrupt flags (EIFT0–EIFT7) for the level triggered interrupts (see Section 6.3.5) cannot be reset by writing 1. Those interrupt flags are reset when the interrupt signal is negated by the interrupt source.

For the occurrence conditions of the causes of interrupt and the module specific settings, refer to the section that describes the interrupt source module.

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6.3.3 Enabling/Disabling Interrupts

To send an interrupt request to the S1C17 Core, the interrupt must be enabled one by one using the interrupt enable bit in the ITC_EN register (0x4302) corresponding to the interrupt flag. To enable an interrupt, set the interrupt enable bit to 1; to disable an interrupt, set the interrupt enable bit to 0 (default). The interrupt enable bit does not affect the interrupt flag status, so the interrupt flag will be set when an interrupt request from the peripheral module occurs regardless of how the interrupt enable bit is set. Table 6.3.3.1 lists the correspondence between the interrupt enable bit and the interrupt flag.

Table 6.3.3.1 List of Interrupt Enable Bits

Vector No. Hardware interrupt Interrupt flag Interrupt enable bit

4 P0 port interrupt EIFT0 (D0/ITC_IFLG register) EIEN0 (D0/ITC_EN register) 5 P1 port interrupt EIFT1 (D1/ITC_IFLG register) EIEN1 (D1/ITC_EN register) 6 Stopwatch timer interrupt EIFT2 (D2/ITC_IFLG register) EIEN2 (D2/ITC_EN register) 7 Clock timer interrupt EIFT3 (D3/ITC_IFLG register) EIEN3 (D3/ITC_EN register) 8 8-bit OSC1 timer interrupt EIFT4 (D4/ITC_IFLG register) EIEN4 (D4/ITC_EN register) 9 SVD interrupt EIFT5 (D5/ITC_IFLG register) EIEN5 (D5/ITC_EN register)

10 LCD interrupt EIFT6 (D6/ITC_IFLG register) EIEN6 (D6/ITC_EN register)

11 PWM & capture timer interrupt EIFT7 (D7/ITC_IFLG register) EIEN7 (D7/ITC_EN register) 12 8-bit timer interrupt IIFT0 (D8/ITC_IFLG register) IIEN0 (D8/ITC_EN register) 13 16-bit timer Ch.0 interrupt IIFT1 (D9/ITC_IFLG register) IIEN1 (D9/ITC_EN register) 14 16-bit timer Ch.1 interrupt IIFT2 (D10/ITC_IFLG register) IIEN2 (D10/ITC_EN register) 15 16-bit timer Ch.2 interrupt IIFT3 (D11/ITC_IFLG register) IIEN3 (D11/ITC_EN register) 16

UART interrupt 17 Remote controller interrupt IIFT5 (D13/ITC_IFLG register) IIEN5 (D13/ITC_EN register) 18 SPI interrupt IIFT6 (D14/ITC_IFLG register) IIEN6 (D14/ITC_EN register)

19 I

C interrupt IIFT7 (D15/ITC_IFLG register) IIEN7 (D15/ITC_EN register)

IIFT4 (D12/ITC_IFLG register) IIEN4 (D12/ITC_EN register)

Notes: • To avoid unexpected interrupts being generated, always be sure to reset the interrupt flag

before enabling the interrupt by writing 1 to the interrupt enable bit.

• In addition to the interrupt enable bit, the IE bit of the Processor Status Register (PSR) in the S1C17 Core must be set to 1 to actually generate an interrupt. If the IE bit has been set to 0, the S1C17 Core cannot accept a maskable interrupt request. In this case, the interrupt request sent from the ITC is held and it will be accepted after the IE bit is set to 1.

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6.3.4 Processing when Multiple Interrupts Occur

The ITC provides the ITC_ELVx and ITC_ILVx registers (0x4306 to 0x4314) to set an interrupt level (zero to seven) for each cause of interrupt.

Table 6.3.4.1 Interrupt Level Setup Bits

Vector No. Hardware interrupt Interrupt level setup bits Register address

4 P0 port interrupt EILV0[2:0] (D[2:0]/ITC_ELV0 register) 0x4306 5 P1 port interrupt EILV1[2:0] (D[10:8]/ITC_ELV0 register) 0x4306 6 Stopwatch timer interrupt EILV2[2:0] (D[2:0]/ITC_ELV1 register) 0x4308 7 Clock timer interrupt EILV3[2:0] (D[10:8]/ITC_ELV1 register) 0x4308 8 8-bit OSC1 timer interrupt EILV4[2:0] (D[2:0]/ITC_ELV2 register) 0x430a

9 SVD interrupt EILV5[2:0] (D[10:8]/ITC_ELV2 register) 0x430a 10 LCD interrupt EILV6[2:0] (D[2:0]/ITC_ELV3 register) 0x430c 11 PWM & capture timer interrupt EILV7[2:0] (D[10:8]/ITC_ELV3 register) 0x430c 12 8-bit timer interrupt IILV0[2:0] (D[2:0]/ITC_ILV0 register) 0x430e 13 16-bit timer Ch.0 interrupt IILV1[2:0] (D[10:8]/ITC_ILV0 register) 0x430e 14 16-bit timer Ch.1 interrupt IILV2[2:0] (D[2:0]/ITC_ILV1 register) 0x4310 15 16-bit timer Ch.2 interrupt IILV3[2:0] (D[10:8]/ITC_ILV1 register) 0x4310 16

UART interrupt 17 Remote controller interrupt IILV5[2:0] (D[10:8]/ITC_ILV2 register) 0x4312 18 SPI interrupt IILV6[2:0] (D[2:0]/ITC_ILV3 register) 0x4314

19 I

C interrupt IILV7[2:0] (D[10:8]/ITC_ILV3 register) 0x4314

The highest interrupt level is 7 and the lowest is 0. The set interrupt level is sent to the S1C17 Core at the same time the ITC sends an interrupt request and is used by the S1C17 Core to disable subsequent interrupts that have the same or a lower interrupt level. (See Section 6.3.6 for more information.) At initial reset, the interrupt levels are all set to 0. The S1C17 Core does not accept an interrupt request whose interrupt level is set to 0.

IILV4[2:0] (D[2:0]/ITC_ILV2 register) 0x4312

In the ITC, the interrupt level is used when two or more causes of interrupt occur simultaneously. If two or more causes of interrupt that have been enabled by the interrupt enable bits occur simultaneously, the cause of interrupt whose ITC_ELVx or ITC_ILVx register contains the highest value is allowed by the ITC to send an interrupt request to the S1C17 Core. If two or more causes of interrupt that have the same interrupt level occur, the interrupt with the smallest vector number is processed first. Other causes of interrupt are kept pending until all interrupts of higher priority are accepted by the S1C17 Core. If another cause of interrupt of higher priority occurs during outputting an interrupt request signal, the ITC changes the vector number and interrupt level to that of the new cause of interrupt. The first interrupt request is left pending.

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6.3.5 Interrupt Trigger Mode

The ITC provides two trigger modes, the pulse trigger mode and the level trigger mode, to accept either a pulse signal or a level signal as interrupt requests from the interrupt sources that set EIFT flags. The trigger mode can be selected using the EITGx bit in the set to 1, level trigger mode is selected; when EITGx is set to 0 (default), pulse trigger mode is selected.

Note: Set all EITGx bits to 1 (level trigger mode) in the S1C17704.

Table 6.3.5.1 Trigger Mode Select Bits

Hardware interrupt Trigger mode select bit Register address

P0 port interrupt EITG0 (D4/ITC_ELV0 register) 0x4306 P1 port interrupt EITG1 (D12/ITC_ELV0 register) 0x4306 Stopwatch timer interrupt EITG2 (D4/ITC_ELV1 register) 0x4308 Clock timer interrupt EITG3 (D12/ITC_ELV1 register) 0x4308 8-bit OSC1 timer interrupt EITG4 (D4/ITC_ELV2 register) 0x430a SVD interrupt EITG5 (D12/ITC_ELV2 register) 0x430a LCD interrupt EITG6 (D4/ITC_ELV3 register) 0x430c PWM & capture timer interrupt EITG7 (D12/ITC_ELV3 register) 0x430c

The interrupt source modules that set the IIFT flags output only a pulse signal to the ITC to request an interrupt, therefore, no trigger mode select bit is provided.

Pulse trigger mode

In pulse trigger mode, the ITC samples interrupt signals at the rising edge of the system clock. When a high

pulse is sampled, the ITC sets the interrupt flag (IIFTx) to 1 and stops sampling of that interrupt signal. The ITC resumes the sampling operation for the interrupt signal after the interrupt flag (IIFTx) is reset to 0 in the application program (interrupt handler).

ITC_ELVx

registers (0x4

306 to 0x430c). When EITGx is

pclk

Interrupt signal

from an interrupt source

Interrupt flag in ITC

The software writes 1 to the interrupt flag to reset.

Figure 6.3.5.1 Pulse Trigger Mode

Note: The following S1C17704 interrupts use pulse trigger mode. When an interrupt occurs, reset (write

1 to) the interrupt flag IIFTx in the interrupt handler routine.

• 8-bit timer interrupt

• 16-bit timer Ch.0 interrupt

• 16-bit timer Ch.1 interrupt

• 16-bit timer Ch.2 interrupt

• UART interrupt

• Remote controller interrupt

• SPI interrupt

• I

C interrupt

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Level trigger mode

In level trigger mode, the ITC continuously samples interrupt signals at every rising edge of the system clock.

The interrupt flag (EIFTx) is set to 1 when a high level is sampled and is reset to 0 when a low level is sampled. In this mode, writing 1 cannot reset the interrupt flag (EIFTx). Therefore, the interrupt source module must hold the interrupt signal to high until the S1C17 Core accepts the interrupt request and must reset the interrupt signal after that.

pclk

Interrupt signal

from an interrupt source

Interrupt flag in ITC

The interrupt source negates the interrupt signal.

Figure 6.3.5.2 Level Trigger Mode

Note: The following S1C17704 interrupts use level trigger mode. The interrupt handler routine must

reset (write 1 to) the interrupt flag provided in the peripheral module, not EIFTx.

• P0 port interrupt

• P1 port interrupt

• Stopwatch timer interrupt

• Clock timer interrupt

• 8-bit OSC1 timer interrupt

• SVD interrupt

• LCD interrupt

• PWM & capture timer interrupt

For the interrupt flag to be reset, see the description for each peripheral module.

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6.3.6 Interrupt Processing by the S1C17 Core

A maskable interrupt to the S1C17 Core occurs when all of the conditions described below are met.

• The ITEN bit (D0/ITC_CTL register) is set to 1.

∗ ITEN: ITC Enable Bit in the ITC Control (ITC_CTL) Register (D0/0x4304)

• The interrupt enable bit for the cause of interrupt that has occurred is set to 1.

• The IE (Interrupt Enable) bit of the PSR (Processor Status Register) in the S1C17 Core is set to 1.

• The cause of interrupt that has occurred has a higher interrupt level than the value that is set in the IL field of the PSR.

• No other cause of interrupt having higher priority, such as NMI, has occurred.

When a cause of interrupt occurs, the corresponding interrupt flag is set to 1 and the flag remains set until it is reset in the software program or by the hardware for a level triggered interrupt. Therefore, in no cases can the generated cause of interrupt be inadvertently cleared even if the above conditions are not met when the cause of interrupt has occurred. The interrupt will occur when the above conditions are met. If two or more maskable causes of interrupt occur simultaneously, the cause of interrupt that has the highest priority is allowed to signal an interrupt request to the S1C17 Core. The other interrupts with lower priorities are kept pending until the above conditions are met.

The S1C17 Core keeps sampling interrupt requests every cycle. When the S1C17 Core accepts an interrupt request, it enters interrupt processing after completing execution of the instruction that was being executed. The following lists the contents executed in interrupt processing.

(1) The PSR and the current program counter (PC) value are saved to the stack. (2) The IE bit of the PSR is reset to 0 (following maskable interrupts are disabled). (3) The IL of the PSR is set to the interrupt level of the accepted interrupt (NMI does not change the interrupt

level).

(4) The vector of the interrupt occurred is loaded into the PC, thus executing the interrupt handler routine.

Thus, once an interrupt is accepted, all maskable interrupts that may follow are disabled in (2). Multiple interrupts can also be handled by setting the IE bit to 1 in the interrupt handler routine. In this case, since the IL has been changed in (3), only an interrupt that has a higher level than that of the currently processed interrupt is accepted. When the interrupt handler routine is terminated by the reti instruction, the PSR is restored to its previous status before the interrupt has occurred. The program restarts processing after branching to the instruction next to the one that was being executed when the interrupt occurred.

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6.4 NMI

In the S1C17704, the watchdog timer generates a non-maskable interrupt (NMI). The vector number of NMI is 2, with the vector address set to the vector table's starting address + 8 bytes. This interrupt is prioritized over other interrupts and is unconditionally accepted by the S1C17 Core.

For how to generate NMI, see Chapter 17, “Watchdog Timer (WDT).”

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6.5 Software Interrupts

The S1C17 Core provides the int imm5 and intl imm5,imm3 instructions allowing the software to generate any interrupts. The operand imm5 specifies a vector number (0–31) in the vector table. In addition to this, the intl instruction has the operand imm3 to specify the interrupt level (0–7) to be set to the IL field in the PSR. The processor performs the same interrupt handling as that of the hardware interrupt.

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6.6 Clearing HALT and SLEEP Modes by Interrupt Causes

A cause of interrupt clears HALT or SLEEP mode to start up the CPU. The program execution sequence (whether it branches to the interrupt handler routine) after the CPU starts up depends on the clock status in HALT/SLEEP mode. See “C.1 Power Saving by Clock Control” in Appendix C for details.

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6.7 Details of Control Registers

Table 6.7.1 List of ITC Registers

Address Register name Function

0x4300 ITC_IFLG Interrupt Flag Register Indicates/resets interrupt occurrence status. 0x4302 ITC_EN Interrupt Enable Register Enables/disables each maskable interrupt. 0x4304 ITC_CTL ITC Control Register Enables/disables the ITC. 0x4306 ITC_ELV0 External Interrupt Level Setup Register 0 Sets the P0 and P1 interrupt levels and trigger modes. 0x4308 ITC_ELV1 External Interrupt Level Setup Register 1 Sets the stopwatch timer and clock timer interrupt levels and trigger modes. 0x430a ITC_ELV2 External Interrupt Level Setup Register 2 Sets the 8-bit OSC1 timer and SVD interrupt levels and trigger modes. 0x430c ITC_ELV3 External Interrupt Level Setup Register 3 Sets the LCD and PWM & capture timer interrupt levels and trigger modes. 0x430e ITC_ILV0 Internal Interrupt Level Setup Register 0 Sets the 8-bit timer and 16-bit timer Ch.0 interrupt levels. 0x4310 ITC_ILV1 Internal Interrupt Level Setup Register 1 Sets the 16-bit timer Ch.1 and 16-bit timer Ch.2 interrupt levels. 0x4312 ITC_ILV2 Internal Interrupt Level Setup Register 2 Sets the UART and remote controller interrupt levels. 0x4314 ITC_ILV3 Internal Interrupt Level Setup Register 3 Sets the SPI and I

The following describes each ITC register. These are all 16-bit registers.

Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.”

C interrupt levels.

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0x4300: Interrupt Flag Register (ITC_IFLG)

Interrupt Flag Register (ITC_IFLG)

0x4300

(16 bits)

D15 D14 D13 D12 D11 D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

IIFT7 IIFT6 IIFT5 IIFT4 IIFT3 IIFT2 IIFT1 IIFT0 EIFT7 EIFT6 EIFT5 EIFT4 EIFT3 EIFT2 EIFT1 EIFT0

D[15:8] IIFT[7:0]: Interrupt Flags (for Pulse Trigger)

These bits are interrupt flags to indicate the interrupt cause occurrence status. 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred (default) 1 (W): Flag is reset 0 (W): Has no effect

The interrupt flag is set to 1 when a cause of interrupt occurs in each peripheral circuit. If the following conditions are met at this time, an interrupt is generated to the S1C17 Core:

1. The corresponding bit of the Interrupt Enable Register is set to 1.

2. No other interrupt request of higher priority has occurred.

3. The IE bit of the PSR is set to 1 (interrupt enabled).

4. The corresponding interrupt level setup bits are set to a level higher than the S1C17 Core's interrupt level (IL).

C interrupt flag 1 Cause of SPI interrupt flag 0 R/W Remote controller interrupt flag 0 R/W UART interrupt flag 0 R/W 16-bit timer Ch.2 interrupt flag 0 R/W 16-bit timer Ch.1 interrupt flag 0 R/W 16-bit timer Ch.0 interrupt flag 0 R/W 8-bit timer interrupt flag 0 R/W PWM&capture timer interrupt flag 1 Cause of LCD interrupt flag 0 R/W SVD interrupt flag 0 R/W 8-bit OSC1 timer interrupt flag 0 R/W Clock timer interrupt flag 0 R/W Stopwatch timer interrupt flag 0 R/W P1 port interrupt flag 0 R/W P0 port interrupt flag 0 R/W

interrupt occurred

0 Cause of

interrupt not occurred

0 Cause of

interrupt not occurred

0 R/W Reset by writing 1.

0 R/W Reset by writing 1 in

pulse trigger mode.

Cannot be reset by software in level trigger mode.

The interrupt flag is always set to 1 when a cause of interrupt occurs regardless of how the interrupt

enable and interrupt level setup bits are set.

In order for the next interrupt to be accepted after interrupt generation, the interrupt flag must be reset

and the PSR must be set up again (by setting the IE bit to 1 or executing the reti instruction).

The flag that has been set to 1 can be reset by writing 1.

Table 6.7.2 Causes of Hardware Interrupt and Interrupt Flags

Interrupt flag Cause of hardware interrupt

IIFT0 (D8) 8-bit timer interrupt: timer underflow IIFT1 (D9) 16-bit timer Ch.0 interrupt: timer underflow IIFT2 (D10) 16-bit timer Ch.1 interrupt: timer underflow IIFT3 (D11) 16-bit timer Ch.2 interrupt: timer underflow IIFT4 (D12) IIFT5 (D13) Remote controller interrupt: data length counter underflow/input rising edge/

IIFT6 (D14) SPI interrupt: transmit buffer empty/receive buffer full IIFT7 (D15) I

UART interrupt:

transmit buffer empty/receive buffer full/receive error

input falling edge

C interrupt: transmit buffer empty/receive buffer full

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D[7:0] EIFT[7:0]: Interrupt Flags (for Level Trigger)

See the description for IIFT[7:0]. However, these interrupts must be set to level trigger mode using the ITC_ELVx register (0x4306 to

0x430c). Therefore, EIFTx cannot be reset by writing 1. To reset the EIFTx, write 1 to the interrupt flag in the peripheral module.

Table 6.7.3 Causes of Hardware Interrupt and Interrupt Flags

Interrupt flag Cause of hardware interrupt

EIFT0 (D0) P0 port interrupt: P00–P07 port inputs EIFT1 (D1) P1 port interrupt: P10–P17 port inputs EIFT2 (D2) Stopwatch timer interrupt: 100 Hz/10 Hz/1 Hz signal EIFT3 (D3) Clock timer interrupt: 32 Hz/8 Hz/2 Hz/1 Hz signal EIFT4 (D4) 8-bit OSC1 timer interrupt: compare match EIFT5 (D5) SVD interrupt: low supply voltage detection EIFT6 (D6) LCD interrupt: frame signal EIFT7 (D7) PWM & capture timer interrupt: compare A/compare B match

Note: Even when a maskable interrupt request is accepted by the S1C17 Core and control branches off

to the interrupt handler routine, the interrupt flag is not reset. Consequently, if control is returned from the interrupt handler routine by the reti instruction without resetting the interrupt flag in a program, the same cause of interrupt occurs again. The interrupt flag of the level triggered interrupt must be reset using the control register in the peripheral module.

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0x4302: Interrupt Enable Register (ITC_EN)

Interrupt Enable Register (ITC_EN)

0x4302

(16 bits)

D15 D14 D13 D12 D11 D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

IIEN7 IIEN6 IIEN5 IIEN4 IIEN3 IIEN2 IIEN1 IIEN0 EIEN7 EIEN6 EIEN5 EIEN4 EIEN3 EIEN2 EIEN1 EIEN0

D[15:8] IIEN[7:0], EIEN[7:0]: Interrupt Enable Bits

These bits enable or disable interrupt generation. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default)

Interrupts are enabled when the corresponding interrupt enable bit is set to 1 and are disabled when the

bit is set to 0.

Table 6.7.4 Causes of Hardware Interrupt and Interrupt Enable Bits

Interrupt

enable bits

EIEN0 (D0) P0 port interrupt: P00–P07 port inputs EIEN1 (D1) P1 port interrupt: P10–P17 port inputs EIEN2 (D2) Stopwatch timer interrupt: 100 Hz/10 Hz/1 Hz signal EIEN3 (D3) Clock timer interrupt: 32 Hz/8 Hz/2 Hz/1 Hz signal EIEN4 (D4) 8-bit OSC1 timer interrupt: compare match EIEN5 (D5) SVD interrupt: low supply voltage detection EIEN6 (D6) LCD interrupt: frame signal EIEN7 (D7) PWM & capture timer interrupt: compare A/compare B match IIEN0 (D8) 8-bit timer interrupt: timer underflow IIEN1 (D9) 16-bit timer Ch.0 interrupt: timer underflow IIEN2 (D10) 16-bit timer Ch.1 interrupt: timer underflow IIEN3 (D11) 16-bit timer Ch.2 interrupt: timer underflow IIEN4 (D12) IIEN5 (D13) Remote controller interrupt: data length counter underflow/input rising edge/

IIEN6 (D14) SPI interrupt: transmit buffer empty/receive buffer full IIEN7 (D15) I

UART interrupt:

input falling edge

C interrupt enable 1 Enable 0 Disable 0 R/W SPI interrupt enable 0 R/W Remote controller interrupt enable 0 R/W UART interrupt enable 0 R/W 16-bit timer Ch.2 interrupt enable 0 R/W 16-bit timer Ch.1 interrupt enable 0 R/W 16-bit timer Ch.0 interrupt enable 0 R/W 8-bit timer interrupt enable 0 R/W PWM&capture timer interrupt enable LCD interrupt enable 0 R/W SVD interrupt enable 0 R/W 8-bit OSC1 timer interrupt enable 0 R/W Clock timer interrupt enable 0 R/W Stopwatch timer interrupt enable 0 R/W P1 port interrupt enable 0 R/W P0 port interrupt enable 0 R/W

Cause of hardware interrupt

transmit buffer empty/receive buffer full/receive error

C interrupt: transmit buffer empty/receive buffer full

0 R/W

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0x4304: ITC Control Register (ITC_CTL)

ITC Control Register (ITC_CTL)

0x4304

(16 bits)

D[15:1] Reserved

D0 ITEN: ITC Enable Bit

Enables the ITC to control interrupt generation. 1 (R/W): Enable 0 (R/W): Disable (default)

Before the ITC can be used, this bit must be set to 1.

D15–1

–

ITEN

reserved – – – 0 when being read.

ITC enable 1 Enable 0 Disable 0 R/W

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0x4306: External Interrupt Level Setup Register 0 (ITC_ELV0)

External Interrupt Level Setup Register 0 (ITC_ELV0)

0x4306

(16 bits)

D[15:13] Reserved

D12 EITG1: P1 Port Interrupt Trigger Mode Select Bit

Selects the trigger mode of the P1 port interrupt. Set this bit 1 in the S1C17704. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default)

In pulse trigger mode, the ITC samples interrupt signals at the rising edge of the system clock. When a

high pulse is sampled, the ITC sets the interrupt flag (EIFTx) to 1 and stops sampling of that interrupt signal. The ITC resumes the sampling operation for the interrupt signal after the interrupt flag (EIFTx) is reset to 0 in the application program (interrupt handler).

In level trigger mode, the ITC continuously samples interrupt signals at every rising edge of the system

clock. The interrupt flag (EIFTx) is set to 1 when a high level is sampled and is reset to 0 when a low level is sampled. In this mode, writing 1 cannot reset the interrupt flag (EIFTx). Therefore, the interrupt source module must hold the interrupt signal to high until the S1C17 Core accepts the interrupt request and must reset the interrupt signal after that.

D11 Reserved

D15–13

D12 D11

D10–8

D7–5

D4 D3

D2–0

– EITG1 – EILV1[2:0] – EITG0 – EILV0[2:0]

reserved – – – 0 when being read. P1 interrupt trigger mode 1 Level 0 Pulse 0 R/W Be sure to set to 1. reserved – – – 0 when being read. P1 interrupt level 0 to 7 0x0 R/W reserved – – – 0 when being read. P0 interrupt trigger mode 1 Level 0 Pulse 0 R/W Be sure to set to 1. reserved – – – 0 when being read. P0 interrupt level 0 to 7 0x0 R/W

D[10:8] EILV1[2:0]: P1 Port Interrupt Level Bits

Sets the interrupt level (0 to 7) of the P1 port interrupt. (Default: 0) If the level is set below the IL value of the PSR, the S1C17 Core does not accept the interrupt request. In the ITC, the interrupt level is used when two or more causes of interrupt occur simultaneously. If two or more causes of interrupt that have been enabled by the interrupt enable register occur

simultaneously, the cause of interrupt whose Interrupt Level Setup Register contains the highest value is allowed by the ITC to send an interrupt request to the S1C17 Core. If two or more causes of interrupt that have the same interrupt level occur, the interrupt with the smallest vector number is processed first. Other causes of interrupt are kept pending until all interrupts of higher priority are accepted by the S1C17 Core. If another cause of interrupt of higher priority occurs during outputting an interrupt request signal, the ITC changes the vector number and interrupt level to those of the new cause of interrupt. The first interrupt request is left pending.

D[7:5] Reserved

D4 EITG0: P0 Port Interrupt Trigger Mode Select Bit

Selects the trigger mode of the P0 port interrupt. Set this bit 1 in the S1C17704. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default)

See the description of EITG1 (D12).

D3 Reserved

D[2:0] EILV0[2:0]: P0 Port Interrupt Level Bits

Sets the interrupt level (0 to 7) of the P0 port interrupt. (Default: 0) See the description of EILV1[2:0] (D[10:8]).

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0x4308: External Interrupt Level Setup Register 1 (ITC_ELV1)

External Interrupt Level Setup Register 1 (ITC_ELV1)

0x4308

(16 bits)

D[15:13] Reserved

D12 EITG3: Clock Timer Interrupt Trigger Mode Select Bit

Selects the trigger mode of the clock timer interrupt. Set this bit 1 in the S1C17704. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default)

See the description of EITG1 (D12) in the ITC_ELV0 register (0x4306).

D11 Reserved

D[10:8] EILV3[2:0]: Clock Timer Interrupt Level Bits

Sets the interrupt level (0 to 7) of the clock timer interrupt. (Default: 0) See the description of EILV1[2:0] (D[10:8]) in the ITC_ELV0 register (0x4306).

D[7:5] Reserved

D15–13

D12 D11

D10–8

D7–5

D4 D3

D2–0

– EITG3 – EILV3[2:0] – EITG2 – EILV2[2:0]

reserved – – – 0 when being read. CT interrupt trigger mode 1 Level 0 Pulse 0 R/W Be sure to set to 1. reserved – – – 0 when being read. CT interrupt level 0 to 7 0x0 R/W reserved – – – 0 when being read. SWT interrupt trigger mode 1 Level 0 Pulse 0 R/W Be sure to set to 1. reserved – – – 0 when being read. SWT interrupt level 0 to 7 0x0 R/W

D4 EITG2: Stopwatch Timer Interrupt Trigger Mode Select Bit

Selects the trigger mode of the stopwatch timer interrupt. Set this bit 1 in the S1C17704. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default)

See the description of EITG1 (D12) in the ITC_ELV0 register (0x4306).

D3 Reserved

D[2:0] EILV2[2:0]: Stopwatch Timer Interrupt Level Bits

Sets the interrupt level (0 to 7) of the stopwatch timer interrupt. (Default: 0) See the description of EILV1[2:0] (D[10:8]) in the ITC_ELV0 register (0x4306).

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0x430a: External Interrupt Level Setup Register 2 (ITC_ELV2)

External Interrupt Level Setup Register 2 (ITC_ELV2)

0x430a

(16 bits)

D[15:13] Reserved

D12 EITG5: SVD Interrupt Trigger Mode Select Bit

Selects the trigger mode of the SVD interrupt. Set this bit 1 in the S1C17704. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default)

See the description of EITG1 (D12) in the ITC_ELV0 register (0x4306).

D11 Reserved

D[10:8] EILV5[2:0]: SVD Interrupt Level Bits

Sets the interrupt level (0 to 7) of the SVD interrupt. (Default: 0) See the description of EILV1[2:0] (D[10:8]) in the ITC_ELV0 register (0x4306).

D[7:5] Reserved

D15–13

D12 D11

D10–8

D7–5

D4 D3

D2–0

– EITG5 – EILV5[2:0] – EITG4 – EILV4[2:0]

reserved – – – 0 when being read. SVD interrupt trigger mode 1 Level 0 Pulse 0 R/W Be sure to set to 1. reserved – – – 0 when being read. SVD interrupt level 0 to 7 0x0 R/W reserved – – – 0 when being read. T8OSC1 interrupt trigger mode 1 Level 0 Pulse 0 R/W Be sure to set to 1. reserved – – – 0 when being read. T8OSC1 interrupt level 0 to 7 0x0 R/W

D4 EITG4: 8-bit OSC1 Timer Interrupt Trigger Mode Select Bit

Selects the trigger mode of the 8-bit OSC1 timer interrupt. Set this bit 1 in the S1C17704. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default)

See the description of EITG1 (D12) in the ITC_ELV0 register (0x4306).

D3 Reserved

D[2:0] EILV4[2:0]: 8-bit OSC1 Timer Interrupt Level Bits

Sets the interrupt level (0 to 7) of the 8-bit OSC1 timer interrupt. (Default: 0) See the description of EILV1[2:0] (D[10:8]) in the ITC_ELV0 register (0x4306).

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0x430c: External Interrupt Level Setup Register 3 (ITC_ELV3)

External Interrupt Level Setup Register 3 (ITC_ELV3)

0x430c

(16 bits)

D[15:13] Reserved

D12 EITG7: PWM & Capture Timer Interrupt Trigger Mode Select Bit

Selects the trigger mode of the PWM & capture timer interrupt. Set this bit 1 in the S1C17704. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default)

See the description of EITG1 (D12) in the ITC_ELV0 register (0x4306).

D11 Reserved

D[10:8] EILV7[2:0]: PWM & Capture Timer Interrupt Level Bits

Sets the interrupt level (0 to 7) of the PWM & capture timer interrupt. (Default: 0) See the description of EILV1[2:0] (D[10:8]) in the ITC_ELV0 register (0x4306).

D[7:5] Reserved

D15–13

D12 D11

D10–8

D7–5

D4 D3

D2–0

– EITG7 – EILV7[2:0] – EITG6 – EILV6[2:0]

reserved – – – 0 when being read. T16E interrupt trigger mode 1 Level 0 Pulse 0 R/W Be sure to set to 1. reserved – – – 0 when being read. T16E interrupt level 0 to 7 0x0 R/W reserved – – – 0 when being read. LCD interrupt trigger mode 1 Level 0 Pulse 0 R/W Be sure to set to 1. reserved – – – 0 when being read. LCD interrupt level 0 to 7 0x0 R/W

D4 EITG6: LCD Interrupt Trigger Mode Select Bit

Selects the trigger mode of the LCD interrupt. Set this bit 1 in the S1C17704. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default)

See the description of EITG1 (D12) in the ITC_ELV0 register (0x4306).

D3 Reserved

D[2:0] EILV6[2:0]: LCD Interrupt Level Bits

Sets the interrupt level (0 to 7) of the LCD interrupt. (Default: 0) See the description of EILV1[2:0] (D[10:8]) in the ITC_ELV0 register (0x4306).

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0x430e: Internal Interrupt Level Setup Register 0 (ITC_ILV0)

Internal Interrupt Level Setup Register 0 (ITC_ILV0)

0x430e

(16 bits)

D[15:11] Reserved

D[10:8] IILV1[2:0]: 16-bit Timer Ch.0 Interrupt Level Bits

Sets the interrupt level (0 to 7) of the 16-bit timer Ch.0 interrupt. (Default: 0) If the level is set below the IL value of the PSR, the S1C17 Core does not accept the interrupt request. In the ITC, the interrupt level is used when two or more causes of interrupt occur simultaneously. If two or more causes of interrupt that have been enabled by the interrupt enable register occur

simultaneously, the cause of interrupt whose Interrupt Level Setup Register contains the highest value is allowed by the ITC to send an interrupt request to the S1C17 Core.

If two or more causes of interrupt that have the same interrupt level occur, the interrupt with the

smallest vector number is processed first.

Other causes of interrupt are kept pending until all interrupts of higher priority are accepted by the

S1C17 Core.

If another cause of interrupt of higher priority occurs during outputting an interrupt request signal,

the ITC changes the vector number and interrupt level to those of the new cause of interrupt. The first interrupt request is left pending.

D[7:3] Reserved

D15–11

D10–8

D7–3 D2–0

– IILV1[2:0] – IILV0[2:0]

reserved – – – 0 when being read. T16 Ch.0 interrupt level 0 to 7 0x0 R/W reserved – – – 0 when being read. T8 interrupt level 0 to 7 0x0 R/W

D[2:0] IILV0[2:0]: 8-bit Timer Interrupt Level Bits

Sets the interrupt level (0 to 7) of the 8-bit timer interrupt. (Default: 0) See the description of IILV1[2:0] (D[10:8]).

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0x4310: Internal Interrupt Level Setup Register 1 (ITC_ILV1)

Internal Interrupt Level Setup Register 1 (ITC_ILV1)

0x4310

(16 bits)

D[15:11] Reserved

D[10:8] IILV3[2:0]: 16-bit Timer Ch.2 Interrupt Level Bits

Sets the interrupt level (0 to 7) of the 16-bit timer Ch.2 interrupt. (Default: 0) See the description of IILV1[2:0] (D[10:8]) in the ITC_ILV0 register (0x430e).

D[7:3] Reserved

D[2:0] IILV2[2:0]: 16-bit Timer Ch.1 Interrupt Level Bits

Sets the interrupt level (0 to 7) of the 16-bit timer Ch.1 interrupt. (Default: 0) See the description of IILV1[2:0] (D[10:8]) in the ITC_ILV0 register (0x430e).

D15–11

D10–8

D7–3 D2–0

– IILV3[2:0] – IILV2[2:0]

reserved – – – 0 when being read. T16 Ch.2 interrupt level 0 to 7 0x0 R/W reserved – – – 0 when being read. T16 Ch.1 interrupt level 0 to 7 0x0 R/W

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0x4312: Internal Interrupt Level Setup Register 2 (ITC_ILV2)

Internal Interrupt Level Setup Register 2 (ITC_ILV2)

0x4312

(16 bits)

D[15:11] Reserved

D[10:8] IILV5[2:0]: Remote Controller Interrupt Level Bits

Sets the interrupt level (0 to 7) of the remote controller interrupt. (Default: 0) See the description of IILV1[2:0] (D[10:8]) in the ITC_ILV0 register (0x430e).

D[7:3] Reserved

D[2:0] IILV4[2:0]: UART Interrupt Level Bits

Sets the interrupt level (0 to 7) of the UART interrupt. (Default: 0) See the description of IILV1[2:0] (D[10:8]) in the ITC_ILV0 register (0x430e).

D15–11

D10–8

D7–3 D2–0

– IILV5[2:0] – IILV4[2:0]

reserved – – – 0 when being read. REMC interrupt level 0 to 7 0x0 R/W reserved – – – 0 when being read. UART interrupt level 0 to 7 0x0 R/W

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0x4314: Internal Interrupt Level Setup Register 3 (ITC_ILV3)

Internal Interrupt Level Setup Register 3 (ITC_ILV3)

0x4314

(16 bits)

D[15:11] Reserved

D[10:8] IILV7[2:0]: I

Sets the interrupt level (0 to 7) of the I See the description of IILV1[2:0] (D[10:8]) in the ITC_ILV0 register (0x430e).

D[7:3] Reserved

D[2:0] IILV6[2:0]: SPI Interrupt Level Bits

Sets the interrupt level (0 to 7) of the SPI interrupt. (Default: 0) See the description of IILV1[2:0] (D[10:8]) in the ITC_ILV0 register (0x430e).

–

D15–11

IILV7[2:0]

D10–8

–

D7–3

IILV6[2:0]

D2–0

C Interrupt Level Bits

reserved – – – 0 when being read.

C interrupt level 0 to 7 0x0 R/W

I reserved – – – 0 when being read. SPI interrupt level 0 to 7 0x0 R/W

C interrupt. (Default: 0)

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6.8 Precautions

• To prevent another interrupt from being generated for the same cause again after generation of an interrupt,

be sure to reset the interrupt flag before enabling interrupts and setting the PSR again or executing the reti instruction.

• The following S1C17704 interrupts use level trigger mode.

- P0 port interrupt

- P1 port interrupt

- Stopwatch timer interrupt

- Clock timer interrupt

- 8-bit OSC1 timer interrupt

- SVD interrupt

- LCD interrupt

- PWM & capture timer interrupt

Set all EITGx bits in the ITC_ELVx register (0x4306 to 0x430c) to 1 (level trigger mode). Furthermore, the interrupt handler routine must reset (write 1 to) the interrupt flag provided in the peripheral

module, not EIFTx. For the interrupt flag to be reset, see the description for each peripheral module.

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7 Oscillator (OSC)

7.1 Configuration of OSC Module

The S1C17704 has two built-in oscillators (OSC3 and OSC1). The OSC3 oscillator generates the main clock (Max.

8.2 MHz) for operating the S1C17 Core and peripheral circuits at high speed. The OSC1 oscillator generates the sub clock (Typ. 32.768 kHz) for operating timers and for power saving operations. At initial reset, the OSC3 clock is selected as the system clock. The oscillators can be turned on and off and the system clock can be switched between OSC1 and OSC3 with software. The OSC module allows the software to turn the oscillators on and off and to switch the system clock source between OSC1 and OSC3. Furthermore, the clocks generated in the OSC module can be output outside the IC. Figure 7.1.1 shows the structure of the clock system and the OSC3 module.

OSC3

OSC4

FOUT3

OSC1

OSC2

SLEEP, On/Off control

OSC3 oscillator

(8.2 MHz)

FOUT3 output circuit

On/Off control

SLEEP, On/Off control

OSC1 oscillator

(32.768 kHz)

wakeup

Wait circuit for wakeup

Divider (1/1–1/4)

Division ratio select

OSC

Clock source select

OSC3

OSC1

System

clock

Gear select

Clock gear (1/1–1/8)

On/Off control

Gate

Gate S1C17 Core

Gate

HALT

CLG

CCLK

BCLK

PCLK

Internal bus, RAM, Flash

ITC, T16, T8F, UART, SPI, I2C, T16E, P, MISC, VD1, SVD, REMC, Control registers (CT, SWT, WDT, T8OSC1, LCD)

FOUT1

RESET

NMI

FOUT1 output circuit

On/Off control

Noise filter

On/Off control

Noise filter

On/Off control

OSC3

Division ratio select

S1C17 Core

Divider (1/32–1/512)

OSC1

Clock source select

OSC1

On/Off control

Gate

Divider

(1/128)

(1/1–1/32)

Division ratio select On/Off control

Divider (1/1–1/16K)

Gate

Gate LCD

On/Off control

PSC

CLK_256Hz

LCLK

T8F, T16, T16E, REMC, P, UART, SPI, I2C

CT, SWT, WDT

T8OSC1

SVD

Figure 7.1.1 Structure of the OSC Module

Current consumption can be reduced by controlling the clocks according to the processing requirements as well as by using the standby mode. For methods to reduce current consumption, see Appendix C, “Power Saving.”

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7.2 OSC3 Oscillator

The OSC3 oscillator generates the main clock (Max. 8.2 MHz) for operating the S1C17 Core and peripheral circuits at high speed. Depending on the product number, the oscillator type is crystal/ceramic oscillation (Max. 8.2 MHz) or CR oscillation (Max. 2.2 MHz).

Table 7.2.1 Lineup

Model No. Main (OSC3) oscillator

S1C17704F00B100 S1C17704F00E100

Figure 7.2.1 shows the structure of the OSC3 oscillator circuit.

Crystal/Ceramic

CG3

CD3

VSS

OSC3

X'tal3 or Ceramic

OSC4

(1) Crystal/ceramic oscillator circuit

fOSC3

Oscillator control signal SLEEP status

fOSC3

CR3

OSC4

(2) CR oscillator circuit

Figure 7.2.1 OSC3 Oscillator Circuit

Oscillator control signal SLEEP status

When the crystal/ceramic oscillator model is selected, connect a crystal (X’tal3) or ceramic resonator (Ceramic) and a feedback resistor (R OSC4 pins and V

SS.

When the CR oscillator model is selected, connect only a resistor (R

f) between the OSC3 and OSC4 pins, and two capacitors (CG3, CD3) to the OSC3 and

CR3) between the OSC3 and OSC4 pins.

Controlling the OSC3 oscillation on and off

Setting OSC3EN (D0/OSC_CTL register) to 0 causes the OSC3 oscillator circuit to stop; setting it to 1 causes

the OSC3 oscillator circuit to start oscillating. Also the OSC3 oscillator circuit stops when the S1C17 Core enters SLEEP mode.

∗ OSC3EN: OSC3 Enable Bit in the Oscillation Control (OSC_CTL) Register (D0/0x5061)

At initial reset, OSC3EN is set to 1 for enabling OSC3 oscillation. Furthermore, the OSC3 clock is selected as

the system clock, so the S1C17 Core starts operating with the OSC3 clock.

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Stable oscillation wait time when OSC3 starts oscillating

The OSC3 oscillator circuit provides an oscillation stabilization-wait timer to prevent malfunctions caused by

an unstable clock immediately after the OSC3 oscillator starts oscillating such as when the power is turned on, when the S1C17 Core is woken from SLEEP mode or when software turns the OSC3 oscillator circuit on. The OSC3 clock supply is disabled until the time set to the timer has elapsed after the OSC3 oscillator starts oscillating.

The stable oscillation wait time can be selected from four kinds of number of clock cycles using OSC3WT[1:0]

(D[5:4]/OSC_CTL register).

∗

OSC3WT[1:0]: OSC3 Wait Cycle Select Bits in the Oscillation Control (OSC_CTL) Register (D[5:4]/0x5061)

Table 7.2.2 Setting Stable Oscillation Wait Time

OSC3WT[1:0] Stable oscillation wait time

0x3 128 cycles 0x2 256 cycles 0x1 512 cycles 0x0 1024 cycles

(Default: 0x0)

The stable oscillation wait time is set to 1024 OSC3 clock cycles at initial reset, the S1C17 Core does not start

operating until the set time has elapsed after releasing reset status.

Note: The oscillation start time varies depending on the resonator and externally attached parts. Set

the stable oscillation wait time with a safety margin. Refer to the oscillation start time example described in Chapter 26, “Electrical Characteristics.”

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7.3 OSC1 Oscillator

The OSC3 oscillator generates the 32.768 kHz (Typ.) sub-clock. Normally, the OSC1 clock is used as the operating clock for timers (clock timer, stopwatch timer, watchdog timer, and 8-bit OSC1 timer). Furthermore, it can be used as the system clock instead of the OSC3 clock to reduce current consumption when high-speed processing is not required. The oscillator type is crystal oscillation. Figure 7.3.1 shows the structure of the OSC1 oscillator circuit.

SLEEP status

OSC1

CG1

X'tal1

fOSC1

OSC2

VSS

Figure 7.3.1 OSC1 Oscillator Circuit

VSS

To configure a crystal oscillator, connect a crystal X’tal1 (Typ. 32.768 kHz) between the OSC1 and OSC1 pins, and a trimmer capacitor C

G1 (0–25 pF) between the OSC1 and VSS.

Controlling the OSC1 oscillation on and off

Setting OSC1EN (D1/OSC_CTL register) to 0 causes the OSC1 oscillator circuit to stop; setting it to 1 causes

the OSC1 oscillator circuit to start oscillating. Also the OSC1 oscillator circuit stops when the S1C17 Core enters SLEEP mode.

∗ OSC1EN: OSC1 Enable Bit in the Oscillation Control (OSC_CTL) Register (D1/0x5061)

Stable oscillation wait time when OSC1 starts oscillating

The OSC1 oscillator circuit provides an oscillation stabilization-wait timer to prevent malfunctions caused by

an unstable clock immediately after the OSC1 oscillator starts oscillating such as when the power is turned on, when the S1C17 Core is woken from SLEEP mode or when software turns the OSC1 oscillator circuit on. The OSC1 clock supply to the system is disabled for 256 OSC1 clock cycles after the OSC1 oscillator starts oscillating.

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7.4 Switching the System Clock

The OSC module allows software to switch the system clock between the OSC3 and OSC1 clocks. Current consumption can be reduced by disabling the OSC3 oscillation after the system clock is switched to OSC1. The following shows the control procedure:

OSC3 to OSC1

1. Set OSC1EN (D1/OSC_CTL register) to 1 to start the OSC1 oscillation if it is disabled.

∗ OSC1EN: OSC1 Enable Bit in the Oscillation Control (OSC_CTL) Register (D1/0x5061)

2. Set CLKSRC (D0/OSC_SRC register) to 1 to switch the system clock from OSC3 to OSC1.

∗ CLKSRC: System Clock Source Select Bit in the Clock Source Select (OSC_SRC) Register (D0/0x5060)

3. If the application does not need the peripheral modules clocked with OSC3 to operate, set OSC3EN (D0/ OSC_CTL register) to 0 to stop the OSC3 oscillation.

∗ OSC3EN: OSC3 Enable Bit in the Oscillation Control (OSC_CTL) Register (D0/0x5061)

Notes: • When the system clock is switched from OSC3 to OSC1 immediately after the OSC1 oscillator

starts oscillating, the system clock is halted until the OSC1 clock is activated (256 OSC1 clock-cycle period).

• The OSC3 oscillation cannot be stopped before switching the system clock to OSC1.

OSC1 to OSC3

1. Set a stable oscillation wait time (see Table 7.2.2) longer than the OSC3 oscillation start time using OSC3WT[1:0] (D[5:4]/OSC_CTL register). (This control is not necessary if it has been set already.)

∗ OSC3WT[1:0]: OSC3 Wait Cycle Select Bits in the Oscillation Control (OSC_CTL) Register (D[5:4]/0x5061)

2. Set OSC3EN (D0/OSC_CTL register) to 1 to start the OSC3 oscillation if it is disabled. The OSC3 clock is not supplied to the system until the wait time set in OSC3WT[1:0] (D[5:4]/OSC_CTL register) has elapsed after the OSC3 oscillator starts oscillating.

3. Set CLKSRC (D0/OSC_SRC register) to 0 to switch the system clock from OSC1 to OSC3.

4. If the application does not need the peripheral modules clocked with OSC1 to operate, set OSC1EN (D1/ OSC_CTL register) to 0 to stop the OSC1 oscillation.

Notes: • Skip Steps 1 and 2 when the OSC2 oscillator circuit is operating.

• The OSC3 oscillation start time varies depending on the resonator and externally attached parts. Set the stable oscillation wait time with a safety margin. Refer to the oscillation start time example described in Chapter 26, “Electrical Characteristics.”

• The OSC1 oscillation cannot be stopped before switching the system clock to OSC3.

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7.5 Controlling the LCD Clock

The OSC module incorporates the LCD clock generator to generate the operating clock (LCLK) for the LCD driver. See Chapter 22, “LCD Driver (LCD),” for details of the LCD driver.

Division ratio select

OSC3 clock

OSC1 clock

Selecting the source clock

Use LCKSRC (D1/OSC_LCLK register) to select either OSC1 or OSC3 as the source clock to generate the

LCD clock. When LCKSRC is 1 (default), OSC1 is selected and when it is set to 1, OSC3 is selected.

∗ LCKSRC: LCD Clock Source Select Bit in the LCD Clock Setup (OSC_LCLK) Register (D1/0x5063)

Selecting a clock division ratio

When the OSC1 clock is used

When OSC1 is selected as the source clock, it is not necessary to select a division ratio. The OSC1 clock (Typ.

32.768 kHz) is sent directly to the LCD driver.

Divider (1/32–1/512)

Figure 7.5.1 LCD Clock Generator

Clock source

select

Gate

On/Off control

LCLK

LCD driver

When the OSC3 clock is used

When OSC3 is selected as the source clock, select a division ratio using LCKDV[2:0] (D[4:2]/OSC_LCLK

∗ LCKDV[2:0]: LCD Clock Division Ratio Select Bits in the LCD Clock Setup (OSC_LCLK) Register

(D[4:2]/0x5063)

Table 7.5.1 Selecting Division Ratio for LCD Clock

LCKDV[2:0] Division ratio

0x7–0x5 Reserved

0x4 OSC3•1/512 0x3 OSC3•1/256 0x2 OSC3•1/128 0x1 OSC3•1/64 0x0 OSC3•1/32

(Default: 0x0)

Controlling the clock supply

Use LCKEN (D0/OSC_LCLK register) to control the clock supply to the LCD driver. LCKEN is set to 0 by

default and the clock supply is disabled. When LCKEN is set to 1, the clock generated with the above conditions is supplied to the LCD driver. If display on the LCD is not necessary, disable the clock supply to reduce current consumption.

∗ LCKEN: LCD Clock Enable Bit in the LCD Clock Setup (OSC_LCLK) Register (D0/0x5063)

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7.6 Controlling the 8-bit OSC1 Timer Clock

The OSC module incorporates a frequency divider and a clock supply control circuit for the 8-bit OSC1 timer. The 8-bit OSC1 timer is a programmable timer that operates with a divided OSC1 clock. See Chapter 14, “8-bit OSC1 Timer (T8OSC1),” for details of the 8-bit OSC1 timer.

OSC1 clock

Divider (1/1–1/32)

Division ratio select On/Off control

Figure 7.6.1 8-bit OSC1 Timer Clock Control Circuit

Selecting a clock division ratio

Select a clock division ratio of the OSC1 clock using T8O1CK[2:0] (D[3:1]/OSC_T8OSC1 register).

∗ T8O1CK[2:0]: T8OSC1 Clock Division Ratio Select Bits in the T8OSC1 Clock Control (OSC_T8OSC1)

Table 7.6.1 Selecting Division Ratio for Generating T8OSC1 Clock

T8O1CK[2:0] Division ratio

0x7–0x6 Reserved

0x5 OSC1•1/32 0x4 OSC1•1/16 0x3 OSC1•1/8 0x2 OSC1•1/4 0x1 OSC1•1/2 0x0 OSC1•1/1

Gate

8-bit OSC1 timer

(Default: 0x0)

Controlling the clock supply

Use T8O1CE (D0/OSC_T8OSC1 register) to control the clock supply to the 8-bit OSC1 timer. T8O1CE is set to 0 by default and the clock supply is disabled. When T8O1CE is set to 1, the clock generated with the above conditions is supplied to the 8-bit OSC1 timer. When the application does not need the 8-bit OSC1 timer to run, disable the clock supply to reduce current consumption.

∗ T8O1CE: T8OSC1 Clock Enable Bit in the T8OSC1 Clock Control (OSC_T8OSC1) Register (D0/0x5065)

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7.7 External Output Clock (FOUT3, FOUT1)

A divided OSC3 clock (FOUT3) and the OSC1 clock (FOUT1) can be output to external devices.

P30 port

OSC3 clock

OSC1 clock

Divider (1/1–1/4)

Division ratio select

Figure 7.7.1 Clock Output Circuit

FOUT3 output circuit

P13 port

FOUT1 output circuit

On/Off control

P30 function

select

P13 function

select

FOUT3(P30)

FOUT1(P13)

FOUT3 output

FOUT3 is a divided OSC3 clock.

Setting up the output pin

The FOUT3 output pin is shared with the P30 port and it functions as the P30 port pin by default. Write 1

to P30MUX (D0/P3_PMUX register) to switch the P30 pin function for the FOUT3 output.

∗ P30MUX: P30 Port Function Select Bit in the P3 Port Function Select (P3_PMUX) Register (D0/0x52a3)

Selecting the FOUT3 clock frequency

The output clock frequency can be selected from three kinds. Select an OSC3 clock division ratio using

FOUT3D[1:0] (D[3:2]/OSC_FOUT register) to set up the clock frequency.

∗ FOUT3D[1:0]: FOUT3 Clock Division Ratio Select Bits in the FOUT Control (OSC_FOUT) Register

Controlling the clock output

Use FOUT3E (D1/OSC_FOUT register) to control the clock output. When FOUT3E is set to 1, the FOUT3

clock is output from the FOUT3 pin and the output is disabled when FOUT3E is set to 0.

∗ FOUT3E: FOUT3 Output Enable Bit in the FOUT Control (OSC_FOUT) Register (D1/0x5064)

(D[3:2]/0x5064)

Table 7.7.1 Selecting Division Ratio for Generating FOUT3 Clock

FOUT3D[1:0] Division ratio

0x3 Reserved 0x2 OSC3•1/4 0x1 OSC3•1/2 0x0 OSC3•1/1

(Default: 0x0)

FOUT3E

FOUT3 output (P30)

001

Figure 7.7.2 FOUT3 Output

Note: The FOUT3 signal is generated asynchronously with writing to FOUT3E, therefore, a hazard will

occur when the output is enabled or disabled.

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FOUT1 output

FOUT1 is the OSC1 clock.

Setting up the output pin

The FOUT1 output pin is shared with the P13 port and it functions as the P13 port pin by default. Write 1

to P13MUX (D3/P1_PMUX register) to switch the P13 pin function for the FOUT1 output.

∗ P13MUX: P13 Port Function Select Bit in the P1 Port Function Select (P1_PMUX) Register (D3/0x52a1)

Controlling the clock output

Use FOUT1E (D0/OSC_FOUT register) to control the clock output. When FOUT1E is set to 1, the FOUT1

clock is output from the FOUT1 pin and the output is disabled when FOUT1E is set to 0.

∗ FOUT1E: FOUT1 Output Enable Bit in the FOUT Control (OSC_FOUT) Register (D0/0x5064)

FOUT1E

FOUT1 output (P13)

001

Figure 7.7.3 FOUT1 Output

Note: The FOUT1 signal is generated asynchronously with writing to FOUT1E, therefore, a hazard will

occur when the output is enabled or disabled.

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7.8 Noise Filters for RESET and NMI Inputs

If the RESET or NMI signal in the S1C17 Core input signals become active due to noise, the S1C17 Core executes unnecessary reset ot NMI handling. To avoid this, the OSC module incorporates noise filters that operate with the system clock to remove noise from these signals before they are input to the S1C17 Core. The noise filter is provided for each signal, and can be enabled or bypassed individually.

RESET input noise filter: Noise will be removed when RSTFE (D1/OSC_NFEN register) = 1; the filter is bypassed

when RSTFE = 0.

NMI input noise filter: Noise will be removed when NMIFE (D0/OSC_NFEN register) = 1; the filter is bypassed

when NMIFE = 0.

∗ RSTFE: Reset Noise Filter Enable Bit in the Noise Filter Enable (OSC_NFEN) Register (D1/0x5062) ∗ NMIFE: NMI Noise Filter Enable Bit in the Noise Filter Enable (OSC_NFEN) Register (D0/0x5062)

The noise filter operates with a divide-by-8 system clock (OSC3 or OSC1 clock). When it is enabled, pulses that have a width of less than two cycles of this operating clock will be removed as noise. Therefore, 16 system clock cycles or longer pulse width is required to accept as a valid signal.

Notes: • Enable the filter for the RESET input under normal circumstances.

• Although the S1C17704 has no external NMI input pin, the NMI request signal of the watchdog timer pass through the filter.

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7.9 Details of Control Registers

Table 7.9.1 List of OSC Registers

Address Register name Function

0x5060 OSC_SRC Clock Source Select Register Selects a clock source. 0x5061 OSC_CTL Oscillation Control Register Controls oscillation. 0x5062 OSC_NFEN Noise Filter Enable Register Enables/disables noise filters. 0x5063 OSC_LCLK LCD Clock Setup Register Sets up the LCD clock. 0x5064 OSC_FOUT FOUT Control Register Controls clock output. 0x5065 OSC_T8OSC1 T8OSC1 Clock Control Register Sets up the 8-bit OSC1 timer clock.

The following describes each OSC module control register. These are all 8-bit registers.

Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.”

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0x5060: Clock Source Select Register (OSC_SRC)

Clock Source Select

(OSC_SRC)

D[7:1] Reserved

D0 CLKSRC: System Clock Source Select Bit

Selects the system clock source. 1 (R/W): OSC1 0 (R/W): OSC3 (default)

Select OSC3 for normal (high-speed) operation. When the OSC3 clock is not necessary, select OSC1 as

Note: When the system clock is switched from OSC3 to OSC1 immediately after the OSC1 oscillator

0x5060

(8 bits)

D7–1

–

CLKSRC

reserved – – – 0 when being read.

System clock source select 1 OSC1 0 OSC3 0 R/W

the system clock and stop OSC3 oscillation to reduce current consumption.

starts oscillating, the system clock is halted until the OSC1 clock is activated (256 OSC1 clock-cycle period).

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0x5061: Oscillation Control Register (OSC_CTL)

Oscillation Control Register (OSC_CTL)

D[7:6] Reserved

D[5:4] OSC3WT[1:0]: OSC3 Wait Cycle Select Bits

Sets the stable oscillation wait time to avoid malfunctions caused by the unstable clock when the OSC3

The OSC3 clock is not supplied to the system until the wait time set here has elapsed after the OSC3

At initial reset, the oscillation stabilization wait time is set to 1024 cycles (OSC3 clock). The CPU does

0x5061

(8 bits)

D7–6 D5–4

D3–2

D1 D0

– OSC3WT[1:0]

– OSC1EN OSC3EN

reserved – – – 0 when being read. OSC3 wait cycle select OSC3WT[1:0] Wait cycle 0x0 R/W

reserved – – – 0 when being read. OSC1 enable 1 Enable 0 Disable 1 R/W OSC3 enable 1 Enable 0 Disable 1 R/W

0x3 0x2 0x1 0x0

128 cycles 256 cycles 512 cycles

1024 cycles

starts oscillating.

starts oscillating such as at power on, at wakeup from SLEEP status, or when the OSC3 oscillator is turned on with software.

Table 7.9.2 Setting the Stable OSC3 Oscillation Wait Time

OSC3WT[1:0] Stable oscillation wait time

0x3 128 cycles 0x2 256 cycles 0x1 512 cycles 0x0 1024 cycles

(Default: 0x0)

not start operating until the set time has elapsed after the reset state is canceled.

Note: The oscillation start time will vary somewhat depending on the resonator and externally

attached parts. Set the oscillation stabilization wait time allowing an adequate margin. For the oscillation start time, see an example indicated in Chapter 26, “Electrical Characteristics.”

D[3:2] Reserved

D1 OSC1EN: OSC1 Enable Bit

Enables/disables the OSC1 oscillator. 1 (R/W): Enable (On) (default) 0 (R/W): Disable (Off)

Notes: • The OSC1 oscillator cannot be disabled when OSC1 is used as the system clock.

• In order to avoid malfunctions, the OSC1 clock will not be supplied to the system for 256 OSC1 clock-cycle period when the OSC1 oscillation is started by setting OSC1EN from 0 to 1.

D0 OSC3EN: OSC3 Enable Bit

Enables/disables the OSC3 oscillator. 1 (R/W): Enable (On) (default) 0 (R/W): Disable (Off)

Note: The OSC3 oscillator cannot be disabled when OSC3 is used as the system clock.

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0x5062: Noise Filter Enable Register (OSC_NFEN)

Noise Filter Enable Register (OSC_NFEN)

0x5062

(8 bits)

D[7:2] Reserved

D1 RSTFE: Reset Noise Filter Enable Bit

Enables/disables the noise filter for the RESET input. 1 (R/W): Enable (reject noise) (default) 0 (R/W): Disable (bypass)

When the noise filter is enabled, RESET pulses that have a width of 16 system clock (OSC1 or OSC3

clock) cycles or more will pass through the filter and are input to the S1C17 Core. Pulses that have a width of less than 16 cycles will be rejected as noise. Enable the filter under normal circumstances.

D0 NMIFE: NMI Noise Filter Enable Bit

Enables/disables the noise filter for the NMI input. 1 (R/W): Enable (reject noise) 0 (R/W): Disable (bypass) (default)

When the noise filter is enabled, NMI pulses that have a width of 16 system clock (OSC1 or OSC3

clock) cycles or more will pass through the filter and are input to the S1C17 Core. Pulses that have a width of less than 16 cycles will be rejected as noise.

Note: Although the S1C17704 has no external NMI input pin, the NMI request signal of the

watchdog timer passes through the filter.

D7–2

D1 D0

– RSTFE NMIFE

reserved – – – 0 when being read. Reset noise filter enable 1 Enable 0 Disable 1 R/W NMI noise filter enable 1 Enable 0 Disable 0 R/W

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0x5063: LCD Clock Setup Register (OSC_LCLK)

LCD Clock Setup Register (OSC_LCLK

D[7:5] Reserved

D[4:2] LCKDV[2:0]: LCD Clock Division Ratio Select Bits

Selects a division ratio when OSC3 is selected for the LCD clock source.

It is not necessary to select a division ratio when OSC1 is selected for the LCD clock source.

0x5063

(8 bits)

)

D7–5 D4–2

D1 D0

– LCKDV[2:0]

LCKSRC LCKEN

reserved – – – 0 when being read. LCD clock division ratio select LCKDV[2:0] Division ratio 0x0 R/W

LCD clock source select 1 OSC1 0 OSC3 1 R/W LCD clock enable 1 Enable 0 Disable 0 R/W

0x7–0x5

0x4 0x3 0x2 0x1 0x0

reserved OSC3•1/512 OSC3•1/256 OSC3•1/128

OSC3•1/64 OSC3•1/32

Table 7.9.3 Selecting the LCD Clock Division Ratio

LCKDV[2:0] Division ratio

0x7–0x5 Reserved

0x4 OSC3•1/512 0x3 OSC3•1/256 0x2 OSC3•1/128 0x1 OSC3•1/64 0x0 OSC3•1/32

(Default: 0x0)

D1 LCKSRC: LCD Clock Source Select Bit

Select the LCD clock source. 1 (R/W): OSC1 (default) 0 (R/W): OSC3

D0 LCKEN: LCD Clock Enable Bit

Enables/disables supplying the LCD clock to the LCD driver. 1 (R/W): Enable (On) 0 (R/W): Disable (Off) (default)

LCKEN is set to 0 and the clock supply is disabled by default. By setting LCKEN to 1, the clock

configured using the control bits above is supplied to the LCD driver. If an LCD display is unnecessary, disable the clock supply to reduce current consumption.

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0x5064: FOUT Control Register (OSC_FOUT)

FOUT Control Register (OSC_FOUT

0x5064

(8 bits)

)

D[7:4] Reserved

D[3:2] FOUT3D[1:0]: FOUT3 Clock Division Ratio Select Bits

Selects a division ratio of the OSC3 clock to set the FOUT3 clock frequency.

D1 FOUT3E: FOUT3 Output Enable Bit

Enables/Disables the FOUT3 clock (OSC3 divide clock) to be output to a device outside the IC. 1 (R/W): Enable (On) 0 (R/W): Disable (Off) (default)

D7–4 D3–2

D1 D0

– FOUT3D[1:0]

FOUT3E FOUT1E

reserved – – – 0 when being read. FOUT3 clock division ratio select FOUT3D[1:0] Division ratio 0x0 R/W

FOUT3 output enable 1 Enable 0 Disable 0 R/W FOUT1 output enable 1 Enable 0 Disable 0 R/W

0x3 0x2 0x1 0x0

Table 7.9.4 Selecting Division Ratio for FOUT3 Clock

FOUT3D[1:0] Division ratio

0x3 Reserved 0x2 OSC3•1/4 0x1 OSC3•1/2 0x0 OSC3•1/1

(Default: 0x0)

reserved OSC3•1/4 OSC3•1/2 OSC3•1/1

When FOUT3E is set to 1, the FOUT3 clock is output from the FOUT3 pin, and is stopped when

FOUT3E is set to 0.

The FOUT3 pin is shared with the P30 port and it functions as the P30 port pin by default. When using

the pin for the FOUT3 output, write 1 to the P30MUX bit (D0/P3_PMUX register) to switch the pin function.

∗ P30MUX: P30 Port Function Select Bit in the P3 Port Function Select (P3_PMUX) Register

(D0/0x52a3)

D0 FOUT1E: FOUT1 Output Enable Bit

Enables/Disables the FOUT1 clock (OSC1 clock) to be output to a device outside the IC. 1 (R/W): Enable (On) 0 (R/W): Disable (Off) (default)

When FOUT1E is set to 1, the FOUT1 clock is output from the FOUT1 pin, and is stopped when

FOUT1E is set to 0.

The FOUT1 pin is shared with the P13 port and it functions as the P13 port pin by default. When using

the pin for the FOUT1 output, write 1 to the P13MUX bit (D3/P1_PMUX register) to switch the pin function.

∗ P13MUX: P13 Port Function Select Bit in the P1 Port Function Select (P1_PMUX) Register

(D3/0x52a1)

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0x5065: T8OSC1 Clock Control Register (OSC_T8OSC1)

)

0x5065

(8 bits)

T8OSC1 Clock Control Register (OSC_T8OSC1

D[7:4] Reserved

D[3:1] T8O1CK[2:0]: T8OSC1 Clock Division Ratio Select Bits

Selects a division ratio of the OSC1 clock to configure the 8-bit OSC1 timer operating clock.

–

D7–4 D3–1

T8O1CK[2:0]

T8O1CE

reserved – – – 0 when being read. T8OSC1 clock division ratio select T8O1CK[2:0] Division ratio 0x0 R/W

T8OSC1 clock output enable 1 Enable 0 Disable 0 R/W

Table 7.9.5 Selecting Division Ratio for T8OSC1 Clock

T8O1CK[2:0] Division ratio

0x7–0x6 Reserved

0x5 OSC1•1/32 0x4 OSC1•1/16 0x3 OSC1•1/8 0x2 OSC1•1/4 0x1 OSC1•1/2 0x0 OSC1•1/1

0x7–0x6

0x5 0x4 0x3 0x2 0x1 0x0

(Default: 0x0)

reserved OSC1•1/32 OSC1•1/16

OSC1•1/8 OSC1•1/4 OSC1•1/2 OSC1•1/1

D0 T8O1CE: T8OSC1 Clock Output Enable Bit

Enables/disables supplying the operating clock to the 8-bit OSC1 timer. 1 (R/W): Enable (On) 0 (R/W): Disable (Off) (default)

T8O1CE is set to 0 and the clock supply is disabled by default. By setting T8O1CE to 1, the clock

configured using the control bits above is supplied to the 8-bit OSC1 timer. If 8-bit OSC1 timer function

is unnecessary, disable the clock supply to reduce current consumption.

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7.10 Precautions

• The oscillation start time will vary somewhat depending on the resonator and externally attached parts. Set the OSC3 oscillation stabilization wait time allowing an adequate margin. For the oscillation start time, see an example indicated in Chapter 26, “Electrical Characteristics.”

• When the system clock is switched from OSC3 to OSC1 immediately after the OSC1 oscillator starts oscillating, the system clock is halted until the OSC1 clock is activated (256 OSC1 clock-cycle period).

• The OSC3 oscillator cannot be disabled when OSC3 is used as the system clock.

• The OSC1 oscillator cannot be disabled when OSC1 is used as the system clock.

• Since the FOUT3/FOUT1 signals are generated asynchronously with writing to FOUT3E/FOUT1E, a hazard may be generated when the signal is turned on or off.

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