Epson S1C17001 Technical Manual

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CMOS 16-BIT SINGLE CHIP MICROCONTROLLER

S1C17001

Technical Manual

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NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of Economy, Trade and Industry or other approval from another government agency.

All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies.

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- Contents -

1 Overview ........................................................................................................................1-1

1.1 Features .......................................................................................................................... 1-1

1-2 Block Diagram ................................................................................................................ 1-2

1.3 Pins ................................................................................................................................. 1-3

1.3.1 Pinout Diagram ................................................................................................. 1-3

1.3.2 Pin Descriptions ................................................................................................ 1-4

2 CPU ................................................................................................................................2-1

2.1 S1C17 Core Features ...................................................................................................... 2-1

2.2 CPU Registers ................................................................................................................. 2-2

2.3 Command Set ................................................................................................................. 2-3

2.4 Vector Table .................................................................................................................... 2-7

2.5 Processor Information ..................................................................................................... 2-8

3 Memory Map and Bus Control ......................................................................................3-1

3.1 Bus Cycle ........................................................................................................................ 3-2

3.1.1 Access Size Restrictions .................................................................................. 3-2

3.1.2 Command Execution Cycle Restrictions .......................................................... 3-2

3.2 Internal ROM Area ........................................................................................................... 3-3

3.2.1 Internal ROM ..................................................................................................... 3-3

3.2.2 ROM Read Access Cycle Settings ................................................................... 3-3

0x5320: ROM Control Register (MISC_FL) ............................................................................... 3-3

3.3 Internal RAM Area ........................................................................................................... 3-4

3.3.1 Internal RAM ..................................................................................................... 3-4

3.4 Internal Peripheral Circuit Area ....................................................................................... 3-5

3.4.1 Internal Peripheral Circuit Area 1 (0x4000 onward) .......................................... 3-5

3.4.2 Internal Peripheral Circuit Area 2 (0x5000 onward) .......................................... 3-5

3.4.3 I/O Map ............................................................................................................. 3-6

3.5 Core I/O Reserved Area .................................................................................................. 3-9

4 Power Supply Voltage ...................................................................................................4-1

5 Initial Reset ....................................................................................................................5-1

5.1 Initial Reset Factors ........................................................................................................ 5-1

5.1.1 #RESET pin ....................................................................................................... 5-1

5.1.2 P0 Port Key-Entry Reset ................................................................................... 5-2

5.1.3 Reset by Watchdog Timer ................................................................................ 5-2

5.2 Initial Reset Sequence .................................................................................................... 5-3

5.3 Initial Settings at Initial Resetting .................................................................................... 5-4

6 Interrupt Controller (ITC) ...............................................................................................6-1

6.1 ITC Configuration ............................................................................................................ 6-1

6.2 Vector Table .................................................................................................................... 6-2

6.3 Maskable Interrupt Control ............................................................................................. 6-3

6.3.1 ITC Enable ........................................................................................................ 6-3

6.3.2 Interrupt Request from Peripheral Module and Interrupt Flag .......................... 6-3

6.3.3 Interrupt Permission/Prohibition ....................................................................... 6-4

6.3.4 Processing for Multiple Interrupts .................................................................... 6-5

6.3.5 Interrupt Trigger Modes .................................................................................... 6-6

6.3.6 S1C17 Core Interrupt Processing ..................................................................... 6-8

6.4 NMI .................................................................................................................................. 6-9

6.5 Software Interrupts ........................................................................................................ 6-10

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6.6 HALT and SLEEP Mode Cancellation by Interrupt Factors ........................................... 6-11

6.7 Control Register Details ................................................................................................. 6-12

0x4300: Interrupt Flag Register (ITC_IFLG) .............................................................................. 6-13

0x4302: Interrupt Enable Register (ITC_EN) ............................................................................. 6-15

0x4304: ITC Control Register (ITC_CTL) .................................................................................. 6-16

0x4306: External Interrupt Level Setup Register 0 (ITC_ELV0) ................................................ 6-17

0x4308: External Interrupt Level Setup Register 1 (ITC_ELV1) ................................................ 6-18

0x430a: External Interrupt Level Setup Register 2 (ITC_ELV2) ................................................ 6-19

0x430c: External Interrupt Level Setup Register 3 (ITC_ELV3) ................................................ 6-20

0x430e: Internal Interrupt Level Setup Register 0 (ITC_ILV0) ................................................... 6-21

0x4310: Internal Interrupt Level Setup Register 1 (ITC_ILV1) ................................................... 6-22

0x4312: Internal Interrupt Level Setup Register 2 (ITC_ILV2) ................................................... 6-23

0x4314: Internal Interrupt Level Setup Register 3 (ITC_ILV3) ................................................... 6-24

6.8 Precautions .................................................................................................................... 6-25

7 Oscillator Circuit (OSC) .................................................................................................7-1

7.1 OSC Module Configuration ............................................................................................. 7-1

7.2 OSC3 Oscillator Circuit ................................................................................................... 7-2

7.3 OSC1 Oscillator Circuit ................................................................................................... 7-4

7.4 System Clock Switching ................................................................................................. 7-5

7.5 8-bit OSC1 Timer Clock Control ..................................................................................... 7-6

7.6 Clock External Output (FOUT3, FOUT1) ......................................................................... 7-7

7.7 RESET and NMI Input Noise Filters ................................................................................ 7-9

7.8 Control Register Details ................................................................................................. 7-10

0x5060: Clock Source Select Register (OSC_SRC) ................................................................. 7-11

0x5061: Oscillation Control Register (OSC_CTL) ..................................................................... 7-12

0x5062: Noise Filter Enable Register (OSC_NFEN) ................................................................. 7-13

0x5064: FOUT Control Register (OSC_FOUT) ......................................................................... 7-14

0x5065: T8OSC1 Clock Control Register (OSC_T8OSC1) ...................................................... 7-15

7.9 Precautions .................................................................................................................... 7-16

8 Clock Generator (CLG) ..................................................................................................8-1

8.1 Clock Generator Configuration ....................................................................................... 8-1

8.2 CPU Core Clock (CCLK) Control .................................................................................... 8-2

8.3 Peripheral Module Clock (PCLK) Control ........................................................................ 8-3

8.4 Control Register Details .................................................................................................. 8-4

0x5080: PCLK Control Register (CLG_PCLK) ........................................................................... 8-5

0x5081: CCLK Control Register (CLG_CCLK) .......................................................................... 8-6

8.5 Precautions ..................................................................................................................... 8-7

9 Prescaler (PSC) ..............................................................................................................9-1

9.1 Prescaler Configuration .................................................................................................. 9-1

9.2 Control Register Details .................................................................................................. 9-2

0x4020: Prescaler Control Register (PSC_CTL) ........................................................................ 9-2

9.3 Precautions ..................................................................................................................... 9-3

10 Input/Output Port (P) ..................................................................................................10-1

10.1 Input/Output Port Configuration .................................................................................. 10-1

10.2 Input/Output Port Pin Function Selection (Port MUX) ................................................. 10-2

10.3 Data Input/Output ........................................................................................................ 10-3

10.4 Pull-up Control ............................................................................................................. 10-4

10.5 Input Interface Level .................................................................................................... 10-5

10.6

P0 Port Chattering Filter Function ................................................................................ 10-6

10.7 Port Input Interrupt ....................................................................................................... 10-7

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10.8 Control Register Details .............................................................................................. 10-10

0x5200/0x5210/0x5220/0x5230: Px Port Input Data Registers (Px_IN) .................................. 10-11

0x5201/0x5211/0x5221/0x5231: Px Port Output Data Registers (Px_OUT) ........................... 10-12

0x5202/0x5212/0x5222/0x5232: Px Port I/O Direction Control Registers (Px_IO) ................. 10-13

0x5203/0x5213/0x5223/0x5233: Px Port Pull-up Control Registers (Px_PU) ......................... 10-14

0x5205/5215: Px Port Interrupt Mask Registers (Px_IMSK) .................................................... 10-15

0x5206/5216: Px Port Interrupt Edge Select Registers (Px_EDGE) ........................................ 10-16

0x5207/5217: Px Port Interrupt Flag Registers (Px_IFLG) ....................................................... 10-17

0x5208: P0 Port Chattering Filter Control Register (P0_CHAT) .............................................. 10-18

0x5209: P0 Port Key-Entry Reset Configuration Register (P0_KRST) .................................... 10-19

0x52a0: P0 Port Function Select Register (P0_PMUX) ........................................................... 10-20

0x52a1: P1 Port Function Select Register (P1_PMUX) ........................................................... 10-21

0x52a2: P2 Port Function Select Register (P2_PMUX) ........................................................... 10-22

0x52a3: P3 Port Function Select Register (P3_PMUX) ........................................................... 10-23

10.9 Precautions ................................................................................................................. 10-24

11 16-bit Timer (T16) .......................................................................................................11-1

11.1 16-bit Timer Overview .................................................................................................. 11-1

11.2 16-bit Timer Operating Modes ..................................................................................... 11-2

11.2.1 Internal Clock Mode ...................................................................................... 11-2

11.2.2 External Clock Mode ..................................................................................... 11-3

11.2.3 Pulse Width Measurement Mode .................................................................. 11-4

11.3 Count Mode ................................................................................................................. 11-5

11.4 16-bit Timer Reload Register and Underflow Cycle .................................................... 11-6

11.5 16-bit Timer Reset ....................................................................................................... 11-7

11.6 16-bit Timer RUN/STOP Control .................................................................................. 11-8

11.7 16-bit Timer Output Signal ........................................................................................... 11-9

11.8 16-bit Timer Interrupts ................................................................................................ 11-10

11.9 Control Register Details .............................................................................................. 11-11

0x4220/0x4240/0x4260: 16-bit Timer Ch.x Input Clock Select Registers (T16_CLKx) ........... 11-12

0x4222/0x4242/0x4262: 16-bit Timer Ch.x Reload Data Registers (T16_TRx) ....................... 11-13

0x4224/0x4244/0x4264: 16-bit Timer Ch.x Counter Data Registers (T16_TCx) ..................... 11-14

0x4226/0x4246/0x4266: 16-bit Timer Ch.x Control Registers (T16_CTLx) ............................. 11-15

11.10 Precautions ............................................................................................................... 11-17

12 8-bit Timer (T8F) .........................................................................................................12-1

12.1 8-bit Timer Overview .................................................................................................... 12-1

12.2 8-bit Timer Count Mode ............................................................................................... 12-2

12.3 Count Clock ................................................................................................................. 12-3

12.4 8-bit Timer Reload Register and Underflow Cycle ...................................................... 12-4

12.5 8-bit Timer Reset ......................................................................................................... 12-5

12.6 8-bit Timer RUN/STOP Control .................................................................................... 12-6

12.7 8-bit Timer Output Signal ............................................................................................. 12-7

12.8 Fine Mode .................................................................................................................... 12-8

12.9 8-bit Timer Interrupts ................................................................................................... 12-9

12.10 Control Register Details ............................................................................................ 12-10

0x4200: 8-bit Timer Input Clock Select Register (T8F_CLK) .................................................. 12-11

0x4202: 8-bit Timer Reload Data Register (T8F_TR) ............................................................... 12-12

0x4204: 8-bit Timer Counter Data Register (T8F_TC) ............................................................. 12-13

0x4206: 8-bit Timer Control Register (T8F_CTL) ..................................................................... 12-14

12.11 Precautions ............................................................................................................... 12-16

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13 PWM & Capture Timer (T16E) ....................................................................................13-1

13.1 PWM & Capture Timer Overview ................................................................................. 13-1

13.2 PWM & Capture Timer Operating Modes .................................................................... 13-2

13.3 Setting and Resetting Counter Value ........................................................................... 13-3

13.4 Compare Data Settings ................................................................................................ 13-4

13.5 PWM & Capture Timer RUN/STOP Control ................................................................. 13-5

13.6 Clock Output Control ................................................................................................... 13-6

13.7 PWM & Capture Timer Interrupts ................................................................................. 13-9

13.8 Control Register Details .............................................................................................. 13-11

0x5300: PWM Timer Compare Data A Register (T16E_CA) .................................................... 13-12

0x5302: PWM Timer Compare Data B Register (T16E_CB) .................................................... 13-13

0x5304: PWM Timer Counter Data Register (T16E_TC) ......................................................... 13-14

0x5306: PWM Timer Control Register (T16E_CTL) ................................................................. 13-15

0x5308: PWM Timer Input Clock Select Register (T16E_CLK) ............................................... 13-17

0x530a: PWM Timer Interrupt Mask Register (T16E_IMSK) ................................................... 13-18

0x530c: PWM Timer Interrupt Flag Register (T16E_IFLG) ...................................................... 13-19

13.9 Precautions ................................................................................................................. 13-20

14 8-bit OSC1 Timer (T8OSC1) .......................................................................................14-1

14.1 8-bit OSC1 Timer Overview ......................................................................................... 14-1

14.2 8-bit OSC1 Timer Count Mode .................................................................................... 14-2

14.3 Count Clock ................................................................................................................. 14-3

14.4 Resetting 8-bit OSC1 Timer ......................................................................................... 14-4

14.5 Compare Data Settings ................................................................................................ 14-5

14.6 8-bit OSC1 Timer RUN/STOP Control ......................................................................... 14-6

14.7 8-bit OSC1 Timer Interrupts ......................................................................................... 14-7

14.8 Control Register Details ............................................................................................... 14-9

0x50c0: 8-bit OSC1 Timer Control Register (T8OSC1_CTL) .................................................. 14-10

0x50c1: 8-bit OSC1 Timer Counter Data Register (T8OSC1_CNT) ........................................ 14-11

0x50c2: 8-bit OSC1 Timer Compare Data Register (T8OSC1_CMP) ..................................... 14-12

0x50c3: 8-bit OSC1 Timer Interrupt Mask Register (T8OSC1_IMSK) ..................................... 14-13

0x50c4: 8-bit OSC1 Timer Interrupt Flag Register (T8OSC1_IFLG) ........................................ 14-14

14.9 Precautions ................................................................................................................. 14-15

15 Clock Timer (CT) .........................................................................................................15-1

15.1 Clock Timer Overview .................................................................................................. 15-1

15.2 Operation Clock ........................................................................................................... 15-2

15.3 Clock Timer Resetting .................................................................................................. 15-3

15.4 Clock Timer RUN/STOP Control .................................................................................. 15-4

15.5 Clock Timer Interrupts ................................................................................................. 15-5

15.6 Control Register Details ............................................................................................... 15-7

0x5000: Clock Timer Control Register (CT_CTL) ..................................................................... 15-8

0x5001: Clock Timer Counter Register (CT_CNT) ................................................................... 15-9

0x5002: Clock Timer Interrupt Mask Register (CT_IMSK) ...................................................... 15-10

0x5003: Clock Timer Interrupt Flag Register (CT_IFLG) ......................................................... 15-11

15.7 Precautions ................................................................................................................. 15-12

16 Stopwatch Timer (SWT) .............................................................................................16-1

16.1 Stopwatch Timer Overview .......................................................................................... 16-1

16.2 BCD Counters .............................................................................................................. 16-2

16.3 Operation Clock ........................................................................................................... 16-3

16.4 Stopwatch Timer Resetting ......................................................................................... 16-4

16.5 Stopwatch Timer RUN/STOP Control .......................................................................... 16-5

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16.6 Stopwatch Timer Interrupts ......................................................................................... 16-6

16.7 Control Register Details ............................................................................................... 16-8

0x5020: Stopwatch Timer Control Register (SWT_CTL) .......................................................... 16-9

0x5021: Stopwatch Timer BCD Counter Register (SWT_BCNT) ............................................16-10

0x5022: Stopwatch Timer Interrupt Mask Register (SWT_IMSK) ........................................... 16-11

0x5023: Stopwatch Timer Interrupt Flag Register (SWT_IFLG) .............................................. 16-12

16.8 Precautions ................................................................................................................. 16-13

17 Watchdog Timer (WDT) ..............................................................................................17-1

17.1 Watchdog Timer Overview ........................................................................................... 17-1

17.2 Operation Clock ........................................................................................................... 17-2

17.3 Watchdog Timer Control .............................................................................................. 17-3

17.3.1 NMI/Reset Mode Selection ............................................................................ 17-3

17.3.2 Watchdog Timer Run/Stop Control ............................................................... 17-3

17.3.3 Watchdog Timer Resetting ............................................................................ 17-3

17.3.4 Operation in Standby Mode .......................................................................... 17-3

17.4 Control Register Details ............................................................................................... 17-4

0x5040: Watchdog Timer Control Register (WDT_CTL) ........................................................... 17-5

0x5041: Watchdog Timer Status Register (WDT_ST) .............................................................. 17-6

17.5 Precautions .................................................................................................................. 17-7

18 UART ...........................................................................................................................18-1

18.1 UART Configuration ..................................................................................................... 18-1

18.2 UART Pin ...................................................................................................................... 18-2

18.3 Transfer Clock .............................................................................................................. 18-3

18.4 Transfer Data Settings .................................................................................................. 18-4

18.5 Data Transfer Control ................................................................................................... 18-5

18.6 Receive Errors .............................................................................................................. 18-8

18.7 UART Interrupts ........................................................................................................... 18-9

18.8 IrDA Interface .............................................................................................................. 18-11

18.9 Control Register Details .............................................................................................. 18-13

0x4100: UART Status Register (UART_ST) ............................................................................. 18-14

0x4101: UART Transmit Data Register (UART_TXD) ............................................................... 18-16

0x4102: UART Receive Data Register (UART_RXD) ............................................................... 18-17

0x4103: UART Mode Register (UART_MOD) .......................................................................... 18-18

0x4104: UART Control Register (UART_CTL) ......................................................................... 18-19

0x4105: UART Expansion Register (UART_EXP) .................................................................... 18-20

18.10 Precautions ............................................................................................................... 18-21

19 SPI ...............................................................................................................................19-1

19.1 SPI Configuration ......................................................................................................... 19-1

19.2 SPI Input/Output Pins .................................................................................................. 19-2

19.3 SPI Clock ..................................................................................................................... 19-3

19.4 Data Transfer Condition Settings ................................................................................. 19-4

19.5 Data Transfer Control ................................................................................................... 19-5

19.6 SPI Interrupts ............................................................................................................... 19-8

19.7 Control Register Details .............................................................................................. 19-10

0x4320: SPI Status Register (SPI_ST) ..................................................................................... 19-11

0x4322: SPI Transmit Data Register (SPI_TXD) ...................................................................... 19-12

0x4324: SPI Receive Data Register (SPI_RXD) ....................................................................... 19-13

0x4326: SPI Control Register (SPI_CTL) ................................................................................. 19-14

19.8 Precautions ................................................................................................................. 19-16

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20 I2C ................................................................................................................................20-1

20.1 I2C Configuration .......................................................................................................... 20-1

20.2 I2C Input/Output Pins ................................................................................................... 20-2

20.3 I

C Clock ...................................................................................................................... 20-3

20.4 Settings Before Data Transfer ...................................................................................... 20-4

20.5 Data Transfer Control ................................................................................................... 20-5

20.6 I2C Interrupts ............................................................................................................... 20-11

20.7 Control Register Details .............................................................................................. 20-13

0x4340: I2C Enable Register (I2C_EN) .................................................................................... 20-14

0x4342: I2C Control Register (I2C_CTL) .................................................................................. 20-15

0x4344: I2C Data Register (I2C_DAT) ...................................................................................... 20-17

0x4346: I

C Interrupt Control Register (I2C_ICTL) .................................................................. 20-19

21 Remote Controller (REMC) .........................................................................................21-1

21.1 REMC Configuration .................................................................................................... 21-1

21.2 REMC Input/output Pin ................................................................................................ 21-2

21.3 Carrier Generation ........................................................................................................ 21-3

21.4 Data Length Counter Clock Settings ........................................................................... 21-4

21.5 Data Transfer Control ................................................................................................... 21-5

21.6 REMC Interrupts .......................................................................................................... 21-8

21.7 Control Register Details .............................................................................................. 21-10

0x5340: REMC Configuration Register (REMC_CFG) ............................................................. 21-11

0x5341: REMC Prescaler Clock Select Register (REMC_PSC) ..............................................21-12

0x5342: REMC H Carrier Length Setup Register (REMC_CARH) ........................................... 21-13

0x5343: REMC L Carrier Length Setup Register (REMC_CARL) ............................................ 21-14

0x5344: REMC Status Register (REMC_ST) ........................................................................... 21-15

0x5345: REMC Length Counter Register (REMC_LCNT) ........................................................ 21-16

0x5346: REMC Interrupt Mask Register (REMC_IMSK) .......................................................... 21-17

0x5347: REMC Interrupt Flag Register (REMC_IFLG) ............................................................. 21-18

21.8 Precautions ................................................................................................................. 21-19

22 On-chip Debugger (DBG) ...........................................................................................22-1

22.1 Resource Requirements and Debugging Tool ............................................................. 22-1

22.2 Debug Break Operation Status .................................................................................... 22-2

22.3 Control Register Details ............................................................................................... 22-3

0x5322: OSC1 Peripheral Control Register (MISC_OSC1) ...................................................... 22-4

0xffff90: Debug RAM Base Register (DBRAM) ......................................................................... 22-5

23 Basic External Connection Diagram .........................................................................23-1

24 Electrical Characteristics ...........................................................................................24-1

24.1 Absolute Maximum Ratings ......................................................................................... 24-1

24.2 Recommended Operating Conditions ......................................................................... 24-1

24.3 DC Characteristics ....................................................................................................... 24-2

24.4 Consumption Current ................................................................................................... 24-3

24.5 AC Characteristics ....................................................................................................... 24-4

24.5.1 SPI AC Characteristics .................................................................................. 24-4

24.5.2 I

C AC Characteristics ................................................................................... 24-4

24.5.3 External Clock Input AC Characteristics ....................................................... 24-5

24.5.4 System AC Characteristics ............................................................................ 24-5

24.6 Oscillation Characteristics ........................................................................................... 24-6

25 Package ......................................................................................................................25-1

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Appendix A I/O Register List ......................................................................................... AP-1

0x4020 Prescaler .................................................................................. AP-4

0x4100–0x4105 UART (with IrDA) ...................................................................... AP-5

0x4200–0x4206 8-bit Timer (with Fine Mode) .................................................... AP-6

0x4220–0x4266 16-bit Timer ............................................................................. AP-7

0x4300–0x4314 Interrupt Controller .................................................................. AP-9

0x4320–0x4326 SPI .......................................................................................... AP-11

0x4340–0x4346 I

C ........................................................................................... AP-12

0x5000–0x5003 Clock Timer ............................................................................ AP-13

0x5020–0x5023 Stopwatch Timer .................................................................... AP-14

0x5040–0x5041 Watchdog Timer ..................................................................... AP-15

0x5060–0x5065 Oscillator ................................................................................. AP-16

0x5080–0x5081 Clock Generator ..................................................................... AP-17

0x50c0–0x50c4 8-bit OSC1 Timer .................................................................... AP-18

0x5200–0x52a3 P Port & Port MUX .................................................................. AP-19

0x5300–0x530c PWM & Capture Timer ............................................................ AP-21

0x5320–0x5322 MISC Registers ....................................................................... AP-22

0x5340–0x5347 Remote Controller .................................................................. AP-23

0xffff80–0xffff90 S1C17 Core I/O ...................................................................... AP-24

Appendix B Power Saving ............................................................................................ AP-25

B.1 Clock Control Power Saving ........................................................................................ AP-25

Appendix C Mounting Precautions ............................................................................... AP-28

Appendix D Initialization Routine ................................................................................. AP-31

Appendix E S1C17001 Mask ROM Code Development .............................................. AP-33

Appendix F Revision History ......................................................................................... AP-34

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1 OVERVIEW

1 Overview

The S1C7001 is a 16-bit MCU featuring high-speed low-power operations, compact dimensions, wide address space, and on-chip ICE. In addition to the S1C17 CPU core, it incorporates 32 Kbytes of ROM, 2 Kbytes of RAM, a serial interface supporting various sensors such as UART, SPI, and I 8-bit timer, 16-bit timer, PWM & capture timer, clock timer, stopwatch timer, watchdog timer, and 28 general purpose input/output ports. It allows 8.2 MHz high-speed operation at an operating voltage of just 1.8 V, and executes single commands using a single clock with 16-bit RISC processing.

1.1 Features

The main features of the S1C17001 are listed below.

● 71C1S eroc UPC CSIR tib-61 lanigiro nospE • UPC

●Main (OSC3) oscillator circuit • Crystal oscillator circuit, ceramic oscillator circuit, or external

clock input 8.2 MHz (max)

●Sub (OSC1) oscillator circuit • Crystal oscillator circuit or external clock input 32.768 kHz (typ)

● setybK 23 • MOR lanretnI

● setybK 2 • MAR lanretnI

C high-bit-rate and IrDA1.0 compatibility,

● lareneg tib-82 .xaM • trop tuptuo/tupnI purpose input/output (shared with periph- eral circuit input/output pins)

● .hc1 )evals/retsam( IPS • ecafretni laireS

I •

C (master) 1ch.

● .hc1 )F8T( remit tib-8 • remiT

● teseR • tpurretnI

IMN •

● VL( egatlov eroC • egatlov ylppus rewoP

●Operating temperature • -40°C to 85°C

●Current consumption (typ.) • 0.5 μA in SLEEP mode

5.2 • μA in HALT mode (32 kHz)

01 • μA when operating (32 kHz)

0081 μA when operating (8 MHz)

DD) 1.65 V to 2.7 V

VH( egatlov O/I •

DD) 1.65 V to 3.6 V

.hc1 )elbitapmoc 0.1ADrI( TRAU •

.hc1 )CMER( rellortnoc etomeR •

.hc3 )61T( remit tib-61 • .hc1 )E61T( remit erutpac &MWP • .hc1 )TC( remit kcolC • .hc1 )TWS( remit hctawpotS • .hc1 )TDW( remit godhctaW • .hc1 )1CSO8T( remit 1CSO tib-8 •

)slevel 8( 41x tpurretni erawdraH •

●Configuration as shipped • WCSP-48pin package

●Mask ROM code development Flash memory • S1C17704 (refer to Appendix E for details)

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1 OVERVIEW

1-2 Block Diagram

#TEST0–5

EXCL0–2

(P16, P07, P06)

SIN, SOUT, SCLK

(P23–25)

SDI, SDO, SPICLK

(P20–22)

(P14–15)

CPU Core S1C17

32 bits

1 cycle

Internal RAM

(2K bytes)

Internal ROM

(32K bytes)

Test circuit

I/O 1 (0x4000–)

Interrupt controller

Prescaler Clock timer

8-bit timer

16-bit timer

UART

SPI

CSDA, SCL

16 bits

1–5 cycles

8/16 bits

1 cycle

8/16 bits

3 cycles

Interrupt system

Reset circuit

I/O 2 (0x5000–)

MISC register

Clock generator

8-bit OSC1 timer

Stopwatch timer

Watchdog timer

PWM & capture

Remote controller

Oscillator/

timer

I/O port/ I/O MUX

DCLK, DST2, DSIO(P31–33)

#RESET

OSC1–2, OSC3–4 FOUT1(P13), FOUT3(P30)

EXCL3(P27), TOUT(P26)

REMI(P04), REMO(P05)

P00–07, P10–17, P20–27, P30–33

Figure 1.2.1: Block diagram

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S1C17001 TECHNICAL MANUAL

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1.3 Pins

1.3.1 Pinout Diagram

1 OVERVIEW

1 Corner A1 Corner

Top View

Index

Bottom View

76543211234567

Top View

234567

P05

REMO

P06

EXCL2

REMI

P03

HVDDP02

P12

P11

#RESET

#TEST3

VSSP04

#TEST2

P07

EXCL1

P15

SCL

LVDD LVDD

DSIO

P33

TEST0 P17

#TEST1 P21

S1C17001 TECHNICAL MANUAL

P16

EXCL0

VSS

DST2

P32

#SPISS

SDO

P14

SDA

DCLK

P31

P20

SDI

HVDD

Figure 1.3.1.1: Pinout diagram (WCSP-48pin)

P01

P00

P22

SPICLK

P23

SIN

P24

SOUT

EPSON

P10

P13

FOUT1

P25

SCLK

VSS

OSC4

P27

EXCL3

VSS

#TEST4

OSC3

P26

TOUT

P30

FOUT3

OSC1

OSC2

#TEST5

Page 13

1 OVERVIEW

1.3.2 Pin Descriptions

Table 1.3.2.1: Pin descriptions

No. Name I/O Default status Function

1 VSS – – Power supply pin (GND) 2 #TEST1 I I (Pull-Up) Test pin (fixed at High during normal operations) 3 #TEST2 I I (Pull-Up) Test pin (fixed at High during normal operations) 4 #TEST3 I I (Pull-Up) Test pin (fixed at High during normal operations) 5 #TEST4 I I (Pull-Up) Test pin (fixed at High during normal operations) 6 #TEST5 I I (Pull-Up) Test pin (fixed at High during normal operations) 7 OSC3 I I OSC3 oscillator input pin (permits external clock input) 8 OSC4 O O OSC3 oscillator output pin

9 OSC1 I I OSC1 oscillator input pin (permits external clock input) 10 OSC2 O O OSC1 oscillator output pin 11 HV

DD – – Power supply pin (HVDD+)

12 V

SS – – Power supply pin (GND)

13 TEST0 I I (Pull-Down) Test pin (fixed at Low during normal operations) 14 #RESET I I (Pull-Up) Initial set input pin 15 DSIO/P33 I/O I (Pull-Up) On-chip debugger data input/output pin*/ input/output port pin 16 DST2/P32 I/O O(L) On-chip debugger status output pin* / input/output port pin 17 DCLK/P31 I/O O(H) On-chip debugger clock output pin* / input/output port pin 18 P30/FOUT3 I/O I (Pull-Up) Input/output port pin*/ OSC3 division clock output pin 19 P27/EXCL3 I/O I (Pull-Up) Input/output port pin*/ T16E external clock input pin 20 P26/TOUT I/O I (Pull-Up) Input/output port pin*/ T16E PWM signal output pin 21 P25/SCLK I/O I (Pull-Up) Input/output port pin*/ UART clock input pin 22 P24/SOUT I/O I (Pull-Up) Input/output port pin*/ UART data output pin 23 P23/SIN I/O I (Pull-Up) Input/output port pin*/ UART data input pin 24 P22/SPICLK I/O I (Pull-Up) Input/output port pin*/ SPI clock input/output pin 25 P21/SDO I/O I (Pull-Up) Input/output port pin*/ SPI data output pin 26 P20/SDI I/O I (Pull-Up) Input/output port pin*/ SPI data input pin 27 P17/#SPISS I/O I (Pull-Up) Input/output port pin (with interrupt)*/ SPI slave select input pin 28 P16/EXCL0 I/O I (Pull-Up) Input/output port pin (with interrupt)*/ T16 Ch.0 external clock input pin 29 P15/SCL I/O I (Pull-Up) Input/output port pin (with interrupt)*/ I 30 P14/SDA I/O I (Pull-Up) Input/output port pin (with interrupt)*/ I 31 P13/FOUT1 I/O I (Pull-Up) Input/output port pin (with interrupt)*/ OSC1 clock output pin 32 P12 I/O I (Pull-Up) Input/output port pin (with interrupt) 33 P11 I/O I (Pull-Up) Input/output port pin (with interrupt) 34 P10 I/O I (Pull-Up) Input/output port pin (with interrupt) 35 P07/EXCL1 I/O I (Pull-Up) Input/output port pin (with interrupt)*/ T16 Ch.1 external clock input pin 36 P06/EXCL2 I/O I (Pull-Up) Input/output port pin (with interrupt)*/ T16 Ch.2 external clock input pin 37 P05/REMO I/O I (Pull-Up) Input/output port pin (with interrupt)*/ Remote output pin 38 P04/REMI I/O I (Pull-Up) Input/output port pin (with interrupt)*/ Remote input pin 39 P03 I/O I (Pull-Up) Input/output port pin (with interrupt) 40 HV

DD – – Power supply pin (HVDD+)

41 V

SS – – Power supply pin (GND)

42 P02 I/O I (Pull-Up) Input/output port pin (with interrupt) 43 P01 I/O I (Pull-Up) Input/output port pin (with interrupt) 44 P00 I/O I (Pull-Up) Input/output port pin (with interrupt) 45 LV

DD – – Power supply pin (LVDD+)

46 V

SS – – Power supply pin (GND)

47 LV

DD – – Power supply pin (LVDD+)

48 V

SS – – Power supply pin (GND)

Note: Pins appearing in bold and functions indicated by “*” are default settings.

2C clock output pin 2C data input/output pin

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2 CPU

The S1C17001 uses an S1C17 core as the core processor. The S1C17 core is an original Seiko Epson 16-bit RISC processor. It features low power consumption, high-speed operation, wide address space, main command single-clock execution, and gate-saving design. It is ideal for use in controllers or sequencers, in which 8-bit CPUs are widely used. For detailed information on the S1C17 core, refer to the S1C17 Family S1C17 Core Manual.

2.1 S1C17 Core Features

Processor type

• Seiko Epson original 16-bit RISC processor

• 0.35 μm to 0.15 μm low-power CMOS process technology

Command set

• Code length Fixed 16-bit length

• Number of commands 111 basic commands (184 in total)

• Execution cycle Main commands executed in one cycle

• Immediate expansion commands Expansion of immediate to 24 bits

• Compact, high-speed command set optimized for development with C

• 24-bit general purpose register x 8

• 24-bit special register x 2

• 8-bit special register x 1

Memory space, buses

• Up to 16 Mbytes of memory space (24-bit address)

• Harvard architecture with separate command bus (16-bit) and data bus (32-bit)

Interrupt

• Supports reset, NMI, and 32 different types of external interrupt

• Irregular address interrupt

• Debug interrupt

• Reading vector from vector table and direct branching to interrupt processing routines

• Permits software interrupts using vector numbers (all vector numbers can be specified)

Power saving

• HALT (halt command)

• SLEEP (slp command)

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2 CPU

2.2 CPU Registers

The S1C17 core contains eight general purpose registers and three special registers.

Special registers

Bit 23 Bit 0

PC SP

PSR

765IE4C3V2Z1N0

IL[2:0]

Figure 2.2.1: Registers

General purpose registers

Bit 23 Bit 0

7 6 5 4 3 2 1 0

R7 R6 R5 R4 R3 R2 R1 R0

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2.3 Command Set

The S1C17 core command codes are all 16-bit and fixed-length. Major commands are executed in a single cycle using pipeline processing. For more information on the various commands, refer to the S1C17 Family S1C17 Core Manual.

Table 2.3.1: S1C17 core command list

Type Mnemonic Function

Data transfer

ld.b

ld.ub

ld.a

%rd,%rs

%rd,[%rb]

%rd,[%rb]+

%rd,[%rb]-

%rd,-[%rb]

%rd,[%sp+imm7]

%rd,[imm7]

[%rb],%rs

[%rb]+,%rs

[%rb]-,%rs

-[%rb],%rs

[%sp+imm7],%rs

[imm7],%rs

%rd,%rs

%rd,[%rb]

%rd,[%rb]+

%rd,[%rb]-

%rd,-[%rb]

%rd,[%sp+imm7]

%rd,[imm7]

%rd,%rs

%rd,sign7

%rd,[%rb]

%rd,[%rb]+

%rd,[%rb]-

%rd,-[%rb]

%rd,[%sp+imm7]

%rd,[imm7]

[%rb],%rs

[%rb]+,%rs

[%rb]-,%rs

-[%rb],%rs

[%sp+imm7],%rs

[imm7],%rs

%rd,%rs

%rd,imm7

%rd,[%rb]

%rd,[%rb]+

%rd,[%rb]-

%rd,-[%rb]

%rd,[%sp+imm7]

%rd,[imm7]

[%rb],%rs

[%rb]+,%rs

[%rb]-,%rs

-[%rb],%rs

[%sp+imm7],%rs

[imm7],%rs

%rd,%sp

%rd,%pc

%rd,[%sp]

%rd,[%sp]+

%rd,[%sp]-

%rd,-[%sp]

General purpose register (byte) ➔ General purpose register (sign extension) Memory (byte) ➔ General purpose register (sign extension) Memory address post-increment/post-decrement A pre-decrement function can be used

Stack (byte) ➔ General purpose register (sign extension) Memory (byte) ➔ General purpose register (sign extension) General purpose register (byte) ➔ Memory Memory address post-increment/post-decrement A pre-decrement function can be used

General purpose register (byte) ➔ Stack General purpose register (byte) ➔ Memory General purpose register (byte) ➔ General purpose register (zero extension) Memory (byte) ➔ General purpose register (zero extension) Memory address post-increment/post-decrement A pre-decrement function can be used

Stack (byte) ➔ General purpose register (zero extension) Memory (byte) ➔ General purpose register (zero extension) General purpose register (16 bits) ➔ General purpose register Immediate ➔ General purpose register (sign extension) Memory (16 bits) ➔ General purpose register Memory address post-increment/post-decrement A pre-decrement function can be used

Stack (16 bits) ➔ General purpose register Memory (16 bits) ➔ General purpose register General purpose register (16 bits) ➔ Memory Memory address post-increment/post-decrement A pre-decrement function can be used

General purpose register (16 bits) ➔ Stack General purpose register (16 bits) ➔ Memory General purpose register (24 bits) Immediate ➔ General purpose register (zero extension) Memory (32 bits) ➔ General purpose register (*1) Memory address post-increment/post-decrement A pre-decrement function can be used

Stack (32 bits) ➔ General purpose register (*1) Memory (32 bits) ➔ General purpose register (*1) General purpose register (32 bits, zero extension) ➔ Memory (*1) Memory address post-increment/post-decrement A pre-decrement function can be used

General purpose register (32 bits, zero extension) ➔ Stack (*1) General purpose register (32 bits, zero extension) ➔ Memory (*1) SP ➔ General purpose register PC ➔ General purpose register Stack (32 bits) ➔ General purpose register (*1) Stack pointer post-increment/post-decrement A pre-decrement function can be used

➔ General purpose register

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Type Mnemonic Function

Data transfer

Integer arithmetic

Logic operations

ld.a [%sp],%rs

add

add/c

add/nc

add

add.a

add.a/c

add.a/nc

add.a %sp,%rs

adc

adc/c

adc/nc

adc

sub

sub/c

sub/nc

sub

sub.a

sub.a/c

sub.a/nc

sub.a %sp,%rs

sbc sbc/c

sbc/nc

sbc

cmp

cmp/c

cmp/nc

cmp

cmp.a

cmp.a/c

cmp.a/nc

cmp.a

cmc

cmc/c

cmc/nc

cmc

and

and/c

and/nc

and

or/c

or/nc

xor

xor/c

xor/nc

xor

not

not/c

not/nc

not

[%sp]+,%rs

[%sp]-,%rs

-[%sp],%rs

%sp,%rs

%sp,imm7

%rd,%rs

%rd,imm7

%rd,%rs

%rd,imm7

%sp,imm7 %rd,%rs

%rd,imm7

%rd,%rs

%rd,imm7

%rd,%rs

%rd,imm7

%sp,imm7 %rd,%rs

%rd,imm7

%rd,%rs

%rd,sign7

%rd,%rs

%rd,imm7

%rd,%rs

%rd,sign7

%rd,%rs

%rd,sign7

%rd,%rs

%rd,sign7

%rd,%rs

%rd,sign7

%rd,%rs

,sign7

%rd

General purpose register (32 bits, zero extension) ➔ Stack (*1) Stack pointer post-increment/post-decrement A pre-decrement function can be used

General purpose register (24 bits) ➔ SP Immediate ➔ SP Adds 16 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Adds general purpose register and immediate 16 bits Adds 24 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Adds SP and general purpose register 24 bits Adds general purpose register and immediate 24 bits Adds SP and immediate 24 bits Adds 16 bits with carry between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Adds general purpose register and immediate 16 bits with carry Subtracts 16 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Subtracts general purpose register and immediate 16 bits Subtracts 24 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Subtracts SP and general purpose register 24 bits Subtracts general purpose register and immediate 24 bits Subtracts SP and immediate 24 bits Subtracts 16 bits with carry between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Subtracts general purpose register and immediate 16 bits with carry Compares 16 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Compares general purpose registers and immediate 16 bits Compares 24 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Compares general purpose registers and immediate 24 bits Compares 16 bits with carry between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Compares general purpose register and immediate 16 bits with carry AND operation between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) AND operation for general purpose register and immediate OR operation between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) OR operation for general purpose register and immediate EXCLUSIVE OR between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) EXCLUSIVE OR for general purpose register and immediate NOT operation between general purpose registers (1 complement) Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) NOT operation for general purpose register and immediate (1 complement)

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2 CPU

Type Mnemonic Function

Shift & swap

Immediate extension Conversion

Branch

System control

swap

ext

cv.ab

cv.as

cv.al

cv.la

cv.ls

jpr

jpr.d

jpa

ipa.d

jrgt

jrgt.d

jrge

jrge.d

jrlt

jrlt.d

jrle

jrle.d

jrugt

jrugt.d

jruge

jruge.d

jrult

jrult.d

jrule

jrule.d

jreq

jreq.d

jrne

jrne.d

call

call.d

calla

calla.d ret

ret.d

int

intl

reti

reti.d

brk

retd

nop

halt

slp

%rd,%rs

%rd,imm7

%rd,%rs

%rd,imm7

%rd,%rs

%rd,imm7

%rd,%rs

imm13

%rd,%rs

sign10

%rb

imm7

%rb

sign7

sign10

%rb

imm7

%rb

imm5

imm5,imm3

Right logic shift (shift bit number specified by register) Right logic shift (shift bit number specified by immediate) Right operation shift (shift bit number specified by register) Right operation shift (shift bit number specified by immediate) Left logic shift (shift bit number specified by register) Left logic shift (shift bit number specified by immediate) Byte swap at 16-bit boundary Extend operand for next command Convert 8-bit coded data to 24 bits Convert 16-bit coded data to 24 bits Convert 32-bit data to 24 bits Convert 24-bit data to 32 bits Convert 16-bit data to 32 bits PC-relative jump Allows delayed branching Absolute jump Allows delayed branching Conditional PC-relative jump Branch conditions: !Z & !(N ^ V) Allows delayed branching Conditional PC-relative jump Branch conditions: !(N ^ V) Allows delayed branching Conditional PC-relative jump Branch conditions: N ^ V Allows delayed branching Conditional PC-relative jump Branch conditions: Z | N ^ V Allows delayed branching Conditional PC-relative jump Branch conditions: !Z & !C Allows delayed branching Conditional PC-relative jump Branch conditions: !C Allows delayed branching Conditional PC-relative jump Branch conditions: C Allows delayed branching Conditional PC-relative jump Branch conditions: Z | C Allows delayed branching Conditional PC-relative jump Branch conditions: Z Allows delayed branching Conditional PC-relative jump Branch conditions: !Z Allows delayed branching PC-relative subroutine call Allows delayed branching Absolute subroutine call Allows delayed branching Return from subroutine Allows delayed branching Software interrupt Software interrupt with interrupt level specification Return from interrupt Allows delayed branching Debug interrupt Return from debug processing No operation HALT SLEEP Permits interrupt Prevents interrupt

*1: Command ld.a accesses 32-bit memory. When data is transferred from register to memory, 32 bits of data with

the first 8 bits set to 0 are written to memory. When data is read from memory, the first 8 bits are ignored.

*2: Coprocessor commands are reserved, since the S1C17001 does not include a coprocessor.

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2 CPU

The codes used in this table are explained below.

Table 2.3.2: Code meanings

Code Description

%rs

%rd

%rb

[

]

%rb

[

%rb

[

%rb

]

%sp [%sp],[%sp+

imm7

] [%sp]+ [%sp]-

-[%sp]

imm3,imm5,imm7,imm13

sign7,sign10

General purpose source register General purpose destination register Memory specified indirectly by general purpose register Memory specified indirectly by general purpose register (with address postincrement) Memory specified indirectly by general purpose register (with address postdecrement) Memory specified indirectly by general purpose register (with address predecrement) Stack pointer Stack Stack (with address post-increment) Stack (with address post-decrement) Stack (with address pre-decrement) Immediate without code (number indicates bit length) Immediate with code (number indicates bit length)

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2 CPU

2.4 Vector Table

The vector table contains the vectors (processing routine start addresses) for interrupt processing routines. When an interrupt occurs, the S1C17 core reads the vector corresponding to the interrupt and executes that processing routine. The boot address for starting program execution must be written at the top of the vector table after resetting. The S1C17001 vector table starts from address 0x8000. The vector table base address can be read from the TTBR (vector table base register) at address 0xffff80. Table 2.4.1 shows the S1C17001 vector table.

Table 2.4.1: Vector table

Vector No./ Soft-

ware interrupt No.

0 (0x00) 0x8000 Reset • Low input to #RESET pin

1 (0x01) 0x8004 Irregular address interrupt Memory access command 2

– (0xfffc00) Debug interrupt brk command etc. 3 2 (0x02) 0x8008 NMI Watchdog timer overflow 3 (0x03) 0x800c reserved – – 4 (0x04) 0x8010 P0 port interrupt P00 to P07 port input High 5 (0x05) 0x8014 P1 port interrupt P10 to P17 port input 6 (0x06) 0x8018 Stopwatch timer interrupt • Timer 100 Hz signal

7 (0x07) 0x801c Clock timer interrupt • Timer 32 Hz signal

8 (0x08) 0x8020 8-bit OSC1 timer interrupt Compare match 9 (0x09) 0x8024 10 (0x0a) 0x8028 11 (0x0b) 0x802c PWM & capture timer interrupt • Compare A

12 (0x0c) 0x8030 8-bit timer interrupt Timer underflow 13 (0x0d) 0x8034 16-bit timer Ch.0 interrupt Timer underflow 14 (0x0e) 0x8038 16-bit timer Ch.1 interrupt Timer underflow

15 (0x0f) 0x803c 16-bit timer Ch.2 interrupt Timer underflow

16 (0x10) 0x8040 UART interrupt • Transmit buffer empty

17 (0x11) 0x8044 Remote controller interrupt • Data length counter underflow

18 (0x12) 0x8048 SPI interrupt • Transmit buffer empty

19 (0x13) 0x804c I

20 (0x14) 0x8050

: : reserved –

31 (0x1f) 0x807c Low

*1: When same interrupt level is set *2: Watchdog timer interrupt selects reset or NMI using software.

Vector address Hardware interrupt name Hardware interrupt factor Priority

• Watchdog timer overflow

• Timer 10 Hz signal

• Timer 1 Hz signal

• Timer 8 Hz signal

• Timer 2 Hz signal

• Timer 1 Hz signal

reserved –

• Compare B

• Receive buffer full

• Receive error

• Input rising edge detection

• Input falling edge detection

C interrupt • Transmit buffer empty

• Receive buffer full

0xffff80: Vector Table Base Register (TTBR)

0xffff80

Vector Table Base Register (TTBR)

S1C17001 TECHNICAL MANUAL EPSON

D31–24 – Unused (fixed at 0) 0x0 0x0 R

(32 bits)

D23–0 TTBR[23:0] Vector table base address 0x8000 0x8000R

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2 CPU

2.5 Processor Information

The S1C17001 contains a processor ID register (0xffff84) to allow specification of the CPU core type by the application software.

0xffff84: Processor ID Register (IDIR)

Processor ID Register (IDIR)

0xffff84

This is the read-only register containing the ID code indicating the processor type. The S1C17 core ID code is 0x10.

D7–0 IDIR[7:0] Processor ID

(8 bits)

0x10: S1C17 Core

0x10 0x10 R

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3 MEMORY MAP AND BUS CONTROL

3 Memory Map and Bus Control

Figure 3.1 shows the S1C17001 memory map.

Peripheral functions

0xff ffff

0xff fc00 0xff fbff

0x01 0000 0x00 ffff

0x00 8000 0x00 7fff

0x00 6000 0x00 5fff

0x00 5000 0x00 4fff

0x00 4400 0x00 43ff

0x00 4000 0x00 3fff

0x00 0800 0x00 07ff 0x00 07c0

0x00 0000

Core I/O reserved area

(1 Kbyte, 1 cycle)

reserved

Internal ROM area

(32 Kbytes, 1-5 cycles)

(Device size: 16 bits)

Vector table

reserved

Internal peripheral circuit area 2

(4 Kbytes, 3 cycles)

reserved

Internal peripheral circuit area 1

(1 Kbyte, 1 cycle)

reserved

Debug RAM area (64 bytes)

Internal RAM area

(2 Kbytes, 1 cycle)

(Device size: 32 bits)

Figure 3.1: S1C17001 memory map

0x5360~0x5fff 0x5340~0x535f 0x5320~0x533f 0x5300~0x531f 0x52c0~0x52ff 0x52a0~0x52bf 0x5280~0x529f 0x5200~0x527f 0x50e0~0x51ff 0x50c0~0x50df 0x50a0~0x50bf 0x5080~0x509f 0x5060~0x507f 0x5040~0x505f 0x5020~0x503f 0x5000~0x501f

0x4360~0x43ff 0x4340~0x435f 0x4320~0x433f 0x4300~0x431f 0x4280~0x42ff 0x4260~0x427f 0x4240~0x425f 0x4220~0x423f 0x4200~0x421f 0x4120~0x41ff 0x4100~0x411f 0x4040~0x40ff 0x4020~0x403f 0x4000~0x401f

reserved Remote controller MISC register PWM & capture timer reserved Port MUX reserved P port reserved 8-bit OSC1 timer reserved Clock generator Oscillator circuit Watchdog timer Stopwatch timer Clock timer

reserved

C SPI Interrupt controller reserved 16-bit timer Ch.2 16-bit timer Ch.1 16-bit timer Ch.0 8-bit timer reserved UART reserved Prescaler reserved

(Device size)

(8 bits) (8 bits) (16 bits)

(8 bits) _

(8 bits) (8 bits) (8 bits) (8 bits) (8 bits)

(16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (8 bits) (8 bits) (8 bits) (8 bits) (8 bits)

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3.1 Bus Cycle

The CPU operates using CCLK as a datum. For more information on CCLK, refer to “8.2 CPU Core Clock (CCLK) Control.” The time from one CCLK rise-up to the next forms 1 CCLK, defined as one bus cycle. As shown in Figure 3.1, the number of cycles required for a single bus access depends on the peripheral circuits and memory. The number of bus accesses also varies and depends on the CPU command (access size) and device size.

Table 3.1.1: Bus access numbers

Device size CPU access size Bus access number

8 bits 8 bits 1

16 bits 2 32 bits * 4

16 bits 8 bits 1

16 bits 1 32 bits * 2

32 bits 8 bits 1

16 bits 1 32 bits * 1

∗ First 8 bits of data for 32-bit data access The first 8 bits of 32-bit data are written to memory as 0. The first 8 bits are ignored when read from memory. In-

terrupt processing stack operation involves reading and writing 32 bits with the PSR value in the first 8 bits and the return address in the last 24 bits.

Bus cycle calculation example

Number of bus cycles when accessing internal peripheral circuit area 2 (8-bit device, 3 cycles) from CPU using

16-bit read/write command:

3 cycles x 2 bus accesses = 6 CCLK cycles

3.1.1 Access Size Restrictions

When programming, note that the modules listed below are subject to access size restrictions.

SPI, I2C

The SPI and I2C registers can be accessed only with 16-bit read/write commands.

All other modules can be accessed using 8-bit, 16-bit, and 32-bit commands. Where possible, we recommend matching access to device size. Reading from non-essential registers may alter the state of peripheral circuits and cause problems.

3.1.2 Command Execution Cycle Restrictions

In the event of any of the conditions listed below, command fetch and data access will not be performed simultaneously, and the command fetch cycle will be extended by the amount of access cycles for the areas in which data exists.

• If a command is executed for an internal ROM area while accessing internal ROM and internal peripheral circuit area 2 (0x5000 onward) data

• If a command is executed for an internal RAM area while accessing internal RAM area data

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3 MEMORY MAP AND BUS CONTROL

3.2 Internal ROM Area

3.2.1 Internal ROM

The 32 Kbyte area from address 0x8000 to 0xffff is ROM. This area can be used for writing application programs and data. Address 0x8000 is defined as the vector table base address, and the vector table must be placed at the start of this area (refer to “2.4 Vector Table”). ROM reads take 1 to 5 cycles.

3.2.2 ROM Read Access Cycle Settings

Set the IROM area read access cycles using FLCYC[2:0] (D[2:0]/MISC_FL register) to retain compatibility with S1C17701. Normally, set FLCYC[2:0] to 0x4.

0x5320: ROM Control Register (MISC_FL)

ROM Control Register (MISC_FL)

0x5320

D7–3 – reserved – – – 0 when being read.

(8 bits)

D2–0 FLCYC[2:0] ROM read access cycle FLCYC[2:0] Read cycle 0x3 R/W

0x7–0x5

0x4 0x3 0x2 0x1 0x0

reserved

1 cycle 5 cycles 4 cycles 3 cycles 2 cycles

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3 MEMORY MAP AND BUS CONTROL

3.3 Internal RAM Area

3.3.1 Internal RAM

The 2 Kbyte area from address 0x0 to 0x7ff is RAM. This RAM can be accessed in one cycle. In addition to storing variables, it can also be used to copy command codes and execute them rapidly in RAM.

Note: The last 64 bytes of the internal RAM (0x7c0 to 0x7ff) are reserved for on-chip debugging. This

area should not be accessed by application programs when using debug functions (for example, during application development).

It can be used for applications in mass-produced products that do not require debugging.

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3 MEMORY MAP AND BUS CONTROL

3.4 Internal Peripheral Circuit Area

The 1 Kbyte area starting at address 0x4000 and the 4 Kbyte area from 0x5000 are assigned for use as internal peripheral circuit I/O and control registers.

3.4.1 Internal Peripheral Circuit Area 1 (0x4000 onward)

The internal peripheral circuit area 1 starting at address 0x4000 is assigned for use as the following internal peripheral function I/O memory and can be accessed in a single cycle.

• Prescaler (PSC, 8-bit device)

• UART (UART, 8-bit device)

• 8-bit timer (T8F, 16-bit device)

• 16-bit timer (T16, 16-bit device)

• Interrupt controller (ITC, 16-bit device)

• SPI (SPI, 16-bit device)

• I

C (I2C, 16-bit device)

3.4.2 Internal Peripheral Circuit Area 2 (0x5000 onward)

The internal peripheral circuit area 2 starting at address 0x5000 is assigned for use as the following internal peripheral function I/O memory, and can be accessed in three cycles.

• Clock timer (CT, 8-bit device)

• Stopwatch timer (SWT, 8-bit device)

• Watchdog timer (WDT, 8-bit device)

• Oscillator circuit (OSC, 8-bit device)

• Clock generator (CLG, 8-bit device)

• 8-bit OSC1 timer (T8OSC1, 8-bit device)

• Input/output port & port MUX (P, 8-bit device)

• PWM & capture timer (T16E, 16-bit device)

• MISC register (MISC, 8-bit device)

• Remote controller (REMC, 8-bit device)

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3 MEMORY MAP AND BUS CONTROL

3.4.3 I/O Map

The I/O map for the internal peripheral circuit area is shown below. For more information on control registers, refer to the I/O register list in the Appendix or the corresponding peripheral circuit explanations.

Note: Addresses indicated as “Reserved” or blank unused peripheral circuit areas should not be ac-

cessed by application programs.

Table 3.4.3.1: I/O map (internal peripheral circuit area 1)

Peripheral circuit

Prescaler (8-bit device)

UART (with IrDA) (8-bit device)

8-bit timer (with F mode) (16-bit device)

16-bit timer Ch.0 (16-bit device)

16-bit timer Ch.1 (16-bit device)

16-bit timer Ch.2 (16-bit device)

Interrupt controller (16-bit device)

SPI (16-bit device)

I (16-bit device)

EPSON S1C17001 TECHNICAL MANUAL

Address Register name Function

0x4020 PSC_CTL Prescaler Control Register Prescaler start/stop control 0x4021 to 0x403f – – Reserved 0x4100 UART_ST UART Status Register Transfer, buffer, and error status display 0x4101 UART_TXD UART Transmit Data Register Transmission data 0x4102 UART_RXD UART Receive Data Register Received data 0x4103 UART_MOD UART Mode Register Transfer data format setting 0x4104 UART_CTL UART Control Register Data transfer control 0x4105 UART_EXP UART Expansion Register IrDA mode setting 0x4106 to 0x411f – – Reserved 0x4200 T8F_CLK 8-bit Timer Input Clock Select Register Prescaler output clock selection 0x4202 T8F_TR 8-bit Timer Reload Data Register Reload data setting 0x4204 T8F_TC 8-bit Timer Counter Data Register Counter data 0x4206 T8F_CTL 8-bit Timer Control Register Timer mode setting and timer RUN/STOP 0x4208 to 0x421f – – Reserved 0x4220 T16_CLK0 16-bit Timer Ch.0 Input Clock Select Register Prescaler output clock selection 0x4222 T16_TR0 16-bit Timer Ch.0 Reload Data Register Reload data setting 0x4224 T16_TC0 16-bit Timer Ch.0 Counter Data Register Counter data 0x4226 T16_CTL0 16-bit Timer Ch.0 Control Register Timer mode setting and timer RUN/STOP 0x4228 to 0x423f – – Reserved 0x4240 T16_CLK1 16-bit Timer Ch.1 Input Clock Select Register Prescaler output clock selection 0x4242 T16_TR1 16-bit Timer Ch.1 Reload Data Register Reload data setting 0x4244 T16_TC1 16-bit Timer Ch.1 Counter Data Register Counter data 0x4246 T16_CTL1 16-bit Timer Ch.1 Control Register Timer mode setting and timer RUN/STOP 0x4248 to 0x425f – – Reserved 0x4260 T16_CLK2 16-bit Timer Ch.2 Input Clock Select Register Prescaler output clock selection 0x4262 T16_TR2 16-bit Timer Ch.2 Reload Data Register Reload data setting 0x4264 T16_TC2 16-bit Timer Ch.2 Counter Data Register Counter data 0x4266 T16_CTL2 16-bit Timer Ch.2 Control Register Timer mode setting and timer RUN/STOP 0x4268 to 0x427f – – Reserved 0x4300 ITC_IFLG Interrupt Flag Register Interrupt occurrence status display/reset 0x4302 ITC_EN Interrupt Enable Register Maskable interrupt permission/prohibition 0x4304 ITC_CTL ITC Control Register ITC operation permission/prohibition 0x4306 ITC_ELV0 External Interrupt Level Setup Register 0 P0/P1 port interrupt level and trigger mode

0x4308 ITC_ELV1 External Interrupt Level Setup Register 1 Stopwatch timer and clock timer interrupt

0x430a ITC_ELV2 External Interrupt Level Setup Register 2 8-bit OSC1 timer interrupt level and trigger

0x430c ITC_ELV3 External Interrupt Level Setup Register 3 PWM & capture timer interrupt level and

0x430e ITC_ILV0 Internal Interrupt Level Setup Register 0 8-bit timer and 16-bit timer Ch.0 interrupt

0x4310 ITC_ILV1 Internal Interrupt Level Setup Register 1 16-bit timer Ch.1 and 16-bit timer Ch.2

0x4312 ITC_ILV2 Internal Interrupt Level Setup Register 2 UART and remote controller interrupt level

0x4314 ITC_ILV3 Internal Interrupt Level Setup Register 3 SPI and I 0x4316 to 0x431f – – Reserved 0x4320 SPI_ST SPI Status Register Transfer and buffer status display 0x4322 SPI_TXD SPI Transmit Data Register Transmission data 0x4324 SPI_RXD SPI Receive Data Register Received data 0x4326 SPI_CTL SPI Control Register SPI mode and data transfer permission

0x4328 to 0x433f – – Reserved 0x4340 I2C_EN I2C Enable Register I2C module enable 0x4342 I2C_CTL I 0x4344 I2C_DAT I 0x4346 I2C_ICTL I 0x4348 to 0x435f – – Reserved

C Control Register I2C control and transfer status display

C Data Register Transfer data

C Interrupt Control Register I2C interrupt control

setting

level and trigger mode setting

mode setting

trigger mode setting

level setting

interrupt level setting

setting

C interrupt level setting

setting

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Peripheral circuit

Clock timer (8-bit device)

Stopwatch timer (8-bit device)

Watchdog timer (8-bit device)

Oscillator circuit (8-bit device)

Clock generator (8-bit device)

8-bit OSC1 timer (8-bit device)

P port & port MUX (8-bit device)

3 MEMORY MAP AND BUS CONTROL

Table 3.4.3.2: I/O map (internal peripheral circuit area 2)

Address Register name Function

0x5000 CT_CTL Clock Timer Control Register Timer reset and RUN/STOP control 0x5001 CT_CNT Clock Timer Counter Register Counter data 0x5002 CT_IMSK Clock Timer Interrupt Mask Register Interrupt mask setting 0x5003 CT_IFLG Clock Timer Interrupt Flag Register Interrupt occurrence status display/reset 0x5004 to 0x501f – – Reserved 0x5020 SWT_CTL Stopwatch Timer Control Register Timer reset and RUN/STOP control 0x5021 SWT_BCNT Stopwatch Timer BCD Counter Register BCD Counter data 0x5022 SWT_IMSK Stopwatch Timer Interrupt Mask Register Interrupt mask setting 0x5023 SWT_IFLG Stopwatch Timer Interrupt Flag Register Interrupt occurrence status display/reset 0x5024 to 0x503f – – Reserved 0x5040 WDT_CTL Watchdog Timer Control Register Timer reset and RUN/STOP control 0x5041 WDT_ST Watchdog Timer Status Register Timer mode setting and NMI status display 0x5042 to 0x505f – – Reserved 0x5060 OSC_SRC Clock Source Select Register Clock source selection 0x5061 OSC_CTL Oscillation Control Register Oscillation control 0x5062 OSC_NFEN Noise Filter Enable Register Noise filter ON/OFF 0x5063 – – Reserved 0x5064 OSC_FOUT FOUT Control Register Clock external output control 0x5065 OSC_T8OSC1 T8OSC1 Clock Control Register 8-bit OSC1 timer clock setting 0x5066 to 0x507f – – Reserved 0x5080 CLG_PCLK PCLK Control Register PCLK feed control 0x5081 CLG_CCLK CCLK Control Register CCLK division ratio setting 0x5082 to 0x509f – – Reserved 0x50c0 T8OSC1_CTL 8-bit OSC1 Timer Control Register Timer mode setting and timer RUN/STOP 0x50c1 T8OSC1_CNT 8-bit OSC1 Timer Counter Data Register Counter data 0x50c2 T8OSC1_CMP 8-bit OSC1 Timer Compare Data Register Compare data setting 0x50c3 T8OSC1_IMSK 8-bit OSC1 Timer Interrupt Mask Register Interrupt mask setting 0x50c4 T8OSC1_IFLG 8-bit OSC1 Timer Interrupt Flag Register Interrupt occurrence status display/reset 0x50c5 to 0x50df – – Reserved 0x5200 P0_IN P0 Port Input Data Register P0 port input data 0x5201 P0_OUT P0 Port Output Data Register P0 port output data 0x5202 P0_IO P0 Port I/O Direction Control Register P0 port input/output direction selection 0x5203 P0_PU P0 Port Pull-up Control Register P0 port pull-up control 0x5204 – – Reserved 0x5205 P0_IMSK P0 Port Interrupt Mask Register P0 port interrupt mask setting 0x5206 P0_EDGE P0 Port Interrupt Edge Select Register P0 port interrupt edge selection 0x5207 P0_IFLG P0 Port Interrupt Flag Register P0 port interrupt occurrence status display/

0x5208 P0_CHAT P0 Port Chattering Filter Control Register P0 port chattering filter control 0x5209 P0_KRST P0 Port Key-Entry Reset Configuration Regis-

ter 0x520a to 0x520f – – Reserved 0x5210 P1_IN P1 Port Input Data Register P1 port input data 0x5211 P1_OUT P1 Port Output Data Register P1 port output data 0x5212 P1_IO P1 Port I/O Direction Control Register P1 port input/output direction selection 0x5213 P1_PU P1 Port Pull-up Control Register P1 port pull-up control 0x5214 – – Reserved 0x5215 P1_IMSK P1 Port Interrupt Mask Register P1 port interrupt mask setting 0x5216 P1_EDGE P1 Port Interrupt Edge Select Register P1 port interrupt edge selection 0x5217 P1_IFLG P1 Port Interrupt Flag Register P1 port interrupt occurrence status display/

0x5218 to 0x521f – – Reserved 0x5220 P2_IN P2 Port Input Data Register P2 port input data 0x5221 P2_OUT P2 Port Output Data Register P2 port output data 0x5222 P2_IO P2 Port I/O Direction Control Register P2 port input/output direction selection 0x5223 P2_PU P2 Port Pull-up Control Register P2 port pull-up control 0x5224 to 0x522f – – Reserved 0x5230 P3_IN P3 Port Input Data Register P3 port input data 0x5231 P3_OUT P3 Port Output Data Register P3 port output data 0x5232 P3_IO P3 Port I/O Direction Control Register P3 port input/output direction selection 0x5233 P3_PU P3 Port Pull-up Control Register P3 port pull-up control 0x5234 to 0x527f – – Reserved 0x52a0 P0_PMUX P0 Port Function Select Register P0 port function selection 0x52a1 P1_PMUX P1 Port Function Select Register P1 port function selection 0x52a2 P2_PMUX P2 Port Function Select Register P2 port function selection 0x52a3 P3_PMUX P3 Port Function Select Register P3 port function selection 0x52a4 to 0x52bf – – Reserved

reset

P0 port key entry reset setting

reset

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3 MEMORY MAP AND BUS CONTROL

Peripheral circuit

PWM & capture timer (16-bit device)

MISC register (8-bit device)

Remote controller (8-bit device)

Address Register name Function

0x5300 T16E_CA PWM Timer Compare Data A Register Compare data A setting 0x5302 T16E_CB PWM Timer Compare Data B Register Compare data B setting 0x5304 T16E_TC PWM Timer Counter Data Register Counter data 0x5306 T16E_CTL PWM Timer Control Register Timer mode setting and timer RUN/STOP 0x5308 T16E_CLK PWM Timer Input Clock Select Register Prescaler output clock selection 0x530a T16E_IMSK PWM Timer Interrupt Mask Register Interrupt mask setting 0x530c T16E_IFLG PWM Timer Interrupt Flag Register Interrupt occurrence status display/reset 0x530e to 0x531f – – Reserved 0x5320 MISC_FL ROM Control Register ROM access condition setting 0x5321 – – Reserved 0x5322 MISC_OSC1 OSC1 Peripheral Control Register OSC1 operation peripheral function setting

for debugging 0x5323 to 0x533f – – Reserved 0x5340 REMC_CFG REMC Configuration Register Transfer selection and permission 0x5341 REMC_PSC REMC Prescaler Clock Select Register Prescaler output clock selection 0x5342 REMC_CARH REMC H Carrier Length Setup Register Carrier H section length setting 0x5343 REMC_CARL REMC L Carrier Length Setup Register Carrier L section length setting 0x5344 REMC_ST REMC Status Register Transfer bit 0x5345 REMC_LCNT REMC Length Counter Register Transfer data length setting 0x5346 REMC_IMSK REMC Interrupt Mask Register Interrupt mask setting 0x5347 REMC_IFLG REMC Interrupt Flag Register Interrupt occurrence status display/reset 0x5348 to 0x535f – – Reserved

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3 MEMORY MAP AND BUS CONTROL

3.5 Core I/O Reserved Area

The 1 Kbyte area from 0xfffc00 to 0xffffff is used as the CPU core I/O area, and the following I/O registers are assigned.

Table 3.5.1: I/O map (Core I/O reserved area)

Peripheral circuit

S1C17 core I/O 0xffff80 TTBR Vector Table Base Register Vector table base address display

For more information on TTBR, refer to “2.4 Vector Table”; and for more information on IDIR, refer to “2.5 Processor Information.” For more information on DBRAM, refer to “22 On-chip Debugging (DBG).”

Address Register name Function

0xffff84 IDIR Processor ID Register Processor ID display 0xffff90 DBRAM Debug RAM Base Register Debugging RAM base address display

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4 Power Supply Voltage

The S1C17001 operation power supply voltages are given below.

4 POWER SUPPLY VOLTAGE

Core voltage (LV I/O voltage (HV

DD): 1.65 V to 2.7 V

DD): 1.65 V to 3.6 V

Supply voltages within the respective ranges to LV The S1C17001 has two LV

DD pins, two HVDD pins, and five VSS pins. All must be connected to the + power supply

and GND. None should be left open.

DD and HVDD pins with the VSS pin as GND.

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5 Initial Reset

5.1 Initial Reset Factors

Shown below are the three different initial reset factors for initializing S1C17001 internal circuits.

(1) External initial reset via #RESET pin (2) External initial reset via P0 port (pins P00 to P03) key entry (set by software) (3) Internal initial reset via watchdog timer (set by software)

Figure 5.1.1 illustrates the initial reset circuit configuration.

5 INITIAL RESET

#RESET

P00 P01 P02 P03

Chattering filter

circuit

Oscillation stabilization

standby circuit

Key reset

control circuit

P0KRST

Watchdog timer

WDTMD

Figure 5.1.1: Initial reset circuit configuration

Digital noise

filter

SRQ

Internal reset

The CPU and peripheral circuits are initialized by initial reset factors. The CPU begins reset processing once the factors are canceled. This causes the reset vector to be read from the start of the vector table, and the program (initialization routine) starting at that address to be executed.

5.1.1 #RESET pin

Initial resetting is possible by inputting external Low level to the #RESET pin. To initialize the S1C17001 reliably, the #RESET pin must be maintained at Low level for at least the specified duration after the power supply voltage rises. (Refer to “24.5 AC Characteristics.”) Initial resetting is canceled if the #RESET input changes from Low to High, and the CPU begins reset interrupt processing. The #RESET pin incorporates a pull-up resistance.

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5 INITIAL RESET

5.1.2 P0 Port Key-Entry Reset

Initial resetting is possible by inputting external Low level simultaneously to the ports (P00 to P03) selected by software. The ports can be selected by P0KRST[1:0] (D[1:0]/P0_KRST register).

∗ P0KRST[1:0]: P0 Port Key-Entry Reset Configuration Bits in the P0 Port Key-Entry Reset Configuration

(P0_KRST) Register (D[1:0]/0x5209)

Table 5.1.2.1: P0 port key-entry reset settings

P0KRST[1:0] Port used

0x3 P00, P01, P02, P03 0x2 P00, P01, P02 0x1 P00, P01 0x0 Not used

For example, initial reset is applied when input to the four ports P00 to P03 is Low level simultaneously if P0KRST[1:0] is set to 0x3.

Note: • Make sure the specified ports are not simultaneously switched to Low during normal op-

erations when using the P0 port key-entry reset function.

• The P0 port key-entry reset function is enabled by software and cannot be used to perform a reset at power-on.

• The P0 port key-entry reset function cannot be used in SLEEP state.

5.1.3 Reset by Watchdog Timer

The S1C17001 incorporates a watchdog timer to detect runaway CPU. If the watchdog timer is not reset by software every 4 seconds (with this failure indicating a runaway CPU), the timer overflows, generating an NMI or reset. A reset is generated by writing “1” to WDTMD (D1/WDT_ST register). (NMI is generated if WDTMD is 0.)

∗WDTMD: NMI/Reset Mode Select Bit in the Watchdog Timer Status (WDT_ST) Register (D1/0x5041)

For detailed information on the watchdog timer, refer to “17 Watchdog Timer (WDT).”

Note: • When using the reset function with the watchdog timer, to prevent accidental resetting, take

care to program so that the watchdog timer is reset every four seconds.

• The watchdog timer reset function is enabled by software and cannot be used to perform a reset at power-on.

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5 INITIAL RESET

5.2 Initial Reset Sequence

CPU startup waits for the oscillation stabilization standby time (1024/fosc3 seconds*) to expire after resetting is cancelled via the #RESET pin at power-on. Figure 5.2.1 illustrates the sequence of operations after canceling the initial reset. The CPU starts up in sync with the OSC3 clock after the reset is canceled.

*fosc3: OSC3 clock frequency

Note: The oscillation stabilization standby time does not include the oscillation start time. The time

may be longer than that shown between power-on or SLEEP cancellation and command execution.

OSC3 clock

#RESET

Reset cancellation

Internal data request

Internal data address

Figure 5.2.1: Sequence of operations after initial reset cancellation

Reset cancellation

Oscillation

stabilization

standby time

Internal reset cancellation

Boot vector

Boot operation start

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5 INITIAL RESET

5.3 Initial Settings at Initial Resetting

The CPU internal register is initialized by initial resetting, as shown below.

R0 to R7: 0x0 PSR: 0x0 (interrupt level = 0, interrupt prohibited) SP: 0x0 PC: Reset vector at start of vector table is loaded by reset processing.

The internal RAM and display memory should be initialized via software, since they are not initialized by initial resetting.

The internal peripheral circuits are initialized in accordance with their particular specifications. They should be reset via software, if necessary. For detailed information on initial values after initial resetting, refer to the I/O register list in the Appendix or the respective peripheral circuit descriptions.

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6 Interrupt Controller

6.1 ITC Configuration

The S1C17001 features the following 14 different types of hardware interrupts:

1. P00 to P07 input interrupt (8 types)

2. P10 to P17 input interrupt (8 types)

3. Stopwatch timer interrupt (3 types)

4. Clock timer interrupt (4 types)

5. 8-bit OSC1 timer interrupt (1 type)

6. PWM & capture timer interrupt (2 types)

7. 8-bit timer interrupt (1 type)

8. 16-bit timer Ch.0 interrupt (1 type)

9. 16-bit timer Ch.1 interrupt (1 type)

10. 16-bit timer Ch.2 interrupt (1 type)

11. UART interrupt (3 types)

12. Remote controller interrupt (3 types)

13. SPI interrupt (2 types)

14. I

C interrupt (2 types)

6 INITERRUPT CONTROLLER

The various interrupt circuits include interrupt flags to indicate an interrupt request from a neighboring module and interrupt enable bits to permit/prohibit interrupts. The interrupt level (priority) for determining the processing order when multiple interrupts occur simultaneously can be set separately for each interrupt circuit. Each interrupt circuit includes the number of interrupt factors indicated in parentheses above. The respective peripheral module register controls the specific interrupt factor used to generate the interrupt request to the ITC. For detailed information on interrupt factors and interrupt factor control, refer to the discussion of the peripheral module. Figure 6.1.1 illustrates the interrupt system configuration.

S1C17 core

Interrupt request

Interrupt level

Vector number

NMI

Interrupt controller

Interrupt

control

Watchdog timer

Debug signal Reset signal

Interrupt flag

Interrupt enable bit

Interrupt level

Vector number

• • • • •

Interrupt flag

Interrupt enable bit

Interrupt level

Vector number

Figure 6.1.1: Interrupt system

Interrupt request

Peripheral module

• •

Peripheral module

• •

Interrupt flag

Interrupt enable

Interrupt flag

Interrupt enable

• • • • • • •

Interrupt flag

Interrupt enable

Interrupt flag

Interrupt enable

Interrupt factor 1

Interrupt factor n

Interrupt factor 1

Interrupt factor n

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6 INITERRUPT CONTROLLER

6.2 Vector Table

The vector table contains the vectors (processing routine start addresses) for interrupt processing routines. When an interrupt occurs, the S1C17 core reads the vector corresponding to the interrupt and executes that processing routine. The S1C17001 vector table starts from address 0x8000. The vector table base address can be read from the TTBR register (0xffff80). Table 6.2.1 shows the S1C17001 vector table.

Table 6.2.1: Vector table

Vector No./ Soft-

ware interrupt No.

0 (0x00) 0x8000 Reset • Low input to #RESET pin

1 (0x01) 0x8004 Irregular address interrupt Memory access command 2

7 (0x07) 0x801c Clock timer interrupt • Timer 32 Hz signal

8 (0x08) 0x8020 8-bit OSC1 timer interrupt Compare match 9 (0x09) 0x8024 10 (0x0a) 0x8028 11 (0x0b) 0x802c PWM & capture timer interrupt • Compare A

12 (0x0c) 0x8030 8-bit timer interrupt Timer underflow 13 (0x0d) 0x8034 16-bit timer Ch.0 interrupt Timer underflow 14 (0x0e) 0x8038 16-bit timer Ch.1 interrupt Timer underflow

15 (0x0f) 0x803c 16-bit timer Ch.2 interrupt Timer underflow

16 (0x10) 0x8040 UART interrupt • Transmit buffer empty

17 (0x11) 0x8044 Remote controller interrupt • Data length counter underflow

18 (0x12) 0x8048 SPI interrupt • Transmit buffer empty

19 (0x13) 0x804c I

20 (0x14) 0x8050

: : reserved –

31 (0x1f) 0x807c Low

*1: When same interrupt level is set *2: Watchdog timer interrupt selects reset or NMI using software.

Vector numbers 4 to 19 are assigned maskable interrupts supported by the S1C17001.

Vector address Hardware interrupt name Hardware interrupt factor Priority

• Watchdog timer overflow

• Timer 10 Hz signal

• Timer 1 Hz signal

• Timer 8 Hz signal

• Timer 2 Hz signal

• Timer 1 Hz signal

reserved –

• Compare B

• Receive buffer full

• Receive error

• Input rising edge detection

• Input falling edge detection

C interrupt • Transmit buffer empty

• Receive buffer full

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6 INITERRUPT CONTROLLER

6.3 Maskable Interrupt Control

6.3.1 ITC Enable

To use ITC, set ITEN (D0/ITC_CTL register) to 1.

∗ ITEN: ITC Enable Bit in the ITC Control (ITC_CTL) Register (D0/0x4304)

If ITEN is 0, maskable interrupts will not occur, regardless of the other register settings.

6.3.2 Interrupt Request from Peripheral Module and Interrupt Flag

If an interrupt factor for a permitted interrupt occurs in a peripheral module, that module sends an interrupt request signal to the ITC. This interrupt request signal causes the corresponding interrupt flag inside the ITC to be set to 1. The interrupt flag is maintained at 1 until it is reset to 0, indicating that an interrupt request was received from the peripheral module. The interrupt flag status can be read from the ITC_IFLG register (0x4300). Table 6.3.2.1 shows the correspondence between interrupt factors and interrupt flags.

Table 6.3.2.1: Hardware interrupt factors and interrupt flags

Vector No.

4 P0 port interrupt: P00 to P07 port input EIFT0 (D0/ITC_IFLG register)

5 P1 port interrupt: P10 to P17 port input EIFT1 (D1/ITC_IFLG register)

6 Stopwatch timer interrupt: 100 Hz/10 Hz/1 Hz signal EIFT2 (D2/ITC_IFLG register)

7 Clock timer interrupt: 32 Hz/8 Hz/2 Hz/1 Hz signal EIFT3 (D3/ITC_IFLG register)

8 8-bit OSC1 timer interrupt: Compare match EIFT4 (D4/ITC_IFLG register)

11 PWM & capture timer interrupt: Compare A/Compare B match EIFT7 (D7/ITC_IFLG register) 12 8-bit timer interrupt: Timer underflow IIFT0 (D8/ITC_IFLG register) 13 16-bit timer Ch.0 interrupt: Timer underflow IIFT1 (D9/ITC_IFLG register) 14 16-bit timer Ch.1 interrupt: Timer underflow IIFT2 (D10/ITC_IFLG register) 15 16-bit timer Ch.2 interrupt: Timer underflow IIFT3 (D11/ITC_IFLG register) 16 UART interrupt: Transmit buffer empty/Receive buffer full/Receive error IIFT4 (D12/ITC_IFLG register) 17 Remote controller interrupt: Data length counter underflow/Input rise-

up/Input drop-off

18 SPI interrupt: Transmit buffer empty/Receive buffer full IIFT6 (D14/ITC_IFLG register)

19 I

C interrupt: Transmit buffer empty/Receive buffer full IIFT7 (D15/ITC_IFLG register)

Hardware interrupt request Interrupt flag

IIFT5 (D13/ITC_IFLG register)

The ITC generates interrupts to the S1C17 core using the interrupt flags. If an interrupt flag is set to 1 with the interrupt permitted (refer to next section for details), the ITC sends the interrupt request, interrupt level, and vector number signals to the S1C17 core.

An interrupt flag set to 1 is reset by writing 1. The interrupt flag should be reset to 0 during the interrupt processing routine. If the interrupt flag is not reset by the interrupt processing routine, the same interrupt will recur after the interrupt processing routine has ended. (The interrupt is prohibited during interrupt processing and returned to the permitted state on execution of the reti command after interrupt processing.) Note however that the interrupt flags (EIFT0 to EIFT7) for interrupts set in the level trigger (refer to Section 6.3.5) are not reset by writing 1. These interrupt flags are reset when the interrupt source sets the interrupt signal to inactive.

Refer to the interrupt source module section for detailed information on the conditions under which interrupt factors arise and individual module interrupt settings are made.

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6 INITERRUPT CONTROLLER

6.3.3 Interrupt Permission/Prohibition

Sending an interrupt request to the S1C17 core requires first permitting the individual interrupts using the interrupt enable bit inside the ITC_EN register (0x4302) corresponding to the interrupt flag. Setting the interrupt enable bit to 1 permits interrupts, while setting it to 0 (default) prohibits interrupts. The interrupt enable bit does not affect the interrupt flag. Interrupt flags for interrupt requests generated by a peripheral module will be set regardless of the interrupt enable bit setting. Table 6.3.3.1 shows the correspondence between interrupt enable bits and interrupt flags.

Table 6.3.3.1: Interrupt enable bit list

Vector No.

4 P0 port interrupt EIFT0 (D0/ITC_IFLG register) EIEN0 (D0/ITC_EN register) 5 P1 port interrupt EIFT1 (D1/ITC_IFLG register) EIEN1 (D1/ITC_EN register) 6 Stopwatch timer interrupt EIFT2 (D2/ITC_IFLG register) EIEN2 (D2/ITC_EN register) 7 Clock timer interrupt EIFT3 (D3/ITC_IFLG register) EIEN3 (D3/ITC_EN register)

8 8-bit OSC1 timer interrupt EIFT4 (D4/ITC_IFLG register) EIEN4 (D4/ITC_EN register) 11 PWM & capture timer interrupt EIFT7 (D7/ITC_IFLG register) EIEN7 (D7/ITC_EN register) 12 8-bit timer interrupt IIFT0 (D8/ITC_IFLG register) IIEN0 (D8/ITC_EN register) 13 16-bit timer Ch.0 interrupt IIFT1 (D9/ITC_IFLG register) IIEN1 (D9/ITC_EN register) 14 16-bit timer Ch.1 interrupt IIFT2 (D10/ITC_IFLG register) IIEN2 (D10/ITC_EN register) 15 16-bit timer Ch.2 interrupt IIFT3 (D11/ITC_IFLG register) IIEN3 (D11/ITC_EN register) 16 UART interrupt IIFT4 (D12/ITC_IFLG register) IIEN4 (D12/ITC_EN register) 17 Remote controller interrupt IIFT5 (D13/ITC_IFLG register) IIEN5 (D13/ITC_EN register) 18 SPI interrupt IIFT6 (D14/ITC_IFLG register) IIEN6 (D14/ITC_EN register)

19 I

C interrupt IIFT7 (D15/ITC_IFLG register) IIEN7 (D15/ITC_EN register)

Hardware interrupt Interrupt flag Interrupt enable bit

Note: • To prevent generating unnecessary interrupts, always set the interrupt flags before

permitting interrupts by writing 1 to the interrupt enable bit.

• To generate an actual interrupt, the IE bit in the S1C17 core Processor Status Register (PSR) must be set to 1, in addition to the interrupt enable bit. The S1C17 core will not accept maskable interrupt requests if the IE bit is set to 0. In this case, interrupt requests from the ITC will be retained and accepted after the IE bit is set to 1.

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6.3.4 Processing for Multiple Interrupts

The ITC ITC_ELVx and ITC_ILVx registers (0x4306 to 0x4314) set the interrupt levels (0 to 7) for the various interrupt factors.

Table 6.3.4.1: Interrupt level setting bits

Vector No. Hardware interrupt Interrupt level setting bit Register address

4 P0 port interrupt EILV0[2:0] (D[2:0]/ITC_ELV0 register) 0x4306 5 P1 port interrupt EILV1[2:0] (D[10:8]/ITC_ELV0 register) 0x4306 6 Stopwatch timer interrupt EILV2[2:0] (D[2:0]/ITC_ELV1 register) 0x4308 7 Clock timer interrupt EILV3[2:0] (D[10:8]/ITC_ELV1 register) 0x4308

8 8-bit OSC1 timer interrupt EILV4[2:0] (D[2:0]/ITC_ELV2 register) 0x430a 11 PWM & capture timer interrupt EILV7[2:0] (D[10:8]/ITC_ELV3 register) 0x430c 12 8-bit timer interrupt IILV0[2:0] (D[2:0]/ITC_ILV0 register) 0x430e 13 16-bit timer Ch.0 interrupt IILV1[2:0] (D[10:8]/ITC_ILV0 register) 0x430e 14 16-bit timer Ch.1 interrupt IILV2[2:0] (D[2:0]/ITC_ILV1 register) 0x4310 15 16-bit timer Ch.2 interrupt IILV3[2:0] (D[10:8]/ITC_ILV1 register) 0x4310 16 UART interrupt IILV4[2:0] (D[2:0]/ITC_ILV2 register) 0x4312 17 Remote controller interrupt IILV5[2:0] (D[10:8]/ITC_ILV2 register) 0x4312 18 SPI interrupt IILV6[2:0] (D[2:0]/ITC_ILV3 register) 0x4314

19 I

The interrupt level can range from 0 to 7. The interrupt level set is issued to the S1C17 core at the same time as an interrupt request from the ITC. This interrupt level is used in the S1C17 core to prohibit subsequent interrupts with the same or lower levels (refer to Section

6.3.6). Initial resets reset all interrupt levels to 0. The S1C17 core rejects interrupt requests if the interrupt level is 0.

C interrupt IILV7[2:0] (D[10:8]/ITC_ILV3 register) 0x4314

The ITC uses the interrupt level when multiple interrupt factors occur simultaneously. If multiple interrupts occur at the same time permitted by the interrupt enable bit, the ITC sends the interrupt request with the highest level set by the ITC_ELVx and ITC_ILVx registers to the S1C17 core. If multiple interrupt factors with the same interrupt level occur simultaneously, the interrupt with the lowest vector number is processed first. The other interrupts are held until all have been accepted by the S1C17 core in descending order of priority. If an interrupt factor of higher priority occurs while the ITC outputs an interrupt request signal to the S1C17 core (before acceptance by the S1C17 core), the ITC alters the vector number and interrupt level signal to the setting details of the most recent interrupt. The immediately preceding interrupt is held.

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6.3.5 Interrupt Trigger Modes

The ITC includes two trigger modes – pulse trigger mode and level trigger mode – which enable acceptance of interrupt requests setting the EIFT flag as pulse or level signals. Trigger mode can be selected using the EITGx bits within the ITC_ELVx register (0x4306 to 0x4308). Setting the EITGx bits to 1 selects the level trigger mode; setting them to 0 (default) selects pulse trigger mode.

Note: All EITGx bits should be set to 1 (level trigger mode) for the S1C17001.

Table 6.3.5.1: Trigger mode selector bits

Hardware interrupt Trigger mode selector bit Register address

P0 port interrupt EITG0 (D4/ITC_ELV0 register) 0x4306 P1 port interrupt EITG1 (D12/ITC_ELV0 register) 0x4306 Stopwatch timer interrupt EITG2 (D4/ITC_ELV1 register) 0x4308 Clock timer interrupt EITG3 (D12/ITC_ELV1 register) 0x4308 8-bit OSC1 timer interrupt EITG4 (D4/ITC_ELV2 register) 0x430a PWM & capture timer interrupt EITG7 (D12/ITC_ELV3 register) 0x430c

The module setting the IIFT flag outputs a pulse signal only as the interrupt request to the ITC. No trigger mode selector bit is provided.

Pulse trigger mode

In pulse trigger mode, the ITC samples the interrupt signal using the system clock rising edge. If a pulse High

period is detected, the ITC sets the interrupt flag (IIFTx) to 1 and stops sampling that interrupt signal. The ITC resumes sampling of the interrupt signal after the application program resets the interrupt flag (IIFTx) to 0 (via interrupt processing routine).

pclk

Interrupt signal from

interrupt source

Interrupt flag

within ITC

Figure 6.3.5.1: Pulse trigger mode

Reset when software writes 1 to interrupt flag

Note: The S1C17001 interrupts listed below are in pulse trigger mode. If an interrupt occurs, reset

the interrupt flag IIFTx (to 1) within the interrupt processing routine.

• 8-bit timer interrupt

• 16-bit timer Ch.0 interrupt

• 16-bit timer Ch.1 interrupt

• 16-bit timer Ch.2 interrupt

• UART interrupt

• Remote controller interrupt

• SPI interrupt

• I

C interrupt

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Level trigger mode

In level trigger mode, the ITC samples the interrupt signal continuously using the system clock rising edge. The interrupt flag (EIFTx) is set to 1 if High level is detected and is reset to 0 if Low level is subsequently detected. Since interrupt flags (EIFTx) cannot be reset by writing 1 in this mode, the interrupt signal is held at High until the interrupt source module is accepted by the S1C17 core, and the interrupt signal must subsequently be cleared.

pclk

Interrupt signal from

interrupt source

Interrupt flag within ITC

Interrupt signal set to inactive by interrupt source

Figure 6.3.5.2: Level trigger mode

Note: The S1C17001 interrupts listed below are in level trigger mode. The interrupt flag within pe-

ripheral modules must be reset (to 1) within the interrupt processing routine rather than EIFTx

• P0 port interrupt

• P1 port interrupt

• Stopwatch timer interrupt

• Clock timer interrupt

• 8-bit OSC1 timer interrupt

• PWM & capture timer interrupt

For more information on interrupt flags for resetting, refer to the peripheral module descrip-

tion.

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6.3.6 S1C17 Core Interrupt Processing

Maskable interrupts for the S1C17 core occur when all of the following conditions are met:

• ITEN (D0/ITC_CTL register) has been set to 1.

∗ ITEN: ITC Enable Bit in the ITC Control (ITC_CTL) Register (D0/0x4304)

• The corresponding interrupt enable bit has been set to 1 for the interrupt factor.

• The PSR (S1C17 core internal processor status register) IE (interrupt enable) bit has been set to 1.

• The interrupt factor has a higher interrupt level set than that set for the PSR IL (interrupt level).

• No other interrupt factors having higher procedence (e.g., NMI) are present.

When an interrupt factor occurs, the corresponding interrupt flag is set to 1. This state is maintained until reset by the program or hardware (for interrupts set in level trigger mode). The interrupt factor is not cleared even if the conditions listed above remain unmet when the interrupt factor occurs. An interrupt occurs when the above conditions are met. If multiple maskable interrupt factors occur simultaneously, the interrupt factor with the highest level becomes the subject of the interrupt request to the S1C17 core. Interrupts with lower levels are held until the above conditions are subsequently met.

The S1C17 core samples interrupt requests for each cycle. On accepting an interrupt request, the S1C17 core switches to interrupt processing when execution of the current command is complete. Interrupt processing involves the following steps:

(1) The PSR and current program counter (PC) value is moved to the stack. (2) The PSR IE bit is reset to 0 (preventing subsequent maskable interrupts). (3) The PSR IL is set to the received interrupt level. (The NMI does not affect interrupt levels.) (4) The vector for the interrupt factor occurring is loaded to the PC to execute the interrupt processing routine.

When an interrupt is received, (2) prevents subsequent maskable interrupts. Setting the IE bit to 1 within the interrupt processing routine allows handling of multiple interrupts. In this case, IL is changed by (3), and only interrupts with higher levels than those already being processed will be accepted. Ending interrupt processing routines using a reti command returns the PSR to the state before the interrupt. The program resumes processing following the command being executed at the time the interrupt occurred via the next branch.

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6.4 NMI

The S1C17001 can generate NMIs (non-maskable interrupts) using the watchdog timer. The vector number for NMIs is 2, and the vector address is set in the vector table initial address + 8 bytes. These interrupts take precedence over other interrupt factors and are accepted unconditionally by the S1C17 core.

For detailed information on generating NMIs, refer to “17 Watchdog Timer (WDT).”

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6.5 Software Interrupts

Interrupts can be generated via software with S1C17 core int imm5 or intl imm5 and imm3 commands. The vector table vector number (0 to 31) is specified by the operand immediate imm5. With the intl command, imm3 can be used to specify an interrupt level (0 to 7) for the PSR IL fields. Details of the processor interrupt processing are the same as for when an interrupt generated by hardware occurs.

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6.6 HALT and SLEEP Mode Cancellation by Interrupt Factors

HALT and SLEEP modes are canceled by interrupt factors, and the CPU starts up. The interrupt factors capable of starting the CPU and specific program execution details after CPU startup (whether to branch into an interrupt processing routine) depend on the clock states in HALT and SLEEP modes. For more information, refer to “B.1 Clock Control Power Saving” in Appendix B.

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6.7 Control Register Details

Table 6.7.1 ITC register list

Address Register name Function

0x4300 ITC_IFLG Interrupt Flag Register Indicates and resets interrupt occurrence status. 0x4302 ITC_EN Interrupt Enable Register Permits/blocks maskable interrupts. 0x4304 ITC_CTL ITC Control Register Permits/blocks ITC operation. 0x4306 ITC_ELV0 External Interrupt Level Setup Register 0 Sets P0 and P1 port interrupt level and trigger mode. 0x4308 ITC_ELV1 External Interrupt Level Setup Register 1 Sets stopwatch timer, clock timer interrupt level and trigger mode. 0x430a ITC_ELV2 External Interrupt Level Setup Register 2 Sets 8-bit OSC1 timer interrupt level and trigger mode. 0x430c ITC_ELV3 External Interrupt Level Setup Register 3 Sets PWM & capture timer interrupt level and trigger mode. 0x430e ITC_ILV0 Internal Interrupt Level Setup Register 0 Sets 8-bit timer and 16-bit timer Ch.0 interrupt level. 0x4310 ITC_ILV1 Internal Interrupt Level Setup Register 1 Sets 16-bit timer Ch.1 and 16-bit timer Ch.2 interrupt level. 0x4312 ITC_ILV2 Internal Interrupt Level Setup Register 2 Sets UART and remote controller interrupt level. 0x4314 ITC_ILV3 Internal Interrupt Level Setup Register 3 Sets SPI and I

The ITC registers are described in detail below. These are 16-bit registers.

Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.

C interrupt levels.

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0x4300: Interrupt Flag Register (ITC_IFLG)

Interrupt Flag Register (ITC_IFLG)

0x4300

(16 bits)

D15 IIFT7 I D14 IIFT6 SPI interrupt flag 0 R/W D13 IIFT5 Remote controller interrupt flag 0 R/W D12 IIFT4 UART interrupt flag 0 R/W D11 IIFT3 16-bit timer Ch.2 interrupt flag 0 R/W D10 IIFT2 16-bit timer Ch.1 interrupt flag 0 R/W

D9 IIFT1 16-bit timer Ch.0 interrupt flag 0 R/W D8 IIFT0 8-bit timer interrupt flag 0 R/W D7 EIFT7 PWM&capture timer interrupt flag 1 Cause of D6 EIFT6 reserved 0 R/W D5 EIFT5 reserved 0 R/W D4 EIFT4 8-bit OSC1 timer interrupt flag 0 R/W D3 EIFT3 Clock timer interrupt flag 0 R/W D2 EIFT2 Stopwatch timer interrupt flag 0 R/W D1 EIFT1 P1 port interrupt flag 0 R/W D0 EIFT0 P0 port interrupt flag 0 R/W

D[15:8] IIFT[7:0]: Interrupt Flags (for Pulse Trigger)

These are interrupt flags indicating the interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled

The interrupt flags are reset to 1 if an interrupt factor occurs in the peripheral modules. An interrupt is generated to the S1C17 core provided the following conditions are met:

1. The corresponding interrupt enable bit is set to 1.

2. No other interrupt having requests higher priority levels have occurred.

3. The PSR IE bit was set to 1 (interrupt permitted).

4. The corresponding interrupt level setting bit has been set to a higher level than the S1C17 core interrupt level (IL).

C interrupt flag 1 Cause of

interrupt occurred

0 Cause of

interrupt not occurred

0 Cause of

interrupt not occurred

0 R/W Reset by writing 1.

0 R/W Reset by writing 1 in

pulse trigger mode.

Cannot be reset by software in level trigger mode.

The interrupt flags are set to 1 when an interrupt factor occurs regardless of the interrupt enable bit or

interrupt level setting bit states.

The interrupt flags must be reset and the PSR must be reset (by setting the IE bit to 1 or with the reti

command) to accept the next interrupt after interrupt occurrence.

An interrupt factor flag set to 1 is reset by writing 1.

Table 6.7.2: Hardware interrupt factors and interrupt flags

Interrupt flag Hardware interrupt factor

IIFT0 (D8) 8-bit timer interrupt: Timer underflow IIFT1 (D9) 16-bit timer Ch.0 interrupt: Timer underflow IIFT2 (D10) 16-bit timer Ch.1 interrupt: Timer underflow IIFT3 (D11) 16-bit timer Ch.2 interrupt: Timer underflow IIFT4 (D12) UART interrupt: Transmit buffer empty/Receive buffer full/Receive error IIFT5 (D13) Remote controller interrupt: Data length counter underflow/Input rise-up/Input drop-

off IIFT6 (D14) SPI interrupt: Transmit buffer empty/Receive buffer full IIFT7 (D15) I

C interrupt: Transmit buffer empty/Receive buffer full

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D[7:0] EIFT[7:0]: Interrupt Flags (for Level Trigger)

These are interrupt flags indicating the interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Disabled 0(W): Disabled

Refer to the description for IIFT[7:0]. Note that these interrupts must be set to level trigger mode in the ITC_ELVx registers (0x4306 to

0x430c). To reset the interrupt flags, rather than writing 1 to the bit, set the interrupt flag to 1 within the peripheral module.

Table 6.7.3: Hardware interrupt factors and interrupt flags

Interrupt flag Hardware interrupt factor

EIFT0 (D0) P0 port interrupt: P00 to P07 port input EIFT1 (D1) P1 port interrupt: P10 to P17 port input EIFT2 (D2) Stopwatch timer interrupt: 100 Hz/10 Hz/1 Hz signal EIFT3 (D3) Clock timer interrupt: 32 Hz/8 Hz/2 Hz/1 Hz signal EIFT4 (D4) 8-bit OSC1 timer interrupt: Compare match EIFT7 (D7) PWM & capture timer interrupt: Compare A/Compare B match

Note: The interrupt flags are not reset even if maskable interrupt requests are accepted by the

S1C17 core and branched to interrupt processing routines. Note that returning from an interrupt processing routine using the reti command without resetting the interrupt flags using the program will generate the same interrupt. Interrupt flags set to level trigger must be reset by the control register within the peripheral module.

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0x4302: Interrupt Enable Register (ITC_EN)

Interrupt Enable Register (ITC_EN)

0x4302

(16 bits)

D15 IIEN7 I D14 IIEN6 SPI interrupt enable 0 R/W D13 IIEN5 Remote controller interrupt enable 0 R/W D12 IIEN4 UART interrupt enable 0 R/W D11 IIEN3 16-bit timer Ch.2 interrupt enable 0 R/W D10 IIEN2 16-bit timer Ch.1 interrupt enable 0 R/W

D9 IIEN1 16-bit timer Ch.0 interrupt enable 0 R/W D8 IIEN0 8-bit timer interrupt enable 0 R/W D7 EIEN7 PWM&capture timer interrupt en-

D6 EIEN6 reserved 0 R/W D5 EIEN5 reserved 0 R/W D4 EIEN4 8-bit OSC1 timer interrupt enable 0 R/W D3 EIEN3 Clock timer interrupt enable 0 R/W D2 EIEN2 Stopwatch timer interrupt enable 0 R/W D1 EIEN1 P1 port interrupt enable 0 R/W D0 EIEN0 P0 port interrupt enable 0 R/W

D[15:0] IIEN[7:0], EIEN[7:0]: Interrupt Enable Bits

These bits permit or prohibit interrupt events. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default)

Setting the interrupt enable bit to 1 permits interrupts. Setting it to 0 prohibits interrupts. Even if interrupt prohibition has been set, the corresponding interrupt can still be used to cancel Stand-

by mode.

Table 6.7.4: Hardware interrupt factors and interrupt enable bits

Interrupt enable bit Hardware interrupt factor

EIEN0 (D0) P0 port interrupt: P00 to P07 port input EIEN1 (D1) P1 port interrupt: P10 to P17 port input EIEN2 (D2) Stopwatch timer interrupt: 100 Hz/10 Hz/1 Hz signal EIEN3 (D3) Clock timer interrupt: 32 Hz/8 Hz/2 Hz/1 Hz signal EIEN4 (D4) 8-bit OSC1 timer interrupt: Compare match EIEN7 (D7) PWM & capture timer interrupt: Compare A/Compare B match IIEN0 (D8) 8-bit timer interrupt: Timer underflow IIEN1 (D9) 16-bit timer Ch.0 interrupt: Timer underflow IIEN2 (D10) 16-bit timer Ch.1 interrupt: Timer underflow IIEN3 (D11) 16-bit timer Ch.2 interrupt: Timer underflow IIEN4 (D12) UART interrupt: Transmit buffer empty/Receive buffer full/Receive error IIEN5 (D13) Remote controller interrupt: Data length counter underflow/Input rise-up/Input drop-

IIEN6 (D14) SPI interrupt: Transmit buffer empty/Receive buffer full IIEN7 (D15) I

C interrupt enable 1 Enable 0 Disable 0 R/W

able

off

C interrupt: Transmit buffer empty/Receive buffer full

0 R/W

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0x4304: ITC Control Register (ITC_CTL)

0x4304

ITC Control Register (ITC_CTL)

D[15:1] Reserved

D0 ITEN: ITC Enable Bit

Permits interrupt control using the ITC. 1 (R/W): Permitted 0 (R/W): Prohibited (default)

Set to 1 before using the ITC.

D15–1 – reserved – – – 0 when being read.

(16 bits)

D0 ITEN ITC enable 1 Enable 0 Disable 0 R/W

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0x4306: External Interrupt Level Setup Register 0 (ITC_ELV0)

External Interrupt Level Setup Register 0 (ITC_ELV0)

D[15:13] Reserved

D12 EITG1: P1 Port Interrupt Trigger Mode Select Bit

Selects P1 port interrupt trigger mode. This should be set to 1 for the S1C17001. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default)

In pulse trigger mode, the ITC samples interrupt signals using system clock rising edges. When the

In level trigger mode, the ITC samples interrupt signals using system clock rising edges. When High

0x4306

D15–13 – reserved – – – 0 when being read.

(16 bits)

D12 EITG1 P1 interrupt trigger mode 1 Level 0 Pulse 0 R/W Be sure to set to 1. D11 – reserved – – – 0 when being read.

D10–8 EILV1[2:0] P1 interrupt level 0 to 7 0x0 R/W

D7–5 – reserved – – – 0 when being read.

D4 EITG0 P0 interrupt trigger mode 1 Level 0 Pulse 0 R/W Be sure to set to 1. D3 – reserved – – – 0 when being read.

D2–0 EILV0[2:0] P0 interrupt level 0 to 7 0x0 R/W

pulse High period is detected, the ITC sets the interrupt flag (EIFTx) to 1 and stops sampling that interrupt signal. The ITC resumes interrupt signal sampling after the application program (interrupt processing routine) resets the interrupt flag (EIFTx) to 0.

level is detected, the interrupt flag (EIFTx) is set to 1 and is subsequently reset to 0 when Low level is detected. Interrupt flags (EIFTx) cannot be reset by writing 1 in this mode. The interrupt signal must be maintained at High until the interrupt source module is accepted by the S1C17 core, and the interrupt signal must then be cleared.

D11 Reserved

D[10:8] EILV1[2:0]: P1 Port Interrupt Level Bits

Set the P1 port interrupt level (0 to 7). (Default: 0) The S1C17 core does not accept interrupts with levels set lower than the PSR IL value. The ITC uses the interrupt level when multiple interrupt factors occur simultaneously. If multiple interrupts occur at the same time permitted by the interrupt enable bit, the ITC sends the in-

terrupt request with the highest level set by the ITC_ELVx and ITC_ILVx registers (0x4306 to 0x4314) to the S1C17 core.

If multiple interrupt factors with the same interrupt level occur simultaneously, the interrupt with the

lowest vector number is processed first. The other interrupts are held until all have been accepted by the S1C17 core in descending order of priority.

If an interrupt factor of higher priority occurs while the ITC outputs an interrupt request signal to the

S1C17 core (before acceptance by the S1C17 core), the ITC alters the vector number and interrupt level signal to the setting details of the most recent interrupt. The immediately preceding interrupt is held.

D[7:5] Reserved

D4 EITG0: P0 Port Interrupt Trigger Mode Select Bit

Selects P0 port interrupt trigger mode. This should be set to 1 for the S1C17001. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default)

Refer to the EITG1 (D12) description.

D3 Reserved

D[2:0] EILV0[2:0]: P0 Port Interrupt Level Bits

Set the P0 port interrupt level (0 to 7). (Default: 0) Refer to the EILV1[2:0] (D[10:8]) description.

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0x4308: External Interrupt Level Setup Register 1 (ITC_ELV1)

External Interrupt Level Setup Register 1 (ITC_ELV1)

D[15:13] Reserved

D12 EITG3: Clock Timer Interrupt Trigger Mode Select Bit

Selects clock timer interrupt trigger mode. This should be set to 1 for the S1C17001. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default)

Refer to the ITC_ELV0 register (0x4306) EITG1 (D12) description.

D11 Reserved

D[10:8] EILV3[2:0]: Clock Timer Interrupt Level Bits

Set the clock timer interrupt level (0 to 7). (Default: 0) Refer to the ITC_ELV0 register (0x4306) EILV1[2:0] (D[10:8]) description.

D[7:5] Reserved

0x4308

D15–13 – reserved – – – 0 when being read.

(16 bits)

D12 EITG3 CT interrupt trigger mode 1 Level 0 Pulse 0 R/W Be sure to set to 1. D11 – reserved – – – 0 when being read.

D10–8 EILV3[2:0] CT interrupt level 0 to 7 0x0 R/W

D7–5 – reserved – – – 0 when being read.

D4 EITG2 SWT interrupt trigger mode 1 Level 0 Pulse 0 R/W Be sure to set to 1. D3 – reserved – – – 0 when being read.

D2–0 EILV2[2:0] SWT interrupt level 0 to 7 0x0 R/W

D4 EITG2: Stopwatch Timer Interrupt Trigger Mode Select Bit

Selects stopwatch timer interrupt trigger mode. This should be set to 1 for the S1C17001. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default)

Refer to the ITC_ELV0 register (0x4306) EITG1 (D12) description.

D3 Reserved

D[2:0] EILV2[2:0]: Stopwatch Timer Interrupt Level Bits

Set the stopwatch timer interrupt level (0 to 7). (Default: 0) Refer to the ITC_ELV0 register (0x4306) EILV1[2:0] (D[10:8]) description.

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0x430a: External Interrupt Level Setup Register 2 (ITC_ELV2)

External Interrupt Level Setup Register 2 (ITC_ELV2)

D[15:5] Reserved

D4 EITG4: 8-bit OSC1 Timer Interrupt Trigger Mode Select Bit

Selects 8-bit OSC1 timer interrupt trigger mode. This should be set to 1 for the S1C17001. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default)

Refer to the ITC_ELV0 register (0x4306) EITG1 (D12) description.

D3 Reserved

D[2:0] EILV4[2:0]: 8-bit OSC1 Timer Interrupt Level Bits

Set the 8-bit OSC1 timer interrupt level (0 to 7). (Default: 0) Refer to the ITC_ELV0 register (0x4306) EILV1[2:0] (D[10:8]) description.

0x430a

D15–5 – reserved – – – 0 when being read.

(16 bits)

D4 EITG4 T8OSC1 interrupt trigger mode 1 Level 0 Pulse 0 R/W Be sure to set to 1. D3 – reserved – – – 0 when being read.

D2–0 EILV4[2:0] T8OSC1 interrupt level 0 to 7 0x0 R/W

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0x430c: External Interrupt Level Setup Register 3 (ITC_ELV3)

External Interrupt Level Setup Register 3 (ITC_ELV3)

D[15:13] Reserved

D12 EITG7: PWM & Capture Timer Interrupt Trigger Mode Select Bit

Selects PWM & capture timer interrupt trigger mode. This should be set to 1 for the S1C17001. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default)

Refer to the ITC_ELV0 register (0x4306) EITG1 (D12) description.

D11 Reserved

D[10:8] EILV7[2:0]: PWM & Capture Timer Interrupt Level Bits

Set the PWM & capture timer interrupt level (0 to 7). (Default: 0) Refer to the ITC_ELV0 register (0x4306) EILV1[2:0] (D[10:8]) description.

D[7:0] Reserved

0x430c

D15–13 – reserved – – – 0 when being read.

(16 bits)

D12 EITG7 T16E interrupt trigger mode 1 Level 0 Pulse 0 R/W Be sure to set to 1. D11 – reserved – – – 0 when being read.

D10–8 EILV7[2:0] T16E interrupt level 0 to 7 0x0 R/W

D7–0 – reserved – – – 0 when being read.

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0x430e: Internal Interrupt Level Setup Register 0 (ITC_ILV0)

Internal Interrupt Level Setup Register 0 (ITC_ILV0)

D[15:11] Reserved

D[10:8] IILV1[2:0]: 16-bit Timer Ch.0 Interrupt Level Bits

Set the 16-bit timer Ch.0 interrupt level (0 to 7). (Default: 0) The S1C17 core does not accept interrupts with levels set lower than the PSR IL value. The ITC uses the interrupt level when multiple interrupt factors occur simultaneously. If multiple interrupts occur at the same time permi tted by the interrupt enable bit, the ITC sends the in-

If multiple interrupt factors with the same interrupt level occur simultaneously, the interrupt with the

If an interrupt factor of higher priority occurs while the ITC outputs an interrupt request signal to the

D[7:3] Reserved

0x430e

D15–11 – reserved – – – 0 when being read.

(16 bits)

D10–8 IILV1[2:0] T16 Ch.0 interrupt level 0 to 7 0x0 R/W

D7–3 – reserved – – – 0 when being read. D2–0 IILV0[2:0] T8 interrupt level 0 to 7 0x0 R/W

terrupt request with the highest level set by the ITC_ELVx and ITC_ILVx registers (0x4306 to 0x4314) to the S1C17 core.

lowest vector number is processed first. The other interrupts are held until all have been accepted by the S1C17 core in descending order of priority.

D[2:0] IILV0[2:0]: 8-bit Timer Interrupt Level Bits

Set the 8-bit timer interrupt level (0 to 7). (Default: 0) Refer to the IILV1[2:0] (D[10:8]) description.

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0x4310: Internal Interrupt Level Setup Register 1 (ITC_ILV1)

Internal Interrupt Level Setup Register 1

(ITC_ILV1)

D[15:11] Reserved

D[10:8] IILV3[2:0]: 16-bit Timer Ch.2 Interrupt Level Bits

Set the 16-bit timer Ch.2 interrupt level (0 to 7). (Default: 0) Refer to the ITC_ILV0 register (0x430e) IILV1[2:0] (D[10:8]) description.

D[7:3] Reserved

D[2:0] IILV2[2:0]: 16-bit Timer Ch.1 Interrupt Level Bits

Set the 16-bit timer Ch.1 interrupt level (0 to 7). (Default: 0) Refer to the ITC_ILV0 register (0x430e) IILV1[2:0] (D[10:8]) description.

0x4310

D15–11 – reserved – – – 0 when being read.

(16 bits)

D10–8 IILV3[2:0] T16 Ch.2 interrupt level 0 to 7 0x0 R/W

D7–3 – reserved – – – 0 when being read. D2–0 IILV2[2:0] T16 Ch.1 interrupt level 0 to 7 0x0 R/W

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0x4312: Internal Interrupt Level Setup Register 2 (ITC_ILV2)

Internal Interrupt Level Setup Register 2 (ITC_ILV2)

D[15:11] Reserved

D[10:8] IILV5[2:0]: Remote Controller Interrupt Level Bits

Set the remote controller interrupt level (0 to 7). (Default: 0) Refer to the ITC_ILV0 register (0x430e) IILV1[2:0] (D[10:8]) description.

D[7:3] Reserved

D[2:0] IILV4[2:0]: UART Interrupt Level Bits

Set the UART interrupt level (0 to 7). (Default: 0) Refer to the ITC_ILV0 register (0x430e) IILV1[2:0] (D[10:8]) description.

0x4312

D15–11 – reserved – – – 0 when being read.

(16 bits)

D10–8 IILV5[2:0] REMC interrupt level 0 to 7 0x0 R/W

D7–3 – reserved – – – 0 when being read. D2–0 IILV4[2:0] UART interrupt level 0 to 7 0x0 R/W

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0x4314: Internal Interrupt Level Setup Register 3 (ITC_ILV3)

Internal Interrupt Level Setup Register 3 (ITC_ILV3)

D[15:11] Reserved

D[10:8] IILV7[2:0]: I

Set the I Refer to the ITC_ILV0 register (0x430e) IILV1[2:0] (D[10:8]) description.

D[7:3] Reserved

D[2:0] IILV6[2:0]: SPI Interrupt Level Bits

Set the SPI interrupt level (0 to 7). (Default: 0) Refer to the ITC_ILV0 register (0x430e) IILV1[2:0] (D[10:8]) description.

0x4314

D15–11 – reserved – – – 0 when being read.

(16 bits)

D10–8 IILV7[2:0] I

D7–3 – reserved – – – 0 when being read. D2–0 IILV6[2:0] SPI interrupt level 0 to 7 0x0 R/W

C Interrupt Level Bits

C interrupt level (0 to 7). (Default: 0)

C interrupt level 0 to 7 0x0 R/W

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6.8 Precautions

• To prevent the recurrence of interrupts due to the same interrupt factor, always reset the interrupt flag before permitting interrupts, resetting PSR, or executing the reti command.

• The S1C17001 interrupts listed below are in level trigger mode.

- P0 port interrupt

- P1 port interrupt

- Stopwatch timer interrupt

- Clock timer interrupt

- 8-bit OSC1 timer interrupt

- PWM & capture timer interrupt

Make sure all EITGx bits within the ITC_ELVx registers (0x4306 to 0x430c) have been set to 1 (level trigger

mode).

The interrupt flag within peripheral modules must be reset (to 1) within the interrupt processing routine rather

than EIFTx. For more information on interrupt flags for resetting, refer to the peripheral module description.

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7 Oscillator Circuit (OSC)

7.1 OSC Module Configuration

The S1C17001 incorporates two internal oscillator circuits (OSC3 and OSC1). The OSC3 oscillator circuit generates the main clock (max. 8.2 MHz) for high-speed operation of the S1C17 core and peripheral circuits. The OSC1 oscillator circuit generates a sub-clock (typ. 32.768 kHz) for timer and low-power operations. The OSC3 clock is selected as the system clock after initial resetting. Oscillator circuit on/off switching and system clock selection (between OSC3 and OSC1) is controlled by software. External clock output is also possible. Figure 7.1.1 illustrates the clock system and OSC module configuration.

OSC3

OSC4

FOUT3

OSC1

OSC2

FOUT1

RESET

NMI

SLEEP, on/off control

OSC3 oscillator circuit (8.2 MHz)

FOUT3 output circuit

On/off control

SLEEP, on/off control

OSC1 oscillator circuit (32.768 kHz)

FOUT1 output circuit

On/off control

Noise filter

On/off control

Noise filter

On/off control

wakeup

Wait circuit for wakeup

Division circuit (1/1 to 1/4)

Division ratio selection

S1C17 core

OSC

Clock source

OSC3

OSC1

selection

System clock

OSC1

Gear selection

Clock gear (1/1 to 1/8)

On/off control

Gate

On/off control

Gate

Division

(1/128)

circuit

(1/1 to 1/32)

Division ratio selection On/off control

Gate

Figure 7.1.1: OSC module configuration

Gate S1C17 core

Gate

Division circuit (1/1 to 1/16K)

HALT

CLG

PSC

CCLK

BCLK

PCLK

CLK_256Hz

Internal bus, RAM, ROM

ITC, T16, T8F, UART, SPI, I2C, T16E, P, MISC, REMC, Control register (CT, SWT, WDT, T8OSC1)

T8F, T16, T16E, REMC, P, UART, SPI, I2C

CT, SWT, WDT

T8OSC1

To reduce power consumption, control the clock in conjunction with processing and use standby mode. For more information on reducing power consumption, refer to “Appendix B: Power Saving.”

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7.2 OSC3 Oscillator Circuit

The OSC3 oscillator circuit generates the main clock (max. 8.2 MHz) for high-speed operation of the S1C17 core and peripheral circuits. The oscillator circuit can be either crystal- or ceramic-based. It also supports external clock input.

CG3

VSS

OSC3

X'tal3 or Ceramic

OSC4

(1) Crystal/ceramic oscillator circuit (2) External clock input

OSC3

Oscillator circuit control signal

SLEEP control

LVDD

OSC3

External clock

N.C.

OSC4

OSC3

Oscillator circuit control signal

SLEEP control

Figure 7.2.1 illustrates the OSC3 oscillator circuit configuration.

When used as a crystal or ceramic oscillator circuit, a crystal oscillator (X’tal3) or ceramic oscillator (Ceramic) and feedback resistor (R should also be connected between the OSC3/OSC4 pins and V the OSC4 pin and C

f) should be connected between the OSC3 and OSC4 pins. Two capacitors (CG3 and CD3)

SS. A drain resistor (Rd) should be connected between

D3, if required.

When used with external clock input, the OSC4 pin should be left free, and a clock with a duty ratio of 50% at LV

DD level should be input to the OSC3 pin.

OSC3 oscillation on/off

The OSC3 oscillator circuit stops oscillating if OSC3EN (D0/OSC_CTL register) is set to 0 and starts oscillat-

ing if set to 1. The OSC3 oscillator circuit stops oscillating even in SLEEP mode.

∗ OSC3EN: OSC3 Enable Bit in the Oscillation Control (OSC_CTL) Register (D0/0x5061)

After initial resetting, OSC3EN is set to 1 and the OSC3 oscillator circuit is on. Since the OSC3 clock is used

as the system clock, the S1C17 core begins operating using the OSC3 clock.

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Stabilization wait time at start of OSC3 oscillation

The OSC3 oscillator circuit incorporates an oscillation stabilization wait timer to prevent malfunctions due

to unstable clock operations at the start of OSC3 oscillation—for example, when power is first turned on, on awaking from SLEEP, or when the OSC3 oscillation circuit is turned on via software. The OSC3 clock is not fed to the system until the time set for this timer has elapsed.

Four different oscillation stabilization wait times can be selected using the OSC3WT[1:0] (D[5:4]/OSC_CTL

∗ OSC3WT[1:0]: OSC3 Wait Cycle Select Bits in the Oscillation Control (OSC_CTL) Register (D[5:4]/0x5061)

Table 7.2.2: OSC3 oscillation stabilization wait time settings

OSC3WT[1:0] Oscillation stabilization

wait time 0x3 128 cycles 0x2 256 cycles 0x1 512 cycles 0x0 1,024 cycles

(Default: 0x0)

This is set to 1,024 cycles (OSC3 clock) after initial resetting. The CPU does not begin operating immediately after resetting until this time has elapsed.

Note: The OSC3 oscillation start time depends on the oscillator and externally connected compo-

nents. The time should be set with an adequate oscillation stabilization wait time. Refer to the typical oscillation start times specified in “24 Electrical Characteristics.”

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7.3 OSC1 Oscillator Circuit

The OSC1 oscillator circuit generates a (typ.) 32.768 kHz sub-clock. The OSC1 clock is generally used as the timer operation clock (for the clock timer, stopwatch timer, watchdog timer, and 8-bit OSC1 timer). It reduces power consumption and can be used as the system clock instead of the OSC3 clock when no high-speed processing is required. The oscillator circuit is crystal-based. The oscillator circuit also allows use of an external clock input. Figure 7.3.1 illustrates the OSC1 oscillator circuit configuration.

CG1

CD1

VSS

X'tal1

OSC1

OSC2

(1) Crystal oscillator circuit

LVDD

OSC1

Oscillator circuit control signal

SLEEP control

OSC1

OSC2

(3) When not used

Figure 7.3.1: OSC1 oscillator circuit

OSC1

External clock

N.C.

OSC2

Low level

Oscillator circuit control signal

SLEEP control

OSC1

Oscillator circuit control signal

SLEEP control

(2) External clock input

When this is used as a crystal oscillator circuit, connect a crystal oscillator X’tal1 (typ. 32.768 kHz) and feedback resistor (R pins and V

f) between the OSC1 and OSC2 pins. Connect two capacitors (CG1 and CD1) between the OSC1/OSC2

SS. A drain resistor (Rd) should be connected between the OSC2 pin and CD1, if required.

When used with external clock (max. 100 kHz) input, the OSC2 pin should be left free, and a clock with a duty ratio of 50% at LV If the OSC1 oscillator circuit is not used, connect the OSC1 pin to V

DD level should be input to the OSC1 pin.

SS while leaving the OSC2 pin open.

OSC1 oscillation on/off

The OSC1 oscillator circuit stops oscillating if OSC1EN (D1/OSC_CTL register) is set to 0 and starts oscillat-

ing if set to 1. The OSC1 oscillator circuit stops oscillating even in SLEEP mode.

∗ OSC1EN: OSC1 Enable Bit in the Oscillation Control (OSC_CTL) Register (D1/0x5061)

Stabilization wait time at start of OSC1 oscillation

The OSC1 oscillator circuit incorporates an oscillation stabilization wait timer to prevent malfunctions due

to unstable clock operations at the start of OSC1 oscillation—for example, when power is first turned on, on awaking from SLEEP, or when the OSC1 oscillation circuit is turned on via software. The OSC1 clock does not feed the system for a period of 256 cycles after the start of oscillation.

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7.4 System Clock Switching

The software can be used to select the OSC3 or OSC1 clocks as the system clock. If possible, you can reduce power consumption by stopping OSC3 oscillation after switching the system clock to OSC1. The procedure is given below.

OSC3 to OSC1

1. If OSC1 oscillation is stopped, start oscillation by setting OSC1EN (D1/OSC_CTL register) to 1.

∗ OSC1EN: OSC1 Enable Bit in the Oscillation Control (OSC_CTL) Register (D1/0x5061)

2. Set CLKSRC (D0/OSC_SRC register) to 1 and switch the system clock from OSC3 to OSC1.

∗ CLKSRC: System Clock Source Select Bit in the Clock Source Select (OSC_SRC) Register (D0/0x5060)

3. If operation is not required for peripheral modules using OSC3 as an oscillation source, set OSC3EN (D0/ OSC_CTL register) to 0 to stop OSC3 oscillation.

∗ OSC3EN: OSC3 Enable Bit in the Oscillation Control (OSC_CTL) Register (D0/0x5061)

Note: • Switching the system clock from OSC3 to OSC1 immediately after starting OSC1 oscillation

will stop the system clock until the OSC1 clock starts up (for the OSC1 clock 256-cycle period).

• OSC3 oscillation cannot be stopped before switching the system clock to OSC1.

OSC1 to OSC3

1. Set the OSC3WT[1:0] (D[5:4]/OSC_CTL register) to an oscillation stabilization wait time (see Table 7.2.2) at least as long as OSC3 oscillation start time. (Not necessary if already set.)

∗ OSC3WT[1:0]: OSC3 Wait Cycle Select Bits in the Oscillation Control (OSC_CTL) Register (D[5:4]/0x5061)

2. If the OSC3 oscillation is stopped, set OSC3EN (D0/OSC_CTL register) to 1 to start oscillation. After starting OSC3 oscillation, the OSC3 clock is not fed until the time set in OSC3WT[1:0] (D[5:4]/OSC_CTL register) has elapsed.

3. Set CLKSRC (D0/OSC_SRC register) to 0 to switch the system clock from OSC1 to OSC3.

4. If operation is not required for peripheral modules using OSC1 as an oscillation source, set OSC1EN (D1/ OSC_CTL register) to 0 to stop OSC1 oscillation.

Note: • Steps 1 and 2 are not required if the OSC3 oscillation circuit is already operating.

• The OSC3 oscillation start time depends on the oscillator and externally connected components. The time should be set with an adequate oscillation stabilization wait time. Refer to the typical oscillation start times specified in “24 Electrical Characteristics.”

• OSC1 oscillation cannot be stopped before switching the system clock to OSC3.

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7.5 8-bit OSC1 Timer Clock Control

The OSC module consists of a division circuit for generating the 8-bit OSC1 timer operation clock and a device for controlling the feed. The 8-bit OSC1 timer is a programmable timer that operates only using the OSC1 division clock. For detailed information, refer to “14 8-bit OSC1 Timer (T8OSC1).”

OSC1 clock

Division circuit (1/1 to 1/32)

Division ratio selection On/off control

Figure 7.5.1: 8-bit OSC1 timer clock control circuit

Gate

8-bit OSC1 timer

Clock division ratio selection

Select the OSC1 clock division ratio using T8O1CK[2:0] (D[3:1]/OSC_T8OSC1 register)

∗ T8O1CK[2:0]: T8OSC1 Clock Division Ratio Select Bits in the T8OSC1 Clock Control (OSC_T8OSC1)

Table 7.5.1: T8OSC1 clock division ratio selection

T8O1CK[2:0] Division ratio

0x7 to 0x6 Reserved

0x5 OSC1-1/32 0x4 OSC1-1/16 0x3 OSC1-1/8 0x2 OSC1-1/4 0x1 OSC1-1/2 0x0 OSC1-1/1

(Default: 0x0)

Clock feed control

The clock feed to the 8-bit OSC1 timer is controlled using T8O1CE (D0/OSC_T8OSC1 register). The T8O1CE default setting is 0, which stops the clock feed. Setting T8O1CE to 1 sends the clock generated as

above to the 8-bit OSC1 timer. Stop the clock feed to reduce power consumption if 8-bit OSC1 timer operation is not required.

∗ T8O1CE: T8OSC1 Clock Enable Bit in the T8OSC1 Clock Control (OSC_T8OSC1) Register (D0/0x5065)

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7.6 Clock External Output (FOUT3, FOUT1)

The OSC3 division clock (FOUT3) and OSC1 clock (FOUT1) can be output to devices outside the chip.

P30 port

OSC3 clock

OSC1 clock

Division circuit (1/1 to 1/4)

Division ratio selection

Figure 7.6.1: Clock output circuit

FOUT3 Output circuit

On/off control P30 function selection

P13 port

FOUT1 Output circuit

On/off control

P13 function selection

FOUT3(P30)

FOUT1(P13)

FOUT3 output

FOUT3 is the OSC3 division clock.

Output pin setting

The FOUT3 output pin is combined with the P30 port. This functions as the P30 port pin by default, so the

pin function should be changed by writing 1 to P30MUX (D0/P3_PMUX register) if use is required for FOUT3 output.

∗ P30MUX: P30 Port Function Select Bit in the P3 Port Function Select (P3_PMUX) Register (D0/0x52a3)

FOUT3 clock frequency selection

Three different clock output frequencies can be selected. Select the division ratio for the OSC3 clock using

FOUT3D[1:0] (D[3:2]/OSC_FOUT register).

∗ FOUT3D[1:0]: FOUT3 Clock Division Ratio Select Bits in the FOUT Control (OSC_FOUT) Register

Clock output control

The clock output is controlled using the FOUT3E (D1/OSC_FOUT register). Setting FOUT3E to 1 outputs

the FOUT3 clock from the FOUT3 pin. Setting it to 0 halts output.

∗ FOUT3E: FOUT3 Output Enable Bit in the FOUT Control (OSC_FOUT) Register (D1/0x5064)

(D[3:2]/0x5064)

Table 7.6.1: FOUT3 clock division ratio selection

FOUT3D[1:0] Division ratio

0x3 Reserved 0x2 OSC3-1/4 0x1 OSC3-1/2 0x0 OSC3-1/1

(Default: 0x0)

FOUT3E

FOUT3 output (P30)

Figure 7.6.2: FOUT3 output

Note: Since the FOUT3 signal is asynchronized with FOUT3E writing, switching output on or off will

generate certain hazards.

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FOUT1 output

FOUT1 is the OSC1 clock.

Output pin setting

The FOUT1 output pin is combined with the P13 port. This functions as the P13 port pin by default, so the

pin function should be changed by writing 1 to P13MUX (D3/P1_PMUX register) if use is required for FOUT1 output.

∗ P13MUX: P13 Port Function Select Bit in the P1 Port Function Select (P1_PMUX) Register (D3/0x52a1)

Clock output control

The clock output is controlled using the FOUT1E (D0/OSC_FOUT register). Setting FOUT1E to 1 outputs

the FOUT1 clock from the FOUT1 pin. Setting it to 0 halts output.

∗ FOUT1E: FOUT1 Output Enable Bit in the FOUT Control (OSC_FOUT) Register (D1/0x5064)

FOUT1E

FOUT1 output (P13)

Figure 7.6.3: FOUT1 output

Note: Since the FOUT1 signal is asynchronized with FOUT1E writing, switching output on or off will

generate certain hazards.

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7.7 RESET and NMI Input Noise Filters

Since accidental activation of RESET or NMI by noise in the S1C17 core input signal will cause unintended resetting or NMI processing, the OSC module incorporates noise filters operated by the system clock. The filters remove noise from these signals before they reach the S1C17 core. Separate noise filters are used for each signal. You can select to use or bypass them individually. All are active immediately after the initial resetting.

RESET input noise filter: Filters noise when RSTFE (D1/OSC_NFEN register) = 1; bypassed when RSTFE = 0 NMI input noise filter: Filters noise when NMIFE (D0/OSC_NFEN register) = 1; bypassed when NMIFE = 0

∗ RSTFE: Reset Noise Filter Enable Bit in the Noise Filter Enable (OSC_NFEN) Register (D1/0x5062) ∗ NMIFE: NMI Noise Filter Enable Bit in the Noise Filter Enable (OSC_NFEN) Register (D0/0x5062)

The noise filters operate using the system clock (OSC3 or OSC1 clock) divided to 1/8. When activated, they filter out noise with pulses not exceeding two clock cycles. This means the pulse width must be at least 16 cycles of the system clock to input as a valid signal.

Note: • All noise filters should normally be enabled.

• The S1C17001 does not feature external NMI input pins, but the watchdog timer NMI request signal passes through these filters.

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7.8 Control Register Details

Table 7.8.1 OSC register list

Address Register name Function

0x5060 OSC_SRC Clock Source Select Register Clock source selection 0x5061 OSC_CTL Oscillation Control Register Oscillation control 0x5062 OSC_NFEN Noise Filter Enable Register Noise filter on/off 0x5064 OSC_FOUT FOUT Control Register Clock external output control 0x5065 OSC_T8OSC1 T8OSC1 Clock Control Register 8-bit OSC1 timer clock setting

The OSC module registers are described in detail below. These are 8-bit registers.

Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.

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0x5060: Clock Source Select Register (OSC_SRC)

Clock Source Select

(OSC_SRC)

0x5060

D[7:1] Reserved

D0 CLKSRC: System Clock Source Select Bit

Selects the system clock source. 1 (R/W): OSC1 0 (R/W): OSC3 (default)

OSC3 is selected for normal (high-speed) operations. If the OSC3 clock is not required, OSC1 can be

set as the system clock and OSC3 stopped to reduce power consumption.

Note: If the system clock is switched from OSC3 to OSC1 immediately after starting OSC1 oscilla-

tion, the system clock will stop until the OSC1 clock starts up (for the OSC1 clock 256-cycle period).

(8 bits)

D7–1 –

D0 CLKSRC System clock source select 1 OSC1 0 OSC3 0 R/W

reserved – – – 0 when being read.

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0x5061: Oscillation Control Register (OSC_CTL)

Oscillation Control Register (OSC_CTL)

0x5061

D[7:6] Reserved

D[5:4] OSC3WT[1:0]: OSC3 Wait Cycle Select Bits

An oscillation stabilization wait timer is set to prevent malfunctions due to unstable clock operation at

the start of OSC3 oscillation.

The OSC3 clock is not fed to the system immediately after OSC3 oscillation starts—for example, when

power is first turned on, on awaking from SLEEP, or when the OSC3 oscillation circuit is turned on via software—until the time set here has elapsed.

This is set to 1,024 cycles (OSC3 clock) after initial resetting. The CPU does not begin operating im-

mediately after resetting until this time has elapsed.

D7–6 – reserved – – – 0 when being read.

(8 bits)

OSC3WT[1:0]

D5–4

D3–2 – reserved – – – 0 when being read.

D1 OSC1EN OSC1 enable 1 Enable 0 Disable 1 R/W D0 OSC3EN OSC3 enable 1 Enable 0 Disable 1 R/W

OSC3 wait cycle select OSC3WT[1:0] Wait cycle 0x0 R/W

0x3 0x2 0x1 0x0

128 cycles 256 cycles 512 cycles

1024 cycles

Table 7.8.2: OSC3 oscillation stabilization wait time settings

OSC3WT[1:0] Oscillation stabilization

wait time 0x3 128 cycles 0x2 256 cycles 0x1 512 cycles 0x0 1,024 cycles

(Default: 0x0)

Note: The OSC3 oscillation start time depends on the oscillator and externally connected compo-

nents. The time should be set with an adequate oscillation stabilization wait time. Refer to the typical oscillation start times specified in “24 Electrical Characteristics.”

D1 OSC1EN: OSC1 Enable Bit

Permits or prohibits OSC1 oscillator circuit operation. 1 (R/W): Permitted (on) (default) 0 (R/W): Prohibited (off)

Note: • The OSC1 oscillator circuit cannot be stopped if the OSC1 clock is being used as the sys-

tem clock.

• The OSC1 clock is not fed to the system for 256 cycles to prevent malfunctions immediately after OSC1 oscillation is started by changing the OSC1EN setting from 0 to 1.

D0 OSC3EN: OSC3 Enable Bit

Permits or prohibits OSC3 oscillator circuit operation. 1 (R/W): Permitted (on) (default) 0 (R/W): Prohibited (off)

Note: The OSC3 oscillator circuit cannot be stopped if the OSC3 clock is being used as the system

clock.

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0x5062: Noise Filter Enable Register (OSC_NFEN)

Noise Filter Enable Register (OSC_NFEN)

0x5062

D1 RSTFE: Reset Noise Filter Enable Bit

Enables or disables the RESET input noise filter. 1 (R/W): Enabled (noise filtering) (default) 0 (R/W): Disabled (bypass)

This noise filter inputs only RESET pulses of not less than 16 cycles of the system clock (OSC3 or

OSC1 clock) to the S1C17 core. Pulses having widths of less than 16 cycles are filtered out as noise. This should normally be enabled.

D0 NMIFE: NMI Noise Filter Enable Bit

Enables or disables the NMI input noise filter. 1 (R/W): Enabled (noise filtering) (default) 0 (R/W): Disabled (bypass)

This noise filter inputs only NMI pulses of not less than 16 cycles of the system clock (OSC3 or OSC1

clock) to the S1C17 core. Pulses having widths of less than 16 cycles are filtered out as noise. This should normally be enabled.

Note: The S1C17001 does not feature external NMI input pins, but the watchdog timer NMI request

signal passes through these filters.

D7–2 – reserved – – – 0 when being read.

(8 bits)

D1 RSTFE Reset noise filter enable 1 Enable 0 Disable 1 R/W D0 NMIFE NMI noise filter enable 1 Enable 0 Disable 1 R/W

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7 OSCILLATOR CIRCUIT (OSC)

0x5064: FOUT Control Register (OSC_FOUT)

FOUT Control Register (OSC_FOUT

0x5064

)

D[7:4] Reserved

D[3:2] FOUT3D[1:0]: FOUT3 Clock Division Ratio Select Bits

Select the OSC3 clock division ratio to set the FOUT3 clock frequency.

D1 FOUT3E: FOUT3 Output Enable Bit

Permits or prohibits FOUT3 clock (OSC3 division clock) external output. 1 (R/W): Permitted (on) 0 (R/W): Prohibited (off) (default)

D7–4 – reserved – – – 0 when being read.

(8 bits)

FOUT3D[1:0]

D3–2

D1 FOUT3E FOUT3 output enable 1 Enable 0 Disable 0 R/W D0 FOUT1E FOUT1 output enable 1 Enable 0 Disable 0 R/W

FOUT3 clock division ratio select FOUT3D[1:0] Division ratio 0x0 R/W

0x3 0x2 0x1 0x0

reserved OSC3-1/4 OSC3-1/2 OSC3-1/1

Table 7.8.3: FOUT3 clock division ratio selection

FOUT3D[1:0] Division ratio

0x3 Reserved 0x2 OSC3-1/4 0x1 OSC3-1/2 0x0 OSC3-1/1

(Default: 0x0)

Setting FOUT3E to 1 outputs the FOUT3 clock from the FOUT3 pin. Setting it to 0 stops the output. The FOUT3 output pin is combined with the P30 port. This functions as the P30 port pin by default, so

the pin function should be changed by writing 1 to P30MUX (D0/P3_PMUX register) if use is required for FOUT3 output.

∗ P30MUX: P30 Port Function Select Bit in the P3 Port Function Select (P3_PMUX) Register

(D0/0x52a3)

D0 FOUT1E: FOUT1 Output Enable Bit

Permits or prohibits FOUT1 clock (OSC1 clock) external output. 1 (R/W): Permitted (on) 0 (R/W): Prohibited (off) (default)

Setting FOUT1E to 1 outputs the FOUT1 clock from the FOUT1 pin. Setting it to 0 stops the output. The FOUT1 output pin is combined with the P13 port. This functions as the P13 port pin by default, so

the pin function should be changed by writing 1 to P13MUX (D3/P1_PMUX register) if use is required for FOUT1 output.

∗ P13MUX: P13 Port Function Select Bit in the P1 Port Function Select (P1_PMUX) Register

(D3/0x52a1)

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7 OSCILLATOR CIRCUIT (OSC)

0x5065: T8OSC1 Clock Control Register (OSC_T8OSC1)

T8OSC1 Clock Control Register (OSC_T8OSC1

0x5065

)

D[7:4] Reserved

D[3:1] T8O1CK[2:0]: T8OSC1 Clock Division Ratio Select Bits

Select the OSC1 clock division ratio and set the 8-bit OSC1 timer operation clock.

D0 T8O1CE: T8OSC1 Clock Output Enable Bit

Permits or prohibits clock feed to the 8-bit OSC1 timer. 1 (R/W): Permitted (on) 0 (R/W): Prohibited (off) (default)

D7–4 – reserved – – – 0 when being read.

(8 bits)

T8O1CK[2:0]

D3–1

D0 T8O1CE T8OSC1 clock output enable 1 Enable 0 Disable 0 R/W

T8OSC1 clock division ratio select T8O1CK[2:0] Division ratio 0x0 R/W

0x7–0x6

0x5 0x4 0x3 0x2 0x1 0x0

reserved OSC1-1/32 OSC1-1/16

OSC1-1/8 OSC1-1/4 OSC1-1/2 OSC1-1/1

Table 7.8.4: T8OSC1 clock division ratio selection

T8O1CK[2:0] Division ratio

0x7 to 0x6 Reserved

0x5 OSC1-1/32 0x4 OSC1-1/16 0x3 OSC1-1/8 0x2 OSC1-1/4 0x1 OSC1-1/2 0x0 OSC1-1/1

(Default: 0x0)

The T8O1CE default setting is 0, which stops the clock feed. Setting T8O1CE to 1 sends the clock

selected by the above bit to the 8-bit OSC1 timer. Stop the clock feed to reduce power consumption if 8-bit OSC1 timer operation is not required.

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7 OSCILLATOR CIRCUIT (OSC)

7.9 Precautions

• The OSC3 oscillation start time depends on the oscillator and externally connected components. The time should be set with an adequate OSC3 oscillation stabilization wait time. Refer to the typical oscillation start times specified in “24 Electrical Characteristics.”

• Switching the system clock from OSC3 to OSC1 immediately after starting OSC1 oscillation will stop the system clock until the OSC1 clock starts up (for the OSC1 clock 256-cycle period).

• The OSC3 oscillator circuit cannot be stopped if the OSC3 clock is being used as the system clock.

• The OSC1 oscillator circuit cannot be stopped if the OSC1 clock is being used as the system clock.

• Since the FOUT3/FOUT1 signal is asynchronized with FOUT3E/FOUT1E writing, switching output on or off will generate certain hazards.

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8 CLOCK GENERATOR (CLG)

8. Clock Generator (CLG)

8.1 Clock Generator Configuration

The clock generator controls the system clock feed to the S1C17 core and peripheral modules. Figure 8.1.1 illustrates the clock system and CLG module configuration.

CLG

HALT

CCLK

BCLK

HALT

PCLK

PSC

CLK_256Hz

OSC3

OSC4

FOUT3

OSC1

OSC2

FOUT1

RESET

NMI

SLEEP, on/off control

OSC3 oscillator circuit (8.2 MHz)

FOUT3 output circuit

On/off control

SLEEP, on/off control

OSC1 oscillator circuit (32.768 kHz)

FOUT1 output circuit

On/off control

Noise filter

On/off control

Noise filter

On/off control

wakeup

Wait circuit for wakeup

Division circuit (1/1 to 1/4)

Division ratio selection

S1C17 core

OSC

Clock source

OSC3

OSC1

selection

System clock

OSC1

Division ratio selection On/off control

Clock gear (1/1 to 1/8)

Gate

Division circuit

(1/1 to 1/32)

Gear selection

On/off control

(1/128)

Gate

Figure 8.1.1: CLG module configuration

Gate S1C17 core

Gate

Division circuit (1/1 to 1/16K)

Internal bus, RAM, ROM

ITC, T16, T8F, UART, SPI, I2C, T16E, P, MISC, REMC, Control register (CT, SWT, WDT, T8OSC1)

T8F, T16, T16E, REMC, P, UART, SPI, I2C

CT, SWT, WDT

T8OSC1

To reduce power consumption, control the clock in conjunction with processing and use standby mode. For more information on reducing power consumption, refer to “Appendix B: Power Saving.”

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8 CLOCK GENERATOR (CLG)

8.2 CPU Core Clock (CCLK) Control

The CLG module incorporates a clock gear to slow down the system clock to send to the S1C17 core. To reduce power consumption, operate the S1C17 core with the slowest possible clock speed. The halt command can be executed to stop the clock feed from the CLG to the S1C17 core for power savings.

OSC3

OSC1

System clock

Gear selection

Cock gear (1/1 to 1/8)

Figure 8.2.1: CCLK feed system

HALT

Gate S1C17 core

CCLK

Clock gear settings

CCLKGR[1:0] (D[1:0]/CLG_CCLK register) is used to select the gear ratio to reduce system clock speeds.

∗

CCLKGR[1:0]: CCLK Clock Gear Ratio Select Bits in the CCLK Control (CLG_CCLK) Register (D[1:0]/0x5081

Table 8.2.1: CCLK gear ratio selection

CCLKGR[1:0] Gear ratio

0x3 1/8 0x2 1/4 0x1 1/2 0x0 1/1

(Default: 0x0)

Clock feed control

The CCLK clock feed is stopped by executing the halt command. Since this does not stop the system clock, pe-

ripheral modules will continue to operate.

HALT mode is cleared by resetting, NMI, or other interrupts. The CCLK feed resumes when HALT mode is

cleared.

Executing the slp command suspends system clock feed to the CLG, thereby halting the CCLK feed as well.

Clearing SLEEP mode with an external interrupt restarts the system clock feed and the CCLK feed.

For more information on system clock control, refer to “7. Oscillator Circuit (OSC).”

)

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8.3 Peripheral Module Clock (PCLK) Control

The CLG module also controls the clock feed to peripheral modules. The system clock is used unmodified for the peripheral module clock (PCLK).

8 CLOCK GENERATOR (CLG)

Internal peripheral circuits

• Prescaler

• UART

• 8-bit timer

• 16-bit timer Ch.0 to 2

• Interrupt controller

• SPI

• I2C

• P port & port MUX

• PWM & capture timer

• MISC register

• Remote controller

• Control register for the modules listed below

Clock timer Stopwatch timer Watchdog timer 8-bit OSC1 timer

OSC3

OSC1

On/off control

System clock

Figure 8.3.1: Peripheral module clock control circuit

Gate

PCLK

Clock feed control

PCLK feed is controlled by PCKEN[1:0] (D[1:0]/CLG_PCLK register).

∗ PCKEN[1:0]: PCLK Enable Bits in the PCLK Control (CLG_PCLK) Register (D[1:0]/0x5080)

Table 8.3.1: PCLK control

PCKEN[1:0] PCLK feed

0x3 Permitted (on) 0x2 Setting prohibited 0x1 Setting prohibited 0x0 Prohibited (off)

(Default: 0x3)

The default setting is 0x3, which enables the clock feed. Stop the clock feed to reduce power consumption un-

less all peripheral modules (modules listed above) within the internal peripheral circuit area need to be running.

Note: Do not set PCKEN[1:0] (D[1:0]/CLG_PCLK register) to 0x2 or 0x1, since doing so will stop the

operation of certain peripheral modules.

Peripheral modules not operating on PCLK

With the exception of control register access, the clock timer, stopwatch timer, watchdog timer, and 8-bit OSC1

timer operate using the OSC1 division clock. Stopping the PCLK prevents read/write access to/from the control register, but operation will continue.

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8 CLOCK GENERATOR (CLG)

8.4 Control Register Details

Table 8.4.1 CLG register list

Address Register name Function

0x5080 CLG_PCLK PCLK Control Register PCLK feed control 0x5081 CLG_CCLK CCLK Control Register CCLK division ratio setting

The CLG module registers are described in detail below. These are 8-bit registers.

Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.

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8 CLOCK GENERATOR (CLG)

0x5080: PCLK Control Register (CLG_PCLK)

PCLK Control Register (CLG_PCLK

0x5080

)

D[7:2] Reserved

D[1:0] PCKEN[1:0]: PCLK Enable Bits

Permit or prohibit clock (PCLK) feed to internal peripheral modules.

The PCKEN[1:0] default setting is 0x3, which enables clock feed. Stop the clock feed to reduce power

consumption if the peripheral modules listed below are not required.

Peripheral modules operated using PCLK

• Prescaler (PWM & capture timer, remote controller, P port)

• UART

• 8-bit timer

• 16-bit timer Ch.0 to 2

• Interrupt controller

• SPI

• I

• P port & port MUX

• PWM & capture timer

• MISC register

• Remote controller

D7–2 – reserved – – – 0 when being read.

(8 bits)

D1–0 PCKEN[1:0] PCLK enable PCKEN[1:0] PCLK supply 0x3 R/W

0x3 0x2 0x1 0x0

Enable Not allowed Not allowed

Disable

Table 8.4.2: PCLK control

PCKEN[1:0] PCLK feed

0x3 Permitted (on) 0x2 Setting prohibited 0x1 Setting prohibited 0x0 Prohibited (off)

(Default: 0x3)

Since the following peripheral modules are not operated using PCLK except for control register access,

PCLK is not required after setting the control register to start operations.

• Clock timer

• Stopwatch timer

• Watchdog timer

• 8-bit OSC1 timer

Note: Do not set PCKEN[1:0] to 0x2 or 0x1, since doing so will stop the operation of certain pe-

ripheral modules.

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8 CLOCK GENERATOR (CLG)

0x5081: CCLK Control Register (CLG_CCLK)

CCLK Control Register (CLG_CCLK

0x5081

)

D[7:2] Reserved

D[1:0] CCLKGR[1:0]: CCLK Clock Gear Ratio Select Bits

Select the gear ratio for reducing system clock speed and set the CCLK clock speed for operating the

S1C17 core. To reduce power consumption, operate the S1C17 core using the slowest possible clock speed.

D7–2 – reserved – – – 0 when being read.

(8 bits)

D1–0 CCLK-

GR[1:0]

CCLK clock gear ratio select CCLKGR[1:0] Gear ratio 0x0 R/W

0x3 0x2 0x1 0x0

1/8 1/4 1/2 1/1

Table 8.4.3: CCLK gear ratio selection

CCLKGR[1:0] Gear ratio

0x3 1/8 0x2 1/4 0x1 1/2 0x0 1/1

(Default: 0x0)

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8 CLOCK GENERATOR (CLG)

8.5 Precautions

(1) The default settings enable PCLK feed to peripheral modules. To reduce power consumption, stop the clock

feed if the peripheral modules listed below are not used.

Peripheral modules operated using PCLK

• Prescaler (PWM & capture timer, remote controller, P port)

• UART

• 8-bit timer

• 16-bit timer Ch.0 to 2

• Interrupt controller

• SPI

• I

• P port & port MUX

• PWM & capture timer

• MISC register

• Remote controller

Since the following peripheral modules are not operated using PCLK except for control register access, PCLK

is not required after setting the control register to start operations.

• Clock timer

• Stopwatch timer

• Watchdog timer

• 8-bit OSC1 timer

(2) Do not set PCKEN[1:0] (D[1:0]/CLG_PCLK register) to 0x2 or 0x1, since doing so will stop the operation of

certain peripheral modules.

∗ PCKEN[1:0]: PCLK Enable Bits in the PCLK Control (CLG_PCLK) Register (D[1:0]/0x5080)

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9 PRESCALER (PSC)

9. Prescaler (PSC)

9.1 Prescaler Configuration

The S1C17001 incorporates a prescaler to generate a clock for timer operations. The prescaler generates 15 different frequencies by dividing the PCLK clock fed from the clock generator into 1/1 to 1/16K. The peripheral modules to which the clock is fed include clock selection registers enabling selection of one as a count or operation clock.

8-bit timer 16-bit timer Ch.0 16-bit timer Ch.1 16-bit timer Ch.2 PWM & capture timer Remote controller P port

PCLK

Debug status

signal

PSC

1/1

1/2 1/4 1/8 1/16 1/32 1/64 1/128

1/256 1/512 1/1K 1/2K 1/4K 1/8K 1/16K

Figure 9.1.1: Prescaler

The prescaler is controlled by the PRUN bit (D0/PSC_CTL register). To operate the prescaler, write 1 to PRUN. Writing 0 to PRUN stops the prescaler. Stopping the prescaler while the timer and interface module are halted enables the current consumption to be reduced. The prescaler is stopped immediately after initial resetting.

∗ PRUN: Prescaler Run/Stop Control Bit in the Prescaler Control (PSC_CTL) Register (D0/0x4020)

UART

SPI

Note: PCLK must be fed from the clock generator to use the prescaler.

The prescaler features another control bit, PRUND (D1/PSC_CTL register), which specifies prescaler operations in Debug mode. Setting PRUND to 1 also operates the prescaler in Debug mode. Setting it to 0 stops the prescaler once the S1C17 core switches to Debug mode. Set PRUND to 1 if the timer and interface module are to be used during debugging.

∗ PRUND: Prescaler Run/Stop Setting Bit in Debug Mode in the Prescaler Control (PSC_CTL) Register (D1/0x4020)

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9 PRESCALER (PSC)

9.2 Control Register Details

Table 9.2.1: Prescaler register

Address Register name Function

0x4020 PSC_CTL Prescaler Control Register Prescaler start/stop control

The prescaler register is an 8-bit register.

Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.

0x4020: Prescaler Control Register (PSC_CTL)

Con-

0x4020

Prescaler trol Register (PSC_CTL)

D[7:2] Reserved

D1 PRUND: Prescaler Run/Stop Setting Bit for Debug Mode

Selects prescaler operations in Debug mode. 1 (R/W): Operate 0 (R/W): Stop (default)

Setting PRUND to 1 operates the prescaler even in Debug mode. Setting it to 0 stops the prescaler once

the S1C17 core switches to Debug mode. Set PRUND to 1 to use the timer and interface module during debugging.

D7–2 – reserved – – – 0 when being read.

(8 bits)

D1 PRUND Prescaler run/stop in debug mode 1 Run 0 Stop 0 R/W D0 PRUN Prescaler run/stop control 1 Run 0 Stop 0 R/W

D0 PRUN: Prescaler Run/Stop Control Bit

Starts or stops prescaler operation. 1 (R/W): Start operation 0 (R/W): Stop (default)

Write 1 to PRUN to operate the prescaler. Write 0 to PRUN to stop the prescaler. To reduce current con-

sumption, stop the prescaler if the timer and interface module are already stopped.

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9.3 Precautions

PCLK must be fed from the clock generator to use the prescaler.

9 PRESCALER (PSC)

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10 INPUT/OUTPUT PORT (P)

10 Input/Output Port (P)

10.1 Input/Output Port Configuration

The S1C17001 includes 28 input/output ports (P0[7:0], P1[7:0], P2[7:0], P3[3:0]) to allow software switching of input/output direction. These share internal peripheral module input/output pins (with certain exceptions), but pins not used for peripheral modules can be used as general purpose input/output ports. Figure 10.1.1 illustrates the input/output port configuration.

Pull-up enable

PxPUy

Input/output direction selection

PxIOy

Peripheral module I/O control

Function selection

PxyMUX

Output data

Internal data bus

PxOUTy

Peripheral module output

Peripheral module input

Figure 10.1.1: Input/output port configuration

HVDD

Pxy

VSS

The P0 and P1 ports can generate input interrupts. The P0[3:0] port can be used for key entry resets. (For more information, refer to “5.1.2 P0 Port Key Entry Reset.”)

Note: The PCLK clock must be fed from the clock generator to access the input/output port. The prescaler output clock is also needed to operate the P0 port chattering filter. Switch on

the prescaler when using this function.

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10 INPUT/OUTPUT PORT (P)

10.2 Input/Output Pin Function Selection (Port MUX)

The input/output port pins share peripheral module input/output pins (with certain exceptions). Each pin can be set for use as an input/output port or for peripheral modules via the corresponding port function selection bits for each port. Pins not used for peripheral modules can be used as general purpose input/output ports.

Table 10.2.1: Input/output pin function selection

Pin function 1

PxxMUX = 0

P00 ––– P01 ––– P02 ––– P03 ––– P04 REMI (REMC) P04MUX (D4) P0 Port Function Select (P0_PMUX) Register (0x52a0) P05 REMO (REMC) P05MUX (D5) P06/EXCL2 (T16CH2) – – – P07/EXCL1 (T16CH1) – – – P10 ––– P11 ––– P12 ––– P13 FOUT1 (OSC) P13MUX (D3) P1 Port Function Select (P1_PMUX) Register (0x52a1) P14 SDA (I2C) P14MUX (D4) P15 SCL (I2C) P15MUX (D5) P16/EXCL0 (T16CH0) – – – P17 #SPISS (SPI) P17MUX (D7) P1 Port Function Select (P1_PMUX) Register (0x52a1) P20 SDI (SPI) P20MUX (D0) P2 Port Function Select (P2_PMUX) Register (0x52a2) P21 SDO (SPI) P21MUX (D1) P22 SPICLK (SPI) P22MUX (D2) P23 SIN (UART) P23MUX (D3) P24 SOUT (UART) P24MUX (D4) P25 SCLK (UART) P25MUX (D5) P26 TOUT (T16E) P26MUX (D6) P27 EXCL3 (T16E) P27MUX (D7) P30 FOUT3 (OSC) P30MUX (D0) P3 Port Function Select (P3_PMUX) Register (0x52a3) DCLK (DBG) P31 P31MUX (D1) DST2 (DBG) P32 P32MUX (D2) DSIO (DBG) P33 P33MUX (D3)

Pin function 2

PxxMUX = 1

Port function

selection bit

Control register

Resetting the input/output port pins (Pxx) resets them to their default functions (pin function 1 in Table 10.2.1).

Pins P06, P07, and P16 can also be used as 16-bit timer external clock input pins by setting them to input mode. Note, however, that no port function selection bits are available, since they are simultaneously set to function as general purpose input ports.

For information on functions other than the input/output ports, refer to the discussion of the peripheral modules indicated in parentheses. The sections below discuss port functions with the pins set as general purpose input/output ports.

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10 INPUT/OUTPUT PORT (P)

10.3 Data Input/Output

The input/output ports permit selection of the data input/output direction for each bit using PxIO[7:0] (Px_IO register).

∗ P0IO[7:0]: P0[7:0] Port I/O Direction Select Bits in the P0 Port I/O Direction Control (P0_IO) Register (D[7:0]/0x5202) ∗ P1IO[7:0]: P1[7:0] Port I/O Direction Select Bits in the P1 Port I/O Direction Control (P1_IO) Register (D[7:0]/0x5212) ∗ P2IO[7:0]: P2[7:0] Port I/O Direction Select Bits in the P2 Port I/O Direction Control (P2_IO) Register (D[7:0]/0x5222) ∗ P3IO[3:0]: P3[3:0] Port I/O Direction Select Bits in the P3 Port I/O Direction Control (P3_IO) Register (D[3:0]/0x5232)

The input/output direction for the port selecting the peripheral module function is controlled by the peripheral module. The PxIO[7:0] setting is ignored.

Data input

When set to input mode, PxIO[7:0] is set to 0 (default). The input/output port set to input mode switches to

high-impedance state, and functions as the input port. If pull-up is enabled by the Px_PU register, the port will be pulled up.

In input mode, the input pin state can be read out directly from PxIN[7:0] (Px_IN register). The value read will

be 1 when the input pin is at High (HV

∗ P0IN[7:0]: P0[7:0] Port Input Data Bits in the P0 Port Input Data (P0_IN) Register (D[7:0]/0x5200) ∗ P1IN[7:0]: P1[7:0] Port Input Data Bits in the P1 Port Input Data (P1_IN) Register (D[7:0]/0x5210) ∗ P2IN[7:0]: P2[7:0] Port Input Data Bits in the P2 Port Input Data (P2_IN) Register (D[7:0]/0x5220) ∗ P3IN[3:0]: P3[3:0] Port Input Data Bits in the P3 Port Input Data (P3_IN) Register (D[3:0]/0x5230)

Data output

When set to output mode, PxIO[7:0] is set to 1. The input/output port set to output mode functions as the output

port, while the port pin outputs High (HV Low (V

SS) level if written as 0. Note that the port will not be pulled up in output mode even if pull-up is en-

abled by the Px_PU register.

∗ P0OUT[7:0]: P0[7:0] Port Output Data Bits in the P0 Port Output Data (P0_OUT) Register (D[7:0]/0x5201) ∗ P1OUT[7:0]: P1[7:0] Port Output Data Bits in the P1 Port Output Data (P1_OUT) Register (D[7:0]/0x5211) ∗ P2OUT[7:0]: P2[7:0] Port Output Data Bits in the P2 Port Output Data (P2_OUT) Register (D[7:0]/0x5221) ∗ P3OUT[3:0]: P3[3:0] Port Output Data Bits in the P3 Port Output Data (P3_OUT) Register (D[3:0]/0x5231)

DD) level and 0 when it is at Low (VSS) level.

DD) level if PxOUT[7:0] (Px_OUT register) is written as 1 and outputs

Writing to PxOUT[7:0] is possible without affecting pin status, even in input mode.

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10 INPUT/OUTPUT PORT (P)

10.4 Pull-up Control

The input/output port contains a pull-up resistor, which you can choose to use or not use individually for each bit using the PxPU[7:0] (Px_PU register).

∗ P0PU[7:0]: P0[7:0] Port Pull-up Enable Bits in the P0 Port Pull-up Control (P0_PU) Register (D[7:0]/0x5203) ∗ P1PU[7:0]: P1[7:0] Port Pull-up Enable Bits in the P1 Port Pull-up Control (P1_PU) Register (D[7:0]/0x5213) ∗ P2PU[7:0]: P2[7:0] Port Pull-up Enable Bits in the P2 Port Pull-up Control (P2_PU) Register (D[7:0]/0x5223) ∗ P3PU[3:0]: P3[3:0] Port Pull-up Enable Bits in the P3 Port Pull-up Control (P3_PU) Register (D[3:0]/0x5233)

Setting PxPU[7:0] to 1 (default) enables the pull-up resistor and pulls up the port pin in input mode. It will not be pulled up if set to 0. The PxPU[7:0] setting is disabled in output mode, and the pin is not pulled up.

Input/output ports that are not used should be set with pull-up enabled. This pull-up setting is also enabled for ports for which the peripheral module function has been selected.

A delay will occur in the waveform rise-up depending on time constants such as pull-up resistance and pin load capacitance if the port pin is switched from Low level to High level by the internal pull-up resistor. An appropriate wait time must be set for the input/output port loading. The wait time set should be a value not less than that calculated from the following equation.

Wait time = R R C

IN x (CIN + load capacitance on board) x 1.6 [s] IN: pull-up resistance maximum value IN: pin capacitance maximum value

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10.5 Input Interface Level

The S1C17001 input interface level is pegged to the CMOS mute level.

10 INPUT/OUTPUT PORT (P)

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10 INPUT/OUTPUT PORT (P)

10.6 P0 Port Chattering Filter Function

The P0 port includes a chattering filter circuit for key entry, which you can select to use or not use (and for which you can select a verification time if used) individually for the four P0[3:0] and P0[7:4] ports using P0CFx[2:0] (P0_CHAT register).

∗ P0CF1[2:0]: P0[3:0] Chattering Filter Time Select Bits in the P0 Port Chattering Filter Control (P0_CHAT)

∗ P0CF2[2:0]: P0[7:4] Chattering Filter Time Select Bits in the P0 Port Chattering Filter Control (P0_CHAT)

Note: • The chattering filter verification time refers to the maximum pulse width that can be filtered.

Generating an input interrupt requires a minimum input time of the verification time and a maximum input time of twice the verification time.

Table 10.6.1: Chattering filter function settings

(Default: 0x0, *when OSC3 = 2 MHz and PCLK = OSC3)

P0CFx[2:0] Verification time *

0x7 16384/f 0x6 8192/f 0x5 4096/f 0x4 2048/f 0x3 1024/f 0x2 512/f 0x1 256/f 0x0 No verification time

PCLK (8ms) PCLK (4ms) PCLK (2ms) PCLK (1ms) PCLK (512μs) PCLK (256μs) PCLK (128μs)

(Off)

• Input interrupts will not be accepted for a transition into SLEEP mode with the chattering filter left on. The chattering filter should be set off (no verification time) before executing the slp command.

• P0 port interrupts must be blocked when P0_CHAT register (0x5208) settings are being changed. Changing the setting while interrupts are permitted may generate inadvertent P0 interrupts.

• A phenomenon may occur in which the internal signal oscillates due to the time elapsed until the signal reaches the threshold value if the input signal rise-up/drop-off time is delayed. Since input interrupts will malfunction under these conditions, the input signal riseup/drop-off time should normally be set to 25 ns or less.

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10 INPUT/OUTPUT PORT (P)

10.7 Port Input Interrupt

Ports P0 and P1 include input interrupt functions. Select which of the 16 ports are to be used for interrupts based on requirements. You can also select whether interrupts are generated for either the rising edge or falling edge of input signals. Figure 10.7.1 illustrates the port input interrupt circuit configuration.

Chattering filter

P00

P0CF1[2:0]

Interrupt edge selection

P0EDGE0

Interrupt enable

P0IE0

• • •

Interrupt flag

P0IF0

P0 port interrupt request (to ITC)

P07

P10

P17

P0CF2[2:0]

P0EDGE7

P0IE7

P1EDGE0

P1IE0

P1EDGE7

P1IE7

• • •

P0IF7

P1IF0

P1 port interrupt request (to ITC)

P1IF7

Figure 10.7.1: Port input interrupt circuit configuration

Interrupt port selection

Select the port generating an interrupt using PxIE[7:0] (Px_IMSK register).

∗ P0IE[7:0]: P0[7:0] Port Interrupt Enable Bits in the P0 Port Interrupt Mask (P0_IMSK) Register (D[7:0]/0x5205) ∗ P1IE[7:0]: P1[7:0] Port Interrupt Enable Bits in the P1 Port Interrupt Mask (P1_IMSK) Register (D[7:0]/0x5215)

Setting PxIE[7:0] to 1 enables interrupt generation by the corresponding port. Setting to 0 (default) disables in-

terrupt generation.

The interrupt controller must also be set to actually generate an interrupt. For more information on making in-

terrupt controller settings, refer to “6. Interrupt Controller (ITC).”

Interrupt edge selection

Port input interrupts can be generated at either the rising edge or falling edge of the input signal. Select the edge

used to generate interrupts using PxEDGE[7:0] (Px_EDGE register).

∗ P0EDGE[7:0]: P0[7:0] Port Interrupt Edge Select Bits in the P0 Port Interrupt Edge Select (P0_EDGE)

∗ P1EDGE[7:0]: P1[7:0] Port Interrupt Edge Select Bits in the P1 Port Interrupt Edge Select (P1_EDGE)

Setting PxEDGE[7:0] to 1 generates port input interrupts at the input signal falling edge. Setting it to 0 (default)

generates interrupts at the rising edge.

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Interrupt flags in P port module

The ITC is able to accept interrupt requests for both P0 and P1 port interrupts, and the P port module contains

interrupt flags PxIF[7:0] corresponding to the individual 16 ports to enable individual control of the 16 P0[7:0] and P1[7:0] port interrupts. Setting the corresponding PxIE[7:0] to 1 sets PxIF[7:0] to 1 at the specified edge (rising or falling edge) of the input signal. A P0 or P1 port interrupt request signal is also output to the ITC at the same time. This interrupt request signal causes the P0/P1 port interrupt flag inside the ITC to be set to 1. Meeting the ITC and S1C17 core interrupt conditions generates an interrupt.

∗ P0IF[7:0]: P0[7:0] Port Interrupt Flags in the P0 Port Interrupt Flag (P0_IFLG) Register (D[7:0]/0x5207) ∗ P1IF[7:0]: P1[7:0] Port Interrupt Flags in the P1 Port Interrupt Flag (P1_IFLG) Register (D[7:0]/0x5217)

The following processing is needed to manage the interrupt factor occurrence state using the P port module in-

terrupt flags.

1. Set the ITC P0 and P1 interrupt trigger mode to level trigger mode.

2. Reset the P port module interrupt flag PxIF[7:0] within the interrupt processing routine after the interrupt occurs (this also resets the ITC interrupt flag).

PxIF[7:0] is reset by writing as 1.

Note: To prevent generating unnecessary interrupts, reset the relevant PxIF[7:0] before permitting

interrupts for the required port using PxIE[7:0] (Px_IMSK register).

Port interrupt ITC register

A P0 or P1 port interrupt signal is output to the ITC if the port for which interrupts are permitted as previously

set detects the specified edge of an input signal.

The interrupt level and interrupt permission should be set for the ITC register in order to generate a port inter-

rupt.

Table 10.7.1 illustrates the port interrupt ITC control bits.

Table 10.7.1: ITC control bits

Port Interrupt flag Interrupt enable Interrupt level setting Trigger mode setting

P0 EIFT0 (D0/ITC_IFLG) EIEN0 (D0/ITC_EN) EILV0[2:0] (D[2:0]/ITC_ELV0) EITG0 (D4/ITC_ELV0) P1 EIFT1 (D1/ITC_IFLG) EIEN1 (D1/ITC_EN) EILV1[2:0] (D[10:8]/ITC_ELV0) EITG1 (D12/ITC_ELV0)

ITC_IFLG register (0x4300) ITC_EN register (0x4302) ITC_ELV0 register (0x4306)

The relevant ITC interrupt flag is set to 1 when the P0 or P1 port interrupt signal is activated. When the inter-

rupt enable bit corresponding to that interrupt flag is set to 1, the ITC sends an interrupt request to the S1C17 core. To block port interrupts, set the interrupt enable bit to 0. The interrupt flag is set to 1 by the P0 or P1 port interrupt signal regardless of the interrupt enable bit setting (even if set to 0).

The interrupt level setting bit sets the port interrupt level (0 to 7). The P0 port takes precedence if the same in-

terrupt level is set.

As previously mentioned, the port interrupt trigger mode setting bit must always be set to 1 (level trigger).

The S1C17 core accepts interrupts when all of the following conditions are met:

• Interrupt enable bit is set to 1

• The PSR (S1C17 core internal processor status register) IE (interrupt enable) bit is set to 1.

• The port interrupt has a higher set interrupt level than the PSR IL (interrupt level).

• No other interrupt factors having higher precedence (e.g., NMI) are present.

For more information on these interrupt control registers and procedures for when an interrupt occurs, refer to “6

Interrupt Controller (ITC).”

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Interrupt vector

The port interrupt vector numbers and vector addresses are as shown below.

Table 10.7.2: Port interrupt vectors

Port Vector number Vector address

P0 4 (0x04) 0x8010 P1 5 (0x05) 0x8014

10 INPUT/OUTPUT PORT (P)

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