Epic EI88C681, EI68C681 Datasheet

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Semiconductor, Inc.

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DESCRIPTION

The Epic Ei88C681/Ei68C681 DUART Dual Universal
Asynchronous Receiver and Transmitter is a data com­munication device that provides two fully independent full
duplex asynchronous communication channels in a
single package. The DUART is designed for use in
microprocessor based systems and may be used in a
polled or interrupt driven environment.

Two basic versions of the DUART are available, each
optimized for use with various microprocessor families:
the 88C81 for 8085/85, 8080/88, Z80, Z8000, 68XX and
65XX family based systems., and the 68C681 for 68000
family based systems. A programmable mode of the
Ei88C681 versions provides an interrupt daisy chain for
use in Z80 and Z8000 based systems. The bus inter­faces are however general enough to allow interfacing
with other microprocessors and microcontrollers. The
88C681 and 68C681 are enhanced versions of the
Signetics 2681 and the Motorola 68681, and are pin and
function compatible with those devices. Each channel of
the DUART may be independently programmed for
operating mode and data format. The operating speed of
each receiver and transmitter can beselected from baud
rate generator, from the multi-purpose on chip
counter/timer or from an external 1 x or 16 x clock.The bit
rate generator can operate directly from a crystal connect­ed across two pins or from an external clock. The ability to
independently program the operating speed of the receiv­er and transmitter of each channel makes the DUART
attractive for split-speed channel application such as clus­tered terminal systems. Both receive and transmit data is
quadruple-buffered in on-chip FIFO to minimize the risk of
receiver overrun or to reduce overhead in interrupt-drive
applications.

Ei68C681
Ei88C681

DUAL UART

FEATURES

• Full duplex, dual channel asynchronous
receiver and transmitter

• Quadruple-buffered receiver and transmitter

• Stop bits programmable in 1/16-bit increments

• Internal bit rate generator with 23 bit rates

• Independent bit rate selection for each Rx
and Tx

• Maximum bit rate: 1 x clock - 2 Mb/sec., 16
x clock- 250 Kb/sec.

• Normal, auto-echo, local loop-back and
remote loop-back modes

• Multi-function 16-bit counter/timer

• Interrupt output with 8 maskable interrupt
ing conditions

• Interrupt vector output on acknowledge

• Programmable interrupt daisy chain

• Up to 15 I/O pins (depending on package
and version)

• Multidrop mode compatible with 8051 nine­bit mode

• On-chip oscillator for crystal

• Stand-by mode to reduce operating power

• Advanced CMOS low power technology

PIN CONFIGURATION

1819202122232425262728

65432

1

4443424140

39
38
37
36
35
34
33
32
31
30
29

A3

IP0

WR•

RD•

RXDB

NC

TXDB

OP1
OP3
OP5
OP7

CE•
RESET
X2
X1/CLK•
RXDA
NC
TXDA
OP0
OP2
OP4
OP6

D1D3D5

D7

GND

NC

INTR

D6D4D2

D0

A2

IP1A2IP3A1NC

VCC

IP4/IEI

IP5/IEO

IP6/IACK

IP2

Ei88C681

4065432144434241

2818 19 20 21 22 23 24 25 26 27

39

29

30

31

32

33

34

35

36

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38

7

17

16

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10

9

8

CS

•

RESET
X2
X1/CLK

•

RXDA
NC
TXDA
OP0
OP2
OP4
OP6

A4

IP0

R/WN

DTACK

•

RXDB

NC

TXDB

OP1
OP3
OP5
OP7

D1D3D5

D7

GND

NC

INTRN

D6D4D2

D0

A3

IP1A2IP3A1NC

VCC

IP4

IP5

IACKN

IP2

Ei68C681

44-PIN PLCC 44-PIN PLCC

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A1

IP3

A2

IP1

A3
A4

IPO

R/W•

DTACK•

RxDB
TxDB

OP1
OP3
OP5
OP7

D1
D3
D5
D7

GND

VCC
IP4
IP5
IACK•
IP2
CS•
RESET•
X2
X1/CLK
RxDA
TxDA
OP0
OP2
OP4
OP6
D0
D2
D4
D6
INTR•

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40-PIN DIP

40
39
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37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A0

IP3

A1

IP1

A2
A3

IPO

WRN

RDN
RxDB
TxDB

OP1
OP3
OP5
OP7

D1
D3
D5
D7

GND

VCC
IP4/IEI
IP5/IEO
IP6/IACKN
IP2
CEN
RESET
X2
X1/CLK
RxDA
TxDA
OP0
OP2
OP4
OP6
D0
D2
D4
D6
INTRN

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40-PIN DIP

Part Numbers May Be Marked With "IMP" or "Ei."

For additional information, contact IMP, Inc. at 408.432.9100 or visit www.impweb.com

IMP, Inc. acquired Epic products on January 26, 2001. (see press release at http://www.impweb.com/PRESS/PR012601.htm)

14

Semiconductor, Inc.

Ei68C681
Ei88C681

DUAL UART

The DUART provides a flow control capability to inhibit
transmission from a remote device when the buffer of
the receiving DUART is full, thus preventing loss of
data. The DUART also provides a general purpose 16­bit counter/timer (which may also be used as a
programmable bit rate generator), a multipurpose input
port and a multipurpose output port.

BLOCK DIAGRAM

BUS BUFFER

8

D0-D7

OPERATION

CONTROL
ADDRESS

DECODE

R/W CONTROL

INTERRUPT

CONTROL

IMR

ISR
IVR

TIMING

AND

CONTROL

LOGIC

CHANNEL

TRANSMIT

LOGIC

RECEIVE

LOGIC

TxDA

RxDA

CHANNEL B
(AS ABOVE)

TxDB
RxDB

INPUT PORT

IPCR

ACR

6

4

8

IP0-IP6

OUTPUT PORT

OPCR

OPR

VCC

GND

R/W•

DT ACK•

CE•

A0-A3

RESET•

INTR•

IACK•

X1/CLK

X2

These ports can be used as general purpose I/O ports
or can be assigned specific functions such as clock
inputs or status/interrupt outputs under program control.

The Ei68C681 are fabricated using Epic’s advanced
CMOS process to provide high performance and low
power consumption.