Emerson PMPPC7448 User Manual

User’s Manual
from Emerson Network Power
Embedded Computing

™

PmPPC7448: PowerPC™-Based Processor PMC Module

September 2007

The information in this manual has been checked and is believed to be accurate and reli­able. HOWEVER, NO RESPONSIBILITY IS ASSUMED BY EMERSON NETWORK POWER,
EMBEDDED COMPUTING FOR ITS USE OR FOR ANY INACCURACIES. Specifications are sub­ject to change without notice. EMERSON DOES NOT ASSUME ANY LIABILITY ARISING OUT
OF USE OR OTHER APPLICATION OF ANY PRODUCT, CIRCUIT, OR PROGRAM DESCRIBED
HEREIN. This document does not convey any license under Emerson patents or the rights of
others.

Emerson. Consider It Solved is a trademark, and Business-Critical Continuity, Emerson Net­work Power, and the Emerson Network Power logo are trademarks and service marks of
Emerson Electric Co. © 2007 Emerson Electric Co.

Revision Level: Principal Changes: Date:

10006757-00 Original release October 2005
10006757-01 Artwork stitch, added “RoHS Compliance”,

updated memory map and monitor (version

1.4), added “Internal SRAM”

10006757-02 Added caution for front panel reset switch;

updated “Monitor” chapter and environment
variables

Copyright © 2005-2007 Emerson Electric Co. All rights reserved.

June 2006

September 2007

Regulatory Agency Warnings & Notices

!

!

The Emerson PmPPC7448 meets the requirements set forth by the Federal Communica­tions Commission (FCC) in Title 47 of the Code of Federal Regulations. The following infor­mation is provided as required by this agency.

Thi s devi ce compli es wit h part 15 of the FCC Rules. Operation is subject to the following two
conditions: (1) This device may not cause harmful interference, and (2) this device must
accept any interference received, including interference that may cause undesired opera­tion.

FCC RULES AND REGULATIONS — PART 15

This equipment has been tested and found to comply with the limits for a Class B digital
device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reason­able protection against harmful interference in a residential installation. This equipment
generates, uses and can radiate radio frequency energy and, if not installed and used in
accordance with the instructions, may cause harmful interference to radio communica­tions. However, there is no guarantee that interference will not occur in a particular installa­tion. If this equipment does cause harmful interference to radio or television reception,
which can be determined by turning the equipment off and on, the user is encouraged to
try to correct the interference by one or more of the following measures:

• Reorient or relocate the receiving antenna

• Increase the separation between the equipment and receiver

• Connect the equipment into an outlet on a circuit different from that to which the
receiver is connected

• Consult the dealer or an experienced radio/TV technician for help

Caution: Making changes or modifications to the PmPPC7448 hardware without the explicit consent

of Emerson Network Power could invalidate the user’s authority to operate this equipment.

EMC COMPLIANCE

The electromagnetic compatibility (EMC) tests used a PmPPC7448 model that includes a
front panel assembly from Emerson Network Power.

Caution: For applications where the PmPPC7448 is provided without a front panel, or where the

front panel has been removed, your system chassis/enclosure must provide the required
electromagnetic interference (EMI) shielding to maintain EMC compliance.

10006757-02 PmPPC7448 User’s Manual

i

Regulatory Agency Warnings & Notices (continued)

EC Declaration of Conformity

According to EN 45014:1998

Manufacturer’s Name: Emerson Network Power

Embedded Computing

Manufacturer’s Address: 8310 Excelsior Drive

Madison, Wisconsin 53717

Declares that the following product, in accordance with the requirements of 2004/108/EEC, EMC
Directive and 1999/5/EC, RTTE Directive and their amending directives,

Product: PowerPC™-Based Processor PMC Module

Model Name/Number: PmPPC7448/10005277-xx

has been designed and manufactured to the following specifications:

EN55022:1998 Information Technology Equipment, Radio disturbance characteristics, Limits and
methods of measurement

EN55024:1998 Information Technology Equipment, Immunity characteristics, Limits and methods
of measurement

EN300386 V.1.3.1 Electromagnetic compatibility and radio spectrum matters (ERM);
Telecommunication network equipment; EMC requirements

As manufacturer we hereby declare that the product named above has been designed to comply
with the relevant sections of the above referenced specifications. This product complies with the
essential health and safety requirements of the EMC Directive and RTTE Directive. We have an inter­nal production control system that ensures compliance between the manufactured products and
the technical documentation.

Issue date: September 26, 2007

Bill Fleury
Compliance Engineer

ii

PmPPC7448 User’s Manual 10006757-02

Contents

1Overview

Components and Features . . . . . . . . . . . 1-1

Functional Overview . . . . . . . . . . . . . . . . 1-3

Physical Memory Map . . . . . . . . . . . . . . . 1-4

Additional Information . . . . . . . . . . . . . . 1-6

Product Certification . . . . . . . . . . . . .1-6

UL Certification. . . . . . . . . . . . . . . . . .1-7

RoHS Compliance. . . . . . . . . . . . . . . .1-8

Terminology and Notation. . . . . . . .1-8

Technical References. . . . . . . . . . . . .1-8

2Setup

Electrostatic Discharge . . . . . . . . . . . . . . 2-1

PmPPC7448 Circuit Board. . . . . . . . . . . . 2-1

Connectors . . . . . . . . . . . . . . . . . . . . .2-4

LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5

Front Panel . . . . . . . . . . . . . . . . . . . . . 2-6

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

PmPPC7448 Setup . . . . . . . . . . . . . . . . . . 2-8

Power Requirements. . . . . . . . . . . . .2-9

Environmental Considerations . . . . 2-9

Installing the Module. . . . . . . . . . . .2-10

Troubleshooting. . . . . . . . . . . . . . . . . . . 2-11

Technical Support . . . . . . . . . . . . . .2-12

Product Repair . . . . . . . . . . . . . . . . .2-13

3 Central Processing Unit

Processor Reset. . . . . . . . . . . . . . . . . . . . . 3-2

Processor Initialization. . . . . . . . . . . . . . . 3-2

Hardware Implementation Dependent

0 Register. . . . . . . . . . . . . . . . . . . . . . . 3-3

Hardware Implementation Dependent

1 Register. . . . . . . . . . . . . . . . . . . . . . . 3-5

Exception Handling . . . . . . . . . . . . . . . . . 3-6

Exception Processing. . . . . . . . . . . . . . . . 3-8

Machine State Register . . . . . . . . . . . 3-8

Cache Memory . . . . . . . . . . . . . . . . . . . . 3-10

L1 Cache. . . . . . . . . . . . . . . . . . . . . . .3-10

L2 Cache. . . . . . . . . . . . . . . . . . . . . . .3-11

4 On-Card Memory
Configuration

Boot Memory Configuration. . . . . . . . . . 4-1

User Flash. . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

On-Card SDRAM . . . . . . . . . . . . . . . . . . . . .4-2

NVRAM Allocation . . . . . . . . . . . . . . . . . . .4-2

5System Controller

CPU Interface . . . . . . . . . . . . . . . . . . . . . . .5-2

CPU Interface Registers . . . . . . . . . . 5-2

Memory Interface. . . . . . . . . . . . . . . . . . . .5-2

DDR SDRAM Controller . . . . . . . . . . 5-2

Internal SRAM. . . . . . . . . . . . . . . . . . . 5-3

Device Controller Interface. . . . . . . . . . . .5-3

Device Control Registers . . . . . . . . . 5-4

Internal (IDMA) Controller . . . . . . . . . . . .5-4

Timer/Counter . . . . . . . . . . . . . . . . . . 5-4

PCI Interface . . . . . . . . . . . . . . . . . . . . . . . .5-4

PCI Configuration Space. . . . . . . . . . 5-5

PCI Subsystem Device and Vendor ID

Assignment. . . . . . . . . . . . . . . . . . . . . 5-5

PCI Read/Write. . . . . . . . . . . . . . . . . . 5-5

PCI Interface Registers . . . . . . . . . . . 5-7

PCI Bus Control Signals . . . . . . . . . . . . . . .5-7

PMC Connector Pinouts . . . . . . . . . . . . 5-10

P11 and P12 Pin Assignments . . . . 5-10

P13 and P14 Pin Assignments . . . . 5-11

PMC Connector . . . . . . . . . . . . . . . . 5-12

Doorbell Registers . . . . . . . . . . . . . . . . . 5-13

Outbound Doorbells . . . . . . . . . . . . 5-13

Inbound Doorbells. . . . . . . . . . . . . . 5-13

Monarch Functionality . . . . . . . . . . . . . 5-13

66 MHz Bus Operation. . . . . . . . . . . . . . 5-14

Watchdog Timer . . . . . . . . . . . . . . . . . . 5-14

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

6 Ethernet Interface

MV64460 Ethernet Registers. . . . . . . . . .6-1

Ethernet Address . . . . . . . . . . . . . . . . . . . .6-2

Ethernet Connection (P1). . . . . . . . . . . . .6-2

7CPLD

Reset Registers . . . . . . . . . . . . . . . . . . . . . .7-1

Reset Event Register (RER). . . . . . . . 7-1

Reset Command Register (RCR) . . . 7-1
PCI Reset Out Enable Register (ROER).
7-2

Interrupt Registers. . . . . . . . . . . . . . . . . . .7-3

Interrupt Enable Register (IER) . . . . 7-4

10006757-02 PmPPC7448 User’s Manual

iii

Contents (continued)

Interrupt Pending Register (IPR) . . . 7-4

Product ID Register (PIR). . . . . . . . . . . . . .7-5

EReady Register (ERdy) . . . . . . . . . . . . . . .7-5

Revision Registers . . . . . . . . . . . . . . . . . . .7-5

Hardware Version Register (HVR) . . 7-6

PLD Version Register (PVR) . . . . . . . 7-6

Board Configuration Registers. . . . . . . . .7-6

8 Serial Input/Output

Multi-Protocol Serial Controllers (MPSC)8-1

Serial DMA (SDMA) Channels. . . . . . . . . .8-1

Programmable Baud Rate. . . . . . . . . . . . .8-1

BRGx Configuration Register . . . . . .8-1

BRGx Tuning Register . . . . . . . . . . . .8-2

I2C Interface . . . . . . . . . . . . . . . . . . . . . . . .8-2

I/O Connection . . . . . . . . . . . . . . . . . . . . . .8-2

9 Real-Time Clock

Block Diagram. . . . . . . . . . . . . . . . . . . . . . .9-1

Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .9-1

Clock Operation . . . . . . . . . . . . . . . . . . . . .9-2

10Development Mezzanine
Card

DMC Circuit Board . . . . . . . . . . . . . . . . . 10-1

Serial Numbers . . . . . . . . . . . . . . . . .10-2

Connectors . . . . . . . . . . . . . . . . . . . . . . . 10-3

P1 Connector Pin Assignments . . . 10-3

P2 EIA-232 Interface . . . . . . . . . . . .10-6

PmPPC7448 to DMC JTAG . . . . . . . . . . 10-7

P3 JTAG/COP. . . . . . . . . . . . . . . . . . .10-7

P4 JTAG Chain Header . . . . . . . . . . .10-8

DMC Jumpers (JP1). . . . . . . . . . . . . . . . . 10-9

Jumper Setting Register . . . . . . . .10-10

Debug/Status LEDs . . . . . . . . . . . . . . . 10-10

DMC Setup. . . . . . . . . . . . . . . . . . . . . . . 10-11

Installing the DMC Card . . . . . . . .10-11

Troubleshooting. . . . . . . . . . . . . . . . . . 10-13

Technical Support . . . . . . . . . . . . .10-13

Product Repair . . . . . . . . . . . . . . . .10-13

11Monitor

Command-Line Features. . . . . . . . . . . . 11-1

Basic Operation. . . . . . . . . . . . . . . . . . . . 11-2

Power-up/Reset Sequence . . . . . . 11-2

POST Diagnostic Results . . . . . . . . 11-4

Monitor SDRAM Usage. . . . . . . . . . 11-4

Monitor Recovery and Updates . . . . . . 11-4

Recovering the Monitor . . . . . . . . . 11-4

Updating the Monitor via TFTP . . . 11-5
Restoring the PmPPC7448 Monitor

Using the KatanaQP . . . . . . . . . . . . 11-6

Resetting Environment Variables . 11-7

Accessing the Console Over Ethernet. 11-8

Monitor Command Reference . . . . . . . 11-8

Command Syntax . . . . . . . . . . . . . . 11-9

Command Help . . . . . . . . . . . . . . . . 11-9

Typographic Conventions . . . . . . . 11-9

Boot Commands . . . . . . . . . . . . . . . . . . 11-9

bootd . . . . . . . . . . . . . . . . . . . . . . . . . 11-9

bootelf. . . . . . . . . . . . . . . . . . . . . . .11-10

bootm . . . . . . . . . . . . . . . . . . . . . . .11-10

bootp . . . . . . . . . . . . . . . . . . . . . . . .11-10

bootv . . . . . . . . . . . . . . . . . . . . . . . .11-10

bootvx . . . . . . . . . . . . . . . . . . . . . . . 11-10

dhcp. . . . . . . . . . . . . . . . . . . . . . . . . 11-11

rarpboot . . . . . . . . . . . . . . . . . . . . . 11-11

tftpboot. . . . . . . . . . . . . . . . . . . . . . 11-11

Memory Commands . . . . . . . . . . . . . . 11-11

cmp . . . . . . . . . . . . . . . . . . . . . . . . . 11-11

cp . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12

find . . . . . . . . . . . . . . . . . . . . . . . . . .11-12

md . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12

mm. . . . . . . . . . . . . . . . . . . . . . . . . . 11-13

nm . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13

mw . . . . . . . . . . . . . . . . . . . . . . . . . .11-13

Flash Commands . . . . . . . . . . . . . . . . . 11-14

cp . . . . . . . . . . . . . . . . . . . . . . . . . . .11-14

erase . . . . . . . . . . . . . . . . . . . . . . . . 11-14

flinfo. . . . . . . . . . . . . . . . . . . . . . . . . 11-14

protect. . . . . . . . . . . . . . . . . . . . . . . 11-15

EEPROM/I2C Commands . . . . . . . . . . 11-15

eeprom . . . . . . . . . . . . . . . . . . . . . . 11-15

icrc32. . . . . . . . . . . . . . . . . . . . . . . .11-16

iloop. . . . . . . . . . . . . . . . . . . . . . . . .11-16

imd . . . . . . . . . . . . . . . . . . . . . . . . . .11-16

imm . . . . . . . . . . . . . . . . . . . . . . . . .11-16

imw . . . . . . . . . . . . . . . . . . . . . . . . .11-16

inm . . . . . . . . . . . . . . . . . . . . . . . . . .11-16

iprobe . . . . . . . . . . . . . . . . . . . . . . .11-16

Environment Parameter Commands 11-17

printenv. . . . . . . . . . . . . . . . . . . . . .11-17

iv

PmPPC7448 User’s Manual 10006757-02

Contents (continued)

saveenv . . . . . . . . . . . . . . . . . . . . . .11-17

setenv. . . . . . . . . . . . . . . . . . . . . . . .11-17

Test Commands . . . . . . . . . . . . . . . . . . 11-17

diags . . . . . . . . . . . . . . . . . . . . . . . . .11-18

mtest . . . . . . . . . . . . . . . . . . . . . . . .11-18

um. . . . . . . . . . . . . . . . . . . . . . . . . . .11-18

Other Commands. . . . . . . . . . . . . . . . . 11-18

autoscr . . . . . . . . . . . . . . . . . . . . . . .11-18

base . . . . . . . . . . . . . . . . . . . . . . . . .11-18

bdinfo. . . . . . . . . . . . . . . . . . . . . . . .11-18

coninfo. . . . . . . . . . . . . . . . . . . . . . .11-18

crc32. . . . . . . . . . . . . . . . . . . . . . . . .11-19

date. . . . . . . . . . . . . . . . . . . . . . . . . .11-19

echo . . . . . . . . . . . . . . . . . . . . . . . . .11-19

enumpci. . . . . . . . . . . . . . . . . . . . . .11-19

getmonver. . . . . . . . . . . . . . . . . . . .11-19

go . . . . . . . . . . . . . . . . . . . . . . . . . . .11-19

help. . . . . . . . . . . . . . . . . . . . . . . . . .11-20

iminfo. . . . . . . . . . . . . . . . . . . . . . . .11-20

isdram . . . . . . . . . . . . . . . . . . . . . . .11-20

loop . . . . . . . . . . . . . . . . . . . . . . . . . 11-20

memmap . . . . . . . . . . . . . . . . . . . . 11-20

moninit . . . . . . . . . . . . . . . . . . . . . . 11-20

pci. . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21

ping . . . . . . . . . . . . . . . . . . . . . . . . . 11-21

reset. . . . . . . . . . . . . . . . . . . . . . . . . 11-21

run . . . . . . . . . . . . . . . . . . . . . . . . . .11-21

script . . . . . . . . . . . . . . . . . . . . . . . . 11-22

showmac. . . . . . . . . . . . . . . . . . . . .11-22

showpci . . . . . . . . . . . . . . . . . . . . . . 11-22

sleep. . . . . . . . . . . . . . . . . . . . . . . . . 11-22

version. . . . . . . . . . . . . . . . . . . . . . . 11-22

Environment Variables . . . . . . . . . . . . 11-22

Troubleshooting. . . . . . . . . . . . . . . . . . 11-25

Download Formats. . . . . . . . . . . . . . . . 11-25

Binary. . . . . . . . . . . . . . . . . . . . . . . .11-25

Motorola S-Record . . . . . . . . . . . . 11-25

12Acronyms

10006757-02 PmPPC7448 User’s Manual

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(blank page)

vi

PmPPC7448 User’s Manual 10006757-02

Figures

Figure 1-1: General System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Figure 1-2: PmPPC7448 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Figure 2-1: Component Map, Top (Rev. 06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Figure 2-2: Component Map, Bottom (Rev. 06). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Figure 2-3: LED Locations, Bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Figure 2-4: Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Figure 2-5: Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Figure 2-6: Module Location on Emerson CC1000-DM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Figure 2-7: Installing the Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Figure 2-8: Serial Number and Product ID on Bottom Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

Figure 3-1: MPC7448 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Figure 5-1: MV64460 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Figure 5-2: PCI Device and Vendor ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Figure 5-3: Example PCI0 Address Map, Monarch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Figure 5-4: Example PCI0 Address Map, Non-Monarch (Default) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Figure 5-5: PCI JTAG Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

Figure 5-6: PMC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

Figure 6-1: Front Panel Ethernet Connector (P1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Figure 6-2: Ethernet Cable Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Figure 8-1: Front Panel Serial Port Connector (P2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

Figure 8-2: Serial Cable Assembly (Emerson Part Number C0007662-00) . . . . . . . . . . . . . . . . . . . 8-3

Figure 9-1: M41T00 Real-Time Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

Figure 10-1: DMC Component Maps, Top and Bottom (Revision 01) . . . . . . . . . . . . . . . . . . . . . . . 10-2

Figure 10-2: DMC P1 PCB-to-PCB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

Figure 10-3: DMC P2 Mini-USB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

Figure 10-4: PmPPC7448 to DMC JTAG Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

Figure 10-5: DMC P3 JTAG/COP Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

Figure 10-6: DMC P4 JTAG Chain Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8

Figure 10-7: DMC JP1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

Figure 10-8: DMC Location on PmPPC7448 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12

Figure 11-1: Example Monitor Start-up Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

Figure 11-2: Power-up/Reset Sequence Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

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Tables

Table 1-1: Address Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Table 1-2: Regulatory Agency Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Table 1-3: Technical References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Table 2-1: Circuit Board Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Table 2-2: Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Table 2-3: Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Table 3-1: PmPPC7448 CPU Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Table 3-2: CPU Internal Register Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Table 3-3: MPC7448 Exception Priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Table 4-1: Memory Configuration Jumper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Table 4-2: Flash Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Table 4-3: NVRAM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Table 5-1: P11/P12 Pin Assignments—32-Bit PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

Table 5-2: P13/P14 Pin Assignments—64-Bit PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

Table 6-1: Ethernet Port Address Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Table 6-2: Front Panel Ethernet Pin Assignments (P1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Table 6-3: Ethernet Cable Wiring Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Table 8-1: I2C Device Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

Table 8-2: Front Panel Serial Port Pin Assignments (P2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

Table 8-3: Serial Cable Wiring Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

Table 9-1: RTC Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

Table 10-1: DMC Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

Table 10-2: DMC P1 Connector Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

Table 10-3: DMC P2 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

Table 10-4: DMC P3 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8

Table 10-5: DMC P4 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

Table 11-1: POST Diagnostic Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

Table 11-2: Standard Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22

Table 11-3: Optional Environment Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24

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Registers

Register 3-1: MPC7448 Hardware Implementation Dependent, HID0. . . . . . . . . . . . . . . . . . . . . . . . 3-3

Register 3-2: MPC7448 Hardware Implementation Dependent, HID1. . . . . . . . . . . . . . . . . . . . . . . . 3-5

Register 3-3: CPU Machine State Register (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Register 3-4: L2 Cache Control Register (L2CR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

Register 7-1: Reset Event Register (RER) at 0xf820,0000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

Register 7-2: Reset Command Register (RCR) at 0xf820,1000. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

Register 7-3: Reset Out Enable Register (ROER) at 0xf820,e000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

Register 7-4: PmPPC7448 Interrupt Enable Register (IER) at 0xf820,2000 . . . . . . . . . . . . . . . . . . . . 7-4

Register 7-5: PmPPC7448 Interrupt Pending Register (IPR) at 0xf820,3000 . . . . . . . . . . . . . . . . . . . 7-4

Register 7-6: PmPPC7448 Product ID Register (PIR) at 0xf820,4000 . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

Register 7-7: PmPPC7448 ERdy Register (ERdy) at 0xf820,5000. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

Register 7-8: Hardware Version Register (HVR) at 0xf820,7000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

Register 7-9: PLD Version Register (PVR) at 0xf820,8000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

Register 7-10: PmPPC7448 Board Configuration 3 (BCR3) at 0xf820,c000 . . . . . . . . . . . . . . . . . . . . . 7-6

Register 7-11: PmPPC7448 Board Configuration 1 (BCR1) at 0xf820,a000 . . . . . . . . . . . . . . . . . . . . . 7-7

Register 7-12: PmPPC7448 Board Configuration 0 (BCR0) at 0xf820,9000 . . . . . . . . . . . . . . . . . . . . . 7-7

Register 10-1: DMC Jumper Setting Register at 0xf820,6000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10

Register 10-2: DMC LED Register at 0xf820,d000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10

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PmPPC7448 User’s Manual 10006757-02

Overview

The Emerson PmPPC7448 module is a Processor PCI Mezzanine Card (PPMC). It is based on
the Freescale® Semiconductor PowerPC™ MPC7448 central processor unit and provides
additional processing power for the baseboard, which must be compatible with PPMC
architecture. The PmPPC7448 module supports various memory configurations, program­mable user Flash memory, a PCI bridge/controller, three Ethernet interfaces, two serial
ports, as well as a real-time clock, and EEPROM.

COMPONENTS AND FEATURES

The following is a brief summary of the PmPPC7448 hardware components and features:

CPU: The Freescale MPC7448 RISC PowerPC microprocessor has an internal speed of up to 1.4

GHz and 166 MHz local bus speed. The MPC7448 includes 32 kilobytes separate level-one
(L1) data and instruction caches and 1 megabyte L2 cache. Standard power supply is 3.3
volts, with a configuration option for both 3.3 and 5 volts.

System Controller/PCI Bridge:

Section 1

The Marvell® MV64460 (Discovery™III) is a single-chip solution that provides one PCI-X
bus, three integrated gigabit Ethernet Medium Access Control (MAC) controllers, two­megabit integrated Synchronous Random Access Memory (SRAM), four Independent
Direct Memory Access (IDMA) engines and two XOR Direct Memory Access (DMA) engines.
The 64-bit PCI interface can operate up to 66 MHz (60X) or 133 MHz (PCI-X).

SDRAM: The PmPPC7448 includes a 32M x 72-bit Double Data Rate (DDR) Synchronous Dynamic

Random Access Memory (SDRAM) Small-Outline Dual In-line Memory Module (SO-DIMM).
Options include 256 megabytes, 512 megabytes, 1 gigabyte, and 2 gigabytes. The inter­face implements eight additional bits to permit the use of error-correcting code (ECC). The
MV64460 bridge acts as the memory controller.

Flash: The PmPPC7448 includes Flash configuration options of 32 or 64 megabytes. The

PmPPC7448 is capable of booting from either an 8-bit, 32-pin PLCC ROM socket on the
Development Mezzanine Card (DMC) or from 32-bit soldered Flash (default).

Serial I/O: The PmPPC7448 includes up to two EIA-232 ports operating between 9600 and 115,200

baud. Serial port one is always routed to the Development Mezzanine Card (DMC) serial
connector; build options include connections to the front panel serial connector, or the P14
connector. When routed to P14, the port has the option of either EIA-232 or TTL signaling
levels. Serial port two is routed to P14 with the same signaling options.

Ethernet: The PmPPC7448 includes three Ethernet ports. Two Broadcom BCM5461S gigabit PHY

devices route Ethernet (ports 0 and 1) through connector P14. The Micrel KSZ8721CL
10/100 PHY device routes Ethernet (port 2) through a mini-USB connector on the front
panel. The Broadcom and Micrel devices are IEEE 802.3-compliant.

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1-1

Overview: Components and Features

Note: GbE ports (0 and 1) are routed through the PHYs directly to connector P14. Therefore, magnetics are

required on the Rear Transition Module (RTM) or baseboard.

CPLD: The PmPPC7448 uses a Complex Programmable Logic Device (CPLD) to implement various

memory-mapped registers and to control access to the Flash, ROM socket, and enumera­tion of Monarch/non-Monarch systems.

RTC: The real-time clock is an ST®Microelectronics M41T00 Serial Access Timekeeper®.

Development Mezzanine Card (DMC):

The DMC is a custom, optional plug-on card mounted on the back of the PmPPC7448. This
card facilitates hardware and software development. See Chapter 10.

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PmPPC7448 User’s Manual 10006757-02

Overview: Functional Overview

Motorola

MPC7448

Microprocessor

Flash

32/64 MB

10/100

Magnetics

10/100

PHY

GbE
PHY

GbE

PHY

Device

CPLD

EIA-232

Tranceivers

Marvell
Config.

SEEPROM

NVRAM

SEEPROM

8 KB

ST Micro
M41T00

RTC

DDR SDRAM

256 MB, 512 MB,

1 GB, 2 GB

SROM

P11

P12

P13

P14

512 K

Socketed

Flash

COP Debug

Jumpers

PLD JTAG

LEDs (4)

Development

Mezzanine Card

(DMC)

MPX Bus

up to 166 MHz

DMC Connector

MII

Device Bus

MPP Bits

DRAM Bus

133 MHz

Mini USB

Connector

Marvell

MV64460

System

Controller

Port 2

(portdbg)

Port 1

(portb)

Port 0

(porta)

GMII

GMII

Serial1

Serial2

I2C

PCI 0

1.1 V

Supply

1.25 V

Supply

1.8 V

Supply

1.5 V

Supply

2.5 V

Supply

3.3 V

Supply

Mini-USB

P2

Mini-USB

P1

Front Panel

PCI/PCI-X 64-bit PMC

(3.3 V only)

GPIO

FUNCTIONAL OVERVIEW

The following block diagram provides a functional overview for the PmPPC7448:

Figure 1-1: General System Block Diagram

10006757-02 PmPPC7448 User’s Manual

1-3

8000,0000

C000,0000

F810,0000

E800,0000

F800,0000

E9FF,FFFF

EBFF,FFFF

F820,0000

F830,0000

FFFF,FFFF

Hex Address

0000,0000

PCI 0

Memory

I/O

MV64460

CPLD

ROM Socket

Boot Mirror

Reserved

Reserved

Flash

32 MB

Flash

64 MB

FF80,0000

Hex Address

F820,0000

Board Configuration Register 3

Reset Event Register

Reset Command Register

Interrupt Enable Register

Board Configuration Register 0

Board Configuration Register 1

DMC LED Register

PLD Version Register

Hardware Version Register

Jumper Settings Register

EREADY Register

Product ID Register

F820,1000

F820,2000

F820,4000

F820,5000

F820,6000

F820,7000

F820,8000

F820,9000

F820,A000

F820,B000

F820,C000

F820,D000

F820,E000

PCI Reset Out Enable Register

Reserved

Reserved

MV64460 SRAM

F850,0000

F854,0000

Interrupt Pending Register

F820,3000

SDRAM

256 MB

SDRAM

512 MB

SDRAM

1 GB

0FFF,FFFF

1FFF,FFFF

3FFF,FFFF

Reserved

B000,0000

Reserved

SDRAM

2 GB

Overview: Physical Memory Map

PHYSICAL MEMORY MAP

Fig. 1-1 illustrates the PmPPC7448 memory map:

Figure 1-2: PmPPC7448 Memory Map

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PmPPC7448 User’s Manual 10006757-02

Overview: Physical Memory Map

Table 1-1 summarizes the physical addresses for the PmPPC7448 and provides a reference

to more detailed information:

Table 1-1: Address Summary

Hex Physical
Address:

FF80,0000 R/W Boot Mirror –
FF80,0000 R/W Boot Mirror –
F854,0000 – Reserved –
F850,0000 MV64460 SRAM 5-3
F830,0000 – Reserved –
F820,E000 R/W PCI Reset Out Enable register 7-2
F820,D000 W DMC LED register 10-10
F820,C000 R Board Configuration register 3 (BCR3) 7-6
F820,B000 – Reserved (BCR2) –
F820,A000 R/W Board Configuration register 1 (BCR1) 7-6
F820,9000 R Board Configuration register 0 (BCR0) 7-6
F820,8000 R PLD Version register (PVR) 7-6
F820,7000 R Hardware Version register (HVR) 7-6
F820,6000 R Jumper Settings register (JSR) 10-10
F820,5000 R/W
F820,4000 R Product ID register (PIR) 7-5
F820,3000 R/W Interrupt Pending register (IPR) 7-4
F820,2000 R/W Interrupt Enable register (IER) 7-4
F820,1000 W Reset Command register (RCR) 7-2
F820,0000 R Reset Event register (RER) 7-1
F820,0000 R/W CPLD 7-1
F810,0000 R/W MV64460 5-5
F800,0000 R/W ROM Flash Socket 4-1
EBFF,FFFF – Reserved
E800,0000 R/W Flash (32 MB, 64 MB) 4-1, 11-14
C000,0000 – Reserved –
8000,0000 R/W PCI 0 — Memory and I/O Space 5-4
0000,0000 R/W SDRAM (256 MB, 512 MB, 1 GB, 2 GB) 4-2

Access
Mode: Description: See Page:

11

EReady (ERdy) register 7-5

2

–

1.If Monarch, read only; if non-Monarch, write only.

2.Depends on Flash size.

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1-5

Overview: Additional Information

ADDITIONAL INFORMATION

This section lists the PmPPC7448 hardware regulatory certifications and briefly discusses
the terminology and notation conventions used in this manual. It also lists general technical
references.

Mean time between failures (MTBF) has been calculated at 309,632 hours using Telcordia
Issue 1 Method I Case 3.

Product Certification

The PmPPC7448 hardware has been tested to comply with various safety, immunity, and
emissions requirements as specified by the Federal Communications Commission (FCC),
Industry Canada (IC), Underwriters Laboratories (UL), and the European Union Directives
(CE mark). The following table summarizes this compliance:

Table 1-2: Regulatory Agency Compliance

Type: Specification:

Safety UL60950-1, CSA C22.2 No. 60950-1-03, 1st Edition – Safety of

Information Technology Equipment, including Electrical Business
Equipment (Bi-National)

IEC60950/EN60950 – Safety of Information Technology Equipment
(Western Europe)

AS/NZS 60950– Safety Standard for Australia and New Zealand

Environmental NEBS: Telcordia GR-63 –

Section 4.1 Transportation and Storage
Section 4.3 Equipment Handling
Section 4.4.3 Office Vibration
Section 4.4.4 Transportation Vibration
Section 4.5 Airborne Contaminants

1-6

PmPPC7448 User’s Manual 10006757-02

Overview: Additional Information

Type: Specification:

EMC FCC Part 15, Class B – Title 47, Code of Federal Regulations, Radio

Note: EMC testing was performed without the front panel serial or Ethernet cables installed. These ports are for

debug purposes only. Also, EMC testing was not performed for the configuration with the taller heatsink (for
15 mm connector stackup). This configuration is designed for use on a customer’s proprietary carrier that
can support 15 mm PCI mezzanine cards. It is the customer’s responsibility to test this PmPPC7448 configu­ration in their system.

Emerson maintains test reports that provide specific information regarding the methods
and equipment used in compliance testing. Unshielded external I/O cables, loose screws, or
a poorly grounded chassis may adversely affect the PmPPC7448 hardware’s ability to com­ply with any of the stated specifications.

Frequency Devices

ICES 003, Class B – Industry Canada Interference-causing Equipment
Standard for Digital Apparatus, Radiated and Conducted Emissions

NEBS: Telcordia GR-1089 level 3 – Emissions and Immunity (circuit pack
level testing only)

AS/NZS 3548 003, Class A – Standard for radiated and conducted
emissions for Australia and New Zealand

EN55022, Class B – Information Technology Equipment, Radio
Disturbance Characteristics, Limits and Methods of Measurement

EN55024 – Information Technology Equipment, Immunity
Characteristics, Limits and Methods of Measurement

EN300386-2 – Electromagnetic Compatibility and Radio Spectrum
Matters (ERM); Telecommunication Network Equipment;
Electromagnetic Compatibility (EMC) Requirements

VCCI, Class 2 – Radiated and Conducted Emissions (Japan)

UL Certification

The UL web site at ul.com has a list of Emerson’s UL certifications.

1 To find the list, search in the online certifications directory using Emerson’s UL file number,

E190079.

2 There is a list for products distributed in the United States, as well as a list for products

shipped to Canada. To find the PmPPC7448, search in the list for the model name and/or
number. The PmPPC7448 is a Processor PCI Mezzanine Card (PPMC). The model number is
PmPPC7448’s Printed Circuit Board (PCB) artwork number, which is 10005277-xx (xx
changes with each artwork revision).

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1-7

Overview: Additional Information

RoHS Compliance

The PmPPC7448 is compliant with the European Union’s RoHS (Restriction of Use of Haz­ardous Substances) directive created to limit harm to the environment and human health
by restricting the use of harmful substances in electrical and electronic equipment. Effec­tive July 1, 2006, RoHS restricts the use of six substances: cadmium (Cd), mercury (Hg),
hexavalent chromium (Cr (VI)), polybrominated biphenyls (PBBs), polybrominated diphe­nyl ethers (PBDEs) and lead (Pb). Configurations that are RoHS compliant are built with
lead-free solder. Configurations that are 5-of-6 are built with tin-lead solder per the lead-in­solder RoHS exemption.

To obtain a certificate of conformity (CoC) for the PmPPC7448, send an e-mail to
[e-mail] or call 1-800-356-9602. Have the part number(s) (e.g., C000####­##) for your configuration(s) available when contacting Emerson.

Terminology and Notation

Active low signals: An active low signal is indicated with an asterisk * after the signal name.

Byte, word: Throughout this manual byte refers to 8 bits, word refers to 16 bits, long word refers to 32

bits, and double long word refers to 64 bits.

MAC: This manual uses the acronym MAC to refer to both a medium access control address and

the media-specific access control protocol within IEEE 802 specifications.

PLD: This manual uses the acronym PLD as a generic term for programmable logic device (also

known as FPGA, CPLD, EPLD, etc.).

Radix 2 and 16: Hexadecimal numbers either end with a subscript 16 or begin with 0x. Binary numbers are

shown with a subscript 2.

Technical References

Further information on basic operation and programming of the PmPPC7448 components
can be found in the following documents:

Table 1-3: Technical References

Device / Interface: Document:

CPU MPC7450 RISC Microprocessor Family User’s Manual

System controller/
PCI bridge

1-8

PmPPC7448 User’s Manual 10006757-02

3

(Freescale Semiconductor MPC7450UM Rev. 4.2 10/2004)
http://www.freescale.com

Discovery™ III PowerPC
(Marvell, MV64460-001 9/03)

http://www.marvell.com

VESA Unified Memory Architecture
http://www.vesa.org

®

System Controller MV64460 Product Brief

Overview: Additional Information

Device / Interface: Document:

Ethernet KSZ8721CL 3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer

Flash Intel

Real-Time Clock Serial Access Timekeeper

SDRAM (SO-DIMM)
Module

PCI PCI Local Bus Specification

PMC IEEE Standard for a Common Mezzanine Card (CMC) Family: IEEE Std 1386-

PPMC Processor PMC Standard for Processor PCI Mezzanine Cards: VITA 32-2003

Transceiver Data Sheet

(Micrel® Inc., Rev. 1.2, M9999-041405 April 2005)
http://www.micrel.com

BCM5461S 10/100/1000BASE-T Gigabit Ethernet Transceiver Data Sheet

(Broadcom® Corporation, 5461S-DS05-R 09/02/04)
http://www.broadcom.com

®

(Intel, Order Number: 306666 Revision: 002 August 2005)
http://www.intel.com

®

(ST

Microelectronics, July 2001)

http://www.st.com

32M X 72 Bits (256MB) 200-Pin DDR SDRAM SO-DIMM with ECC

(SimpleTech, Inc. Doc. Part Number 61000-01906-101 June 2001)
http://www.simpletech.com

(PCI Special Interest Group, Revision 2.2, December 18, 1998)

PCI-X Addendum to the PCI Local Bus Specification

(PCI Special Interest Group, Revision 1.0a, July 24, 2000)
http://www.pcisig.com

2001

(IEEE: New York, NY)

IEEE Standard for Physical and Environmental Layers for PCI Mezzanine Cards:
IEEE Std 1386.1-2001

(IEEE: New York, NY)
http://www.ieee.org

Revision 1.0a / 29 April 2003

(VITA: Scottsdale, AZ)
http://www.vita.com

3

StrataFlash® Embedded Memory (P30) Datasheet

®

M41T00

(continued)

3.Frequently, the most current information regarding addenda/errata for specific documents may be found on
the corresponding web site.

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PmPPC7448 User’s Manual 10006757-02

Setup

!

Section 2

This chapter describes the physical layout of the boards, the setup process, and how to
check for proper operation once the boards have been installed. This chapter also includes
troubleshooting, service, and warranty information.

ELECTROSTATIC DISCHARGE

Before you begin the setup process, please remember that electrostatic discharge (ESD)
can easily damage the components on the PmPPC7448 hardware. Electronic devices, espe­cially those with programmable parts, are susceptible to ESD, which can result in opera­tional failure. Unless you ground yourself properly, static charges can accumulate in your
body and cause ESD damage when you touch the board.

Caution: Use proper static protection and handle PmPPC7448 boards only when absolutely

necessary. Always wear a wriststrap to ground your body before touching a board. Keep
your body grounded while handling the board. Hold the board by its edges–do not touch
any components or circuits. When the board is not in an enclosure, store it in a static­shielding bag.

To ground yourself, wear a grounding wriststrap. Simply placing the board on top of a
static-shielding bag does not provide any protection–place it on a grounded dissipative
mat. Do not place the board on metal or other conductive surfaces.

PMPPC7448 CIRCUIT BOARD

The PmPPC7448 is a fourteen-layer circuit board that conforms to the IEEE 1386 Common
Mezzanine Card (CMC) standard. It has the following physical dimensions:

Table 2-1: Circuit Board Dimensions

Width: Depth: Height (top side): Height (bottom side):

2.913 in.
(74 mm)

5.866 in.
(149 mm)

0.323 in. (I/O area, 0.524 in.)
(8.2 mm, I/O area is 13.5 mm)

0.007 in.
(1.9 mm)

10006757-02 PmPPC7448 User’s Manual

2-1

SW1

U3

SODIMM

C15

C19

C9

C43

C28

C29

C16

C17

C31

C18

C32

C110

C199

C5

C323

C253

C46

C40

C22

C27

C36

C38

C25

C37

C51

C23

C50

C49

C47

C62

C63

C53

C52

C54 C56
C58

C60

C24

C26

C30

C33

C34

C35

C39

C41

C42

C44

C48

C294

C295

C280

C281

C286

C45

R25

R470

R471

R472

R473

R482 R483

R486

R485

R484

R487

R488

R491

R490

R489

R76

R88

R33

R34

R85

R86

R87

R89

R492

R75

R1

R19

R2

R291

R293

R30
R36

R4

R40

R5

R505

R507

R508

R510
R511

R6

R80

R81

R83

R84

R90

R91

R12

R13

R29

R7

L2

C1

R10

R11

R175

R18

R183

R24

R3

R303 R306

R307

R308

R32

R37

R38

R39

R41

R42

R43

R47

R48

R50

R504

R51

R52

R53

R54 R55

R56

R57

R58
R59

R60

R61

R62

R63

R64

R65

R66
R67

R68

R69

R70

R71

R72

R73

R78

R79

R8

R82

C55

C57

C59

C61

R20
R22
R23

R26

R27

R31

L3

L4

L5

R493

R562

C320

C321

R585

U2

U10

U11

U12
U13

U14

U15

U5 U6

U9

U7

U8

C300

R563

R564

C325

C326

RN1

RN10

RN12

RN14

RN16

RN17

RN18

RN5

RN6

RN7

RN8

RN9

RN3

RN4

RN11

RN13

RN15

RN19

RN2

U4

MV64460

System Controller

U1

MPC7447

CPU

M5 M6

P1

P11

1

2

63

64

P12

1

2

63

64

P13

1

2

63

64

P14

1

2

63

64

P2

Setup: PmPPC7448 Circuit Board

The following figures show the component maps for the PmPPC7448 circuit board.

Figure 2-1: Component Map, Top (Rev. 06)

2-2

PmPPC7448 User’s Manual 10006757-02

Setup: PmPPC7448 Circuit Board

C189

C245

C91

C249
C248

C274

C261

C263

C250

C265

C73

C251

C231

C215

C180

C247

C242

C246

C241

C232

C188

Y3

C190

L13

C20

C174

C107

C21

C185

C142 C144

C104

C76

C89

C90

C103

C84

C79

C97

C68

C85

C80

C66

C77

C101

C95

C75

C98

C81

C71

C225

C102

C86

C78

C94

C92

C96

C74

C87

C72

C93

C99

C100

C82

C88

C70

C235

C112

C83

C64

C268

C120

C278

C129

C119

C171

C111

C139

C115

C173

C184

C153

C113

C237

C269

C156

C106

C109

C167

C147

C267

C131

C130

C158

C135

C125

C116

C164

C140

C168

C141

C137

C136

C134

C133

C160

C138

C148

C151

C161

C162

C159

C117

C108

C114

C126

C163

C256

C255

C240

C266

C264

C128

C254

C221

C127

C276

C262

C238

C271

C260

C244

C270

C272

C218

C105

C275

C183

C182

C181

C194

C187

C192

C179

C176

C175

C178

C196

C177

C201

C213

C214

C209

C186

C208

C197

C210

C203

C202

C198

C216

C155

C211

C229

C154

C152

C165

C217

C205

C220

C207

C206

C204

C149

C212

C150

C169

C145

C239

C118

C121

C123

C122

C277

C124

C219

C172

C252

C279

C65

C200

C230

C227

C224

C259
C258

C273

C257

L18

C236

C243

C226

C228

C234

C233

C143

C146

C157

C166

C191

C195

C222C223

C14

C284

C29

C170

L22

C282

C299

CR22

R520

R349

R350

R351

R352

R122

R123

R337

R382

R275

R290

R295

R312

R313

R322

R323

R324

R335

R395
R407

R414

R415

R419

R420

R422

R423

R427

R428

R465

R480

R481

R500

R501

R523

R227

R229

R231

R233

R235

R244

R246

R249

R251

R255

R259

R273

R276

R277

R278

R279

R284

R285

R286

R287

R296
R301

R316

R317

R318

R320

R321

R334

R339

R342

R343

R347

R348

R360

R366

R377

R468

R469

R300

R292

R425

R426

R444

R447

R393

R440

R107

R108

R109

R110

R454

R455

R456

R457

R458

R459

R460

R461

R95

R325

R371

R298

R98

R413

R336

R330

R477

R202

R204R221

R305

R315

R326

R327

R328

R331

R370

R372

R373

R374

R384

R387

R436

R74

R105

R106

R112

R113

R114R115

R124

R125

R138

R187

R189

R192

R361

R375

R390

R400

R421

R424

R429

R448

R449

R450

R495

R506

R509 R512

R513

R516

R517

R521

R92

R93

R94

R96

R97

R99

R219

R223

R205

R238

R274

R280

R281

R282

R283

R329

R365

R443

R462

L11

L12

L14

L15

L16

L17

L19

L21

L6

L7

L8

L9

R381

R376
R379

R253

R254

R311

R314

R319

R341

R396

R399

R438

R439

R206

R222

CR14

CR15

CR16

CR21

R338

R383

R389

R111

R332

R385

R100

R102

R103

R104

R117

R118

R119

R120

R121

R127

R128

R129

R131

R132

R133

R134

R139

R140

R141

R142

R143

R144

R145

R146

R147

R148

R149

R150

R151

R152

R153

R154

R155

R156

R157

R158

R159

R162

R163

R164

R165

R167

R168

R169

R170

R171

R172

R173

R174

R176

R177

R179

R180

R182

R185

R186

R188

R190

R191

R193

R194

R195

R196

R197

R198

R199

R200

R208

R209

R210

R211

R212

R213

R256

R257

R258

R288

R289

R304

R309

R310

R333

R340

R344

R345

R346

R555

R353

R354

R355

R356

R357

R358R359

R362

R363

R364

R367

R368

R369
R378

R391

R392

R394

R397

R401

R402

R403

R404

R405

R406

R408

R433

R434

R435

R44

R441

R442

R445

R446

R45

R451

R46

R49

R494

R515

R476

R226

R294

R299

R466R467

R474

C67
C69

R475

R409

R418

C285

R502

R503

R101

R116

R136

R137

R160

R166

R203

R217

R218

R225

R228

R230

R232

R234

R236

R245

R247

R250

R252

R260

R261

R262

R263

R264

R265

R267

R268

R269

R270

R271

R297

R398

R410

R411

R412

R416

R417

R431

R432

R452

R453

R463

R464

R514

R478

R380

R388

R430

R479

R522

R518

R519

R559

R561

R524

R551

R541

R549

R552

C322

R536

R542

R545

R546

R547

C304

C305

C307

C312

C314

C315

C317

C318

C319

C324

C331

C332

C333

C334

C335

C336

C337

C338

R565

R566

R567

R568

R569

R570

R571

R572

R573

R574

R575

R576

R577

R578

R579

R580

R581

R582

R583

R584

R543

U40

U41

R526

R527

R528
R529
R530

R531

R532

R533

R538

R539

R550

R535

R537

R548

C301

C302

C308

C309

C310

C327

C328

R557

U42

R534

U36

U33

U34

U39

U29

U28

U27

U16

U26

U30

U37

U38

C297

C298

C303

C306

C311

C313

C343

U35

U24

R525

C344

C345

Y1

Y2

Y4

RN46

RN107

RN108

RN117

RN118

RN189

RN26RN27

RN30

RN41

RN51

RN52

RN53

RN55

RN57

RN58

RN61

RN63

RN64

RN84RN85

RN86

RN102

RN103

RN104

RN105

RN106

RN109

RN110

RN111

RN112

RN120

RN121

RN128

RN129

RN130

RN131

RN132

RN136

RN139RN140

RN141

RN150

RN151

RN152

RN167

RN42RN43RN44RN45

RN47RN48RN49RN50

RN79

RN80RN81

RN82RN83

RN87

RN88

RN89

RN90

RN113RN114

RN115

RN116

RN119

RN122

RN125

RN126

RN133

RN137

RN143

RN145

RN146

RN148

RN154

RN155

RN157

RN160

RN161

RN163

RN164

RN165

RN166

RN100

RN101

RN172

RN173

RN175

RN176

RN177

RN24RN25

RN29

RN40

RN54

RN56

RN59

RN60

RN62

RN65

RN66

RN67

RN68

RN69

RN70

RN71

RN72

RN73

RN74

RN75

RN76

RN77

RN78

RN91

RN92

RN93

RN94RN95

RN96RN97RN98

RN99

RN123

RN124

RN127

RN134

RN135

RN138

RN142

RN144

RN147

RN149

RN153

RN156

RN158

RN159

RN162

RN168RN169

RN170

RN171

RN178

RN187

RN188

RN20

RN21

RN28

RN31RN32RN33RN34

RN35

RN36RN37RN38RN39

U20

Flash

U31
GbE

U32
GbE

U18

PLD

M1

M2

M3

M4

R161

684-

XXXXXX

1000XXXX-XX D

R272

U19

Flash

P3

PMC-to-PMC

CR5

CR4

CR3

CR2

CR1

CR11

CR10

R544

C193

RN174

CR23

CR24

CR25

CR26

CR27

CR28

CR29

CR30

Figure 2-2: Component Map, Bottom (Rev. 06)

10006757-02 PmPPC7448 User’s Manual

2-3

Setup: PmPPC7448 Circuit Board

Connectors

The PmPPC7448 has the following connectors:

P1: This mini-USB (universal serial bus) is the connection to the front panel 10/100 PHY Ether-

net (port 2). Refer to

Table 6-2 for the pin assignments.

P2: P2 is a mini-USB connector for the front panel serial port. Refer to

Table 8-2 for the pin

assignments.

P3: This is an 80-pin PCB-to-PCB male connector on the bottom side of the PmPPC7448. P3

routes memory, CPLD, and CPU signals from the PmPPC7448 to the DMC for development
use. See

Table 10-2 for the pin assignments.

P11, P12, P13: These 64-pin connectors provide the standard 64-bit PCI interface between the

PmPPC7448 and the PMC host. See

Table 5-1 for pinouts.

P14: This 64-pin connector conforms to the PCI specification as user-defined. Ethernet signals

are also available at P14. See

Table 5-2 for pinouts.

U3: This is the socket for the small-outline, dual inline memory module (SO-DIMM). The SO-

DIMM board layout depends on the memory configuration and manufacturer.

2-4

PmPPC7448 User’s Manual 10006757-02

Setup: PmPPC7448 Circuit Board

P3-DMC

CR5

CR4

CR3

CR2

CR1

CR11

CR10

CR26

CR25

CR24

CR23

CR30

CR29

CR28

CR27

CR1-Debug LED4
CR2-Debug LED3
CR3-Debug LED2
CR4-Debug LED1
CR5-MPC7448 Check stop out

Port 2 Ethernet

(10/100BASE-TX/FX)

CR10-Link
CR11-Activity

Port 0 Ethernet

(10/100/1000BASE-T)

CR23-Activity
CR24-Link
CR25-Link1
CR26-Link2

Port 1 Ethernet

(10/100/1000BASE-T)

CR27-Activity
CR28-Link
CR29-Link1
CR30-Link2

LEDs

The PmPPC7448 has fifteen green light-emitting diodes (LEDs) on the back side of the
board (see

Figure 2-3: LED Locations, Bottom

Fig. 2-3).

10006757-02 PmPPC7448 User’s Manual

2-5

Setup: PmPPC7448 Circuit Board

!

Ethernet

Reset

Serial

P1 Ethernet connector

P2 serial connector

SW1

Front Panel

The PmPPC7448 has a single-wide PPMC front panel with an Electromagnetic Interference
(EMI) gasket.

Note: The electromagnetic compatibility (EMC) tests used a PmPPC7448 model that includes a

front panel assembly from Emerson.

Caution: For applications where the PmPPC7448 is provided without a front panel, or where the

front panel has been removed, your system chassis/enclosure must provide the required
electromagnetic interference (EMI) shielding to maintain EMC compliance.

Figure 2-4: Front Panel

2-6

PmPPC7448 User’s Manual 10006757-02

Setup: PmPPC7448 Circuit Board

!

Reset

The reset signals are routed to the CPLD, unless stated otherwise. See Chapter 7 for the
reset registers. The following sources can reset the PmPPC7448:

Power-on: This causes a hard reset to the entire board, including the PCI interfaces.

Front panel: This reset switch is accessible through a small hole in the front panel and causes a hard reset

to the entire board, including the PCI interfaces.

Caution: Use minimal force when pressing the front panel reset switch. Excessive force may damage

the switch.

PCI RESET: This causes a hard reset to the entire board, including the PCI interfaces.

COP HRESET: This reset is activated by the common on-chip processor (COP) debugger interface via a

header located on the Development Mezzanine Card (DMC). It causes a hard reset to the
entire board, including the PCI interfaces.

COP SRESET: This reset is activated by the COP debugger interface and causes a soft reset to the Frees-

cale MPC7448 and a reset to Flash.

COP TRST: This is routed directly to the MPC7448 TRST.

PMC TRST: This is routed directly to the MV64460 TRST.

Software controlled: The software controlled resets are described in the Reset Command register, Register

Map 7-2.

10006757-02 PmPPC7448 User’s Manual

2-7

Setup: PmPPC7448 Setup

CPLD

P11/P12

Ethernet

MII

(portdbg)

MV64460

PCI Bridge

CPLD_MV_64EN*

PER_AD(31:0)*

MV_SYSRST*

PCI_RST*

OSC_EN

Voltage
Monitor

ENET_RST*

DEBUG_HRESET

FLASH_RP*

MPC7448_HRESET*

Development

Mezzanine

Card

PMC_CPLD_PCI_REQ64*

MPC7448

MV_INIT_ACT

MV_WDE

Flash

PMC_CPLD_PCI_DEVSEL*

PMC_CPLD_PCI_STOP*
PMC_CPLD_PCI_TRDY*

PMC_CPLD_PCI_RST*

PMC_RESET_OUT*

POR_RST*

Voltage
Monitor

Ethernet

RGMII
(port0)

Ethernet

RGMII
(port1)

MPC7448_SRESET*

MPC7448_TRST*

DEBUG_SRESET

DEBUG_TRST

DMC_PD

DMC_BOOT_SRC

Init ROM

I2C

MV_SCL

MV_SDA

PMC_CPLD_PCI_RST_R*

Figure 2-5: Reset Diagram

2-8

PmPPC7448 User’s Manual 10006757-02

PMPPC7448 SETUP

You need the following items to set up and check the operation of the Emerson
PmPPC7448:

❐ An Emerson PmPPC7448 board

❐ A compatible host board, such as the Emerson CC1000-DM or Katana750i

❐ Card cage and power supply

❐ CRT terminal

When you unpack the board, save the antistatic bag and box for future shipping or storage.

Setup: PmPPC7448 Setup

!

Caution: Do not install the board in a rack or remove the board from a rack while power is applied, at

risk of damage to the board.

Power Requirements

Be sure your power supply is sufficient for the PmPPC7448 circuit board. Standard power is

3.3 volts, however a dual power supply option is available.
power requirements.

Table 2-2: Power Requirements

Voltage: Range:

+3.3 V +/- 5% 5.1 amps 1 GHz MPC7448 and 1 GB DDR SDRAM

Specific PmPPC7448 configurations may draw over 20 watts of power. The configurations
with a faster core CPU frequency and increased DDR memory draw more power and gener­ate more heat. When monitoring the ambient air temperature increase across the module
(from the inlet side of the PmPPC7448 to the outlet), the temperature can rise approxi­mately 4-7° C at high airflow (300 lfm) to 5-12° C at low airflow (100 lfm). The system
designer should consider the cumulative effects of installing multiple PMC modules on a
single carrier and ensure adequate airflow.

Table 2-2 lists the board’s specific

Current
(typical): Watt Requirements/Configuration:

configuration typically requires 17 watts

Environmental Considerations

As with any printed circuit board, be sure that air flow to the board is adequate. Chassis
constraints and other factors greatly affect the air flow rate. The environmental require­ments are as follows:

Table 2-3: Environmental Requirements

Environment: Range: Relative Humidity:

Operating Temperature 0° to +55° Centigrade, ambient

Storage Temperature —40° to 85° Centigrade Not to exceed 95%

Altitude 0 to 4,000 meters above sea level n/a

1

Air Flow

1. Airflow is required at the processor to maintain junction temperature less than 95° C at specified
ambient temperature.

(at board)

100 linear feet/minute @ 45° C ambient
200 linear feet/minute @ 55° C ambient

10006757-02 PmPPC7448 User’s Manual

Not to exceed 85%
(non-condensing)

(non-condensing)

n/a

2-9

Setup: PmPPC7448 Setup

PmPPC7448

(Bottomside)

PmPPC7448
(Bottomside)

J21

J22

J23

J24

J11

J12

J13

J14

J5J3J2J1

PMC 1 PMC 2

Installing the Module

Most PPMC-compatible baseboards have two sets of four connectors (J11, J12, J13, J14 and
J21, J22, J23, J24), as defined by the PMC standard P1386.1. This allows the PmPPC7448 to
be installed in either PPMC slot.
location of the PmPPC7448 modules on the baseboard.

Figure 2-6: Module Location on Emerson CC1000-DM

Fig. 2-6 shows the location of these connectors and the

2-10

Use the following procedure to attach the PmPPC7448 module to your baseboard in slot
PMC1 (see

1 Remove the screws from the standoffs on the PPMC module.

2 Hold the module at an angle and gently slide the faceplate into the opening on the

Fig. 2-7):

baseboard.

PmPPC7448 User’s Manual 10006757-02

Setup: Troubleshooting

!

PmPPC7448

P14

P13

P11

P12

Tighten these two screws first.

PMC1

PMC2

J11

J12

Reset

Serial

J14

J13

J21

J22

J23

J24

3 Align the P11 and P12 connectors and gently press the module into place until firmly

mated.

Caution: To avoid damaging the module and/or baseboard, do not force the module onto the

baseboard.

Figure 2-7: Installing the Module

4 Using four M2.5x5 mm panhead screws (Emerson part #10006275-00), secure the

PmPPC7448 module from the bottom of the baseboard. First, insert and tighten the screws
closest to the P11 through P14 connectors. Next, insert and tighten the screws nearest to
the front panel.

TROUBLESHOOTING

In case of difficulty, use this checklist:

10006757-02 PmPPC7448 User’s Manual

2-11

Setup: Troubleshooting

❐ Be sure the PmPPC7448 module is seated firmly on the PPMC host and that the PPMC

host is seated firmly in the card cage.

❐ Verify the boot jumper setting if the DMC is installed (see page 10-9).

❐ Be sure the system is not overheating.

❐ Check the cables and connectors to be certain they are secure.

❐ Check your power supply for proper DC voltages. If possible, use an oscilloscope to look

for excessive power supply ripple or noise (over 50 mV

Technical Support

If you need help resolving a problem with your PmPPC7448, visit
http://www.emersonembeddedcomputing.com/contact/postsalessupport.html on the
Internet or send e-mail to [e-mail]. If you do not have internet access, call
Emerson for further assistance:

[phone] or [phone] (US)
44-131-475-7070 (UK)

below 10 MHz).

pp

Have the following information available when contacting support:

• PmPPC7448 serial number and product identification (see

• monitor version (see

• version and part number of the operating system (if applicable). This information is
labeled on the master media supplied by Emerson or another vendor

• whether your board has been customized for options such as a higher processor speed
or additional memory

Fig. 11-1 startup display)

Fig. 2-8)

2-12

PmPPC7448 User’s Manual 10006757-02

684-

XXXXXX

00000000-00 D MMYY
PRODUCT OF XXXXX X

Serial Number

Product ID

Setup: Troubleshooting

Figure 2-8: Serial Number and Product ID on Bottom Side

Product Repair

If you plan to return the board to Emerson Network Power for service, visit
http://www.emersonembeddedcomputing.com/contact/productrepair.html on the inter­net or send e-mail to [e-mail] to obtain a Return Merchandise Authori­zation (RMA) number. We will ask you to list which items you are returning and the board
serial number, plus your purchase order number and billing information if your PmPPC7448
hardware is out of warranty. Contact our Test and Repair Services Department for any war­ranty questions. If you return the board, be sure to enclose it in an antistatic bag, such as
the one in which it was originally shipped. Send it prepaid to:

10006757-02 PmPPC7448 User’s Manual

2-13

Setup: Troubleshooting

Please put the RMA number on the outside of the package so we can handle your problem
efficiently. Our service department cannot accept material received without an RMA num­ber.

Emerson Network Power, Embedded Computing
Test and Repair Services Department
8310 Excelsior Drive
Madison, WI 53717

RMA #____________

2-14

PmPPC7448 User’s Manual 10006757-02

Central Processing Unit

This chapter is an overview of the processor logic on the PmPPC7448. It includes informa­tion on the CPU, exception handling, and cache memory. The PmPPC7448 utilizes the Free­scale MPC7448 RISC microprocessor, for more detailed information reference the Freescale
Semiconductor MPC7450 RISC Microprocessor Family User’s Manual.

The following table outlines some of the key features for the MPC7448 CPU.

Table 3-1: PmPPC7448 CPU Features

Category: MPC7448 Key Features:

Instruction Set Up to three instructions can be dispatched, four

CPU Speed (Internal) Up to 1.4 GHz
Data Bus 64-bit with 8 bits of data parity
Address Bus 36-bit with 5 bits of address parity
Seven Stage Pipeline

Control
L1 Cache 32 kilobytes instruction, 32 kilobytes data
L2 Cache 1 megabyte, eight-way set-associative unified

Execution Units Branch processing (BPU), four integer (IU), 64-bit

Memory
Management Units

Voltages Processor core, 1.0 V at 1.0 GHz or lower,

Power Management Dynamic Frequency Switching capability (divide-by-

Section 3

instructions can be fetched, 12 instructions can be in
the queue, and 16 instructions can be at some stage of
execution

Fetch, dispatch/decode, execute, complete/write
back

instruction and data cache, ECC capability

floating-point (FPU), four vector (VPU, VIU1, VIU2,
VFPU), three-stage load/store (LSU), three issue
queues (FIQ, VIQ, GIQ), rename buffers, dispatch, and
completion

52-bit virtual address, 32- or 36-bit physical address

1.15 V at 1.4 GHz

two and divide-by-four modes)

10006757-02 PmPPC7448 User’s Manual

3-1

Central Processing Unit: Processor Reset

Memory Subsystem

System Bus

Interface

1 MB L2

Cache

Controller

L1 Service

Queues

Floating

Point

Unit

Instruction MMU

Data MMU

Tags

32-KB

D Cache

Tags

32-KB

I Cache

Integer

Unit 2

Integer

Unit 1

(3)

Completion

Unit

Branch

Processing

Unit

Instruction

Queue

VR Issue GPR Issue FPR Issue

Instruction Unit

Load/Store Unit

Vector

Permute Unit

Vector Integer

Unit 2

Vector Integer

Unit 1

Vector FPU

Figure 3-1: MPC7448 Block Diagram

PROCESSOR RESET

Circuitry on the PmPPC7448 module resets the processor and the board. It activates the
RESET_OUT* signal on pin 60 of the P12 connector if the module voltages fall out of toler­ance or if the optional on-board reset switch is activated. A COP SRESET causes a soft reset

Table 3-2: CPU Internal Register Initialization

3-2

PmPPC7448 User’s Manual 10006757-02

to the processor, see the Reset Command register in Register Map 7-2.

PROCESSOR INITIALIZATION

Initially, the PmPPC7448 powers up with specific values stored in the CPU registers. The ini­tial power-up state of the Hardware Implementation Dependent register (HID0) and the
Machine State register (MSR) are given in

Register: Default After Initialization (Hex): Notes:

HID0 8000,0000 (icache and dcache off) Hardware Implementation

8000,C000 (icache and dcache on)

MSR 0000,B032 Machine State register

Table 3-2.

Dependent register
(See Register Map 3-1)

(See Register Map 3-3)

Central Processing Unit: Processor Initialization

Hardware Implementation Dependent 0 Register

The Hardware Implementation Dependent 0 (HID0) register contains bits for CPU-specific
features. Most of these bits are cleared on initial power-up of the PmPPC7448. Please refer
to the MPC7450 RISC Microprocessor Family User’s Manual for more detailed descriptions of
the HIDx registers. The following register map summarizes HID0 for the MPC7448 CPU:

Register 3-1: MPC7448 Hardware Implementation Dependent, HID0

0 4 5 6 7 8 9 10 11 12 13 14 15

BHT

reserved TBE RSTEHBENAPSLPDPMR

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

CLR

XAE NHR

ICE DCE

ILOCKDLO

CK

ICFI DCFI SPD

XBS

EN

SGE

RBTIC

LRSTKFOL

D

BHT

TBE: Time Base Enable—this bit must be set and the TBEN signal must be asserted to enable the

time base and decrementer.

STE: Software Table Search Enable—after a TLB miss, one of the three TLB miss exceptions is

taken so that software can search the page tables for the appropriate PTE.
0 Hardware table search enabled
1 Software table search enabled

HBE: High BATs Enable

0 Additional 4 IBATs (4-7) and 4 DBATs (4-7) disabled
1 Additional 4 IBATs (4-7) and 4 DBATs (4-7) enabled

NAP: Nap Mode Enable

0 Nap mode disabled
1 Nap mode enabled

SLP: Sleep Mode Enable

0 Sleep mode disabled
1 Sleep mode enabled

DPM: Dynamic Power Management Enable

0 Dynamic power management is disabled
1 Functional units enter low-power mode automatically if unit is idle

BHTCLR: Clear Branch History Table

0 The MPC7448 clears this bit one cycle after it is set
1 Setting this bit initializes all entries in BHT

NOP

DST

NOP

TI

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3-3

Central Processing Unit: Processor Initialization

XAE: Extended Addressing Enabled

0 Disabled; the 4 MSB bits of the 36-bit physical address are cleared, 32-bit physical
address is used
1 Enabled; the 32-bit effective address is translated to a 36-bit physical address

NHR: Not Hard Reset (software use only)

0 A hard reset occurred if software had previously set this bit
1 A hard reset has not occurred

ICE/DCE: Instruction and Data Cache Enable

0 Instruction and data caches are neither accessed nor updated
1 Instruction and data caches are enabled

I/DLOCK: Instruction and Data Cache Lock bits

0 Normal operation
1 All the ways of the instruction and data caches are locked

ICFI/DCFI: Instruction and Data Cache Flash Invalidate bits

0 Instruction and data caches are not invalidated
1 An invalidate operation is issued that marks the state of each instruction and data
cache block as invalid

SPD: Speculative DCache and ICache Access Disable

0 Bus accesses to nonguarded space from both caches enabled
0 Bus accesses to nonguarded space from both caches disabled

XBSEN: Extended BAT Block Size Enable

0 Disables and clears to zero IBAT[XBL] and DBAT[XBL] bits
1 Enables IBAT[XBL] and DBAT[XBL] bits

SGE: Store Gathering Enable

0Disabled
1Enabled

BTIC: Branch Target Instruction Cache Enable

0 BTIC contents are invalidated and acts as if empty
1 BTIC enables and new entries can be added

LRSTK: Link Register Stack Enable

0 Link register prediction disabled
1Allows bclr and bclrl instructions to predict the branch target address using the link reg­ister stack

FOLD: Branch Folding Enable

0Disabled
1Enabled

3-4

PmPPC7448 User’s Manual 10006757-02

Central Processing Unit: Processor Initialization

BHT: Branch History Table Enable

0Disabled
1 Allows use of dynamic prediction 2048-entry BHT

NOPDST: No-op the dst, dstt, dstst, and dststt instructions

0 Instructions enabled
1 Instructions are no-oped globally and all previously executed dst streams are cancelled

NOPTI: No-op the dcbt/dcbtst instructions

0 Instructions enabled
1 Instructions are no-oped globally

Hardware Implementation Dependent 1 Register

One of the functions of the Hardware Implementation Dependent 1 (HID1) register is to
display the state of the PLL_CFG[0:5] signals. The following register map summarizes HID1
for the MPC7448 CPU:

Register 3-2: MPC7448 Hardware Implementation Dependent, HID1

012345678910 131415

EMC

P

REBAEBD

BCL

K

ECL

R

K

PAR

DFS4DFS

2

reserved PC5 PC0

16 17 18 19 20 21 22 31

SYN

PC1 PC2 PC3 PC4

CBE

ABE

reserved

EMCP: Machine Check Signal Enable

0Disabled
1 Signal (MCP*) enabled to cause machine check errors or checkstops

EBA: Enable/disable 60x/MPX Bus Address parity checking

0Disabled
1 Allows an address bus parity error to cause a checkstop or machine check exception

EBD: Enable/disable 60x/MPX Bus Data parity checking

0Disabled
1 Allows a data bus parity error to cause a checkstop or machine check exception

BCLK/ECLK: Enable the CLK_OUT output and clock type selection:

HRESET*: HID1[ECLK]: HID1[BCLK]: CLK_OUT:

Asserted x x High impedance
Negated 0 0 Zero

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3-5

Central Processing Unit: Exception Handling

HRESET*: HID1[ECLK]: HID1[BCLK]: CLK_OUT:

Negated 0 1 Bus/2
Negated 1 0 Core
Negated 1 1 Core/2

PAR: Disable Precharge for ARTRY*, SHD0*, and SHD1* pins

0 Signals driven high when negated
1 Signals not driven high when negated

DFS4: Dynamic Frequency Switching divide-by-four mode

0Disabled
1Enabled

DFS2: Dynamic Frequency Switching divide-by-two mode

0Disabled
1Enabled

PC5: PLL Configuration bit 5 (PLL CFG[5]), read only

PC0: PLL Configuration bit 0 (PLL CFG[0]), read only

PC1: PLL Configuration bit 1 (PLL CFG[1]), read only

PC2: PLL Configuration bit 2 (PLL CFG[2]), read only

PC3: PLL Configuration bit 3 (PLL CFG[3]), read only

PC4: PLL Configuration bit 4 (PLL CFG[4]), read only

SYNCBE: Address Broadcast Enable for sync, eieio

0Disabled
1Enabled

ABE: Address Broadcast Enable for dcbf, dcbst, dcbi, icbi, tlbie, tlbsync

0 Disable address broadcasting for cache and TLB control operations
1 Enable address broadcasting for cache and TLB control operations

EXCEPTION HANDLING

Each CPU exception type transfers control to a different address in the vector table. The
vector table normally occupies the first 0x2000 bytes of RAM (with a base address of
0000,0000
may be used to point to an error routine or for code or data storage.
cessor exceptions starting with the highest priority per the following four exception classes.

Asynchronous: Nonmaskable exceptions have priority over all other exceptions. These exceptions cannot

be delayed and do not wait for completion of any precise exception handling.

) or ROM (with a base address of F800,000016). An unassigned vector position

16

Table 3-3 lists the pro-

3-6

PmPPC7448 User’s Manual 10006757-02

Central Processing Unit: Exception Handling

Instruction Fetch: Synchronous precise exceptions are taken in strict program order.

Instruction Dispatch/Execution:

Imprecise exceptions are delayed until higher priority exceptions are taken.

Post-Instruction Execution:

Maskable asynchronous exceptions are delayed until higher priority exceptions are taken.

Table 3-3: MPC7448 Exception Priorities

Priority: Exception: Notes:

Asynchronous Exceptions (Interrupts)
0 System Reset Power-on reset, assertion of HRESET* and

TRST* (hard reset)
1 Machine Check Any enabled machine check condition
2 System Reset Assertion of SRESET* (soft reset)
3 System Management

Interrupt
4 External Interrupt Assertion of INT*
5 Performance Monitor Any programmer-specific performance

6 Decrementer Decrementer passes through zero
Instruction Fetch Exceptions
0 Instruction Storage

Interrupt (ISI)
1 Instruction Translation

Lookaside Buffer (ITLB)

Miss
2 ISI Due to effective address that can not be

Instruction Dispatch/Execution Exceptions
0 Instruction Address

Breakpoint (IABR)
1 Program Trap exception, illegal or privileged instruction
2 System call (SC) Execution of system call (sc) instruction
3 Floating-Point Unavailable

(FPA)
4 AltiVec™ Unavailable Any unavailable AltiVec exception
5 Program (PI) Due to a floating-point enabled exception
6 Alignment Any alignment exception condition
7 Data Storage (DSI) Due to stvx, stvxl, lvx, or lvxl
8Alignment Due to stvx, stvxl, lvx, or lvxl

Assertion of SMI*

monitor condition

Due to no-execute segment or direct-store
(T=1) segment

Due to miss in ITLB with HID0[STEN]=1

translated, instruction fetch from guarded
memory, or protection violation

Highest priority—any instruction address
breakpoint exception condition

Any floating-point unavailable exception

10006757-02 PmPPC7448 User’s Manual

3-7

Central Processing Unit: Exception Processing

Priority: Exception: Notes: (continued)

9 Data Storage (DSI) Due to eciwx, ecowx with EAR(E)=0

10 Data Storage (DSI) Due to lwarx/stwcx
11 Data Storage (DSI) Due to BAT/page protection violation

12 Data Storage (DSI) Due to any access except cache operations to

13 Data TLB miss on store Due to store miss in DTLB with HID0[STEN]=1
14 Data TLB miss-on-load Due to load miss in DTLB with HID0[STEN]=1
15 Data Storage (DSI) Due to TLB detects page protection violation

16 Data TLB miss on store Due to HID0[STEN]=1 and the PTE changed bit

17 Data Storage (DSI) Due to DABR address match (DSISR[9])
18 AltiVec Assist Denormalized data detected as input or output

Post-Instruction Execution Exceptions
19 Trace Lowest priority—due to MSR[SE]=1

(DSISR[11])

(DSISR[4]) or lwarx/stwcx to BAT entry

SR[T]=1 (DSISR[5]) or T=0->T=1 crossing

(DSISR[4]), lwarx/stwcx to page table entry, or
hardware table search page fault (DSISR[1])

not set (C=0) for a store operation

in the AltiVec vector floating-point unit (VFPU)
while in Java mode (VSCR[NJ]=0)

(or MSR[BE]=1 for branches)

EXCEPTION PROCESSING

When an exception occurs, the address saved in Machine Status Save/Restore register 0
(SRR0) helps determine where instruction processing should resume when the exception
handler returns control to the interrupted process. Machine Status Save/Restore register 1
(SRR1) is used to save machine status on exceptions and to restore those values when an rfi
instruction is executed.

When an exception is taken, the MPC7448 controller uses SRR0 and SRR1 to save the con­tents of the Machine State register (MSR) for the current context and to identify where
instruction execution resumes after the exception is handled.

Machine State Register

The Machine State register (MSR) configures the state of the MPC7448 CPU. On initial
power-up of the PmPPC7448, most of the MSR bits are cleared. Please refer to the MPC7450
RISC Microprocessor Family User’s Manual for more detailed descriptions of the individual bit
fields.

3-8

PmPPC7448 User’s Manual 10006757-02

Central Processing Unit: Exception Processing

Register 3-3: CPU Machine State Register (MSR)

0 5 6 7 12 13 14 15

reserved VEC reserved

PO

W

RILE

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

EE PR FP ME FE0 SE BE FE1 RIPIRDRR

PM

RI LE

M

VEC: AltiVec vector unit available

0 Prevents AltiVec instructions dispatch
1Executes AltiVec instructions

POW: Power Management enable—setting this bit enables the programmable power manage-

ment modes: nap, doze, or sleep. These modes are selected in the HID0 register. This bit
has no effect on dynamic power management.
0 Power management disabled (normal operation mode)
1 Power management enabled (reduced power mode)

ILE: Exception Little-Endian mode—when an exception occurs, ILE is copied into MSR[LE] to

select the endian mode for the context established by the exception.

EE: External Interrupt enable—this bit allows the processor to take an external interrupt, system

management interrupt, or decrementer interrupt.
0 External interrupts and decrementer exception conditions delayed
1 External interrupt or decrementer exception enabled

PR: Privilege level

0 User- and supervisor-level instructions are executed
1 Only user-level instructions are executed

FP: Floating-Point available—this bit is set on initial power-up.

0 Prevents floating-point instructions dispatch (loads, stores, moves)
1 Executes floating-point instructions

ME: Machine Check enable

0 Machine check exceptions disabled
1 Machine check exceptions enabled

FE0/FE1: These bits define the Floating-Point Exception mode:

FE0: FE1: FP Exception Mode:

00Disabled
0 1 Imprecise nonrecoverable

10006757-02 PmPPC7448 User’s Manual

3-9

Central Processing Unit: Cache Memory

FE0: FE1: FP Exception Mode: (continued)

1 0 Imprecise recoverable
11Precise

SE: Single-Step Trace enable

0 Executes instructions normally
1 Single-step trace exception generated

BE: Branch Trace enable

0 Executes instructions normally
1 Branch type trace exception generated

IP: Exception Prefix

0 Places the exception vector table at the base of RAM (0000,0000
1 Places the exception vector table at the base of ROM (FFF0,0000

IR/DR: Instruction and Data address translation enables

0 Address translation disabled
1 Address translation enabled

)

16

)

16

PMM: Marks a process for the Performance Monitor

0 Process is not marked
1 Process is marked

RI: Recoverable exception enable for system reset and machine check—this feature is enabled

on initial power-up.
0 Exception is not recoverable
1 Exception is recoverable

LE: Little-endian mode enable

0 Big-endian mode (default)
1 Little-endian mode

CACHE MEMORY

L1 Cache

The MPC7448 processor implements two separate 32-kilobyte, level-one (L1) instruction
and data caches that are eight-way, set-associative. The L1 supports a four-state modi­fied/exclusive/shared/invalid (MESI) cache coherency protocol. The caches also employ
pseudo least-recently-used (PLRU) replacement algorithms within each way.

3-10

PmPPC7448 User’s Manual 10006757-02

Central Processing Unit: Cache Memory

L2 Cache

The internal 1 megabyte L2 cache is an eight-way set associative instruction and data cache
with ECC capability. The L2 cache is fully pipelined to provide 32 bytes per clock to the L1
caches. The L2 Cache Control register (L2CR) configures and operates the L2 cache. The
L2CR is read/write and contents are cleared during power-on reset.

Register 3-4: L2 Cache Control Register (L2CR)

0 1 2 9 101112 1415

L2E L2PE reserved L2I L2IO R

L2D

16 18 19 20 21 23 24 25 27 28 31

R

L2

REPL2HWF

R

LVR

AME

LVRAMM

reserved

L2E: L2 Cache enable—enables and disables the operation of the L2 cache, starting with the next

transaction.
0 Operation disabled
1Operation enabled

L2PE: L2 Data Parity Checking enable

0 L2 parity checking disabled
1 L2 parity checking enabled

L2I: L2 Global Invalidate—setting this bit invalidates the L2 cache globally by clearing the L2 sta-

tus bits.
0 Not invalidated globally
1 Invalidated globally

L2IO: L2 Instruction-Only mode—for this operation, only instruction accesses cause new entries to

be allocated in the L2 cache.
0Operation enabled
1 Operation disabled

L2DO: L2 Data-Only mode—for this operation, only data accesses cause new entries to be allocated

in the L2 cache.
0Operation enabled
1 Operation disabled

O

L2REP: L2 Replacement Algorithm

0 Pseudo-random replacement algorithm is used (default)
1 3-bit counter replacement algorithm is used

10006757-02 PmPPC7448 User’s Manual

3-11

Central Processing Unit: Cache Memory

L2HWF: L2 Hardware Flush

0Flush disabled
1 Flush enabled

LVRAME: LVRAM enable

0 LVRAM mode disabled
1LVRAM mode enabled

LVRAMM: LVRAM mode (read-only)

000 Reserved if LVRAM mode is enabled
001 Mode 1
010 Mode 2
011 Mode 3
100 Mode 4
101 Mode 5
110 Mode 6
111 Mode 7

The L2 cache is cleared following a power-on or hard reset. Before enabling the L2 cache,
configuration parameters must be set in the L2CR and the L2 tags must be globally invali­dated. Initialize the L2 cache during system start-up per the following sequence:

3-12

1 Power-on reset (automatically performed by the assertion of HRESET* signal).

2 Disable interrupts and dynamic power management (DPM).

3 Disable L2 cache by clearing L2CR[L2E].

4 Perform an L2 global invalidate.

5 Enable the L2 cache for normal operation by setting the L2CR[L2E] bit to 1.

PmPPC7448 User’s Manual 10006757-02

On-Card Memory Configuration

The PmPPC7448 includes the following memory devices:

• Up to 64 megabytes of Flash memory

• Synchronous DRAM (SDRAM) configurations up to 2 gigabytes

• Eight kilobytes of non-volatile memory

BOOT MEMORY CONFIGURATION

The PmPPC7448 boot default is the on-board Flash which occupies the physical address
space beginning at E800,0000
zanine Card (DMC) allows the 8-bit ROM socket as the boot device (see “DMC Jumpers
(JP1)” on page 10-9). Read bit 3 of Board Configuration register 1 at F820,A000

ister Map 7-11

Table 4-1: Memory Configuration Jumper

) for the boot device selection.

. Selecting jumper JP2 on the optional Development Mez-

16

(see Reg-

16

Section 4

Jumper: Function: Options: Default Configuration:

JP2 Selects monitor

boot device

The MV64460 controls the access time for ROM. The default power-up timing allows
boards of any speed to work with ROMs that have access times faster than 150 nanosec­onds. We strongly suggest that you use the default timing because of the inherent risks of
optimizing timing for a specific configuration.

USER FLASH

This configuration supports one bank of Flash memory. The PmPPC7448 circuit board
accommodates two Intel StrataFlash
64 megabytes of 32-bit wide user Flash at location E800,0000
of Flash is reserved for the monitor. The following table shows the configuration options.

Table 4-2: Flash Memory Configurations

Device
Density:

256 Mb 32 bits 1 64
128 Mb 32 bits 1 32

The Flash devices interface to the most significant data bits of the PowerPC data bus. For
example, if the data path is 64 bits wide, the PowerPC data bus is declared as D[0:63],
where D0 is the most significant bit and D63 is the least significant bit. For a 32-bit data
path, the Flash devices interface to D[0:31]. For a 16-bit path, the data bus is D[0:15].

Data Path
Width: No. of Banks:

JP2 out, User Flash
JP2 in, DMC ROM socket

™

devices (each 16 bits wide), allowing for as much as

JP2 out, User Flash

. One megabyte at the base

16

Total Memory
(Megabytes):

10006757-02 PmPPC7448 User’s Manual

4-1

On-Card Memory Configuration: On-Card SDRAM

!

If booting from user Flash, the MV64460 controller initially maps one megabyte addressing
of Flash memory (beginning at FF80,0000
Flash device is installed in the PLCC socket, it always appears at F800,0000
rored at FF80,0000

when the socket is the boot device).

16

Caution: When removing socketed PLCC devices, always use an extraction tool designed specifically

for that task. Otherwise, you risk damaging the PLCC device.

Since the 16-bit Flash device is soldered, an 8-bit ROM could be used to bootstrap the pro­cessor and execute a routine that programs the soldered Flash from a serial port, Ethernet,
or through the PCI interface.

ON-CARD SDRAM

The PmPPC7448 supports 256 megabyte, 512 megabyte, 1 gigabyte, and 2 gigabyte con­figurations of 72-bit wide SDRAM. This interface implements eight additional bits to permit
the use of error-correcting code (ECC).

A low profile, small-outline, dual inline memory module (SO-DIMM) is installed to reduce
board density and routing constraints. A serial EEPROM on the module provides the serial
presence detects (SPD). On-card SDRAM occupies physical addresses from 0000,0000
7FFF,FFFF
grammed for most memory sizes and speeds, various block sizes, and write protection.

. The SDRAM is controlled by the MV64460 DRAM controller, which may be pro-

16

) at the top of the address space. When an 8-bit

16

(and is mir-

16

16

to

In addition to the basic SDRAM control functions, the MV64460 chip provides several addi­tional DRAM-related functions and contains the following performance enhancing fea­tures:

• Supports page mode—minimizing SDRAM cycles on multiple transactions to the same
SDRAM page and can be configured to support up to 16 simultaneously opened pages.

• Supports error-correcting code (ECC) and read-modify-write (RMW) in the case of
partial writes (smaller than 64-bit) to DRAM.

• ECC provides single bit correction and two bits detection.

NVRAM ALLOCATION

The PmPPC7448 uses an eight kilobyte SROM attached to the MV64460 bridge for storing
non-volatile information such as board, monitor, and operating system configurations, as
well as information specific to user application. All Emerson-specific data is stored in the
upper two kilobytes of the device. The remainder of the device is available for user applica­tion.

Table 4-3 defines the organization of data within the SROM.

4-2

PmPPC7448 User’s Manual 10006757-02

On-Card Memory Configuration: NVRAM Allocation

Table 4-3: NVRAM Memory Map

Window Size

Address Offset (hex): Name:

0x1E14-0x1FFF Reserved 492
0x1E00-0x1E13 Test software flags 20
0x1DDC-0x1DFF Boot verify parameters 24
0x1DD8-0x1DDB Power-on self-test (POST) diagnostic results 4
0x1800-0x1DD7 Monitor configuration parameters 1508
0x1600-0x17FF Operating system 512
0x0000-0x15FF User defined 5632

(bytes):

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4-3

(blank page)

4-4

PmPPC7448 User’s Manual 10006757-02

System Controller

CPU at 166 MHz

10/100/1000

72-bit at 133 MHz

SCC, TWSI

64-bit at 133 MHz

CPU Interface
+ 2 Mb SRAM

4 DMA
2 XOR

GPIO, SCC,

TWSI, Int,

Timers

3 Ports Gb
Ethernet +

FIFO Interface

PCI-x

DDR/

FCRAM

PCI-x

Device

32-bit at 133 MHz

64-bit at 133 MHz

The Marvell MV64460 is an integrated system controller with a PCI interface and communi­cation ports for high performance embedded control applications. The MV64460 has a five
bus architecture:

• A 64-bit interface to the CPU bus

• A 64-bit interface to DDR SDRAM

• A 32-bit interface to devices

• Two 64-bit PCI/PCI-X interfaces, only PCI0 is used on the PmPPC7448

These interfaces are connected through a crossbar fabric, or central routing unit, which
enables simultaneous operation of the CPU bus, PCI device, and access to memory. The
crossbar fabric contains programmable arbitration mechanisms to optimize device perfor­mance.

The MV64460 communications unit includes the following:

Section 5

• Three Ethernet ports

• Two multi-protocol serial controllers (MPSC)

• Ten serial DMAs (SDMA)

• Two baud rate generators (BRG)

2

•I

C interface

Note: Proprietary information on the Marvell MV64460 device is not available in this user’s manual. Please refer to

the Marvell web site for available documentation, http://www.marvell.com.

Figure 5-1: MV64460 Block Diagram

10006757-02 PmPPC7448 User’s Manual

5-1

System Controller: CPU Interface

!

CPU INTERFACE

CPU interface features include:

• 32-bit address and 64-bit data buses

• Support for Symmetrical Multi-Processing (SMP) in both 60x and MPX bus modes

• Support for up to four slave devices on the same 60x bus

• 166 MHz CPU bus frequency

• CPU address remapping to the PCI

• Support for access, write, and caching protection to a configurable address range

• Support for up to 16 pipelined address transactions

CPU Interface Registers

The PmPPC7448 monitor configures the MV64460 controller so that it provides these 32­bit registers to the PowerPC processor in the correct byte order (assuming the access width
is 32 bits). The CPU setting of the CPU Configuration register affects the MV64460 behavior
on subsequent CPU accesses. This register activates with transactions pipeline disabled. In
order to gain the maximum CPU interface performance, change this default by following
these steps:

1 Read the CPU Configuration register. This guarantees that all previous transactions in the

CPU interface pipe are flushed.

2 Program the register to its new value.

3 Read polling of the register until the new data is being read.

Caution: Setting the CPU Configuration register must be done only once. For example, if the CPU

interface is configured to support Out of Order (OOO) read completion, changing the
register to not support OOO read completion is fatal.

MEMORY INTERFACE

DDR SDRAM Controller

The DDR SDRAM controller supports up to four DRAM banks. It has a 16-bit address bus
(M_DA[13:0] and M_BA[1:0]) and a 72-bit data bus (M_DQ[63:0] and M_CB7[7:0]). The
DRAM controller supports two DDR DRAM DIMMs—registered and unbuffered. Other fea­tures include:

• 64-bit wide (+ 8-bit ECC) SDRAM interface

5-2

PmPPC7448 User’s Manual 10006757-02

System Controller: Device Controller Interface

• Up to 166 MHz clock frequency

• Support for 256 megabytes to 2 gigabytes

• Up to two gigabytes address space per DRAM bank

• Supports both physical bank (M_CS[3:0]) and virtual bank (M_BA[1:0]) interleaving

The MV64460 has a number of SDRAM registers. Refer to the Marvell web site for available
documentation.

Internal SRAM

The MV64460 integrated SRAM occupies two megabits of space for general purpose mem­ory. The SRAM is cleared on reset by the monitor to initialize ECC. ECC implementation is
based on 8-bit ECC code per 64-bit of data. ECC support includes:

• Single bit error correction, two bits error detection

• Read-modify-write in case of partial write

• Single bit errors cleanup

• Single and double bit error counters

• Force bad ECC

DEVICE CONTROLLER INTERFACE

The device controller supports up to five banks of devices. Each bank’s supported memory
space can be programmed separately in one megabyte quantities, up to 512 megabytes of
address space, with a total device space of 2.5 gigabytes. Other features include:

• Dedicated 32-bit multiplexed address/data bus (separate from the SDRAM bus)

• Up to 133 MHz bus frequency

• Five chip selects, each with programmable timing

• Use as a high bandwidth interface to user specific logic

• Supports many types of standard memory devices

10006757-02 PmPPC7448 User’s Manual

5-3

System Controller: Internal (IDMA) Controller

Device Control Registers

Each bank has its own parameters register and can be programmed to 8, 16, or 32-bits
wide. The device interface consists of 128 bytes of write buffer and 128 bytes of read
buffer.

INTERNAL (IDMA) CONTROLLER

Each of the four DMA engines can move data between any source and any destination, such
as the SDRAM, device, PCI_0, or CPU bus. These engines optimize system performance by
moving large amounts of data without significant CPU intervention. Read and write are
handled independently and concurrently.

Timer/Counter

Each of the four 32-bit wide timer/counters can be selected to operate as a timer or a
counter. Each timer/counter increments with every TCLK rising edge. In counter mode, the
counter counts down to terminal count, stops, and issues an interrupt. In timer mode, the
timer counts down, issues an interrupt on terminal count, reloads itself to the programmed
value, and continues to count. Reads from the counter or timer are completed directly from
the counter, and writes are to the timer/counter register.

PCI INTERFACE

The Emerson PmPPC7448 module complies with the PCI mezzanine card (PMC) form factor
for peripheral component interconnect (PCI) modules and the specification for Processor
PCI Mezzanine Cards (PPMC). The MV64460 supports two 64-bit PCI interfaces, compliant
to the PCI Local Bus Specification revision 2.3. Only PCI0 is functional on the PmPPC7448.
Other features include:

• Support for PCI-to-PCI memory, I/O, and configuration transactions between the two
PCI interfaces

• Support for PCI-to-PCI-X bridging between the two PCI interfaces

• PCI bus speed up to 66 MHz in conventional PCI mode or up to 133 MHz in PCI-X mode

• When both PCI interfaces are functional, they operate in asynchronous clocks to each
other and to the MV64460 core clock

• 32/64-bit PCI master and target operations

5-4

PmPPC7448 User’s Manual 10006757-02

System Controller: PCI Interface

PCI Configuration Space

The PCI slave supports Type 00 configuration space header as defined in the PCI specifica­tion. The MV64460 is a multi-function device and the header is implemented in all five
functions. The PCI interface implements the configuration header and this space is accessi­ble from the CPU or PCI bus.

PCI Subsystem Device and Vendor ID Assignment

The PmPPC7448 has been assigned the following PCI identification number.

Figure 5-2: PCI Device and Vendor ID

Vendor ID: Device ID: Description:

0x1223 0x003F Reported by the PCI bridge

The PmPPC7448 sets the PCI revision ID to the hardware version number located in the
CPLD’s Hardware Version register (

PCI Read/Write

The MV64460 becomes a PCI bus master when the CPU, IDMA, gigabit Ethernet controller,
or MPSC SDMAs initiate a bus cycle to a PCI device. Conventional PCI mode allows unlimited
DMA bursts between PCI and memory. PCI-X mode supports up to four split transactions
and write combining. It supports all PCI commands including 64-bit addressing using dual
access cycles (DAC).

Register Map 7-8).

The MV64460 acts as a target when a PCI device initiates a memory access (or an I/O access
in the case of internal registers, or a P2P transaction). It responds to all memory read and
write accesses, including DAC, and to all configuration and I/O cycles in the case of internal
registers. Its internal buffers allow unlimited burst reads and writes, and can support up to
four pending delayed reads in conventional PCI mode and up to four split read transactions
in PCI-X mode.

The PCI0 address map is illustrated in Monarch mode in
in

Fig. 5-4.

Note: Fig. 5-3 is a typical example depending on the PCI system and only if another PmPPC7448 in the system rack

is the Monarch. Depending on the host, the PCI memory space may shift.

10006757-02 PmPPC7448 User’s Manual

Fig. 5-3, and in non-Monarch mode

5-5

System Controller: PCI Interface

0000,0000

8000,0000

B000,0000

B400,0000

CPU

0000,0000

8000,0000

B000,0000

PCI0 Memory

0000,0000

8000,0000

SDRAM Size

Max SDRAM Size

PCI Memory

Space

PCI0 I/O

0000,0000

0400,0000

CPU

0000,0000

8000,0000

B000,0000

B400,0000

0000,0000

B000,0000

PCI0 Memory

0000,0000

8000,0000

SDRAM Size

Max SDRAM Size

PCI Memory

Space

PCI0 I/O

0000,0000

0400,0000

PCI Memory

Space

Figure 5-3: Example PCI0 Address Map, Monarch

Figure 5-4: Example PCI0 Address Map, Non-Monarch (Default)

5-6

PmPPC7448 User’s Manual 10006757-02

System Controller: PCI Bus Control Signals

PCI Interface Registers

PCI0 and PCI1 contain the same set of internal registers, but are located at different offsets.
A CPU access to the MV64460 PCIx Configuration register is performed via the PCIx Config­uration Address and Data registers. Only PCI0 is functional on the PmPPC7448.

All PCI configuration registers are located at their standard offset in the configuration
header, as defined in the PCI specification, when accessed from their corresponding PCI
bus. For example, if a master on PCI0 performs a PCI configuration cycle on PCI’s Status and
Command register, the register is located at 0x004.

The PmPPC7448 module may generate interrupts to other PCI devices by accessing door­bell-type interrupt-generating registers or address ranges within their PCI bridges. The
module will respond to interrupts caused by another PCI device when it accesses a pro­grammable range of local memory, as provided by the MV64460 memory controller. In
addition, it may monitor the state of the PCI bus INTA*—INTD* signals routed directly to the
memory controller’s multipurpose pins (MPP). The MV64460 contains registers that con­trol the masking, unmasking, and priority of the PMC interrupts as inputs to the processor.

PCI BUS CONTROL SIGNALS

The following signals for the PCI interface are available on connectors P11, P12, and P13.
Refer to the PCI specification for details on using these signals. All signals are bi-directional
unless stated otherwise. A sustained tri-state line is driven high for one clock cycle before
float.

Note: The PmPPC7448 host board must adhere to the PCI Local Bus Specification (Revision 2.3) for terminating

JTAG signals.

ACK64*: ACKNOWLEDGE 64-bit TRANSFER This sustained three-state signal indicates the target is

willing to transfer data using 64 bits.

AD[31:00]: ADDRESS and DATA bus (bits 0-31) These three-state signals are used for both address

and data handling. A bus transaction consists of an address phase followed by one or more
data phases.

AD[63:32]: ADDRESS and DATA bus (bits 32-63) These provide 32 additional bits. During an address

phase the upper 32-bits of a 64-bit address are transferred; otherwise these bits are
reserved. During a data phase, an additional 32-bits of data are transferred when a 64-bit
transaction has been negotiated by the assertion of REQ64* and ACK64*.

C/BE[3:0]*: BUS COMMAND and BYTE ENABLES These three-state signals have different functions

depending on the phase of a transaction. During the address phase of a transaction these
lines define the bus command. During a data phase the lines are used as byte enables.

10006757-02 PmPPC7448 User’s Manual

5-7

System Controller: PCI Bus Control Signals

C/BE[7:4]*: BUS COMMAND and BYTE ENABLES During the address phase, the actual bus command is

transferred, otherwise these bits are reserved. During a data phase the lines are used as
byte enables.

CLK: CLOCK This input signal to PPMC modules provides timing for PCI transactions.

DEVSEL*: DEVICE SELECT This sustained three-state signal indicates when a device on the bus has

been selected as the target of the current access.

EREADY: READY This signal is an input for Monarch modules and an output for non-Monarch mod-

ules. It indicates that all modules are initialized and the PCI bus is ready to be enumerated.

FRAME*: CYCLE FRAME This sustained three-state signal is driven by the current master to indicate

the beginning of an access, and continues to be asserted until the transaction reaches its
final data phase.

GNT*: GRANT This three-state signal indicates that access to the bus has been granted to a par-

ticular master. Each master has its own GNT*.

IDSEL: INITIALIZATION DEVICE SELECT This input signal acts as a chip select during configuration

read and write transactions.

INTA*, INTB*, INTC*, INTD*:

PMC INTERRUPTS A, B, C, D These open drain lines are used by the PPMC module to inter­rupt the baseboard, or vice versa.

IRDY*: INITIATOR READY This sustained three-state signal indicates that the bus master is ready

to complete the data phase of the transaction.

M66EN: ENABLE 66 MHZ This signal indicates to a device whether the bus segment is operating at

66 or 33 MHz in conventional PCI.

MONARCH*: MONARCH When this signal is grounded, it indicates that the PPMC module is a Monarch

and must provide PCI bus enumeration and interrupt handling.

PAR: PARITY This is even parity across AD[31:00] and C/BE[3:0]*. Parity generation is required

by all PCI agents. This three-state signal is stable and valid one clock after the address
phase, and one clock after the bus master indicates that it is ready to complete the data
phase (either IRDY* or TRDY* is asserted). Once PAR is asserted, it remains valid until one
clock after the completion of the current data phase.

PAR64: PARITY UPPER DWORD This three-state signal is the even parity bit that protects

AD[63:32] and C/BE[7:4]*.

PERR*: PARITY ERROR This sustained three-state line is used to report data parity errors during all

PCI transactions except a Special Cycle.

5-8

PmPPC7448 User’s Manual 10006757-02

System Controller: PCI Bus Control Signals

PRESENT*: PRESENT When grounded, this input signal indicates to a carrier that a PPMC module is

installed.

RESET_OUT*: RESET OUTPUT This output signal may be used to support a reset button or other reset

source on the PPMC module. It is an open drain output from the PPMC module that
becomes an input to the reset logic on the carrier card. To avoid reset loops, do not use
RST* to generate RESET_OUT*.

REQ64*: REQUEST 64-bit TRANSFER When asserted by the current bus master, this sustained

three-state line indicates the ability to transfer data using 64 bits.

REQ*: REQUEST This three-state signal indicates to the arbiter that a particular master wants to

use the bus.

RST*: RESET The assertion of this input signal brings PCI registers, sequencers, and signals to a

consistent state. The carrier card generates this system reset signal (pull-up resistor
required) as an input to all PPMC modules.

SERR*: SYSTEMS ERROR This open-drain output signal is used to report any system error with

catastrophic results.

STOP*: STOP A sustained three-state signal used by the current target to request that the bus

master stop the current transaction.

TCK: TEST CLOCK This input signal clocks state information and test data into and out of the

device during operation of the TAP.

TDI: TEST DATA INPUT This input signal serially shifts test data and test instructions into the

device during TAP operations.

TDO: TEST DATA OUTPUT This output signal serially shifts test data and test instructions out of

the device during TAP operation.

TMS: TEST MODE SELECT This input signal controls the state of the TAP controller in the device.

TRDY*: TARGET READY A sustained three-state signal that indicates the target’s ability to com-

plete the current data phase of the transaction.

TRST*: TEST RESET This input signal provides asynchronous initialization of the TAP controller.

10006757-02 PmPPC7448 User’s Manual

5-9

System Controller: PMC Connector Pinouts

P12

MV64460

TCK

TRST*

TMS

TDI TDO

PMC_MV_TCK

PMC_MV_TMS

PMC_MV_TRST*

PMC_MV_TDI

PMC_MV_TDO

PMC_VIO

P11

PMC CONNECTOR PINOUTS

Each connector has 64 pins (see Fig. 5-6 on page 5-12).

P11 and P12 Pin Assignments

P11 and P12 support the 32-bit PCI bus connectors (see Table 5-1). Fig. 5-5 illustrates the
MV64460 JTAG signals routed from connector P12.

Figure 5-5: PCI JTAG Block Diagram

5-10

Table 5-1: P11/P12 Pin Assignments—32-Bit PCI

Pin: P11 Signal: P11 Signal: Pin: P11 Signal: P12 Signal:

1MV_TCK Not connected 2 Not connected MV_TRST*
3 GND MV_TMS 4 INTA* MV_PMC_TDO
5 INTB* MV_PMC_TDI 6 INTC* GND
7 PRESENT*/GND GND 8 +5 V
9INTD*
11 GND PUP0 (pull up) 12
13 PCI_CLK RST* 14 GND PDN0 (pull down)
15 GND +3.3 V 16 GNT* PDN1 (pull down)
17 REQ*
19 V(I/O) AD30 20 AD31 AD29
21 AD28 GND 22 AD27 AD26
23 AD25 AD24 24 GND +3.3 V
25 GND IDSEL 26 C/BE3* AD23
27 AD22 +3.3 V 28 AD21 AD20
29 AD19 AD18 30 +5 V GND
31 V(I/O) AD16 32 AD17 C/BE2*

PmPPC7448 User’s Manual 10006757-02

33 FRAME* GND 34 GND
35 GND TRDY* 36 IRDY* +3.3 V

Not connected

Not connected 10 Not connected Not connected

Not connected +3.3 V

Not connected 18 +5 V GND

Not connected

System Controller: PMC Connector Pinouts

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin: P11 Signal: P11 Signal: Pin: P11 Signal: P12 Signal:

37 DEVSEL* GND 38 +5 V STOP*
39 GND_PCIXCAP PERR* 40
41
43 PAR C/BE1* 44 GND GND
45 V(I/O) AD14 46 AD15 AD13
47 AD12 M66EN 48 AD11 AD10
49 AD9 AD8 50 +5 V +3.3 V
51 GND AD7 52 C/BE0*
53 AD6 +3.3 V 54 AD5
55 AD4
57 V(I/O)
59 AD2 GND 60 AD1 RESET_OUT*
61 AD0 ACK64* 62 +5 V +3.3 V
63 GND GND 64 REQ64* MONARCH*

P13 and P14 Pin Assignments

P13 and P14 route the 64-bit PCI, SIO, and Ethernet configuration signals to the backplane.
Eight general purpose input/output (GPIO) pins are provided on P14—these are routed
directly from the MV64460 multipurpose pins.

Table 5-2: P13/P14 Pin Assignments—64-Bit PCI

Not connected +3.3 V 42 Not connected SERR*

Not connected 56 GND GND
Not connected 58 AD3 EREADY

Not connected GND

Not connected
Not connected

Pin: P13 Signal: P14 Signal: Pin: P13 Signal: P14 Signal:

1 Not connected LPa_DA+ 2 GND LPa_DC+
3 GND LPa_DA- 4 C/BE7* LPa_DC­5 C/BE6* GND 6 C/BE5* GND
7C/BE4* LPa_DB+ 8GND LPa_DD+
9 V(I/O) LPa_DB- 10 PAR64 LPa_DD­11 AD63 GND 12 AD62 GND
13 AD61 LPb_DA+ 14 GND LPb_DC+
15 GND LPb_DA- 16 AD60 LPb_DC­17 AD59 GND 18 AD58 GND
19 AD57 LPb_DB+ 20 GND LPb_DD+
21 V(I/O) LPb_DB- 22 AD56 LPb_DD­23 AD55 GND 24 AD54 GND
25 AD53
27 GND
29 AD51
31 AD49
33 GND

Not connected 26 GND Not connected
Not connected 28 AD52 Not connected
Not connected 30 AD50 Not connected
Not connected 32 GND Not connected
Not connected 34 AD48 Not connected

10006757-02 PmPPC7448 User’s Manual

5-11

System Controller: PMC Connector Pinouts

1

2

63

64

Pin: P13 Signal: P14 Signal: Pin: P13 Signal: P14 Signal:

35 AD47
37 AD45
39 V(I/O)
41 AD43
43 AD41
45 GND
47 AD39
49 AD37 GPIO0 50 GND GPIO1
51 GND GPIO2 52 AD36 GPIO3
53 AD35 GPIO4 54 AD34 GPIO5
55 AD33 GPIO6 56 GND GPIO7
57 V(I/O)
59
61
63 GND Serial2 TxD 64

Not connected Not connected 60 Not connected Not connected
Not connected Serial1 TxD 62 GND Serial1 RxD

The following signals for the PCI interface are available on connector P14.

Not connected 36 AD46 Not connected
Not connected 38 GND Not connected
Not connected 40 AD44 Not connected
Not connected 42 AD42 Not connected
Not connected 44 GND Not connected
Not connected 46 AD40 Not connected
Not connected 48 AD38 Not connected

Not connected 58 AD32 Not connected

Not connected Serial2 RxD

GPIOx: GENERAL PURPOSE INPUT OUTPUT These I/O signals (TTL) are connected to MV64460

MPP[19, 21:27]. At powerup (default), these pins are configured as inputs.

LPa_DX+/-, LPb_DX+/-: LINK PORT signals for Ethernet 10/100/1000 MDI

SERIALxTXD: SERIAL PORT 1-2 TRANSMIT DATA (Output to PMC, TTL or EIA-232)

SERIALxRXD: SERIAL PORT 1-2 RECEIVE DATA (Input to PMC, TTL or EIA-232)

PMC Connector

Refer to the component map in Fig. 2-1 for the location of the PMC connectors on the
PmPPC7448 circuit board.

Figure 5-6: PMC Connector

5-12

PmPPC7448 User’s Manual 10006757-02

System Controller: Doorbell Registers

DOORBELL REGISTERS

The MV64460 uses the doorbell registers in the messaging unit (MU) to request interrupts
on both the PCI and CPU buses. There are two types of doorbell registers:

Outbound: These are set by the MV64460’s local CPU to request an interrupt service on the PCI bus.

Inbound: These are set by an external PCI agent to request interrupt service from the local CPU.

Outbound Doorbells

The local CPU generates an interrupt request to the PCI bus by setting bits in the Outbound
Doorbell register (ODR). The interrupt may be masked in the Outbound Interrupt Mask reg­ister (OIMR), but that does not prevent the bit from being set in the ODR. The ODR is
located at PCI_0 offset 0x1C2C.

Note: The CPU or the PCI interface can set the ODR bits. This allows for passing interrupt requests between CPU and

PCI interfaces.

Inbound Doorbells

The PCI bus generates an interrupt request to the local CPU by setting bits in the Inbound
Doorbell register (IDR). The interrupt may be masked in the Inbound Interrupt Mask regis­ter (IIMR), but masking the interrupt does not prevent the bit from being set in the IDR. The
IDR is located at PCI_0 offset 0x1C20.

Note: The interrupt request triggered from the PCI bus can be targeted to the CPU or to the PCI interface, depending

on the software setting of the interrupt mask registers.

MONARCH FUNCTIONALITY

The PmPPC7448 can be configured to function as either a Monarch or non-Monarch mod­ule, as described in the VITA 32 PPMC specification. A Monarch is the main PPMC device on
the local PCI bus. It performs enumeration on that bus after power-up and is often the inter­rupt handler. A non-Monarch module does not perform enumeration on the local bus after
power-up. Bit 2 of Board Configuration Register 3 (see
F820,C000
determined by the signal on pin 64 of connector P12. The software can read the Monarch
line status to configure the board, and the hardware is unaffected.

The EReady register (see
support Monarch functionality. EREADY bit 0 monitors the EREADY line. For a non-Mon­arch, it is presumed that this signal is initially asserted, then removed when the bus is ready
for enumeration. When all the other PCI devices have stopped driving this signal low, the
Monarch will enumerate the bus. Please see the PPMC standard (reference in
carrier board pull-up requirements.

indicates how the module is configured (0=non-Monarch, 1=Monarch), as

16

Register Map 7-7) at location F820,5000

10006757-02 PmPPC7448 User’s Manual

Register Map 7-10) at location

has an additional bit to

16

Table 1-3) for

5-13

System Controller: 66 MHz Bus Operation

!

66 MHZ BUS OPERATION

Conventional PCI: In order for the PCI bus to operate at 66 MHz, all devices on the bus must be capable of that

speed. When the M66EN signal (connector P12 pin 47) is high for a particular PCI device, it
indicates that the device can operate at 66 MHz. For 33 MHz modules, M66EN is grounded,
so the signal will be high only when all devices on the PCI bus are capable of operating at 66
MHz. Software can read bit 21 of the PCI Status and Command register to determine the
bus speed. If bit 21 is high, the bus speed is 66 MHz; if it is low, the bus speed is 33 MHz. If
any PCI device pulls the wire or M66EN signal low, then the bus speed will be 33 MHz for all
of the devices. Please see the PPMC standard (reference in
up requirements.

WATCHDOG TIMER

The 32-bit count down watchdog timer generates a nonmaskable interrupt or resets the
system in the event of unpredictable software behavior. After the watchdog is enabled, it is
a free-running counter that requires periodic servicing to prevent its expiration. After reset,
the watchdog is disabled.

Table 1-3) for carrier board pull-

RESET

Circuitry on the PmPPC7448 resets the entire module if the voltages fall out of tolerance
(due to power-on reset) or if the optional on-board reset switch is activated. The Marvell
MV64460 control register settings are initialized immediately following this reset to config­ure the module properly before allowing any external PCI accesses to occur. The MV64460
supports three reset pins:

SYSRST*: SYSRST* is the main reset pin. When asserted, all MV64460 logics are in a reset state and all

outputs are floated, except for DRAM address and control outputs. SYSRST* is separated
from the PCI reset pins so the CPU can boot and start to initialize the board before the PCI
slot reset signal is deasserted.

PCI0_RST* and PCI1_RST*:These pins are the independent PCI interface reset pins. The PCI is kept in a reset state as

long as its corresponding reset pin is asserted. On reset deassertion, all PCI configuration
registers are set to their initial values as specified in the PCI specification. The two methods
of PCI reset configuration include: pins sampled on SYSRST* deassertion and serial ROM ini­tialization. Only PCI0 is functional on the PmPPC7448.

Caution: When the MV64460 is in reset, any other attempts for PCI device access is ignored.

Therefore, use RESET_OUT and drive RST as long as it is asserted or wait for EReady
assertion before attempting an access.

5-14

PmPPC7448 User’s Manual 10006757-02

Ethernet Interface

The PmPPC7448 provides three independent full duplex Ethernet ports. Using the Marvell
MV64460, these ports are configured to one 10/100 Mbps Media Independent Interface
(MII) and two 10/100/1000 Mbps Gigabit MII (GMII). The two gigabit Ethernet ports (ports
0 and 1) are routed through PMC connector P14. The 10/100 Mbps Ethernet port (port 2) is
routed to the front panel mini-USB connector.

Note: Since GbE ports 0 and 1 are routed through the PHYs directly to connector P14, magnetics are required on

the Rear Transition Module (RTM) or baseboard.

Some additional Ethernet features on the MV64460 include:

• IEEE 802.3 compliant MAC layer function

• 10/100/1000 megabit operation — half and full duplex are automatically mapped out
through the PHY

• IEEE 802.3x flow-control for full duplex operation mode and back pressure for half
duplex mode

Section 6

• Internal and external loop back modes

• Short frame transmission (less than 64 bytes) zero padding and long frame transmission
(limited only by external memory size)

The Micrel KSZ8721CL 10/100BASE-TX/FX and two Broadcom BCM5461S 1000BASE­T/100BASE-TX/FX/10BASE-T transceivers provide:

• Compliance with IEEE 802.3 standards

• Compliance with PICMG 2.15 standards

• Low power consumption; less than 340 mW

• IEEE 1149.1 (JTAG) boundary scan chain support

Note: Proprietary information on the Micrel and Broadcom Ethernet transceiver devices is not available in this

user’s manual. Please refer to the Micrel web site at http://www.micrel.com or the Broadcom web site at
http://www.broadcom.com for available documentation.

MV64460 ETHERNET REGISTERS

The MV64460 is capable of implementing three 10/100/1000 Ethernet controllers. These
controllers interface with the PHY via MII or GMII interface.

The Serial Management Interface (SMI) unit continuously queries the PHY devices for their
link status. The PHY addresses for the link query operation are programmable per port in
the PHY_Address register.

10006757-02 PmPPC7448 User’s Manual

6-1

Ethernet Interface: Ethernet Address

ETHERNET ADDRESS

The Ethernet address for your board is a unique identifier on a network and must not be
altered. The address consists of 48 (MAC[47:0]) bits divided into two equal parts. The upper
24 bits define a unique identifier that has been assigned to Emerson Network Power by
IEEE. The lower 24 bits are defined by Emerson for identification of each of our products.

The Ethernet address for the PmPPC7448 is a binary number referenced as 12 hexadecimal
digits separated into pairs, with each pair representing eight bits. The address assigned to
the PmPPC7448 has the following form:

00 80 F9 xx yy zz

00 80 F9 is Emerson’s identifier. The last three bytes of the Ethernet address comprise the
data for the Ethernet addresses in non-volatile memory (NVRAM). The PmPPC7448 has
been assigned the Ethernet address range 00:80:F9:81:00:00 to 00:80:F9:83:FF:FF. The for­mat is shown in

Table 6-1: Ethernet Port Address Numbering

Offset: MAC: Description:

Byte 5
Byte 4 MSB of (serial number -1000) —

Byte 3 23:16

Byte 2
Byte 1 80
Byte 0 00

Table 6-1.

15:0

47:24 Assigned to Emerson by IEEE

LSB of (serial number -1000) —

Port 2 (front panel debug port, portdbg) 83
Port 1 (portb) 82
Port 0 (porta) 81

Ethernet
Identifier (Hex):

F9

The last pair of hex numbers correspond to the following formula: n — 1000, where n is the
unique serial number assigned to each board. For example, if the serial number of a
PmPPC7448 is 2867, the calculated value is 1867 (74B
Ethernet address is 00:80:F9:82:07:4B.

ETHERNET CONNECTION (P1)

The Micrel KSZ8721CL 10/100 PHY (port 2) signals are routed to the P1 connector. P1 is a
mini-USB connector available at the front panel. See
(Emerson part number C0007666-00) is shown in

6-2

PmPPC7448 User’s Manual 10006757-02

). Therefore, the board’s port 1

16

Table 6-2 below. The Ethernet cable

Fig. 6-1.

Ethernet Interface: Ethernet Connection (P1)

Pin 1

RJ45 Connector

Mini-B USB

ETHERNET

!

Figure 6-1: Front Panel Ethernet Connector (P1)

Table 6-2: Front Panel Ethernet Pin Assignments (P1)

Pin: Signal: Pin: Signal:

1 Ethernet 1 transmit positive 2 Ethernet 1 transmit negative
3 Ethernet 1 receive positive 4 Ethernet 1 receive negative
5 Signal ground 6-9 Connector housing ground

Figure 6-2: Ethernet Cable Assembly

Caution: The Mini-USB cable connection to P1 does not have a locking mechanism. Pulling on the

cable may result in a disconnection.

Table 6-3: Ethernet Cable Wiring Assignments

Mini-B USB Pin: Description: RJ45 Pin:

Shell Drain wire (shield) Shell (G)
1 White/orange wire (TX+) 1
2Orange wire (TX-)2
3White/blue wire (RX+)3
4Blue wire (RX-)6
5

No connection 4
No connection 5
No connection 7
No connection 8

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6-3

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6-4

PmPPC7448 User’s Manual 10006757-02

CPLD

Section 7

This chapter lists the registers implemented by the complex programmable logic device
(CPLD).

RESET REGISTERS

The reset signals are routed to and distributed by the CPLD. To support this functionality,
the CPLD includes two registers; one indicates the reason for the last reset, and the other
forces one of several types of reset.

Reset Event Register (RER)

This read-only register contains the cause of the latest reset.

Register 7-1: Reset Event Register (RER) at 0xf820,0000

76543210

InitAct SW WD COPS COPH RPCIOFP

InitAct: Initialization Active

Set to 1 when the MV64460 InitAct pin does not go inactive after reset.

SW: Software

Set to 1 when the last reset was caused by a write to the Reset Command register.

WD: Watchdog

Set to 1 when a reset was caused by the expiration of the MV64460 watchdog timer.

COPS: Soft Reset

Set to 1 when a COP header soft reset (SRESET) has occurred.

COPH: Hard Reset

Set to 1 when a COP header hard reset (HRESET) has occurred.

R: Reserved (default is 00)

PCIO: PCI O

Set to 1 when a PMC PCI reset (RST* signal) has occurred.

FP: Front Panel

Set to 1 when the front panel switch caused a reset.

Reset Command Register (RCR)

The Reset Command register forces one of several types of resets, as shown below. A reset
sequence is initiated by writing a one to a valid bit, then the bit is automatically cleared.

10006757-02 PmPPC7448 User’s Manual

7-1

CPLD: Reset Registers

Register 7-2: Reset Command Register (RCR) at 0xf820,1000

76543210

SCL SDA RI2CFRSR RHR

SCL: Serial I2C Clock

1 Tri-states the PLD
0Drives logic low

SDA: Serial I

R: Reserved (default is 00)

I2C: I

FR: Flash Reset command

2

C Data/Address
1 Tri-states the PLD
0Drives logic low

2

C reset

1Causes the I

2

0No I

C reset (default)

1 Causes Flash to be reset
0 No Flash reset (default)

2

C bus to be reset into a known state

SR: Soft Reset command

1 Causes a soft reset to the CPU and resets on-board Flash
0 No soft reset (default)

HR: Hard Reset command

1 Causes a hard reset on board
0 No hard reset (default)

PCI Reset Out Enable Register (ROER)

The Reset Out Enable register determines the functionality of the PCI ResetOut signal.

Register 7-3: Reset Out Enable Register (ROER) at 0xf820,e000

76543210

RSWWDRCOPHRPCI0FP

R: Reserved (default is 00)

7-2

PmPPC7448 User’s Manual 10006757-02

CPLD: Interrupt Registers

SW: Software

PCI reset driven when on-board hard reset is caused by a write to the Reset Command regis­ter.
1Enabled
0Disabled

WD: WatchDog

PCI reset driven when on-board reset is caused by a timeout of the WatchDog timer.
1Enabled
0Disabled

COPH: Hard RESET

PCI reset driven when reset is caused by a COP HRESET.
1Enabled
0Disabled

PCI0: PCI reset driven when on-board reset is caused by the assertion of PCI0 reset (PCI RESET).

1Enabled
0Disabled

FP: Front Panel

PCI reset driven when on-board reset is caused by the front panel pushbutton.
1Enabled
0Disabled

INTERRUPT REGISTERS

The system error and parity error interrupts are routed to the CPLD. These signals, per the
PCI specification, are sampled on the rising edge of the PCI clock. Since the PCI clock is
restricted to one load, SERR and PERR from the PPMC site are sampled with a 66 MHz on­board clock. These signals should be held low for a clock cycle or they will be ignored. The
following signals are routed to the appropriate MV64460 MPP pin:

• PERR and SERR are combined into a single interrupt and routed to MPP13.

• The non-maskable watchdog timer is routed to MPP18.

To control the routing of the interrupts, the CPLD implements the following enable and
pending registers.

10006757-02 PmPPC7448 User’s Manual

7-3

CPLD: Interrupt Registers

Interrupt Enable Register (IER)

Register 7-4: PmPPC7448 Interrupt Enable Register (IER) at 0xf820,2000

76543210

R: Reserved (default is 000)

SR0EN: PCI0 SERR Enable interrupt routed from PCI0 SERR to MV64460

1 Enabled to generate an interrupt
0 Disabled (default)

PR0EN: PCI0 PERR Enable interrupt routed from PCI0 PERR to MV64460

1 Enabled to generate an interrupt
0 Disabled (default)

Interrupt Pending Register (IPR)

This register allows software to determine which source has caused an interrupt.

Register 7-5: PmPPC7448 Interrupt Pending Register (IPR) at 0xf820,3000

Reserved SR0EN PR0EN

76543210

R: Reserved (default is 000)

SERR0: PCI0 SERR Enable

1 SERR has occurred and is enabled (IER SR1EN=1)
0 No SERR (default)

PERR0: PCI0 PERR Enable

1 PERR has occurred and is enabled (IER PR1EN=1)
0No PERR (default)

7-4

PmPPC7448 User’s Manual 10006757-02

Reserved SERR0 PERR0

CPLD: Product ID Register (PIR)

PRODUCT ID REGISTER (PIR)

This read-only register identifies the board as PmPPC7448.

Register 7-6: PmPPC7448 Product ID Register (PIR) at 0xf820,4000

76543210

PIDR: Product Identification register

05

PmPPC7448

16

EREADY REGISTER (ERDY)

The PmPPC7448 provides a register for status and control of enumeration. In a Monarch
system, the register is readable to indicate that other boards in the system are ready for
enumeration. In a non-Monarch system, the register is writeable to indicate the
PmPPC7448 is ready for enumeration.

Register 7-7: PmPPC7448 ERdy Register (ERdy) at 0xf820,5000

PIDR

76543210

Reserved ERdy

R: Reserved (default is 0000000)

ERdy: Monarch (read)

1 PCI devices are ready to be enumerated.
0PCI devices are not ready to be enumerated.

Non-Monarch (write) (default for non-Monarch)
1 PMC is ready to be enumerated.
0 PMC is not ready to be enumerated.

REVISION REGISTERS

Two read-only registers are provided to track hardware and PLD revisions. A PLD version
register provides a hard-coded tracking number that changes with each major CPLD code
release.

10006757-02 PmPPC7448 User’s Manual

7-5

CPLD: Board Configuration Registers

Hardware Version Register (HVR)

Register 7-8: Hardware Version Register (HVR) at 0xf820,7000

76543210

HVR: Hardware Version number

This is hard coded in the PLD and changes with every major PCB version. Version starts at
00

.

16

PLD Version Register (PVR)

Register 7-9: PLD Version Register (PVR) at 0xf820,8000

76543210

PVR: PLD code Version number

This is hard coded in the PLD and changes with every major code change. Version starts at
00

.

16

HVR

PVR

BOARD CONFIGURATION REGISTERS

Three byte-wide, read-only Board Configuration registers start at location F820,900016.
These registers allow the monitor software to easily determine specific hardware configu­rations, including Monarch/non-Monarch, DMC status, Boot device, and system clock
speed.

Note: Board Configuration register 2 (0xf820,b000) is not available.

Register 7-10: PmPPC7448 Board Configuration 3 (BCR3) at 0xf820,c000

76543210

Reserved: Reserved for future use, default is 0

Mon: Processor PMC Monarch indication

1PPMC is Monarch
0 PPMC is non-Monarch

7-6

PmPPC7448 User’s Manual 10006757-02

Reserved Mon DMC R

CPLD: Board Configuration Registers

DMC: Development Mezzanine Card installation option

1 DMC is installed
0 DMC is not installed

Register 7-11: PmPPC7448 Board Configuration 1 (BCR1) at 0xf820,a000

76543210

Reserved Boot

DMC

R: Reserved, default is 0

Boot DMC: Boot from Development Mezzanine Card ROM or PPMC Flash

1 Boot from DMC PLCC ROM
0 Boot from PPMC Flash (default)

Register 7-12: PmPPC7448 Board Configuration 0 (BCR0) at 0xf820,9000

76543210

SysCLK Reserved

SysCLK: System Clock Speed

11 133 MHz
10 166 MHz
01 Reserved
00 Reserved

R: Reserved (default is 000000)

Reserved

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7-8

PmPPC7448 User’s Manual 10006757-02

Serial Input/Output

The PmPPC7448 has two EIA-232 serial ports. These ports operate between 9600 and
115,200 baud. Software selects the speed and these settings are stored in non-volatile
memory. Serial port one is always routed to the Development Mezzanine Card (DMC) serial
connector as 12 volts; build options include connections to the front panel serial connector,
or the P14 connector. When routed to P14, there is the option of either EIA-232 or TTL sig­naling levels. Port two is routed to P14 with the same options. The Marvell MV64460 sys­tem controller provides the communication ports for the PmPPC7448. For more detailed
information on the MV64460, reference the web site http://www.marvell.com.

MULTI-PROTOCOL SERIAL CONTROLLERS (MPSC)

The MV64460 has two MPSCs with each channel supporting HDLC, BISYNC, UART, or Trans­parent protocols.

Signals Routing: The two MPSCs can be routed to serial port 0 and serial port 1, or not connected. These are

defined in the Main Routing register (MRR).

Section 8

MPSCx Main Configuration Registers:

Each MPSC has an MPSC Main Configuration register (MMCRx) for port 0 and port 1. The
MMCRx is a 64-bit register that configures common MPSC features and is protocol indepen­dent. Each MMCRx consists of two 32-bit registers, MMCRLx (low) and MMCRHx (high).

SERIAL DMA (SDMA) CHANNELS

Two of the SDMA channels support data movement between the MPSCs and memory buff­ers on the MV64460. Each channel consists of a DMA engine for receiving and one for trans­mitting. The SDMA uses a linked chain of descriptors and buffers to reduce CPU overhead.

PROGRAMMABLE BAUD RATE

The MV64460 has two programmable baud rate generators (BRG); each with five clock
inputs: BClkIn, TClk, SCLK, TSCLK, and CLKSel.

BRGx Configuration Register

When a BRG is enabled, it loads the Count Down Value (CDV) from the BRG configuration
register into its count down counter. When the counter expires (reaches zero), the BRG
clock output (BCLK) is toggled and the counter reloads.

Note: The EIA-232C specification defines a maximum rate of 20,000 bits per second over a typical 50-foot cable

(2,500 picofarads maximum load capacitance). Higher baud rates are possible, but depend specifically upon
the application, cable length, and overall signal quality.

10006757-02 PmPPC7448 User’s Manual

8-1

Serial Input/Output: I2C Interface

Pin 1

BRGx Tuning Register

A baud tuning mechanism adjusts the generated clock rate to the receive clock rate. When
baud tuning is enabled, the baud tuning mechanism monitors for a start bit (for example
high-to-low transition). Once the start bit is found, the baud tuning machine measures the
bit length by counting up until the next Low-to-High transition. Then the count-up value of
the BRG is loaded into the Count Up Value (CUV) register and a maskable interrupt is gener­ated signaling the CPU that the bit length value is available. Finally, the CPU reads the value
from the CUV and adjusts the CDV to the requested value.

I2C INTERFACE

The MV64460 has full I2C interface support, acting as both a master generating read/write
requests and as a slave responding to read/write requests. The I
open drain signals—serial clock (SCL) and serial data/address (SDA).

Note: Marvell documentation refers to this as the Two-Wire Serial Interface (TWSI).

An I2C serial configuration ROM is connected to the MV64460’s I2C interface, and is dis­abled by default. Emerson uses the addresses in

Table 8-1: I2C Device Addresses

Table 8-1 for I

Device (reference designator): Hex Address:

64460 I2C (U33) 0xA4
NVRAM I
RTC (U36) 0xD0
SO-DIMM I2C (U3) 0xAE

2

C (U34) 0xA6

I/O CONNECTION

Specific PmPPC7448 configurations provide a standard EIA-232 serial I/O port; P2 is a mini­USB connector available at the front panel. See
ments are in

Figure 8-1: Front Panel Serial Port Connector (P2)

Table 8-3.

Table 8-2 below. The cable wiring assign-

2

C port consists of two

2

C devices.

8-2

PmPPC7448 User’s Manual 10006757-02

Serial Input/Output: I/O Connection

DB9 Connector

Mini-B USB

!

Table 8-2: Front Panel Serial Port Pin Assignments (P2)

Pin: Signal: Pin: Signal:

1 Not connected 2

1

3

5 Ground 6-9 Connector housing ground

1.Signals (pins 2 and 3) can be switched as a factory build option.

Figure 8-2: Serial Cable Assembly (Emerson Part Number C0007662-00)

Transmit (Tx) Data Output,
EIA-232 (alternate is Rx)

1

1

4

Receive (Rx) Data Input,
EIA-232 (alternate is Tx)

Not connected

1

Caution: The Mini-USB cable connection to P2 does not have a locking mechanism. Pulling on the

cable may result in a disconnection.

Table 8-3: Serial Cable Wiring Assignments

Mini-USB Pin: Description:

Shell Drain wire (shield) Shell
1
2 White wire (receive) 3
3 Green wire (transmit) 2
4
5 Black wire (signal ground) 5

No connection 1

No connection 4

No connection 6
No connection 7
No connection 8
No connection 9

2

DB9 Pin:

2.The USB cable red wire is not used.

10006757-02 PmPPC7448 User’s Manual

8-3

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8-4

PmPPC7448 User’s Manual 10006757-02

Real-Time Clock

!

Seconds

Minutes

Century/Hours

Day

Date

Month

Year

Control

1Hz

OSC1

OSC0

FT/OUT

SCL

SDA

V

CC

V

SS

V

BAT

Address
Register

Control

Logic

Divider

Oscillator

32.768 KHz

Voltage

Sense and

Switch

Circuitry

Serial

Bus

Interface

The standard real-time clock (RTC) for the PmPPC7448 is provided by an M41T00 device
from STMicroelectronics. This device has an integrated year-2000-compatible RTC, power
sense circuitry, and uses eight bytes of non-volatile RAM for the clock/calendar function.
The M41T00 is powered from the +3.3 volt rail during normal operation.

Caution: A supercapacitor on the PmPPC7448 provides backup operation in the event of a power

failure. However, if power is not reapplied within 12 hours, all data stored in non-volatile
RAM may be lost.

BLOCK DIAGRAM

Figure 9-1: M41T00 Real-Time Clock Block Diagram

Section 9

OPERATION

The M41T00 clock operates as a slave device on the serial bus. To obtain access, the RTC
implements a start condition followed by the correct slave address (D0h). Access the eight
bytes in the following order:

10006757-02 PmPPC7448 User’s Manual

9-1

Real-Time Clock: Clock Operation

1 Seconds register

2 Minutes register

3 Century/Hours register

4 Day register

5 Date register

6 Month register

7 Years register

8 Control register

The M41T00 clock continually monitors the supply voltage (Vcc) for an out of tolerance
condition. If Vcc falls below switch-over voltage (Vso), the M41T00:

• Terminates an access in progress

• Resets the device address counter

• Does not recognize inputs (prevents erroneous data from being written)

At power-up, the M41T00 uses Vcc at Vso and recognizes inputs.

CLOCK OPERATION

Read the seven Clock registers one byte at a time or in a sequential block. Access the Con­trol register (address location 7) independently. An update to the Clock registers is delayed
for 250 ms to allow the read to be completed before the update occurs. This delay does not
alter the actual clock time. The eight byte clock register sets the clock and reads the date
and time from the clock, as summarized in

Table 9-1: RTC Register Map

Address: Data: Function/Range:

00
01

02
03
04
05
06
07

Table 9-1.

D7 D6 D5 D4 D3 D2 D1 D0 BCD Format

ST 10 Seconds Seconds Seconds 00—59

X 10 Minutes Minutes Minutes 00—59

CEB CB 10 Hours Hours Century/

Hours
X X X X X Day Day 01—07

X X 10 Date Date Date 01—31

X X X 10 M Month Month 01—12

10 Years Years Years 00—99

OUT FT S Calibration Control —

0-1/

00-23

9-2

PmPPC7448 User’s Manual 10006757-02

Real-Time Clock: Clock Operation

ST: Stop bit

1=Stops the oscillator
0=Restarts the oscillator within one second

CEB: Century Enable Bit

1=Causes CB to toggle either from 0 to 1 or from 1 to 0 at the turn of the century
0=CB will not toggle

CB: Century Bit

Day: Day of the week

Date: Day of the month

OUT: Output level

1=Default at initial power-up
0=FT/OUT (pin 7) driven low when FT is also zero

FT: Frequency Test bit

1=When oscillator is running at 32,768 Hz, the FT/OUT pin will toggle at 512 Hz
0=The FT/OUT pin is an output driver (default at initial power-up)

S: Sign bit

1=Positive calibration
0=Negative calibration

Calibration: Calibration bits The calibration circuit adds or subtracts counts from the oscillator divider

circuit at the divide by 256 stage. The number of times pulses are blanked (subtracted, neg­ative calibration) or split (added, positive calibration) depends on this five-bit byte. Adding
counts accelerates the clock, and subtracting counts slows the clock down.

X: Don’t care bit

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9-3

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9-4

PmPPC7448 User’s Manual 10006757-02

Development Mezzanine Card

The Development Mezzanine Card (DMC) is an optional plug-on card mounted on the back
of the PmPPC7448 board to expedite product development. This chapter describes the
physical layout of the DMC, the setup process, and how to check for proper operation once
the board has been installed. The DMC facilitates hardware and software development by
providing:

• Four LEDs for software development (connected to the MV64460 MPP pins)

• An EIA-232 debug serial port (mini-USB connector) with cable to DB-9 connectors

• JTAG/COP header for software development

• JTAG header for CPLD programming

• A 32-pin, PLCC 8-bit ROM socket for software development

• Four software-readable jumpers for development use

DMC CIRCUIT BOARD

Section 10

The DMC is a custom four-layer circuit board. It has the following physical dimensions.

Table 10-1: DMC Mechanical Specifications

Width: Depth: Height (top side): Height (bottom side):

2.913 in.
(74.0 mm)

2.100 in.
(53.3 mm)

0.323 in.
(8.2 mm)

0.007 in.
(1.9 mm)

10006757-02 PmPPC7448 User’s Manual

10-1

Development Mezzanine Card: DMC Circuit Board

SPARE

ENET

BOOT

JP3

JP4

CPLD JTAG

COP/JTAG

PORT 1

PORT 0

1

2

1

2

12

10002939-00

C3

C4

C5

C7

C10

C11

C13

C12

C1

F1

U2

CR1

CR2

CR3

CR4

R23

R24

R25

R26

R27

R28

R29

R30

R3

R4R5R6

R1
R2

U5U3

R9
R10
R11
R12

R13
R14
R15
R16

R7

R17

R18

R20

R33

R34

R36

R38

C2 C6C8 C9

R19

R21

R31

R32

R35

R37

P3

JP1

P2

Mini-USB

P6

RJ45

P5

RJ45

P4

9

10

10

9

15 16

1

10002939-00

COPYRIGHT 2002

TECHNOLOGIES

R

P1

P7

P8

41

40

80

00000000-00 D

667C-

XXXXXX

Figure 10-1: DMC Component Maps, Top and Bottom (Revision 01)

Serial Numbers

Before you install the DMC in a system, you should record the following information:

❐ The board serial number: 667C- ______________________________________ .

❐ The board product identification (ID): _________________________________ .

❐ Any custom or user ROM installed, including version and serial number:

The board serial number appears on a bar code sticker located on the bottom of the
board.

This product ID sticker is located near the serial number.

________________________________________________________________ .

10-2

PmPPC7448 User’s Manual 10006757-02

Development Mezzanine Card: Connectors

40 1

4180

It is useful to have these numbers available when you contact Technical Support or Test and
Repair Services at Emerson Network Power.

CONNECTORS

The DMC has the following connectors:

P1: This 80-pin PCB-to-PCB female connector on the bottom side of the DMC routes memory,

CPLD, and CPU signals from the PmPPC7448 to the DMC for development use. See

for the pin assignments.

2

Table 10-

P2: This mini-USB 9-pin connector provides the EIA-232 interface. See

assignments.

P3: The 14-pin COP/JTAG interface header allows software development to the Freescale

MPC7448. Refer to

Table 10-4 for the pin assignments.

P4: The CPLD JTAG header provides access to the CPLD programming interface. Refer to

Table 10-5 for the pin assignments.

P5-P6: The DMC 10/100 fast Ethernet RJ-45 connectors are not used for the PmPPC7448.

P1 Connector Pin Assignments

Figure 10-2: DMC P1 PCB-to-PCB Connector

Table 10-2: DMC P1 Connector Pin Assignments

Pin: Signal: Pin: Signal:

13.3 V 2CPLD_TCK
3GND 4

Not connected 6 DMC_CS*

5
7DMC_OE* 8WE0*
9 LA17 10 LA16
11 LA15 12 LA14
13 LA13 14 LA12
15 LA11 16 LA10
17 LA9 18 LA8

Table 10-3 for the pin

Not connected

10006757-02 PmPPC7448 User’s Manual

10-3

Development Mezzanine Card: Connectors

Pin: Signal: Pin: Signal:

19 LA7 20 LA6
21 LA5 22 LA4
23 LA3 24 LA2
25 BADDR2 26 BADDR1
27 BADDR0 28 AD7
29 AD6 30 AD5
31 AD4 32 AD3
33 AD2 34 AD1
35 AD0 36 FILT_TX
37 FILT_RX 38 GND
39 CPU_VIO

(DMC JTAG)
41 3.3 V 42 MPC7448_TCK
43 GND 44

Not connected 46 Not connected

45

Not connected 48 Not connected

47

Not connected 50 Not connected

49
51 DMC_JP1 52 DMC_BOOT_SRC
53 DMC_JP3 54 DMC_JP4
55 LED1* 56 LED2*
57 LED3* 58 LED4*
59 MPC7448_TDO 60 MPC7448_TDI
61 DEBUG_TRST* 62 MPC7448_TMS
63 DEBUG_SRESET* 64 DEBUG_HRESET*
65 MPC7448_CKSTP

_OUT

Not connected 68 Not connected

67

Not connected 70 Not connected

69

Not connected 72 CPLD_TDI

71
73 CPLD_TMS 74 CPLD_TDO
75 GND/DMC_PD

Not connected 78 GND

77

Not connected 80 3.3 V

79

11

40 3.3 V

Not connected

Not connected

66

Not connected

76

10-4

1. When pin 75 is grounded, this notifies the PmPPC7448 that a DMC module is attached—presence detect
(PD).

3.3 V: 3.3 V is the power supply to the DMC (analog).

CPLD_TCK: PLD Test Clock is an input to DMC and part of the PLD JTAG interface.

DMC_CS*: Chip Select for DMC Flash is an input to DMC.

PmPPC7448 User’s Manual 10006757-02

Development Mezzanine Card: Connectors

DMC_OE*: Output Enable for DMC Flash is an input to DMC.

WE0*: Write Enable for DMC Flash is an input to DMC.

LA(17:2): Latched Address for DMC Flash is an input to DMC.

BADDR(2:0): Burst Address for DMC Flash is an input to DMC.

AD(7:0): Multiplexed Address/Data bus for DMC Flash data is an output from DMC.

FILT_TX: Serial IO Transmit (console port) is an input to DMC.

FILT_RX: Serial IO Receive (console port) is an output from DMC.

CPU_VIO: IO Voltage for CPU is used as reference/power on the debug header (analog).

MPC7448_TCK: CPU Test Clock is an output from DMC and part of CPU JTAG interface.

DMC_BOOT_SRC: Boot source is an output from DMC and indicates to the PmPPC7448 whether to boot from

the DMC socketed Flash or the PmPPC7448 soldered Flash (default).

DMC_JP(4:3,1): Jumpers are an output from DMC and these three spare DMC jumpers are for development

purposes.

LED(4:1)*: These DMC LEDs are an input to DMC and are user definable for development purposes.

MPC7448_TDO: CPU Test Data Out is an input to DMC and part of CPU JTAG interface.

MPC7448_TDI: CPU Test Data In is an output from DMC and part of CPU JTAG interface.

DEBUG_TRST*: CPU Test Reset is an output from DMC and part of CPU JTAG interface.

MPC7448_TMS: CPU Test Mode Select is an output from DMC and part of CPU JTAG interface.

DEBUG_SRESET*: Common On-Chip Processor Soft Reset is an output of DMC and used by the debug header

to issue a soft reset.

DEBUG_HRESET*: Common On-Chip Processor Hard Reset is an output of DMC and used by the debug header

to issue a hard reset.

MPC7448_CKSTP_OUT: Check Stop Out is an input to DMC used by the debug header.

CPLD_TDI: PLD Test Data In is part of the PLD JTAG interface (analog).

CPLD_TMS: PLD Test Mode Select is an output from DMC and part of PLD JTAG interface.

CPLD_TDO: PLD Test Data Out is an input to DMC and part of PLD JTAG interface.

DMC_PD*: DMC Presence Detect is an output from DMC and indicates to the PPMC that the DMC is

installed.

10006757-02 PmPPC7448 User’s Manual

10-5

Development Mezzanine Card: Connectors

Pin 1

P2 EIA-232 Interface

Use the standard serial cable, Emerson part number C0007662-00, to access connector P2.
Pin assignments are listed in

Figure 10-3: DMC P2 Mini-USB Connector

Table 10-3: DMC P2 Pin Assignments

Pin: Signal: Pin: Signal:

1 Not connected 2 DMC_RXD (Input)
3DMC_TXD (Output) 4
5 GND 6-9 Connector housing ground

Table 10-3.

Not connected

10-6

PmPPC7448 User’s Manual 10006757-02

Development Mezzanine Card: PmPPC7448 to DMC JTAG

MPC7448

Device

CPLD

Development

Mezzanine Card

(DMC)

COP Debug
TDO
TDI

TCK
TMS

TRST*

15 16

2

PLD JTAG
TCK
TDO
TMS

10

2

TDI

CPLD_TDI

CPLD_TMS

CPLD_TDO

CPLD_TCK

MPC7448_TDO

MPC7448_TDI

MPC7448_TCK
MPC7448_TMS

MPC7448_SRESET*

MPC7448_HRESET*

MPC7448_TRST*

MPC7448_SRESET_OUT*

MPC7448_HRESET_OUT*

MPC7448_TRST_OUT*

DEBUG_TRST*

DEBUG_TRST_B*

DEBUG_HRESET_B*

DEBUG_SRESET_B*

CPLD

TCK
TDO
TMS

TDI

TCK

TDI

TDO

TMS

CKSTP_OUT*

SRESET*

HRESET*

TRST*

MPC7448_CKSTP_OUT*

DEBUG_SRESET*
DEBUG_HRESET*

DMC Connector

Convert

3.3 V 1.8V

Convert

1.8 V 3.3V

1

2

15

16

PMPPC7448 TO DMC JTAG

Figure 10-4: PmPPC7448 to DMC JTAG Block Diagram

P3 JTAG/COP

The JTAG/COP interface provides for boundary-scan testing of the CPU and the
PmPPC7448. This interface is compliant with the IEEE 1149.1 standard.

Figure 10-5: DMC P3 JTAG/COP Header

10006757-02 PmPPC7448 User’s Manual

10-7

Development Mezzanine Card: PmPPC7448 to DMC JTAG

1

2

9

10

Table 10-4: DMC P3 Pin Assignments

Pin: Signal: Pin: Signal:

1 MPC7448_TDO 2 Not connected
3 MPC7448_TDI 4 DEBUG_TRST*
5
7 MPC7448_TCK 8
9 MPC7448_TMS 10
11 DEBUG_SRESET* 12 GND
13 DEBUG_HRESET* 14 Key
15 MPC7448CKSTP_OUT* 16 GND

2. Pin 14 is not installed.

MPC7448 CKSTP_OUT*:Checkstop Output—when asserted, this output signal indicates that the CPU has detected a

checkstop condition and has ceased operation.

DEBUG_HRESET*: Hard Reset—this input signal indicates that a complete Power-on Reset must be initiated by

the processor.

DEBUG_SRESET*: Soft Reset—this input signal indicates that the MPC7448 must initiate a System Reset inter-

rupt.

Not connected 6 JTAG_PWR (1.8 V)

Not connected
Not connected

22

MPC7448_TCK: Test Clock Input—scan data is latched at the rising edge of this signal.

MPC7448_TDI: Test Data Input—this signal acts as the input port for scan instructions and data.

MPC7448_TDO: Test Data Output—this signal acts as the output port for scan instructions and data.

MPC7448_TMS: Test Mode Select—this input signal is the test access port (TAP) controller mode signal.

DEBUG_TRST*: Test Reset—this input signal resets the test access port.

P4 JTAG Chain Header

This header allows access to the CPLD programming interface.

Figure 10-6: DMC P4 JTAG Chain Header

10-8

PmPPC7448 User’s Manual 10006757-02

Development Mezzanine Card: DMC Jumpers (JP1)

SPARE

ENET

BOOT

JP3

JP4

1

2

9

10

34567

8

(JP1)

(JP2)

Table 10-5: DMC P4 Pin Assignments

Pin: Signal: Pin: Signal:

1CPLD_TCK 2GND
3 CPLD_TDO 4 Fused 3.3 V
5CPLD_TMS 6
7
9CPLD_TDI 10GND

Not connected 8 Not connected

CPLD_TCK: Test Clock Input—this is the clock input to the boundary scan test (BST) circuitry. Some

operations occur at the rising edge, while others occur at the falling edge.

CPLD_TDI: Test Data Input—this is the serial input pin for instructions as well as test and programming

data. Data is shifted in on the rising edge of TCK.

CPLD_TDO: Test Data Output—this is the serial data output pin for instructions as well as test and pro-

gramming data. Data is shifted out on the falling edge of TCK.

CPLD_TMS: Test Mode Select—this input pin provides the control signal to determine the transitions of

the TAP controller state machine. Transitions within the state machine occur at the rising
edge of TCK. Therefore, TMS must be set up before the rising edge of TCK. TMS is evaluated
on the rising edge of TCK.

Not connected

DMC JUMPERS (JP1)

There are a total of five jumper pairs on the DMC. Pins 9 and 10 are spare jumper posts. See

Fig. 10-1 for the jumper location on the DMC.

Figure 10-7: DMC JP1 Pin Assignments

JP1: The Ethernet configuration jumper (pins 1 and 2) is not used for the PmPPC7448.

JP2: JP2 (pins 3 and 4) selects the 8-bit ROM socket as the boot device. So in order for the socket

to provide boot code, the DMC must be seated on the PmPPC7448 and the boot jumper
must be in place.

10006757-02 PmPPC7448 User’s Manual

10-9

Development Mezzanine Card: Debug/Status LEDs

JP3: This is a user-defined jumper.

JP4: JP4 is the MV64460 serial ROM configuration jumper. If JP4 is installed, the MV64460 will

not try to configure from the serial ROM.

Jumper Setting Register

These read-only bits may be read by software at location F820,6000 to determine the cur­rent DMC jumper (JP1) settings.

Register 10-1: DMC Jumper Setting Register at 0xf820,6000

76543210

Reserved JP4 JP3 JP2 JP1

JP4: Jumper 4 on DMC (MV64460 serial ROM configuration):

1 Installed (MV64460 will not configure from ROM)
0 Not installed (MV64460 will configure from ROM)

JP3: Jumper 3 on DMC (user defined):

1Installed
0 Not installed

10-10

JP2: Jumper 2 on DMC (BOOT):

1 Installed (Boot from DMC ROM socket)
0 Not installed (Boot from PmPPC7448 Flash-default)

JP1: Jumper 1 on DMC (ENET) is not used for the PmPPC7448.

DEBUG/STATUS LEDS

The DMC has four green, light-emitting diodes (LEDs) for software development; see

Fig. 10-1 for LED locations. These LEDs are controlled through the DMC LED register.

Register 10-2: DMC LED Register at 0xf820,d000

76543210

Reserved LED4 LED3 LED2 LED1

LED4: Asserting (1) this bit lights the DMC CR4.

LED3: Asserting (1) this bit lights the DMC CR3.

LED2: Asserting (1) this bit lights the DMC CR2.

LED1: Asserting (1) this bit lights the DMC CR1.

PmPPC7448 User’s Manual 10006757-02

Development Mezzanine Card: DMC Setup

!

DMC SETUP

You need the following items to set up and check the operation of the Emerson DMC.

❐ A compatible PPMC board, such as the Emerson PmPPC7448

❐ Card cage and power supply

❐ CRT terminal

When you unpack the board, save the antistatic bag and box for future shipping or storage.

Caution: Do not install the board in a rack or remove the board from a rack while power is applied, at

risk of damage to the board.

Installing the DMC Card

Use the following procedure to attach the DMC to the PmPPC7448
(see

Fig. 10-8 for DMC location):

1 Remove the protective vinyl caps from the screws.

2 Line up the screws with the threaded holes on the bezel from the bottom side of the

PmPPC7448.

3 Snap the connectors (P1) together and secure the mounting screws through the standoffs

on the DMC to the PmPPC7448.

10006757-02 PmPPC7448 User’s Manual

10-11

684-

XXXXXX

1000XXXX-XX

SPARE

ENET

BOOT

JP3

JP4

CPLD JTAG

COP/JTAG

PORT 1

PORT 0

1

2

1

2

12

10002939-00

C3

C4

C5

C7

C10

C11

C13

C12

C1

F1

U2

CR1

CR2

CR3

CR4

R23

R24

R25

R26

R27

R28

R29

R30

R3

R4R5R6

R1
R2

U5U3

R9
R10
R11
R12

R13
R14
R15
R16

R7

R17

R18

R20

R33

R34

R36

R38

C2

C6

C8

C9

R19

R21

R31

R32

R35

R37

P3

JP1

P2

Mini-USB

P6

RJ45

P5

RJ45

P4

9

10

10

9

15 16

Development Mezzanine Card: DMC Setup

Figure 10-8: DMC Location on PmPPC7448

10-12

PmPPC7448 User’s Manual 10006757-02