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查询EM19101供应商
8-BIT 5 MSPS A/D CONVERTER (CMOS)
8-BIT 5 MSPS A/D CONVERTER (CMOS)
GENERAL DESCRIPTION
EM19101 is a 8-bit CMOS A/D converter for scanner use. The adoption of a 2-step parallel system achieves low
consumption at a maximum conversion speed of 7 MSPS.
FEATURES
• 7MSPS maximum conversion speed
• Build-in sampling and hold circuit
• Internal self-bias reference voltage
• 45 mW very low power dissipation at 5MSPS
• +5V single power supply
• Available in 24 pin SOP
• Series
EM19101M for 300 mil SOP
EM19101S for 209 mil SOP
EM19101
EM19101
APPLICATION
Scanner and a wide range of fields where high speed A/D conversion is required in the digital communication.
PIN ASSIGNMENT
EM19101
DVSS
DVDD
CLK
OE
1
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10
11
12
DVSS
24
VRB
23
VRBS
22
AVSS
21
AVSS
20
VIN
19
AVDD
18
VRT
17
VRTS
16
AVDD
15
AVDD
14
DVDD
13
FUNCTIONAL BLOCK DIAGRAM
DVSS
1
/OE
DVSS
2
D0
3
D1
4
Lower data
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10
DVDD
11
12
CLK DVDD
latches
Upper data
latches
Clock generator
Lower encoder
(4bit)
Upper encoder
(4bit)
Comparators with
S/ H (4bit)
Comparators with
S/ H (4bit)
Reference voltage
Lower
Upper
24
VRB
23
VRBS
22
21
AVSS
20
AVSS
VIN
19
AVDD
18
17
VRT
VRTS
16
AVDD
15
14
AVDD
13
* This specification are subject to be changed without notice.
4.23.1997
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PIN DESCRIPTIONS
N-3
N-2
N
N+1
N+2
N+3
N+4
N-1
N N+1
N+2
Clock
Analog input
Data output
External
Clock
Transf er
Symbol Function
OE Output enable
DVSS Digital ground
D0 Data output bit 0 (LSB)
D1 Data output bit 1
D2 Data output bit 2
D3 Data output bit 3
D4 Data output bit 4
D5 Data output bit 5
D6 Data output bit 6
D7 Data output bit 7 (MSB)
DVDD Digital power supply
CLK Clock input
DVDD Digital power supply
AVDD Analog power supply
AVDD Analog power supply
VRTS Top internal reference voltage
VRT Top reference voltaget
AVDD Analog power supply
VIN Analog input voltage
AVSS Analog ground
AVSS Analog ground
VRBS Bottom internal reference voltage
VRB Bottom reference voltage
DVSS Digital ground
EM19101
8-BIT 5 MSPS A/D CONVERTER (CMOS)
TIMING DIAGRAM
* This specification are subject to be changed without notice.
4.23.1997
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OUTPUT CODING
Step Analog Input (V) Digital Output Code Conditions
0 0.607815 00000000 VRB=0.6V
1 0.607815~0.6156250 00000001 VRT=2.6V
2 0.6156250~0.6234375 00000010 1LSB=7.8125mV
.... .... ....
124 1.6000000~1.6078125 10000000
125 1.6078125~1.6156250 10000001
.... .... ....
254 2.5843750~2.5921875 11111110
255 2.5921875~ 11111111
EM19101
8-BIT 5 MSPS A/D CONVERTER (CMOS)
ABSOLUTE MAXIMUM RATINGS (T
=25°C)
A
Items Sym. Rating Unit
Supply voltage V
Operating temperature T
Input voltage V
Ref, Input voltage V
DD
OPR
IN
RT,VRB
7V
-20 to +65 °C
V
to V
SS
DD
V
to V
SS
DD
V
V
Recommended Poerating Conditions
Items Sym. Rating Unit
Supply voltage AV
Reference input voltage V
Analog input voltage V
(FC=5MPS,VDD=5V,VRB=0.5V,VRT=2.5V,Ta=25°C External clock duty=40 to 60%)
Parameter Sym. Conditions Min. Typ. Max. Unit
Maximum Conversion Speed F
Supply current I
Reference pin current I
Analog input bandwidth BW 1 MHz
Analog input capacitance C
Reference resistance R
Internal bias V
Offset Voltage E
Digital input voltage V
Digital input current I
DV
DD
DD
,AV
,DV
SS
SS
4.75 TO 5.25 V
|DGND-AGND| 0 to 100 mV
0 and above V
VDD and below V
1.0 to 3.0 V
V
to V
RB
RT
5.7 8.0 9.1 mA
220 250 350 Ω
RBS
RTS
0.55 0.6 0.65 V
1.9 2.0 2.1
-10 -35 -60 mV
01545
4.0 V
DD
VIL=0V 5
V
1.0
V
V
RB
RT
RT
IN
- V
V
RB
C
DD
REF
IN
REF
RB
RT-VRB
OT
E
OB
IH
V
IL
IH
I
IL
Vin=0.6V to 2.6V fin=1kHz ramp 5 MSPS
FC=5MSPS NTSC ramp wave input 10 15 mA
VIN=1.5V+0.07Vrms 11 pF
Short VRB and V
Short VRT and V
VDD=max. VIH=V
5uA
* This specification are subject to be changed without notice.
4.23.1997
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Parameter Sym. Conditions Min. Typ. Max. Unit
Digital output current I
Digital output current I
Output data delay T
I
OZH
OH
OL
DL
Integral nonlinearity EL F
Differential nonlinearity ED F
OE=VSS,V
VDD=min. VOL=0.4V 3.7
OE=VDD,V
=5MSPS VIN=0.6V to 2.6V 0.5 1.3 LSB
C
=5MSPS VIN=0.6V to 2.6V ±0.3 ±0.5 LSB
C
Differential gain error DG NTSC 40 IRE mod ramp,
F
=14.3MSPS 1.0 %
Differential phase error D
Aperture jitter t
Sampling delay t
P
AJ
DS
C
Application Note
VDD,V
SS
8-BIT 5 MSPS A/D CONVERTER (CMOS)
OH=VDD
OH=VDD
V
OL
-0.5V -1.1 mA
=0V 16
0.5 °C
EM19101
16 uA
25 40 ns
30 ps
4ns
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and
analog V
pins, use a ceramic capacitor of about 0.1uF set as close as possible to the pin to bypass to the
DD
respective GND’s.
Analog input
Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However
it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When
driving with an amplifier of low output impedance, parasite oscillation may occur. That may be prevented by
inserting a resistance of about 100Ω in series between the amplifier output and A/D input.
Clock input
The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate
it from other circuits
Reference input
Voltage between V
V
pins to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained. By shorting V
RB
and V
, VRB and VRBS, the self bias function that generates VRT=2.6V and VRB=0.6V, is activated.
RTS
to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and
RT
Timing
RT
Analog input is sampled with the falling edge of external clock and output as digital data with a delay of 2.5
clocks and with the following rising edge. The delay from the clock rising edge to the data output is about 25ns.
OE pin
By connecting OE to GND output mode is obtained. By connecting to V
* This specification are subject to be changed without notice.
high impedance is obtained.
DD
4.23.1997
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EM19101
8-BIT 5 MSPS A/D CONVERTER (CMOS)
About latch up
It is necessary that AVDD and DVDD pins be the common source of power supply. This is to avoid latch up
due to the voltage difference between AV
and DVDD pins when power is ON.
DD
* This specification are subject to be changed without notice.
4.23.1997
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Application Circuit
U2
U2
U3
EM19101
8-BIT 5 MSPS A/D CONVERTER (CMOS)
* This specification are subject to be changed without notice.
4.23.1997
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