ELPID HM5225405BLTT-75, HM5225405BLTT-A6, HM5225405BLTT-B6, HM5225405BTT-75, HM5225405BTT-A6 Datasheet

4-Mword × 16-bit × 4-bank/8-Mword × 8-bit × 4-bank

Description

HM5225165B-75/A6/B6
HM5225805B-75/A6/B6
HM5225405B-75/A6/B6

256M LVTTL interface SDRAM

133 MHz/100 MHz

/16-Mword × 4-bit × 4-bank

PC/133, PC/100 SDRAM

E0082H10 (1st edition)

(Previous ADE-203-1073B (Z))

Jan. 31, 2001

The HM5225165B is a 256-Mbit SDRAM organized as 4194304-word × 16-bit × 4 bank. The HM5225805B
is a 256-Mbit SDRAM organized as 8388608-word × 8-bit × 4 bank. The HM5225405B is a 256-Mbit
SDRAM organized as 16777216-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge
of the clock input. It is packaged in standard 54-pin plastic TSOP II.

Features

• 3.3 V power supply

• Clock frequency: 133 MHz/100 MHz (max)

• LVTTL interface

• Single pulsed RAS

• 4 banks can operate simultaneously and independently

• Burst read/write operation and burst read/single write operation capability

• Programmable burst length: 1/2/4/8

• 2 variations of burst sequence
 Sequential (BL = 1/2/4/8)
 Interleave (BL = 1/2/4/8)

• Programmable CAS latency: 2/3

Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

• Byte control by DQM : DQM (HM5225805B/HM5225405B)

: DQMU/DQML (HM5225165B)

• Refresh cycles: 8192 refresh cycles/64 ms

• 2 variations of refresh
 Auto refresh
 Self refresh

Ordering Information

Type No. Frequency CAS latency Package

1

HM5225165BTT-75*
HM5225165BTT-A6
HM5225165BTT-B6*

HM5225165BLTT-75*
HM5225165BLTT-A6
HM5225165BLTT-B6*

HM5225805BTT-75*
HM5225805BTT-A6
HM5225805BTT-B6*

HM5225805BLTT-75*
HM5225805BLTT-A6
HM5225805BLTT-B6*

HM5225405BTT-75*
HM5225405BTT-A6
HM5225405BTT-B6*

HM5225405BLTT-75*
HM5225405BLTT-A6
HM5225405BLTT-B6*

133 MHz
100 MHz

2

100 MHz

1

133 MHz
100 MHz

2

100 MHz

1

133 MHz
100 MHz

2

100 MHz

1

133 MHz
100 MHz

2

100 MHz

1

133 MHz
100 MHz

2

100 MHz

1

133 MHz
100 MHz

2

100 MHz

Notes: 1. 100 MHz operation at CAS latency = 2.

2. 66 MHz operation at CAS latency = 2.

3
2/3
3

3
2/3
3

3
2/3
3

3
2/3
3

3
2/3
3

3
2/3
3

400-mil 54-pin plastic TSOP II (TTP-54D)

Data Sheet E0082H10

2

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

Pin Arrangement (HM5225165B)

V
DQ0

V

CC

DQ1
DQ2

V

SS

DQ3
DQ4

V

CC

DQ5
DQ6

V

SS

DQ7

V

DQML

WE
CAS
RAS

BA0
BA1

A10

V

CC

CC

CS

A0
A1
A2
A3

CC

Q

Q

Q

Q

54-pin TSOP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

(Top view)

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

V

SS

DQ15
V

Q

SS

DQ14
DQ13

Q

V

CC

DQ12
DQ11

Q

V

SS

DQ10
DQ9

Q

V

CC

DQ8
V

SS

NC
DQMU
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V

SS

Pin Description

Pin name Function Pin name Function

A0 to A12,
BA0, BA1

DQ0 to DQ15 Data-input/output V

CS Chip select V
RAS Row address strobe command VCCQ Power for DQ circuit
CAS Column address strobe command VSSQ Ground for DQ circuit

Address input WE Write enable

Row address A0 to A12 DQMU/DQML Input/output mask
Column address A0 to A8 CLK Clock input
Bank select address BA0/BA1 (BS) CKE Clock enable

CC

SS

Power for internal circuit
Ground for internal circuit

NC No connection

Data Sheet E0082H10

3

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

Pin Arrangement (HM5225805B)

54-pin TSOP

CC

NC

NC

NC

NC

CC

NC

CS

A0
A1
A2
A3

CC

Q

Q

Q

Q

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

(Top view)

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

V

SS

DQ7
V

SS

NC
DQ6
V

CC

NC
DQ5
V

SS

NC
DQ4
V

CC

NC
V

SS

NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V

SS

Q

Q

Q

Q

V
DQ0

V

CC

DQ1

V

DQ2

V

CC

DQ3

V

CAS
RAS

BA0
BA1

SS

SS

V

WE

A10

V

Pin Description

Pin name Function Pin name Function

A0 to A12,
BA0, BA1

DQ0 to DQ7 Data-input/output V

CS Chip select V
RAS Row address strobe command VCCQ Power for DQ circuit
CAS Column address strobe command VSSQ Ground for DQ circuit

4

Address input WE Write enable

Row address A0 to A12 DQM Input/output mask
Column address A0 to A9 CLK Clock input
Bank select address BA0/BA1 (BS) CKE Clock enable

CC

SS

Power for internal circuit
Ground for internal circuit

NC No connection

Data Sheet E0082H10

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

Pin Arrangement (HM5225405B)

V

V

CC

DQ0

V

SS

V

CC

DQ1

V

SS

V

WE
CAS
RAS

BA0
BA1

A10

V

CC

NC
NC

NC
NC

NC

NC

CC

NC

CS

A0
A1
A2
A3

CC

Q

Q

Q

Q

54-pin TSOP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

(Top view)

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

V

SS

NC
V

SS

NC
DQ3
V

CC

NC
NC
V

SS

NC
DQ2
V

CC

NC
V

SS

NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V

SS

Q

Q

Q

Q

Pin Description

Pin name Function Pin name Function

A0 to A12,
BA0, BA1

DQ0 to DQ3 Data-input/output V

CS Chip select V
RAS Row address strobe command VCCQ Power for DQ circuit
CAS Column address strobe command VSSQ Ground for DQ circuit

Address input WE Write enable

Row address A0 to A12 DQM Input/output mask
Column address A0 to A9, A11 CLK Clock input
Bank select address BA0/BA1 (BS) CKE Clock enable

CC

SS

Power for internal circuit
Ground for internal circuit

NC No connection

Data Sheet E0082H10

5

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

Block Diagram (HM5225165B)

A0 to A12, BA0, BA1

Column address

counter

Row decoder

Memory array

Bank 0

Column decoder

8192 row
X 512 column
X 16 bit

Sense amplifier & I/O bus

A0 to A8

Column address

Row decoder

Memory array

Bank 1

Column decoder

8192 row
X 512 column
X 16 bit

Sense amplifier & I/O bus

Input
buffer

buffer

Output

buffer

Row address

Row decoder

Memory array

Bank 2

Column decoder

8192 row
X 512 column
X 16 bit

Sense amplifier & I/O bus

buffer

A0 to A12, BA0, BA1

Control logic &

timing generator

Refresh
counter

Row decoder

Memory array

Bank 3

Column decoder

8192 row
X 512 column
X 16 bit

Sense amplifier & I/O bus

DQ0 to DQ15

CLK

CKECSRAS

CAS

WE

DQMU

/DQML

Data Sheet E0082H10

6

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

Block Diagram (HM5225805B)

A0 to A12, BA0, BA1

Column address

counter

Row decoder

Memory array

Column decoder

8192 row
X 1024 column
X 8 bit

Sense amplifier & I/O bus

Bank 0

A0 to A9

Column address

Row decoder

Memory array

Bank 1

Column decoder

8192 row
X 1024 column
X 8 bit

Sense amplifier & I/O bus

Input
buffer

buffer

Output

buffer

Row address

Row decoder

Memory array

Column decoder

8192 row
X 1024 column
X 8 bit

Sense amplifier & I/O bus

buffer

Bank 2

A0 to A12, BA0, BA1

Control logic &

timing generator

Refresh
counter

Row decoder

Memory array

Column decoder

8192 row
X 1024 column
X 8 bit

Sense amplifier & I/O bus

Bank 3

DQ0 to DQ7

Data Sheet E0082H10

CLK

CKECSRAS

CAS

WE

DQM

7

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

Block Diagram (HM5225405B)

A0 to A12, BA0, BA1

A0 to A9, A11

A0 to A12, BA0, BA1

Column address

counter

Row decoder

Memory array

Bank 0

Column decoder

8192 row
X 2048 column
X 4 bit

Sense amplifier & I/O bus

Column address

Row decoder

Memory array

Bank 1

Column decoder

8192 row
X 2048 column
X 4 bit

Sense amplifier & I/O bus

Input
buffer

DQ0 to DQ3

buffer

Output

buffer

Row address

Row decoder

Memory array

Bank 2

Column decoder

8192 row
X 2048 column
X 4 bit

Sense amplifier & I/O bus

buffer

Control logic &

timing generator

CLK

CKECSRAS

Refresh
counter

Row decoder

Memory array

Bank 3

Column decoder

CAS

8192 row
X 2048 column
X 4 bit

Sense amplifier & I/O bus

WE

DQM

Data Sheet E0082H10

8

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

Pin Functions

CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK

rising edge.

CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.

RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional DRAMs,
they function in a different way. These pins define operation commands (read, write, etc.) depending on the
combination of their voltage levels. For details, refer to the command operation section.

A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active
command cycle CLK rising edge. Column address (AY0 to AY8; HM5225165B, AY0 to AY9;
HM5225805B, AY0 to AY9, AY11; HM5225405B) is determined by A0 to A8, A9 or A11 (A8;
HM5225165B, A9; HM5225805B, A9, A11; HM5225405B) level at the read or write command cycle CLK
rising edge. And this column address becomes burst access start address. A10 defines the precharge mode.
When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the
precharge command cycle, only the bank that is selected by BA0/BA1 (BS) is precharged. For details refer to
the command operation section.

BA0/BA1 (input pin): BA0/BA1 are bank select signal (BS). The memory array of the HM5225165B,
HM5225805B, the HM5225405B is divided into bank 0, bank 1, bank 2 and bank 3. HM5225165B contain
8192-row × 512-column × 16-bit. HM5225805B contain 8192-row × 1024-column × 8-bit. HM5225405B
contain 8192-row × 2048-column × 4-bit. If BA0 is Low and BA1 is Low, bank 0 is selected. If BA0 is Low
and BA1 is High, bank 1 is selected. If BA0 is High and BA1 is Low, bank 2 is selected. If BA0 is High and
BA1 is High, bank 3 is selected.

CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK
rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down
mode, clock suspend mode and self refresh mode.

DQM, DQMU/DQML (input pins): DQM, DQMU/DQML controls input/output buffers.

Read operation: If DQM, DQMU/DQML is High, the output buffer becomes High-Z. If the DQM,
DQMU/DQML is Low, the output buffer becomes Low-Z. (The latency of DQM, DQMU/DQML during
reading is 2 clocks.)

Write operation: If DQM, DQMU/DQML is High, the previous data is held (the new data is not written). If
DQM, DQMU/DQML is Low, the data is written. (The latency of DQM, DQMU/DQML during writing is 0
clock.)

DQ0 to DQ15 (DQ pins): Data is input to and output from these pins (DQ0 to DQ15; HM5225165B, DQ0
to DQ7; HM5225805B, DQ0 to DQ3; HM5225405B).

VCC and VCCQ (power supply pins): 3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the
output buffer.)

Data Sheet E0082H10

9

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

VSS and VSSQ (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the

output buffer.)

Command Operation

Command Truth Table

The SDRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins.

CKE

Command Symbol n - 1 n CS RAS CAS WE BA0/BA1 A10A0to A12

Ignore command DESL H × H ×××× ××
No operation NOP H × LH H H×××
Column address and read command READ H × LH L HV L V
Read with auto-precharge READ A H × LH L HV H V
Column address and write command WRIT H × LH L L V L V
Write with auto-precharge WRIT A H × LH L L V H V
Row address strobe and bank active ACTV H × LL H HV V V
Precharge select bank PRE H × LL H L V L ×
Precharge all bank PALL H × LL H L × H ×
Refresh REF/SELF H V L L L H ×××
Mode register set MRS H × LL L L V V V

Note: H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input

Ignore command [DESL]: When this command is set (CS is High), the SDRAM ignore command input at
the clock. However, the internal status is held.

No operation [NOP]: This command is not an execution command. However, the internal operations
continue.

Column address strobe and read command [READ]: This command starts a read operation. In addition,
the start address of burst read is determined by the column address (AY0 to AY8; HM5225165B, AY0 to
AY9; HM5225805B, AY0 to AY9, AY11; HM5225405B) and the bank select address (BS). After the read
operation, the output buffer becomes High-Z.

Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a
burst read with a burst length of 1, 2, 4 or 8.

Data Sheet E0082H10

10

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

Column address strobe and write command [WRIT]: This command starts a write operation. When the

burst write mode is selected, the column address (AY0 to AY8; HM5225165B, AY0 to AY9; HM5225805B,
AY0 to AY9, AY11; HM5225405B) and the bank select address (BA0/BA1) become the burst write start
address. When the single write mode is selected, data is only written to the location specified by the column
address (AY0 to AY8; HM5225165B, AY0 to AY9; HM5225805B, AY0 to AY9, AY11; HM5225405B) and
the bank select address (BA0/BA1).

Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a
burst write with a length of 1, 2, 4 or 8, or after a single write operation.

Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by
BA0/BA1 (BS) and determines the row address (AX0 to AX12). When BA0 and BA1 are Low, bank 0 is
activated. When BA0 is Low and BA1 is High, bank 1 is activated. When BA0 is High and BA1 is Low,
bank 2 is activated. When BA0 and BA1 are High, bank 3 is activated.

Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by
BA0/BA1. If BA0 and BA1 are Low, bank 0 is selected. If BA0 is Low and BA1 is High, bank 1 is selected.
If BA0 is High and BA1 is Low, bank 2 is selected. If BA0 and BA1 are High, bank 3 is selected.

Precharge all banks [PALL]: This command starts a precharge operation for all banks.

Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation,

the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.

Mode register set [MRS]: The SDRAM has a mode register that defines how it operates. The mode register
is specified by the address pins (A0 to BA0 and BA1) at the mode register set cycle. For details, refer to the
mode register configuration. After power on, the contents of the mode register are undefined, execute the
mode register set command to set up the mode register.

Data Sheet E0082H10

11

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

DQM Truth Table (HM5225165B)

CKE

Command Symbol n - 1 n DQMU DQML

Upper byte (DQ8 to DQ15) write enable/output enable ENBU H × L ×
Lower byte (DQ0 to DQ7) write enable/output enable ENBL H ××L
Upper byte (DQ8 to DQ15) write inhibit/output disable MASKU H × H ×
Lower byte (DQ0 to DQ7) write inhibit/output disable MASKL H ××H

Note: H: VIH. L: VIL. ×: VIH or VIL.

Write: I
Read: I

DQM Truth Table (HM5225805B/HM5225405B)

Command Symbol n - 1 n DQM

Write enable/output enable ENB H × L
Write inhibit/output disable MASK H × H

Note: H: VIH. L: VIL. ×: VIH or VIL.

Write: I
Read: I

is needed.

DID

is needed.

DOD

is needed.

DID

is needed.

DOD

CKE

The SDRAM can mask input/output data by means of DQM, DQMU/DQML.

DQMU masks the upper byte and DQML masks the lower byte. (HM5225165B)

During reading, the output buffer is set to Low-Z by setting DQM, DQMU/DQML to Low, enabling data
output. On the other hand, when DQM, DQMU/DQML is set to High, the output buffer becomes High-Z,
disabling data output.

During writing, data is written by setting DQM, DQMU/DQML to Low. When DQM, DQMU/DQML is set
to High, the previous data is held (the new data is not written). Desired data can be masked during burst read
or burst write by setting DQMU/DQML. For details, refer to the DQM, DQMU/DQML control section of the
SDRAM operating instructions.

12

Data Sheet E0082H10

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

CKE Truth Table

CKE

Current state Command n - 1 n CS RAS CAS WE Address

Active Clock suspend mode entry H L ЧЧЧЧЧ
Any Clock suspend L L ЧЧЧЧЧ
Clock suspend Clock suspend mode exit L H ЧЧЧЧЧ
Idle Auto-refresh command (REF) H H LLLH×
Idle Self-refresh entry (SELF) H LLLLH×
Idle Power down entry H L L H H H ×

HLH××××

Self refresh Self refresh exit (SELFX) L H L H H H ×

LHH××××

Power down Power down exit L H L H H H ×

LHH××××

Note: H: VIH. L: VIL. ×: VIH or VIL.

Clock suspend mode entry: The SDRAM enters clock suspend mode from active mode by setting CKE to
Low. If command is input in the clock suspend mode entry cycle, the command is valid. The clock suspend
mode changes depending on the current status (1 clock before) as shown below.

ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining
the bank active status.

READ suspend and READ with Auto-precharge suspend: The data being output is held (and continues to
be output).

WRITE suspend and WRIT with Auto-precharge suspend: In this mode, external signals are not
accepted. However, the internal state is held.

Clock suspend: During clock suspend mode, keep the CKE to Low.

Clock suspend mode exit: The SDRAM exits from clock suspend mode by setting CKE to High during the

clock suspend state.

IDLE: In this state, all banks are not selected, and completed precharge operation.

Auto-refresh command [REF]: When this command is input from the IDLE state, the SDRAM starts auto-

refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the
auto-refresh operation, refresh address and bank select address are generated inside the SDRAM. For every
auto-refresh cycle, the internal address counter is updated. Accordingly, 8192 times are required to refresh
the entire memory. Before executing the auto-refresh command, all the banks must be in the IDLE state. In
addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge
command is required after auto-refresh.

Data Sheet E0082H10

13

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

Self-refresh entry [SELF]: When this command is input during the IDLE state, the SDRAM starts self-

refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self­refresh is performed internally and automatically, external refresh operations are unnecessary.

Power down mode entry: When this command is executed during the IDLE state, the SDRAM enters power
down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit.

Self-refresh exit: When this command is executed during self-refresh mode, the SDRAM can exit from self­refresh mode. After exiting from self-refresh mode, the SDRAM enters the IDLE state.

Power down exit: When this command is executed at the power down mode, the SDRAM can exit from
power down mode. After exiting from power down mode, the SDRAM enters the IDLE state.

Function Truth Table

The following table shows the operations that are performed when each command is issued in each mode of
the SDRAM.

The following table assumes that CKE is high.

Current state CS RAS CAS WE Address Command Operation

Precharge H ×××× DESL Enter IDLE after t

LHHH× NOP Enter IDLE after t
L H L H BA, CA, A10 READ/READ A ILLEGAL*
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL*
L L H H BA, RA ACTV ILLEGAL*
L L H L BA, A10 PRE, PALL NOP*

6

LLLH× REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL

Idle H ×××× DESL NOP

LHHH× NOP NOP
L H L H BA, CA, A10 READ/READ A ILLEGAL*
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL*
L L H H BA, RA ACTV Bank and row active
L L H L BA, A10 PRE, PALL NOP
LLLH× REF, SELF Refresh
L L L L MODE MRS Mode register set

RP

RP

4

4

4

5

5

14

Data Sheet E0082H10

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

Current state CS RAS CAS WE Address Command Operation

Row active H ×××× DESL NOP

LHHH× NOP NOP
L H L H BA, CA, A10 READ/READ A Begin read
L H L L BA, CA, A10 WRIT/WRIT A Begin write
L L H H BA, RA ACTV Other bank active

ILLEGAL on same bank*
L L H L BA, A10 PRE, PALL Precharge
LLLH× REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL

Read H ×××× DESL Continue burst to end

LHHH× NOP Continue burst to end
L H L H BA, CA, A10 READ/READ A Continue burst read to CAS

latency and New read
L H L L BA, CA, A10 WRIT/WRIT A Term burst read/start write
L L H H BA, RA ACTV Other bank active

ILLEGAL on same bank*
L L H L BA, A10 PRE, PALL Term burst read and

Precharge
LLLH× REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL

Read with auto­precharge

H ×××× DESL Continue burst to end and

precharge
LHHH× NOP Continue burst to end and

precharge
L H L H BA, CA, A10 READ/READ A ILLEGAL*
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL*

4

4

L L H H BA, RA ACTV Other bank active

ILLEGAL on same bank*
L L H L BA, A10 PRE, PALL ILLEGAL*

4

LLLH× REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL

3

3

3

Data Sheet E0082H10

15

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

Current state CS RAS CAS WE Address Command Operation

Write H ×××× DESL Continue burst to end

LHHH× NOP Continue burst to end
L H L H BA, CA, A10 READ/READ A Term burst and New read
L H L L BA, CA, A10 WRIT/WRIT A Term burst and New write
L L H H BA, RA ACTV Other bank active

ILLEGAL on same bank*
L L H L BA, A10 PRE, PALL Term burst write and

LLLH× REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL

Write with auto-

H ×××× DESL Continue burst to end and

precharge

LHHH× NOP Continue burst to end and

L H L H BA, CA, A10 READ/READ A ILLEGAL*
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL*
L L H H BA, RA ACTV Other bank active

L L H L BA, A10 PRE, PALL ILLEGAL*
LLLH× REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL

Refresh (auto-

H ×××× DESL Enter IDLE after t

refresh)

LHHH× NOP Enter IDLE after t
L H L H BA, CA, A10 READ/READ A ILLEGAL*
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL*
L L H H BA, RA ACTV ILLEGAL*
L L H L BA, A10 PRE, PALL ILLEGAL*
LLLH× REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL

Notes: 1. H: VIH. L: VIL. ×: VIH or VIL. The other combinations are inhibit.

2. An interval of t

3. If t

is not satisfied, this operation is illegal.

RRD

is required between the final valid data input and the precharge command.

DPL

4. Illegal for same bank, except for another bank.

5. Illegal for all banks.

6. NOP for same bank, except for another bank.

Precharge*

precharge

precharge

ILLEGAL on same bank*

2

4

4

4

RC

RC

5

5

5

5

3

3

16

Data Sheet E0082H10

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

From PRECHARGE state, command operation

To [DESL], [NOP]: When these commands are executed, the SDRAM enters the IDLE state after tRP has

elapsed from the completion of precharge.

From IDLE state, command operation

To [DESL], [NOP], [PRE] or [PALL]: These commands result in no operation.

To [ACTV]: The bank specified by the address pins and the ROW address is activated.

To [REF], [SELF]: The SDRAM enters refresh mode (auto-refresh or self-refresh).

To [MRS]: The synchronous DRAM enters the mode register set cycle.

From ROW ACTIVE state, command operation

To [DESL], [NOP]: These commands result in no operation.

To [READ], [READ A]: A read operation starts. (However, an interval of t

To [WRIT], [WRIT A]: A write operation starts. (However, an interval of t

To [ACTV]: This command makes the other bank active. (However, an interval of t

is required.)

RCD

is required.)

RCD

is required.)

RRD

Attempting to make the currently active bank active results in an illegal command.

To [PRE], [PALL]: These commands set the SDRAM to precharge mode. (However, an interval of t

RAS

is

required.)

From READ state, command operation

To [DESL], [NOP]: These commands continue read operations until the burst operation is completed.

To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS

latency, the data output resulting from the next command will start.

To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.

To [ACTV]: This command makes other banks bank active. (However, an interval of t

is required.)

RRD

Attempting to make the currently active bank active results in an illegal command.

To [PRE], [PALL]: These commands stop a burst read, and the SDRAM enters precharge mode.

From READ with AUTO-PRECHARGE state, command operation

Data Sheet E0082H10

17

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and

the SDRAM then enters precharge mode.

To [ACTV]: This command makes other banks bank active. (However, an interval of t

is required.)

RRD

Attempting to make the currently active bank active results in an illegal command.

From WRITE state, command operation

To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.

To [READ], [READ A]: These commands stop a burst and start a read cycle.

To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.

To [ACTV]: This command makes the other bank active. (However, an interval of t

is required.)

RRD

Attempting to make the currently active bank active results in an illegal command.

To [PRE], [PALL]: These commands stop burst write and the SDRAM then enters precharge mode.

From WRITE with AUTO-PRECHARGE state, command operation

To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the

synchronous DRAM enters precharge mode.

To [ACTV]: This command makes the other bank active. (However, an interval of t

is required.)

RRD

Attempting to make the currently active bank active results in an illegal command.

From REFRESH state, command operation

To [DESL], [NOP]: After an auto-refresh cycle (after tRC), the SDRAM automatically enters the IDLE state.

18

Data Sheet E0082H10

Simplified State Diagram

HM5225165B/HM5225805B/HM5225405B-75/A6/B6

SELF
REFRESH

SR ENTRY

SR EXIT

WRITE
SUSPEND

WRITEA
SUSPEND

MODE
REGISTER
SET

Write

CKE_

CKE

WRITE
WITH AP

CKE_

CKE

MRS

ACTIVE

CLOCK

SUSPEND

CKE

WRITE

WRITE
WITH
AP

WRITE

READ
WITH AP

WRITEA

PRECHARGE PRECHARGE

IDLE

ACTIVE

CKE_

ROW
ACTIVE

READ

WRITE

PRECHARGE

CKE_

READ
WITH
AP

WRITE
WITH AP

REFRESH

CKE

READ

AUTO
REFRESH

IDLE
POWER
DOWN

READ

READA

CKE_

READ
WITH AP

CKE_

*1

Read

CKE

CKE

READ
SUSPEND

READA

SUSPEND

POWER
APPLIED

POWER
ON

PRECHARGE

PRECHARGE

Automatic transition after completion of command.
Transition resulting from command input.

Note: 1. After the auto-refresh operation, precharge operation is performed automatically and
enter the IDLE state.

Data Sheet E0082H10

19