ELPID HB54R5128KN-B75B, HB54R5128KN-A75B, HB54R5128KN-10B, HB54A2568KN-B75B, HB54A2568KN-A75B Datasheet

PRELIMINARY DATA SHEET

256MB DDR SDRAM S.O.DIMM

HB54A2568KN-A75B/B75B/10B

Description

The HB54A2568KN is Double Data Rate (DDR)
SDRAM Module, mounted 256M bits DDR SDRAM
(HM5425161BTT) sealed in TSOP package, and 1
piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD). The HB54A2568KN is
organized as 16M × 64 × 2 bank mounted 8 pieces of
256M bits DDR SDRAM. Read and write operations
are performed at the cross points of the CK and the
/CK. This high-speed data transfer is realized by the 2
bits prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. An outline of the products is
200-pin socket type package (dual lead out).
Therefore, it makes high density mounting possible
without surface mount technology. It provides common
data inputs and outputs. Decoupling capacitors are
mounted beside each TSOP on the module board.

(32M words

××××

64 bits, 2 Banks)

Features

• 200-pin socket type package (dual lead out)
 Outline: 67.6mm (Length) × 31.75mm (Height) ×

3.80mm (Thickness)

 Lead pitch: 0.6mm

• 2.5V power supply (VCC)

• SSTL-2 interface for all inputs and outputs

• Clock frequency: 133 MHz (max) (-A75B/B75B)

: 100 MHz (max) (-10B)

• Data inputs, outputs and DM are synchronized with
DQS

• 4 banks can operate simultaneously and
independently (Component)

• Burst read/write operation

• Programmable burst length: 2, 4, 8

 Burst read stop capability

• Programmable burst sequence

 Sequential
 Interleave

• Start addressing capability

 Even and Odd

• Programmable /CAS latency (CL): 2, 2.5

• 8192 refresh cycles: 7.8µs (8192row /64ms)

• 2 variations of refresh

 Auto refresh
 Self refresh

Document No. E0148H20 (Ver. 2.0)
Date Published April 2002 (K) Japan
URL: http://www.elpida.com

Elpida Memory, Inc. 2001-2002
Hitachi, Ltd. 2001

Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

Ordering Information

Part number

HB54A2568KN-A75B*
HB54A2568KN-B75B*
HB54A2568KN-10B*

3

Notes: 1. 143 MHz operation at /CAS latency = 2.5.

2. 100 MHz operation at /CAS latency = 2.0.

3. 125 MHz operation at /CAS latency = 2.5.

1

2

Clock frequency
MHz (max.)

133 MHz
133 MHz
100 MHz

/CAS latency Package

2.0

2.5

2.0

Pin Configurations

Front side

39 pin

1 pin

41 pin

HB54A2568KN-A75B/B75B/10B

Contact pad

200-pin dual lead out socket
type

199 pin

Gold

2 pin

40 pin

42 pin

Back side

200 pin

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

1 VREF 51 VSS 2 VREF 52 VSS

3 VSS 53 DQ19 4 VSS 54 DQ23

5 DQ0 55 DQ24 6 DQ4 56 DQ28

7 DQ1 57 VCC 8 DQ5 58 VCC

9 VCC 59 DQ25 10 VCC 60 DQ29

11 DQS0 61 DQS3 12 DM0 62 DM3

13 DQ2 63 VSS 14 DQ6 64 VSS

15 VSS 65 DQ26 16 VSS 66 DQ30

17 DQ3 67 DQ27 18 DQ7 68 DQ31

19 DQ8 69 VCC 20 DQ12 70 VCC

21 VCC 71 NC 22 VCC 72 NC

23 DQ9 73 NC 24 DQ13 74 NC

25 DQS1 75 VSS 26 DM1 76 VSS

27 VSS 77 NC 28 VSS 78 NC

29 DQ10 79 NC 30 DQ14 80 NC

31 DQ11 81 VCC 32 DQ15 82 VCC

33 VCC 83 NC 34 VCC 84 NC

35 CK0 85 NC 36 VCC 86 NC

37 /CK0 87 VSS 38 VSS 88 VSS

39 VSS 89 CK2 40 VSS 90 VSS

41 DQ16 91 /CK2 42 DQ20 92 VCC

43 DQ17 93 VCC 44 DQ21 94 VCC

45 VCC 95 CKE1 46 VCC 96 CKE0

47 DQS2 97 NC 48 DM2 98 NC

49 DQ18 99 A12 50 DQ22 100 A11

Preliminary Data Sheet E0148H20 (Ver. 2.0)

2

HB54A2568KN-A75B/B75B/10B

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

101 A9 151 DQ42 102 A8 152 DQ46

103 VSS 153 DQ43 104 VSS 154 DQ47

105 A7 155 VCC 106 A6 156 VCC

107 A5 157 VCC 108 A4 158 /CK1

109 A3 159 VSS 110 A2 160 CK1

111 A1 161 VSS 112 A0 162 VSS

113 VCC 163 DQ48 114 VCC 164 DQ52

115 A10/AP 165 DQ49 116 BA1 166 DQ53

117 BA0 167 VCC 118 /RAS 168 VCC

119 /WE 169 DQS6 120 /CAS 170 DM6

121 /S0 171 DQ50 122 /S1 172 DQ54

123 NC 173 VSS 124 NC 174 VSS

125 VSS 175 DQ51 126 VSS 176 DQ55

127 DQ32 177 DQ56 128 DQ36 178 DQ60

129 DQ33 179 VCC 130 DQ37 180 VCC

131 VCC 181 DQ57 132 VCC 182 DQ61

133 DQS4 183 DQS7 134 DM4 184 DM7

135 DQ34 185 VSS 136 DQ38 186 VSS

137 VSS 187 DQ58 138 VSS 188 DQ62

139 DQ35 189 DQ59 140 DQ39 190 DQ63

141 DQ40 191 VCC 142 DQ44 192 VCC

143 VCC 193 SDA 144 VCC 194 SA0

145 DQ41 195 SCL 146 DQ45 196 SA1

147 DQS5 197 VCCSPD 148 DM5 198 SA2

149 VSS 199 VCCID 150 VSS 200 NC

Preliminary Data Sheet E0148H20 (Ver. 2.0)

3

HB54A2568KN-A75B/B75B/10B

Pin Description

Pin name Function

Address input

A0 to A12

BA0, BA1 Bank select address

DQ0 to DQ63 Data input/output

/RAS Row address strobe command

/CAS Column address strobe command

/WE Write enable

/S0, /S1 Chip select

CKE0, CKE1 Clock enable

CK0 to CK2 Clock input

/CK0 to /CK2 Differential clock input

DQS0 to DQS7 Input and output data strobe

DM0 to DM7 Input mask

SCL Clock input for serial PD

SDA Data input/output for serial PD

SA0 to SA2 Serial address input

VCC Power for internal circuit

VCCSPD Power for serial EEPROM

VREF Input reference voltage

VSS Ground

VCCID VCC identification flag

NC No connection

Row address A0 to A12
Column address A0 to A8

Preliminary Data Sheet E0148H20 (Ver. 2.0)

4

HB54A2568KN-A75B/B75B/10B

Serial PD Matrix*

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

0

1

2 Memory type 0 0 0 0 0 1 1 1 07 SDRAM DDR

3 Number of row address 0 0 0 0 1 1 0 1 0D 13

4 Number of column address 0 0 0 0 1 0 0 1 09 9

5 Number of DIMM banks 0 0 0 0 0 0 1 0 02 2

6 Module data width 0 1 0 0 0 0 0 0 40 64 bits

7 Module data width continuation 0 0 0 0 0 0 0 0 00 0 (+)

8 Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04 SSTL 2.5V

9

-B75B 0 1 1 1 0 1 0 1 75

-10B 1 0 0 0 0 0 0 0 80

10

-10B 1 0 0 0 0 0 0 0 80 0.8ns*5

11 DIMM configuration type 0 0 0 0 0 0 0 0 00 Non-parity

12 Refresh rate/type 1 0 0 0 0 0 1 0 82

13 Primary SDRAM width 0 0 0 1 0 0 0 0 10 × 16

14 Error checking SDRAM width 0 0 0 0 0 0 0 0 00 Not used

15

16

17

18

19

20

21 SDRAM module attributes 0 0 1 0 0 0 0 0 20 Unbuffered

22 SDRAM device attributes: General 1 0 0 0 0 0 0 0 80 ± 0.2V

23

-B75B/10B 1 0 1 0 0 0 0 0 A0

24

-10B 1 0 0 0 0 0 0 0 80 0.8ns*5

25

26

27 Minimum row precharge time (tRP) 0 1 0 1 0 0 0 0 50 20ns

Number of bytes utilized by module
manufacturer

Total number of bytes in serial PD
device

DDR SDRAM cycle time, CL = X

-A75B

SDRAM access from clock (tAC)

-A75B/B75B

SDRAM device attributes:
Minimum clock delay back-to-back
column access

SDRAM device attributes:
Burst length supported

SDRAM device attributes: Number of
banks on SDRAM device

SDRAM device attributes:
/CAS latency

SDRAM device attributes:
/CS latency

SDRAM device attributes:
/WE latency

Minimum clock cycle time at
CLX - 0.5

-A75B

Maximum data access time (tAC) from
clock at CLX - 0.5

-A75B/B75B

Minimum clock cycle time at
CLX - 1

Maximum data access time (tAC) from
clock at CLX - 1

1

1 0 0 0 0 0 0 0 80 128

0 0 0 0 1 0 0 0 08 256 byte

0 1 1 1 0 0 0 0 70 CL = 2.5*5

0 1 1 1 0 0 0 0 70 0.7ns*5

7.8 µs
Self refresh

0 0 0 0 0 0 0 1 01 1 CLK

0 0 0 0 1 1 1 0 0E 2, 4, 8

0 0 0 0 0 1 0 0 04 4

0 0 0 0 1 1 0 0 0C 2, 2.5

0 0 0 0 0 0 0 1 01 0

0 0 0 0 0 0 1 0 02 1

0 1 1 1 0 1 0 1 75 CL = 2*5

0 1 1 1 0 0 0 0 70 0.7ns*5

0 0 0 0 0 0 0 0 00

0 0 0 0 0 0 0 0 00

Preliminary Data Sheet E0148H20 (Ver. 2.0)

5