ELPID HB54A5129F1U-B75B, HB54A5129F1U-A75B, HB54A5129F1U-10B Datasheet

DATA SHEET

512MB Registered DDR SDRAM DIMM

HB54A5129F1U-A75B/B75B/10B

Description

The HB54A5129F1U is a 64M × 72 × 1 bank Double

Data Rate (DDR) SDRAM Module, mounted 18 pieces
of 256Mbits DDR SDRAM (HM5425401BTT) sealed in
TSOP package, 1 piece of PLL clock driver, 2 pieces of
register driver and 1 piece of serial EEPROM (2k bits
EEPROM) for Presence Detect (PD). Read and write
operations are performed at the cross points of the CK
and the /CK. This high-speed data transfer is realized
by the 2-bit prefetch-pipelined architecture. Data
strobe (DQS) both for read and write are available for
high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. An outline of
the products is 184-pin socket type package (dual lead
out). Therefore, it makes high density mounting
possible without surface mount technology. It provides
common data inputs and outputs. Decoupling
capacitors are mounted beside each TSOP on the
module board.

Features

• 184-pin socket type package (dual lead out)
 Outline: 133.35mm (Length) × 30.48mm (Height) ×

 Lead pitch: 1.27mm

• 2.5V power supply (VCC/VCCQ)

• SSTL-2 interface for all inputs and outputs

• Clock frequency: 143MHz/133MHz/125MHz (max.)

• Data inputs and outputs are synchronized with DQS

• 4 banks can operate simultaneously and

• Burst read/write operation

• Programmable burst length: 2, 4, 8
 Burst read stop capability

• Programmable burst sequence
 Sequential
 Interleave

• Start addressing capability
 Even and Odd

• Programmable /CAS latency (CL): 3, 3.5

• 8192 refresh cycles: 7.8µs (8192/64ms)

• 2 variations of refresh
 Auto refresh
 Self refresh

(64M words

4.00mm (Thickness)

independently (Component)

××××

72 bits, 1 Bank)

Document No. E0191H30 (Ver. 3.0)
Date Published September 2002 (K) Japan

URL: http://www.elpida.com
Elpida Memory,Inc. 2001-2002

Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

HB54A5129F1U-A75B/B75B/10B

Ordering Information

Part number

HB54A5129F1U-A75B*
HB54A5129F1U-B75B*
HB54A5129F1U-10B*

Notes: 1. 143MHz operation at /CAS latency = 3.5.

2. 100MHz operation at /CAS latency = 3.0.

3. 125MHz operation at /CAS latency = 3.5.

Pin Configurations

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

1 VREF 47 DQS8 93 VSS 139 VSS

2 DQ0 48 A0 94 DQ4 140 DM8/DQS17

3 VSS 49 CB2 95 DQ5 141 A10

4 DQ1 50 VSS 96 VCCQ 142 CB6

5 DQS0 51 CB3 97 DM0/DQS9 143 VCCQ

6 DQ2 52 BA1 98 DQ6 144 CB7

7 VCC 53 DQ32 99 DQ7 145 VSS

8 DQ3 54 VCCQ 100 VSS 146 DQ36

9 NC 55 DQ33 101 NC 147 DQ37

10 /RESET 56 DQS4 102 NC 148 VCC

11 VSS 57 DQ34 103 NC 149 DM4/DQS13

12 DQ8 58 VSS 104 VCCQ 150 DQ38

13 DQ9 59 BA0 105 DQ12 151 DQ39

14 DQS1 60 DQ35 106 DQ13 152 VSS

15 VCCQ 61 DQ40 107 DM1/DQS10 153 DQ44

16 NC 62 VCCQ 108 VCC 154 /RAS

17 NC 63 /WE 109 DQ14 155 DQ45

18 VSS 64 DQ41 110 DQ15 156 VCCQ

19 DQ10 65 /CAS 111 NC 157 /S0

20 DQ11 66 VSS 112 VCCQ 158 NC

21 CKE0 67 DQS5 113 NC 159 DM5/DQS14

22 VCCQ 68 DQ42 114 DQ20 160 VSS

23 DQ16 69 DQ43 115 A12 161 DQ46

24 DQ17 70 VCC 116 VSS 162 DQ47

25 DQS2 71 NC 117 DQ21 163 NC

26 VSS 72 DQ48 118 A11 164 VCCQ

27 A9 73 DQ49 119 DM2/DQS11 165 DQ52

28 DQ18 74 VSS 120 VCC 166 DQ53

Clock frequency
MHz (max.)

1

133

2

133
100

/CE latency

3.0

3.5

3.0

Front side

1 pin

93 pin 144 pin 145 pin184 pin

Back side

Package

184-pin dual lead out socket
type

52 pin53 pin 92 pin

Contact pad

Gold

Data Sheet E0191H30 (Ver. 3.0)

2

HB54A5129F1U-A75B/B75B/10B

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

29 A7 75 NC 121 DQ22 167 NC

30 VCCQ 76 NC 122 A8 168 VCC

31 DQ19 77 VCCQ 123 DQ23 169 DM6/DQS15

32 A5 78 DQS6 124 VSS 170 DQ54

33 DQ24 79 DQ50 125 A6 171 DQ55

34 VSS 80 DQ51 126 DQ28 172 VCCQ

35 DQ25 81 VSS 127 DQ29 173 NC

36 DQS3 82 VCCID 128 VCCQ 174 DQ60

37 A4 83 DQ56 129 DM3/DQS12 175 DQ61

38 VCC 84 DQ57 130 A3 176 VSS

39 DQ26 85 VCC 131 DQ30 177 DM7/DQS16

40 DQ27 86 DQS7 132 VSS 178 DQ62

41 A2 87 DQ58 133 DQ31 179 DQ63

42 VSS 88 DQ59 134 CB4 180 VCCQ

43 A1 89 VSS 135 CB5 181 SA0

44 CB0 90 NC 136 VCCQ 182 SA1

45 CB1 91 SDA 137 CK0 183 SA2

46 VCC 92 SCL 138 /CK0 184 VCCSPD

Data Sheet E0191H30 (Ver. 3.0)

3

HB54A5129F1U-A75B/B75B/10B

Pin Description

Pin name Function

Address input

A0 to A12

BA0, BA1 Bank select address

DQ0 to DQ63 Data input/output

CB0 to CB7 Check bit (Data input/output)

/RAS Row address strobe command

/CAS Column address strobe command

/WE Write enable

/S0 Chip select

CKE0 Clock enable

CK0 Clock input

/CK0 Differential clock input

DQS0 to DQS8 Input and output data strobe

DM0 to DM8/DQS9 to DQS17 Input and output data strobe

SCL Clock input for serial PD

SDA Data input/output for serial PD

SA0 to SA2 Serial address input

VCC Power for internal circuit

VCCQ Power for DQ circuit

VCCSPD Power for serial EEPROM

VREF Input reference voltage

VSS Ground

VCCID VCC identification flag

/RESET Reset pin (forces register inputs low)

NC No connection

Row address A0 to A12
Column address A0 to A9, A11

Data Sheet E0191H30 (Ver. 3.0)

4

HB54A5129F1U-A75B/B75B/10B

Serial PD Matrix*

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

0

1

2 Memory type 0 0 0 0 0 1 1 1 07 SDRAM DDR

3 Number of row address 0 0 0 0 1 1 0 1 0D 13

4 Number of column address 0 0 0 0 1 0 1 1 0B 11

5 Number of DIMM banks 0 0 0 0 0 0 0 1 01 1

6 Module data width 0 1 0 0 1 0 0 0 48 72 bits

7 Module data width continuation 0 0 0 0 0 0 0 0 00 0 (+)

8 Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04 SSTL 2.5V

9

-B75B 0 1 1 1 0 1 0 1 75

-10B 1 0 0 0 0 0 0 0 80

10

-10B 1 0 0 0 0 0 0 0 80 0.8ns*5

11 DIMM configuration type 0 0 0 0 0 0 1 0 02 ECC

12 Refresh rate/type 1 0 0 0 0 0 1 0 82

13 Primary SDRAM width 0 0 0 0 0 1 0 0 04 × 4
14 Error checking SDRAM width 0 0 0 0 0 1 0 0 04 × 4

15

16

17

18

19

20

21 SDRAM module attributes 0 0 1 0 0 1 1 0 26 Registered

22 SDRAM device attributes: General 1 1 0 0 0 0 0 0 C0 ± 0.2V

23

-B75B/10B 1 0 1 0 0 0 0 0 A0

24

-10B 1 0 0 0 0 0 0 0 80 0.8ns*5

25

26

27 Minimum row precharge time (tRP) 0 1 0 1 0 0 0 0 50 20ns

Number of bytes utilized by module
manufacturer

Total number of bytes in serial PD
device

DDR SDRAM cycle time, CL = X

-A75B

SDRAM access from clock (tAC)

-A75B/B75B

SDRAM device attributes:
Minimum clock delay back-to-back
column access

SDRAM device attributes:
Burst length supported

SDRAM device attributes: Number of
banks on SDRAM device

SDRAM device attributes:
/CAS latency

SDRAM device attributes:
/CS latency

SDRAM device attributes:
/WE latency

Minimum clock cycle time at
CLX - 0.5

-A75B

Maximum data access time (tAC) from
clock at CLX - 0.5

-A75B/B75B

Minimum clock cycle time at
CLX - 1

Maximum data access time (tAC) from
clock at CLX - 1

1

1 0 0 0 0 0 0 0 80 128

0 0 0 0 1 0 0 0 08 256 byte

0 1 1 1 0 0 0 0 70 CL = 2.5*5

0 1 1 1 0 1 0 1 75 0.75ns*5

7.8 µs
Self refresh

0 0 0 0 0 0 0 1 01 1 CLK

0 0 0 0 1 1 1 0 0E 2, 4, 8

0 0 0 0 0 1 0 0 04 4

0 0 0 0 1 1 0 0 0C 2/2.5

0 0 0 0 0 0 0 1 01 0

0 0 0 0 0 0 1 0 02 1

0 1 1 1 0 1 0 1 75 CL = 2*5

0 1 1 1 0 1 0 1 75 0.75ns*5

0 0 0 0 0 0 0 0 00

0 0 0 0 0 0 0 0 00

Data Sheet E0191H30 (Ver. 3.0)

5