ELPID HB52R1289E22-B6B, HB52R1289E22-A6B Datasheet

HB52R1289E22-A6B/B6B

1 GB Registered SDRAM DIMM

128-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module

(36 pcs of 64 M × 4 Components)

PC100 SDRAM

E0017H20 (Ver. 2.0)

Aug. 20, 2001 (K)

Description

The HB52R1289E22 belongs to 8-byte DIMM (Dual In-line Memory Module) family, and has been
developed as an optimized main memory solution for 8-byte processor applications. The HB52R1289E22 is a
64M × 72 × 2-bank Synchronous Dynamic RAM Module, mounted 36 pieces of 256-Mbit SDRAM
(HM5225405BTB) sealed in TCP package, 1 piece of PLL clock driver, 3 pieces register driver and 1 piece of
serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52R1289E22 is 168-pin socket type
package (dual lead out). Therefore, the HB52R1289E22 makes high density mounting possible without
surface mount technology. The HB52R1289E22 provides common data inputs and outputs. Decoupling
capacitors are mounted beside TCP on the module board.

Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would

be electrical defects.

Features

• Fully compatible with : JEDEC standard outline 8-byte DIMM

: Intel PCB Reference design (Rev. 1.2)

• 168-pin socket type package (dual lead out)
 Outline: 133.37 mm (length) × 38.10 mm (Height) × 4.80 mm (Thickness)
 Lead pitch: 1.27 mm

• 3.3 V power supply

• Clock frequency: 100 MHz (max)

• LVTTL interface

• Data bus width: × 72 ECC

• Single pulsed RAS

• 4 Banks can operates simultaneously and independently

• Burst read/write operation and burst read/single write operation capability

• Programmable burst length: 1/2/4/8

Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

HB52R1289E22-A6B/B6B

• 2 variations of burst sequence
 Sequential
 Interleave

• Programmable CE latency: 3/4 (HB52R1289E22-A6B)

: 4 (HB52R1289E22-B6B)

• Byte control by DQMB

• Refresh cycles: 8192 refresh cycles/64 ms

• 2 variations of refresh
 Auto refresh
 Self refresh

Ordering Information

Type No. Frequency CE latency Package Contact pad

HB52R1289E22-A6B 100 MHz 3/4 168-pin dual lead out socket type Gold
HB52R1289E22-B6B 100 MHz 4

Pin Arrangement

1 pin 10 pin11 pin 40 pin 41 pin 84 pin

85 pin 94 pin 95 pin 124 pin 125 pin 168 pin

Data Sheet E0017H20

2

HB52R1289E22-A6B/B6B

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

1V

SS

43 V

SS

2 DQ0 44 NC 86 DQ32 128 CKE0
3 DQ1 45 S2 87 DQ33 129 S3
4 DQ2 46 DQMB2 88 DQ34 130 DQMB6
5 DQ3 47 DQMB3 89 DQ35 131 DQMB7
6VCC48 NC 90 V
7 DQ4 49 V

CC

8 DQ5 50 NC 92 DQ37 134 NC
9 DQ6 51 NC 93 DQ38 135 NC
10 DQ7 52 CB2 94 DQ39 136 CB6
11 DQ8 53 CB3 95 DQ40 137 CB7
12 V

SS

54 V

SS

13 DQ9 55 DQ16 97 DQ41 139 DQ48
14 DQ10 56 DQ17 98 DQ42 140 DQ49
15 DQ11 57 DQ18 99 DQ43 141 DQ50
16 DQ12 58 DQ19 100 DQ44 142 DQ51
17 DQ13 59 V
18 V

CC

60 DQ20 102 V

CC

19 DQ14 61 NC 103 DQ46 145 NC
20 DQ15 62 NC 104 DQ47 146 NC
21 CB0 63 NC 105 CB4 147 REGE
22 CB1 64 V
23 V

SS

65 DQ21 107 V

SS

24 NC 66 DQ22 108 NC 150 DQ54
25 NC 67 DQ23 109 NC 151 DQ55
26 V

CC

68 V

SS

27 W 69 DQ24 111 CE 153 DQ56
28 DQMB0 70 DQ25 112 DQMB4 154 DQ57
29 DQMB1 71 DQ26 113 DQMB5 155 DQ58
30 S0 72 DQ27 114 S1 156 DQ59
31 NC 73 V
32 V

SS

74 DQ28 116 V

CC

33 A0 75 DQ29 117 A1 159 DQ61
34 A2 76 DQ30 118 A3 160 DQ62
35 A4 77 DQ31 119 A5 161 DQ63

85 V

SS

CC

127 V

132 NC

91 DQ36 133 V

96 V

SS

138 V

101 DQ45 143 V

CC

144 DQ52

106 CB5 148 V

149 DQ53

152 V

110 V

SS

CC

115 RE 157 V

SS

158 DQ60

SS

CC

SS

CC

SS

SS

CC

Data Sheet E0017H20

3

HB52R1289E22-A6B/B6B

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

36 A6 78 V

SS

37 A8 79 CK2 121 A9 163 CK3
38 A10 (AP) 80 NC 122 BA0 164 NC
39 BA1 81 WP 123 A11 165 SA0
40 V
41 V

CC

CC

42 CK0 84 V

82 SDA 124 V
83 SCL 125 CK1 167 SA2

CC

Pin Description

Pin name Function

A0 to A12 Address input

BA0/BA1 Bank select address BA0/BA1
DQ0 to DQ63 Data input/output
CB0 to CB7 Check bit (Data input/output)

S0 to S3 Chip select input
RE Row enable (RAS) input
CE Column enable (CAS) input
W Write enable input

DQMB0 to DQMB7 Byte data mask
CK0 to CK3 Clock input
CKE0 Clock enable input
WP Write protect for serial PD

1

REGE*
SDA Data input/output for serial PD
SCL Clock input for serial PD
SA0 to SA2 Serial address input
V

CC

V

SS

NC No connection
Note: 1. REGE ≥ VIH: Register mode.

REGE ≤ V

: Buffer mode.

IL

Register/Buffer enable

Primary positive power supply
Ground

120 A7 162 V

CC

166 SA1

126 A12 168 V

Row address A0 to A12
Column address A0 to A9, A11

SS

CC

Data Sheet E0017H20

4

HB52R1289E22-A6B/B6B

Serial PD Matrix*

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

0 Number of bytes used by

module manufacturer
1 Total SPD memory size 0000100008 256 byte
2 Memory type 0000010004 SDRAM
3 Number of row addresses bits 000011010D 13
4 Number of column addresses

bits
5 Number of banks 0000001002 2
6 Module data width 0100100048 72 bit
7 Module data width (continued) 0000000000 0 (+)
8 Module interface signal levels 0000000101 LVTTL
9 SDRAM cycle time

(highest CE latency)

10 ns
10 SDRAM access from Clock

(highest CE latency)

6 ns
11 Module configuration type 0000001002 ECC
12 Refresh rate/type 1000001082 Normal

13 SDRAM width 0000010004 64M × 4
14 Error checking SDRAM width 0000010004 × 4
15 SDRAM device attributes:

minimum clock delay for back-to-

back random column addresses
16 SDRAM device attributes:

Burst lengths supported
17 SDRAM device attributes:

number of banks on SDRAM

device
18 SDRAM device attributes:

CE latency

(-A6B)

(-B6B) 0000010004 3
19 SDRAM device attributes:

S latency

1

1000000080 128

000010110B 11

10100000A0 CL = 3

0110000060 *

0000000101 1 CLK

000011110F 1, 2, 4, 8

0000010004 4

0000011006 2/3

0000000101 0

3

(7.8125 µs)
Self refresh

Data Sheet E0017H20

5

HB52R1289E22-A6B/B6B

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

20 SDRAM device attributes:

W latency
21 SDRAM device attributes 000111111F Registered
22 SDRAM device attributes:

General
23 SDRAM cycle time

(2nd highest CE latency)

(-A6B) 10 ns
(-B6B) Undefined 0000000000

24 SDRAM access from Clock

(2nd highest CE latency)

(-A6B) 6 ns
(-B6B) Undefined 0000000000

25 SDRAM cycle time

(3rd highest CE latency)

Undefined
26 SDRAM access from Clock

(3rd highest CE latency)

Undefined
27 Minimum row precharge time 0001010014 20 ns
28 Row active to row active min 0001010014 20 ns
29 RE to CE delay min 0001010014 20 ns
30 Minimum RE pulse width 0011001032 50 ns
31 Density of each bank on module 1000000080 2 bank

32 Address and command signal

input setup time
33 Address and command signal

input hold time
34 Data signal input setup time 0010000020 2 ns*
35 Data signal input hold time 0001000010 1 ns*
36 to 61 Superset information 0000000000 Future use
62 SPD data revision code 0001001012 Rev. 1.2A
63 Checksum for bytes 0 to 62

(-A6B)

(-B6B) 0010001022 34
64 Manufacturer’s JEDEC ID code 0000011107 HITACHI
65 to 71 Manufacturer’s JEDEC ID code 0000000000
72 Manufacturing location ЧЧЧЧЧЧЧЧЧ× *4 (ASCII-

0000000101 0

000011100E VCC ± 10%

10100000A0 CL = 2

0110000060

0000000000

0000000000

512M byte

0010000020 2 ns*

0001000010 1 ns*

3

3

3

3

0010010024 36

8bit code)

Data Sheet E0017H20

6