ELPID EDS2508APTA-7ATI, EDS2508APTA-75TI, EDS2516APTA-7ATI, EDS2516APTA-75TI, EDS2504APTA-7ATI Datasheet
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PRELIMINARY DATA SHEET
256M bits SDRAM
WTR (Wide Temperature Range)
EDS2504APTA-TI (64M words ×××× 4 bits)
EDS2508APTA-TI (32M words ×××× 8 bits)
EDS2516APTA-TI (16M words ×××× 16 bits)
Description
The EDS2504AP is a 256M bits SDRAM organized as
16,777,216 words × 4 bits × 4 banks. The EDS2508
AP is a 256M bits SDRAM organized as 8,388,608
words × 8 bits × 4 banks. The EDS2516 AP is a 256M
bits SDRAM organized as 4194304 words × 16 bits × 4
banks. All inputs and outputs are referred to the rising
edge of the clock input. It is packaged in standard 54pin plastic TSOP (II).
Features
• 3.3V power supply
• Clock frequency: 133MHz (max.)
• LVTTL interface
• Single pulsed /RAS
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8, full page
• 2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8)
Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQM
: DQM (EDS2504/08AP)
: UDQM, LDQM (EDS2516AP)
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
• Ambient temperature range: –40 to +85°C
Pin Configurations
/xxx indicates active low signal.
54-pin TSOP
VDD
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
VDD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
A0 to A12,
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
(Top view)
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
LDQM
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
X 16
X 8
X 4
VSS
54
DQ15
53
VSSQ
52
DQ14
51
DQ13
50
VDDQ
49
DQ12
48
DQ11
47
VSSQ
46
DQ10
45
DQ9
44
VDDQ
43
DQ8
42
VSS
41
NC
40
UDQM
39
CLK
38
CKE
37
A12
36
A11
35
A9
34
A8
33
A7
32
A6
31
A5
30
A4
29
VSS
28
Input/output mask
DQM
Clock enable
CKE
Clock input
CLK
Power for internal circuit
VDD
Ground for internal circuit
VSS
Power for DQ circuit
VDDQ
Ground for DQ circuit
VSSQ
No connection
NC
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Document No. E0248E10 (Ver. 1.0)
Date Published March 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002
Ordering Information
Part number
EDS2504APTA-7ATI
EDS2504APTA-75TI
EDS2508APTA-7ATI
EDS2508APTA-75TI
EDS2516APTA-7ATI
EDS2516APTA-75TI
Part Number
Elpida Memory
Material Type
D: Mono
Function
S: SDRAM
Mask
Version
P 64M × 4 4 133
32M × 8
16M × 16
EDS2504APTA/08APTA/16APTA-TI
Organization
(words × bits)
Internal Banks
Clock frequency
MHz (max.)
/CAS latency Package
2, 3
3
2, 3
3
2, 3
3
54-pin Plastic
TSOP (II)
E D S 25 04 A P TA - 7A TI
Density & Bank
25: 256M/4 Banks
Bit Organization
04: x4
08: x8
16: x16
Interface
A: 3.3V, LVTTL
Mask Revision
Package
TA: TSOP (II)
Speed
7A: 133MHz/CL2, 3
75: 133MHz/CL3
100MHz/CL2
Wide Temperature Range
TI: −40 to +85°C
Preliminary Data Sheet E0248E10 (Ver. 1.0)
2
CONTENTS
EDS2504APTA/08APTA/16APTA-TI
Description .................................................................................................................................................... 1
Features ........................................................................................................................................................1
Pin Configurations ......................................................................................................................................... 1
Ordering Information .....................................................................................................................................2
Part Number .................................................................................................................................................. 2
Electrical Specifications................................................................................................................................. 4
Block Diagram ............................................................................................................................................... 8
Pin Function ................................................................................................................................................ 13
Command Operation ................................................................................................................................... 15
Simplified State Diagram............................................................................................................................. 23
Mode Register Configuration ...................................................................................................................... 24
Power-up sequence .................................................................................................................................... 25
Operation of the SDRAM ............................................................................................................................ 26
Timing Waveforms ...................................................................................................................................... 42
Package Drawing ........................................................................................................................................48
Recommended Soldering Conditions.......................................................................................................... 49
Revision History .......................................................................................................................................... 52
Preliminary Data Sheet E0248E10 (Ver. 1.0)
3
EDS2504APTA/08APTA/16APTA-TI
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute Power on sequence and CBR (auto) Refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter Symbol Rating Unit Note
Voltage on any pin relative to VSS VT –0.5 to VDD + 0.5 (≤ 4.6 (max.)) V
Supply voltage relative to VSS VDD –0.5 to +4.6 V
Short circuit output current IOS 50 mA
Power dissipation PD 1.0 W
Operating temperature TA –40 to +85 °C
Storage temperature Tstg –55 to +125 °C
Notes: 1. Respect to VSS.
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions (TA = –40 to +85°°°°C)
Parameter Symbol min. max. Unit Notes
Supply voltage VDD, VDDQ 3.0 3.6 V 1, 2
VSS, VSSQ 0 0 V 3
Input high voltage VIH 2.0 VDD + 0.3 V 1, 4
Input low voltage VIL –0.3 0.8 V 1, 5
Notes: 1. All voltage referred to VSS.
2. The supply voltage with all VDD and VDDQ pins must be on the same level.
3. The supply voltage with all VSS and VSSQ pins must be on the same level.
4. VIH (max.) = VDD + 2.0 V for pulse width ≤ 3ns at VDD.
5. VIL (min.) = VSS – 2.0 V for pulse width ≤ 3ns at VSS.
Preliminary Data Sheet E0248E10 (Ver. 1.0)
4
EDS2504APTA/08APTA/16APTA-TI
DC Characteristics 1 (TA = –40 to +85°°°°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter max.
/CAS latency Symbol Grade × 4 × 8 × 16 Unit Test condition Notes
Operating current ICC1 -7A 130 130 135 mA
ICC1 -75 110 110 115 mA
Standby current in power
down
Standby current in power
down (input signal stable)
Standby current in non
power down
Standby current in non
power down (input signal
stable)
Active standby current in
power down
Active standby current in
power down (input signal
stable)
Active standby current in
non power down
Active standby current in
non power down (input
signal stable)
Burst operating current ICC4 130 135 145 mA tCK = min., BL = 4 1, 2, 5
Refresh current ICC5 -7A 250 250 250 mA tRC = min. 3
ICC5 -75 220 220 220 mA tRC = min.
Self refresh current ICC6 3 3 3 mA
ICC2P 3 3 3 mA CKE = VIL, tCK = min. 6
ICC2PS 2 2 2 mA CKE = VIL, tCK = ∞ 7
ICC2N 20 20 20 mA
ICC2NS 9 9 9 mA
ICC3P 4 4 4 mA CKE = VIL, tCK = min. 1, 2, 6
ICC3PS 3 3 3 mA CKE = VIL, tCK = ∞ 2, 7
ICC3N 30 30 30 mA
ICC3NS 15 15 15 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Burst length = 1
tRC = min.
Burst length = 1
tRC = min.
CKE, /CS = VIH,
tCK = min.
CKE = VIH, tCK = ∞,
/CS = VIH
CKE, /CS = VIH,
tCK = min.
CKE = VIH, tCK = ∞,
/CS = VIH
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
1, 2, 3
4
8
1, 2, 4
2, 8
Preliminary Data Sheet E0248E10 (Ver. 1.0)
5
EDS2504APTA/08APTA/16APTA-TI
DC Characteristics 2 (TA = –40 to +85°°°°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter Symbol min. max. Unit Test condition Notes
Input leakage current ILI –1 1 µA 0 ≤ VIN ≤ VDD
Output leakage current ILO –1.5 1.5 µA 0 ≤ VOUT ≤ VDD, DQ = disable
Output high voltage VOH 2.4 — V IOH = –4 mA
Output low voltage VOL — 0.4 V IOL = 4 mA
Pin Capacitance (TA = 25°C, VDD, VDDQ = 3.3V ± 0.3V)
Parameter Symbol Pins min. Typ max. Unit
Input capacitance CI1 CLK 2.5 — 3.5 pF
CI2
Data input/output capacitance CI/O DQ 4 — 6.5 pF
Address, CKE, /CS, /RAS,
/CAS, /WE, DQM,
2.5 — 3.8 pF
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1MHz, 1.4V bias, 200mV swing.
3. DQM = VIH to disable DOUT.
4. This parameter is sampled and not 100% tested.
Notes
1, 2, 4
1, 2, 4
1, 2, 3, 4
AC Characteristics (TA = –40 to +85°°°°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
-7A -75
Parameter Symbol min. min. max. Unit Notes
System clock cycle time tCK 7.5 7.5 — ns 1
CLK high pulse width tCH 2.5 2.5 — ns 1
CLK low pulse width tCL 2.5 2.5 — ns 1
Access time from CLK tAC — — 5.4 ns 1, 2
Data-out hold time tOH 2.7 2.7 — ns 1, 2
CLK to Data-out low impedance tLZ 1 1 — ns 1, 2, 3
CLK to Data-out high impedance tHZ — — 5.4 ns 1, 4
Input setup time tSI 1.5 1.5 — ns 1
Input hold time tHI 0.8 0.8 — ns 1
Ref/Active to Ref/Active command period tRC 60 67.5 — ns 1
Active to Precharge command period tRAS 45 45 120000 ns 1
Active command to column command
(same bank)
Precharge to active command period tRP 15 20 — ns 1
Write recovery or data-in to precharge
lead time
Last data into active latency tDAL 2CLK + 15ns 2CLK + 20ns —
Active (a) to Active (b) command period tRRD 15 15 — ns 1
Transition time (rise and fall) tT 0.5 0.5 5 ns
Refresh period
(8192 refresh cycles)
tRCD 15 20 — ns 1
tDPL 15 15 — ns 1
tREF — — 64 ms
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.
2. Access time is measured at 1.4V. Load condition is CL = 50pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Preliminary Data Sheet E0248E10 (Ver. 1.0)
6
EDS2504APTA/08APTA/16APTA-TI
Test Conditions
• Input and output timing reference levels: 1.4V
• Input waveform and output load: See following figures
2.4 V
0.4 V
2.0 V
0.8 V
t
T
tT
input
Output load
Relationship Between Frequency and Minimum Latency
Parameter -7A -75
Frequency (MHz) 133
tCK (ns) Symbol 7.5 7.5 Notes
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
Self refresh exit time lSREX 1 1 2
Last data in to active command
(Auto precharge, same bank)
Self refresh exit to command input lSEC 8 9
Precharge command to high impedance
(CL = 2)
(CL = 3) lHZP 3 3
Last data out to active command
(auto precharge) (same bank)
Last data out to precharge (early precharge)
(CL = 2)
(CL = 3) lEP –2 –2
Column command to column command lCCD 1 1
Write command to data in latency lWCD 0 0
DQM to data in lDID 0 0
DQM to data out lDOD 2 2
CKE to CLK disable lCLE 1 1
Register set to active command lMRD 2 2
/CS to command disable lCDD 0 0
Power down exit to command input lPEC 1 1
lRCD 2 3 1
lRC 8 9 1
lRAS 6 6 1
lRP 2 3 1
lDPL 2 2 1
lRRD 2 2 1
lDAL 4 5 = [lDPL + lRP]
lHZP
lAPR 1 1
lEP
2
–1
Notes: 1. IRCD to IRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
I/O
CL
2
–1
= [lRC]
3
Preliminary Data Sheet E0248E10 (Ver. 1.0)
7
EDS2504APTA/08APTA/16APTA-TI
VIL/VIH Clamp
This SDRAM component has VIL and VIH clamp for CLK, CKE, /CS, DQM and DQ pins.
[Minimum VIL Clamp Current]
VIL (V) I (mA)
–2 –32
–1.8 –25
–1.6 –19
–1.4 –13
–1.2 –8
–1 –4
–0.9 –2
–0.8 –0.6
–0.6 0
–0.4 0
–0.2 0
0 0
–5
–10
–15
–20
I (mA)
–25
–30
–35
0
–2
–1.5 –1 –0.5
VIL (V)
0
Minimum VIL Clamp Current
Preliminary Data Sheet E0248E10 (Ver. 1.0)
8
EDS2504APTA/08APTA/16APTA-TI
[Minimum VIH Clamp Current]
VIH (V) I (mA)
VDD + 2 10
VDD + 1.8 8
VDD + 1.6 5.5
VDD + 1.4 3.5
VDD + 1.2 1.5
VDD + 1 0.3
VDD + 0.8 0
VDD + 0.6 0
VDD + 0.4 0
VDD + 0.2 0
VDD + 0 0
10
8
6
I (mA)
4
2
0
VDD + 0 VDD + 1 VDD + 2VDD + 0.5 VDD + 1.5
VIH (V)
Minimum VIH Clamp Current
Preliminary Data Sheet E0248E10 (Ver. 1.0)
9
EDS2504APTA/08APTA/16APTA-TI
IOL/IOH Characteristics
[Output Low Current (IOL)]
IOL IOL
VOUT (V) min. (mA) max. (mA)
0 0 0
0.4 27 71
0.65 41 108
0.85 51 134
1 58 151
1.4 70 188
1.5 72 194
1.65 75 203
1.8 77 209
1.95 77 212
3 80 220
3.45 81 223
250
200
150
IOL (mA)
100
50
0
0 0.5 1 1.5 2 2.5 3 3.5
VOUT (V)
Output Low Current (IOL)
min.
max.
Preliminary Data Sheet E0248E10 (Ver. 1.0)
10
EDS2504APTA/08APTA/16APTA-TI
[Output High Current (IOH)]
IOH IOH
VOUT (V) min. (mA) max. (mA)
3.45 — –3
3.3 — –28
3 0 –75
2.6 –21 –130
2.4 –34 –154
2 –59 –197
1.8 –67 –227
1.65 –73 –248
1.5 –78 –270
1.4 –81 –285
1 –89 –345
0 –93 –503
250
200
150
IOL (mA)
100
50
0
0 0.5 1 1.5 2 2.5 3 3.5
VOUT (V)
Output High Current (IOH)
min.
max.
Preliminary Data Sheet E0248E10 (Ver. 1.0)
11
Block Diagram
CLK
CKE
Address
/CS
/RAS
/CAS
/WE
Clock
Generator
Mode
Register
Control Logic
Command Decoder
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Burst
Counter
EDS2504APTA/08APTA/16APTA-TI
Bank 3
Bank 2
Bank 1
Bank 0
Row Decoder
Sense Amplifier
Column Decoder &
Latch Circuit
Data Control Circuit
Latch Circuit
DQM
DQ
Input & Output
Buffer
Preliminary Data Sheet E0248E10 (Ver. 1.0)
12
EDS2504APTA/08APTA/16APTA-TI
Pin Function
CLK (input pin)
CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge.
/CS (input pin)
When /CS is Low, the command input cycle becomes valid. When /CS is High, all inputs are ignored. However,
internal operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
Although these pin names are the same as those of conventional DRAMs, they function in a different way. These
pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details,
refer to the command operation section.
A0 toA12 (input pins)
Row address (AX0 to AX12) is determined by A0 to A12 at the bank active command cycle CLK rising edge.
Column address is determined by A0 to A8, A9 or A11 (see Address Pins Table) at the read or write command cycle
CLK rising edge. And this column address becomes burst access start address.
[Address Pins Table]
Address (A0 to A12)
Part number Row address Column address
EDS2504AP AX0 to AX12 AY0 to AY9, AY11
EDS2508AP AX0 to AX12 AY0 to AY9
EDS2516AP AX0 to AX12 AY0 to AY8
A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged.
But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0 and BA1 (BS) is
precharged. For details refer to the command operation section.
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal (BS). (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0 BA1
Bank 0 L L
Bank 1 H L
Bank 2 L H
Bank 3 H H
Remark: H: VIH. L: VIL. ×: VIH or VIL
CKE (input pin)
This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is
Low, the next CLK rising edge is invalid. This pin is used for power-down mode, clock suspend mode and self
refresh mode.
Preliminary Data Sheet E0248E10 (Ver. 1.0)
13
EDS2504APTA/08APTA/16APTA-TI
DQM, UDQM and LDQM (input pins)
DQM controls input/output buffers. In 16M × 16 products, UDQM and LDQM control upper byte (DQ8 to DQ15) and
lower byte (DQ0 to DQ7).
Read operation: If DQM is High, the output buffer becomes High-Z. If the DQM is Low, the output buffer becomes
Low-Z. (The latency of DQM during reading is 2 clocks.)
Write operation: If DQM is High, the previous data is held (the new data is not written). If DQM is Low, the data is
written. (The latency of DQM during writing is 0 clock.)
DQ0 toDQ15 (input/output pins)
Data is input to and output from these pins (DQ0 to DQ3; EDS2504AP , DQ0 to DQ7; EDS2508AP, DQ0 to DQ15;
EDS2516AP).
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Preliminary Data Sheet E0248E10 (Ver. 1.0)
14
EDS2504APTA/08APTA/16APTA-TI
Command Operation
Command Truth Table
The SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE
Function Symbol n – 1 n /CS /RAS /CAS /WE BA1,BA0 A10
Device deselect DESL H × H × × × × × ×
No operation NOP H × L H H H × × ×
Burst stop BST H × L H H L × × ×
Read READ H × L H L H V L V
Read with auto precharge READA H × L H L H V H V
Write WRIT H × L H L L V L V
Write with auto precharge WRITA H × L H L L V H V
Bank activate ACT H × L L H H V V V
Precharge select bank PRE H × L L H L V L ×
Precharge all banks PALL H × L L H L × H ×
Mode register set MRS H × L L L L L L V
Remark: H: VIH. L: VIL. ×: VIH or VIL
Device deselect command [DESL]
When this command is set (/CS is High), the SDRAM ignore command input at the clock. However, the internal
status is held.
No operation [NOP]
This command is not an execution command. However, the internal operations continue.
Burst stop command [BST]
This command can stop the current burst operation.
Column address strobe and read command [READ]
This command starts a read operation. In addition, the start address of burst read is determined by the column
address (see Address Pins Table in Pin Function) and the bank select address. After the read operation, the output
buffer becomes High-Z.
Read with auto-precharge [READA]
This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8.
Column address strobe and write command [WRIT]
This command starts a write operation. When the burst write mode is selected, the column address (see Address
Pins Table in Pin Function) and the bank select address (BA0, BA1) become the burst write start address. When the
single write mode is selected, data is only written to the location specified by the column address (see Address Pins
Table in Pin Function) and the bank select address (BA0, BA1).
Write with auto-precharge [WRITA]
This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a
single write operation.
A0 to A12
Preliminary Data Sheet E0248E10 (Ver. 1.0)
15
EDS2504APTA/08APTA/16APTA-TI
Row address strobe and bank activate [ACT]
This command activates the bank that is selected by BA0, BA1 and determines the row address (AX0 to AX12).
(See Bank Select Signal Table)
Precharge selected bank [PRE]
This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0 BA1
Bank 0 L L
Bank 1 H L
Bank 2 L H
Bank 3 H H
Remark: H: VIH. L: VIL. ×: VIH or VIL
Precharge all banks [PALL]
This command starts a precharge operation for all banks.
Refresh [REF/SELF]
This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and
the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set [MRS]
The SDRAM has a mode register that defines how it operates. The mode register is specified by the address pins
(A0 to BA0 and BA1) at the mode register set cycle. For details, refer to the mode register configuration. After
power on, the contents of the mode register are undefined, execute the mode register set command to set up the
mode register.
Preliminary Data Sheet E0248E10 (Ver. 1.0)
16
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