ECS RS780Q-LM3 Schematics rev0.1
5
4
3
2
1
RS780Q-LM3
D D
VER:0.1
2009 / 6 / 8
SCHEMATICS TABLE:
Page Index
------- ------------------------
1
3
C C
4
5
6
7
8
9
10
11
12
B B
13
14
15
16
17
18
COVER PAGE
BLOCK DIAGRAM2
HT,CPU MEMORY
CPU CONTROL & MISC
CPU PWR & GND
DDR3 DIMM Socket
RS780-HT LINK I/F
RS780-PCIE I/F
RS780-SYSTEM I/F
RS780-SPMEM/STRAPS
RS780-POWER
SB700-PCIE/PCI/CPU/LPC/CLK
SB700-ACPI/GPIO/USB/AUDIO
SB700-POWER & DECOUPLING
SB700-SATA/IDE/HWM/SPI
SB700-STRAPS
VGA / DVI
Page Index
------- ------------------------
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PCIE-16X/1X
USB, 5VDUAL SWITCH
PCI SLOT
LPC SIO ITE8720
PS2 / COM PORT
LAN(RTL8103EL/RTL8111DL)
AUDIO ALC662
AUDIO ALC662(PANEL)
CPU VCORE ISL6323B
DC POWER, DDRIII POWER
NB CORE POWER
PANEL,ATX24P,SMRTFAN,BUZZERCLOCK GENERATOR-SLG8LP625
POWER ENABLE
Attention
Power Sequence
Reset Diagram
Power Distribution
History
PCB Size: 244mm*224mm
A A
L1:TOPPCB STACK:
L2:PWR
L3:GND
L4:BOTTOM
2116, 5mils, 60 ohm
5
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
Cover Page
Cover Page
Cover Page
RS780Q-LM3
RS780Q-LM3
RS780Q-LM3
1
1
1
1
37Tuesday, June 30, 2009
37Tuesday, June 30, 2009
37Tuesday, June 30, 2009
0.1
0.1
0.1
5
4
3
2
1
RS780Q-LM3
D D
CPU VCORE
ISL6323B
27
AMD
AM3
AM3 SOCKET
3,4,5
NB CORE Power
UP6109A
29
DVI/TMDS CON
Clock
Generator
SLG8LP625
12
VGA CON
C C
18
18
HyperTransport
Link
2CH TMDS
OUT
RS780
HyperTransport LINK0 CPU I/F
DX10 IGP( RS780)
LVDS/TVOUT/TMDS(RS780/740)
DISPLAY PORT X2 (RS780)
Side Port Memory(RS780/740)
1 X16 PCIE I/F
1 X4 PCIE I/F WITH SB
6 X1 PCIE I/F (4 X1 for RS740)
IN
16x16
6,7,8,9,10,11
DDRIII 800, 1066, 1333
128bit
DDRIII 800, 1066, 1333
16X
6 1X PCIE INTERFACE
PCIE GPP0
X1
19 19
PCIE GPP1
X1
UNBUFFERED
DDRIII DIMM1
UNBUFFERED
DDRIII DIMM2
DDRIII FIRST LOGICAL DIMM
PCIE
16X
SLOT
PCIE GPP3
10/100M LAN
6
6
19
23
4X PCIE ALink
USB-9
20
USB-10
USB-8
20
USB-11
USB-5USB-6USB-7
20
2020
20
20
USB-1USB-2USB-3USB-4
USB-0
2020 20
USB 2.0
SB700
USB2.0 (12)+ 1.1(2)
SATA II (6 PORTS)
AZALIA HD AUDIO
HD AUDIO I/F
SATA II I/F
ATA 66/100/133
HD AUDIO HDR
26 25
SATA#0 SATA#1 SATA#2 SATA#3
17 17 17 17
HD AUDIO
REAR CON
SPI I/F
LPC I/F(S5)
B B
SPI ROM
SPI I/F
16
ACPI 1.1
INT RTC
HW MONITOR
PCI/PCI BDGE
PCI SLOT
X1
PCI
21
13,14,15,16,17
ITE SIO IT8720
22
A A
KBD
MOUSE
COM
23
5
4
3
HW MONITOR I/F
HW
MONITOR
2
22
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Custom
Custom
Custom
RS780Q-LM3
RS780Q-LM3
RS780Q-LM3
1
2
2
2
0.1
0.1
0.1
37Tuesday, June 30, 2009
37Tuesday, June 30, 2009
37Tuesday, June 30, 2009
5
4
3
2
1
CPU Memory
TP33
TP35
TP34
TP31
TP96
TP97
TP98
STP34
TP27
TP29
TP30
TP32
STP35
TP101
TP102
TP103
MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0
DDR3 Memory Interface BDDR3 Memory Interface A
CPU1C
AJ19
AK19
AL19
AL18
W29
W28
W31
AE30
AC31
AF31
AD29
AE29
AB31
AG31
AD31
AC29
AC30
AB29
AA31
AA28
AE31
AA29
AA30
AK13
AJ13
AK17
AJ17
AK23
AL23
AL28
AL29
AJ14
AH17
AJ23
AK29
U31
U30
Y31
Y30
V31
A18
A19
C19
D19
B19
N31
M31
M29
N28
N29
N30
P29
P31
R29
R28
R31
R30
T31
T29
U29
U28
D31
C31
C24
C23
D17
C17
C14
C13
C30
A23
B17
B13
CPU1C
MB_CLK_H7
MB_CLK_L7
MB_CLK_H6
MB_CLK_L6
MB_CLK_H5
MB_CLK_L5
MB_CLK_H4
MB_CLK_L4
MB_CLK_H3
MB_CLK_L3
MB_CLK_H2
MB_CLK_L2
MB_CLK_H1
MB_CLK_L1
MB_CLK_H0
MB_CLK_L0
MB0_CS_L1
MB0_CS_L0
MB0_ODT1
MB0_ODT0
MB1_CS_L1
MB1_CS_L0
MB1_ODT1
MB1_ODT0
MB_RESET_L
MB_CAS_L
MB_WE_L
MB_RAS_L
MB_BANK2
MB_BANK1
MB_BANK0
MB_CKE1
MB_CKE0
MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0
MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0
AM3_SOCKET
AM3_SOCKET
3
MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MEM CHB
MEM CHB
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0
MB_DQS_H8
MB_DQS_L8
MB_DM8
MB_CHECK7
MB_CHECK6
MB_CHECK5
MB_CHECK4
MB_CHECK3
MB_CHECK2
MB_CHECK1
MB_CHECK0
MB_EVENT_L
MB_DATA63
AH13
MB_DATA62
AL13
MB_DATA61
AL15
MB_DATA60
AJ15
MB_DATA59
AF13
MB_DATA58
AG13
MB_DATA57
AL14
MB_DATA56
AK15
MB_DATA55
AL16
MB_DATA54
AL17
MB_DATA53
AK21
MB_DATA52
AL21
MB_DATA51
AH15
MB_DATA50
AJ16
MB_DATA49
AH19
MB_DATA48
AL20
MB_DATA47
AJ22
MB_DATA46
AL22
MB_DATA45
AL24
MB_DATA44
AK25
MB_DATA43
AJ21
MB_DATA42
AH21
MB_DATA41
AH23
MB_DATA40
AJ24
MB_DATA39
AL27
MB_DATA38
AK27
MB_DATA37
AH31
MB_DATA36
AG30
MB_DATA35
AL25
MB_DATA34
AL26
MB_DATA33
AJ30
MB_DATA32
AJ31
MB_DATA31
E31
MB_DATA30
E30
MB_DATA29
B27
MB_DATA28
A27
MB_DATA27
F29
MB_DATA26
F31
MB_DATA25
A29
MB_DATA24
A28
MB_DATA23
A25
MB_DATA22
A24
MB_DATA21
C22
MB_DATA20
D21
MB_DATA19
A26
MB_DATA18
B25
MB_DATA17
B23
MB_DATA16
A22
MB_DATA15
B21
MB_DATA14
A20
MB_DATA13
C16
MB_DATA12
D15
MB_DATA11
C21
MB_DATA10
A21
MB_DATA9
A17
MB_DATA8
A16
MB_DATA7
B15
MB_DATA6
A14
MB_DATA5
E13
MB_DATA4
F13
MB_DATA3
C15
MB_DATA2
A15
MB_DATA1
A13
MB_DATA0
D13
J31
J30
J29
K29
K31
G30
G29
L29
L28
H31
G31
MB_EVENT_LMA_EVENT_L
V29
R364 1K-04R364 1K-04
1 2
MB_DATA[63..0] 6
MB_EVENT_L6
H_CLKIN_P17
H_CLKIN_N17
H_CLKIN_P07
H_CLKIN_N07 H_CLKOUT_N0 7
H_CTLIN_P17
H_CTLIN_N17
H_CTLIN_P07
H_CTLIN_N07
H_CADIN_P157
H_CADIN_N157
H_CADIN_P147
H_CADIN_N147
H_CADIN_P137
H_CADIN_N137
H_CADIN_P127
H_CADIN_N127
H_CADIN_P117
H_CADIN_N117
H_CADIN_P107
H_CADIN_N107
H_CADIN_P97
H_CADIN_N97
H_CADIN_P87
H_CADIN_N87
H_CADIN_P77
H_CADIN_N77
H_CADIN_P67
H_CADIN_N67
H_CADIN_P57
H_CADIN_N57
H_CADIN_P47
H_CADIN_N47
H_CADIN_P37
H_CADIN_N37
H_CADIN_P27
H_CADIN_N27
H_CADIN_P17
H_CADIN_N17
H_CADIN_P07
H_CADIN_N07
2
H_CLKIN_P1
H_CLKIN_N1
H_CLKIN_P0
H_CLKIN_N0
H_CTLIN_P1
H_CTLIN_N1
H_CTLIN_P0
H_CTLIN_N0
H_CADIN_P15
H_CADIN_N15
H_CADIN_P14
H_CADIN_N14
H_CADIN_P13
H_CADIN_N13
H_CADIN_P12
H_CADIN_N12
H_CADIN_P11
H_CADIN_N11
H_CADIN_P10
H_CADIN_N10
H_CADIN_P9
H_CADIN_N9
H_CADIN_P8
H_CADIN_N8
H_CADIN_P7
H_CADIN_N7
H_CADIN_P6
H_CADIN_N6
H_CADIN_P5
H_CADIN_N5
H_CADIN_P4
H_CADIN_N4
H_CADIN_P3
H_CADIN_N3
H_CADIN_P2
H_CADIN_N2
H_CADIN_P1
H_CADIN_N1
H_CADIN_P0 H_CADOUT_P0
H_CADIN_N0
+VCC
2009 6 23 V0.1
SWAP IP1 for PCB
NOTE:
We can repair two 1X2 headers for layout design more convenience!!
HT LINK
CPU1A
CPU1A
N6
L0_CLKIN_H1
P6
L0_CLKIN_L1
N3
L0_CLKIN_H0
N2
L0_CLKIN_L0
V4
L0_CTLIN_H1
V5
L0_CTLIN_L1
U1
L0_CTLIN_H0
V1
L0_CTLIN_L0
U6
L0_CADIN_H15
V6
L0_CADIN_L15
T4
L0_CADIN_H14
T5
L0_CADIN_L14
R6
L0_CADIN_H13
T6
L0_CADIN_L13
P4
L0_CADIN_H12
P5
L0_CADIN_L12
M4
L0_CADIN_H11
M5
L0_CADIN_L11
L6
L0_CADIN_H10
M6
L0_CADIN_L10
K4
L0_CADIN_H9
K5
L0_CADIN_L9
J6
L0_CADIN_H8
K6
L0_CADIN_L8
U3
L0_CADIN_H7
U2
L0_CADIN_L7
R1
L0_CADIN_H6
T1
L0_CADIN_L6
R3
L0_CADIN_H5
R2
L0_CADIN_L5
N1
L0_CADIN_H4
P1
L0_CADIN_L4
L1
L0_CADIN_H3
M1
L0_CADIN_L3
L3
L0_CADIN_H2
L2
L0_CADIN_L2
J1
L0_CADIN_H1
K1
L0_CADIN_L1
J3
L0_CADIN_H0
J2
L0_CADIN_L0
AM3_SOCKET
AM3_SOCKET
Layer 1 Layer 2
IMPEDANCE_T IMPEDANCE_B
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
HT LINK
HT LINK
IP1
IP1
1 2
3 4
H2X2-O
H2X2-O
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
AD5
L0_CLKOUT_H1
AD4
L0_CLKOUT_L1
AD1
L0_CLKOUT_H0
AC1
L0_CLKOUT_L0
Y6
L0_CTLOUT_H1
W6
L0_CTLOUT_L1
W2
L0_CTLOUT_H0
W3
L0_CTLOUT_L0
Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
L0_CADOUT_H9
AG6
L0_CADOUT_L9
AH5
L0_CADOUT_H8
AH4
L0_CADOUT_L8
Y1
L0_CADOUT_H7
W1
L0_CADOUT_L7
AA2
L0_CADOUT_H6
AA3
L0_CADOUT_L6
AB1
L0_CADOUT_H5
AA1
L0_CADOUT_L5
AC2
L0_CADOUT_H4
AC3
L0_CADOUT_L4
AE2
L0_CADOUT_H3
AE3
L0_CADOUT_L3
AF1
L0_CADOUT_H2
AE1
L0_CADOUT_L2
AG2
L0_CADOUT_H1
AG3
L0_CADOUT_L1
AH1
L0_CADOUT_H0
AG1
L0_CADOUT_L0
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
H_CLKOUT_P1
H_CLKOUT_N1
H_CLKOUT_P0
H_CLKOUT_N0
H_CTLOUT_P1
H_CTLOUT_N1
H_CTLOUT_P0
H_CTLOUT_N0
H_CADOUT_P15
H_CADOUT_N15
H_CADOUT_P14
H_CADOUT_N14
H_CADOUT_P13
H_CADOUT_N13
H_CADOUT_P12
H_CADOUT_N12
H_CADOUT_P11
H_CADOUT_N11
H_CADOUT_P10
H_CADOUT_N10
H_CADOUT_P9
H_CADOUT_N9
H_CADOUT_P8
H_CADOUT_N8
H_CADOUT_P7
H_CADOUT_N7
H_CADOUT_P6
H_CADOUT_N6
H_CADOUT_P5
H_CADOUT_N5
H_CADOUT_P4
H_CADOUT_N4
H_CADOUT_P3
H_CADOUT_N3
H_CADOUT_P2
H_CADOUT_N2
H_CADOUT_P1
H_CADOUT_N1
H_CADOUT_N0
HT,CPU MEMORY
HT,CPU MEMORY
HT,CPU MEMORY
RS780Q-LM3
RS780Q-LM3
RS780Q-LM3
1
H_CLKOUT_P1 7
H_CLKOUT_N1 7
H_CLKOUT_P0 7
H_CTLOUT_P1 7
H_CTLOUT_N1 7
H_CTLOUT_P0 7
H_CTLOUT_N0 7
H_CADOUT_P15 7
H_CADOUT_N15 7
H_CADOUT_P14 7
H_CADOUT_N14 7
H_CADOUT_P13 7
H_CADOUT_N13 7
H_CADOUT_P12 7
H_CADOUT_N12 7
H_CADOUT_P11 7
H_CADOUT_N11 7
H_CADOUT_P10 7
H_CADOUT_N10 7
H_CADOUT_P9 7
H_CADOUT_N9 7
H_CADOUT_P8 7
H_CADOUT_N8 7
H_CADOUT_P7 7
H_CADOUT_N7 7
H_CADOUT_P6 7
H_CADOUT_N6 7
H_CADOUT_P5 7
H_CADOUT_N5 7
H_CADOUT_P4 7
H_CADOUT_N4 7
H_CADOUT_P3 7
H_CADOUT_N3 7
H_CADOUT_P2 7
H_CADOUT_N2 7
H_CADOUT_P1 7
H_CADOUT_N1 7
H_CADOUT_P0 7
H_CADOUT_N0 7
3
3
3
0.1
0.1
0.1
36Tuesday, June 30, 2009
36Tuesday, June 30, 2009
36Tuesday, June 30, 2009
2009 6 23 V0.1
Change TP99,TP100 to STP34,STP35
CPU1B
D D
MA0_CLK_P06
MA0_CLK_N06
MA0_CLK_P16
MA0_CLK_N16
2009 6 6 V0.1
Del two DDR3
socket #3,#4
MA0_CS_L16
MA0_CS_L06
MA0_ODT16
MA0_ODT06
C C
MA_RESET_L6
MA_CAS_L6
MA_WE_L6
MA_RAS_L6
MA_BANK26
MA_BANK16
MA_BANK06
MA_CKE16
MA_CKE06
MA_ADD[15..0]6
B B
MA_DQS_P76
MA_DQS_N76
MA_DQS_P66
MA_DQS_N66
MA_DQS_P56
MA_DQS_N56
MA_DQS_P46
MA_DQS_N46
MA_DQS_P36
MA_DQS_N36
MA_DQS_P26
MA_DQS_N26
MA_DQS_P16
MA_DQS_N16
MA_DQS_P06
MA_DQS_N06
MA_DM[7..0]6
A A
STP32STP32
STP33STP33
STP29STP29
STP25STP25
STP90STP90
STP91STP91
STP92STP92
STP93STP93
STP26STP26
STP27STP27
STP31STP31
STP30STP30
STP94STP94
STP95STP95
STP96STP96
STP97STP97
STP28STP28
STP32
STP33
STP29
STP25
STP90
STP91
STP92
STP93
STP26
STP27
STP31
STP30
STP94
STP95
STP96
STP97
MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0
CPU1B
AG21
MA_CLK_H7
AG20
MA_CLK_L7
AE20
MA_CLK_H6
AE19
MA_CLK_L6
U27
MA_CLK_H5
U26
MA_CLK_L5
V27
MA_CLK_H4
W27
MA_CLK_L4
W26
MA_CLK_H3
W25
MA_CLK_L3
U24
MA_CLK_H2
V24
MA_CLK_L2
G19
MA_CLK_H1
H19
MA_CLK_L1
G20
MA_CLK_H0
G21
MA_CLK_L0
AC25
MA0_CS_L1
AA24
MA0_CS_L0
AE28
MA0_ODT1
AC28
MA0_ODT0
AD27
MA1_CS_L1
AA25
MA1_CS_L0
AE27
MA1_ODT1
AC27
MA1_ODT0
E20
MA_RESET_L
AB25
MA_CAS_L
AB27
MA_WE_L
AA26
MA_RAS_L
N25
MA_BANK2
Y27
MA_BANK1
AA27
MA_BANK0
L27
MA_CKE1
M25
MA_CKE0
M27
MA_ADD15
N24
MA_ADD14
AC26
MA_ADD13
N26
MA_ADD12
P25
MA_ADD11
Y25
MA_ADD10
N27
MA_ADD9
R24
MA_ADD8
P27
MA_ADD7
R25
MA_ADD6
R26
MA_ADD5
R27
MA_ADD4
T25
MA_ADD3
U25
MA_ADD2
T27
MA_ADD1
W24
MA_ADD0
AD15
MA_DQS_H7
AE15
MA_DQS_L7
AG18
MA_DQS_H6
AG19
MA_DQS_L6
AG24
MA_DQS_H5
AG25
MA_DQS_L5
AG27
MA_DQS_H4
AG28
MA_DQS_L4
D29
MA_DQS_H3
C29
MA_DQS_L3
C25
MA_DQS_H2
D25
MA_DQS_L2
E19
MA_DQS_H1
F19
MA_DQS_L1
F15
MA_DQS_H0
G15
MA_DQS_L0
AF15
MA_DM7
AF19
MA_DM6
AJ25
MA_DM5
AH29
MA_DM4
B29
MA_DM3
E24
MA_DM2
E18
MA_DM1
H15
MA_DM0
AM3_SOCKET
AM3_SOCKET
5
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MEM CHA
MEM CHA
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
MA_DQS_H8
MA_DQS_L8
MA_DM8
MA_CHECK7
MA_CHECK6
MA_CHECK5
MA_CHECK4
MA_CHECK3
MA_CHECK2
MA_CHECK1
MA_CHECK0
MA_EVENT_L
MA_DATA63
AE14
MA_DATA62
AG14
MA_DATA61
AG16
MA_DATA60
AD17
MA_DATA59
AD13
MA_DATA58
AE13
MA_DATA57
AG15
MA_DATA56
AE16
MA_DATA55
AG17
MA_DATA54
AE18
MA_DATA53
AD21
MA_DATA52
AG22
MA_DATA51
AE17
MA_DATA50
AF17
MA_DATA49
AF21
MA_DATA48
AE21
MA_DATA47
AF23
MA_DATA46
AE23
MA_DATA45
AJ26
MA_DATA44
AG26
MA_DATA43
AE22
MA_DATA42
AG23
MA_DATA41
AH25
MA_DATA40
AF25
MA_DATA39
AJ28
MA_DATA38
AJ29
MA_DATA37
AF29
MA_DATA36
AE26
MA_DATA35
AJ27
MA_DATA34
AH27
MA_DATA33
AG29
MA_DATA32
AF27
MA_DATA31
E29
MA_DATA30
E28
MA_DATA29
D27
MA_DATA28
C27
MA_DATA27
G26
MA_DATA26
F27
MA_DATA25
C28
MA_DATA24
E27
MA_DATA23
F25
MA_DATA22
E25
MA_DATA21
E23
MA_DATA20
D23
MA_DATA19
E26
MA_DATA18
C26
MA_DATA17
G23
MA_DATA16
F23
MA_DATA15
E22
MA_DATA14
E21
MA_DATA13
F17
MA_DATA12
G17
MA_DATA11
G22
MA_DATA10
F21
MA_DATA9
G18
MA_DATA8
E17
MA_DATA7
G16
MA_DATA6
E15
MA_DATA5
G13
MA_DATA4
H13
MA_DATA3
H17
MA_DATA2
E16
MA_DATA1
E14
MA_DATA0
G14
J28
J27
J25
K25
J26
G28
G27
L24
K27
H29
H27
W30
R339 1K-04R339 1K-04
1 2
for layout change it to bottom side
2009 6 6 V0.1
Del two DDR3
socket #3,#4
MB_ADD[15..0]6
MB_DQS_P76
MB_DQS_N76
MB_DQS_P66
MB_DQS_N66
MB_DQS_P56
MB_DQS_N56
MB_DQS_P46
MB_DQS_N46
MB_DQS_P36
MB_DQS_N36
MB_DQS_P26
MB_DQS_N26
MB_DQS_P16
MB_DQS_N16
MB_DQS_P06
MB_DQS_N06
MB_DM[7..0]6
TP33TP33
TP35TP35
TP34TP34
TP31TP31
TP96TP96
TP97TP97
MB0_CLK_P06
MB0_CLK_N06
TP98TP98
STP34STP34
MB0_CLK_P16
MB0_CLK_N16
TP27TP27
TP29TP29
TP30TP30
TP32TP32
MB0_CS_L16
MB0_CS_L06
MB0_ODT16
MB0_ODT06
STP35STP35
TP101TP101
TP102TP102
TP103TP103
STP24STP24
MB_RESET_L6
MB_CAS_L6
MB_WE_L6
MB_RAS_L6
MB_BANK26
MB_BANK16
MB_BANK06
MB_CKE16
MB_CKE06
MA_DATA[63..0] 6
MA_EVENT_L 6
+VDIMM +VDIMM
4
5
VDDA_2P5V for CPU PLL
+12V
VDDA_EN_H31
+VREF_2P5V
R305 10K-04R305 10K-04
1 2
VDDA_2P5V_FB
D D
2 1
C480
C480
.1u-04-O
.1u-04-O
R505
R505
0-04
0-04
1 2
VDDA_2P5V@250mA
Note: Update with new
clock termination
scheme, if necessary.
H_CLK200_P12
H_CLK200_N12
2009 6 6 V0.1
Del level shift
for cost down
C C
2009 6 6 V0.1
The Side Band Interface bus is not used
and del ohm for cost down
H_THERMTRIP_L14
B B
A A
H_CLK200_P
H_CLK200_N
08'1009
H_THERMTRIP_L
H_THERMTRIP_L_1.5
+VDIMM
R440 300-04R440 300-04
1 2
R441 300-04R441 300-04
1 2
R442 300-04R442 300-04
1 2
+VDIMM
R387 1K-04R387 1K-04
1 2
R399 1K-04R399 1K-04
1 2
+VDIMM
R270 300-04R270 300-04
1 2
+VDIMM
R264 1K-04R264 1K-04
1 2
+VDIMM
R285 510-04R285 510-04
1 2
R290 510-04R290 510-04
1 2
5
84
3
+
+
2
-
-
C266 3900P-04C266 3900P-04
21
Cs
C453
C453
10P-04-O
10P-04-O
2 1
Cs
C272 3900P-04C272 3900P-04
21
FDV301N-S
03-050-530106
Q40
Q40
DS
FDV301N-S
FDV301N-S
H_FETGATE
G
H_PWROK
H_STOP_L
H_RST_L
H_TEST27_SINGLECHAIN
H_TEST26_BURNIN_L
08'1003
H_THERMTRIP_L_1.5
H_SIC
H_TEST25_BYPASSCLK
H_TEST25_BYPASSCLK_L
C65
C65
4.7U-08-O
4.7U-08-O
2009 6 6 V0.1
C65 reserved
for cost down
1
U19A
U19A
OP358-S
OP358-S
Rs
+VDIMM
Q45_G
12
R268
R268
169-1-04
169-1-04
+VDIMM
12
12
R300
R300
15-1
15-1
12
R301
R301
15-1
15-1
+VCC3
DS
Q45
Q45
2N7002-S
2N7002-S
G
+VDDA_2P5V
12
EC43
EC43
100U-16DE
100U-16DE
STP85STP85
H_CLKIN_P
H_CLKIN_N
STP86STP86
R273
R273
4.7K-04
4.7K-04
2009 6 6 V0.1
The Side Band Interface bus is not used
for cost down
C292
C292
.1U-04
.1U-04
2 1
2 1
+VDDA_2P5V
2009 6 24 V0.1
Add FB17 stuff 0 ohm
for SI
H_M_VREF
C291
C291
1000P-04
1000P-04
Place witin 500 mils
of the CPU socket.
4
+VCC
4
+12V
C473
C473
84
.1U-04-O
5
6
1 2
FB17 0-08FB17 0-08
+
+
-
-
.1U-04-O
7
U19B
U19B
OP358-S
OP358-S
C290
C290
4.7U-25VX5-08
4.7U-25VX5-08
2 1
2009 6 6 V0.1
The Side Band Interface bus is not used
and del ohm for cost down
Del R269,R251,R248
3
2
CPU Control and Miscellaneous
2009 6 29 V0.1
Add R240 reserved
for PSI_L function
H_PSI_L
R240 1K-04-OR240 1K-04-O
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
C288
C288
.22U-X5-04
.22U-X5-04
2 1
+VDIMM
R241 10K-04R241 10K-04
1 2
H_VCORE_FB27
H_VCORE_FB_L27
+VDIMM
R298 39.2-1-04R298 39.2-1-04
1 2
R299 39.2-1-04R299 39.2-1-04
1 2
+VDIMM
RN8
RN8
1 2
3 4
5 6
7 8
1K-8P4R-O
1K-8P4R-O
2009 6 6 V0.1
RN8 reserved for cost down
H_DBREQ_L
H_DBRDY
H_TCK
H_TMS
H_TDI
H_TRST_L
H_TDO
STP19STP19
CPU1D
CPU1D
C10
VDDA_1
D10
VDDA_2
MISC.
H_CLKIN_P
C286
C286
H_CLKIN_N
3300P-04
3300P-04
2 1
STP3STP3
STP23STP23
TP23TP23
TP25TP25
STP9STP9
STP11STP11
STP14STP14
STP7STP7
STP20STP20
STP6STP6
STP5STP5
STP10STP10
STP8STP8
+VDIMM
H_TCK
H_TMS
H_TDI
H_TRST_L
R252
R252
300-04-O
300-04-O
H_PWROK
H_STOP_L
H_RST_L
H_PRESENT_L
H_SIC
H_TDI
H_TRST_L
H_TCK
H_TMS
H_DBREQ_L
H_VCORE_FB
H_VCORE_FB_L
STP3
H_VTT_SENSE
H_M_VREF
H_M_ZN
H_M_ZP
H_TEST25_BYPASSCLK
H_TEST25_BYPASSCLK_L
H_TEST19_PLLTEST0
H_TEST18_PLLTEST1
H_TEST17_BP3
H_TEST16_BP2
H_TEST15_BP1
H_TEST14_BP0
H_TEST12_SCANSHIFTENB
H_TEST7_ANALOG_T
H_TEST6_DIECRACKMON
H_TEST3_GATE0
H_TEST2_DRAIN0
+VDIMM
HDT_HEADER
HDT_HEADER
1
3
5
7
9
11
13
15
17
19
21
23
KEY
KEY
ASP-68200-07-O-X
ASP-68200-07-O-X
H_PWROK13
H_STOP_L9,13
H_RST_L13
AL3
AL6
AK6
AK4
AL4
AL10
AJ10
AH10
AL9
E12
F12
AH11
AJ11
A10
B10
F10
AJ7
AH9
AJ5
AH7
AJ6
C18
C20
G24
G25
H25
A8
B8
C9
D8
C7
A5
G2
G1
F3
E9
F6
D6
E7
F8
C5
E5
F2
L25
L26
AM3_SOCKET
AM3_SOCKET
MISC.
CLKIN_H
CLKIN_L
PWROK
LDTSTOP_L
RESET_L
CPU_PRESENT_L
SIC
SID
SA0
ALERT_L
TDI
TRST_L
TCK
TMS
DBREQ_L
VDD_FB_H
VDD_FB_L
M_VDDIO_PWRGD
VDDR_SENSE
M_VREF
M_ZN
M_ZP
TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12
TEST7
TEST6
TEST3
TEST2
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
INT. MISC.
INT. MISC.
RSVD6
RSVD7
RSVD8
2
4
6
8
+VCC3
10
12
14
16
18
20
22
24
26
R302
R302
4.7K-04-O
4.7K-04-O
H_RST_L_X
CORE_TYPE
SVC/VID3
SVD/VID2
PVIEN/VID1
THERMDC
THERMDA
THERMTRIP_L
PROCHOT_L
DBRDY
VDDIO_FB_H
VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
HTREF1
HTREF0
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
+VDIMM
G
D S
Q44
Q44
FDV301N-S-O
FDV301N-S-O
R303 0-04-OR303 0-04-O
VID5
VID4
VID0
TDO
PSI_L
H_CORETYPE
G5
H_VID5
D2
H_VID4
D1
H_SVC
C1
H_SVD
E3
H_VID1_PVEN
E2
H_VID0
E1
AG9
AG8
H_THERMTRIP_L_1.5
AK7
AL7
H_TDO
AK10
H_DBRDY
B6
AK11
H_VDIMM_FB_L
AL11
NB_VCORE_FB
G4
G3
F1
H_HTREF1
V8
H_HTREF0
V7
H_TEST29_FBCLKOUT
C11
H_TEST29_FBCLKOUT_L
D11
H_TEST24_SCANCLK1
AK8
H_TEST23_TSTUPD
AH8
H_TEST22_SCANSHIFTEN
AJ9
H_TEST21_SCANEN
AL8
H_TEST20_SCANCLK2
AJ8
H_TEST28_PLLCHRZ
J10
H_TEST28_PLLCHRZ_L
H9
H_TEST27_SINGLECHAIN
AK9
H_TEST26_BURNIN_L
AK5
H_TEST10_ANALOGOUT
G7
H_TEST8_DIG_T
D4
L30
L31
AD25
AE24
AE25
AJ18
AJ20
AK3
H_RST_L
Use buffered reset
HDT Header
3
2
1
H_SVC
H_SVC 27
H_SVD
H_SVD 27
1 2
R235 1K-04R235 1K-04
R215 1K-04R215 1K-04
R214 1K-04R214 1K-04
R277 300-04R277 300-04
2009 6 6 V0.1
Del R282,R292
for cost down
R218 44.2-1-04R218 44.2-1-04
R217 44.2-1-04R217 44.2-1-04
R291 300-04R291 300-04
R297 300-04R297 300-04
A1
1 2
1 2
1 2
1 2
H_PSI_L
1 2
1 2
12
R294
R294
80.6-1-04
80.6-1-04
1 2
1 2
+VDIMM
R213
R213
49.9-1-04-O
49.9-1-04-O
12
12
R242
R242
300-04
300-04
A31
+VDIMM
TP14TP14
TP11TP11
+VDIMM
H_VID1_PVEN 27
TP9TP9
CPU_THERMDC 22
CPU_THERMDA 22
H_PROCHOT_L 13
+VDIMM
STP22STP22
H_VDIMM_FB 28
STP21STP21
NB_VCORE_FB 27
NB_VCORE_FB_L 27
TP16TP16
H_PSI_L 22
+HT_1P2V_B
STP15STP15
STP16STP16
STP18STP18
STP17STP17
STP13STP13
STP12STP12
STP4STP4
AM3
Top View
AL1
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
CPU CONTROL & MISC
CPU CONTROL & MISC
CPU CONTROL & MISC
AL31
RS780Q-LM3
RS780Q-LM3
RS780Q-LM3
1
4
4
4
0.1
0.1
0.1
36Tuesday, June 30, 2009
36Tuesday, June 30, 2009
36Tuesday, June 30, 2009
5
4
3
2
1
Processor Power and Ground
+NB_VCORE
SC62
SC62
22u-6V3X-08-X
22u-6V3X-08-X
SC91
SC91
.22U-X5-04-X
.22U-X5-04-X
+HT_1P2V
2 1
SC64
SC64
4.7U-08-X
4.7U-08-X
2 1
+NB_VCORE
DHOLE1
DHOLE2
DHOLE3
DHOLE4
MT10
MT11
MT12
MT13
MT14
MT15
MT16
NB_VCORE
C207
C207
10U-X5-08
10U-X5-08
HT_1P2V
C240
C240
10U-X5-08
10U-X5-08
SC73
SC73
22u-6V3X-08-X
22u-6V3X-08-X
SC92
SC92
.22U-X5-04-X
.22U-X5-04-X
2 1
4
A4
A6
B5
B7
C6
C8
D7
D9
E8
E10
F9
F11
G10
G12
MT1
MT2
MT3
MT4
MT5
MT6
MT7
MT8
MT9
B2
H20
AE7
C208
C208
10U-X5-08
10U-X5-08
C237
C237
10U-X5-08
10U-X5-08
2 1
SC57
SC57
4.7U-08-X
4.7U-08-X
2 1
CPU1G
CPU1G
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDNB_6
VDDNB_7
VDDNB_8
VDDNB_9
VDDNB_10
VDDNB_11
VDDNB_12
VDDNB_13
VDDNB_14
DHOLE1
DHOLE2
DHOLE3
DHOLE4
MT1
MT2
MT3
MT4
MT5
MT6
MT7
MT8
MT9
MT10
MT11
MT12
MT13
MT14
MT15
MT16
NP/RSVD
NP/VSS1
NP/VSS2
AM3_SOCKET
AM3_SOCKET
SC55
SC55
22u-6V3X-08-X
22u-6V3X-08-X
SC89
SC89
180P-04-X
180P-04-X
2 1
MT17
C209
C209
4.7U-25VX5-08
4.7U-25VX5-08
2 1
C250
C250
10U-X5-08
10U-X5-08
2 1
SC60
SC60
22u-6V3X-08-X
22u-6V3X-08-X
SC49
SC49
.01U-04-X
.01U-04-X
2 1
MT17
MT18
MT18
MT19
MT19
MT20
POWER/GND3
POWER/GND3
MT20
MT21
MT22
MT23
MT24
MT25
MT26
MT21
MT22
MT23
MT24
MT25
MT26
C211
C211
.01U-04
.01U-04
2 1
C236
C236
4.7U-25VX5-08
4.7U-25VX5-08
2 1
SC69
SC69
.22U-X5-04-X
.22U-X5-04-X
2 1
SC75
SC75
.01U-04-X
.01U-04-X
2 1
MT27
MT27
MT28
2 1
MT28
MT29
MT30
MT29
MT30
MT31
C229
C229
.01U-04
.01U-04
2 1
C239
C239
4.7U-25VX5-08
4.7U-25VX5-08
2 1
2 1
SC70
SC70
180P-04-X
180P-04-X
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
MT31
MT32
MT32
SC76
SC76
.22U-X5-04-X
.22U-X5-04-X
C230
C230
.01U-04
.01U-04
2 1
2 1
+NB_VCORE
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
C251
C251
180P-04
180P-04
+HT_1P2V
SC59
SC59
22u-6V3X-08-X
22u-6V3X-08-X
SC58
SC58
22u-6V3X-08-X-O
22u-6V3X-08-X-O
3
2 1
2009 6 6 V0.1
SC58 reserved for cost down
+VCORE
CPU1E
CPU1E
B3
VDD_1
C2
VDD_2
C4
VDD_3
D3
VDD_4
D5
VDD_5
E4
VDD_6
E6
D D
C C
B B
A A
VDD_7
F5
VDD_8
F7
VDD_9
G6
VDD_10
G8
VDD_11
H7
VDD_12
H11
VDD_13
H23
VDD_14
J8
VDD_15
J12
VDD_16
J14
VDD_17
J16
VDD_18
J18
VDD_19
J20
VDD_20
J22
VDD_21
J24
VDD_22
K7
VDD_23
K9
VDD_24
K11
VDD_25
K13
VDD_26
K15
VDD_27
K17
VDD_28
K19
VDD_29
K21
VDD_30
K23
VDD_31
L4
VDD_32
L5
VDD_33
L8
VDD_34
L10
VDD_35
L12
VDD_36
L14
VDD_37
L16
VDD_38
L18
VDD_39
L20
VDD_40
L22
VDD_41
M2
VDD_42
M3
VDD_43
M7
VDD_44
M9
VDD_45
M11
VDD_46
M13
VDD_47
M15
VDD_48
M17
VDD_49
M19
VDD_50
M21
VDD_51
M23
VDD_52
N8
VDD_53
N10
VDD_54
N12
VDD_55
N14
VDD_56
N16
VDD_57
N18
VDD_58
N20
VDD_59
N22
VDD_60
P7
VDD_61
P9
VDD_62
P11
VDD_63
P13
VDD_64
P15
VDD_65
P17
VDD_66
P19
VDD_67
P21
VDD_68
P23
VDD_69
R4
VDD_70
R5
VDD_71
R8
VDD_72
R10
VDD_73
R12
VDD_74
R14
VDD_75
R16
VDD_76
R18
VDD_77
R20
VDD_78
R22
VDD_79
T2
VDD_80
T3
VDD_81
T7
VDD_82
T9
VDD_83
T11
VDD_84
T13
VDD_85
AM3_SOCKET
AM3_SOCKET
+VCORE
Bottom Side Decoupling
SC56
SC56
SC63
SC63
22u-6V3X-08-X
22u-6V3X-08-X
22u-6V3X-08-X
22u-6V3X-08-X
+VCORE
SC80
SC80
SC71
SC71
10U-X5-08-X
10U-X5-08-X
10U-X5-08-X
10U-X5-08-X
+VDIMM
SC82
SC82
SC86
SC86
22u-6V3X-08-X
22u-6V3X-08-X
22u-6V3X-08-X
22u-6V3X-08-X
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
POWER/GND1
POWER/GND1
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
SC67
SC67
22u-6V3X-08-X
22u-6V3X-08-X
SC78
SC78
10U-X5-08-X
10U-X5-08-X
SC83
SC83
22u-6V3X-08-X
22u-6V3X-08-X
5
A3
A7
A9
A11
B4
B9
B11
B14
B16
B18
B20
B22
B24
B26
B28
B30
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F4
F14
F16
F18
F20
F22
F24
F26
F28
F30
G9
G11
H8
H10
H12
H14
H16
H18
H24
H26
H28
H30
J4
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
SC79
SC79
22u-6V3X-08-X
22u-6V3X-08-X
SC65
SC65
10U-X5-08-X
10U-X5-08-X
SC85
SC85
22u-6V3X-08-X
22u-6V3X-08-X
+VCORE
W10
W12
W14
W16
W18
W20
W22
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AD11
AD23
AE10
AE12
AF11
SC77
SC77
10U-X5-08-X
10U-X5-08-X
CPU1F
CPU1F
T15
VDD_86
T17
VDD_87
T19
VDD_88
T21
VDD_89
T23
VDD_90
U8
VDD_91
U10
VDD_92
U12
VDD_93
U14
VDD_94
U16
VDD_95
U18
VDD_96
U20
VDD_97
U22
VDD_98
V9
VDD_99
V11
VDD_100
V13
VDD_101
V15
VDD_102
V17
VDD_103
V19
VDD_104
V21
VDD_105
V23
VDD_106
W4
VDD_107
W5
VDD_108
W8
VDD_109
VDD_110
VDD_111
VDD_112
VDD_113
VDD_114
VDD_115
VDD_116
Y2
VDD_117
Y3
VDD_118
Y7
VDD_119
Y9
VDD_120
Y11
VDD_121
Y13
VDD_122
Y15
VDD_123
Y17
VDD_124
Y19
VDD_125
Y21
VDD_126
Y23
VDD_127
AA8
VDD_128
VDD_129
VDD_130
VDD_131
VDD_132
VDD_133
VDD_134
VDD_135
AB7
VDD_136
AB9
VDD_137
VDD_138
VDD_139
VDD_140
VDD_141
VDD_142
VDD_143
VDD_144
AC4
VDD_145
AC5
VDD_146
AC8
VDD_147
VDD_148
VDD_149
VDD_150
VDD_151
VDD_152
VDD_153
VDD_154
AD2
VDD_155
AD3
VDD_156
AD7
VDD_157
AD9
VDD_158
VDD_159
VDD_160
VDD_161
VDD_162
AF7
VDD_163
AF9
VDD_164
VDD_165
AG4
VDD_166
AG5
VDD_167
AG7
VDD_168
AH2
VDD_169
AH3
VDD_170
AM3_SOCKET
AM3_SOCKET
SC61
SC61
22u-6V3X-08-X
22u-6V3X-08-X
SC72
SC72
10U-X5-08-X
10U-X5-08-X
SC84
SC84
10U-X5-08-X
10U-X5-08-X
POWER/GND2
POWER/GND2
SC54
SC54
22u-6V3X-08-X
22u-6V3X-08-X
SC74
SC74
10U-X5-08-X
10U-X5-08-X
SC87
SC87
.01U-04-X
.01U-04-X
2 1
2 1
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
SC66
SC66
22u-6V3X-08-X
22u-6V3X-08-X
SC68
SC68
4.7U-08-X
4.7U-08-X
2 1
SC88
SC88
.01U-04-X
.01U-04-X
M12
M14
M16
M18
M20
M22
N4
N5
N7
N9
N11
N13
N15
N17
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W7
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
Y14
Y16
Y18
Y20
Y22
AA4
AA5
AA7
AA9
2 1
+HT_1P2V
CPU1H
CPU1H
AJ1
VLDT_A_1
AJ2
AJ3
AJ4
+HT_1P2V_C +HT_1P2V
A12
B12
C12
D12
+VDIMM
M24
M26
M28
M30
P24
P26
P28
P30
T24
T26
T28
T30
V25
V26
V28
V30
Y24
Y26
Y28
Y29
AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30
SC149
SC149
180P-04-X
180P-04-X
VLDT_A_2
VLDT_A_3
VLDT_A_4
VDDR_1
VDDR_2
VDDR_3
VDDR_4
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10
VDDIO_11
VDDIO_12
VDDIO_13
VDDIO_14
VDDIO_15
VDDIO_16
VDDIO_17
VDDIO_18
VDDIO_19
VDDIO_20
VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29
AM3_SOCKET
AM3_SOCKET
A1
HT1:0.5A
HT3:1.4A
1.75A
3.6A
AM3
Top View
AL1
C238
C238
180P-04
180P-04
2 1
SC53
SC50
SC50
22u-6V3X-08-X
22u-6V3X-08-X
SC51
SC51
.22U-X5-04-X
.22U-X5-04-X
2 1
SC47
SC47
.22U-X5-04-X
.22U-X5-04-X
2 1
2 1
SC52
SC52
.01U-04-X
.01U-04-X
SC53
.22U-X5-04-X
.22U-X5-04-X
2 1
POWER/GND4
POWER/GND4
VLDT_B_1
VLDT_B_2
VLDT_B_3
VLDT_B_4
VDDR_5
VDDR_6
VDDR_7
VDDR_8
VDDR_9
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
A31
AL31
EMC
SC81 2.2U-X-OSC81 2.2U-X-O
SC90 2.2U-X-OSC90 2.2U-X-O
+HT_1P2V_B
H1
H2
H5
H6
AG12
AH12
AJ12
AK12
AL12
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
AK20
AK22
AK24
AK26
AK28
AK30
AL5
+HT_1P2V_C
+HT_1P2V
HT_1P2V_B
C297
C297
22u-6V3X-08
22u-6V3X-08
C308
C308
4.7U-25VX5-08
4.7U-25VX5-08
2 1
21
21
2
Place as close
as possible to
CPU socket.
C225
C225
10U-X5-08
10U-X5-08
2 1
+VDIMM
C320
C320
4.7U-25VX5-08
4.7U-25VX5-08
2 1
+VDIMM
C323
C323
4.7U-25VX5-08
4.7U-25VX5-08
2 1
Place across each
VDIMM-GND plane split.
CPU_VDDR
C306
C303
C303
4.7U-25VX5-08
4.7U-25VX5-08
2 1
+HT_1P2V_C
C456
C456
.01U-04
.01U-04
2 1
C306
4.7U-25VX5-08
4.7U-25VX5-08
2 1
C457
C457
.01U-04-O
.01U-04-O
2 1
2009 6 10 V0.1
C456 stuff for AMD suggest
CPU_VDDR
C301
C301
4.7U-25VX5-08
4.7U-25VX5-08
2 1
+VDIMM+VCORE
+VCORE +NB_VCORE
C210 2.2U-OC210 2.2U-O
MEM CHA A0 MEM CHB B0
C321
C322
C322
4.7U-25VX5-08
4.7U-25VX5-08
2 1
C327
C327
4.7U-25VX5-08
4.7U-25VX5-08
2 1
C307
C307
.22U-X5-04
.22U-X5-04
2 1
C458
C458
.01U-04-O
.01U-04-O
2 1
+HT_1P2V
C372
C372
4.7U-25VX5-08
4.7U-25VX5-08
C309
C309
2 1
.01U-04
.01U-04
2 1
21
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
C321
180P-04
180P-04
2 1
C325
C325
180P-04
180P-04
2 1
C305
C305
C294
C294
.22U-X5-04
.22U-X5-04
.22U-X5-04
.22U-X5-04
2 1
C387
C386
C386
4.7U-25VX5-08
4.7U-25VX5-08
2 1
C235
C235
.1U-X7-04
.1U-X7-04
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
C387
4.7U-25VX5-08
4.7U-25VX5-08
2 1
+NB_VCORE
+HT_1P2V
SC48
SC48
.1U-X7-04-X
.1U-X7-04-X
CPU PWR & GND
CPU PWR & GND
CPU PWR & GND
RS780Q-LM3
RS780Q-LM3
RS780Q-LM3
1
Custom
Custom
Custom
2 1
C459
C459
.22U-X5-04-O
.22U-X5-04-O
2 1
+HT_1P2V
DIMMs
C302
C302
.22U-X5-04
.22U-X5-04
2 1
2 1
C311
C311
.1U-X7-04-O
.1U-X7-04-O
+HT_1P2V_C
C444
C444
4.7U-25VX5-08-O
4.7U-25VX5-08-O
2 1
2009 6 6 V0.1
C444 reserved
for cost down
C385
C385
4.7U-25VX5-08
4.7U-25VX5-08
5 36Friday, July 03, 2009
5 36Friday, July 03, 2009
5 36Friday, July 03, 2009
0.1
0.1
0.1
5
MA_EVENT_L
MA_EVENT_L3
+DDR_VTTR
D D
C C
+VDIMM
+VCC3
+MEM_VREFCA
+MEM_VREFDQ
SCLK0
SCLK012,14
SDATA0
B B
MA_ADD[15..0]3
A A
SDATA012,14
MA_BANK23
MA_BANK13
MA_BANK03
MA_CKE13
MA_CKE03
MA0_CS_L13
MA0_CS_L03
MA0_CLK_N13
MA0_CLK_P13
MA0_CLK_N03
MA0_CLK_P03
MA_ADD[15..0]
MA_RESET_L3
MA_CAS_L3
MA_RAS_L3
MA_WE_L3
MA_BANK2
MA_BANK1
MA_BANK0
MA_CKE1
MA_CKE0
MA0_CS_L1
MA0_CS_L0
MA0_CLK_N1
MA0_CLK_P1
MA0_CLK_N0
MA0_CLK_P0
MA_RESET_L
MA_CAS_L
MA_RAS_L
MA_WE_L
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
198
187
49
48
240
120
239
235
232
229
226
223
220
217
214
211
208
205
202
199
166
163
160
157
154
151
148
145
142
139
136
133
130
127
124
121
119
116
113
110
107
104
101
98
95
92
89
86
83
80
47
44
41
38
35
32
29
26
23
20
17
14
11
8
5
2
197
194
191
189
186
183
182
179
176
173
170
78
75
72
69
66
65
62
60
57
54
51
236
67
1
118
238
237
117
52
190
71
169
50
76
193
64
63
185
184
188
181
61
180
59
58
178
56
177
175
70
55
174
196
172
171
168
74
192
73
DIMM1
DIMM1
FREE
FREE
FREE
FREE
VTT
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDSPD
VREFCA
VREFDQ
SCL
SDA
SA1
SA0
BA2
BA1
BA0
CKE1
CKE0
S1*
S0*
CK1/NU*
CK1/NU
CK0*
CK0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
RESET*
CAS*
RAS*
WE*
DDR3-240P-BL
DDR3-240P-BL
RSVD
NC/PAR IN
NC/ERR OUT
NC/TEST4
DQS(0)
DQS*(0)
DSQ(1)
DSQ*(1)
DSQ(2)
DSQ*(2)
DSQ(3)
DSQ*(3)
DQS(4)
DQS*(4)
DQS(5)
DQS*(5)
DSQ(6)
DSQ*(6)
DQS(7)
DQS*(7)
DQS(8)
DQS*(8)
DM0/DQS9
NC/DQS9*
DM1/DQS10
NC/DQS10*
DM2/DQS11
NC/DQS11*
DM3/DQS12
NC/DQS12*
DM4/DQS13
NC/DQS13*
DM5/DQS14
NC/DQS14*
DM6/DQS15
NC/DQS15*
DM7/DQS16
NC/DQS16*
DM8/DQS17
NC/DQS17*
DQ(0)
DQ(1)
DQ(2)
DQ(3)
DQ(4)
DQ(5)
DQ(6)
DQ(7)
DQ(8)
DQ(9)
DQ(10)
DQ(11)
DQ(12)
DQ(13)
DQ(14)
DQ(15)
DQ(16)
DQ(17)
DQ(18)
DQ(19)
DQ(20)
DQ(21)
DQ(22)
DQ(23)
DQ(24)
DQ(25)
DQ(26)
DQ(27)
DQ(28)
DQ(29)
DQ(30)
DQ(31)
DQ(32)
DQ(33)
DQ(34)
DQ(35)
DQ(36)
DQ(37)
DQ(38)
DQ(39)
DQ(40)
DQ(41)
DQ(42)
DQ(43)
DQ(44)
DQ(45)
DQ(46)
DQ(47)
DQ(48)
DQ(49)
DQ(50)
DQ(51)
DQ(52)
DQ(53)
DQ(54)
DQ(55)
DQ(56)
DQ(57)
DQ(58)
DQ(59)
DQ(60)
DQ(61)
DQ(62)
DQ(63)
ODT1
ODT0
CB(0)
CB(1)
CB(2)
CB(3)
CB(4)
CB(5)
CB(6)
CB(7)
79
77
195
68
53
167
39
40
45
46
158
159
164
165
7
6
16
15
25
24
34
33
85
84
94
93
103
102
112
111
43
42
125
126
134
135
143
144
152
153
203
204
212
213
221
222
230
231
161
162
3
4
9
10
122
123
128
129
12
13
18
19
131
132
137
138
21
22
27
28
140
141
146
147
30
31
36
37
149
150
155
156
81
82
87
88
200
201
206
207
90
91
96
97
209
210
215
216
99
100
105
106
218
219
224
225
108
109
114
115
227
228
233
234
MA0_ODT1
MA0_ODT0
MA_DQS_P0
MA_DQS_N0
MA_DQS_P1
MA_DQS_N1
MA_DQS_P2
MA_DQS_N2
MA_DQS_P3
MA_DQS_N3
MA_DQS_P4
MA_DQS_N4
MA_DQS_P5
MA_DQS_N5
MA_DQS_P6
MA_DQS_N6
MA_DQS_P7
MA_DQS_N7
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
4
MA0_ODT1 3
MA0_ODT0 3
MA_DQS_P0 3
MA_DQS_N0 3
MA_DQS_P1 3
MA_DQS_N1 3
MA_DQS_P2 3
MA_DQS_N2 3
MA_DQS_P3 3
MA_DQS_N3 3
MA_DQS_P4 3
MA_DQS_N4 3
MA_DQS_P5 3
MA_DQS_N5 3
MA_DQS_P6 3
MA_DQS_N6 3
MA_DQS_P7 3
MA_DQS_N7 3
MA_DM[7..0]
MA_DATA[63..0]
MA_DM[7..0] 3
MA_DATA[63..0] 3
+VCC3
+MEM_VREFDQ
MB_ADD[15..0]3
3
MB_EVENT_L3
+MEM_VREFCA
MB0_CLK_N13
MB0_CLK_P13
MB0_CLK_N03
MB0_CLK_P03
MB_ADD[15..0]
MB_RESET_L3
MB_CAS_L3
MB_RAS_L3
MB_WE_L3
DIMM2
DIMM2
198
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
187
49
48
240
120
239
235
232
229
226
223
220
217
214
211
208
205
202
199
166
163
160
157
154
151
148
145
142
139
136
133
130
127
124
121
119
116
113
110
107
104
101
98
95
92
89
86
83
80
47
44
41
38
35
32
29
26
23
20
17
14
11
8
5
2
197
194
191
189
186
183
182
179
176
173
170
78
75
72
69
66
65
62
60
57
54
51
236
67
1
118
238
237
117
52
190
71
169
50
76
193
64
63
185
184
188
181
61
180
59
58
178
56
177
175
70
55
174
196
172
171
168
74
192
73
FREE
FREE
FREE
FREE
VTT
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDSPD
VREFCA
VREFDQ
SCL
SDA
SA1
SA0
BA2
BA1
BA0
CKE1
CKE0
S1*
S0*
CK1/NU*
CK1/NU
CK0*
CK0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
RESET*
CAS*
RAS*
WE*
DDR3-240P-BL
DDR3-240P-BL
MB_EVENT_L
+DDR_VTTR
+VDIMM
+VCC3
SCLK0
SCLK012,14
SDATA0
SDATA012,14
MB_BANK2
MB_BANK23
MB_BANK1
MB_BANK13
MB_BANK0
MB_BANK03
MB_CKE1
MB_CKE13
MB_CKE0
MB_CKE03
MB0_CS_L1
MB0_CS_L13
MB0_CS_L0
MB0_CS_L03
MB0_CLK_N1
MB0_CLK_P1
MB0_CLK_N0
MB0_CLK_P0
MB_RESET_L
MB_CAS_L
MB_RAS_L
MB_WE_L
RSVD
ODT1
ODT0
NC/PAR IN
NC/ERR OUT
NC/TEST4
CB(0)
CB(1)
CB(2)
CB(3)
CB(4)
CB(5)
CB(6)
CB(7)
DQS(0)
DQS*(0)
DSQ(1)
DSQ*(1)
DSQ(2)
DSQ*(2)
DSQ(3)
DSQ*(3)
DQS(4)
DQS*(4)
DQS(5)
DQS*(5)
DSQ(6)
DSQ*(6)
DQS(7)
DQS*(7)
DQS(8)
DQS*(8)
DM0/DQS9
NC/DQS9*
DM1/DQS10
NC/DQS10*
DM2/DQS11
NC/DQS11*
DM3/DQS12
NC/DQS12*
DM4/DQS13
NC/DQS13*
DM5/DQS14
NC/DQS14*
DM6/DQS15
NC/DQS15*
DM7/DQS16
NC/DQS16*
DM8/DQS17
NC/DQS17*
DQ(0)
DQ(1)
DQ(2)
DQ(3)
DQ(4)
DQ(5)
DQ(6)
DQ(7)
DQ(8)
DQ(9)
DQ(10)
DQ(11)
DQ(12)
DQ(13)
DQ(14)
DQ(15)
DQ(16)
DQ(17)
DQ(18)
DQ(19)
DQ(20)
DQ(21)
DQ(22)
DQ(23)
DQ(24)
DQ(25)
DQ(26)
DQ(27)
DQ(28)
DQ(29)
DQ(30)
DQ(31)
DQ(32)
DQ(33)
DQ(34)
DQ(35)
DQ(36)
DQ(37)
DQ(38)
DQ(39)
DQ(40)
DQ(41)
DQ(42)
DQ(43)
DQ(44)
DQ(45)
DQ(46)
DQ(47)
DQ(48)
DQ(49)
DQ(50)
DQ(51)
DQ(52)
DQ(53)
DQ(54)
DQ(55)
DQ(56)
DQ(57)
DQ(58)
DQ(59)
DQ(60)
DQ(61)
DQ(62)
DQ(63)
2
79
MB0_ODT1
77
195
68
53
167
39
40
45
46
158
159
164
165
7
6
16
15
25
24
34
33
85
84
94
93
103
102
112
111
43
42
125
126
134
135
143
144
152
153
203
204
212
213
221
222
230
231
161
162
3
4
9
10
122
123
128
129
12
13
18
19
131
132
137
138
21
22
27
28
140
141
146
147
30
31
36
37
149
150
155
156
81
82
87
88
200
201
206
207
90
91
96
97
209
210
215
216
99
100
105
106
218
219
224
225
108
109
114
115
227
228
233
234
MB0_ODT0
MB_DQS_P0
MB_DQS_N0
MB_DQS_P1
MB_DQS_N1
MB_DQS_P2
MB_DQS_N2
MB_DQS_P3
MB_DQS_N3
MB_DQS_P4
MB_DQS_N4
MB_DQS_P5
MB_DQS_N5
MB_DQS_P6
MB_DQS_N6
MB_DQS_P7
MB_DQS_N7
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
MB0_ODT1 3
MB0_ODT0 3
MB_DQS_P0 3
MB_DQS_N0 3
MB_DQS_P1 3
MB_DQS_N1 3
MB_DQS_P2 3
MB_DQS_N2 3
MB_DQS_P3 3
MB_DQS_N3 3
MB_DQS_P4 3
MB_DQS_N4 3
MB_DQS_P5 3
MB_DQS_N5 3
MB_DQS_P6 3
MB_DQS_N6 3
MB_DQS_P7 3
MB_DQS_N7 3
MB_DM[7..0]
MB_DM[7..0] 3
+VDIMM
C371
C371
22u-6V3X-08-O
22u-6V3X-08-O
Place within 500 mils of the DIMM socket
2009 6 6 V0.1
C371,C380 reserved for SI
C499,C500 stuff for AMD NB Schematic Checklist
C370
C370
10U-08-O
10U-08-O
2009 6 6 V0.1
C370 reserved
for SI
MB_DATA[63..0]
MB_DATA[63..0] 3
1
2009 6 9 V0.1
Add C507 reserved
for AMD checklist
R376
R376
C507
15-1-04
15-1-04
R377
R377
15-1-04
15-1-04
+VDIMM
R345
R345
15-1-04
15-1-04
R335
R335
15-1-04
15-1-04
C507
.1U-04-O
.1U-04-O
C380
C380
22u-6V3X-08-O
22u-6V3X-08-O
C499
C499
.1U-04
.1U-04
2009 6 9 V0.1
Add C508 reserved
for AMD checklist
C508
C508
+MEM_VREFDQ
.1U-04-O
.1U-04-O
C342
C342
.1U-04
.1U-04
+MEM_VREFCA
C340
C340
1000P-04
1000P-04
C500
C500
1000P-04
1000P-04
Place within 500 mils of the DIMM socket
+VDIMM +VDIMM
DE-COULPING CAP FOR DIMMs
C364
C364
C361
C361
C367
C373
C373
1U-X5-04
1U-X5-04
1U-X5-04
1U-X5-04
5
4
1U-X5-04
1U-X5-04
C367
1U-X5-04
1U-X5-04
C365
C365
1U-X5-04
1U-X5-04
C374
C374
1U-X5-04
1U-X5-04
C369
C369
1U-X5-04
1U-X5-04
+DDR_VTTR
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
Title
Title
C359
C359
C366
1U-X5-04
1U-X5-04
C366
.1U-04
.1U-04
2
C358
C358
C368
C368
1U-X5-04
1U-X5-04
1U-X5-04
1U-X5-04
3
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
DDR3 DIMM
DDR3 DIMM
DDR3 DIMM
RS780Q-LM3
RS780Q-LM3
RS780Q-LM3
1
6
6
6
36Friday, July 03, 2009
36Friday, July 03, 2009
36Friday, July 03, 2009
0.1
0.1
0.1
5
D D
H_CADOUT_P0
TP54TP54
H_CADOUT_N0
TP55TP55
H_CADOUT_P1
TP56TP56
H_CADOUT_N1
TP57TP57
H_CADOUT_P2
TP58TP58
H_CADOUT_N2
TP59TP59
H_CADOUT_P3
TP60TP60
H_CADOUT_N3
TP61TP61
H_CADOUT_P4
TP62TP62
H_CADOUT_N4
TP63TP63
H_CADOUT_P5
TP64TP64
H_CADOUT_N5
TP65TP65
H_CADOUT_P6
TP66TP66
H_CADOUT_N6
TP67TP67
H_CADOUT_P7
TP68TP68
H_CADOUT_N7
TP69TP69
TP71TP71
TP72TP72
TP73TP73
H_CADOUT_P8
H_CADOUT_N8
H_CADOUT_P9
H_CADOUT_N9
H_CADOUT_P10
H_CADOUT_N10
H_CADOUT_P11
H_CADOUT_N11
H_CADOUT_P12
H_CADOUT_N12
H_CADOUT_P13
H_CADOUT_N13
H_CADOUT_P14
H_CADOUT_N14
H_CADOUT_P15
H_CADOUT_N15
H_CLKOUT_P0
H_CLKOUT_N0
H_CLKOUT_P1
H_CLKOUT_N1
H_CTLOUT_P0
H_CTLOUT_N0
H_CTLOUT_P1
H_CTLOUT_N1
STP40STP40
STP41STP41
STP42STP42
C C
B B
STP43STP43
STP44STP44
STP45STP45
STP46STP46
STP47STP47
STP48STP48
STP49STP49
STP50STP50
STP51STP51
STP52STP52
STP53STP53
STP54STP54
STP55STP55
STP56STP56
STP57STP57
STP58STP58
STP59STP59
H_CADOUT_P03
H_CADOUT_N03
H_CADOUT_P13
H_CADOUT_N13
H_CADOUT_P23
H_CADOUT_N23
H_CADOUT_P33
H_CADOUT_N33
H_CADOUT_P43
H_CADOUT_N43
H_CADOUT_P53
H_CADOUT_N53
H_CADOUT_P63
H_CADOUT_N63
H_CADOUT_P73
H_CADOUT_N73
H_CADOUT_P83
H_CADOUT_N83
H_CADOUT_P93
H_CADOUT_N93
H_CADOUT_P103
H_CADOUT_N103
H_CADOUT_P113
H_CADOUT_N113
H_CADOUT_P123
H_CADOUT_N123
H_CADOUT_P133
H_CADOUT_N133
H_CADOUT_P143
H_CADOUT_N143
H_CADOUT_P153
H_CADOUT_N153
H_CLKOUT_P03
H_CLKOUT_N03
H_CLKOUT_P13
H_CLKOUT_N13
H_CTLOUT_P03
H_CTLOUT_N03
H_CTLOUT_P13
H_CTLOUT_N13
H_CADOUT_P0
H_CADOUT_N0
H_CADOUT_P1
H_CADOUT_N1
H_CADOUT_P2
H_CADOUT_N2
H_CADOUT_P3
H_CADOUT_N3
H_CADOUT_P4
H_CADOUT_N4
H_CADOUT_P5
H_CADOUT_N5
H_CADOUT_P6
H_CADOUT_N6
H_CADOUT_P7
H_CADOUT_N7
H_CADOUT_P8
H_CADOUT_N8
H_CADOUT_P9
H_CADOUT_N9
H_CADOUT_P10
H_CADOUT_N10
H_CADOUT_P11
H_CADOUT_N11
H_CADOUT_P12
H_CADOUT_N12
H_CADOUT_P13
H_CADOUT_N13
H_CADOUT_P14
H_CADOUT_N14
H_CADOUT_P15
H_CADOUT_N15
H_CLKOUT_P0
H_CLKOUT_N0
H_CLKOUT_P1
H_CLKOUT_N1
H_CTLOUT_P0
H_CTLOUT_N0
H_CTLOUT_P1
H_CTLOUT_N1
R148 301-1-04R148 301-1-04
1 2
2009 6 6 V0.1
Del R153,R142
for not Co-lay RS740
4
NB1A
NB1A
Y25
HT_RXCAD0P
HT_RXCALP
HT_RXCALN
Y24
HT_RXCAD0N
V22
HT_RXCAD1P
V23
HT_RXCAD1N
V25
HT_RXCAD2P
V24
HT_RXCAD2N
U24
HT_RXCAD3P
U25
HT_RXCAD3N
T25
HT_RXCAD4P
T24
HT_RXCAD4N
P22
HT_RXCAD5P
P23
HT_RXCAD5N
P25
HT_RXCAD6P
P24
HT_RXCAD6N
N24
HT_RXCAD7P
N25
HT_RXCAD7N
AC24
HT_RXCAD8P
AC25
HT_RXCAD8N
AB25
HT_RXCAD9P
AB24
HT_RXCAD9N
AA24
HT_RXCAD10P
AA25
HT_RXCAD10N
Y22
HT_RXCAD11P
Y23
HT_RXCAD11N
W21
HT_RXCAD12P
W20
HT_RXCAD12N
V21
HT_RXCAD13P
V20
HT_RXCAD13N
U20
HT_RXCAD14P
U21
HT_RXCAD14N
U19
HT_RXCAD15P
U18
HT_RXCAD15N
T22
HT_RXCLK0P
T23
HT_RXCLK0N
AB23
HT_RXCLK1P
AA22
HT_RXCLK1N
M22
HT_RXCTL0P
M23
HT_RXCTL0N
R21
HT_RXCTL1P
R20
HT_RXCTL1N
C23
HT_RXCALP
A24
HT_RXCALN
RS780L A13
RS780L A13
01-201-215123
PART 1 OF 6
PART 1 OF 6
3
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_TXCALP
HT_TXCALN
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
H24
H25
L21
L20
M24
M25
P19
R18
B24
B25
HT_TXCALP
HT_TXCALN
H_CADIN_P0
H_CADIN_N0
H_CADIN_P1
H_CADIN_N1
H_CADIN_P2
H_CADIN_N2
H_CADIN_P3
H_CADIN_N3
H_CADIN_P4
H_CADIN_N4
H_CADIN_P5
H_CADIN_N5
H_CADIN_P6
H_CADIN_N6
H_CADIN_P7
H_CADIN_N7
H_CADIN_P8
H_CADIN_N8
H_CADIN_P9
H_CADIN_N9
H_CADIN_P10
H_CADIN_N10
H_CADIN_P11
H_CADIN_N11
H_CADIN_P12
H_CADIN_N12
H_CADIN_P13
H_CADIN_N13
H_CADIN_P14
H_CADIN_N14
H_CADIN_P15
H_CADIN_N15
H_CLKIN_P0
H_CLKIN_N0
H_CLKIN_P1
H_CLKIN_N1
H_CTLIN_P0
H_CTLIN_N0
H_CTLIN_P1
H_CTLIN_N1
R163 301-1-04R163 301-1-04
1 2
2009 6 6 V0.1
Del SR32,SR33
for not Co-lay RS740
2
H_CADIN_P0 3
H_CADIN_N0 3
H_CADIN_P1 3
H_CADIN_N1 3
H_CADIN_P2 3
H_CADIN_N2 3
H_CADIN_P3 3
H_CADIN_N3 3
H_CADIN_P4 3
H_CADIN_N4 3
H_CADIN_P5 3
H_CADIN_N5 3
H_CADIN_P6 3
H_CADIN_N6 3
H_CADIN_P7 3
H_CADIN_N7 3
H_CADIN_P8 3
H_CADIN_N8 3
H_CADIN_P9 3
H_CADIN_N9 3
H_CADIN_P10 3
H_CADIN_N10 3
H_CADIN_P11 3
H_CADIN_N11 3
H_CADIN_P12 3
H_CADIN_N12 3
H_CADIN_P13 3
H_CADIN_N13 3
H_CADIN_P14 3
H_CADIN_N14 3
H_CADIN_P15 3
H_CADIN_N15 3
H_CLKIN_P0 3
H_CLKIN_N0 3
H_CLKIN_P1 3
H_CLKIN_N1 3
H_CTLIN_P0 3
H_CTLIN_N0 3
H_CTLIN_P1 3
H_CTLIN_N1 3
1
H_CADIN_P0
H_CADIN_N0
H_CADIN_P1
H_CADIN_N1
H_CADIN_P2
H_CADIN_N2
H_CADIN_P3
H_CADIN_N3
H_CADIN_P4
H_CADIN_N4
H_CADIN_P5
H_CADIN_N5
H_CADIN_P6
H_CADIN_N6
H_CADIN_P7
H_CADIN_N7
H_CADIN_P8
H_CADIN_N8
H_CADIN_P9
H_CADIN_N9
H_CADIN_P10
H_CADIN_N10
H_CADIN_P11
H_CADIN_N11
H_CADIN_P12
H_CADIN_N12
H_CADIN_P13
H_CADIN_N13
H_CADIN_P14
H_CADIN_N14
H_CADIN_P15
H_CADIN_N15
H_CLKIN_P0
H_CLKIN_N0
H_CLKIN_P1
H_CLKIN_N1
H_CTLIN_P0
H_CTLIN_N0
H_CTLIN_P1
H_CTLIN_N1
TP74TP74
TP75TP75
TP76TP76
TP77TP77
TP78TP78
TP79TP79
TP80TP80
TP81TP81
TP82TP82
TP83TP83
TP84TP84
TP85TP85
TP86TP86
TP87TP87
TP88TP88
TP89TP89
STP60STP60
STP61STP61
STP62STP62
STP63STP63
STP64STP64
STP65STP65
STP66STP66
STP67STP67
STP68STP68
STP69STP69
STP70STP70
STP71STP71
STP72STP72
STP73STP73
STP74STP74
STP75STP75
TP90TP90TP70TP70
TP91TP91
STP76STP76
STP77STP77
TP92TP92
TP93TP93
STP78STP78
STP79STP79
080907 add ICT test point
HT LINK STITCHING CAPS.
+VCORE
A A
5
4
C202
C202
C215
C215
C197
.1u-04
.1u-04
C197
.1u-04
.1u-04
2 1
2 1
3
.1u-04
.1u-04
2 1
2 1
C224
C224
.1u-04
.1u-04
C141
C141
C173
C173
C189
.1u-04
.1u-04
2 1
C189
.1u-04
.1u-04
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
RS780-HT LINK I/F
RS780-HT LINK I/F
RS780-HT LINK I/F
RS780Q-LM3
RS780Q-LM3
RS780Q-LM3
7
7
7
1
36Tuesday, June 30, 2009
36Tuesday, June 30, 2009
36Tuesday, June 30, 2009
0.1
0.1
0.1
.1u-04
.1u-04
2 1
2 1
5
4
3
2
1
NB1B
NB1B
AE3
AD4
AE2
AD3
AD1
AD2
AA8
AA7
AA5
AA6
D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3
V5
W6
U5
U6
U8
U7
Y8
Y7
W5
Y5
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
RS780L A13
RS780L A13
PART 2 OF 6
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
GFX_RX0P19
GFX_RX0N19
D D
C C
B B
GFX_RX1P19
GFX_RX1N19
GFX_RX2P19
GFX_RX2N19
GFX_RX3P19
GFX_RX3N19
GFX_RX4P19
GFX_RX4N19
GFX_RX5P19
GFX_RX5N19
GFX_RX6P19
GFX_RX6N19
GFX_RX7P19
GFX_RX7N19
GFX_RX8P19
GFX_RX8N19
GFX_RX9P19
GFX_RX9N19
GFX_RX10P19
GFX_RX10N19
GFX_RX11P19
GFX_RX11N19
GFX_RX12P19
GFX_RX12N19
GFX_RX13P19
GFX_RX13N19
GFX_RX14P19
GFX_RX14N19
GFX_RX15P19
GFX_RX15N19
GPP_RX0P19
GPP_RX0N19
GPP_RX1P19
GPP_RX1N19
GPP_RX3P24
GPP_RX3N24
A_RX0P13
A_RX0N13
A_RX1P13
A_RX1N13
A_RX2P13
A_RX2N13
A_RX3P13
A_RX3N13
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
AC8
AB8
GFX_TX0P_CGFX_TX0P_C
GFX_TX0N_CGFX_TX0N_C
GFX_TX1P_CGFX_TX1P_C
GFX_TX1N_C
GFX_TX2P_CGFX_TX2P_C
GFX_TX2N_CGFX_TX2N_C
GFX_TX3P_CGFX_TX3P_C
GFX_TX3N_CGFX_TX3N_C
GFX_TX4P_CGFX_TX4P_C
GFX_TX4N_CGFX_TX4N_C
GFX_TX5P_CGFX_TX5P_C
GFX_TX5N_CGFX_TX5N_C
GFX_TX6P_CGFX_TX6P_C
GFX_TX6N_CGFX_TX6N_C
GFX_TX7P_CGFX_TX7P_C
GFX_TX7N_CGFX_TX7N_C
GFX_TX8P_CGFX_TX8P_C
GFX_TX8N_CGFX_TX8N_C
GFX_TX9P_C
GFX_TX9N_C
GFX_TX10P_C
GFX_TX10N_C
GFX_TX11P_C
GFX_TX11N_C
GFX_TX12P_C
GFX_TX12N_C
GFX_TX13P_C
GFX_TX13N_C
GFX_TX14P_C
GFX_TX14N_C
GFX_TX15P_C
GFX_TX15N_C
GPP_TX0P_C
GPP_TX0N_C
GPP_TX1P_C
GPP_TX1N_C
GPP_TX3P_C
GPP_TX3N_C
A_TX0P_CA_TX0P_C
A_TX0N_CA_TX0N_C
A_TX1P_CA_TX1P_C
A_TX1N_CA_TX1N_C
A_TX2P_C
A_TX2N_C
A_TX3P_C
A_TX3N_C
PCE_CALRP
PCE_CALRN
X7R:for PCI-E
C142 .1U-X7-04C142 .1U-X7-04
21
C146 .1U-X7-04C146 .1U-X7-04
21
C152 .1U-X7-04C152 .1U-X7-04
21
C153 .1U-X7-04C153 .1U-X7-04
21
C158 .1U-X7-04C158 .1U-X7-04
21
C156 .1U-X7-04C156 .1U-X7-04
21
C160 .1U-X7-04C160 .1U-X7-04
21
C162 .1U-X7-04C162 .1U-X7-04
21
C171 .1U-X7-04C171 .1U-X7-04
21
C174 .1U-X7-04C174 .1U-X7-04
21
C188 .1U-X7-04C188 .1U-X7-04
21
C190 .1U-X7-04C190 .1U-X7-04
21
C196 .1U-X7-04C196 .1U-X7-04
21
C200 .1U-X7-04C200 .1U-X7-04
21
C204 .1U-X7-04C204 .1U-X7-04
21
C206 .1U-X7-04C206 .1U-X7-04
21
C213 .1U-X7-04C213 .1U-X7-04
21
C216 .1U-X7-04C216 .1U-X7-04
21
C223 .1U-X7-04C223 .1U-X7-04
21
C228 .1U-X7-04C228 .1U-X7-04
21
C234 .1U-X7-04C234 .1U-X7-04
21
C244 .1U-X7-04C244 .1U-X7-04
21
C253 .1U-X7-04C253 .1U-X7-04
21
C259 .1U-X7-04C259 .1U-X7-04
21
C263 .1U-X7-04C263 .1U-X7-04
21
C269 .1U-X7-04C269 .1U-X7-04
21
C278 .1U-X7-04C278 .1U-X7-04
21
C282 .1U-X7-04C282 .1U-X7-04
21
C289 .1U-X7-04C289 .1U-X7-04
21
C293 .1U-X7-04C293 .1U-X7-04
21
C296 .1U-X7-04C296 .1U-X7-04
21
C298 .1U-X7-04C298 .1U-X7-04
21
C144 .1U-X7-04C144 .1U-X7-04
21
C147 .1U-X7-04C147 .1U-X7-04
21
C148 .1U-X7-04C148 .1U-X7-04
21
C145 .1U-X7-04C145 .1U-X7-04
21
C159 .1U-X7-04C159 .1U-X7-04
21
C161 .1U-X7-04C161 .1U-X7-04
21
C183 .1U-X7-04C183 .1U-X7-04
21
C184 .1U-X7-04C184 .1U-X7-04
21
C191 .1U-X7-04C191 .1U-X7-04
21
C192 .1U-X7-04C192 .1U-X7-04
21
C182 .1U-X7-04C182 .1U-X7-04
21
C181 .1U-X7-04C181 .1U-X7-04
21
C177 .1U-X7-04C177 .1U-X7-04
21
C178 .1U-X7-04C178 .1U-X7-04
21
R200 1.27K-1-04R200 1.27K-1-04
1 2
R199 2K-1-04R199 2K-1-04
1 2
+NB_VCC
GFX_TX0P 19
GFX_TX0N 19
GFX_TX1P 19
GFX_TX1N 19
GFX_TX2P 19
GFX_TX2N 19
GFX_TX3P 19
GFX_TX3N 19
GFX_TX4P 19
GFX_TX4N 19
GFX_TX5P 19
GFX_TX5N 19
GFX_TX6P 19
GFX_TX6N 19
GFX_TX7P 19
GFX_TX7N 19
GFX_TX8P 19
GFX_TX8N 19
GFX_TX9P 19
GFX_TX9N 19
GFX_TX10P 19
GFX_TX10N 19
GFX_TX11P 19
GFX_TX11N 19
GFX_TX12P 19
GFX_TX12N 19
GFX_TX13P 19
GFX_TX13N 19
GFX_TX14P 19
GFX_TX14N 19
GFX_TX15P 19
GFX_TX15N 19
GPP_TX0P 19
GPP_TX0N 19
GPP_TX1P 19
GPP_TX1N 19
GPP_TX3P 24
GPP_TX3N 24
A_TX0P 13
A_TX0N 13
A_TX1P 13
A_TX1N 13
A_TX2P 13
A_TX2N 13
A_TX3P 13
A_TX3N 13
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
RS780-PCIE I/F
RS780-PCIE I/F
RS780-PCIE I/F
RS780Q-LM3
RS780Q-LM3
RS780Q-LM3
8
8
8
1
36Tuesday, June 30, 2009
36Tuesday, June 30, 2009
36Tuesday, June 30, 2009
0.1
0.1
0.1
5
+VCC3
2009 6 6 V0.1
Del I2C_DATA,I2C_CLK
to R125,R124 +VDDG_NB
for not Co-lay RS740
+VCC
2009 6 6 V0.1
D D
Change RJ3,RJ4 to R120,R142
for not Co-lay RS740
C C
B B
DDR3: Connected to Southbridge and CPU
through a level shifter set to 3.3 V_S0 at the Northbridge.
DDR2:Connected directly to Southbridge and CPU.
Level-shifter not required.
A A
SCL0_AUX0P
SDA0_AUX0N
SC132
SC132
2 1
10P-04-X-O
10P-04-X-O
H_STOP_L4,13
RS780 difference table (Control signal)
NB_PWRGD
IN
ALLOW_LDTSTOP
OUT(default)/IN
H_STOP_L
IN(default)/OUT
SYSTEMRESETb 3.3V IN
IN
R120 4.7K-04R120 4.7K-04
R142 4.7K-04R142 4.7K-04
SC133
SC133
2 1
10P-04-X-O
10P-04-X-O
OSC_14M_NB
C114
C114
10P-04-O
10P-04-O
2009 6 6 V0.1
Del Net RS740_DFT_GPIO0
RS740_DFT_GPIO2
for not Co-lay RS740
2009 6 6 V0.1
Del Net RS740_DFT_GPIO3
for not Co-lay RS740
03-050-530106
SN74LVC1G08-O
SN74LVC1G08-O
RS780
1.8V IN
OD/3.3V IN
3.3V IN/OD
5
1 2
1 2
ROUT
GOUT
BOUT
SC134
SC134
2 1
10P-04-X-O
10P-04-X-O
+1.8V
Q13
Q13
G
FDV301N-S
FDV301N-S
U5
U5
1
2
3 4
OD-BUFFER(NEED PULL HIGH)SN74LVC1G07
+1.8V +1.8V_PLL
+1.8V
12
DS
+1.8V
5
SINGLE 2-INPUT AND GATESN74LVC1G08(02-197-008133)
+VCC
ROUT18
GOUT18
BOUT18
HSYNC10,18
VSYNC10,18
DDCCLK18
DDCDATA18
R1120R112
0
1 2
2009 6 6 V0.1
Del VDDA18PCIEPLL
to SFB7 to +NB_VCC
for not Co-lay RS740
ALLOW_LDTSTOP13
KG_NBHT_CLKP12
KG_NBHT_CLKN12
OSC_14M_NB12
KG_NBGFX_CLKP12
KG_NBGFX_CLKN12
KG_NBREF_CLKP12
KG_NBREF_CLKN12
I2C_CLK18
I2C_DATA18
SDA0_AUX0N19
SCL0_AUX0P19
RS740_DFT_GPIO110
2009 6 16 V0.1
Change +VCC3
to +1.8V
for not Co-lay RS740
R117
R117
1K-04
1K-04
NB_LDT_STOP-
2009 6 6 V0.1
Add U5 reserved for SI
+1.8V
+1.8V_PLL
+NB_VCC
SFB3 0-04-XSFB3 0-04-X
1 2
FB14 FB600-04FB14 FB600-04
1 2
SFB2 FB600-04-XSFB2 FB600-04-X
1 2
SFB6 FB600-04-XSFB6 FB600-04-X
1 2
2009 6 6 V0.1
Del R169 for not Co-lay RS740
+NB_VCC
4
600 ohm 300mA =>16-105-601141
0402 bead
SFB4 FB600-04-XSFB4 FB600-04-X
2009 6 6 V0.1
Change SC7
from 10uF to 2.2uF
for AMD Schematic
Review Checklist
SFB1 FB600-04-XSFB1 FB600-04-X
16-105-601370
1 2
2009 6 6 V0.1
Del SR1
for cost down
1 2
2009 6 6 V0.1
Change SC8
from 10uF to 2.2uF
for AMD Schematic
Review Checklist
31mA
2009 6 15 V0.1
Change SR17 from 680ohm
to 715ohm For AMD review
7.6mA
10mA
37mA
SC12
SC12
2.2U-X
2.2U-X
2 1
2 1
SR4 150-1-04-XSR4 150-1-04-X
1 2
RS780 stuff
C179
C179
SC135
SC135
.1U-04-O
.1U-04-O
.1U-04-X-O
.1U-04-X-O
2 1
2 1
PCIE_RST-10,13,22,24
2009 6 6 V0.1
Del R118,R121
for not Co-lay RS740
RS780 JTAG PIN MAPPING
TRST
TMS(TP220)
TDI
TCK
TDO(TP218)
4
SC10
SC10
.1U-04-X-O
.1U-04-X-O
2 1
SC20
SC20
.1U-X7-04-X
.1U-X7-04-X
2 1
0.81mA
SC6
SC6
.1U-04-X-O
.1U-04-X-O
2 1
PLLVDD
PLLVDD18
VDDA18HTPLL
SC15
SC15
2.2U-X
2.2U-X
PLLVDD
PLLVDD18
VDDA18HTPLL
VDDA18PCIEPLL
SC136
SC136
.1U-04-X
.1U-04-X
2 1
0.07mA
2009 6 6 V0.1
SC13 reserved
for cost down
2009 6 6 V0.1
SC6 reserved
for SI
SR17
SR17
1 2
715-1-04-X
715-1-04-X
NB_RST-
AVDD
SC7
SC7
2.2U-X5-08-X
2.2U-X5-08-X
2 1
SC13
SC13
2.2U-X-O
2.2U-X-O
2 1
AVDDQ
SC8
SC8
2.2U-X5-08-X
2.2U-X5-08-X
2 1
RS780 A13 for 140ohm
SR10 140-1-04-XSR10 140-1-04-X
1 2
SR9 150-1-04-XSR9 150-1-04-X
1 2
SR8 150-1-04-XSR8 150-1-04-X
1 2
VDDA18PCIEPLL
SC5
SC5
C116
C116
2.2U-X
2.2U-X
2.2U
2.2U
2 1
2 1
SR3 150-1-04-XSR3 150-1-04-X
1 2
2009 6 6 V0.1 Del STRP_DATA
to R126 to +VCC3 for not Co-lay RS740
SC137
SC137
.1U-04-X-O
.1U-04-X-O
2 1
R158 0-04R158 0-04
1 2
RS740 & RS780 only
RS740/RS780
TEST_EN
DDC_DATA(TP223)
I2C_DATA
I2C_CLK
TMDS_HPD(TP221)
DAC_RSET
08'1028
NB_RSTNB_PWRGD_IN
NB_LDT_STOP-
OSC_14M_NB
REFCLK_INN
3
NB1C
NB1C
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
A11
DAC_HSYNC(PWM_GPIO4)
B11
DAC_VSYNC(PWM_GPIO6)
F8
DAC_SCL(PCE_RCALRN)
E8
DAC_SDA(PCE_TCALRN)
G14
DAC_RSET(PWM_GPIO1)
A12
PLLVDD(NC)
D14
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN(OSCIN)
F11
REFCLK_N(PWM_GPIO3)
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP(SB_REFCLKP)
V3
GPPSB_REFCLKN(SB_REFCLKN)
B9
I2C_CLK
A9
I2C_DATA
B8
DDC_DATA0/AUX0N(NC)
A8
DDC_CLK0/AUX0P(NC)
B7
DDC_CLK1/AUX1P(NC)
A7
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
G11
RSVD
C8
AUX_CAL(NC)
RS780L A13
RS780L A13
NB_PWRGD_IN
RS740: Powered from the 3.3-V rail.
RS780: Powered from the 1.8-V rail.
WD_PWRGD14
SB_PWRGD14,22,27,29,31
PART 3 OF 6
PART 3 OF 6
R119 0-04R119 0-04
R137 0-04-OR137 0-04-O
080911 add level shift
RS780 DEBUG PIN MAPPING
DEBUG_OUT0
DEBUG_OUT1
DEBUG_OUT2
DEBUG_OUT3
DEBUG_OUT4
DEBUG_OUT5
DEBUG_OUT6
DEBUG_OUT7
3
RS780
LVDS_DIGON
LVDS_ENA_BL
LVDS_BLON
TMDS_HPD
AUX1N
AUX1P
HPD
AUX_CAL
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3N(DBG_GPIO2)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
CRT/TVOUT
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
LVTM
LVTM
PM
PM
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
CLOCKs PLL PWR
CLOCKs PLL PWR
MIS.
MIS.
SUS_STAT#(PWM_GPIO5)
1 2
1 2
co-lay 74LVC32
2
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L3P(NC)
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3N(NC)
VDDLTP18(NC)
VSSLTP18(NC)
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
TMDS_HPD(NC)
HPD(NC)
THERMALDIODE_P
THERMALDIODE_N
TESTMODE
NB_PWRGD_IN voltage
RS740:3.3V
RS780:1.8V
U18
U18
1
2
3 4
SN74AUC1G17DBVR
SN74AUC1G17DBVR
R466
2
R466
1 2
0-04-O
0-04-O
PWRGD_X
TMDS_00P
A22
TMDS_00N
B22
TMDS_01P
A21
TMDS_01N
B21
TMDS_02P
B20
TMDS_02N
A20
A19
B19
B18
A18
A17
B17
D20
D21
D18
D19
TMDS_CLKP
B16
TMDS_CLKN
A16
D16
D17
VDDLTP18
A13
B13
VDDLT18
A15
B15
A14
B14
C14
D15
C16
C18
C20
E20
C22
E9
F7
G12
D9
D10
D12
AE8
AD8
TEST_EN
D13
+1.8V
5
NB_PWRGD_IN
02-197-017130
02-196-017030
1
2009 6 6 V0.1
Del R138,R147,R156
R155,R146,R137,R145
for not Co-lay RS740
TMDS_00P 18
TMDS_00N 18
TMDS_01P 18
TMDS_01N 18
TMDS_02P 18
TMDS_02N 18
2009 6 6 V0.1
Del PinA19~B17 Net
for DVI cost down
TMDS_CLKP 18
TMDS_CLKN 18
2 1
2 1
TMDS_HPD2 18
TMDS_HPD0 19
SUS_STAT- 10,14
NB_THERMDA 16
NB_THERMDC 16
C461
C461
.1U-04-O
.1U-04-O
21
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
9mA
FB13 FB600-04FB13 FB600-04
1 2
C112
C112
2.2U
2.2U
C111
C111
.1U-04
.1U-04
12
SR14
SR14
1.8K-04-X
1.8K-04-X
2009 6 23 V0.1
Del Add R119,U18,C461,R137,R466,
for SI
2009 6 6 V0.1
C102
C102
2.2U-O
2.2U-O
C102 reserved for cost down
2 1
1 2
FB12 FB600P-08FB12 FB600P-08
C101
C101
4.7U-08
4.7U-08
2 1
2009 6 6 V0.1
Del Net RS740_DFT_GPIO5
for not Co-lay RS740
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
RS780-SYSTEM I/F
RS780-SYSTEM I/F
RS780-SYSTEM I/F
+1.8V_PLL
96mA
Q14_D
D S
2N7002-S
2N7002-S
2009 6 6 V0.1
Del FB15,C115,Q12
for not Co-lay RS740
RS780Q-LM3
RS780Q-LM3
RS780Q-LM3
1
+1.8V
Q14
Q14
G
+12V
0.1
0.1
9
9
9
0.1
36Monday, July 06, 2009
36Monday, July 06, 2009
36Monday, July 06, 2009
5
4
3
2
1
RS740/RS780 STRAPS
Note: for RS780, change RJJ to 150R as AUX_CAL,place close to pin C8
D D
RS740_DFT_GPIO19
Note:RS740_DFT_GPIO1:Made provision for external pull-down
which is not installed by default. Northbridge has an internal pull-up
for bypassing EEPROM strapping and using default values for RS740
RJJ
R143 150-04R143 150-04
1 2
D14 1N4148-S-OD14 1N4148-S-O
P N
PCIE_RST- 9,13,22,24SUS_STAT-9,14
RS740/RS780: LOAD_EEPROM_STRAPS
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740: pin DFT_GPIO1
RS780: pin SUS_STAT#
NB1D
NB1D
AB12
MEM_A0(NC)
AE16
MEM_A1(NC)
V11
MEM_A2(NC)
AE15
MEM_A3(NC)
AA12
MEM_A4(NC)
AB16
MEM_A5(NC)
AB14
MEM_A6(NC)
AD14
MEM_A7(NC)
AD13
MEM_A8(NC)
AD15
C C
STP82
1
STP82STP82
B B
AC16
AE13
AC14
Y14
AD16
AE17
AD17
W12
Y12
AD18
AB13
AB18
V14
V15
W14
AE12
AD12
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)
MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)
MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)
MEM_CKP(NC)
MEM_CKN(NC)
MEM_COMPP(NC)
MEM_COMPN(NC)
RS780L A13
RS780L A13
PAR 4 OF 6
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
IOPLLVDD18(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)
MEM_VREF(NC)
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
Y17
W18
AD20
AE21
W17
AE19
AE23
AE24
AD23
AE18
VSYNC9,18
+NB_VCC+1.8V
HSYNC9,18
R145 3K-1-04R145 3K-1-04
1 2
R146 3K-1-04R146 3K-1-04
1 2
+VCC3
2009 6 6 V0.1
Del RJ2,RJ7;
Add R145
for not Co-lay RS740
2009 6 6 V0.1
Del SR2,SR5,R143
for not Co-lay RS740
+VCC3
2009 6 6 V0.1
Del RJ1,RJ6;
Add R146
for not Co-lay RS740
RS740/RS780: STRAP_DEBUG_BUS_GPIO_ENABLE
Enables the Test Debug Bus using GPIO and/or memory IO
1 : Disable (RS740/RS780); Enable (RX780)
0 : Enable (RS740/RS780); Disable(RX780)
RS740: pin DFT_GPIO5
RS780: pin VSYNC
RS740/RS780: SIDE-PORT
MEMORY ENABLE
Enables Side port memory
1. Disable (RS740/RS780)
0 : Enable (RS740/RS780)
RS740: pin DFT_GPIO0
RS780: pin HSYNC
RS780:
STRAP_DEBUG_BUS_PCIE_ENABLE
Enables Test debug bus
using PCIE bus
1. Disable (can be enabled
thru nbcfg register)
0 : Enable
RS780: configurable thru register
setting only
RS740: Not supported
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
RS780-SPMEM/STRAPS
RS780-SPMEM/STRAPS
RS780-SPMEM/STRAPS
RS780Q-LM3
RS780Q-LM3
RS780Q-LM3
10
10
10
1
36Friday, July 03, 2009
36Friday, July 03, 2009
36Friday, July 03, 2009
0.1
0.1
0.1
5
4
3
2
1
RS740/RS780 POWER DIFFERENCE TABLE
PIN NAME
D11
E14
E15
J12
K14
M11
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
AE14
D D
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
GROUND
GROUND
PART 6/6
PART 6/6
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
P15
R11
R14
T12
U14
VSS20
U11
VSSAHT20
J22
L17
L22
L24
A25
E22
D23
G22
G24
G25
C C
+NB_VCC
H19
L25
P20
N22
R19
M20
2009 6 10 V0.1
change SC18、SC9 from 22U to 4.7U
for AMD Schematic Checklist
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
L12
M14
N13
P12
299mA
SC27
SC27
SC23
SC18
SC18
4.7U-08-X
4.7U-08-X
2 1
SC23
.1U-X7-04-X
.1U-X7-04-X
2 1
.1U-X7-04-X
.1U-X7-04-X
2 1
SC19
SC19
.1U-X7-04-X
.1U-X7-04-X
2 1
384mA
2009 6 6 V0.1
Del FB22,SFB5,SR11
for cost down
+1.2V
SC9
SC9
4.7U-08-X
4.7U-08-X
2 1
2 1
SC16
SC16
.1U-X7-04-X
.1U-X7-04-X
SC17
SC17
.1U-X7-04-X
.1U-X7-04-X
2 1
SC21
SC21
.1U-X7-04-X
.1U-X7-04-X
2 1
282mA
SC42
SC152
SC152
4.7U-08-X
4.7U-08-X
2 1
B B
+1.8V
SFB8
SFB8
1 2
FB600P-08-X
FB600P-08-X
A A
5
225mA
SC45
SC45
4.7U-08-X
4.7U-08-X
2 1
SC46
SC46
4.7U-08-X
4.7U-08-X
2 1
+1.8V
2009 6 6 V0.1
Del SR12
cost down
SC42
.1U-X7-04-X
.1U-X7-04-X
2 1
2 1
SC43
SC43
.1U-X7-04-X
.1U-X7-04-X
2 1
2 1
SC14
SC14
1U-X5-04-X
1U-X5-04-X
2 1
2009 6 6 V0.1
Del R195
for not Co-lay RS740
SC36
SC36
.1U-X7-04-X
.1U-X7-04-X
SC38
SC38
.1U-X7-04-X
.1U-X7-04-X
18mA
SC144
SC144
.1U-04-X
.1U-04-X
2 1
SC35
SC35
.1U-X7-04-X
.1U-X7-04-X
2 1
4
SC39
SC39
.1U-X7-04-X
.1U-X7-04-X
2 1
VDDA18PCIE
SC44
SC44
.1U-X7-04-X
.1U-X7-04-X
2 1
VSSAPCIE39
VSSAPCIE40
VSS21
VSS22
VSS23
VSS24
V12
U15
W11
W15
VSS1
VSS25
AC12
VSS2
VSS26
AA14
M16
G19
AE25
AD24
AC23
AB22
AA21
W19
M17
M10
AD9
AE11
AD11
VSS3G8VSS4
VSS27
Y18
J17
K16
L16
P16
R16
T16
H18
F20
E21
D22
B23
A23
Y20
V18
U17
T17
R17
P17
J10
P10
K10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AE9
U10
F9
G9
AB11
L15
J15
VSS5
VSS7
VSS8
VSS9
VSS6
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
K11
AB15
AB17
AB19
AE20
AB21
NB1E
NB1E
VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7
VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7
VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)
RS780L A13
RS780L A13
NB1F
NB1F
RS780L A13
RS780L A13
VSS10
VSS34
PART 5/6
PART 5/6
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
POWER
POWER
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
VDD33_1(NC)
VDD33_2(NC)
3
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
AE10
AA11
Y11
AD10
AB10
AC10
H11
H12
VDDHT
VDDHTRX
VDDHTTX
VDDA18PCIE
VDD18
VDD18_MEM +1.8V
VDDPCIE
VDDC
VDD_MEM
VDD33
IOPLLVDD18
SC150
SC150
.1U-04-X
.1U-04-X
2 1
2 1
SC11
SC11
.1U-X7-04-X
.1U-X7-04-X
2 1
2 1
60mA
SC24
SC24
.1U-X7-04-X
.1U-X7-04-X
2 1
2 1
RS740 RS740 RS780
NC
+1.2V
NC
+1.8V
NC
+1.2V +1.1V
+1.2V
+1.8V
+3.3V
+1.8V +1.8V
SC34
SC34
SC22
SC22
.1U-X7-04-X
.1U-X7-04-X
1U-X5-04-X
1U-X5-04-X
2 1
SC33
SC33
SC37
SC37
.1U-X7-04-X
.1U-X7-04-X
.1U-X7-04-X
.1U-X7-04-X
2 1
+VCC3
2009 6 6 V0.1
SC25
SC25
.1U-X7-04-X
.1U-X7-04-X
Del SR19
cost down
2
+1.8V(DDR2)
+1.5V(DDR3)
SC151
SC151
1U-X5-04-X
1U-X5-04-X
2 1
SC40
SC40
.1U-X7-04-X
.1U-X7-04-X
2 1
RS780
+1.1V
+1.1V
+1.2V
+1.8V
+1.8V
+1.8V
+1.1V
+3.3V
2 1
PIN NAME
IOPLLVDD
AVDDDI
AVDDQ
PLLVDD
PLLVDD18
VDDA18HTPLL
VDDLTP18
VDDLT18
VDDLT33
+1.2V
+3.3V
+1.8V +1.8V
+1.8V +1.8V
+1.2V
+1.8V
+1.2VVDDA18PCIEPLL
+1.8V
+1.8V
+1.8V
+3.3V
+NB_VCC
+1.1V
+3.3VAVDDNC
+1.1V
+1.8V
+1.8V
+1.8V
+1.8V
NC
693mA
2009 6 6 V0.1
Del R159
C483
C483
4.7U-08
4.7U-08
2 1
SC31
SC31
4.7U-08-X-O
4.7U-08-X-O
2 1
2009 6 6 V0.1
SC31 reserved
for cost down
for cost down
+NB_VCC
3193mA
SC30
SC30
SC41
SC41
SC28
SC28
.1U-X7-04-X
.1U-X7-04-X
2 1
2009 6 6 V0.1
Del RJ9
for not Co-lay RS740
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
.1U-X7-04-X
.1U-X7-04-X
.1U-X7-04-X
.1U-X7-04-X
2 1
2 1
2009 6 6 V0.1
SC29,SC32
change 22U to 10U
for AMD NB Schematic Checklist
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
RS780-POWER
RS780-POWER
RS780-POWER
SC29
SC29
SC32
SC32
10U-X5-08-X
10U-X5-08-X
10U-X5-08-X
10U-X5-08-X
2 1
RS780Q-LM3
RS780Q-LM3
RS780Q-LM3
1
2 1
C185
C185
.1U-04-O
.1U-04-O
EMI
08'1030
11
11
11
+NB_VCC+NB_VCC
SC153
SC153
.1U-04-X-O
.1U-04-X-O
2 1
36Monday, July 06, 2009
36Monday, July 06, 2009
36Monday, July 06, 2009
0.1
0.1
0.1
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