5
4
3
2
1
MEMORY CHANNEL A
D D
TSOP Memory 64/128MB
MEMORY TERMINATIONS A
MA[14..0]
CASA#
RASA#
WEA#
QSA[7..0]
CS0A#MDA[63..0]
MEMORY CHANNEL B (NOT USED)
DQMA[0..7]
CLKA01CKEA
CLKA01#
PRIMARY CRT
LOGIC
Slim VGA
CONN
MEM A MEM B
DAC1
C C
TMDS
STRAPS
DDR/SDR
R G B / HSHYC VSHYC
TMDS_TX[C,2..0]N TMDS_TX[C,2..0]P HPD, DDC2CLK DDC2DATA
INTEGRATED TMDS
LOGIC
DVI-I CONN
DVO
BIOS
B B
POWER
REGULATION
VDDC VDDC_CT MVDDC (MVDDQ)
PVDD TPVDD MPVDD
A2VDD Vref
ROMCS#
ROM
RV350
TVO
DDR DVO
VIP
DAC2
CRT2 Filters
DNI(OPTION)
TVOUT Filters
CRT2
CONN
TVOUT
CONN
AGP/PCI
CBE3..0
GNT#
CLK
SBA[7..0]
AD_STB1#
CPUCLK
TRDY#
INTR
ST2..0
WBF#
AD_STB0
DEVSEL#
DBI_HI
SB_STB
AD_STB0#
RESET#
DBI_LO
SB_STB#
RBF#
REFERENCE
DESIGN
THESE SCHEMATICS ARE
SUBJECT TO MODIFICATION
AND DESIGN IMPROVEMENTS.
PLEASE CONTACT ATI FIELD
APPLICATION ENGINEERING
BEFORE USING THE INFORMATION CONTAINED HEREIN.
3
RESTRICTION
NOTICE
THESE SCHEMATICS CONTAIN
INFORMATION W HICH IS PROPRIETARY
TO AND IS THE PROPERTY OF ATI, AND
MAY NOT BE USED, REPRODUCED OR
DISCLOSED IN ANY MANNER WITHOUT
EXPRESSED WRITTEN PERMISSION
FROM ATI.
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP8X RV350 64/128M TSOP DVI-I/Slim_VGA VO
Size Document Number Rev
B
2
Date: Sheet
81-105-L50XXX
115Tuesday, January 06, 2004
1
of
1.0
AD31..0
IRDY#
FRAME#
+5V_BUS+3.3V_BUS
+12V_BUS
+VDDQ_BUS
A A
5
AGPREF
AD_STB1
AGP B US
1X/2X/4X/8X
4
PAR
REQ#
STOP#
8
LAYOUT NOTE: S OME OF TH E CAPS BELOW MAY BE
REMOVED IF SPACE IS AN ISSUE, ASK BEFORE REMOVING
+12V_BUS
C10
100uF_16V
D D
C C
B B
+5V_BUS +3.3V_BUS
C5
100uF_6.3V
AGP_INTR#3
AGP_RESET#3
AGP_GNT#3
AGP_MB_8X_DET#3
AGP_DBI_HI3
AGP_WBF#3
AGP_SBSTB#3
AGP_ADSTB1#3
AGP_FRAME#3
AGP_TRDY#3
AGP_STOP#3
AGP_PAR3
AGP_ADSTB0#3
C8
100uF_6.3V
7
+VDDQ_BUS
Use 47uF Tant. 16V 20% D si ze (P/ N 4230047600),
800mR Max. ESR and Max. ripple 430mA @ 100kHz
C2
100uF_6.3V
>= 6.3Voror
100uF, Alum. 6.3V 20% 6.3mm dia (P/N 4261010700),
440mR Max. ESR and Max. ripple 230mA @ 100kHz
47uF, Alum. 6.3V 20% 5mm dia (P/N 4262047600),
760mR Max. ESR and Max. ripple 150mA @ 100kHz
Place C2 on left side of AGP connector
AGP_TYPEDET#
AGP_GC_8X_DET#
R1 0R
R5 0R
R12 0R
AGP_VREFGC
6
5
4X/8X AGP BUS
+12V_BUS
+3.3V_BUS
+VDDQ_BUS
AGP_ST1
AGP_SBA1
AGP_SBA3
AGP_SBA5
AGP_SBA7
AGP_AD30
AGP_AD28
AGP_AD26
AGP_AD24
AGP_C/BE#3
AGP_AD22
AGP_AD20 AGP_AD19
AGP_AD18
AGP_AD16
AGP_PAR_R
AGP_AD15
AGP_AD13
AGP_AD11
AGP_AD9
AGP_C/BE#0
AGP_AD6
AGP_AD4
AGP_AD2
AGP_AD0
MAGP1
A1
12V
A2
TYPEDET#
A3
GC_DET#/RESERVED
A4
USB-
A5
GND
A6
INTA#
A7
RST#
A8
GNT#
A9
VCC3.3
A10
ST1
A11
MB_DET#/RESERVED
A12
DBI_HI/PIPE#
A13
GND#A13
A14
WBF#
A15
SBA1
A16
VCC3.3#A16
A17
SBA3
A18
SB_STB#
A19
GND#A19
A20
SBA5
A21
SBA7
A22
RESERVED
A23
GND#A23
A24
RESERVED#A24
A25
VCC3.3#A25
A26
AD30
A27
AD28
A28
VCC3.3#A28
A29
AD26
A30
AD24
A31
GND#A31
A32
AD_STB1#
A33
C/BE3#
A34
VDDQ1.5
A35
AD22
A36
AD20
A37
GND#A37
A38
AD18
A39
AD16
A40
VDDQ1.5#A40
A41
FRAME#
A42
KEY
A43
KEY#A43
A44
KEY#A44
A45
KEY#A45
A46
TRDY#
A47
STOP#
A48
PME#
A49
GND#A49
A50
PAR
A51
AD15
A52
VDDQ1.5#A52
A53
AD13
A54
AD11
A55
GND#A55
A56
AD9
A57
C/BE0#
A58
VDDQ1.5#A58
A59
AD_STB0#
A60
AD6
A61
GND#A61
A62
AD4
A63
AD2
A64
VDDQ1.5#A64
A65
AD0
A66
VREFGC
1.5V_AGP_BUS
OVRCNT#
5.0V#B3
USB+
GND#B5
INTB#
REQ#
VCC3.3#B9
RBF#
GND#B13
DBI_LO/RESERVED
SBA0
VCC3.3#B16
SBA2
SB_STB
GND#B19
SBA4
SBA6
RESERVED#B22
GND#B23
3.3VAUX
VCC3.3#B25
AD31
AD29
VCC3.3#B28
AD27
AD25
GND#B31
AD_STB1
AD23
VDDQ1.5#B34
AD21
AD19
GND#B37
AD17
C/BE2#
VDDQ1.5#B40
IRDY#
KEY#B42
KEY#B43
KEY#B44
KEY#B45
DEVSEL#
VDDQ1.5#B47
PERR#
GND#B49
SERR#
C/BE1#
VDDQ1.5#B52
AD14
AD12
GND#B55
AD10
VDDQ1.5#B58
AD_STB0
GND#B61
VDDQ1.5#B64
VREFCG
+3.3V_BUS
+5V_BUS
+VDDQ_BUS
B1
B2
5.0V
B3
B4
B5
B6
B7
CLK
B8
B9
B10
ST0
B11
ST2
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
AD8
B58
B59
B60
AD7
B61
B62
AD5
B63
AD3
B64
B65
AD1
B66
AGP_ST0
AGP_ST2
AGP_SBA0
AGP_SBA2
AGP_SBA4
AGP_SBA6
AGP_AD31
AGP_AD29
AGP_AD27
AGP_AD25
AGP_AD23
AGP_AD21
AGP_AD17
AGP_C/BE#2
AGP_C/BE#1
AGP_AD14
AGP_AD12
AGP_AD10
AGP_AD8
AGP_AD7
AGP_AD5
AGP_AD3
AGP_AD1
4
AGP_C/BE#[3..0]
AGP_AD[31..0]
AGP_SBA[7..0]
AGP_ST[2..0]
AGP_SBSTB_R
AGP_ADSTB1_R
AGP_ADSTB0_R
AGP_AGPREF
R2 0R
R6 0R
R13 0R
3
AGP_C/BE#[3..0] 3
AGP_AD[31..0] 3
AGP_SBA[7..0] 3
AGP_ST[2..0] 3
AGP_AGPCLK 3
AGP_REQ# 3
AGP_RBF# 3
AGP_DBI_LO 3
AGP_SBSTB 3
AGP_ADSTB1 3
AGP_IRDY# 3
AGP_DEVSEL# 3
AGP_ADSTB0 3
2
GND_TPVSSGND_MPVSS
GND_A2VSSN
C9
100nF
GND_A2VSSQ
GND_AVSSQ GND_RSET
SYMBOL LEGEND
DNI
+3.3V_BUS+5V_BUS
C15
100nF
GND_R2SETGND_AVSSN
#
GND_PVSS GND_TXVSSR
NOTE: THIS IS A DRAWING. THESE
GROUNDS MUST BE MANUALLY
CONNECTED TO THE GROUND PLANE
+12V_BUS
C4
100nF
Caps for EMI - install close to AGP connector
DO NOT
INSTALL
ACTIVE
LOW
DIGITAL
GROUND
ANALOG
GROUND
1
UNIVERSAL VREFGC CIRCUIT (4X, 8X)
May be placed far from connector
AGP_TYPEDET#
AGP_GC_8X_DET#
A A
R19
0R
R60
0R
8
For retail, 1K ohm
pull-down causes AMD
system detects
AGP2X only
+12V, TYPEDET#
short protection
for OEM (1KR)
+12V_BUS
FAN1
1
2
WAFER 2-PIN
AGP_MB_8X_DET#3
7
6
+3.3V_BUS +12V_BUS
R17
47K
5
1
10
9
Q12
32
DNI_BSN20
U7C
SN74ACT86D
R3
DNI_20K
8
R23
1K
4
DNI
+VDDQ_BUS
32
TESTAGP_MB_8X_DET#
1
Q1
2N7002E
R21
147R
R20
324R
R24
100R
3
AGP_VREFGC
C6
10nF
Close to ASIC
AGP_AGPREF
TEST
UNIVERSAL VREFCG CIRCUIT (4X, 8X)
+VDDQ_BUS
32
1
Q5
2N7002E
R67
147R
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
Size Docum e n t N u mb er R ev
C
Date: Sheet
2
DNI
R66
R64
324R
DNI_0R
AGP_AGPREFCG
R65
100RC710nF
Close to ASIC
*
AGP8X RV350 64/128M TSOP DVI-I/Slim_VGA VO
81-105-L50XXX
AGP_AGPREFCG 3
215Tuesday, J anu ary 06, 2004
of
1
1.0
5
4
3
2
1
AGP_AD[31..0]2
D D
AGP_C/BE#[3..0]2
C C
AGP_SBA[7..0]2
AGP_ST[2..0]2
+VDDQ_BUS
R37
47R
B B
C71
15pF
Y1
3
27_MHZ
C72
2 1
15pF
A A
AGP_AGPREFCG2
AGP_MB_8X_DET#2
A_R/C_DAC213
A_G/Y_DAC213
A_B/COMP_DAC213
R32
1M
AGP_AD[31..0]
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_C/BE#[3..0]
AGP_AGPCLK2
AGP_RESET#2
AGP_REQ#2
AGP_GNT#2
AGP_PAR2
AGP_STOP#2
AGP_DEVSEL#2
AGP_TRDY#2
AGP_IRDY#2
AGP_FRAME#2
AGP_INTR#2
TP10
AGP_WBF#2
AGP_RBF#2
AGP_ADSTB02
AGP_ADSTB12
AGP_SBSTB2
AGP_SBA[7..0]
AGP_ST[2..0]
AGP_SBSTB#2
AGP_ADSTB0#2
AGP_ADSTB1#2
AGP_DBI_LO2
AGP_DBI_HI2
GND_R2SET
TP6
H2SYNC13
V2SYNC13
DDC3CLK13
DDC3DATA13
R33
0R
AGP_AD29
AGP_AD30
AGP_AD31
AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3
OPTIONAL SCAN PIN_PERMISSION
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
R40 715R
TESTEN
TP21
R41
R42
0R
0R
+3.3V_BUS
R44
10K
U1A
H29
AD0
Part 1 of 6
H28
AD1
J29
AD2
J28
AD3
K29
AD4
K28
AD5
L29
AD6
L28
AD7
N28
AD8
P29
AD9
P28
AD10
R29
AD11
R28
AD12
T29
AD13
T28
AD14
U29
AD15
N25
AD16
R26
AD17
P25
AD18
R27
AD19
R25
AD20
T25
AD21
T26
AD22
U25
AD23
V27
AD24
W26
AD25
W25
AD26
Y26
AD27
Y25
AD28
AA26
AD29
AA25
AD30
AA27
AD31
N29
C/BE#0
U28
C/BE#1
P26
C/BE#2
U26
C/BE#3
AG30
PCICLK
AG28
RST#
AF28
REQ#
AD26
GNT#
M25
PAR
N26
STOP#
V29
DEVSEL#
V28
TRDY#
W29
IRDY#
W28
FRAME#
AE26
INTA#
AC26
WBF#
AE29
RBF#
M28
AD_STBF_0
V25
AD_STBF_1
AB29
SB_STBF
AD28
SBA0
AD29
SBA1
AC28
SBA2
AC29
SBA3
AA28
SBA4
AA29
SBA5
Y28
SBA6
Y29
SBA7
AF29
ST0
AD27
ST1
AE28
ST2
AB28
SB_STBS
M29
ADSTBS_0
V26
ADSTBS_1
M26
AGPREF
M27
AGPTEST
AB26
DBI_LO
AB25
DBI_HI
AGP_DET#
R2SET
C_R_Pr
Y_G_Y
COMP_B_Pb
H2SYNC
V2SYNC
DDC3CLK
DDC3DATA
VSS
NC#AJ25
XTALIN
XTALOUT
TESTEN
TEST_YCLK
TEST_MCLK
PLLTEST
STEREOSYNC
NC
NC#AH29
RSTB_MSK
RV350
AGP
AC25
AK21
AJ23
AJ22
AK22
AJ24
AK24
AG23
AG24
AK25
AJ25
AH28
AJ29
AH27
E8
B6
AE25
AG26
AH30
AH29
AG29
R30
0R
PCI / AGPAGP2X
4X
8X
DAC2CLK
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
DVOMODE
ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8
ZV_LCDDATA9
DVO / EXT TMDS / GPIOTMDSDAC1
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15
ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23
ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDCNTL2
ZV_LCDCNTL3
VREFG
NC#AK16
NC#AH16
NC#AH17
NC#AJ16
NC#AH18
NC#AJ17
NC#AK19
NC#AH19
NC#AK18
NC#AJ18
NC#AG16
NC#AF16
NC#AG17
NC#AF17
NC#AF18
NC#AE18
NC#AH20
NC#AG20
NC#AF19
NC#AG19
NC#AE12
NC#AG12
TX0M
TX1M
TX2M
TXCM
TXCP
DDC2CLK
DDC2DATA
HPD1
HSYNC
VSYNC
RSET
DDC1DATA
DDC1CLK
AUXWIN
DPLUS
DMINUS
THERM
TX0P
TX1P
TX2P
R
G
B
AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2
AE10
AH6
AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10
AJ10
AK10
AJ11
AH11
AG4
AK16
AH16
AH17
AJ16
AH18
AJ17
AK19
AH19
AK18
AJ18
AG16
AF16
AG17
AF17
AF18
AE18
AH20
AG20
AF19
AG19
AE12
AG12
AJ13
AH14
AJ14
AH15
AJ15
AK15
AH13
AK13
AE13
AE14
AF12
AK27
AJ27
AJ26
AG25
AH25
AH26
AF25
AF24
AF26
AF11
AE11
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
VID/DVO14
VID/DVO15
VID/DVO16
VID/DVO17
VID/DVO18
VID/DVO19
VID/DVO20
+3.3V_BUS
R39 499R
AUXWIN
R43
10K
TP11
TP12
GPIO[13..0]
Mem_Strap1 10
Mem_Strap0 10
+3.3V_BUS
R35
1.00K
Both resistors close to ASIC
R34
C16
1.00K
100nF
GND_RSET
TP13
R63
4.7K
+3.3V_BUS
GPIO7
GPIO10
TP7
GPIO[13..0] 10
DC_Strap3 10,14
DC_Strap4 10
LCDDATA16 10
LCDDATA17 10
PAL/NTSC 10
DEMUX_SEL 10,13
VHAD0 10
TMDS_TX0N 12
TMDS_TX0P 12
TMDS_TX1N 12
TMDS_TX1P 12
TMDS_TX2N 12
TMDS_TX2P 12
TMDS_TXCN 12
TMDS_TXCP 12
DVIDDCCLK 11
DVIDDCDATA 11
HPD 12
A_R_DAC1 11
A_G_DAC1 11
A_B_DAC1 11
A_HSYNC_DAC1 11
A_VSYNC_DAC1 11
DNI
R407
DNI_0R
R410
DNI_0R
R414
DNI_0R
DC_Strap1 10
+3.3V_BUS
R31
10K
GPIO8
GPIO9
GPIO10
ROMCS#4
ROMCS#
U11
D
C
S
HOLD
W
VCC
M25P05-VMN6T
2
Q
4
VSS
5
6
1
+3.3V_BUS
7
3
8
C80
100nF
Drop-in without strap change
Pm25LV512-25SC P/N2280002900
IT IS RECOMMENDED TO ALLOW SERIES RESISTOR
FOOT PRINTS ON THE INDICATED AGP CONTROL SIGNALS
TO ADDRESS ANY LAYOUT NOISE RELATED
SIGNAL DAMPING REQUIREMENTS
5
4
3
2
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP8X RV350 64/128M TSOP DVI-I/S lim_VGA VO
Size Docum e n t N u mb er R ev
Custom
Date: Sheet
81-105-L50XXX
1
315Tuesday, January 06, 2004
of
1.0
1
2
3
4
5
6
7
8
QSA[7..0]8
DQMA#[7..0]8
MAA[14..0]9
MDA[63..0]8
A A
B B
C C
QSA[7..0]
DQMA#[7..0]
MAA[14..0]
MDA[63..0]
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
U1B
L25
DQA0
L26
DQA1
K25
DQA2
K26
DQA3
J26
DQA4
H25
DQA5
H26
DQA6
G26
DQA7
G30
DQA8
D29
DQA9
D28
DQA10
E28
DQA11
E29
DQA12
G29
DQA13
G28
DQA14
F28
DQA15
G25
DQA16
F26
DQA17
E26
DQA18
F25
DQA19
E24
DQA20
F23
DQA21
E23
DQA22
D22
DQA23
B29
DQA24
C29
DQA25
C25
DQA26
C27
DQA27
B28
DQA28
B25
DQA29
C26
DQA30
B26
DQA31
F17
DQA32
E17
DQA33
D16
DQA34
F16
DQA35
E15
DQA36
F14
DQA37
E14
DQA38
F13
DQA39
C17
DQA40
B18
DQA41
B17
DQA42
B15
DQA43
C13
DQA44
B14
DQA45
C14
DQA46
C16
DQA47
A13
DQA48
A12
DQA49
C12
DQA50
B12
DQA51
C10
DQA52
C9
DQA53
B9
DQA54
B10
DQA55
E13
DQA56
E12
DQA57
E10
DQA58
F12
DQA59
F11
DQA60
E9
DQA61
F9
DQA62
F8
DQA63
RV350
Part 2 of 6
MEMORY INTERFACE A
MEMORY CHANNEL A
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
RASA#
CASA#
WEA#
CSA0#
CSA1#
CKEA
CLKA0
CLKA0#
CLKA1
CLKA1#
MVREFD
MVREFS
DIMA_0
DIMA_1
U1C
D7
MAA0
E22
MAA1
B22
MAA2
B23
MAA3
B24
MAA4
C23
MAA5
C22
MAA6
F22
MAA7
F21
MAA8
C21
MAA9
A24
MAA10
C24
MAA11
A25
MAA12
E21
MAA13
B20
MAA14
C19
DQMA#0
J25
DQMA#1
F29
DQMA#2
E25
DQMA#3
A27
DQMA#4
F15
DQMA#5
C15
DQMA#6
C11
DQMA#7
E11
QSA0
J27
QSA1
F30
QSA2
F24
QSA3
B27
QSA4
E16
QSA5
B16
QSA6
B11
QSA7
F10
RASA#
A19
CASA#
E18
WEA#
E19
CSA#0
E20
F20
CKEA
B19
CLKA0
B21
CLKA#0
C20
CLKA1
C18
CLKA#1
A18
B7
B8
D30
B13
RASA# 9
CASA# 9
WEA# 9
CSA#0 9
CKEA 8,9
CLKA0 8 ,9
CLKA#0 8,9
CLKA1 8 ,9
CLKA#1 8,9
100nF
C152
+MVDD
R58
100R
R59
100R
100nF
C351
+MVDD
R56
100R
R57
100R
DQB0
F7
DQB1
E7
DQB2
G6
DQB3
G5
DQB4
F5
DQB5
E5
DQB6
C4
DQB7
B5
DQB8
C5
DQB9
A4
DQB10
B4
DQB11
C2
DQB12
D3
DQB13
D1
DQB14
D2
DQB15
G4
DQB16
H6
DQB17
H5
DQB18
J6
DQB19
K5
DQB20
K4
DQB21
L6
DQB22
L5
DQB23
G2
DQB24
F3
DQB25
H2
DQB26
E2
DQB27
F2
DQB28
J3
DQB29
F1
DQB30
H3
DQB31
U6
DQB32
U5
DQB33
U3
DQB34
V6
DQB35
W5
DQB36
W4
DQB37
Y6
DQB38
Y5
DQB39
U2
DQB40
V2
DQB41
V1
DQB42
V3
DQB43
W3
DQB44
Y2
DQB45
Y3
DQB46
AA2
DQB47
AA6
DQB48
AA5
DQB49
AB6
DQB50
AB5
DQB51
AD6
DQB52
AD5
DQB53
AE5
DQB54
AE4
DQB55
AB2
DQB56
AB3
DQB57
AC2
DQB58
AC3
DQB59
AD3
DQB60
AE1
DQB61
AE2
DQB62
AE3
DQB63
RV350
Part 3 of 6
MEMORY INTERFACE B
MEMVMODE_0
MEMVMODE_1
MEMORY CHANNEL B
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
RASB#
CASB#
WEB#
CSB0#
CSB1#
CKEB
CLKB0
CLKB0#
CLKB1
CLKB1#
DIMB_0
DIMB_1
ROMCS#
MEMTEST
N5
M1
M3
L3
L2
M2
M5
P6
N3
K2
K3
J2
P5
P3
P2
E6
B2
J5
G3
W6
W2
AC6
AD2
F6
B3
K6
G1
V5
W1
AC5
AD1
R2
T5
T6
R5
R6
R3
N1
N2
T2
T3
E3
AA3
AF5
C6
C7
C8
R53
4.7K
R55
47R
LAYOUT NOTE : SOME OF THE RESISTORS R51-54 MAY BE
REMOVED IF SPACE I S AN ISSUE, ASK BEF ORE REMOVING
R51 4.7K
R52
R54
DNI_4.7K
ROMCS# 3
DNI_4.7K
+VDDC_CT
PLACE C351/152 VERY CLOSE TO ASIC
R56/57/58/59 CLOSE TO ASIC AS WELL
FOR 2.5V VDDR1
MEMVMODE_0 = VDDC
MEMVMODE_1 = GND
FOR 1.8V VDDR1
MEMVMODE_0 = GND
MEMVMODE_1 = VDDC
(SEE DESIGN GUIDE)
D D
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, On ta ri o
Canada, L3T 7X6
(905) 882-2600
Title
AGP8X RV350 64/128M TSOP DVI-I/Slim_VGA VO
Size Document Number Re v
Custom
1
2
3
4
5
6
Date: Sheet
7
81-105-L50XXX
1.0
of
415Tuesday, January 06, 2004
8
5
+MVDD
D D
C C
+A2VDD
+AVDD
+MPVDD
C73
2.2uF
C67
4.7uF
C52
4.7uF
R10
0R
+VDDOI_PINS
C68
2.2uF
C51
100nF
+MVDD
+TPVDD
C81
100pF
C63
4.7uF
C43
2.2uF
C64
100nF
C58
2.2uF
GND_AVSSN
GND_MPVSS
C50
10uf_6.3V
GND_TPVSS
+TXVDDR_PINS
C60
100nF
GND_TXVSSR
+A2VDD
B B
C804
10uF_6.3V
GND_A2VSSN
+PVDD
GND_PVSS
C62
2.2uF
GND_A2VSSQ
C53
100nF
+A2VDDQ
C65
100nF
AG21
AH21
AH24
AE17
AE20
AE15
AF21
AJ20
AK12
AF13
AF14
AF22
AE24
AE22
AK28
T7
R4
R1
N8
N7
M4
L27
L8
J24
J23
J8
J7
J4
J1
H10
H13
H15
H17
T8
V4
V7
V8
AA1
AA4
AA7
AA8
A3
A9
A15
A21
A28
B1
B30
D26
D23
D20
D17
D14
D11
D8
D5
E27
F4
G7
G10
G13
G15
G19
G22
G27
H22
H19
AD4
T4
N4
D19
D13
F18
N6
A7
U1D
VDDR1#T7
VDDR1#R4
VDDR1#R1
VDDR1#N8
VDDR1#N7
VDDR1#M4
VDDR1#L27
VDDR1#L8
VDDR1#J24
VDDR1#J23
VDDR1#J8
VDDR1#J7
VDDR1#J4
VDDR1#J1
VDDR1#H10
VDDR1#H13
VDDR1#H15
VDDR1#H17
VDDR1#T8
VDDR1#V4
VDDR1#V7
VDDR1#V8
VDDR1#AA1
VDDR1#AA4
VDDR1#AA7
VDDR1#AA8
VDDR1#A3
VDDR1
VDDR1#A15
VDDR1#A21
VDDR1#A28
VDDR1#B1
VDDR1#B30
VDDR1#D26
VDDR1#D23
VDDR1#D20
VDDR1#D17
VDDR1#D14
VDDR1#D11
VDDR1#D8
VDDR1#D5
VDDR1#E27
VDDR1#F4
VDDR1#G7
VDDR1#G10
VDDR1#G13
VDDR1#G15
VDDR1#G19
VDDR1#G22
VDDR1#G27
VDDR1#H22
VDDR1#H19
VDDR1#AD4
VDDR1#T4
VDDR1#N4
VDDR1#D19
VDDR1#D13
A2VDD
VDDL1
VDDL0#AE15
VDDL0#AF21
VDDL0
TPVDD
TXVDDR
TXVDDR#AF14
VDDRH0
VDDRH1
A2VDD#AG21
A2VDD#AH21
A2VDDQ
AVDD
VDD1DI
VDD2DI
PVDD
MPVDD
RV350
Part 4 of 6
VDDC15#AC11
VDDC15#AC20
VDDC15#Y23
VDDC15#L23
VDDC15#H20
VDDC15#H11
VDDR3#AD19
VDDR3#AD21
VDDR3#AD22
VDDR3#AC22
VDDR3#AC21
VDDR3#AC19
VDDR4#AC10
VDDR4#AD10
I/O POWER
TXVSSR#AH12
TXVSSR#AG13
A2VSSN#AJ21
VDDC
VDDC#AD13
VDDC#AD15
VDDC#AC15
VDDC#AC17
VDDC15
VDDC15#Y8
VDDR3
VDDR3#AC8
VDDR4#AG7
VDDR4#AD9
VDDR4
VDDP#J30
VDDP#AF27
VDDP#AE30
VDDP#AC27
VDDP#AC23
VDDP#AB30
VDDP#AA24
VDDP#AA23
VDDP#Y27
VDDP#W30
VDDP#V23
VDDP#V24
VDDP#M23
VDDP#M24
VDDP
VDDP#P23
VDDP#P27
VDDP#T23
VDDP#T24
VDDP#T30
VDDP#U27
AVSSQ
VSS#AF20
VSS#AE19
VSS#AE16
VSS#AF15
TPVSS
TXVSSR
VSSRH0
VSSRH1
A2VSSN
A2VSSQ
AVSSN
VSS1DI
VSS2DI
PVSS
MPVSS
4
AC13
AD13
AD15
+VDDC
AC15
AC17
P8
Y8
AC11
AC20
Y23
L23
+VDDC_CT
H20
H11
AD7
AD19
AD21
AD22
AC22
AC21
+3.3V_BUS
AC19
AC8
AG7
AD9
AC9
AC10
AD10
J30
AF27
AE30
AC27
AC23
AB30
AA24
AA23
Y27
W30
V23
V24
M23
M24
N30
P23
P27
T23
T24
T30
U27
AD24
AF20
AE19
AE16
AF15
AJ19
VSS
AJ12
AH12
AG13
AG14
F19
M6
AH22
AJ21
AF23
AH23
AE23
AE21
AJ28
A6
+3.3V_BUS
+VDDQ_BUS
GND_AVSSQ
GND_TPVSS
GND_TXVSSR
GND_A2VSSN
GND_A2VSSQ
GND_AVSSN
GND_PVSS
GND_MPVSS
C69
100nF
TP9
+VDDQ_BUS
3
DIODE SUPPLIES POWER TO
5 4
2 1
5 4
5 4
CP5D
10nF
D30
DNI_2.4V
CP8D
10nF
CP4D
10nF
C48
100nF
VDDC RAIL WHILE VDDC
REGULATOR STABALIZES
DURING POWER ON
+VDDC
+3.3V_BUS
2 1
C47
100nF
+3.3V_BUS
DNI
+VDDC +VDDC
C44
100nF
CP2D
CP8A
CP8B
CP2C
10nF
5 4
CP3D
10nF
5 4
CP6D
10nF
5 4
10uf_6.3V
10nF
8 1
CP4A
10nF
8 1
CP9B
CP9C
10nF
10nF
7 2
6 3
CP5A
10nF
8 1
C39
C38
10uf_6.3V
10nF
6 3
CP3C
10nF
6 3
CP9A
10nF
8 1
CP6C
10nF
6 3
+MVDD
C35
100nF
CP8C
10nF
10nF
7 2
6 3
CP4C
CP4B
10nF
10nF
6 3
7 2
+VDDC_CT
C49
100nF
CP9D
10nF
5 4
CP5B
CP5C
10nF
10nF
7 2
6 3
+VDDC
+MVDD
+MVDD
8 1
8 1
8 1
CP2A
10nF
CP3A
10nF
C46
100nF
C36
100nF
CP6A
10nF
C32
100nF
CP2B
10nF
7 2
CP3B
10nF
7 2
+3.3V_BUS
C37
100nF
CP6B
10nF
7 2
C33
100nF
C24
10uf_6.3V
C26
100nF
D31
DNI_2.4V
C45
100nF
DNI
C27
100nF
2
+VDDC
U1F
P17
VDDC
Part 6 of 6
P18
VDDC#P18
P19
VDDC#P19
U12
VDDC#U12
U13
VDDC#U13
U14
VDDC#U14
U17
VDDC#U17
U18
VDDC#U18
U19
VDDC#U19
V19
VDDC#V19
V18
VDDC#V18
CENTER
V17
VDDC#V17
V14
VDDC#V14
ARRAY
V13
VDDC#V13
V12
VDDC#V12
N18
VDDC#N18
N17
VDDC#N17
N14
VDDC#N14
W17
VDDC#W17
W18
VDDC#W18
W12
VDDC#W12
W13
VDDC#W13
W14
VDDC#W14
N13
VDDC#N13
N19
VDDC#N19
M19
VDDC#M19
M18
VDDC#M18
M12
VDDC#M12
N12
C28
100nF
C29
100nF
C30
100nF
ADD ASIC DECOUPLING FOR ALL POWER AS REQUIRED
WITH AS MANY AS POSSIBLE PLACED UNDER THE ASIC
VDDC#N12
M13
VDDC#M13
M14
VDDC#M14
P12
VDDC#P12
P13
VDDC#P13
P14
VDDC#P14
M17
VDDC#M17
W19
VDDC#W19
RV350
U1E
A2
VSS
VSS#A10
VSS#A16
VSS#A22
VSS#A29
VSS#C1
VSS#C3
VSS#C28
VSS#C30
VSS#D27
VSS#D24
VSS#D21
VSS#D18
VSS#D15
VSS#D12
VSS#D9
VSS#D6
VSS#D4
VSS#F27
VSS#G9
VSS#G12
VSS#G16
VSS#G18
VSS#G21
VSS#G24
VSS#H27
VSS#H23
VSS#H21
VSS#H18
VSS#H16
VSS#H14
VSS#H12
VSS#H9
VSS#H8
VSS#H4
VSS#K30
VSS#K27
VSS#K24
VSS#K23
VSS#AG15
VSS#AD12
VSS#AE27
VSS#AG5
VSS#AG9
VSS#AG11
VSS#AG18
VSS#AG22
VSS#AG27
VSS#E4
VSS#AB4
RV350
Part 5 of 6
CORE GND
AG15
AD12
AE27
AG11
AG18
AG22
AG27
A10
A16
A22
A29
C1
C3
C28
C30
D27
D24
D21
D18
D15
D12
D9
D6
D4
F27
G9
G12
G16
G18
G21
G24
H27
H23
H21
H18
H16
H14
H12
H9
H8
H4
K30
K27
K24
K23
AG5
AG9
E4
AB4
PLACED CLOSE TO THE POWER/GND PINS
VSS#D21
VSS#D18
VSS#D15
VSS#D12
VSS#D9
VSS#D6
VSS#D4
VSS#F27
VSS#H21
VSS#H18
VSS#H16
VSS#H14
VSS#H12
VSS#H9
VSS#H8
VSS#H4
VSS#K7
VSS#AE16
VSS#AF15
VSS#AF20
VSS#AE19
VSS#M7
VSS#N23
VDDC1
VDDC1#M15
VDDC1#R19
VDDC1#T12
VSS#K8
VSS#K7
VSS#AE16
VSS#AF15
VSS#AF20
VSS#AE19
VSS#M7
VSS#N23
VSS#N24
VSS#N27
VSS#P4
VSS#R7
VSS#R8
VSS#R23
VSS#R24
VSS#R30
VSS#T27
VSS#T1
VSS#U4
VSS#U8
VSS#U23
VSS#V30
VSS#W7
VSS#W8
VSS#W23
VSS#W24
VSS#W27
VSS#Y4
VSS#AA30
VSS#AB27
VSS#AB24
VSS#AB23
VSS#AB8
VSS#AB7
VSS#AB1
VSS#AC4
VSS#AC12
VSS#AC14
VSS#AD16
VSS#AC16
VSS#AC18
VSS#AD30
VSS#AD25
VSS#AD18
VSS#AK2
VSS#AK29
VSS#AJ30
VSS#AJ1
VSS#D10
VSS#D25
1
M16
VSS
N16
N15
P15
P16
R18
R17
R16
R15
R14
R13
R12
T13
T14
T15
W15
V16
V15
U15
U16
T19
T18
T17
T16
W16
M15
R19
T12
K8
K7
K1
L4
M30
M8
M7
N23
N24
N27
P4
R7
R8
R23
R24
R30
T27
T1
U4
U8
U23
V30
W7
W8
W23
W24
W27
Y4
AA30
AB27
AB24
AB23
AB8
AB7
AB1
AC4
AC12
AC14
AD16
AC16
AC18
AD30
AD25
AD18
AK2
AK29
AJ30
AJ1
D10
D25
A A
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP8X RV350 64/128M TSOP DVI-I/S lim_VGA VO
Size Docum e n t N u mb er R ev
C
5
4
3
2
Date: Sheet
81-105-L50XXX
1
515Tuesday, J anu ary 06, 2004
1.0
of
8
7
6
5
4
3
2
1
Regulator for VDDC (ASIC Core)
Vin = 5.0V AGP
Vout = 1.2V
Iout = Unknown (7A MAX at 350MHz) (load consumption)
Iout = 3A MAX (Po wer rail consumption)
D D
+5V_BUS
C C
R7
2.2_0805
C151
2.2uF
R8
C153
12K
R1022
DNI
C863
DNI
C862
DNI
*
U816
7
OCSET
APW7057/RT9202
FB6PHASE
470pF
B B
+12V_BUS
R4
0_0805
5
VCC
1
BOOT
2
UGATE
8
4
LGATE
GND
3
**
C240
0.1uF
D129
DNI_1N4148
C154
DNI_0.1uF
UPPER_GATE
LOWER_GATE
R351
0_0805
R1018
0_0805
Q29A
APM7318
2
+PW_VDDC_M
Q29B
APM7318
4
VDDC_FB
71
8
53
6
** **
L21 3.3uH
D130
1A
1 2
+PW_VDDC
C102
100nF
***
C301
470uF_10V
C310
0.1uF
R254
0
B321
60R
680uF 4V as alternate
>= 6.3V if 3. 3V_BU S is used
>= 10V if 5V_B US i s used
R1
R353
1.00K
1%
R2
R356
2K
1%
***
0.8V Ref
C305
470uF_10V
******
C307
470uF_10V
**
**
C308
22uF_10V
+VDDC
**
*****
C309
22uF_10V
***
Indicate number of via required for the
connection
Part Vou t R1 R2
APW7057
RT9202
0.8V Ref
1.2V
1.3V
1.62V
1.00K 1%
ATI P/N 3240100100 ATI P/N 3240110100
1.00K 1%
ATI P/N 3240100100
1.00K 1%
ATI P/N 3240100100
ATI P/N 3240100100 ATI P/N 3240475300
3.3V
TSOP Memory
3.45V
TSOP Memory
1.00K 1%
ATI P/N 3240100100
1.00K 1%
ATI P/N 3240100100
2.00K 1%
1.6K 1%
ATI P/N
976R 1%
ATI P/N 3240976000
475R 1%1.00K 1%2.5V
324R 1%
ATI P/N 3240332000
301 1%
ATI P/N 3240301000
A A
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP8X RV350 64/128M TSOP DVI-I/S lim_VGA VO
Size Docum e n t N u mb er R ev
C
8
7
6
5
4
3
Date: Sheet
2
81-105-L50XXX
615Tuesday, J anu ary 06, 2004
1
1.0
of
8
Rx3 / Rx9 Rx4 / Rx10
+MVDD
2.5V
2.6V
REF2
1.5V
D D
[-0.02V/+0.02V]
+TPVDD / +VDDR
Rx1 Rx2
1.800V
1.847V
1.855V
+3.3V_BUS
R800
22R
C C
C810
4.7uF
+VDDR
B B
C17
100nF
B28
DNI_200R
B27
200R
U810
431L
3 2
+TPVDD
+AVDD
1
R107
0R
C241
4.7uF_6.3V
Place caps very
close to power pin
1.24V REF
AVDD/A 2V D DQ (1 st & 2 nd D AC Band Gap) - 200mA
8
+A2VDDQ
+VDDOI_PINS
+TXVDDR_PINS
C59
4.7uF
GND_TXVSSR
+MPVDD
+PVDD
C803
10uF_6.3V
GND_PVSS
NO ALT
B29
200R
B12
200R
B11
200R
B31
200R
A A
B30
200R
7
Infineon,16Mx16, 200MHZ,
Samsung,8Mx16, 250MHZ,
Memory
Samsung, 16Mx16, 200MHZ
C11
4.7uF
C242
R14
0.01uF
10K
7
C130
DNI_100uF_16V
+12V_BUS
C14
100nF
411
3
+
2
-
R802
DNI_3.48K
5
+
6
-
R11
4.75K_1%
12
+
13
-
R804
2.21K_1%
10
+
9
-
R806
2.21K_1%
C132
DNI_100nF
X7R
U811A
1
LM324M
R801 DNI_4. 75K
Rx4Rx3
U811B
7
LM324M
R9
1K_1%
U811D
14
LM324M
R803 1K_1%
Rx6Rx5
U811C
8
LM324M
R805 1K_1%
Rx8Rx7
6
Regulator for :
+MVDD/+A2VDD
+VDDC_CT
+PVDD/+MPVDD
+VDDR4
+5V_BUS
R105
0R
R104
0R
R106
0R
4
Q813
Q25
DNI_MTD3055V
32
60V 12A DPAK-4PIN
1
R15
DNI_0
+3.3V_BUS
1
+3.3V_BUS
1
+3.3V_BUS
1
4
3 2
BCP68
25V 1A SOT-223
Q812
CMPT3904
2 3
60V 200mA SOT-23
4
3 2
Q811
BCP68
25V 1A SOT-223
6
+MVDDC
DNI_100nF
C131
+VDDC_CT
+TPVDD
+VDDR
Vout = 3.3V
DNI
***
C333
DNI_470uF_6.3V
***
Vout = 1.5V
C844
22uF_6.3V
Vout = 1.80V
C802
10uF_6.3V
Vout = 1.80V
C801
10uF_6.3V
>= 6.3V
100uF_6.3V
C806
5
Regulator for +MVDD
Vin = +3.3V AGP
Vout = 2.5V
C134
100nF
X7R
+12V_BUS
3 2
4
+3.3V_BUS +MVDD
4
32
60V 12A DPAK-4PIN
1
R810
470
U813
431L
1
Q26
MTD3055V
Rx10
Rx9
R812
4.75K_1%
R811
4.64K_1%
Vout = 2.5V
C135
100nF
3
***
C334
470uF_10V
***
>= 6.3V
2
Rt3 Rt4
Rp1
432R1.61V
+0.01V/-0.01V
1.69V
+0.01V/-0.01V
1.718V
+0.01V/-0.01V
1.8175V
+0.01V/-0.01V
Regulator for +PVDD (30mA)
Vin = +3.3V AGP
Vout = 1.8V
SC431LCSK-1
3240432000
432R 3240432000 1.21K 3240121100
+3.3V_BUS
+PVDD
R284
DNI_33R
R287
REG25
DNI_431L
3 2
DNI_681R
1%
1
R290
DNI_1.5K
1%
GND_PVSS
Rp1
Rp2
Rp2
1.5K
/Rt2//Rt1/
3230015200
32300152001.5K562R 3240562000
32300152001.5K681R 3240681000
1
DNI
Regulator for +A2VDD (150mA)
Vin = +3.3V AGP
Vout = 2.5V
+5V_BUS
R397
220
REG24
431L
R399
4.64K_1%
3 2
+A2VDD and GND_A2VSSN routed with at least 15 mil
trace and not longer than 1.5 inch.
C805
0.01uF
5
DNI when use 2.5v Mem
1
4
R398
4.75K_1%
Q30
2N2222
C861
0.1uF
*
GND_A2VSSN
+A2VDD
3
Regulator for +MPVDD (10mA)
Vin = +3.3V AGP
Vout = 1.8V
+3.3V_BUS+3.3V_BUS
+MPVDD
R285
DNI_75R
Rt3
REG26
DNI_431L
SC431LCSK-1
3 2
Title
Size Docum e n t N u mb er R ev
C
Date: Sheet
2
R288
DNI_681R
1%
1
R291
DNI_1.5K
1%
Rt4
GND_MPVSS
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
AGP8X RV350 64/128M TSOP DVI-I/Slim_VGA VO
81-105-L50XXX
DNI
1.0
of
715Wednesday, February 11, 2004
1
5
TERMINATION FOR
MEMORY
CHANNEL A
D D
C C
4
MDA[63..0]
MDA[63..0]4
QSA[7..0]
QSA[7..0]4
MDA0
RP117D 47R
MDA1
RP117C 47R
MDA2
RP117B 47R
MDA3
RP117A 47R
MDA4
RP118D 47R
MDA5
RP118C 47R
MDA6
RP118B 47R
MDA7
RP118A 47R
MDA8
RP119B 47R
MDA9
RP120D 47R
MDA10
RP120C 47R
MDA11
RP120A 47R
MDA12
RP120B 47R
MDA13
RP119C 47R
MDA14
RP119D 47R
MDA15
RP119A 47R
MDA16
RP121D 47R
MDA17
RP121C 47R
MDA18
RP121B 47R
MDA19
RP121A 47R
MDA20
RP122D 47R
MDA21
RP122C 47R
MDA22
RP122B 47R
MDA23
RP122A 47R
MDA24
RP123B 47R
MDA25
RP123A 47R
MDA26
RP124B 47R
MDA27
RP123D 47R
MDA28
RP123C 47R
MDA29
RP124A 47R
MDA30
RP124D 47R
MDA31
RP124C 47R
MDA32
RP127B 47R
MDA33
RP127C 47R
MDA34
RP127D 47R
MDA35
RP127A 47R
MDA36
RP128A 47R
MDA37
RP128B 47R
MDA38
RP128C 47R
MDA39
RP128D 47R
MDA40
RP125C 47R
MDA41
RP125D 47R
MDA42
RP125B 47R
MDA43
RP126D 47R
MDA44
RP126A 47R
MDA45
RP126B 47R
MDA46
RP126C 47R
MDA47
RP125A 47R
MDA48
RP129A 47R
MDA49
RP129D 47R
MDA50
RP129B 47R
MDA51
RP129C 47R
MDA52
RP130A 47R
MDA53
RP130C 47R
MDA54
RP130D 47R
MDA55
RP130B 47R
MDA56
RP131A 47R
MDA57
RP131C 47R
MDA58
RP132D 47R
MDA59
RP131B 47R
MDA60
RP131D 47R
MDA61
RP132B 47R
MDA62
RP132C 47R
MDA63 M_MDA63
RP132A 47R
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
3
5 4
6 3
7 2
8 1
5 4
6 3
7 2
8 1
72
5 4
6 3
8 1
7 2
63
54
81
5 4
6 3
7 2
8 1
5 4
6 3
7 2
8 1
7 2
8 1
72
5 4
6 3
81
54
63
7 2
6 3
5 4
8 1
81
72
63
54
63
54
72
54
81
72
63
81
8 1
5 4
7 2
6 3
8 1
6 3
5 4
7 2
81
63
5 4
72
54
7 2
6 3
8 1
R759 47R
R760 47R
R761 47R
R762 47R
R763 47R
R764 47R
R765 47R
R766 47R
M_MDA0
M_MDA1
M_MDA2
M_MDA3
M_MDA4
M_MDA5
M_MDA6
M_MDA7
M_MDA8
M_MDA9
M_MDA10
M_MDA11
M_MDA12
M_MDA13
M_MDA14
M_MDA15
M_MDA16
M_MDA17
M_MDA18
M_MDA19
M_MDA20
M_MDA21
M_MDA22
M_MDA23
M_MDA24
M_MDA25
M_MDA26
M_MDA27
M_MDA28
M_MDA29
M_MDA30
M_MDA31
M_MDA32
M_MDA33
M_MDA34
M_MDA35
M_MDA36
M_MDA37
M_MDA38
M_MDA39
M_MDA40
M_MDA41
M_MDA42
M_MDA43
M_MDA44
M_MDA45
M_MDA46
M_MDA47
M_MDA48
M_MDA49
M_MDA50
M_MDA51
M_MDA52
M_MDA53
M_MDA54
M_MDA55
M_MDA56
M_MDA57
M_MDA58
M_MDA59
M_MDA60
M_MDA61
M_MDA62
M_MDA[63..0]
SERIES Resistors
For Bi-Directional signals,
Series resistors should be
placed close to the memory
M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7
M_QSA[7..0]
M_MDA[63..0] 9
M_QSA[7..0] 9
2
1
CLOCK
terminations
Change from 1:1 spacing to at least a
2.5:1 spacing between the pair
These resis to r s and caps m ust be placed to minimize any stubs. These
must also be placed after the memory
M_CLKA0
R797
56R
C778
10nF_0805
R798
M_CLKA#0
M_CLKA1
M_CLKA#1
M_CLKA04,9
M_CLKA#04,9
M_CLKA14,9
M_CLKA#14,9
M_CLKA0
M_CLKA#0
M_CLKA1
M_CLKA#1
56R
R799
56R
R796
56R
CLKA0 4,9
CLKA#0 4,9
CLKA1 4,9
CLKA#1 4,9
C779
10nF_0805
M_DQMA#[7..0]9
B B
A A
5
4
M_DQMA#[7..0]
M_DQMA#0
R775 47R
M_DQMA#1
R776 47R
M_DQMA#2
R777 47R
R778 47R
M_DQMA#4
R780 47R
M_DQMA#5
R779 47R
M_DQMA#6
R781 47R
M_DQMA#7
R782 47R
M_MAA[14..0]4,9
M_RASA#4,9
M_CASA#4,9
M_WEA#4,9
M_CSA#04,9
M_CKEA4,9
M_MAA[14..0]
M_MAA0 MAA0
M_MAA1 MAA1
M_MAA5 MAA5
M_MAA6 MAA6
M_MAA7 MAA7
M_MAA11 MAA11
R893
10K
DQMA#0
DQMA#1
DQMA#2
DQMA#3M_DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
MAA2M_MAA2
MAA3M_MAA3
MAA4M_MAA4
MAA8M_MAA8
MAA9M_MAA9
MAA10M_MAA10
MAA12M_MAA12
MAA13M_MAA13
MAA14M_MAA14
RASA# 4,9
CASA# 4,9
WEA# 4,9
CSA#0 4,9
CKEA 4,9
3
DQMA#[7..0]
MAA[14..0]
DQMA#[7..0] 4
MAA[14..0] 4,9
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
(905) 882-2600
Title
AGP8X RV350 64/128M TSOP DVI-I/Slim_VGA VO
Size Document Number Rev
Custom
2
Date: Sheet
81-105-L50XXX
1
1.0
of
815Tuesday, January 06, 2004
8
7
6
5
4
3
2
1
+VREF_U29
M_DQMA#[7..0]8
D D
M_QSA[7..0]8
C C
M_MAA[14..0]4
B B
M_DQMA#[7..0]
M_QSA[7..0]
M_CLKA#04,8
M_CLKA#14,8
M_CLKA04,8
M_CLKA14,8
M_CKEA4,8
M_WEA#4
M_CASA#4
M_RASA#4
M_CSA#04
M_MAA[14..0]
M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#7
M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7
M_CLKA0#
M_CLKA1#
M_CLKA0
M_CLKA1
M_CKEA
M_WEA#
M_CASA#0
M_RASA#0
M_CSA#0
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13
M_MAA14
M_CLKA0
M_CLKA#0
M_CKEA
+MVDD +MVDD
C566
100nF
M_CLKA0
M_CLKA0#
M_CKEA
M_MDA[63..0]8
Channel A Bottom Down
U29
C418
49
100nF
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_QSA2
M_QSA0
M_DQMA#2
M_DQMA#0
M_MAA12
M_MAA13
+VREF_U33
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_QSA1
M_QSA3
M_DQMA#1
M_DQMA#3
M_MAA12
M_MAA13
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
1MX16X4
U33
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
1MX16X4
Channel A Top Down
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ
VSSQ#58
VSSQ#64
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ
VSSQ#58
VSSQ#64
M_MDA23
2
DQ0
M_MDA22
4
DQ1
M_MDA21
5
DQ2
M_MDA20
7
DQ3
M_MDA19
8
DQ4
M_MDA18
10
DQ5
M_MDA17
11
DQ6
M_MDA16
13
DQ7
M_MDA7
54
DQ8
M_MDA6
56
DQ9
M_MDA5
57
M_MDA4
59
M_MDA3M_DQMA#6
60
M_MDA2
62
M_MDA1
63
M_MDA0
65
14
NC
17
19
25
M_MAA14
42
43
50
+MVDDC +MVDDC
53
1
VDD
18
+MVDD
33
3
9
15
55
61
34
VSS
48
66
6
12
52
58
64
M_MDA14
2
DQ0
M_MDA13
4
DQ1
M_MDA8
5
DQ2
M_MDA15
7
DQ3
M_MDA11
8
DQ4
M_MDA12
10
DQ5
M_MDA10
11
DQ6
M_MDA9
13
DQ7
M_MDA25
54
DQ8
M_MDA24
56
DQ9
M_MDA28
57
M_MDA27
59
M_MDA30
60
M_MDA31
62
M_MDA26
63
M_MDA29
65
14
NC
17
19
25
M_MAA14
42
43
50
+MVDDC
53
1
VDD
18
+MVDD
33
3
9
15
55
61
34
VSS
48
66
6
12
52
58
64
+VREF_U30
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_CLKA1
M_CLKA1#
M_CKEA
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_QSA7
M_QSA4
M_DQMA#7
M_DQMA#4
M_MAA12
M_MAA13
C569
100nF
+VREF_U34
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_CLKA1
M_CLKA1#
M_CKEA
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_QSA5
M_QSA6
M_DQMA#5
M_DQMA#6
M_MAA12
M_MAA13
Put 1 100nF cap per power pin of memory
+MVDD
C381
100nF
C239
100nF
C237
100nF
C238
100nF
Place as many as possible.
C572
100nF
C592
100nF
C573
100nF
C593
100nF
C574
100nF
C594
100nF
+MVDD
+MVDD
C221
100nF
C222
100nF
C577
100nF
C597
100nF
C578
100nF
C598
100nF
C579
100nF
C599
100nF
+MVDD
+MVDD
C223
100nF
C224
100nF
Channel A Bottom Up
U30
C420
49
VREF
100nF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
1MX16X4
U34
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
1MX16X4
Channel A Top Up
M_MDA63
2
DQ0
M_MDA61
4
DQ1
M_MDA62
5
DQ2
M_MDA58
7
DQ3
M_MDA60
8
DQ4
M_MDA57
10
DQ5
M_MDA59
11
DQ6
M_MDA56
13
DQ7
M_MDA39
54
DQ8
M_MDA38
56
DQ9
M_MDA37
57
DQ10
M_MDA36
59
DQ11
M_MDA35
60
DQ12
M_MDA32
62
DQ13
M_MDA33
63
DQ14
M_MDA34
65
DQ15
14
NC
17
NC#17
19
NC#19
25
NC#25
M_MAA14
42
NC#42
43
NC#43
50
NC#50
53
NC#53
1
VDD
18
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ
VSSQ#58
VSSQ#64
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ
VSSQ#58
VSSQ#64
+MVDDC +MVDD
+MVDD
33
3
9
15
55
61
34
48
66
6
12
52
58
64
M_MDA41
2
M_MDA40
4
M_MDA42
5
M_MDA47
7
M_MDA43
8
M_MDA46
10
M_MDA45
11
M_MDA44
13
M_MDA48
54
M_MDA50
56
M_MDA51
57
M_MDA49
59
M_MDA52
60
M_MDA55
62
M_MDA53
63
M_MDA54
65
14
17
19
25
M_MAA14
42
43
50
+MVDDC
53
1
18
+MVDD
33
3
9
15
55
61
34
48
66
6
12
52
58
64
B327
60R
DDR SDRAM 64MB 8Mx16bit x 4pcs
DDR SDRAM 128MB 16Mx16bit x 4pcs
+MVDD+MVDD
R360
5.1K
+VREF_U29
R361
5.1K
+MVDD
R378
5.1K
+VREF_U33
R369
5.1K
Note: These indications of the location of
the memory for the solder side (bottom)
are looking thru from the component side.
DATA GROUP SHOULD BE ASSIGNED TO EACH DQS AND DQM ACCORDINGLY
AND THIS MAPPING IS JUST FOR PLACEMENT AND ROUTING REASONS
+MVDD
R367
5.1K
+VREF_U30
R363
5.1K
R370
5.1K
+VREF_U34
R371
5.1K
A A
U29 U30 U34U33
+MVDDC
C595
100nF
C596
100nF
C229
100nF
+MVDDC +MVDDC +MVDDC
C600
100nF
C601
100nF
C235
100nF
C575
100nF
C232
100nF
C576
100nF
C231
100nF
C580
100nF
C581
100nF
Place as many as possible.
8
7
6
5
4
3
All +VDD_MEM_IO and +VDD decoupling caps should be equally distributed
per memory chip. As close to the pin as possible.
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
(905) 882-2600
Title
AGP8X RV350 64/128M TSOP DVI-I/Slim_VGA VO
Size Document Number Rev
Custom
Date: Sheet
2
81-105-L50XXX
1.0
of
915Tuesday, January 06, 2004
1
8
7
6
5
4
3
2
1
OPTION STRAPS
GPIO[13..0]
GPIO[13..0]3
STRAP
D D
C C
GPIO0
GPIO1
GPIO2
GPIO3
GPIO11
GPIO12
GPIO13
GPIO9
GPIO8
GPIO4
GPIO5
GPIO6
G
STRAP
H
STRAP
J
STRAP
K
STRAP L
STRAP M
STRAP N
STRAP O
STRAP A
STRAP D
STRAP E
STRAP F
R201 10K
R202 DNI_10K
R203 10K
R204 DNI_10K
R205 DNI_10K
R206 10K
R207 DNI_10K
R208 10K
R209 DNI_10K
R210 10K
R211 DNI_10K
R212 10K
R213 10K
R214 DNI_10K
R215 10K
R216 DNI_10K
R217 DNI_10K
R218 10K
R219 DNI_10K
R220 10K
R221 DNI_10K
R222 10K
R223 DNI_10K
R224 10K
+3.3V_BUS
STRAPS
AGPFBSKEW(1:0)
X1CLK_SKWE(1:0)
ROMIDCFG(3:0)
ID_DISABLE
BUSCFG(2:0)
PIN
GPIO(1:0)
GPIO(3:2)
GPIO(9,13:11)
GPIO(8)
GPIO(6:4)
DESCRIPTION
AGP 1x clock feedback phase adjustment wrt refclk(cpuclk)
00 - refclk slightly earlier then feedback
01 - refclk 1 tap earlier then feedback
10 - refclk 1 t ap later then feedback
11 - refclk 2 t aps earlier then feedback clock
Clock phase adjustment between x1 clk and x2clk
00 - 0 tap delay
01 - 1 tap delay
10 - 2 taps delay
11 - 3 taps delay
If no ROM attached, comtrols chip IDis. If rom attached identifies ROM type
0000 - No ROM, CHG_ID=0
0001 - No ROM, CHG_ID=1
0100 - reserved
0110 - reserved
1000 - Parallel ROM, chip IDis from ROM
1001 - Serial AT25F1024 ROM (Atmel), chip IDis from ROM
1010 - Serial AT45DB011 ROM (Atmel), chip IDis from ROM
1011 - Serial M25P10 ROM (ST), chip IDis from ROM
1100 - Serial M25P05 ROM (ST), chip IDis from ROM
1100 - Serial NX25F011B ROM (ISSI), chip IDis from ROM
0 - Normal operation
1 - Shuts the chip down by not responding to any config cycles
In a system w i th two graphics chips, one on the motherboard,
the other on add-in card, the strap can be used to disable one of the two throught a jumper.
Controls bus type , CL K PL L select, and IDSEL
000 - 1.5V BUS -> AGP 4x, PLL clk, IDSEL=AD16
000 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD16
001 - 1.5V BUS -> AGP 4x, PLL clk, IDSEL=AD17
001 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD17
010 - 1.5V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD16
010 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD16
011 - 1.5V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD17
011 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD17
100 - PCI 66MHz, PLL clk
101 - PCI 33MHz, 3.3v, REF clk
110 - 1.5V BUS -> AGP 1x, REF clk, IDSEL=AD16
110 - 3.3V BUS -> AGP 1x, REF clk, IDSEL=AD16
111 - 1.5V BUS -> AGP 1x, REF clk, IDSEL=AD17
111 - 3.3V BUS -> AGP 1x, REF clk, IDSEL=AD17
Note that for AGP configurations GPIO(4) acts as the IDSEL strap.
For PCI it acts as the PLL bypass (33 or 66MHz) strap.
DEFAULT
00
(internal pull-down)
00
(internal pull-down)
1001
0
(internal pull-down)
000
(internal pull-down)
Mem_Strap03
Mem_Strap13
B B
LCDDATA163
LCDDATA173
VHAD03
+3.3V_BUS
R582 10K
R578 10K
R575 10K
A A
DEMUX_SEL3,13
DC_Strap33,14
DC_Strap13
R574 DNI_10K
R579 DNI_10K
R583 DNI_10K
8
DC Straps
R584 10K
R580 10K
DC_Strap4 3
R581 DNI_10K
R585 DNI_10K
7
STRAP R
STRAP S
STRAP T
+3.3V_BUS
R235 DNI_10K
R236 10K
R237 DNI_10K
R238 10K
R227 DNI_10K
R228 10K
R229 10K
R230 DNI_10K
R231 10K
R232 DNI_10K
PAL/NTSC 3
6
MULTIFUNC(1:0)
VIP_DEVICE
STRAP P
LOW
HIGH
STRAPS
DC_STRAP1 LCDDATA12
DC_STRAP2 LCDDATA13
DC_STRAP4 LCDDATA15 DAC2 ConfigurationDC_STRAP5 LCDDATA19
DC_STRAP6 LCDDATA18 TVO Standard Default (Resistor pull-up and switch short to GND)
DC_STRAP3 LCDDATA14 Connected to Component TV-Out Detect pin
LCDDATA(17:16)
LCDDATA(20)
STRAP T
INTERRUPT
ENABLED (DEFAULT)
DISABLED
PIN
00
01
1
11
5
Multi-function device select
00 - single function device.
01 - two function device. No AGP in either function
10 - two function device. AGP only in function 0
11 - two function device. AGP in both functions
If BUSCFG pin bas ed s tra ps ar e s et t o P CI, t he n AGP will not be enabled in any function.
See AGP func t io n table below for detail on AGP ability claims.
Indicates if any slave VIP host devices drove this in low during reset.
0 - Slave VIP host port devices present
1 - No slave VIP host port devices reporting presence during reset
DESCRIPTION
Internal TMDS Enabled
0 - Disabled
1 - Enabled
Video Capture Enabled
0 - Disabled
1 - Enabled
DAC2 Off
DAC2 On as CRT
0
DAC2 On as TVOUT
DAC2 On as TVOUT and CRT
0 - PAL (on board resistor pull-down and switch closed)
1 -NTSC (on board resistor pull-up)
THIS STRAP IS NO T PRESENT ON THIS CARD!
Normally high, pulled low by Component TVO dongle
4
00
0
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
(905) 882-2600
Title
AGP8X RV350 64/128M TSOP DVI-I/Slim_VGA VO
Size Document Number Rev
Custom
3
Date: Sheet
2
81-105-L50XXX
1.0
of
10 15Tuesday, January 06, 2004
1
8
7
6
5
4
3
2
1
OPTIONAL ESD/HOTPLUG PROTECTION DIODES
LAYOUT NOTE: MAY BE POSSIBLE TO REMOVE ALL DIODES ABOVE IF THERE'S NO SPACE,
PRIMARY CRT
D D
Place close to MJ2
C402
1
2
U7B
6
SN74ACT86D
12
13
C403
DNI_3.3pF
L51 82nH
L52 82nH
L53 82nH
DNI
+5V_BUS
147
U7A
3
SN74ACT86D
U7D
11
SN74ACT86D
R413
R494
Place close to U7
A_HSYNC_DAC13
A_VSYNC_DAC13
Pr
Y
Pb
R401 75.0R
R402 75.0R
R403 75.0R
DNI_3.3pF
C401
DNI_3.3pF
C450
100nF
4
5
A_R_DAC13
A_G_DAC13
A_B_DAC13
C C
B B
C404
3.3pF
L54 68nH
L55 68nH
L56 68nH
C406
C405
3.3pF
3.3pF
51R
51R
A_HSYNC_DAC1_B
A_VSYNC_DAC1_B
A_HSYNC_DVI-I_R
A_VSYNC_DVI-I_R
A_R_DVI-I
A_G_DVI-I
A_B_DVI-I
DDCDATA_DAC1_5V
DDCCLK_DAC1_5V
A_HSYNC_DAC1_B
A_VSYNC_DAC1_B
A_HSYNC_DVI-I_R 12
A_VSYNC_DVI-I_R 12
A_R_DVI-I 12
A_G_DVI-I 12
A_B_DVI-I 12
DNI
DVIDDCDATA3
DVIDDCCLK3
ASK BEFORE REMOVING.
C408
DNI_5pF
L61
DNI_82nH
+5V_BUS +5V_BUS
DNI_BAT54SLT1
D51
3
C409
DNI_5pF
L62
DNI_82nH
DNI_BAT54SLT1
2
2
D52
3
1
1
Place close to MJ2
DDCDATA_DAC1_5V
DDCDATA_DVI-I_R
DDCCLK_DAC1_5V
DDCCLK_DVI-I_R
+3.3V_BUS +3.3V_BUS +3.3V_BUS +5V_BUS+5V_BUS
DNI_BAT54SLT1
D55
3
+3.3V_BUS
R454
4.7K
+3.3V_BUS
R456
4.7K
2
1
DNI_BAT54SLT1
D56
3
1
1
DNI_BAT54SLT1
2
1
32
BSN20
Q71
32
BSN20
Q72
D57
3
DNI_5pF
DNI
DNI_82nH
GND_CHASSIS
+5V_BUS
R455
6.8k
+5V_BUS
R457
6.8k
2
1
C407
L60
DNI_BAT54SLT1
D53
3
DNI_BAT54SLT1
2
2
D54
3
1
1
DDCDATA_DVI-I_R 12
DDCCLK_DVI-I_R 12
+5V_BUS
F1
750mA
Resettable fuse
B51 30R
C441
68pF
Pr
Y
Pb
GND_CHASSIS
+5V_DIN
DNI_MJ2
1
R
2
G
3
B
11
MS0
12
MS1
4
MS2
15
MS3
9
NC
13
HS
14
VS
5
VSS
6
VSS#6
7
VSS#7
8
VSS#8
10
VSS#10
16
CASE
17
CASE#17
18
CASE#18
19
CASE#19
DB15F_slim_RA
<3RD PART FIELD>
+5V_DIN 12,13
DDC2_MONID0
DDC2_MONID1(SDA)
DDC2_MONID2
DDC2_MONID3(SCL)
+5V_BUS
Provide Return Path
Three on top side, three at
the bottom, spreaded high,
middle and low vertically
R1001 0_0805
R1002 0_0805
Remove R1003
A A
8
7
6
5
R1004 0_0805
R1005 0_0805
R1006 0_0805
4
GND_CHASSIS
3
C31
100nF
GND_CHASSIS
2
for Split Plane.
C34
100nF
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
(905) 882-2600
Title
AGP8X RV350 64/128M TSOP DVI-I/Slim_VGA VO
Size Document Number Rev
C
Date: Sheet
81-105-L50XXX
of
11 15Tuesday, January 06, 2004
1
1.0
5
4
3
2
1
D D
INSTALL TERMINATION RESISTORS CLOSE TO U1
TMDS_TX2N3
TMDS_TX2P3
TMDS_TX1N3
TMDS_TX1P3
C C
B B
TMDS_TX0N3
TMDS_TX0P3
TMDS_TXCP3
TMDS_TXCN3
HPD3
DDCCLK_DVI-I_R11
DDCDATA_DVI-I_R11
R601 330R
R602 330R
R603 330R
R604 330R
DDCCLK_DVI-I
DDCDATA_DVI-I
+5V_DIN11,13
A_VSYNC_DVI-I_R11
A_R_DVI-I11
A_G_DVI-I11
A_B_DVI-I11
A_HSYNC_DVI-I_R11
R610 20K
D121
2.5V
2 1
R609
100K
B52 30R
PRIMARY DVI-I CONNECTOR
J2
25
25
1
TMDS Data2-
2
TMDS Data2+
3
TMDS Data2/4 Shield
4
TMDS Data4-
5
TMDS Data4+
6
DDC Clock
7
DDC Data
8
Analog VSYNC
9
TMDS Data1-
10
TMDS Data1+
11
TMDS Data1/3 Shield
12
TMDS Data3-
13
TMDS Data3+
14
+5V Power
15
GND (for +5V)
16
Hot Plug Detect
17
TMDS Data0-
18
TMDS Data0+
19
TMDS Data0/5 Shield
20
TMDS Data5-
21
TMDS Data5+
22
TMDS Clock Shield
23
TMDS Clock+
24
TMDS Clock-
Pr
Y
Pb
C510
68pF
C1
Analog Red
C2
Analog Green
C3
Analog Blue
C4
Analog HYNC
C5
Analog GND
C6
Analog GND#C6
26
26
DVI_A/D
IF HOT PLUG DETECT IS NOT REQUIRED
REMOVE ALL T H I S L OGIC EXCEPT
FOR 100K PULL DOWN
A A
5
4
3
2
GND_CHASSIS GND_CHASSIS
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP8X RV350 64/128M TSOP DVI-I/Slim_VGA VO
Size Document Number Rev
B
Date: Sheet
81-105-L50XXX
of
12 15Tuesday, January 06, 2004
1
1.0
8
7
6
5
4
3
2
1
+3.3V_BUS +5V_BUS+5V_BUS
DNI_BAT54SLT1
DNI_BAT54SLT1
2
D123
DNI
D122
1 2
1 2
1 2
DNI
3
1
A_R_H2
A_G_H2
A_B_H2
DDC3DATA_H2
DDC3CLK_H2
H2SYNC_H2
V2SYNC_H2
3
D D
C C
B B
To HD1
R1007
75.0R
A_B_H
A_G_H
A_R_H
R1008
75.0R
+5V_BUS
+5V_BUS
R1016 51R
8
U814C
SN74ACT86D
R1017 51R
6
U814B
SN74ACT86D
SN74ACT86D
U814A
3
R1011
6.8k
R1014
6.8k
A_R_DAC2_H1
A_G_DAC2_H1
A_B_DAC2_H1
R1012
0_0805
33R
R1015
0_0805
33R
B324
0_0805
B325
0_0805
C848
5pF
B322
B323
C849
5pF
L94 82nH
1 2
L96 82nH
1 2
L98 82nH
1 2
C846
C845
R1009
75.0R
DNI/3.3pF
DNI/3.3pF
+3.3V_BUS
DDC3DATA3
+3.3V_BUS
DDC3CLK3
H2SYNC3
V2SYNC3
R1010
4.7K
R1013
4.7K
0.1uF
C858
C847
DNI/3.3pF
10
9
5
4
1
32
BSN20
Q814
1
32
BSN20
Q815
+5V_BUS
147
1
2
L95 68nH
L97 68nH
L99 68nH
C850
5pF
Close to HD1
DNI_BAT54SLT1
2
DNI
1
DNI/82nH
D124
L100
+3.3V_BUS+3.3V_BUS
DNI_BAT54SLT1
DNI
D125
3
C853
DNI/5pF
L102
DNI/82nH
1 2
DNI_BAT54SLT1
2
DNI
1
DNI
2
3
1
C851
C852
DNI/5pF
DNI/5pF
L101
DNI/82nH
1 2
1 2
D126
C854
DNI_BAT54SLT1
2
D127
DNI
C855
3
C856
DNI
GND_CHASSIS
3
1
DNI
For R9600L-64/128T
R1019 DNI_0
R1020 D N I_0
R1021
U815
1
SEL
2
1A0
3
1A1
5
1B0
6
1B1
11
1C0
1C1101D0
15
E
PI5V330
VCC
GND
16
4
YA
7
YB
9
YC
12
YD
13
1D1
14
8
2
1
C857
DNI
DNI_0
+5V_BUS
+5V_BUS+5V_BUS
DNI_BAT54SLT1
D128
DNI
3
C859
100nF
2
+5V_DIN11,12
1
B326
30R
C860
68pF
GND_CHASSIS
HD1
1
R
2
G
3
B
11
MS0
12
MS1
4
MS2
15
MS3
9
NC
13
HS
14
VS
5
VSS
6
VSS
7
VSS
8
VSS
10
VSS
16
CASE
Header 2x8
From U1
DEMUX_SEL 3 ,10
A_B/COMP_DAC2 3
A_G/Y_DAC2 3
A_R/C_DAC2 3
A_COMP_DAC214
A_Y_DAC214
A A
A_C_DAC214
To J5
A_COMP_DAC2
A_Y_DAC2
A_C_DAC2
8
7
6
5
4
3
<Variant Name>
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP8X RV350 64/128M TSOP DVI-I/Slim_VGA VO
Size Document Number Rev
Custom
Date: Sheet
2
81-105-L50XXX
of
13 15Tuesday, January 06, 2004
1
1.0
8
7
6
5
4
3
2
1
D D
C C
Y
A_Y_DAC213
R504
75.0R
Pr
A_C_DAC213
R505
75.0R
Pb
A_COMP_DAC213
R506
75.0R
L91 1.8uH
C501
82pF
L92 1.8uH
C503
82pF
L93 1.8uH
C505
82pF
A_Y_DAC2_F
C502
82pF
A_C_DAC2_F
C504
82pF
A_COMP_DAC2_F
C506
82pF
Cm3
Cm4
Cm5
Place close to connector J5
TV Out (SVHS)
J5
Y
A_Y_DAC2_F
A_C_DAC2_F
Pr
A_COMP_DAC2_F
Pb
B B
R519 0R
R520 0R
R521 0R
DNI
C509
DNI_82pF
C507
DNI_82pF
A_Y_DAC2_DIN
A_C_DAC2_DIN
A_COMP_DAC2_DIN PIN7
C508
DNI_82pF
GND_CHASSISGND_CHASSISGND_CHASSIS
DC_Strap33,10
PIN1
R513
1Kohm@100MHz
R377 0_0805
PIN2
R514
1Kohm@100MHz
PIN5
GND_CHASSIS
6
3
4
7
5
1
2
8
9
10
Jm4
+12V
Y-OUT
C-OUT
Comp_out
SYNC
GND
GND#2
CASE
CASE#9
CASE#10
Conn_DIN_Mini_Circular_7_Pin_with_O_Ring
A A
ATI Techno lo gi es Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP8X RV350 64/128M TSOP DVI-I/Slim_VGA VO
Size D o c ument N umber Re v
Custom
8
7
6
5
4
3
Date: Sheet
2
81-105-L50XXX
1.0
of
14 15Tuesday, J anuary 06, 2004
1
5
D D
4
3
2
1
PCB MOUNTING HOLE
MT1
MT_Hole_0.136_in.
C C
MT2
MT_Hole_0.136_in.
GND_CHASSIS GND_CHASSIS
B B
A A
5
4
3
2
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP8X RV350 64/128M TSOP DVI-I/Slim_VGA VO
Size Document Number Rev
B
Date: Sheet
81-105-L50010
of
15 15Tuesday, January 06, 2004
1
A
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