ECS R9200L-64TD Schematics

8
GND_TXVSSR
+12V_BUS
C10 place at the AGP connector
C10
DD
AGP_INTR#2
AGP_GNT#2 AGP_WBF#2
AGP_SB_STB#2
AGP_MB_8X_DET#2
AGP_DBI_HI2
AGP_RESET#2
CC
BB
AA
AGP_RESET#
AGP_AD_STB1#2
AGP_FRAME#2
AGP_TRDY#2
AGP_STOP#2 AGP_PAR2
AGP_AD_STB0#2
AGP_MB_8X_DET#
DNI/10uF_20V
R3 100R
U6A
R4
SN74ACT86D
180R
COMMON
AGP_TYPEDET#
AGP_GC_8X_DET#
+3.3V_BUS
UNIVERSAL VREFGC CIRCUIT (2X, 4X, 8X)
8
R830R
+5V_BUS
147
3
R19 0R
R81 0R
R90 47K
13 12
7
C11 100nF
X7R
1 2
For retail, 1K ohm pull-down causes AMD system detects AGP2X only
+12V, TYPEDET# short protection for OEM (1KR)
SN74ACT86D
7
6
The following grounds should be routed back to their respective regulators and then tied directly to the ground plane with one
GND_R2SETGND_PVSSGND_MPVSSGND_AVSSQGND_AVSSNGND_A2VSSN GND_A2VSSQGND_TPVSS
GND_RSET
C2 100uF_6.3V
Biggest footprint
AGP_TYPEDET# AGP_GC_8X_DET#
AGP_ST1
AGP_SBA1 AGP_SBA3
AGP_SBA5 AGP_SBA7
AGP_AD30 AGP_AD28
AGP_AD26 AGP_AD24
AGP_C/BE#3
AGP_AD22 AGP_AD20
AGP_AD18 AGP_AD16
AGP_AD15 AGP_AD13
AGP_AD11 AGP_AD9
AGP_C/BE#0
AGP_AD6 AGP_AD4
AGP_AD2 AGP_AD0
+VDDQ_BUS
32
11
R91 1K
2N7002E Q10
1
R92
147R_1%
via: GND_PVSS, GND_MPVSS, GND_TPVSS, and GND_A2VSSN. The other ground pins (GND_AVSSN, GND_A2VSSQ, GND_RSET, GND_R2SET) should be tied to the ground plane directly through one via as close to the pins as possible without connecting to anything else. If space is an issue it is possible to use one via for two adjacent pins.
Use 47uF Tant. 16V 20% D size (P/N 4230047600), 800mR Max. ESR and Max. ripple 430mA @ 100kHz or 100uF, Alum. 6.3V 20% 6.3mm dia (P/N 4261010700), 440mR Max. ESR and Max. ripple 230mA @ 100kHz or 47uF, Alum. 6.3V 20% 5mm dia (P/N 4262047600), 760mR Max. ESR and Max. ripple 150mA @ 100kHz
MAGP1
A1
12V
A2
TYPEDET#
A3
GC_DET#/RESEVED
A4
USB-
A5
GND
A6
INTA#
A7
RST#
A8
GNT#
A9
VCC3.3
A10
ST1
A11
MB_DET#/RESERVED
A12
DBI_HI/PIPE#
A13
GND
A14
WBF#
A15
SBA1
A16
VCC3.3
A17
SBA3
A18
SB_STB#
A19
GND
A20
SBA5
A21
SBA7
A22
KEY
A23
KEY
A24
KEY
A25
KEY
A26
AD30
A27
AD28
A28
VCC3.3
A29
AD26
A30
AD24
A31
GND
A32
AD_STB1#
A33
C/BE3#
A34
VDDQ
A35
AD22
A36
AD20
A37
GND
A38
AD18
A39
AD16
A40
VDDQ
A41
FRAME#
A42
KEY
A43
KEY
A44
KEY
A45
KEY
A46
TRDY#
A47
STOP#
A48
PME#
A49
GND
A50
PAR
A51
AD15
A52
VDDQ
A53
AD13
A54
AD11
A55
GND
A56
AD9
A57
C/BE0#
A58
VDDQ
A59
AD_STB0#
A60
AD6
A61
GND
A62
AD4
A63
AD2
A64
VDDQ
A65
AD0
A66
VREFGC UNIVERSAL_AGP_BUS
AGP_VREFGC
R_AGP8X must be 1% resistor to provide 350mV +/- 5% on Vref
R_AGP8X
R93 332R_1%
C19
R94
10nF
100R_1%
6
OVRCNT#
USB+ INTB# REQ#
VCC3.3
RBF#
DBI_LO/RESERVED
SBA0
VCC3.3
SBA2
SB_STB
SBA4 SBA6
AD31 AD29
VCC3.3
AD27 AD25
AD_STB1
AD23
VDDQ
AD21 AD19
AD17
C/BE2#
VDDQ IRDY#
DEVSEL#
VDDQ
PERR# SERR#
C/BE1#
VDDQ
AD14 AD12
AD10
VDDQ
AD_STB0
VDDQ
VREFCG
5
+3.3V_BUS+5V_BUS+VDDQ_BUS
C8
C5
DNI/47uF_6.3V
DNI/47uF_6.3V
>=6.3V
>=6.3V
B1 B2
5.0V B3
5.0V B4
B5
GND
B6 B7
CLK
B8 B9 B10
ST0
B11
ST2
B12 B13
GND
B14 B15 B16 B17 B18 B19
GND
B20 B21 B22
KEY
B23
KEY
B24
KEY
B25
KEY
B26 B27 B28 B29 B30 B31
GND
B32 B33 B34 B35 B36 B37
GND
B38 B39 B40 B41 B42
KEY
B43
KEY
B44
KEY
B45
KEY
B46 B47 B48 B49
GND
B50 B51 B52 B53 B54 B55
GND
B56 B57
AD8
B58 B59 B60
AD7
B61
GND
B62
AD5
B63
AD3
B64 B65
AD1
B66
5
AGP_ST0 AGP_ST2
AGP_SBA0 AGP_SBA2
AGP_SBA4 AGP_SBA6
AGP_AD31 AGP_AD29
AGP_AD27 AGP_AD25
AGP_AD23 AGP_AD21
AGP_AD19 AGP_AD17
AGP_C/BE#2
AGP_C/BE#1 AGP_AD14
AGP_AD12 AGP_AD10
AGP_AD8
AGP_AD7 AGP_AD5
AGP_AD3 AGP_AD1
AGP_AGPREF
+12V_BUS
J8 1
2
DNI/CON2
4
AGP_SBA[7..0] AGP_ST[2..0] AGP_C/BE#[3..0] AGP_AD[31..0]
R860R
4
3
AGP_SBA[7..0]2 AGP_ST[2..0]2 AGP_C/BE#[3..0]2 AGP_AD[31..0]2
AGP_AGP/PCICLK2 AGP_REQ#2
AGP_RBF#2 AGP_DBI_LO2
AGP_SB_STB2
AGP_AD_STB12
AGP_IRDY#2
AGP_DEVSEL#2
AGP_AD_STB02
3
AGP_AGPREF AGP_VREFGC
+VDDQ_BUS
32
1
R84DNI/0R R85DNI/0R
+VDDQ_BUS
32
1
2
R88169R_1%
Q9 2N7002E
R8971.5R_1%
AGP_AGPTEST
Keep stubs short
R_AGP8X must be 1% resistor to provide 350mV +/- 5% on Vref
AGP_AGPTEST2
R_AGP8X
2N7002E Q11
R95
147R_1%
R96 332R_1%U6D
R97 100R_1%
ATI Technologies Inc.
1 Commerce Valley Drive East Markham, Ontario Canada, L3T 7N6 (905) 882-2600
Title SizeDocument NumberRev
Custom
Date:Sheet of
2
C21 10nF
AGP_AGPREFCG2
R9200L-64TD 81-105-L31020
1
114Monday, October 20, 2003
1
1.0
8
AGP_RESET#1
AGP_DEVSEL#1
AGP_IRDY#1
AGP_FRAME#1
AGP_AD_STB01 AGP_AD_STB11
AGP_SB_STB1
AGP_SBA[7..0]1
AGP_REQ#1
AGP_GNT#1
AGP_PAR1
AGP_STOP#1 AGP_TRDY#1
AGP_INTR#1
AGP_WBF#1 AGP_RBF#1
8
AGP_AD[31..0]
AGP_C/BE#[3..0]
R360R
AGP_ST[2..0]
C20 100nF
A_R/C_DAC213 A_G/Y_DAC213
A_B/COMP_DAC213 A_HSYNC_DAC212,13 A_VSYNC_DAC213
Y2
27_MHZ
3
2 1
C73 DNI/22pF
AGP_SBA[7..0]
+3.3V_BUS
OSC_IN
AGP_AD[31..0]1
DD
AGP_C/BE#[3..0]1
AGP_AGP/PCICLK1
CC
AGP_ST[2..0]1
AGP_AGPREFCG1
BB
AGP_AGPTEST1
AA
AGP_SB_STB#1 AGP_AD_STB0#1 AGP_AD_STB1#1
AGP_MB_8X_DET#1 AGP_DBI_HI1 AGP_DBI_LO1
TP8 TP
7
GND_R2SET
C120527pF
R1115 1M
C120627pF
7
AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31
AGP_C/BE#0 AGP_C/BE#1 AGP_C/BE#2 AGP_C/BE#3
AGP_SBA0 AGP_SBA1 AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA6
AGP_SBA7
AGP_ST0 AGP_ST1 AGP_ST2
R40715R
R1198DNI/4.7K R1199DNI/4.7K
R33 1K
TESTEN
W29 W28
AA29 AA28
AF29 AG30 AE29 AG28
AF28 AF27 AJ26
AH25 AC29
AB26 AE27
AD26 AC25 AC26 AA25 AA26
AD28 AD29 AC28
AB25
AG27 AB28 AB29
AJ21 AJ22 AK22 AK21 AG25 AF25
AF23 AG24
AG29 AH29
AJ28 AJ29
AH26 AJ27
K27
L26 L25
L27 M25 M26 N26 N25 R26 R25 T26 T25 U26 U25 U27 V26 M28 N29 N28 P29 P28 R29 R28 T28 V29 V28
Y29 Y28
P27 V25 M29 T29
J29
J28 K29 K28
L29
L28
P25 U29
Y25 Y26
P26 U28 H29 H28
6
U1A
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
C/BEb0 C/BEb1 C/BEb2 C/BEb3
PCICLK RSTb REQb GNTb PAR STOPb DEVSELb TRDYb IRDYb FRAMEb INTAb
WBFb NC19
NC18 RBFb AD_STBF0 AD_STBF1 SB_STBF
SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7/IDSEL
ST0 ST1 ST2
SB_STBS AD_STBS0 AD_STBS1 AGPREF AGPTEST AGP8X_DETb DBI_HI DBI_LO
R2SET C_R Y_G COMP_B H2SYNC V2SYNC
CRT2DDCCLK CRT2DDCDAT
NC34 NC33
XTALIN XTALOUT
TESTEN STEREOSYNC
RV280
STEREOSYNC
6
Part 1 of 5
EXT TMDS / GPIO / ROM
PCI/AGPAGP2XCLK
NCSTMDSDAC1
AGP4X/8X
SSC DAC2
STEREOSYNC7
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8
GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16
ROMCSb
DVOMODE ZV_LCDDATA0 ZV_LCDDATA1 ZV_LCDDATA2 ZV_LCDDATA3 ZV_LCDDATA4 ZV_LCDDATA5 ZV_LCDDATA6 ZV_LCDDATA7 ZV_LCDDATA8 ZV_LCDDATA9
ZV_LCDDATA10 ZV_LCDDATA11 ZV_LCDDATA12 ZV_LCDDATA13 ZV_LCDDATA14 ZV_LCDDATA15 ZV_LCDDATA16 ZV_LCDDATA17 ZV_LCDDATA18 ZV_LCDDATA19 ZV_LCDDATA20 ZV_LCDDATA21 ZV_LCDDATA22 ZV_LCDDATA23
ZV_LCDCNTL0 ZV_LCDCNTL1 ZV_LCDCNTL2 ZV_LCDCNTL3
NC35 NC27 NC36 NC28 NC37 NC29 NC39 NC31 NC38 NC30 NC22 NC13 NC23 NC14 NC24 NC15 NC26 NC17 NC25 NC16
NC7 NC8
DPLUS
DMINUS
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
DVIDDCCLK
DVIDDCDATA
HPD
HSYNC VSYNC
RSET
VGADDCDATA
VGADDCCLK
AUXWIN
R G B
5
5
AJ5 AK4 AJ4 AF4 AG4 AH4 AK3 AJ3 AH3 AG3 AF3 AJ2 AH2 AG2 AF2 AH1 AG1 AH5 AE10 AF5 AE6 AF6 AE7 AG6 AF7 AG8 AF8 AE8 AE9 AF9 AG9 AK7 AJ7 AH8 AJ8 AH9 AJ9 AK9 AH10 AK10 AJ10 AH11 AJ11
AK6 AJ6 AH6 AH7
AE15 AF15 AE16 AF16 AG15 AH15 AH16 AH17 AF17 AG17 AJ17 AH18 AK18 AJ18 AG19 AH19 AJ16 AK16 AH20 AJ20 AF11 AE12
AF10 AE11
AJ13 AH13 AJ14 AH14 AJ15 AK15 AK12 AK13
AF13 AE13
AF12 AK25
AJ25 AK24 AH28 AH27
AJ23
AG26 AF26
AE25
VID/DVO12 VID/DVO13 VID/DVO14 VID/DVO15
R39499R
GND_RSET
TP10 TP
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 ROMCS# DVOMODE
VID/DVO16 VID/DVO17 VID/DVO18 VID/DVO19 VID/DVO20
TP7 TP
4
R986 10K
VSYNC
VGADDCDATA VGADDCCLK
4
GPIO[13..0]
R1278
DNI
24bit-SDR-DVO
DC_Strap18 DC_Strap28 DC_Strap38 DC_Strap48
TMDS_TX0N14 TMDS_TX0P14 TMDS_TX1N14 TMDS_TX1P14 TMDS_TX2N14 TMDS_TX2P14 TMDS_TXCN14 TMDS_TXCP14
DVIDDCCLK13 DVIDDCDATA13
CHARGE_POW14 A_R_DAC111
A_G_DAC111 A_B_DAC111 A_HSYNC_DAC111 A_VSYNC_DAC111
CRT1DDCDATA11 CRT1DDCCLK11
+VDDC_CT
3
GPIO[13..0]7,8
RSET R2SET
Mem_Strap27 Mem_Strap17 Mem_Strap07 ROMCS#8
3
2
THE VALUES OF RSET AND R2SET SHOWN IN THE TABLE MAY BE APPROXIMATE VALUES ONLY (SUITABLE FOR PROTOTYPING) BEFORE GOING INTO PRODUCTION,CONTACT YOUR ATI
499R
REPRESENTATIVE FOR THE RSET/R2SET VALUES QUALIFIED FOR MASS PRODUCTION
715R
LCDDATA167 LCDDATA177 PAL/NTSC8 DC_Strap58,13 LCDDATA207
STEREOSYNC VGADDCDATA VGADDCCLK VSYNC TESTEN
TDO TDI TMS TCK TRST
ATI Technologies Inc.
1 Commerce Valley Drive East Markham, Ontario Canada, L3T 7N6 (905) 882-2600
Title SizeDocument NumberRev
Custom
Date:Sheet of
2
1
TP1
OPTION BOUNDARY
TP2
TP
SCAN WITH TESTEN
TP3
TP TP4
TP TP5
TP TP
Some Part Ref's updated to 988 brd
R9200L-64TD 81-105-L31020
214Thursday, November 20, 2003
1
1.0
5
DD
4
3
2
1
MEMORY CHANNEL A
QSA[7..0]9
DQMA#[7..0]9
MAA[13..0]9 MDA[63..0]9
CC
BB
AA
QSA[7..0] DQMA#[7..0] MAA[13..0] MDA[63..0]
MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63
U1B
G29
DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 DQA9 DQA10 DQA11 DQA12 DQA13 DQA14 DQA15 DQA16 DQA17 DQA18 DQA19 DQA20 DQA21 DQA22 DQA23 DQA24 DQA25 DQA26 DQA27 DQA28 DQA29 DQA30 DQA31 DQA32 DQA33 DQA34 DQA35 DQA36 DQA37 DQA38 DQA39 DQA40 DQA41 DQA42 DQA43 DQA44 DQA45 DQA46 DQA47 DQA48 DQA49 DQA50 DQA51 DQA52 DQA53 DQA54 DQA55 DQA56 DQA57 DQA58 DQA59 DQA60 DQA61 DQA62 DQA63
RV280
Part 2 of 5
MEMORY INTER F A C E A
ELPIDA
G30 F28 F30 E29 D28 D29 D30 K25 K26
J25
J26 G28 G25 G26 G27 C29 B29 B28 C27 C26 B26 C25 B25 E26 F25 E25 F24 E23 D22 F22 E22 C17 B17 C16 B16 C14 B14 C13 B13 E18 F17 E17 D16 F15 E15 F14 E14 A13 C12 A12 B12 C10 B10
C9
B9 E13 F12 E12 F11 E10
F9
E9
F8
AA10 AA11 AA12 AA13
DQMAb0 DQMAb1 DQMAb2 DQMAb3 DQMAb4 DQMAb5 DQMAb6 DQMAb7
QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6
QSA7 RASAb CASAb
WEAb CSAb0 CSAb1
CKEA
CLKA0
CLKA0b
CLKA1
CLKA1b
CLKAFB
VREF DIMA0
DIMA1
MAA0
B24
AA0
MAA1
A24
AA1
MAA2
B23
AA2
MAA3
C23
AA3
MAA4
B21
AA4
MAA5
F21
AA5
MAA6
E21
AA6
MAA7
F20
AA7
MAA8
E20
AA8
MAA9
C21
AA9
MAA10
B22
MAA11
C22
MAA12
A25
MAA13
C24
DQMA#0
E28
DQMA#1
H26
DQMA#2
A27
DQMA#3
E24
DQMA#4
B15
DQMA#5
E16
DQMA#6
C11
DQMA#7
E11
QSA0
F29
QSA1
H25
QSA2
B27
QSA3
F23
QSA4
C15
QSA5
F16
QSA6
B11
QSA7
F10
RASA#
A19
CASA#
C18
WEA#
F18
CSA#0
E19
CSA#1
F19
CKEA
B19
CLKA0
C20
CLKA#0
B20
CLKA1
B18
CLKA#1
A18 C19
TP11 TP
B8 F26
F13
RASA#9 CASA#9 WEA#9 CSA#09 CSA#19 CKEA9
CLKA09,10 CLKA#09,10
CLKA19,10 CLKA#19,10
+VREF
Place close to ASIC ball Use localized Vref on the memory page
Vref Voltage
+MVDDQ
R265
Re6
499R_1%
R268
Re7
499R_1%
+VREF
MEMORY CHANNEL B
U1C
B6
DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 DQB9 DQB10 DQB11 DQB12 DQB13 DQB14 DQB15 DQB16 DQB17 DQB18 DQB19 DQB20 DQB21 DQB22 DQB23 DQB24 DQB25 DQB26 DQB27 DQB28 DQB29 DQB30 DQB31 DQB32 DQB33 DQB34 DQB35 DQB36 DQB37 DQB38 DQB39 DQB40 DQB41 DQB42 DQB43 DQB44 DQB45 DQB46 DQB47 DQB48 DQB49 DQB50 DQB51 DQB52 DQB53 DQB54 DQB55 DQB56 DQB57 DQB58 DQB59 DQB60 DQB61 DQB62 DQB63
RV280
Part 3 of 5
ELPIDA
MEMORY INTERFACE B
MEMVMODE
MEMVMODE1
C6
B5
C5
B2 C3 C2 D2
E8
E7 D4 D3
F6
F3
F5 G6 D1
E2
F2
F1 G2
H3
H2
J3 G4
H6
H5
J6
K5
K4
L6
L5
U2
V2
V1
V3 W3
Y2
Y3
AA2 AA3 AB2 AB3 AC2 AD1 AD3 AE1 AE2
U6
U5
U3
V6 W5 W4
Y6
Y5
AA6 AA5 AB6 AB5 AD6 AD5 AE5 AE4
DQMBb0 DQMBb1 DQMBb2 DQMBb3 DQMBb4 DQMBb5 DQMBb6 DQMBb7
QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6
QSB7 RASBb CASBb
WEBb CSBb0 CSBb1
CKEB CLKB0
CLKB0b
CLKB1
CLKB1b CLKBFB
DIMB0 DIMB1
MEMTEST
J2
AB0
K3
AB1
K2
AB2
L3
AB3
L2
AB4
M3
AB5
M2
AB6
N5
AB7
M1
AB8
M5
AB9
N3
AB10
P2
AB11
P6
AB12
P5
AB13
A4 E3 G3 J5 W2 AC3 W6 AC6
B4 E5 G1 K6 W1 AD2 V5 AC5
R2 T5 T6 R5 R6 R3 N1
N2 T2
T3 P3
TP12 TP
R53
4.7K
R514.7K R52DNI/4.7K
R54 DNI/4.7K
B7 C7
G5 AE3
C8
R55 47R
MEMVMODE[1:0]MEMORY IO VOLTAGE
0 1
2.5V (DDR)
1.8V (DDR)
1 0
1 1
3.3V (SDR)
+VDDC_CT
Default
ATI Technologies Inc.
1 Commerce Valley Drive East Markham, Ontario Canada, L3T 7N6 (905) 882-2600
Title SizeDocument NumberRev
Custom
5
4
3
2
Date:Sheet of
R9200L-64TD 81-105-L31020
1
314Monday, October 20, 2003
1.0
5
U1D
P18
VDDC
P19 U12 U13 U14 U17
+MVDDQ
+VDDC_CT
GND_A2VSSN
(80mA)
U18
U19
V12
V13
V14
V17
V18
V19
W12 W13 W14 W17 W18 W19
H10 H13 H15 H17 H19 H22
J1 J23 J24 J27
J4
J7
J8
L8
M4 N4 N7 N8 R1 R4
T4
T7
T8
E27
F4
G10 G13 G15 G22
G7
Y23 L23
H20 H11
P8
Y8
AC11 AC20
AK19 AE19 AE20 AF20 AG20
AJ19 AF18 AF19 AE18 AE17
AJ12 AH12
AF14 AE14
AG14 AG13 AG12
AF21 AF22
AH21 AF24 AE23
AE21 AE22 AG22 AH22
GND_A2VSSQ
Matching Ground
AVSSN (Noisy) AVSSQ
DD
CC
+3.3V_BUS
D31
2.4V
2 1
C55 47uF_6.3V
100nF
>=6.3V
X7R
+TPVDD
C58
C57
100nF
4.7uF
>=6.3V
X7R
Ceramic
BB
+VDDC_CT
+A2VDD
C61
C62
22uF_10V
100nF
X7R
GND_A2VSSN
AA
GND_TPVSS
B16200R
C59
4.7uF
>=6.3V Ceramic
+A2VDDQ
C63
4.7uF
GND_A2VSSQ
C77
C60
100nF
DNI/100pF X7R
X7R
+AVDD
C64 100nF
X7R
Board power and ground option(s)
5
C68
C67
100nF
4.7uF
X7R
GND_AVSSN
+AVDD
Pin Names Voltage
DAC1 VDD A2VSSQ
Usage
DAC1 Band Gap Ref. AVDD sourced from VDDC_CT
thru bead at least 15 mil trace and not longer than 1.5 inch. AVSSN and AVSSQ with single via to GND close to the pin.
Part 4 of 5
VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC
VDDR1
Memory I/O Power
VDDR1
(1.8V/2.5V/3.3V)
VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1
VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1
I/O l evel shift pow er
(1.8V)
VDDC18 VDDC18 VDDC18 VDDC18 VDDC18 VDDC18 VDDC18 VDDC18
NC VDDC18 VDDC18 NC NC
NC NC NC NC NC
(1.8V)
TMDS PLL TMDS I/O
TPVDD TPVSS
TXVDDR TXVDDR
(1.8V)
TXVSSR TXVSSR TXVSSR
Analog Display Power,
A2VDD
see table below
A2VDD A2VDDQ
AVDD AVDD
A2VSSN A2VSSN A2VSSDI A2VSSQ
RV280
+A2VDD
2.5V1.8V
DAC2 VDD
(120mA)
(1) A2VDD regulated source and A2VSSN return path routed with at least 15 mil trace and not longer than 1.5 inch. AVSSN with single via to GND at the regulator.
(2) Sourced from VDD thru bead instead of the regulator
VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1
VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1
I/O POWER
VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1
VDDRH0 VDDRH1
VSSRH0 VSSRH1
VDDRH 1 - CH B Clock PowerAGP Bus I /O Power
VDDRH 0 - CH A Clock Power
(VDDR1)
MPVDD MPVSS
PLL MPLL
VDDR4 VDDR4 VDDR4 VDDR4 VDDR4
(1.8V/3.3V)
Ext. TMDS/
DVO Power
VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR3
(3.3V)
GPIO & Ext.
TMDS I/O Power
(1.5V/3.3V) (1.8V) (1.8V)
AVDDDI
A2VDDDI
AVSSQ
AVSSDI
AVSSN AVSSN
+A2VDDQ
Matching Ground
1.8V
A2VSSN
DAC2 Band Gap Ref.
(Noisy)
Source from AVDD thru bead. A2VSSQ with sigle via to GND close to the pin.
VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC
PVDD PVSS
VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP
4
+VDDC
+MPVDD
C52
4.7uF
>=6.3V Ceramic
B733 220
+VDDC_CT+3.3V_BUS
B17200R C66
4.7uF
>=6.3V Ceramic
B734 DNI
Matching Ground
AVSSDI A2VSSDI (Digital)(Quiet)
C53 100nF
X7R
+VDDC
CP9A
8 1 10nF
+PVDD
GND_PVSS
+VDDC_CT
CP9B
7 2 10nF
C54
4.7uF
>=6.3V Ceramic
AC13 AC15 AC17 AD13 AD15 M12 M13 M14 M17 M18 M19 N12 N13 N14 N17 N18 N19 P12 P13 P14 P17
+MVDDQ A15 A21 AA7 AA8 D11 D14 D17 D8 V4
A28 A3 A9 AA1 AA4 AD4 B1 B30 D10 D19 D20 D23 D26 D6 V7 V8
G19 N6
G18 M6
A7 A6
AK27 AK28
AC10 AC9 AD10 AD9 AG10 AD22 AC22 AC21 AD21 AC19 AD19 AD7 AC8
AA23 AA24 AB27 AB30 AC23 AD27 AE30 AH30 J30 M23 M24 N27 N30 P23 T23 T24 T27 T30 V23 V24 W27 W30 Y27
AH24 AH23
AJ24 AG23 AD24 AE24
4
+3.3V_BUS
GND_AVSSQ
GND_AVSSN
Matching
Ground
(Quiet)
C51 100nF
X7R
C1215
1uF
+VDDQ_BUS
TP9
C65 100nF
TP
X7R
+AVDDDI +A2VDDDI
1.8V Digital Power for
DAC1 and DAC2
Source from VDDC_CT thru bead
GND_MPVSS
3
CP9D
CP3A
CP3C
CP9C
6 3 10nF
CP3B
5 4
8 1
6 3
7 2
10nF
10nF
10nF
10nF
+VDDC
C27
C26
100nF
100nF
X7RX7RX7RX7RX7R
+3.3V_BUS
CP1B
CP1A
7 2
8 1
10nF
10nF
+MVDDQ +MVDDQ
CP5C
CP5B
CP5A
6 3
7 2
8 1
10nF
10nF
10nF
+MVDDQ
C32
C33
100nF
100nF
X7RX7RX7RX7R
+VDDC_CT
CP1C
CP1D
6 3
5 4
10nF
10nF
+VDDQ_BUS
C45
C46
100nF
100nF
X7R
X7RX7RX7RX7R
C47 100nF
CP3D
5 4 10nF
C28 100nF
C44 100nF
CP5D
5 4 10nF
C34 100nF
C83 100nFC56
X7R
C48 100nF
CP4A
8 1 10nF
C29 100nF
CP6A
8 1 10nF
C35 100nF
CP4B
7 2 10nF
CP6B
7 2 10nF
C49 100nF
C30 100nF
Distributed around +VDDQ_BUS plane
3
CP4C
6 3 10nF
CP6C
6 3 10nF
CP2A
CP4D
8 1
5 4
10nF
10nF
C38 10uf
CP6D
5 4 10nF
PLACE DIRECTLY UNDERNEATH CHANNEL A & B SECTION OF ASIC.
CP2B
CP2C
7 2
6 3
10nF
10nF
C39 10uf
+VDDQ_BUS
CP8A
8 1 10nF
+3.3V_BUS
CP8B
7 2 10nF
2 1
CP2D
5 4 10nF
CP8C
6 3 10nF
D30
2.4V
2
+VDDC
C23 10uf
At the corner of VDDC plane
CP8D
5 4 10nF
2
1
U1E
F27
VSS
F7 G12 G16 G21 G24
G9 H12 H14 H16 H18 H21 H23 H27
H4
H8
H9
K1 K23 K24 K30
K7
K8
L4
M15 M16 M27 M30
M7
M8 N15 N16 N23 N24 P15 P16
P4 R12 R13 R14 R15 R16 R17 R18 R19 R23 R24 R27 R30
R7 R8
T1 T12 T13 T14 T15 T16 T17 T18 T19
W23 W24 W25 W26
W7 W8
Y4
Part 5 of 5
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
RV280
CORE GND
ATI Technologies Inc.
1 Commerce Valley Drive East Markham, Ontario Canada, L3T 7N6 (905) 882-2600
Title SizeDocument NumberRev
Custom
Date:Sheet of
U15
VSS
U16
VSS
U23
VSS
U4
VSS
U8
VSS
V15
VSS
A10
VSS
A16
VSS
A2
VSS
A22
VSS
A29
VSS
AA27
VSS
AA30
VSS
AB1
VSS
AB23
VSS
AB24
VSS
AB4
VSS
AB7
VSS
AB8
VSS
AC12
VSS
AC14
VSS
AC16
VSS
AC18
VSS
AC27
VSS
AC4
VSS
AD12
VSS
AD16
VSS
AD18
VSS
AD25
VSS
AD30
VSS
AE26
VSS
AE28
VSS
AG11
VSS
AG16
VSS
AG18
VSS
AG21
VSS
AG5
VSS
AG7
VSS
AJ1
VSS
AJ30
VSS
AK2
VSS
AK29
VSS
B3
VSS
C1
VSS
C28
VSS
C30
VSS
C4
VSS
D12
VSS
D13
VSS
D15
VSS
D18
VSS
D21
VSS
D24
VSS
D25
VSS
D27
VSS
D5
VSS
D7
VSS
D9
VSS
E4
VSS
E6
VSS
V16
VSS
V27
VSS
V30
VSS
W15
VSS
W16
VSS
R9200L-64TD 81-105-L31020
1
414Monday, October 20, 2003
1.0
8
DD
Regulator for VDDC (ASIC Core)
7
Vin = 3.3V AGP
6
5
Cout1
4
470uF thru hole capacitor (P/N 4051047700)
3
2
1
has 30mR ESR where as 470uF SMT (P/N
4262047700) capacitor has 150mR ESR. For current below 4.5A, 1 thru 470uF is enough.
Vout = 1.5V ~ 1.62V Iout = 4A MAX (load consumption) Iout = 2.5A MAX (Power rail consumption)
***
Indicate number of via required for the connection
+3.3V_BUS
***
21
D12
1N5400
21
These dummy resistors are placed under the diodes to avoid PCB heat
D13
damage due to hot diodes.
1N5400
CC
+3.3V_BUS
R255 33_0805
C105 1uF
BB
AA
8
7
REG27
*
431L
1
3 2
*
*
6
R257 249_1%
R258 DNI
1uF_0805
+12V_BUS
C104
**
84
3
+
2
-
U28A LM358
SO8
*
VREF1256
1
5
C103
0.1uF R254
0_0805
4
C102
1.0uF
Q21 MTD3055V
32
1
***
C101 470uF_16V
***
R253
1.07K_1%
R256
3.48K_1%
*
R554 0R
******
C106A
C106
DNI
DNI
***
COPPER
4
R553 0R
***
C107 1000uF_10V
R552 0R
C107A
DNI
3
R551 0R
+VDDC
**
**
C108 10uF_10V
ATI Technologies Inc.
1 Commerce Valley Drive East Markham, Ontario Canada, L3T 7N6 (905) 882-2600
Title SizeDocument NumberRev
B
Date:Sheet of
2
R9200L-64TD 81-105-L31010
514Monday, October 20, 2003
1
1.0
8
7
6
5
4
3
2
1
Regulator for VDDC_CT (Core Transform)
and AVDD/A2VDDQ/AVDDDI/A2VDDDI
TXVDDR, LVDDRx, MPVDD
Vin = 3.3V AGP Vout = 1.8V Iout = 350mA + 100mA + 50mA = 500mA MAX
DD
CC
BB
Iout = 600mA MAX (with PVDD/TPVDD)
Rct1Rct2 1K3240100100
1.9V
IN3OUT
C131 100nF
X7R
Regulator for PVDD (Core PLLs)
and optional TPVDD (TMDS PLLs)
Vin = 3.3V AGP Vout = +1.8V Iout = 25mA MAX (PVDD only) Iout = 30mA MAX (PVDD + TPVDD)
+3.3V_BUS +VDDC_CT
3 2
The value of resistor were chosen to reduce failure rate caused by possible defective regulators, i.e., 33R are used instead of 47R or 51R for more start up current. (3.465V - 1.8V) / 33R = 50.5mA
805 package resistor are required for sufficient power rating (0.1W rating). (3.465V - 1.8V) * 50.5mA = 0.085W; therefore, smaller resistor value would require 1206 package
LT1117CST
ADJ
1
R284 DNI/33R
REG25
1 DNI/AS432S PVDD
REG22
CASE
Rvdd
Rvdd
422R1.8V
603
499R3240499000603
+VDDC_CT+3.3V_BUS
2 4
+PVDD
R287 DNI/681R 1% PVDD
R290 DNI/1.5K 1% PVDD
3240422000 603
C126 47uF_6.3V
R282
1.00K
Rct1
1%
R278
Rct2
422R
442--->R9200L-128TD
1%
B23 200R PVDD_VDDC18
4
NC
1
NC
2
5 3
GND_PVSS
MRG25 SC431LC5SK-1
ALT
C1207 100nF
AVDD/A2VDDQ (1st DAC & 2nd DAC Band Gap)
AA
8
7
Regulator for MVDDQ (MEM IO)and VDDR1
Vin = 3.3V AGP Vout = 2.5V (TSOP) Iout = 1200mA MAX Iout = 1000mA Est. MAX
Q25 Pin2/4 should be soldered to board for heat dissipation and a GND fill area.
C130
DNI/47uF_6.3V
C132 100nF
X7R
REG23
431L
1
3 2
Regulator for MPVDD (Memory PLLs)
Vin = 3.3V AGP Vout = +1.8V Iout = 10mA MAX
(Optional)
R288 DNI/681R 1% MPVDD
R291
1.5K 1% MPVDD
+AVDD +A2VDDQ+VDDC_CT
+VDDC_CT
B24 200R MPVDD_VDDC18
4
NC
1
NC
2
5 3
GND_MPVSS
B29200R
5
MRG26 SC431LC5SK-1
ALT
COMMON
6
+3.3V_BUS +MPVDD
R285 DNI/33R
Rvdd
REG26
1 DNI/AS432S MPVDD
3 2
Rvdd
B27200R
COMMON
+3.3V_BUS
4
1
Q25 MTD3055V
32
R281 2K
C1208 100nF
+MVDDQ
+12V_BUS
C136 100nF
5 3
MRG23 SC431LC5SK-1
4
NC
1
NC
ALT
2
/.25W
R277 470R
R279
4.75K_1%
Rq1
R283
4.64K_1%
Rq2
Regulator For TPVDD (TMDS PLLs)
Vin = +3.3V AGP Vout = 1.8V Iout = 15mA MAX
TPVDD = TPVDD + LPVDD + TXVDDR
Regulator for TPVDD (TMDS PLLs)
Vin = 3.3V AGP Vout = +1.62V Iout = 10mA MAX 15mA Estimeatd MAX
+3.3V_BUS
R1325 33R
Rvdd
REG29 431L
1
+TPVDD
3 2
Rvdd
4
Placed close to +MVDDQ output for EMI
+MVDDQ
C127 330uF_6.3V
+TPVDD
R1326 432R_1%
TPVDD R1327
1.4K_1% TPVDD
C133 100nF
X7R
(Optional)
+VDDC_CT+TPVDD
C1259 100nF
GND_TPVSS
TPVDD might not be needed if PVDD can provide stable 1.8V
B25 DNI/200R TPVDD_PVDD
Regulator for MVDDC
Vin = 5V Vout = 3.4V 2A MAX
+5V_BUS
**
C1035
DNI/22uF_16V
**
Placed close to +VDDC output for EMI
VREF1255
3
+3.3V_BUS
SP1
1 2
DNI
U97AMS1085_TO252
C1036 100nF
DNI/47uF_6.3V
3
C1214
2
IN
OUT
ADJ
1
C1037
0.1uF
C1033
DNI/100nF
R958 121_1%
R960 191_1%
+MVDDQ +MVDDC
1 2
Regulator For A2VDD (2nd DACs)
Vin = +3.3V AGP Vout = 2.5V Iout = 150mA MAX
+3.3V_BUS
Q2
2N2222
C139 100nF
U28B
5
+
7
6
-
LM358
A2VDD and A2VSSN routed with at least 15 mil trace and not longer than 1.5 inch. A2VSSN with signle via to GND at the regulator
<Variant Name>
Title SizeDocument NumberRev Date:Sheet of
2
+A2VDD
23
1
R259 0
R260
1.02K_1%
R261
1K_1%
GND_A2VSSN
ATI Technologies Inc.
1 Commerce Valley Drive East Markham, Ontario Canada, L3T 7N6 (905) 882-2600
Custom
A2VDD might not be needed if VDD can provide stable 2.5V
C138
0.1uF
+MVDDC
****
C1034 330uF_6.3V
****
C119 DNI/22uF_16V
COPPER
SP2
DNI
3
2N2222
2
1
Some Part Ref's updated to 988 brd
R9200L-64TD
81-105-L31020
614Tuesday, November 25, 2003
1
1.0
8
7
6
5
4
3
2
1
+3.3V_BUS
GPIO[13..0]2,8
DD
GPIO[13..0]
GPIO0
GPIO1
GPIO2
STRAP G
STRAP H
STRAP J
R201DNI/10KDNI R20210K R203DNI/10KDNI R20410K R205DNI/10KDNI
STRAPS
AGPFBSKEW(1:0)
PIN
GPIO(1:0)
R20610K
GPIO3
STRAP K
R207DNI/10KDNI
X1CLK_SKWE(1:0)
GPIO(3:2)
R20810K
GPIO11
GPIO12
STRAP L
STRAP M
R20910K R210DNI/10K R21110K
ROMIDCFG(3:0)
GPIO(9,13:11)
R212DNI/10K
GPIO13
STRAP N
R213DNI/10K R21410K
GPIO9
STRAP O
CC
GPIO8
STRAP A
R21510K R216DNI/10K
R217DNI/10K
ID_DISABLE
GPIO(8)
R21810K
GPIO4
STRAP D
R219DNI/10K
BUSCFG(2:0)
GPIO(6:4)
R22010K
GPIO5
STRAP E
R221DNI/10K R22210K
GPIO6
STRAP F
R223DNI/10K R22410K
GPIO7
STRAP B
BB
LCDDATA162
LCDDATA172
LCDDATA202
STEREOSYNC2
STRAP R
STRAP S
STRAP T
STRAP P
Mem_Strap02
AA
Mem_Strap12
Mem_Strap22
8
7
R225DNI/10K R22610K
R227DNI/10K R22810K R22910K R230DNI/10K
R23110K R232DNI/10K
R233DNI/10K R23410K
R235DNI/10K R23610K R237DNI/10K R23810K R239DNI/10K R24010K
6
VGA_DISABLE
MULTIFUNC(1:0)
VIP_DEVICE
GPIO(7)
LCDDATA(17:16)
LCDDATA(20) STRAP T
STRAP P INTERRUPT
LOW
ENABLED (DEFAULT)
DISABLED
HIGH
5
4
OPTION STRAPS
DESCRIPTION
AGP 1x clock feedback phase adjustment wrt refclk(cpuclk)
00 - refclk slightly earlier then feedback
01 - refclk 1 tap earlier then feedback 10 - refclk 1 tap later then feedback 11 - refclk 2 taps earlier then feedback clock
Clock phase adjustment between x1 clk and x2clk
00 - 0 tap delay
01 - 1 tap delay 10 - 2 taps delay 11 - 3 taps delay
If no ROM attached, comtrols chip IDis. If rom attached identifies ROM type 0000 - No ROM, CHG_ID=0 0001 - No ROM, CHG_ID=1 0100 - reserved 0110 - reserved 1000 - Parallel ROM, chip IDis from ROM 1001 - Serial AT25F1024 ROM (Atmel), chip IDis from ROM 1010 - Serial AT45DB011 ROM (Atmel), chip IDis from ROM
1011 - Serial M25P05/10 ROM (ST), chip IDis from ROM
1100 - Reserved 1100 - Serial NX25F011B ROM (ISSI), chip IDis from ROM
0 - Normal operation
1 - Shuts the chip down by not responding to any config cycles In a system with two graphics chips, one on the motherboard, the other on add-in card, the strap can be used to disable one of the two throught a jumper.
Controls bus type, CLK PLL select, and IDSEL
000 - 1.5V BUS -> AGP 4x, PLL clk, IDSEL=AD16
000 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD16 001 - 1.5V BUS -> AGP 4x, PLL clk, IDSEL=AD17 001 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD17 010 - 1.5V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD16 010 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD16 011 - 1.5V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD17 011 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD17 100 - PCI 66MHz, PLL clk 101 - PCI 33MHz, 3.3v, REF clk 110 - 1.5V BUS -> AGP 1x, REF clk, IDSEL=AD16 110 - 3.3V BUS -> AGP 1x, REF clk, IDSEL=AD16 111 - 1.5V BUS -> AGP 1x, REF clk, IDSEL=AD17 111 - 3.3V BUS -> AGP 1x, REF clk, IDSEL=AD17 Note that for AGP configurations GPIO(4) acts as the IDSEL strap. For PCI it acts as the PLL bypass (33 or 66MHz) strap.
0 - VGA controller capabillity enabled.
1 - The device will not be recognized as the systemis VGA controller.
Multi-function device select 00 - single function device. 01 - two function device. No AGP in either function
10 - two function device. AGP only in function 0
11 - two function device. AGP in both functions If BUSCFG pin based straps are set to PCI, then AGP will not be enabled in any function. See AGP function table below for detail on AGP ability claims.
Indicates if any slave VIP host devices drove this in low during reset.
0 - Slave VIP host port devices present
1 - No slave VIP host port devices reporting presence during reset
<Variant Name>
ATI Technologies Inc.
1 Commerce Valley Drive East Markham, Ontario Canada, L3T 7N6 (905) 882-2600
Title SizeDocument NumberRev
B
Date:Sheet of
3
R9200L-64TD 81-105-L31020
2
DEFAULT
00 (internal pull-down)
00 (internal pull-down)
1100
0 (internal pull-down)
000 (internal pull-down)
0
10
0
714Monday, October 20, 2003
1
1.0
8
7
6
5
4
3
2
1
SERIAL EEPROM BIOS
DD
ROMCS#2 GPIO[13..0]2,7
CC
ROMCS#
GPIO[13..0]
GPIO9 GPIO10
+3.3V_BUS
C80 100nF
X7R
U11
5 6 1 7 3 8
PM25LV512-25SC
D C S HOLD W VCC
VSS
M25P05-VMN6T
Q
GPIO8
2
4
+3.3V_BUS
Daughter Card Straps
R58210K R578DNI/10K R57410K
BB
DC_Strap52,13 DC_Strap32 DC_Strap42 DC_Strap12
R575DNI/10K R579DNI/10K R583DNI/10K
R58410K R58010K R576DNI/10K
DC_Strap22
R57710K R581DNI/10K R585DNI/10K
+3.3V_BUS
PAL/NTSC2
STRAPS
DC_STRAP1LCDDATA12
DC_STRAP2LCDDATA13
DC_STRAP4LCDDATA15DAC2 ConfigurationDC_STRAP5LCDDATA19
PIN
00 01 1 11
0
DESCRIPTION
Internal TMDS Enabled
0 - Disabled
1 - Enabled
Video Capture Enabled
0 - Disabled
1 - Enabled
DAC2 Off DAC2 On as CRT DAC2 On as TVOUT DAC2 On as TVOUT and CRT
DC_STRAP6LCDDATA18TVO Standard Default (Resistor pull-up and switch short to GND)
0 - PAL (on board resistor pull-down and switch closed) 1 -NTSC (on board resistor pull-up)
AA
8
7
6
5
4
3
ATI Technologies Inc.
1 Commerce Valley Drive East Markham, Ontario Canada, L3T 7N6 (905) 882-2600
Title SizeDocument NumberRev
B
Date:Sheet of
2
R9200L-64TD 81-105-L31020
814Monday, October 20, 2003
1
1.0
5
4
3
2
1
TERMINATION FOR MEMORY CHANNEL A
DD
CC
Proper Termination of QSA?
MDA[63..0]
MDA0
RP117D56R
MDA1
RP117C56R
MDA2
RP117B56R
MDA3
RP117A56R
MDA4
RP118D56R
MDA5
RP118C56R
MDA6
RP118B56R
MDA7
RP118A56R
MDA8
RP119D56R
MDA9
RP119C56R
MDA10
RP119B56R
MDA11
RP119A56R
MDA12
RP120A56R
MDA13
RP120B56R
MDA14
RP120C56R
MDA15
RP120D56R
MDA16
RP121D56R
MDA17
RP121C56R
MDA18
RP121B56R
MDA19
RP121A56R
MDA20
RP122D56R
MDA21
RP122C56R
MDA22
RP122B56R
MDA23
RP122A56R
MDA24
RP123A56R
MDA25
RP123B56R
MDA26
RP123C56R
MDA27
RP123D56R
MDA28
RP124D56R
MDA29
RP124C56R
MDA30
RP124B56R
MDA31
RP124A56R
MDA32
RP127A56R
MDA33
RP127B56R
MDA34
RP127C56R
MDA35
RP127D56R
MDA36 M_MDA36
RP128A56R
MDA37
RP128B56R
MDA38
RP128C56R
MDA39
RP128D56R
MDA40
RP125D56R
MDA41
RP125C56R
MDA42 M_MDA42
RP125B56R
MDA43
RP125A56R
MDA44
RP126D56R
MDA45
RP126C56R
MDA46
RP126B56R
MDA47
RP126A56R
MDA48
RP129A56R MDA49 MDA50
RP129C56R MDA51
RP129D56R MDA52
RP130A56R MDA53
RP130B56R MDA54
RP130C56R MDA55
RP130D56R MDA56
RP131A56R MDA57
RP131B56R MDA58
RP131C56R MDA59
RP131D56R MDA60
RP132D56R MDA61
RP132C56R MDA62
RP132B56R MDA63
QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7
RP132A56R
R7590R R7600R R7610R R7620R R7640R R7630R R7650R R7660R
QSA[7..0]
QSA[7..0]3 M_QSA[7..0]10
5 4 6 3 7 2 8 1
5 4 6 3 7 2 8 1 8 1 7 2 6 3 5 4 8 1 7 2 6 3 5 4 5 4 6 3 7 2 8 1 5 4 6 3 7 2 8 1 8 1 7 2 6 3 5 4 8 1 7 2 6 3 5 4
5 4 6 3 7 2 8 1
M_MDA0
54
M_MDA1
63
M_MDA2
72
M_MDA3
81
M_MDA4
54
M_MDA5
63
M_MDA6
72
M_MDA7
81
M_MDA8 M_MDA9 M_MDA10 M_MDA11 M_MDA12
81
M_MDA13
72
M_MDA14
63
M_MDA15
54
M_MDA16
54
M_MDA17
63
M_MDA18
72
M_MDA19
81
M_MDA20
54
M_MDA21
63
M_MDA22
72
M_MDA23
81
M_MDA24
81
M_MDA25
72
M_MDA26
63
M_MDA27
54
M_MDA28 M_MDA29 M_MDA30 M_MDA31 M_MDA32 M_MDA33 M_MDA34 M_MDA35
M_MDA37 M_MDA38 M_MDA39 M_MDA40 M_MDA41
M_MDA43 M_MDA44 M_MDA45 M_MDA46 M_MDA47 M_MDA48 M_MDA49 M_MDA50 M_MDA51 M_MDA52 M_MDA53 M_MDA54 M_MDA55 M_MDA56
81
M_MDA57
72
M_MDA58
63
M_MDA59
54
M_MDA60 M_MDA61 M_MDA62 M_MDA63
M_MDA[63..0]
SERIES Resistors
M_QSA0 M_QSA1 M_QSA2 M_QSA3 M_QSA4 M_QSA5 M_QSA6 M_QSA7
M_MDA[63..0]10MDA[63..0]3
For Bi-Directional signals, Series resistors should be placed close to the memory
M_QSA[7..0]
CLOCK terminations
Change from 1:1 spacing to at least a
2.5:1 spacing between the pair
These resistors and caps must be placed to minimize any stubs. These must also be placed after the memory
CLKA03,10
CLKA#03,10
CLKA13,10
CLKA#13,10
M_CLKA0
M_CLKA03,10
M_CLKA#0
M_CLKA#03,10
M_CLKA1
M_CLKA13,10
M_CLKA#1
M_CLKA#13,10
R797 56R
R798 56R
R799 56R
R800 56RRP129B56R
C778 10nF
C779 10nF
M_DQMA#[7..0]
M_DQMA#[7..0]10
BB
M_MAA[13..0]
M_MAA[13..0]10
M_RASA#10
M_CASA#10
M_WEA#10 M_CSA#010 M_CSA#110
M_CKEA10
AA
5
4
M_RASA# M_CASA# M_WEA# M_CSA#0 M_CSA#1 M_CKEA
M_DQMA#0 M_DQMA#1 M_DQMA#2 M_DQMA#3 M_DQMA#4 M_DQMA#5 M_DQMA#6 M_DQMA#7
M_MAA0 M_MAA1 M_MAA2 M_MAA3 M_MAA4 M_MAA5 M_MAA6 M_MAA7 M_MAA8 M_MAA9 M_MAA10 M_MAA11 M_MAA12 M_MAA13
R77556R R77656R R77756R R77856R R78056R R77956R R78156R R78256R
RP137A0R
8 1
RP137B0R
7 2
RP137C0R
6 3
RP137D0R
5 4 RP138C0R RP138B0R RP138A0R RP139A0R RP139B0R RP139C0R RP138D0R RP139D0R RP140C0R RP140D0R
RP142B0R RP142C0R RP142D0R RP142A0R RP140A0R RP140B0R
8 1
7 2
6 3
5 4
63 72 81
54 63
54
72 63 54 81 81 72
DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7
MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13
RASA#3 CASA#3 WEA#3 CSA#03 CSA#13 CKEA3
DQMA#[7..0]
MAA[13..0]
3
DQMA#[7..0]3
MAA[13..0]3
For Uni-Directional signals, Series resistors should be placed close to the ASIC
<Variant Name>
2
ATI Technologies Inc.
1 Commerce Valley Drive East Markham, Ontario Canada, L3T 7N6 (905) 882-2600
Title SizeDocument NumberRev
Custom
Date:Sheet of
R9200L-64TD 81-105-L31020
1
914Monday, October 20, 2003
1.0
8
M_DQMA#[7..0]9
DD
M_QSA[7..0]9
CC
M_MAA[13..0]9
BB
M_DQMA#[7..0]
M_QSA[7..0]
M_CLKA#03,9 M_CLKA#13,9
M_CLKA03,9 M_CLKA13,9
M_CKEA9 M_WEA#9 M_CASA#9 M_RASA#9 M_CSA#09 M_CSA#19
M_MAA[13..0]
M_DQMA#0 M_DQMA#1 M_DQMA#2 M_DQMA#3 M_DQMA#4 M_DQMA#5 M_DQMA#6 M_DQMA#7
M_QSA0 M_QSA1 M_QSA2 M_QSA3 M_QSA4 M_QSA5 M_QSA6 M_QSA7
M_CLKA0# M_CLKA1#
M_CLKA0 M_CLKA1
M_CKEA M_WEA# M_CASA#0 M_RASA#0 M_CSA#0 M_CSA#1
M_MAA0 M_MAA1 M_MAA2 M_MAA3 M_MAA4 M_MAA5 M_MAA6 M_MAA7 M_MAA8 M_MAA9 M_MAA10 M_MAA11 M_MAA12 M_MAA13
M_MDA[63..0]9
7
U29
C418
49
VREF
100nF M_MAA0
29
A0
M_MAA1
30
A1
M_MAA2
31
A2
M_MAA3
32
A3
M_MAA4
35
A4
M_MAA5
36
A5
M_MAA6
37
A6
M_MAA7
38
A7
M_MAA8
39
A8
M_MAA9
40
A9
M_MAA10
28
A10/AP
M_MAA11
41
A11
M_CLKA0
45
M_CSA#0 M_RASA#0 M_CASA#0 M_WEA#
M_QSA3 M_QSA1
M_DQMA#3 M_DQMA#1
M_MAA13 M_MAA12
+VREF_U33
M_MAA0 M_MAA1 M_MAA2 M_MAA3 M_MAA4 M_MAA5 M_MAA6 M_MAA7 M_MAA8 M_MAA9 M_MAA10 M_MAA11
M_CSA#0 M_RASA#0 M_CASA#0 M_WEA#
M_QSA0 M_QSA2
M_DQMA#0 M_DQMA#2
M_MAA13 M_MAA12
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
1MX16X4 64MB U33
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
1MX16X4 64MB
M_CLKA#0 M_CKEA
+MVDDQ +MVDDQ
C566 100nF
M_CLKA0 M_CLKA0# M_CKEA
6
M_MDA31 M_MDA63
2
DQ0
M_MDA30
4
DQ1
M_MDA29
5
DQ2
M_MDA28
7
DQ3
M_MDA27
8
DQ4
M_MDA26
10
DQ5
M_MDA25
11
DQ6
M_MDA24
13
DQ7
M_MDA15
54
DQ8
M_MDA14
56
DQ9
M_MDA13
57
DQ10
M_MDA12
59
DQ11
M_MDA11
60
DQ12
M_MDA10
62
DQ13
M_MDA9
63
DQ14
M_MDA8
65
DQ15
14
NC
17
NC
19
NC
25
NC
M_CSA#1 M_CSA#1
42
NC
43
NC
+MVDDC +MVDDC
50
NC
53
NC
1
VDD
+MVDDQ
18
VDD
33
VDD
3
VDDQ
9
VDDQ
15
VDDQ
55
VDDQ
61
VDDQ
34
VSS
48
VSS
66
VSS
6
VSSQ
12
VSSQ
52
VSSQ
58
VSSQ
64
VSSQ
M_MDA0
2
DQ0
M_MDA1
4
DQ1
M_MDA2
5
DQ2
M_MDA3
7
DQ3
M_MDA4
8
DQ4
M_MDA5
10
DQ5
M_MDA6
11
DQ6
M_MDA7
13
DQ7
M_MDA16
54
DQ8
M_MDA17
56
DQ9
M_MDA18
57
DQ10
M_MDA19
59
DQ11
M_MDA20
60
DQ12
M_MDA21
62
DQ13
M_MDA22
63
DQ14
M_MDA23
65
DQ15
14
NC
17
NC
19
NC
25
NC
42
NC
43
NC
50
NC
53
NC
1
VDD
+MVDDQ
18
VDD
33
VDD
3
VDDQ
9
VDDQ
15
VDDQ
55
VDDQ
61
VDDQ
34
VSS
48
VSS
66
VSS
6
VSSQ
12
VSSQ
52
VSSQ
58
VSSQ
64
VSSQ
+VREF_U30+VREF_U29
C420 100nF
M_MAA0 M_MAA1 M_MAA2 M_MAA3 M_MAA4 M_MAA5 M_MAA6 M_MAA7 M_MAA8 M_MAA9 M_MAA10 M_MAA11
M_CLKA1 M_CLKA1# M_CKEA
M_CSA#0 M_RASA#0 M_CASA#0 M_WEA#
M_QSA7 M_QSA5
M_DQMA#7 M_DQMA#5
M_MAA13 M_MAA12
C569 100nF
+VREF_U34
M_MAA0 M_MAA1 M_MAA2 M_MAA3 M_MAA4 M_MAA5 M_MAA6 M_MAA7 M_MAA8 M_MAA9 M_MAA10 M_MAA11
M_CLKA1 M_CLKA1# M_CKEA
M_CSA#0 M_RASA#0 M_CASA#0 M_WEA#
M_QSA4 M_QSA6
M_DQMA#4 M_DQMA#6
M_MAA13 M_MAA12
5
Channel A Bottom UpChannel A Bottom Down
U30
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
1MX16X4 64MB U34
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
1MX16X4 64MB
Channel A Top UpChannel A Top Down
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
VDDQ VDDQ VDDQ VDDQ VDDQ
VSSQ VSSQ VSSQ VSSQ VSSQ
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
VDDQ VDDQ VDDQ VDDQ VDDQ
VSSQ VSSQ VSSQ VSSQ VSSQ
2
DQ0
M_MDA62
4
DQ1
M_MDA61
5
DQ2
M_MDA60
7
DQ3
M_MDA59
8
DQ4
M_MDA58
10
DQ5
M_MDA57
11
DQ6
M_MDA56
13
DQ7
M_MDA47
54
DQ8
M_MDA46
56
DQ9
M_MDA45
57
M_MDA44
59
M_MDA43
60
M_MDA42
62
M_MDA41
63
M_MDA40
65 14
NC
17
NC
19
NC
25
NC
42
NC
43
NC
50
NC
53
NC
1
VDD
+MVDDQ
18
VDD
33
VDD
3 9 15 55 61
34
VSS
48
VSS
66
VSS
6 12 52 58 64
M_MDA32
2
DQ0
M_MDA33
4
DQ1
M_MDA34
5
DQ2
M_MDA35
7
DQ3
M_MDA36
8
DQ4
M_MDA37
10
DQ5
M_MDA38
11
DQ6
M_MDA39
13
DQ7
M_MDA48
54
DQ8
M_MDA49
56
DQ9
M_MDA50
57
M_MDA51
59
M_MDA52
60
M_MDA53
62
M_MDA54
63
M_MDA55
65 14
NC
17
NC
19
NC
25
NC
M_CSA#1M_CSA#1
42
NC
43
NC
+MVDDC+MVDDC
50
NC
53
NC
1
VDD
+MVDDQ
18
VDD
33
VDD
3 9 15 55 61
34
VSS
48
VSS
66
VSS
6 12 52 58 64
4
DDR SDRAM 64Mbit 1Mx16x4
+MVDDQ+MVDDQ
+MVDDQ
R60
5.1K
R61
5.1K
R68
5.1K
+VREF_U33
R69
5.1K
+MVDDQ
R62
5.1K
+VREF_U30+VREF_U29
R63
5.1K
R70
5.1K
+VREF_U34
R71
5.1K
3
2
1
Put 1 1uF cap per power pin of memory
C573 100nF
C593 100nF
C574 100nF
C594 100nF
+MVDDC
+MVDDC
+MVDDQ
C575 100nF
C595 100nF
C221 100nF
C576 100nF
C596 100nF
C222 100nF
+MVDDQ
+MVDDQ
C577 100nF
C597 100nF
C223 100nF
6
C578 100nF
C598 100nF
C224 100nF
+MVDDQ
C572 100nF
C232 100nF
C235 100nF
+MVDDQ
C592 100nF
7
2 capacitors SHOULD BE PLACED CLOSE TO THE REFERENCE LAYER CHANGE OF CLOCKS FOR
AA
EMI REDUCE.
Place as many as possible.
+MVDDC
C231 100nF
8
C579 100nF
C599 100nF
C580 100nF
C600 100nF
+MVDDC
+MVDDC
C581
100nF
C601
100nF
+MVDDQ
C237 100nF
DATA GROUP SHOULD BE ASSIGNED TO EACH DQS AND DQM ACCORDINGLY AND THIS MAPPING IS JUST FOR PLACEMENT AND ROUTING REASONS
All +VDD_MEM_IO and +VDD decoupling caps should be equally distributed per memory chip. As close to the pin as possible.
<Variant Name>
C238
C239
C240
100nF
100nF
5
100nF
C243 100nF
4
3
ATI Technologies Inc.
1 Commerce Valley Drive East Markham, Ontario Canada, L3T 7N6 (905) 882-2600
Title SizeDocument NumberRev
C
Date:Sheet of
2
Some Part Ref's updated to 988 brd
R9200L-64TD 81-105-L31020
1014Monday, October 20, 2003
1
1.0
8
DD
7
6
5
OPTIONAL ESD/HOTPLUG PROTECTION DIODES
4
3
+5V_BUS
2
1
C410
DNI/5pF
B14 DNI/82nH
1 2
+5V_BUS +5V_BUS
BAT54SLT1
D4
DNI
3
C406 DNI/5pF
B13 DNI/82nH
1 2
BAT54SLT1
2
DNI
1
C736 DNI
BAT54SLT1
2
D5
3
1
C737 DNI
2
D8
DNI
3
1
C738 DNI
Place close to CONNECTOR
BAT54SLT1 DNI
C739 DNI
+5V_BUS+5V_BUS
D9
3
F1 750mA
Resettable fuse
2
1
B626R
Close to Connector
C402 68pF
+5V_DIN14
+5V_DIN_CNCR
GND_CHASSIS
J4
1
R
2
G
3
B
11
MS0
12
MS1
4
MS2
15
MS3
9
NC
13
HS
14
VS
5
VSS
6
VSS
7
VSS
8
VSS
10
VSS
16
CASE
Header 2x8
DDC2_MONID0 DDC2_MONID1(SDA) DDC2_MONID2 DDC2_MONID3(SCL)
PRIMARY CRT
Place close to ASIC
B782nH
A_R_DAC12 A_G_DAC12
A_B_DAC12
R1258
R1260
R1259
75.0R
75.0R
75.0R
CC
+3.3V_BUS
R416
CRT1DDCDATA2
CRT1DDCCLK2
BB
A_HSYNC_DAC12
A_VSYNC_DAC12
4.7K
+3.3V_BUS
R417
4.7K
C404
DNI/3.3pF
DNI/3.3pF
1
32
BSN20 Q3
1
32
BSN20 Q4
5
6
4
U6B SN74ACT86D
10
8
9
U6C SN74ACT86D
1 2
B982nH
1 2
B1182nH
1 2
C412
C408
DNI/3.3pF
+5V_BUS
R400
6.8k DDCDATA_DAC1_5V
+5V_BUS
R399
6.8k
DDCCLK_DAC1_5V
A_HSYNC_DAC1_B
A_VSYNC_DAC1_B A_VSYNC_DAC1_R
C413
C409
5pF
5pF
R52033R
R52133R
R88551R
R88451R
B882nH
1 2
B1082nH
1 2
B1282nH
1 2
C405 5pF
B52
0_0805
B53
0_0805
B54
0_0805
B55
0_0805
DDCDATA_DAC1_R
DDCCLK_DAC1_R
A_HSYNC_DAC1_R
+3.3V_BUS +3.3V_BUS +3.3V_BUS
BAT54SLT1
2
D3
DNI
3
1
DDCDATA_DAC1_R DDCCLK_DAC1_R A_HSYNC_DAC1_R
A_VSYNC_DAC1_R
Change these inductors to 0R for EMI
BAT54SLT1 DNI
BAT54SLT1
2
DNI
D2
3
1
DNI/82nH
2
D1
3
1
C414
DNI/5pF
B15
1 2
GND_CHASSIS
R4110R
805 805 805 805 805 805
GND_CHASSIS
Three on top side, three at the bottom, spreaded high, middle and low vertically
7
<Variant Name>
6
5
4
3
ATI Technologies Inc.
1 Commerce Valley Drive East Markham, Ontario Canada, L3T 7N6 (905) 882-2600
Title SizeDocument NumberRev
C
Date:Sheet of
2
R9200L-64TD 81-105-L31020
1114Monday, October 20, 2003
1
1.0
R4120R R4130R R4140R R4150R R4180R
AA
8
8
7
6
5
4
3
2
1
Place Resistors close to ASIC.
DD
CC
BB
A_Y_DAC213
A_C_DAC213
A_COMP_DAC213
A_Y_DAC2
R1257
75.0R
A_C_DAC2 A_C_DAC2_FA_C_DAC2_F
R1256
75.0R
A_COMP_DAC2
R1255
75.0R
L201.8uH
C550 82pF
GND_CHASSIS
L211.8uH
C552 82pF
GND_CHASSIS
L221.8uH
C554 82pF
GND_CHASSIS
A_HSYNC_DAC22,13
C551 82pF
C553 82pF
C555 82pF
A_Y_DAC2_F
Cm3
Cm4
A_COMP_DAC2_F
Cm5
1 2
+5V_BUS
53
C18 DNI/100nF
X7R
A_HSYNC_DAC2_B
4
U3
DNI/TC7SZ08FU
A_Y_DAC2_F A_COMP_DAC2_F
R308DNI/330R
Rx
HSync to ConnectorRx = 330R, Rcx = 470pF, Ux INSTALL
Place near connector 0R leaves footprint for Ferrite Beads if req'd for EMI
R5190R R12660R R12670R
Rcx
C435 DNI/470pF DNI
A_Y_DAC2_DIN A_C_DAC2_DIN
Rx = DNI, Rcx = 0R, Ux = DNIHSync NOT Connected
Add alternate part for 7 pin Svideo 6071001500
TV Out (SVHS)
J6
+12V
6
Y
5 7
C SDA
6
SCK
4
GND
1 2
GND CASE
10 11
CASE CASE
12
Connector_DIN_Miniature_Circular_7_Pin
PIN1 PIN2
GND_CHASSIS
PIN7A_COMP_DAC2_DIN PIN5
Ux
<Variant Name>
AA
8
7
6
5
4
3
ATI Technologies Inc.
1 Commerce Valley Drive East Markham, Ontario Canada, L3T 7N6 (905) 882-2600
Title SizeDocument NumberRev
Custom
Date:Sheet of
2
R9200L-64TD 81-105-L31020
1214Monday, October 20, 2003
1
1.0
8
7
6
5
4
3
2
1
BAT54SLT1
BAT54SLT1
SECONDARY CRT
DD
U96
1
SEL
2
1A0
3
1A1
5
1B0
6
1B1 1C0 1C1101D0 E
PI5V330
A_R_DAC2_F1 A_G_DAC2_F2 A_B_DAC2_F3
C454 5pF
+5V_BUS
16
VCC
4
YA
7
YB
9
YC
12
YD
13
1D1
14 8
GND
L7482nH L7582nH L7682nH
C456
C455
5pF
5pF
C735 100nF
1 2 1 2 1 2
L7182nH
1 2
L7282nH
1 2
L7382nH
1 2
C452
C451
DNI/3.3pF
R45175.0R R45275.0R R45375.0R
CC
BB
A_R/C_DAC22 A_G/Y_DAC22
A_B/COMP_DAC22
DC_Strap52,8
A_B_DAC2 A_G_DAC2
A_R_DAC2
DNI/3.3pF
C453 DNI/3.3pF
11 15
Place close to connector DVI1
A_R_DVI-I A_G_DVI-I A_B_DVI-I
DDCDATA_DVI-I_R DDCCLK_DVI-I_R A_HSYNC_DVI-I_R
A_VSYNC_DVI-I_R
TO J6
A_C_DAC2 A_Y_DAC2 A_COMP_DAC2
A_C_DAC212 A_Y_DAC212 A_COMP_DAC212
2
D75
DNI
3
1
DVIDDCDATA2
DVIDDCCLK2
BAT54SLT1
2
D76
DNI
DNI
3
1
DNI/82nH
+3.3V_BUS +5V_BUS
R454
4.7K
+3.3V_BUS +5V_BUS
R456
4.7K
2
D77
3
1
C457 DNI/5pF
L81
L80
DNI/82nH
1 2
GND_CHASSIS
BAT54SLT1 DNI
C458 DNI/5pF
1 2
1
1
D71
3
C459 DNI/5pF
L82 DNI/82nH
1 2
32
BSN20 Q71
32
BSN20 Q72
BAT54SLT1
2
DNI
1
R455
6.8k
R457
6.8k
D72
C740 DNI
BAT54SLT1
2
D73
DNI
3
1
C741
C742
DNI
DNI
R458
B56
DDCDATA_DVI-I_R
0_0805
33R
B57
R459
33R
0_0805
DDCCLK_DVI-I_R
+5V_BUS+5V_BUS+3.3V_BUS+3.3V_BUS+3.3V_BUS +5V_BUS+5V_BUS
BAT54SLT1
2
2
D74
DNI
3
3
1
1
A_R_DVI-I14 A_G_DVI-I14
A_B_DVI-I14 DDCDATA_DVI-I_R14 DDCCLK_DVI-I_R14 A_HSYNC_DVI-I_R14
A_VSYNC_DVI-I_R14
C743 DNI
To DVI1
B58
+5V_BUS
147
3
R46051R
8
U7C SN74ACT86D
R46151R
11
U7D SN74ACT86D
SN74ACT86D U7A
3
0_0805
B59
0_0805
<Variant Name>
A_HSYNC_DVI-I_R
A_VSYNC_DVI-I_R
ATI Technologies Inc.
1 Commerce Valley Drive East Markham, Ontario Canada, L3T 7X6 (905) 882-2600
Title SizeDocument NumberRev
Custom
Date:Sheet of
2
R9200L-64TD 81-105-L31020
1314Monday, October 20, 2003
1
1.0
C1216
0.1uF
MODIFY
10
9
13 12
1 2
A_HSYNC_DAC22,12
A_VSYNC_DAC22
AA
8
7
6
5
4
5
4
3
2
1
INSTALL TERMINATION RESISTORS CLOSE TO ASIC
DD
TMDS_TX2N2 TMDS_TX2P2
TMDS_TX1N2 TMDS_TX1P2
TMDS_TX0N2 TMDS_TX0P2
CC
TMDS_TXCP2 TMDS_TXCN2
R1269330R
R1271330R
R1273330R
R1275330R
CHARGE_POW2
DDCCLK_DVI-I_R13 DDCDATA_DVI-I_R13
BB
INSTALL TERMINATION RESISTORS CLOSE TO CONNECTOR
R1268DNI/330R
TMDS
R1270DNI/330R
TMDS
R1272DNI/330R
TMDS
R1274DNI/330R
TMDS
D78
2.4V
2 1
+5V_DIN11
A_VSYNC_DVI-I_R13
A_R_DVI-I13 A_G_DVI-I13 A_B_DVI-I13
A_HSYNC_DVI-I_R13
R127620K
R1277 100K TMDS
IF HOT PLUG DETECT IS NOT REQUIRED
REMOVE ALL THIS LOGIC EXCEPT
FOR 100K PULL DOWN
DDCCLK_DVI-I DDCDATA_DVI-I
B73226R
PRIMARY DVI-I CONNECTOR
C1209
1.0uF
GND_CHASSIS GND_CHASSIS
GND_CHASSIS
DVI1
M1
CASE
M3
CASE
1
TMDS Data2-
2
TMDS Data2+
3
TMDS Data2/4 Shield
4
TMDS Data4-
5
TMDS Data4+
6
DDC Clock
7
DDC Data
8
Analog VSYNC
9
TMDS Data1-
10
TMDS Data1+
11
TMDS Data1/3 Shield
12
TMDS Data3-
13
TMDS Data3+
14
+5V Power
15
GND (for +5V)
16
Hot Plug Detect
17
TMDS Data0-
18
TMDS Data0+
19
TMDS Data0/5 Shield
20
TMDS Data5-
21
TMDS Data5+
22
TMDS Clock Shield
23
TMDS Clock+
24
TMDS Clock-
C1
Analog Red
C2
Analog Green
C3
Analog Blue
C4
Analog HYNC
C5
Analog GND
C6
Analog GND
M4
CASE
M2
CASE
DVI_A/D
J7
1
R
2
G
3
B
11
MS0
12
MS1
4
MS2
15
MS3
9
NC
13
HS
14
VS
5
VSS
6
VSS
7
VSS
8
VSS
10
VSS
16
CASE
17
Slim_Connector_DB15_Female_VGA_Blue
CASE
<Variant Name>
AA
5
4
3
2
ATI Technologies Inc.
1 Commerce Valley Drive East Markham, Ontario Canada, L3T 7X6 (905) 882-2600
Title SizeDocument NumberRev
B
Date:Sheet of
R9200L-64TD 81-105-L31020
1414Monday, October 20, 2003
1
1.0
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