ECS R9200-64DV Schematics
8
VINGND
+12V_BUS
C10 place at the AGP connector
C10
DD
AGP_INTR#2
AGP_GNT#2
AGP_WBF#2
AGP_SB_STB#2
AGP_MB_8X_DET#2
AGP_DBI_HI2
AGP_RESET#2,12
CC
BB
AA
AGP_RESET#
AGP_AD_STB1#2
AGP_FRAME#2
AGP_TRDY#2
AGP_STOP#2
AGP_PAR2
AGP_AD_STB0#2
AGP_MB_8X_DET#
DNI/10uF_20V
R3
100R
U6A
R4
SN74ACT86D
180R
COMMON
AGP_TYPEDET#
AGP_GC_8X_DET#
+3.3V_BUS
UNIVERSAL VREFGC CIRCUIT (2X, 4X, 8X)
8
GND_AVSSQGND_R2SETGND_RT
R830R
+5V_BUS
147
3
R19
0R
R81
0R
R90
47K
13
12
7
C11
100nF
X7R
1
2
For retail, 1K ohm
pull-down causes
AMD system detects
AGP2X only
+12V, TYPEDET#
short protection
for OEM (1KR)
U6D
SN74ACT86D
7
6
The following grounds should be routed back to their respective regulators and then tied directly to the ground plane with one
GND_PVSSGND_MPVSSGND_AVSSNGND_A2VSSN GND_A2VSSQGND_TPVSS
TEST
11
AGP_ST1
AGP_SBA1
AGP_SBA3
AGP_SBA5
AGP_SBA7
AGP_AD30
AGP_AD28
AGP_AD26
AGP_AD24
AGP_C/BE#3
AGP_AD22
AGP_AD20
AGP_AD18
AGP_AD16
AGP_AD15
AGP_AD13
AGP_AD11
AGP_AD9
AGP_C/BE#0
AGP_AD6
AGP_AD4
AGP_AD2
AGP_AD0
R91
1K
+VDDQ_BUS
1
GND_RSET
32
R92
C2
100uF_6.3V
Biggest footprint
AGP_TYPEDET#
AGP_GC_8X_DET#
2N7002E
Q10
147R_1%
via: GND_PVSS, GND_MPVSS, GND_TPVSS, and GND_A2VSSN. The other ground pins (GND_AVSSN, GND_A2VSSQ,
GND_RSET, GND_R2SET) should be tied to the ground plane directly through one via as close to the pins as possible
without connecting to anything else. If space is an issue it is possible to use one via for two adjacent pins.
Use 47uF Tant. 16V 20% D size (P/N 4230047600),
800mR Max. ESR and Max. ripple 430mA @ 100kHz
or
100uF, Alum. 6.3V 20% 6.3mm dia (P/N 4261010700),
440mR Max. ESR and Max. ripple 230mA @ 100kHz
or
47uF, Alum. 6.3V 20% 5mm dia (P/N 4262047600),
760mR Max. ESR and Max. ripple 150mA @ 100kHz
MAGP1
A1
12V
A2
TYPEDET#
A3
GC_DET#/RESEVED
A4
USB-
A5
GND
A6
INTA#
A7
RST#
A8
GNT#
A9
VCC3.3
A10
ST1
A11
MB_DET#/RESERVED
A12
DBI_HI/PIPE#
A13
GND
A14
WBF#
A15
SBA1
A16
VCC3.3
A17
SBA3
A18
SB_STB#
A19
GND
A20
SBA5
A21
SBA7
A22
KEY
A23
KEY
A24
KEY
A25
KEY
A26
AD30
A27
AD28
A28
VCC3.3
A29
AD26
A30
AD24
A31
GND
A32
AD_STB1#
A33
C/BE3#
A34
VDDQ
A35
AD22
A36
AD20
A37
GND
A38
AD18
A39
AD16
A40
VDDQ
A41
FRAME#
A42
KEY
A43
KEY
A44
KEY
A45
KEY
A46
TRDY#
A47
STOP#
A48
PME#
A49
GND
A50
PAR
A51
AD15
A52
VDDQ
A53
AD13
A54
AD11
A55
GND
A56
AD9
A57
C/BE0#
A58
VDDQ
A59
AD_STB0#
A60
AD6
A61
GND
A62
AD4
A63
AD2
A64
VDDQ
A65
AD0
A66
VREFGC
UNIVERSAL_AGP_BUS
AGP_VREFGC
R_AGP8X must be 1%
resistor to provide
350mV +/- 5% on Vref
R_AGP8X
R93
332R_1%
C19
R94
10nF
100R_1%
6
OVRCNT#
USB+
INTB#
REQ#
VCC3.3
RBF#
DBI_LO/RESERVED
SBA0
VCC3.3
SBA2
SB_STB
SBA4
SBA6
AD31
AD29
VCC3.3
AD27
AD25
AD_STB1
AD23
VDDQ
AD21
AD19
AD17
C/BE2#
VDDQ
IRDY#
DEVSEL#
VDDQ
PERR#
SERR#
C/BE1#
VDDQ
AD14
AD12
AD10
VDDQ
AD_STB0
VDDQ
VREFCG
5
+3.3V_BUS+5V_BUS+VDDQ_BUS
C8
C5
47uF_6.3V
DNI/47uF_6.3V
>=6.3V
>=6.3V
B1
B2
5.0V
B3
5.0V
B4
B5
GND
B6
B7
CLK
B8
B9
B10
ST0
B11
ST2
B12
B13
GND
B14
B15
B16
B17
B18
B19
GND
B20
B21
B22
KEY
B23
KEY
B24
KEY
B25
KEY
B26
B27
B28
B29
B30
B31
GND
B32
B33
B34
B35
B36
B37
GND
B38
B39
B40
B41
B42
KEY
B43
KEY
B44
KEY
B45
KEY
B46
B47
B48
B49
GND
B50
B51
B52
B53
B54
B55
GND
B56
B57
AD8
B58
B59
B60
AD7
B61
GND
B62
AD5
B63
AD3
B64
B65
AD1
B66
+12V_BUS
5
AGP_ST0
AGP_ST2
AGP_SBA0
AGP_SBA2
AGP_SBA4
AGP_SBA6
AGP_AD31
AGP_AD29
AGP_AD27
AGP_AD25
AGP_AD23
AGP_AD21
AGP_AD19
AGP_AD17
AGP_C/BE#2
AGP_C/BE#1
AGP_AD14
AGP_AD12
AGP_AD10
AGP_AD8
AGP_AD7
AGP_AD5
AGP_AD3
AGP_AD1
AGP_AGPREF
J1
1
2
WAFER 2-PIN
4
AGP_SBA[7..0]
AGP_ST[2..0]
AGP_C/BE#[3..0]
AGP_AD[31..0]
R860R
4
3
AGP_SBA[7..0]2
AGP_ST[2..0]2
AGP_C/BE#[3..0]2
AGP_AD[31..0]2
AGP_AGP/PCICLK2
AGP_REQ#2
AGP_RBF#2
AGP_DBI_LO2
AGP_SB_STB2
AGP_AD_STB12
AGP_IRDY#2
AGP_DEVSEL#2
AGP_AD_STB02
3
TEST
AGP_AGPREF
AGP_VREFGC
TEST
+VDDQ_BUS
32
1
R84DNI/0R
R85DNI/0R
+VDDQ_BUS
32
1
2
R88169R_1%
Q9
2N7002E
R8971.5R_1%
AGP_AGPTEST
Keep stubs short
R_AGP8X must be 1%
resistor to provide
350mV +/- 5% on Vref
AGP_AGPTEST2
R_AGP8X
2N7002E
Q11
R95
147R_1%
R96
332R_1%
R97
100R_1%
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7N6
(905) 882-2600
Title
SizeDocument NumberRev
Custom
Date:Sheet of
2
C21
10nF
R9200-64/128DV
81-105-L30100
AGP_AGPREFCG2
1
116Monday, September 29, 2003
1
1.0
8
AGP_RESET#1,12
AGP_DEVSEL#1
AGP_IRDY#1
AGP_FRAME#1
AGP_AD_STB01
AGP_AD_STB11
AGP_SB_STB1
AGP_SBA[7..0]1
AGP_REQ#1
AGP_GNT#1
AGP_PAR1
AGP_STOP#1
AGP_TRDY#1
AGP_INTR#1
AGP_WBF#1
AGP_RBF#1
8
AGP_AD[31..0]
AGP_C/BE#[3..0]
R360R
AGP_ST[2..0]
C20
100nF
A_R/C_DAC214
A_G/Y_DAC214
A_B/COMP_DAC214
A_HSYNC_DAC214
A_VSYNC_DAC214
CLK_RT12
DNI/18pF
DNI/18pF
C73
DNI/22pF
AGP_SBA[7..0]
+3.3V_BUS
C1260
3
C1261
AGP_AD[31..0]1
DD
AGP_C/BE#[3..0]1
AGP_AGP/PCICLK1
CC
AGP_ST[2..0]1
AGP_AGPREFCG1
BB
AGP_AGPTEST1
AA
AGP_SB_STB#1
AGP_AD_STB0#1
AGP_AD_STB1#1
AGP_MB_8X_DET#1
AGP_DBI_HI1
AGP_DBI_LO1
TP8
TP
GND_R2SET
21
Y1
DNI/27 MHZ
7
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
R40715R_1%
R1198DNI/4.7KDNI
R1199DNI/4.7KDNI
CLK_XIN
R1329
DNI/1M
R300_XOUT
7
R13190R
R1320DNI_0R
CLK_XIN
R300_XOUT
TESTEN
R33
1K
W29
W28
AA29
AA28
AF29
AG30
AE29
AG28
AF28
AF27
AJ26
AH25
AC29
AB26
AE27
AD26
AC25
AC26
AA25
AA26
AD28
AD29
AC28
AB25
AG27
AB28
AB29
AJ21
AJ22
AK22
AK21
AG25
AF25
AF23
AG24
AG29
AH29
AJ28
AJ29
AH26
AJ27
K27
L26
L25
L27
M25
M26
N26
N25
R26
R25
T26
T25
U26
U25
U27
V26
M28
N29
N28
P29
P28
R29
R28
T28
V29
V28
Y29
Y28
P27
V25
M29
T29
J29
J28
K29
K28
L29
L28
P25
U29
Y25
Y26
P26
U28
H29
H28
6
U1A
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BEb0
C/BEb1
C/BEb2
C/BEb3
PCICLK
RSTb
REQb
GNTb
PAR
STOPb
DEVSELb
TRDYb
IRDYb
FRAMEb
INTAb
WBFb
NC19
NC18
RBFb
AD_STBF0
AD_STBF1
SB_STBF
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7/IDSEL
ST0
ST1
ST2
SB_STBS
AD_STBS0
AD_STBS1
AGPREF
AGPTEST
AGP8X_DETb
DBI_HI
DBI_LO
R2SET
C_R
Y_G
COMP_B
H2SYNC
V2SYNC
CRT2DDCCLK
CRT2DDCDAT
NC34
NC33
XTALIN
XTALOUT
TESTEN
STEREOSYNC
RV280
STEREOSYNC
Part 1 of 5
EXT TMDS / GPIO / ROM
PCI/AGPAGP2XCLK
NCSTMDSDAC1
AGP4X/8X
SSC DAC2
STEREOSYNC7
ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8
ZV_LCDDATA9
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15
ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23
ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDCNTL2
ZV_LCDCNTL3
DVIDDCDATA
VGADDCDATA
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
ROMCSb
DVOMODE
NC35
NC27
NC36
NC28
NC37
NC29
NC39
NC31
NC38
NC30
NC22
NC13
NC23
NC14
NC24
NC15
NC26
NC17
NC25
NC16
NC7
NC8
DPLUS
DMINUS
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
DVIDDCCLK
HPD
HSYNC
VSYNC
RSET
VGADDCCLK
AUXWIN
R
G
B
5
AJ5
AK4
AJ4
AF4
AG4
AH4
AK3
AJ3
AH3
AG3
AF3
AJ2
AH2
AG2
AF2
AH1
AG1
AH5
AE10
AF5
AE6
AF6
AE7
AG6
AF7
AG8
AF8
AE8
AE9
AF9
AG9
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AK10
AJ10
AH11
AJ11
AK6
AJ6
AH6
AH7
AE15
AF15
AE16
AF16
AG15
AH15
AH16
AH17
AF17
AG17
AJ17
AH18
AK18
AJ18
AG19
AH19
AJ16
AK16
AH20
AJ20
AF11
AE12
AF10
AE11
AJ13
AH13
AJ14
AH14
AJ15
AK15
AK12
AK13
AF13
AE13
AF12
AK25
AJ25
AK24
AH28
AH27
AJ23
AG26
AF26
AE25
VID/DVO12
VID/DVO13
VID/DVO14
VID/DVO15
R39499R_1%
GND_RSET
TP10
TP
Theater install ---- install Ra1,Ra4, remove Ra2,Ra3,R1115
Theater not install ---- install Ra2,Ra3, remove Ra1,Ra4,R41,R42,R1285 should be 0 ohm
6
5
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
ROMCS#
DVOMODE
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VID/DVO16
VID/DVO17
VID/DVO18
VID/DVO19
VID/DVO20
TP7
TP
4
VSYNC
VGADDCDATA
VGADDCCLK
4
GPIO[13..0]
VID[7:0]
DC_Strap18
DC_Strap28
DC_Strap38
DC_Strap48
LCDDATA207,12
VHAD112
VPHCTL12
CLK_VIP12
CLK_VID12
TMDS_TX0N16
TMDS_TX0P16
TMDS_TX1N16
TMDS_TX1P16
TMDS_TX2N16
TMDS_TX2P16
TMDS_TXCN16
TMDS_TXCP16
DVIDDCCLK14
DVIDDCDATA14
CHARGE_POW16
A_R_DAC113
A_G_DAC113
A_B_DAC113
A_HSYNC_DAC113
A_VSYNC_DAC113
CRT1DDCDATA13
CRT1DDCCLK13
3
GPIO[13..0]7,8
RSET
R2SET
Mem_Strap27
Mem_Strap17
Mem_Strap07
ROMCS#8
VID[7..0]12
3
2
THE VALUES OF RSET AND R2SET SHOWN IN THE TABLE MAY BE
APPROXIMATE VALUES ONLY (SUITABLE FOR PROTOTYPING)
BEFORE GOING INTO PRODUCTION,CONTACT YOUR ATI
499R
REPRESENTATIVE FOR THE RSET/R2SET VALUES QUALIFIED FOR
MASS PRODUCTION
715R
R986
24bit-SDR-DVO
10K
R1318
R
+VDDC_CT
LCDDATA167
LCDDATA177
PAL/NTSC8
DC_Strap58,14
STEREOSYNC
VGADDCDATA
VGADDCCLK
VSYNC
TESTEN
TDO
TDI
TMS
TCK
TRST
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7N6
(905) 882-2600
Title
SizeDocument NumberRev
Custom
Date:Sheet of
2
1
TP1
OPTION BOUNDARY
TP2
TP
SCAN WITH TESTEN
TP3
TP
TP4
TP
TP5
TP
TP
Some Part Ref's updated to 988 brd
R9200-64/128DV
81-105-L30100
216Monday, September 29, 2003
1
1.0
5
DD
4
3
2
1
MEMORY CHANNEL A
QSA[7..0]9
DQMA#[7..0]9
MAA[13..0]9
MDA[63..0]9
CC
BB
AA
QSA[7..0]
DQMA#[7..0]
MAA[13..0]
MDA[63..0]
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
QSB[7..0]10
DQMB#[7..0]10
MAB[13..0]10
R265
499R_1%
R268
499R_1%
MDB[63..0]10
+VREF
U1B
G29
DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQA8
DQA9
DQA10
DQA11
DQA12
DQA13
DQA14
DQA15
DQA16
DQA17
DQA18
DQA19
DQA20
DQA21
DQA22
DQA23
DQA24
DQA25
DQA26
DQA27
DQA28
DQA29
DQA30
DQA31
DQA32
DQA33
DQA34
DQA35
DQA36
DQA37
DQA38
DQA39
DQA40
DQA41
DQA42
DQA43
DQA44
DQA45
DQA46
DQA47
DQA48
DQA49
DQA50
DQA51
DQA52
DQA53
DQA54
DQA55
DQA56
DQA57
DQA58
DQA59
DQA60
DQA61
DQA62
DQA63
RV280
Part 2 of 5
MEMORY INTERFACE A
ELPIDA
G30
F28
F30
E29
D28
D29
D30
K25
K26
J25
J26
G28
G25
G26
G27
C29
B29
B28
C27
C26
B26
C25
B25
E26
F25
E25
F24
E23
D22
F22
E22
C17
B17
C16
B16
C14
B14
C13
B13
E18
F17
E17
D16
F15
E15
F14
E14
A13
C12
A12
B12
C10
B10
C9
B9
E13
F12
E12
F11
E10
F9
E9
F8
AA10
AA11
AA12
AA13
DQMAb0
DQMAb1
DQMAb2
DQMAb3
DQMAb4
DQMAb5
DQMAb6
DQMAb7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
RASAb
CASAb
WEAb
CSAb0
CSAb1
CKEA
CLKA0
CLKA0b
CLKA1
CLKA1b
CLKAFB
VREF
DIMA0
DIMA1
MAA0
B24
AA0
MAA1
A24
AA1
MAA2
B23
AA2
MAA3
C23
AA3
MAA4
B21
AA4
MAA5
F21
AA5
MAA6
E21
AA6
MAA7
F20
AA7
MAA8
E20
AA8
MAA9
C21
AA9
MAA10
B22
MAA11
C22
MAA12
A25
MAA13
C24
DQMA#0
E28
DQMA#1
H26
DQMA#2
A27
DQMA#3
E24
DQMA#4
B15
DQMA#5
E16
DQMA#6
C11
DQMA#7
E11
QSA0
F29
QSA1
H25
QSA2
B27
QSA3
F23
QSA4
C15
QSA5
F16
QSA6
B11
QSA7
F10
RASA#
A19
CASA#
C18
WEA#
F18
CSA#0
E19
CSA#1
F19
CKEA
B19
CLKA0
C20
CLKA#0
B20
CLKA1
B18
CLKA#1
A18
C19
TP11
TP
B8
F26
F13
+VREF
RASA#9
CASA#9
WEA#9
CSA#09
CSA#19
CKEA9
CLKA09,11
CLKA#09,11
CLKA19,11
CLKA#19,11
Vref Voltage
+MVDDQ
Re6
Re7
Place close to ASIC ball
Use localized Vref on the memory page
QSB[7..0]
DQMB#[7..0]
MAB[13..0]
MDB[63..0]
MEMORY CHANNEL B
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
U1C
B6
C6
B5
C5
B2
C3
C2
D2
E8
E7
D4
D3
F6
F3
F5
G6
D1
E2
F2
F1
G2
H3
H2
J3
G4
H6
H5
J6
K5
K4
L6
L5
U2
V2
V1
V3
W3
Y2
Y3
AA2
AA3
AB2
AB3
AC2
AD1
AD3
AE1
AE2
U6
U5
U3
V6
W5
W4
Y6
Y5
AA6
AA5
AB6
AB5
AD6
AD5
AE5
AE4
RV280
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQB9
DQB10
DQB11
DQB12
DQB13
DQB14
DQB15
DQB16
DQB17
DQB18
DQB19
DQB20
DQB21
DQB22
DQB23
DQB24
DQB25
DQB26
DQB27
DQB28
DQB29
DQB30
DQB31
DQB32
DQB33
DQB34
DQB35
DQB36
DQB37
DQB38
DQB39
DQB40
DQB41
DQB42
DQB43
DQB44
DQB45
DQB46
DQB47
DQB48
DQB49
DQB50
DQB51
DQB52
DQB53
DQB54
DQB55
DQB56
DQB57
DQB58
DQB59
DQB60
DQB61
DQB62
DQB63
Part 3 of 5
ELPIDA
MEMORY INTERFACE B
DQMBb0
DQMBb1
DQMBb2
DQMBb3
DQMBb4
DQMBb5
DQMBb6
DQMBb7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
RASBb
CASBb
WEBb
CSBb0
CSBb1
CKEB
CLKB0
CLKB0b
CLKB1
CLKB1b
CLKBFB
MEMVMODE
MEMVMODE1
DIMB0
DIMB1
MEMTEST
MAB0
J2
AB0
MAB1
K3
AB1
MAB2
K2
AB2
MAB3
L3
AB3
MAB4
L2
AB4
MAB5
M3
AB5
MAB6
M2
AB6
MAB7
N5
AB7
MAB8
M1
AB8
MAB9
M5
AB9
MAB10
N3
AB10
MAB11
P2
AB11
MAB12
P6
AB12
MAB13
P5
AB13
DQMB#0
A4
DQMB#1
E3
DQMB#2
G3
DQMB#3
J5
DQMB#4
W2
DQMB#5
AC3
DQMB#6
W6
DQMB#7
AC6
QSB0
B4
QSB1
E5
QSB2
G1
QSB3
K6
QSB4
W1
QSB5
AD2
QSB6
V5
QSB7
AC5
RASB#
R2
T5
T6
R5
R6
R3
N1
N2
T2
T3
P3
B7
C7
G5
AE3
C8
RASB#10
CASB#
CASB#10
WEB#
WEB#10
CSB#0
CSB#010
CSB#1
CSB#110
CKEB
CKEB10
CLKB0
CLKB010,11
CLKB#0
CLKB#010,11
CLKB1
CLKB110,11
CLKB#1
CLKB#110,11
TP12
TP
R55
47R
MEMVMODE[1:0]MEMORY IO VOLTAGE
0 1
1 0
1 1
2.5V (DDR)
1.8V (DDR)
3.3V (SDR)
R53
4.7K
R514.7K
R52DNI/4.7K
DNI
R54
DNI/4.7K
DNI
Default
+VDDC_CT
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7N6
(905) 882-2600
Title
SizeDocument NumberRev
Custom
5
4
3
2
Date:Sheet of
R9200-64/128DV
81-105-L30100
1
316Monday, September 29, 2003
1.0
5
U1D
P18
VDDC
P19
U12
U13
U14
U17
+MVDDQ
+VDDC_CT
GND_A2VSSN
(80mA)
U18
U19
V12
V13
V14
V17
V18
V19
W12
W13
W14
W17
W18
W19
H10
H13
H15
H17
H19
H22
J1
J23
J24
J27
J4
J7
J8
L8
M4
N4
N7
N8
R1
R4
T4
T7
T8
E27
F4
G10
G13
G15
G22
G7
Y23
L23
H20
H11
P8
Y8
AC11
AC20
AK19
AE19
AE20
AF20
AG20
AJ19
AF18
AF19
AE18
AE17
AJ12
AH12
AF14
AE14
AG14
AG13
AG12
AF21
AF22
AH21
AF24
AE23
AE21
AE22
AG22
AH22
GND_A2VSSQ
Matching
Ground
AVSSN
(Noisy)
AVSSQ
DD
CC
+3.3V_BUS
D31
2.4V
2 1
C55
47uF_6.3V
100nF
>=6.3V
X7R
+TPVDD
C58
C57
100nF
4.7uF
>=6.3V
X7R
Ceramic
B16200R
>=6.3V
Ceramic
C63
4.7uF
>=6.3V
Ceramic
GND_TPVSS
C59
4.7uF
+A2VDDQ
GND_A2VSSQ
C77
C60
100nF
100pF
X7R
X7R
+AVDD
C64
100nF
X7R
Board power
and ground
option(s)
5
C68
C67
100nF
4.7uF
>=6.3V
X7R
Ceramic
GND_AVSSN
+AVDD
Pin Names
Voltage
DAC1 VDD A2VSSQ
Usage
DAC1 Band Gap Ref.
AVDD sourced from VDDC_CT
thru bead at least 15 mil trace
and not longer than 1.5 inch.
AVSSN and AVSSQ with single
via to GND close to the pin.
BB
+VDDC_CT
+A2VDD
C61
C62
22uF_10V
100nF
X7R
>=6.3V
Ceramic
GND_A2VSSN
AA
Part 4 of 5
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDR1
Memory I/O Power
VDDR1
(1.8V/2.5V/3.3V)
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
I/O l evel shift pow er
(1.8V)
VDDC18
VDDC18
VDDC18
VDDC18
VDDC18
VDDC18
VDDC18
VDDC18
NC
VDDC18
VDDC18
NC
NC
NC
NC
NC
NC
NC
(1.8V)
TMDS PLL TMDS I/O
TPVDD
TPVSS
TXVDDR
TXVDDR
(1.8V)
TXVSSR
TXVSSR
TXVSSR
Analog Display Power,
A2VDD
see table below
A2VDD
A2VDDQ
AVDD
AVDD
A2VSSN
A2VSSN
A2VSSDI
A2VSSQ
RV280
+A2VDD
2.5V1.8V
DAC2 VDD
(120mA)
(1) A2VDD regulated source
and A2VSSN return path routed
with at least 15 mil trace and
not longer than 1.5 inch.
AVSSN with single via to GND
at the regulator.
(2) Sourced from VDD thru bead
instead of the regulator
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
I/O POWER
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDRH0
VDDRH1
VSSRH0
VSSRH1
VDDRH 1 - CH B Clock PowerAGP Bus I /O Power
VDDRH 0 - CH A Clock Power
(VDDR1)
MPVDD
MPVSS
PLL MPLL
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
(1.8V/3.3V)
Ext. TMDS/
DVO Power
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
(3.3V)
GPIO & Ext.
TMDS I/O Power
(1.5V/3.3V) (1.8V) (1.8V)
AVDDDI
A2VDDDI
AVSSQ
AVSSDI
AVSSN
AVSSN
+A2VDDQ
Matching
Ground
1.8V
A2VSSN
DAC2 Band Gap Ref.
(Noisy)
Source from AVDD thru bead.
A2VSSQ with sigle via to GND
close to the pin.
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
PVDD
PVSS
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
4
+VDDC
+MPVDD
C52
4.7uF
>=6.3V
Ceramic
B739
200R
B740
DNI/BEAD
B17200R
C66
4.7uF
>=6.3V
Ceramic
+3.3V_BUS
+VDDC_CT
Matching
Ground
AVSSDI
A2VSSDI
(Digital)(Quiet)
C53
100nF
X7R
+VDDC
CP9A
8 1
10nF
+PVDD
GND_PVSS
+VDDC_CT
CP9B
7 2
10nF
C54
4.7uF
>=6.3V
Ceramic
AC13
AC15
AC17
AD13
AD15
M12
M13
M14
M17
M18
M19
N12
N13
N14
N17
N18
N19
P12
P13
P14
P17
+MVDDQ
A15
A21
AA7
AA8
D11
D14
D17
D8
V4
A28
A3
A9
AA1
AA4
AD4
B1
B30
D10
D19
D20
D23
D26
D6
V7
V8
G19
N6
G18
M6
A7
A6
AK27
AK28
AC10
AC9
AD10
AD9
AG10
AD22
AC22
AC21
AD21
AC19
AD19
AD7
AC8
AA23
AA24
AB27
AB30
AC23
AD27
AE30
AH30
J30
M23
M24
N27
N30
P23
T23
T24
T27
T30
V23
V24
W27
W30
Y27
AH24
AH23
AJ24
AG23
AD24
AE24
4
+3.3V_BUS
GND_AVSSQ
GND_AVSSN
Matching
Ground
(Quiet)
C51
100nF
X7R
1uF
C1258
+VDDQ_BUS
TP9
C65
100nF
TP
X7R
+AVDDDI
+A2VDDDI
1.8V
Digital Power for
DAC1 and DAC2
Source from VDDC_CT
thru bead
GND_MPVSS
3
CP9D
CP3A
CP3C
CP9C
6 3
10nF
CP3B
5 4
8 1
6 3
7 2
10nF
10nF
10nF
10nF
+VDDC
C27
C26
100nF
100nF
X7RX7RX7RX7RX7R
+3.3V_BUS
CP1B
CP1A
7 2
8 1
10nF
10nF
+MVDDQ +MVDDQ
CP5C
CP5B
CP5A
6 3
7 2
8 1
10nF
10nF
10nF
+MVDDQ
C32
C33
100nF
100nF
X7RX7RX7RX7R
+VDDC_CT
CP1C
CP1D
6 3
5 4
10nF
10nF
+VDDQ_BUS
C45
C46
100nF
100nF
X7R
X7RX7RX7RX7R
C47
100nF
CP3D
5 4
10nF
C28
100nF
C44
100nF
CP5D
5 4
10nF
C34
100nF
C83
100nFC56
X7R
C48
100nF
CP4A
8 1
10nF
C29
100nF
CP6A
8 1
10nF
C35
100nF
CP4B
7 2
10nF
CP6B
7 2
10nF
C49
100nF
C30
100nF
Distributed around
+VDDQ_BUS plane
3
CP4C
6 3
10nF
CP6C
6 3
10nF
CP2A
CP4D
8 1
5 4
10nF
10nF
C38
10uf
CP6D
5 4
10nF
PLACE DIRECTLY
UNDERNEATH CHANNEL
A & B SECTION OF ASIC.
CP2B
CP2C
7 2
6 3
10nF
10nF
C39
10uf
+VDDQ_BUS
CP8A
8 1
10nF
+3.3V_BUS
CP8B
7 2
10nF
2 1
CP2D
5 4
10nF
CP8C
6 3
10nF
D30
2.4V
2
+VDDC
C23
10uf
At the corner of VDDC plane
CP8D
5 4
10nF
2
1
U1E
F27
VSS
F7
G12
G16
G21
G24
G9
H12
H14
H16
H18
H21
H23
H27
H4
H8
H9
K1
K23
K24
K30
K7
K8
L4
M15
M16
M27
M30
M7
M8
N15
N16
N23
N24
P15
P16
P4
R12
R13
R14
R15
R16
R17
R18
R19
R23
R24
R27
R30
R7
R8
T1
T12
T13
T14
T15
T16
T17
T18
T19
W23
W24
W25
W26
W7
W8
Y4
Part 5 of 5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RV280
CORE GND
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7N6
(905) 882-2600
Title
SizeDocument NumberRev
Custom
Date:Sheet of
U15
VSS
U16
VSS
U23
VSS
U4
VSS
U8
VSS
V15
VSS
A10
VSS
A16
VSS
A2
VSS
A22
VSS
A29
VSS
AA27
VSS
AA30
VSS
AB1
VSS
AB23
VSS
AB24
VSS
AB4
VSS
AB7
VSS
AB8
VSS
AC12
VSS
AC14
VSS
AC16
VSS
AC18
VSS
AC27
VSS
AC4
VSS
AD12
VSS
AD16
VSS
AD18
VSS
AD25
VSS
AD30
VSS
AE26
VSS
AE28
VSS
AG11
VSS
AG16
VSS
AG18
VSS
AG21
VSS
AG5
VSS
AG7
VSS
AJ1
VSS
AJ30
VSS
AK2
VSS
AK29
VSS
B3
VSS
C1
VSS
C28
VSS
C30
VSS
C4
VSS
D12
VSS
D13
VSS
D15
VSS
D18
VSS
D21
VSS
D24
VSS
D25
VSS
D27
VSS
D5
VSS
D7
VSS
D9
VSS
E4
VSS
E6
VSS
V16
VSS
V27
VSS
V30
VSS
W15
VSS
W16
VSS
R9200-64/128DV
81-105-L30100
1
416Monday, September 29, 2003
1.0
8
DD
7
6
Regulator for VDDC (ASIC Core)
Vin = 3.3V AGP
5
4
Cout1
470uF thru hole capacitor (P/N 4051047700)
3
2
1
has 30mR ESR where as 470uF SMT (P/N
4262047700) capacitor has 150mR ESR. For
current below 4.5A, 1 thru 470uF is enough.
Vout = 1.5V ~ 1.62V
Iout = 4A MAX (load consumption)
Iout = 2.5A MAX (Power rail consumption)
***
Indicate number of via required for the
connection
D12
1N5400
C102
1.0uF
+3.3V_BUS
***
21
21
***
C101
470uF_16V
These dummy resistors are placed
under the diodes to avoid PCB heat
D13
damage due to hot diodes.
1N5400
R554
0R
R553
0R
R552
0R
R551
0R
CC
***
Q21
+3.3V_BUS
C104
**
1uF_0805
3
2
5
84
+
1
-
U28A
LM358
*
SO8
VREF1256
C103
0.1uF
R254
0_0805
REG28
431L
R255
33_0805
3 2
*
6
R257
249_1%
1
R258
DNI
*
BB
C105
1uF
*
AA
8
7
MTD3055V
32
1
R253
1.07K_1%
R256
3.48K_1%
*
4
******
C106
820uF_4V
***
***
C107
820uF_4V
+VDDC+12V_BUS
**
C108
22uF_10V
**
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7N6
(905) 882-2600
Title
SizeDocument NumberRev
B
3
Date:Sheet of
2
R9200-64/128TD
81-105-L30100
516Monday, September 29, 2003
1
1.0
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