Series 6000 Chip databook
Table of contents
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Series 6000
Chip Data
Provides detailed specifications on the electrical interfaces, mechanical interfaces, and operating environment
characteristics for the FT 6000 Smart Transceiver and
Neuron 6000 Processor.
005-0230-01B
Echelon, LONWORKS, LonTalk, Neuron, 3120, 3150, LNS, FTXL,
Izot, ShortStack, and the Echelon logo are trademarks of
Echelon Corporation that may be registered in the United
States and other countries.
Other brand and product names are trademarks or
registered trademarks of their respective holders.
Smart Transceivers, Neuron Chips, and other OEM Products
were not designed for use in equipment or systems which
involve danger to human health or safety or a risk of
property damage and Echelon assumes no responsibility or
liability for use of the Smart Transceivers or Neuron Chips in
such applications.
Parts manufactured by vendors other than Echelon and
referenced in this document have been described for
illustrative purposes only, and may not have been tested
by Echelon. It is the responsibility of the customer to
determine the suitability of these parts for each
application.
ECHELON MAKES AND YOU RECEIVE NO WARRANTIES OR
CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR IN ANY
COMMUNICATION WITH YOU, AND ECHELON SPECIFICALLY
DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY
OR FITNESS FOR A PARTIC ULAR PURPOSE.
Except as expressly permitted herein, no part of this
publication may be reproduced, stored in a retrieval system,
or transmitted, in any form or by any means, electronic,
mechanical, photocopying, recording, or otherwise, without
the prior written permission of Echelon Corporation.
Printed in the United States of America.
Copyright © 2014 Echelon Corporation.
Echelon Corporation
www.echelon.com
ii
Welcome
Echelon’s FT 6000 Free Topology Smart Transceiver is the latest addition to Echelon’s FT
Smart Transceiver family.
The FT 6000 Smart Transceivers includes a network transceiver that is fully compatible with
the TP/FT-10 channel. The free topology transceiver supports polarity-insensitive cabling
using a star, bus, daisy chain, loop, or combined topologies. This flexibility frees the installer
from the need to adhere to a strict set of wiring rules. Free topology wiring reduces the time
and expense of device installation by allowing the wiring to be installed in the most
expeditious and cost-effective manner. It also simplifies network expansion by eliminating
restrictions on wire routing, splicing, and device placement.
The Neuron 6000 Processor has similar performance, robustness, and low cost as the FT
6000 Smart Transceiver, but you can use it with a number of different types of network
transceivers so that you can integrate different channel types (such as the TP/XF-1250
channel) into a L
Together, the FT 6000 Smart Transceiver and the Neuron 6000 Processor are part of a
family of products, collectively known as Series 6000 chips.
This document provides technical specifications for the electrical interfaces, mechanical
interfaces, and operating environment characteristics for the FT 6000 Smart Transceiver
and Neuron 6000 Processor.
ONWORKS network.
This manual does not describe Echelon’s Power Line Smart Transceivers. For more
information about that technology, see the PL 3120 / PL 3150 / PL 3170 Power Line Smart
Transceiver Data Book (005-0193-01A).
Audience
This manual provides specifications and user instructions for engineers who develop
applications and devices that use FT 6000 Smart Transceivers or Neuron 6000 Processors,
and for users of network interfaces based on the FT Smart Transceivers or Neuron Chips.
What’s New for Echelon’s Smart Transceivers and Neuron Chips
Echelon’s FT 6000 Smart Transceiver and Neuron 6000 Processor include new features and
functions compared with Echelon’s FT 5000 Smart Transceiver and Neuron 5000 Processor.
This section describes some of the major new features and functions of the Series 6000 chips.
New Memory Layout
Series 6000 chips use only an external SPI flash of at least 512KB. This flash contains active
and standby bootloaders, system images, and applications. It also holds persistent system
and application data, as well as data logs. Larger applications can be supported because
certain code can be designated to be “transient” which means it is brought into RAM for
execution out of flash only on demand. See the Memory Architecture section in Chapter 2 for
a full description.
Series 6000 Chip Data Book iii
The memory map for a Series 6000 chip is “auto-tuned”. This means that the linker decides
how to partition the RAM based upon the needs placed on it by the application. The user
does not need to specify the address ranges used for each type of memory (code vs data vs
persistent data).
IP Support
The system image for the Series 6000 chip contains a UDP/IP (V4) stack along with ICMP
and SNMP (V1). In conjunction with an IzoT Router, the device can communicate using
LonTalk/IP, BACnet/IP, be pinged from a device on the Ethernet side of the IzoT router or
monitored via SNMP from a standard SNMP client such as Solar Winds. The device can also
get an IP address via DHCP from the IzoT Router. Furthermore, one can use a socket API
on a Windows or Linux PC (or any device that supports sockets) to open a UDP socket
connection to a Series 6000 device through an IzoT Router.
BACnet Support
The larger application space allows an application to include a BACnet library that enables a
device to be monitored and controlled in a traditional manner from an OpenLNS based tool
and simultaneously from a standard BACnet workstation using BACnet/IP.
Extended Address Table
Series 6000 chips use system firmware version 21 or later which supports up to 254 address
table entries for Neuron hosted devices (devices without a host microprocessor). The entries
beyond 15 are used by OpenLNS Server 4.02 and the IzoT Commissioning Tool.
Compiler Enhancements
The Neuron C compiler supports auto initializers for scalars (e.g., int i=0;) Furthermore, the
Neuron C preprocessor has been replaced by a standard preprocessor called MCPP
(http://mcpp.sourceforge.net).
Related Documen tation
The following table lists related Echelon documentation that can be useful when designing or
using Series 6000 chips with L
includes documentation for the IzoT NodeBuilder Development Tool, the primary
development tools for L
Echelon Web site (www.echelon.com
Title Part Number Description
FT 6000 EVB Hardware Guide 078-0504-01A This manual describes the hardware
ONWORKS devices. All of these manuals are available from the
ONWORKS devices and LONWORKS networks. The table
).
Table 1. Related Documentation
for the FT 6000 EVB evaluation
boards that are included with the FT
6000 EVK.
FT 6000 EVB Schematic 012-1460-51A This document provides the
schematic diagrams for the FT 6000
EVB
iv
Title Part Number Description
Introduction to the LONWORKS
Platform
078-0183-01B This manual provides an
introduction to the ISO/IEC 14908
(ANSI/EIA/CEA-709.1 and EN
14908) Control Networking Protocol,
and provides a high-level
introduction to L
ONWORKS
®
networks
and the tools and components that
are used for developing, installing,
operating, and maintaining them.
IzoT NodeBuilder User’s Guide 078-0516-01A This manual describes how to
develop L
ONWORKS devices and
applications using the IzoT
NodeBuilder Development Tool.
I/O Model Reference for Smart
Transceivers and Neuron Chips
078-0392-01C This manual provides information
about the I/O models used by
Echelon’s Neuron Chips and Smart
Transceivers.
It includes hardware and software
considerations for each of the I/O
models.
Neuron Assembly Language
Reference
078-0399-01B This manual describes the Neuron
assembly language and how to write
Neuron assembly language functions.
Neuron C Programmer’s Guide 078-0002-01I This manual describes how to write
programs using the Neuron C
Version 2.2 programming language.
Neuron C Reference Guide 078-0140-01G This manual provides reference info
for writing programs using the
Neuron C Version 2.2 programming
language.
IzoT BACnet Developer’s Guide 078-0507-01A This manual details how to develop a
BACnet/IP application on a Series
6000 device.
NodeLoad User’s Guide 078-0286-01G This manual details the uaage of the
NodeLoad application.
NodeUtil User’s Guide 078-0438-01B This manual details the uaage of the
NodeUtil application.
For information about previous generation Smart Transceivers, see the Echelon FT 3120 /
FT 3150 Smart Transceiver Data Book or the Series 5000 Chip Data Book.
Series 6000 Chip Data Book v
All of the Echelon product documentation is available in Adobe® PDF format. To view the
PDF files, you must have a current version of the Adobe Reader
. Most Echelon products
include the English-language version of the Adobe Reader; you can download other language
versions from Adobe at: www.adobe.com/products/acrobat/readstep2.html
.
Standards Documents Referenced in this Manual
This manual refers to the following standards documents:
• American Society for Testing and Materials (ASTM) B258 - 02(2008) Standard
Specification for Standard Nominal Diameters and Cross-Sectional Areas of AWG
Sizes of Solid Round Wires Used as Electrical Conductors.
www.astm.org/Standards/B258.htm
• Comité européen de normalisation electrotechnique
Information technology equipment – Radio disturbance characteristics – Limits and
methods of measurement.
• Comité international spécial des perturbations radioélectriques
Information Technology Equipment – Radio Disturbance Characteristics – Limits
and Methods of Measurement.
1
(CENELEC) EN 55022 –
2
(CISPR) 22 –
• Electrostatic Discharge Association standard ESD STM5.1: Electrostatic Discharge
Sensitivity Testing – Human Body Model. www.esda.org/freedowloads.html
• European Union Restriction of Hazardous Substances (RoHS) Directive 2002/95/EC.
europa.eu.int/eur-lex/pri/en/oj/dat/2003/l_037/l_03720030213en00190023.pdf
• Comité européen de normalisation
3
(CEN) Electromagnetic Compatibility (EMC)
standards (see Table 2).
• International Organization for Standardization (ISO) and International
Electrotechnical Commission (IEC) standard ISO/IEC 14908 Control Network
Protocol
• Institute of Electrical and Electronics Engineers (IEEE) Standard Test Access Port
and Boundary-Scan Architecture (IEEE 1149.1-1990).
www.ieee.org/web/standards/home/index.html
.
• Institute for Printed Circuits (IPC) / Joint Electron Device Engineering Council
(JEDEC) Solid State Technology Association standard: IPC/JEDEC J-STD-020D.1 –
Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface
Mount Devices. www.jedec.org/download/search/JSTD020D-01.pdf
• Title 47 of the Code of Federal Regulations (CFR) Part 15, Radio Frequency Devices.
www.fcc.gov/oet/info/rules/
• US Military Standard MIL-STD-883 Test Method Standard, Microcircuits: Method
3015.7, Electrostatic Discharge Sensitivity Classification.
1
European Committee for Electrotechnical Standardization
2
International Special Committee on Radio Interference
3
European Committee for Standardization
vi
You can purchase copies of CENELEC documents, IEC EMC standards, ISO standards, US
Military Standards, and CISPR documents from the Information Handling Services (IHS)
Global page at: global.ihs.com
www.iec.ch.
Table 2. IEC Electromagnetic Compatibility (EMC) Standards
Standard Title
IEC 61000-4-1 Electromagnetic compatibility (EMC) - Part 4-1: Testing and
measurement techniques - Overview of IEC 61000-4 series
IEC 61000-4-2 Electromagnetic compatibility (EMC) - Part 4-2: Testing and
measurement techniques - Electrostatic discharge immunity test
IEC 61000-4-3 Electromagnetic compatibility (EMC) - Part 4-3 : Testing and
measurement techniques - Radiated, radio-frequency, electromagnetic
field immunity test
. IEC EMC standards are also available from the IEC at:
IEC 61000-4-4 Electromagnetic compatibility (EMC) - Part 4-4: Testing and
measurement techniques - Electrical fast transient/burst immunity test
IEC 61000-4-5 Electromagnetic compatibility (EMC) - Part 4-5: Testing and
measurement techniques - Surge immunity test
IEC 61000-4-6 Electromagnetic compatibility (EMC) - Part 4-6: Testing and
measurement techniques - Immunity to conducted disturbances, induced
by radio-frequency fields
Series 6000 Chip Data Book vii
Table of Contents
Welcome ......................................................................................................... iii
Audience ........................................................................................................ iii
What’s New for Echelon’s Smart Transceivers and Neuron Chips ........... iii
Related Documentation ................................................................................ iv
Standards Documents Referenced in this Manual ..................................... vi
Introduction ....................................................................................................... 1
Product Family Overview .............................................................................. 2
FT 6000 Smart Transceiver .................................................................... 2
Neuron 6000 Processor ............................................................................ 2
Development Resources for Series 6000 Chips ............................................ 2
Introduction to LONWORKS Networks .......................................................... 3
Overview of the IzoT Platform ...................................................................... 4
Overview of Free Topology Technology ........................................................ 5
Key Features of Series 6000 Chips ............................................................... 8
Additional Key Features for FT 6000 Smart Transceivers................... 8
Specification Summaries ............................................................................... 9
Specification Summary for FT 6000 Smart Transceivers ..................... 9
Specification Summary for Neuron 6000 Processors .......................... 11
Hardware Resources ...................................................................................... 13
Series 6000 Architecture ............................................................................. 14
Neuron Processor Architecture ............................................................. 15
Multiple Processors ............................................................................... 17
Interrupts ............................................................................................... 19
Assembly Instruction Set ...................................................................... 19
Memory Architecture ................................................................................... 23
On-Chip Memory ................................................................................... 24
Memory Map .......................................................................................... 24
External Serial Memory Interface ........................................................ 26
Serial Peripheral Interface (SPI) ................................................... 26
Non-Volatile Memory Integrity ...................................................... 27
Device Support ................................................................................ 28
Device Programming....................................................................... 29
Recovering a Device ........................................................................ 29
Transience .............................................................................................. 30
Data Logging .......................................................................................... 30
Boot Loader ............................................................................................ 30
JTAG Interface ............................................................................................. 31
Operating Conditions ................................................................................... 32
Pin Assignments .......................................................................................... 34
FT 6000 Smart Transceiver .................................................................. 34
Neuron 6000 Processor .......................................................................... 36
Pin Connections ............................................................................................ 39
Characteristics of the Digital Pins .............................................................. 43
Communications Port (CP) Pins for the Neuron 6000 Processor .............. 44
Single-Ended Mode ................................................................................ 46
Collision Detection for Single-Ended Mode ................................... 48
Beta 1 and Beta 2 Timeslots in Single-Ended Mode .................... 48
Special-Purpose Mode ........................................................................... 50
Network Connection .................................................................................... 54
Connection for an FT 6000 Smart Transceiver ................................... 54
viii
Comparison with FT 3120 or FT 3150 Devices ............................. 55
Comparison with Series 5000 Devices ........................................... 56
Comparison with the FTT-10A Transceiver .................................. 56
Connection for a Neuron 6000 Processor ............................................. 57
TPT/XF-1250 Transceivers ............................................................. 57
EIA-485 Transceivers ..................................................................... 58
LPT-11 Link Power Transceivers .................................................. 59
Clock Requirements ..................................................................................... 61
External Crystal .................................................................................... 61
Comparison with Series 3100 Clocks ................................................... 62
Reset Function.............................................................................................. 63
RST~ Pin ................................................................................................ 63
Reset Sources ......................................................................................... 64
Power-Up and LVI .......................................................................... 65
Watchdog Timer .............................................................................. 65
Traps ................................................................................................ 66
Software-Controlled Reset .............................................................. 66
Reset Processes and Timing ................................................................. 66
SVC~ Pin ...................................................................................................... 69
Integrity Mechanisms .................................................................................. 70
Processor Integrity ................................................................................ 70
System Firmware Image ....................................................................... 70
Application Integrity Using Checksums .............................................. 70
Hardware Design Considerations ............................................................... 73
PC Board Layout Guidelines ....................................................................... 74
Design and Test for Electromagnetic Compatibility ............................. 77
Overview ....................................................................................................... 78
Achieving High Immunity ........................................................................... 79
Electrostatic Discharge ................................................................................ 79
Electromagnetic Interference ...................................................................... 80
Radiated and Conducted Immunity ............................................................ 82
Surge and Burst ........................................................................................... 85
Lightning Protection .................................................................................... 86
Building Entrance Protection ............................................................... 86
Network Line Protection ....................................................................... 86
Shield Protection ................................................................................... 86
Suggested Gas Discharge Arresters ..................................................... 86
Avoiding Magnetic Field Interference ........................................................ 88
Summary and Testing Results .................................................................... 89
Network Cabling and Connections for FT Devices ................................ 91
Network Connection .................................................................................... 92
Network Topology Overview ....................................................................... 92
System Performance and Cable Selection .................................................. 94
System Specifications ............................................................................ 95
Transmission Distance Specifications .................................................. 95
Cable Termination and Shield Grounding ................................................. 96
Free Topology Network Segment ......................................................... 96
Doubly Terminated Bus Topology Segment ........................................ 96
Grounding Shielded Twisted Pair Cable .............................................. 97
Input/Output Interfaces for the Series 6000 ............................................ 99
Overview ..................................................................................................... 100
Series 6000 Chip Data Book ix
Two 16-Bit Timer/Counters ....................................................................... 100
Summary of the Available I/O Objects ..................................................... 101
Hardware Considerations .......................................................................... 109
Programming Considerations.................................................................... 113
Application Program Development ........................................................... 114
IzoT NodeBuilder Development Tool ........................................................ 114
Development Hardware Setup ........................................................... 114
Release Hardware Setup ..................................................................... 115
SNMP Support ........................................................................................... 116
Supported Commands ......................................................................... 116
Supported Objects ................................................................................ 116
Migrating from earlier Neuron Chips ....................................................... 117
Migrating Self-Installation Routines ................................................. 117
Series 6000 Design Checklists .................................................................... 119
Checklist 1: Series 6000 Chip Connections .............................................. 120
Checklist 2: FT 6000 Smart Transceiver Connections ............................ 122
Checklist 3: Neuron 6000 Processor Connections .................................... 123
Checklist 4: Power Supply ......................................................................... 124
Checklist 5: Device PCB Layout ............................................................... 125
Checklist 6: Network Cabling and Termination ...................................... 126
Checklist 7: Device Programming ............................................................. 127
Qualified TP/FT-10 Cable Specifications ................................................ 129
Introduction ................................................................................................ 130
Qualified Cables ......................................................................................... 130
Category 5 and 6 Cable Specifications ............................................... 131
NEMA Type 4 Cable Specifications .................................................... 131
16 AWG (1.3 mm) “Generic” Cable Specifications ............................. 133
FT-X3 Communications Transformer ...................................................... 135
Transformer Pinout ................................................................................... 136
Transformer Electrical Connections ......................................................... 137
Transformer Pad Layout ........................................................................... 138
Handling and Manufacturing Guidelines ............................................... 141
Application Considerations ....................................................................... 142
Termination of Unused Pins ............................................................... 142
Avoidance of Damaging Conditions .................................................... 143
Electrostatic Discharge Design Guidelines ........................................ 145
Power Supply, Ground, and Noise Considerations ........................... 145
Decoupling Capacitors ......................................................................... 146
Board Soldering Considerations ............................................................... 146
Recommended Solder Profile .............................................................. 146
Soldering Surface Mount (SMT) Parts ............................................... 147
General ESD Handling Guidelines ........................................................... 147
Power Distribution and Decoupling Capacitors ....................................... 151
Recommended Bypass Capacitor Placement ............................................ 151
Example Schematic ...................................................................................... 155
Example Schematic .................................................................................... 156
Basic Electrical Connections ............................................................... 156
Memory Interface Connections ........................................................... 157
Transformer Connections .................................................................... 157
x
I/O and Network Connections ............................................................. 157
BOM for Example Schematic .................................................................... 158
Vendor Contact Information ...................................................................... 160
Vendor Information .................................................................................... 161
Abracon Corporation ........................................................................... 161
Atmel Corporation ............................................................................... 161
Belden Inc. ........................................................................................... 161
BPM Microsystems .............................................................................. 162
Citel Inc. ............................................................................................... 162
CommScope Inc. ................................................................................... 162
Emulation Technology Inc. ................................................................. 163
Fairchild Semiconductor Inc. .............................................................. 163
HiLo System Research Company Ltd. ............................................... 163
Laird Technologies PLC ...................................................................... 164
Littelfuse Inc. ....................................................................................... 164
Numonyx BV ........................................................................................ 164
NXP Semiconductors BV ..................................................................... 165
ON Semiconductor ............................................................................... 165
Panasonic Corp. ................................................................................... 165
Plastronics Socket Company Inc. ....................................................... 166
Sankosha Corp. .................................................................................... 166
Silicon Storage Technology Inc. .......................................................... 166
Taiyo Yuden Company Ltd. ................................................................ 167
TDK Corp. ............................................................................................ 167
Total Phase Inc. ................................................................................... 167
Vishay Intertechnology Inc. ................................................................ 168
Series 6000 Chip Data Book xi
Introduction
This chapter introduces the Series 6000 of products,
ONWORKS networks, and free topology networking.
L
1
Series 6000 Chip Data Book 1
Product Family Overview
Echelon designed the original Neuron Chip as a system-on-a-chip semiconductor device to
provide intelligence and networking capabilities to low-cost control devices. Through a
unique combination of hardware and firmware, the Neuron Chip provided all of the key
functions necessary to process inputs from sensors and control devices intelligently, and to
propagate control information across a variety of network media. Since then, Echelon has
continued to develop and improve the families of products that are based on the Neuron
Chip.
This book describes the newest additions to the Neuron families of products:
• FT 6000 Free Topology Smart Transceivers
• Neuron 6000 Processors
This book describes these products generically as “Series 6000 chips”.
All Series 6000 chips include multiple processors, read-write and read-only memory (RAM
and ROM), communication subsystems, and I/O subsystems. Each Series 6000 chip includes
a processor core for running applications and managing network communications, memory,
I/O, and a 48-bit identification number (the Neuron ID) that is unique to every device. In
addition, all Series 6000 chips include the Neuron system firmware, which provides an
implementation of the LonTalk
application-program management. The device manufacturer provides the application code
and the I/O devices that complete a L
®
protocol, along with I/O libraries, and a task scheduler for
ONWORKS device.
The Neuron 6000 Processor provides a media-independent communications port which
permits short distance Neuron Chip-to-Neuron Chip communications, and can also be used
with external line drivers and transceivers of almost any type.
FT 6000 Smart Transceiver
The FT 6000 Free Topology Smart Transceiver integrates a high performance Neuron core
with a free topology twisted pair transceiver. Together with the FT-X3 Communications
Transformer and inexpensive serial memories, the FT 6000 Smart Transceiver provides a
low-cost, high-performance solution.
Neuron 6000 Processor
The Neuron 6000 Processor provides a media-independent communications port that
supports external transceivers for EIA-485 or TP/XF-1250 channels, using an external
transceiver circuit. The Neuron 6000 Processor can also connect to a link-power TP/FT-10
channel using a L
provides a lower-cost, higher-performance alternative to the previous generation of Neuron
Chips.
ONWORKS LPT-11 Link Power Transceiver. The Neuron 6000 Processor
Development Resources for Series 6000 Chips
A wide assortment of technical documentation, diagnostic tools, support programs, and
training courses are available to assist customers with their projects. Additionally, Echelon
offers fee-based pre-production design reviews of customers’ products, schematics, PCB
layouts, and bills of material to verify that they comply with published guidelines.
2 Introduction
Introduction to LONWORKS Networks
In almost every industry, there is a trend away from proprietary control schemes and
centralized systems. The migration towards open, distributed, peer-to-peer networks is
being driven by the need for interoperability, robust technology, faster development time,
and scale economies.
With thousands of application developers and millions of devices installed worldwide, the
ONWORKS system is the leading open solution for building and home automation,
L
industrial, transportation, and public utility control networks. A control network is any
group of devices working in a peer-to-peer fashion to monitor sensors, control actuators,
communicate reliably, manage network operation, and provide complete access to network
data. A L
network data from any device in the network.
ONWORKS network provides communications and complete access to control
The communications protocol used for L
ONWORKS networks is the ISO/IEC 14908-1
(ANSI/CEA 709.1-B and EN14908.1) Control Network Protocol. This protocol is an
international standard seven-layer protocol that has been optimized for control applications
and is based on the Open Systems Interconnection (OSI) Basic Reference Model (the OSI
Model, ISO standard 7498-1). The OSI Model describes computer network communications
through the seven abstract layers described in Table 3. The implementation of these layers
ONWORKS device provides standardized interconnectivity for devices within a
in a L
ONWORKS network.
L
Table 3. L
ONWORKS Network Protocol Layers
OSI Layer Purpose Services Provided
7 Application Application compatibility Network configuration, self-installation,
network diagnostics, file transfer,
application configuration, application
specification, alarms, data logging,
scheduling
6 Presentation Data interpretation Network variables, application messages,
foreign frame transmission
5 Session Control Request/response, authentication
4 Transport End-to-end
communication reliability
Acknowledged and unacknowledged
message delivery, common ordering,
duplicate detection
3 Network Destination addressing Unicast and multicast addressing,
routers
2 Data Link Media access and framing Framing, data encoding, CRC error
checking, predictive carrier sense
multiple access (CSMA), collision
avoidance, priority, collision detection
1 Physical Electrical interconnect Media-specific interfaces and modulation
schemes
Series 6000 Chip Data Book 3
Echelon’s implementation of the ISO/IEC 14908-1 Control Network Protocol is called the
LonTalk protocol. Echelon provides implementations of the LonTalk protocol with several
product offerings, including the Neuron system firmware, OpenLNS
client, SmartServers,and the ShortStack
ISO/IEC 14908-1 Control Network Protocol as the “LonTalk protocol”, although other
interoperable implementations exist.
ONWORKS system is based on the following concepts:
A L
• Control systems have many common requirements regardless of application.
• A networked control system is significantly more powerful, flexible, and scalable than
a non-networked control system.
• Businesses can save and make more money with control networks over the long term
than they can with non-networked control systems.
L
ONWORKS networks provide a complete suite of messaging services, including end-to-end
acknowledgement, authentication, and priority message delivery. Network management
services allow network tools to interact with devices over the network, including local or
remote reconfiguration of network addresses and parameters, downloading of application
programs, reporting of network problems, and start/stop/reset of device application
programs.
ONWORKS networks range in sophistication from small networks embedded in machines to
L
large networks with thousands of devices controlling fusion lasers, paper manufacturing
machines, or building automation systems. L
trains, airplanes, factories, and hundreds of other processes. Manufacturers are using open,
off-the-shelf chips, operating systems, and parts to build products that feature improved
reliability, flexibility, system cost, and performance.
®
Micro Server. This document refers to the
ONWORKS networks are used in buildings,
®
Server, LNS remote
Echelon manufactures many L
and end users implement L
ONWORKS solution including development tools, network management software, power line
L
and twisted pair transceivers and control modules, network interfaces, technical support and
training.
See Introduction to the LonWorks Platform (078-0183-01B) for more information about
ONWORKS networks.
L
ONWORKS products to help developers, system integrators,
ONWORKS networks. These products provide a complete
Overview of the IzoT Platform
The IzoT™ Platform is an IP-enabled family of chips, stacks, interfaces, and
management software that enables the development of devices, peer-to-peer device
communities, and applications for the Industrial Internet of Things. Unlike consumergrade platforms, the IzoT Platform comprehensively addresses unique IIoT requirements
such as autonomous control, multi-cast addressing and industrial-strength reliability.
The IzoT platform builds on LonWorks networking technology by adding native IP
support down to individual field devices, with Neuron 6050 and FT 6050 based devices
providing the option of backwards compatibility with ISO/IEC 14908-1.
4 Introduction
Series 6000 based field devices are capable of running multiple protocols (LonTalk,
LonTalk/IP, BACnet/IP, SNMP, ICMP with UDP sockets available) with a variety of
transceiver options.
Overview of Free Topology Technology
A conventional control system using bus topology wiring (such as an EIA-485 network)
consists of a network of sensors and actuators that are interconnected using a twisted wire
pair. In accordance with EIA-485 guidelines, all of the devices must be wired in a bus
topology to limit electrical reflections and to ensure reliable communications. There is a high
cost associated with installing and maintaining the cable plant that links together the
devices of an EIA-485-based control system. Bus topology wiring is more time consuming
and expensive to install, because the installer is unable to branch or star the wiring where
convenient. All devices must be connected directly to the main bus.
The best solution to reduce installation and maintenance costs and to simplify system
modifications is to use a free topology communications system. Echelon’s free topology
transceiver technology offers such a solution, providing an elegant and inexpensive method
of interconnecting the different elements of a distributed control system.
A free topology architecture allows the installer to wire the control devices with virtually no
topology restrictions. Power is supplied by a local DC power supply located at each device as
shown in Figure 1.
Series 6000 Chip Data Book 5
Smart
Transceiver
Smart
Transceiver
Smart
Transceiver
Smart
Transceiver
Smart
Transceiver
Smart
Transceiver
Termination
To Additional
Free Topology
Devices
Sensor
Actuator
DC power
Smart Transceivers
:
•
FT
3120
Smart Transceiver
•
FT
3150 Smart Transceiver
•
FT
5000
Smart Transceiver
•
FT
6000
Smart Transceiver
Unlike bus wiring designs, the free topology FT Smart Transceivers or Neuron Chips with
associated transceivers use a wiring scheme that supports star, loop, or bus wiring (see
Figure 2).
Figure 1. Free Topology Transceiver System
6 Introduction
Figure 2. Typical Wiring Topologies Supported by FT Smart Transceivers
This design has many advantages:
• The installer is free to select the method of wiring that best suits the installation,
reducing the need for advanced planning and allowing last minute changes at the
installation site.
• If installers have been trained to use one style of wiring for all installations, free
topology technology can be introduced without requiring retraining.
• Retrofit installations with existing wiring plants can be accommodated with minimal,
if any, rewiring. This capability ensures that FT Smart Transceiver technology can
be adapted to both old and new projects.
• Free topology permits FT Smart Transceiver or Neuron Chip systems to be expanded
in the future by simply tapping into the existing wiring where it is most convenient
to do so. This reduces the time and expense of system expansion, and from the
customer's perspective, keeps down the life-cycle cost of the free topology network.
Series 6000 Chip Data Book 7
Key Features of Series 6000 Chips
Series 6000 chips include the following key features:
• Provide a high performance Neuron Core, with internal system clock rates up to 80
MHz
• Require as little as 30 mW of power for operations
• Packaged as a 7 mm by 7 mm 48-pin quad flat no leads (QFN) chip
• Include a serial memory interface for inexpensive external flash non-volatile memory
• Support up to 254 network variables (NVs) for FT 6000 Smart Transceivers and
Neuron 6000 Processors, without the need for a host microprocessor
• Support user-programmable interrupts to provide fast response time to external
events
• Provide an interface for the Institute of Electrical and Electronics Engineers (IEEE)
Standard Test Access Port and Boundary-Scan Architecture (IEEE 1149.1-1990) of
the Joint Test Action Group (JTAG) to allow a Series 6000 chip to be included in the
boundary-scan chain for device production tests
• Include 12 I/O pins with 35 programmable standard I/O models that support both 5 V
and 3.3 V I/O operation
• Support up to 256 KB of user application code space (with a 1MB external flash)
• Include 64 KB RAM (of which 44 KB is user accessible) and 16 KB of ROM on-chip
• Include a unique 48-bit MAC ID in every device for network installation and
management
• Support a –40°C to +85°C operating temperature range
• Compliant with the European Union Restriction of Hazardous Substances (RoHS)
Directive 2002/95/EC.
Additional Key Features for FT 6000 Smart Transceivers
FT 6000 Smart Transceivers include the following additional key features:
• Support polarity insensitive free topology star, daisy chain, bus, loop, or mixed
topology wiring for TP/FT-10 channels
• Compliant with TP/FT-10 channels that currently use FT 3120 Smart Transceivers,
FT 3150 Smart Transceivers, FTT-10A transceivers, LPT-11 transceivers or FT-5000
Transceivers
• Provide very high common-mode noise immunity
8 Introduction
Specification Summaries
The following sections summarize the specifications for FT 6000 Smart Transceivers and
Neuron 6000 Processors.
Specification Summary for FT 6000 Smart Transceivers
Table 4 summarizes the specifications for the FT 6000 Smart Transceiver.
Table 4. FT 6000 Smart Transceiver Specification Summary
Description Specification
Data communications type Differential Manchester encoding
Transmission speed 78 kilobits per second
Network polarity Polarity insensitive
Number of transceivers per network
segment
Network wiring 24 to 16 AWG twisted pair
Network length for free topology Varies by wire type.
Network length for bus topology Varies by wire type.
Maximum stub length for bus
topology
Network termination One terminator for free topology
Up to 64
• Up to 1000 m (3280 ft) maximum total wire
with one repeater
• Up to 500 m (1640 ft) maximum total wire
with no repeaters
• 5400 m (17 710 ft) maximum total wire with
one repeater
• 2700 m (8850 ft) maximum total wire with no
repeaters
3 m (9.8 ft)
Two terminators for bus topology
Voltage for FT 6000 Smart
Transceiver
Operating temperature –40 ºC to +85 ºC
Series 6000 Chip Data Book 9
3.3 V ±5%
Description Specification
Reflow soldering temperature profile Refer to Joint Industry Standard document
IPC/JEDEC J-STD-020D.1 (March 2008)
Peak reflow soldering temperature 260 ºC
Package type 48-pin QFN
RoHS compliant Yes
EMI
ESD Designed to comply with EN 61000-4-2, Level 4
Radiated Electromagnetic
Susceptibility
Fast Transient/Burst Immunity Designed to comply with EN 61000-4-4, Level 4
Surge Immunity Designed to comply with EN 61000-4-5, Level 3
Conducted RF Immunity Designed to comply with EN 61000-4-6, Level 3
Table 5 summarizes the specifications for the FT-X3 Communications Transformer.
Table 5. FT-X3 Communications Transformer Specification Summary
Description Specification
Operating humidity 25-90% RH @50 °C, non-condensing
Non-operating humidity 95% RH @ 50 °C, non-condensing
Designed to comply with FCC Part 15 Subpart B and
EN 55022 Level B
Designed to comply with EN 61000-4-3, Level 3
Vibration 1.5 g peak-to-peak, 8 Hz to 2 kHz
Mechanical shock 100 g (peak)
Reflow soldering temperature profile Refer to Joint Industry Standard document
IPC/JEDEC J-STD-020D.1 (March 2008)
Peak reflow soldering temperature 245 ºC
10 Introduction
Specification S ummary for Neuron 6000 Processors
Table 6 summarizes the specifications for the Neuron 6000 Processor.
Table 6. Neuron 6000 Processor Specification Summary
Description Specification
Transmission speed Depends on network transceiver:
• 78 kbit/s for TP/FT-10 channel
• 1250 kbit/s for TP/XF-1250 channel
• See EIA-485 channel specification for
transmission speed characteristics
Voltage for Neuron 6000 Processor 3.3 V ±10%
Operating temperature –40 ºC to +85 ºC
Reflow soldering temperature profile Refer to Joint Industry Standard document
IPC/JEDEC J-STD-020D.1 (March 2008)
Peak reflow soldering temperature 260 ºC
Package type 48-pin QFN
RoHS compliant Yes
EMC Depends on network transceiver
Series 6000 Chip Data Book 11
2
Hardware Resources
This chapter provides an overview of the hardware resources
for an FT 6000 Smart Transceiver and a Neuron 6000
Processor, including the overall chip architecture, memory
interface, operating parameters, pinouts, network
connection, clock requirements, the reset function, and
integrity mechanisms.
Series 6000 Chip Data Book 13
Series 6000 Architecture
The main components of the architecture for a Series 6000 chip, as shown in Figure 3
include:
• CPUs — a Series 6000 chip includes three processors to manage operation of the
chip, the network, and the user application. At higher clock rates, there is also a
separate processor to handle interrupts.
• ROM — a Series 6000 chip includes 16 KB of read-only memory (ROM), which holds
the a system firmware image used for booting a system image from flash.
• RAM — a Series 6000 chip includes 64 KB of random access memory (RAM), which
stores user applications and data. The RAM is partitioned according to a logical
memory map so that the amount that is available for user applications and data is
less than 64 KB. See Memory Map for information about how the RAM is configured.
• Serial memory interface — this interface manages the external non-volatile memory
(NVM) using the serial peripheral interface (SPI).
• Communications port — the communications port provides network access for the
chip. For an FT 6000 Smart Transceiver, this port connects to an FT-X3
Communications Transformer. For a Neuron 6000 Processor, this port connects to an
external transceiver.
• I/O — 12 dedicated I/O pins (see Characteristics of the Digital Pins).
• Clock, reset, and service — on-chip clock, phase-locked loop (PLL), reset, and service-
pin functions.
• JTAG — a Series 6000 chip includes a JTAG (IEEE 1149.1) interface for boundary
scan operations. See JTAG Interface.
The pinout labels shown in Figure 3 are described in Pin Assignments.
14 Hardware Resources
Clock, Reset,
and Service
Serial
Memory
Interface
RAM
(64K x
8
)
I
/
O
Comm
Port
NET CPU
Transformer
or
transceiver
NVM
(
SPI
)
ROM
(16
K x 8
)
JTAG
APP CPU
IRQ CPU
MAC
CPU
XIN
XOUT
RST~
/
/
/
/
12
5
5
6
SVC~
Neuron Processor Architecture
The basic Neuron processor architecture is stack-oriented:
• An 8-bit-wide stack is used for data references, and the arithmetic-logic unit (ALU)
• Another stack stores the return addresses for CALL instructions, and can also be
This stack architecture leads to very compact code. See Assembly Instruction Set for a
summary of the instruction set.
Figure 4 shows the layout of a base page, which can be up to 256 bytes long. Each of the
chip’s processors uses a different base page, whose address is given by the contents of the BP
(Base Page) register of that processor. The top of the data stack is in the 8-bit TOS register,
and the next element in the data stack is at the location within the base page at the offset
given by the contents of the DSP (Data Stack Pointer) register. The assembler shorthand
operates on the TOS (Top of Stack) register and on the next entry in the data stack
(which is in RAM).
used for temporary data storage.
Figure 3. Series 6000 Chip Architecture
Series 6000 Chip Data Book 15
symbol NEXT refers to the next element in the data stack, which is determined by contents
of the location (BP+DSP) in memory, and is thus not an actual processor register.
Figure 4. Base-Page Memory Layout
The data stack grows from low memory towards high memory, and is managed through the
DSP (Data Stack Pointer) register. Pushing a byte of data onto the data stack involves the
following steps:
1. Incrementing the DSP register
2. Storing the current contents of TOS at the address (BP+DSP) in memory
3. Moving the byte of data to TOS
Popping a byte of data from the data stack involves the following steps:
1. Moving TOS to the destination
2. Moving the contents of the address (BP+DSP) in memory to TOS
3. Decrementing the DSP register
The return stack grows from high memory towards low memory, and is managed through the
RSP (Return Stack Pointer) register. Calling a subroutine involves the following steps:
1. Storing the high byte of the instruction pointer (IP) register at the address (BP+RSP)
in memory
2. Decrementing RSP
3. Storing the low byte of IP at the address (BP+RSP) in memory
4. Decrementing RSP
5. Moving the destination address to the IP register
Similarly, returning from a subroutine involves the following steps:
16 Hardware Resources
1. Incrementing RSP
2. Moving the contents of (BP+RSP) to the low byte of the IP register
3. Incrementing RSP
4. Moving the contents of (BP+RSP) to the high byte of IP
The primary programming language used for applications is the Neuron C language, which
is a derivative of the ANSI C language that has been optimized and enhanced for L
distributed control applications. The major enhancements include:
• A network communication model, based on functional blocks and network variables,
that simplifies and promotes data sharing between like and disparate devices.
• A network configuration model, based on functional blocks and configuration
properties, that facilitates interoperable network configuration tools.
• A type model based on standard and user resource files that expands the market for
interoperable devices by simplifying the integration of devices from multiple
manufacturers.
• An extensive set of I/O models that support the I/O capabilities of Neuron Chips and
Smart Transceivers.
• Powerful event-driven programming extensions, based on when statements, that
provide easy handling of network, I/O, and timer events.
ONWORKS
• A high-level programming model that supports application-specific interrupt
handlers and synchronization tools.
See the Neuron C Programmer’s Guide for more information about the Neuron C
programming language. The support for these capabilities is part of the Neuron firmware,
and does not need to be written by the programmer.
Multiple Processors
The Neuron core is composed of four independent logical processors:
• Processor 1 is the Media Access Control (MAC) processor
• Processor 2 is the network (NET) processor
• Processor 3 is the application (APP) processor
• Processor 4 is the interrupt (ISR) processor
The interrupt processor is only available for system clock rates of 20 MHz and higher. At the
two lower system clock rates, interrupts are handled by the application processor. See
Interrupts for more information about interrupts.
The processors share a common memory, arithmetic-logic unit (ALU), and control circuitry.
Each processor has its own set of registers, as listed in Table 7.
Table 7. Register Set
Register Size (Bits) Contents
FLAGS 8 Carry Bit and reserved internal flags
IP 16 Next Instruction Pointer
Series 6000 Chip Data Book 17
MAC
Processor
Network
Processor
Application
Processor
Interrupt
Processor
Shared
Network Buffers Application Buffers
Communications
Port
Input/Output
Register Size (Bits) Contents
BP 16 Address of 256-Byte Base Page
DSP 8 Data Stack Pointer within Base Page
RSP 8 Return Stack Pointer within Base Page
TOS 8 Top of Data Stack, ALU Input
Processor 1 is the MAC layer processor that handles layers 1 and 2 of the seven-layer
®
LonTalk
protocol, which includes driving the communications subsystem hardware and
running the media access control algorithm. The MAC processor communicates with the
NET processor using network buffers located in shared RAM memory, as shown in Figure 5.
Processor 2 is the network processor that implements layers 3 through 6 of the LonTalk
protocol. The NET processor handles network variable processing, addressing, transaction
processing, authentication, background diagnostics, software timers, network management,
and routing functions. The NET processor uses network buffers in shared memory to
communicate with the MAC processor, and application buffers to communicate with the APP
processor. These buffers are also located in shared memory (RAM). Access to the shared
memory is mediated with hardware semaphores to resolve contention when updating shared
data.
Processor 3 is the application processor. The APP processor executes the user-written code,
together with the system services called by user code.
Figure 5. Processor Shared Memory Allocation
18 Hardware Resources
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