Echelon LonWorks LPT-11 User Manual

LONWORKS®

LPT-11 Link Power

Transceiver

User’s Guide

Version 1

@

ECHELON®

C o r p o r a t i o n

078-0198-01A

Echelon,

ONMARK, LonPoint, Neuron, 3120, 3150, and the Echelon logo are

L
trademarks of Echelon Corporation registered in the United States and
other countries. LonSupport and LonMaker are trademarks of Echelon
Corporation

Other brand and product names are trademarks or registered
trademarks of their respective holders.

Neuron Chips, Link Power Twisted Pair Transceiver Modules, and other
OEM Products were not designed for use in equipment or systems
which involve danger to human health or safety or a risk of property
damage and Echelon assumes no responsibility or liability for use of
the Neuron Chips or Link Power Twisted Pair Transceiver Modules in
such applications.

Parts manufactured by vendors other than Echelon and referenced in
this document have been described for illustrative purposes only, and
may not have been tested by Echelon. It is the responsibility of the
customer to determine the suitability of these parts for each
application.

ECHELON MAKES AND YOU RECEIVE NO WARRANTIES OR
CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR IN ANY
COMMUNICATION WITH YOU, AND ECHELON SPECIFICALLY DISCLAIMS
ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A
PARTICULAR PURPOSE.

LON, LONWORKS, LonBuilder, NodeBuilder, LonTalk, LNS,

No part of this publication may be reproduced, stored in a retrieval
system, or transmitted, in any form or by any means, electronic,
mechanical, photocopying, recording, or otherwise, without the prior
written permission of Echelon Corporation.

Printed in the United States of America.
Copyright ©2003 by Echelon Corporation.

Echelon Corporation
www.echelon.com

1 Introduction 1-1

Applications 1-3

Audience 1-5

Content 1-5
Related Documentation 1-6

2 Electrical Interface 2-1

LPT-11 Pinout 2-2
Network Connection 2-4
Clock Input 2-4
Neuron® Chip Communications Port (CP) Lines 2-4
PC Board Layout Guidelines 2-4
Choosing the Inductor and Capacitors for the LPT-11 Switching Power
Supply 2-7
Alternative Inductor and Capacitor Selection for Low-Current
Applications 2-9

3 Mechanical Considerations 3-1

Mechanical Footprint 3-2

4 Power Output 4-1

Transceiver Output Power 4-2

Powering Non-Isolated Devices 4-4

5 Network Cabling and System Performance 5-1

Network Overview 5-2

System Performance and Cable Selection 5-4
System Specifications 5-5
Transmission Specifications 5-5
Power Specifications, Simplified Form 5-6
Power Specifications for Extended Performance 5-8

Cable Termination 5-13

Commissioning LPT-11 Transceivers 5-13

Contents

LONWORKS LPT-11 Transceiver User’s Guide iii

6 Design Issues 6-1

EMI Design Issues 6-2

Designing Systems for EMC (Electromagnetic Compatibility) 6-2
ESD Design Issues 6-5
Designing Systems for ESD Immunity 6-5
Surge Design Issues 6-6
Designing Systems for Surge Immunity 6-6
Building Entrance Protection 6-7

EN 61000-4 Electromagnetci Compatibility (EMC) Testing 6-8

7 Programming Considerations 7-1

Application Program Development and Export 7-2

LonBuilder® Developer's Workbench 7-2
Development Hardware Setup 7-2
Release Hardware Setup 7-4
NodeBuilder® Development Tool 7-5
Development Hardware Setup 7-5

Release Hardware Setup 7-5

8 References 8-1

Reference Documentation 8-2

Appendix A - Physical Layer Repeaters A-1

Physical Layer Repeaters A-2

Appendix B - Differences Between LPT-10 and LPT-11 B-1

Differences Between LPT-10 and LPT-11 Link Power Transceivers B-2

Functional Differences B-2
Differences in Form B-2
Modifications for Migrating from the LPT-10 to the LPT-11 Transcevier B-3

Appendix C - LPT-11 Transceiver-Based Device Checklist C-1

LPT-11 Transceiver-Based Device Checklist C-2

LPT-11 Transceiver and Neuron Chip Connections C-2
LPT-11 PCB Layout C-2

LPT-11 DC-DC Converter C-3
LPT-11 Transient Immunity C-4
LPT-11 Transceiver Programming C-4
Link Power Network Considerations C-4
LPT-11 Physical Layer Repeater C-5

iv Contents

1

Introduction

The LPT-11 Link Power Twisted Pair Transceiver provides a simple,
cost effective method of adding a network-powered LONWORKS

®

transceiver to any Neuron
lighting device, or general purpose I/O controller. The LPT-11
transceiver consists of a Single In-Line Package (SIP) containing a
78kbps differential Manchester coded communication transceiver, a
switching power supply that draws power from the twisted pair
network, and connections for the Neuron Chip Communications Port
(CP) lines and the twisted pair network. The LPT-11 transceiver
eliminates the need to use a local power supply for each device, since
device power is supplied by a central power supply over the same
twisted wire pair that handles network communications. Up to 128
devices can be supported on a single free topology network segment.

Chip-based sensor, activator, display,

LONWORKS LPT-11 Transceiver User’s Guide 1-1

The LPT-11 transceiver supports free topology wiring, freeing the system installer
from the need to wire in a doubly-terminated bus arrangement. Star, bus, and loop
wiring are all supported by this architecture. Free topology wiring reduces the time
and expense of system installation by allowing the wiring to be installed in the most
expeditious manner. It also simplifies network expansion by alleviating the need for
the installer to follow strict rules about stub lengths. Should it be necessary to add
more devices or wire in excess of the system limits, then two or more link power
systems can be interconnected with an inexpensive, physical layer repeater. The
LPT-11 contains built-in circuitry to allow connection to one or more FTT-10A
transceivers back-to-back to make a repeater. The LPT-11 transceiver includes an
integral switching power supply that can furnish +5VDC at up to 100mA. The LPT­11 transceiver derives its power directly from the switching power supply, leaving up
to 100mA of current for a Neuron Chip, application electronics, sensors, actuators,
and displays. The high current capability of the LPT-11 transceiver eliminates the
need for local power supplies at each device, resulting in equipment and labor cost
savings.

The LPT-11 transceiver is compatible with Echelon's FTT-10A Free Topology

Transceiver and FT 3120
31xx devices), and these transceivers can communicate with each other on a single
twisted pair cable. This capability provides an inexpensive means of interfacing to
devices whose current and/or voltage requirements would otherwise exceed the
capacity of the link power segment. When equipped with an FTT-10A or FT 31xx
transceiver, these devices can be operated from a local power supply without the
need for additional electrical isolation from the link power network.

®

/FT 3150® Smart Transceivers (referred to hereafter as FT

Using the LPT-11 transceiver can save literally thousands of hours of development
time compared with a custom-designed transceiver. The LPT-11 transceiver is
designed to comply with FCC, CE, ICES-003, CISPR22, EN55022, EN55024, and
EN61000-4 EMC requirements, minimizing time consuming and expensive laboratory
transceiver testing. As a UL, cUL, and TuV recognized component, the LPT-11
transceiver can be integrated into a product with minimal additional safety testing of

the LPT-11 transceiver module. The LPT-11 transceiver also meets L
interoperability standards.

ONMARK

®

1-2 Introduction

Applications

A conventional control system using bus topology wiring (such as RS-485) consists of
a network of sensors and control outputs that are interconnected using a shielded
twisted pair wire. In accordance with EIA RS-485 guidelines, all of the devices must
be wired in a bus topology to limit electrical reflections and ensure reliable
communications. There is a high cost associated with installing and maintaining the
cable plant that links together the many elements of an RS-485-based control
system. Bus topology wiring is more time consuming and expensive to install
because the installer is unable to branch or star the wiring where convenient; all
devices must be connected directly to the main bus. The installation of local power
supplies for each device is especially expensive since it usually involves an AC mains
connection.

Installing separate data and power wiring also implies that a technician's time will
be spent troubleshooting the wiring harness to isolate and repair cable faults.
Moreover, each time a sensor is added or an actuator is moved, both data and power
wiring must be changed accordingly, often resulting in network down time until the
new connections can be established.

The best solution for reducing installation and maintenance costs and simplifying
system modifications is a free topology communication system that combines power
and data on a common twisted wire pair. Echelon's link power technology offers just
such a solution, and provides an elegant and inexpensive method of interconnecting
the different elements of a distributed control system.

The link power system sends power and data on a common twisted wire pair, and
allows the user to wire the control devices with virtually no topology restrictions.
Power is supplied by a customer-furnished nominal 48VDC power supply, and flows
through an LPI-10 Power Supply Interface onto the twisted pair wire (figure 1.1).
The LPI-10 module isolates the power supply from wiring faults on the twisted pair,
couples power to the system wiring, and terminates the twisted pair network.

There are two versions of the LPI-10 interface: a simple, low-cost, inductor-based
design intended for customers who are building power supplies, and an electronic
LPI-10 interface designed for use with off-the-shelf 48VDC power supplies.

LONWORKS LPT-11 Transceiver User’s Guide 1-3

Figure 1.1 Free Topology Link Power System Example

LPT-11 Link Power Transceivers located along the twisted wire pair include integral
switching power supplies. These supplies regulate the voltage on the twisted pair
down to +5VDC at currents up to 100mA for use by the Neuron Chip and the various
sensors, actuators, and displays. If a high current or high voltage device must be
controlled, then the +5VDC power can be used to trigger an isolating high current
triac, relay, or contactor.

The integral power supply does away with the need for a local AC-to-DC power
supply, charging circuit, battery, and the related installation and labor expenses.
The savings in money and time that results from eliminating the local power supply
can be up to 20% of the total system cost; the larger the system, the greater the
savings. Moreover, if standby batteries are used, then additional savings will be
realized throughout the life of the system, since only one set of batteries will require
service.

The link power system uses a single point of ground, at the LPI-10 module, and all of
the LPT-11 transceivers electrically float relative to the local ground. Differential
transmission minimizes the effects of common mode noise on signal transmission. If
grounded sensors or actuators are used, then either the communication port (CP) or
the I/O lines of the Neuron Chip must be electrically isolated.

Unlike bus wiring designs, the link power system uses a wiring scheme that supports
star, loop, and/or bus wiring (figure 1.2). This design has many advantages:

1. The installer is free to select the method of wiring that best suits the installation,
reducing the need for advanced planning and allowing last minute changes at
the installation site.

1-4 Introduction

2 If installers have been trained to use one style of wiring for all installations, free

topology technology can be introduced without requiring retraining.

3. Retrofit installations with existing wiring plants can be accommodated with
minimal rewiring, if any. This capability ensures that FT 3120 and FT 3150
Smart Transceiver technology can be adapted to both old and new projects.

4. Free topology permits FT 3120 and FT 3150 Smart Transceiver systems to be
expanded in the future by simply tapping into the existing wiring where it is
most convenient to do so. This reduces the time and expense of system
expansion, and from the customer's perspective, keeps down the life cycle cost of
the free topology network. See Chapter 5, Network Cabling and Performance, for
a presentation of the five different network topologies.

System expansion is simplified in another important way, too. Each link power
transciever incorporates a repeater function. If a link power system grows beyond
the maximum number of transceivers or total wire distance, then additional link
power systems can be added by interconnecting transceivers using the repeater

function. The repeaters will transfer LonTalk® packets between the two systems,
doubling the number of transceivers as well as the length of wire over which they
communicate. The repeater function permits a link power system to grow as system
needs expand, without retrofitting existing controllers or requiring the use of
specialized bridges. Note that systems requiring high levels of network traffic may
benefit from the use of L
necessary. See Appendix A for more details.

ONWORKS routers which forward packets only when

Audience

This user guide is for developers of Link Power Transceiver-based LONWORKS
devices and systems.

Content

This manual provides detailed technical specifications on the electrical and
mechanical interfaces and operating environment characteristics for the LPT-11
transceiver module.

This document also provides guidelines for migrating applications from a
LonBuilder® Developer’s Workbench Emulator or NodeBuilder® Developer's Tool to
a transceiver module-based product design. Vendor sources are included to simplify
the task of integrating the transceiver module with application electronics.

LONWORKS LPT-11 Transceiver User’s Guide 1-5

Related Documentation

The following Echelon documents are suggested reading:

LonBuilder User's Guide (078-0001-01)

NodeBuilder User's Guide (078-0141-01)

Neuron C Programmer's Guide (078-0002-01)

LonBuilder Startup and Hardware Guide (078-0003-01)

L

ONWORKS LPI-10 Link Power Interface Module User's Guide (078-0104-01)

L

ONWORKS FTT-10A Free Topology Transceiver User's Guide (078-0156-01)

FT 3120/FT 3150 Smart Transceiver Data Book (005-0139-01)

L

ONWORKS Product Catalog (Catalog/Spring02)

1-6 Introduction

2

Electrical Interface

The LPT-11 Link Power Transceiver’s 14 pins provide a polarity
insensitive connection to the twisted pair network, an interface to the
Neuron Chip communications port, and a switching power supply.

LONWORKS LPT-11 Transceiver User’s Guide 2-1

LPT-11 Pinout

The pinout of the LPT-11 transceiver is shown in table 2.1. The interconnection
between the LPT-11 and a Neuron Chip is shown in the block diagram in figure 2.1.
See figure 3.1 for the physical location of pin 1.

Name Pin# Function

NET_A 1 Connection to TP network, polarity insensitive
NET_B 2 Connection to TP network, polarity insensitive
V+ 3 Power supply input voltage (≈ 35VDC)
INDUCTOR 4 Power supply inductor connection
Vcc 5 +5VDC power output

GND 6 Power supply ground
CLK 7 Transceiver clock input from Neuron Chip
NC 8 No Connect (not connected internally)
TXD 9 Neuron Chip CP1
RXD 10 Neuron Chip CP0
NC 11 No Connect (not connected internally)
NC 12 No Connect (not connected internally)
NC 13 No Connect (not connected internally)
NC 14 No Connect (not connected internally)

Table 2.1 LPT-11 Transceiver Pinout

2-2 Electrical Interface

NET_A

To

Network

C1

NET_B

V+

INDUCTOR

Vcc

GND

CLK

NC

TXD

RXD

NC

NC

NC

NC

C3

L1

C2

GROUND GUARD

+5V

GND

+5V

CLOCK

CIRCUIT

CLK2 CLK1

CP1

CP0

CP2

CP3

IO0 - IO10

LPT-11

Link Power

Transceiver

To
Application
Electronics

Neuron 3120
or 3150 Chip

Figure 2.1 LPT-11 Transceiver-to-Neuron Chip Interconnections

LONWORKS LPT-11 Transceiver User’s Guide 2-3

Network Connection

The network connection (NET_A and NET_B) is polarity insensitive, and therefore
either of the two twisted pair wires can be connected to either of the two NET pins.
Details on network wiring are discussed in Chapter 5.

Transient protection may be required to protect the LPT-11 transceiver against
surge voltages resulting from network transients and lightning strikes. Details on
surge protection are discussed in Chapter 6.

Clock Input

The LPT-11 transceiver receives its clock input from the Neuron Chip via the CMOS
input CLK pin. This pin is driven by the CLK2 output of the Neuron Chip, whether
the Neuron Chip's oscillator or an external clock oscillator is used. Clock traces
should be kept short (≤2cm) to minimize noise coupling.

The LPT-11 transceiver can operate at 20, 10, 5, or 2.5MHz. Operation at 2.5MHz
does not comply with L

1.25 MHz operation is not supported. The operating frequency is automatically
detected on the CLK pin.

ONMARK interoperability guidelines for the TP/FT-10 channel.

Neuron Chip Communications Port (CP) Lines

The LPT-11 transceiver transmits and receives LonTalk® network packets via the
Neuron Chip's direct, single-ended mode over CP0-1. CP0 is the data input to the
Neuron Chip and is connected to the LPT-11 transceiver's RXD pin. CP1 is the data
output from the Neuron Chip and is connected to the TXD pin. These connections
are summarized in table 2.2.

Table 2.2 Neuron Chip

Neuron Chip Pin Neuron Chip Function LPT-11 Pin

CP0 Data input RXD

CP1 Data output TXD

CP Line Connections

PC Board Layout Guidelines

The recommended PC board layout for the LPT-11 transceiver and its external
components is shown in figure 2.2.

2-4 Electrical Interface

Variations on this suggested PC board layout are possible as long as the general
principles of grounding, shielding, guarding, and spacing are employed. For
example, using a suitable fixture, the LPT-11 transceiver pins can be formed into a
right angle before the transceiver is soldered onto the PC board. In this case, the
layout in figure 2.2 would be modified to accommodate horizontal (90°) mounting of
the transceiver. If the transceiver is bent to the left in figure 2.2, then C1 should be
moved up and to the right, above L1. L1 and C2 can shift down slightly to minimize
the trace lengths for L1, C1 and C2 in this variation on the original layout. Note
that the ground plane on the solder side of the board becomes more important in this
variation since the ground pin of C1 is now on the right-hand side of the transceiver,
and a low-impedance path between the ground pins for C1 and C2 is needed.

NETWORK

CONNECTOR

L1

C1

Figure 2.2

C2 C3

+5V

GROUND

LPT-11

CLK

Neuron Chip

and

Application Electronics

Recommended PC Board Layout for LPT-11 Transceiver

LONWORKS LPT-11 Transceiver User’s Guide 2-5

Figure 2.2 illustrates the connections between the LPT-11 transceiver and its four
power supply-related components on one layer of a two-layer PC board. The other
layer (generally the solder side of the board) should contain as much ground plane as
possible.

The switching power supply circuit in the LPT-11 transceiver uses the external
components L1, C1, and C2 as part of its switching regulator. Because moderate
currents are switched at approximately 140kHz, it is very important that L1, C1, and
C2 are placed close to the LPT-11 transceiver and oriented as shown in the figure.
The inductor L1 and the capacitors C1 and C2 should be placed with minimum gaps
to the body of the transceiver. If L1 has exposed ferrite, care should be taken to
avoid contact between L1 and the LPT-11 SIP.

The ground connections between the LPT-11 transceiver and L1, C1, and C2 should
be as similar as possible to those shown in figure 2.2. The wide ground traces and
the ground plane on the other layer of the board serve two functions. First, the wide
ground traces reduce inductance to provide a low-impedance path for the power
supply switching currents. Second, the wide ground areas minimize electric and
magnetic field noise generated by the power supply circuit. The “INDUCTOR” trace
from pin 4 of the LPT-11 transceiver to the input of inductor L1 can have voltage
signals as high as 35Vp-p at 140kHz. This DC-DC switching waveform may generate
moderate levels of electric field noise that can capacitively couple into any nearby
high-impedance circuitry. The ground plane is shown close to the “INDUCTOR”
trace in order to absorb some of the electric field noise generated by the trace.

Note that L1 is shown in figure 2.2 with a dot marking that is oriented toward the
transceiver. In the Taiyo-Yuden LHL08 series of inductors, the dot identifies which
pin is connected to the inner portion (beginning) of the cylindrical wire winding on
the ferrite slug. Since the input to L1 is a 35V switching waveform and the output is
a smooth +5VDC, it is best to orient the inductor so that the windings with the noisy
35V switching waveform are in the inner part of the inductor coil. This uses the
inductor coils themselves as part of the electric field shielding. Consult the
manufacturer’s data sheet for the inductor you are using to determine if polarity
marking is available, and whether the marked pin is connected to the inner or outer
portion of the coil winding.

If inductor L1 is an “open slug” type without shielding, it often can generate
moderate levels of magnetic field noise during normal power supply operation.
Ground guarding and a ground plane on the other PC board layer will help to contain
the magnetic field noise in a smaller volume near L1. Since the switching frequency
of the power supply is near 140kHz, the copper ground plane serves as a fairly
effective magnetic field shield.

The electric and magnetic field noise generated by any switching power supply
circuit may interfere with the operation of sensitive circuitry nearby. The magnetic
field noise can be minimized by using a toroidal inductor for L1, or by using a slug
inductor with an integral magnetic shield. Sensitive circuits on a link power device
should be laid out to minimize the loop area of any amplifier inputs or high­impedance lines. Minimizing these loop areas reduces the amount of voltage that
can be induced in the circuits from the magnetic switching noise that is present.
Note that the traces from the network connector to the LPT-11 transceiver as shown

2-6 Electrical Interface

in figure 2.2 are spaced as closely together as possible in order to minimize their loop
area. Circuits that are sensitive to electric field noise should be kept away from L1
and pin 4 of the transceiver, and ground guarding should be employed to shield them
from the electric field noise.

The +5VDC Vcc trace and GROUND trace are shown leading away from the
transceiver into the general board area for the Neuron Chip and application circuit.
The Vcc and GROUND should be routed directly off the C2 capacitor to the device's
circuitry, as shown. The ground guarding around the network connector should not
be used as a source of ground for the digital circuitry. C3 is a small 0.1µF decoupling
capacitor that should be placed near C2 to minimize switching noise.

The CLK input to the LPT-11 transceiver (pin 7) needs to be guarded by ground traces
to minimize clock noise, and to help keep EMI levels low (see Chapter 6). In general,
the

Neuron 3120 or 3150 Chip should be placed close enough to the LPT-11 transceiver

and oriented correctly so that the CLK trace from the Neuron Chip to the transceiver
is no longer than 2cm. At the same time, the Neuron
circuitry should be kept away from the network connector and NET_A/NET_B pins
(pins 1 and 2) on the transceiver. If noisy digital circuitry is located too close to the
network connector or wires, RF noise may couple onto the network cable and cause
EMI problems. With these constraints in mind, it is apparent that the best place to
locate the Neuron Chip is in the lower right corner of figure 2.2, with an orientation
that places the Neuron Chip’s CLK2 line closest to the transceiver's CLK input pin.
This position and orientation work well for both the Neuron
since the CP lines are oriented near the lower portion of the LPT-11 transceiver for the
rest of the interconnections.

Chip and any other fast digital

3120 and 3150 Chips,

Choosing the Inductor and Capacitors for the LPT-11
Switching Power Supply

Parts that are chosen for L1, C1, and C2 must meet several key specifications to
ensure that the switching power supply conversion performed by the LPT-11
transceiver stays within specified limits. As long as these key specifications are met,
the designer of a link power device is free to choose parts that have other
specifications that best match the application. These specifications allow up to
100mA of sustained peak current to be drawn by the application, including the
Neuron Chip. Component selection for low-current applications is discussed in the
next section.

Suitable parts for inductor L1 are listed in table 2.3. L1 has the following key
specifications that must be met over the device's operating temperature range:
L = 1mH ±10%, DCR ≤4Ω, I

current at which the measured inductance has not fallen below 80% of its low
frequency value, e.g., 800µHenries at 800kHz.

≥200mA, F

sat

res ≥ 800KHz. Isat

is defined as the DC

LONWORKS LPT-11 Transceiver User’s Guide 2-7

Table 2.3 Examples of L1 Inductor Selections for Consideration (1mH)

Manufacturer

(Series)

Taiyo-Yuden (LHL08) LHL08-102J -40°C to +85°C *

TDK (TSL) TSL0808-102KR26 -40°C to +85°C

The inductors in table 2.3 are unshielded. For compact designs where the
components are located very close to one another, Echelon recommends using a
shielded construction for L1, in order to minimize the magnetic field interference on
nearby transformers, e.g., the FTT-10A transceiver. Contact your inductor
manufacturer for availability.

Suitable parts for the V+ input capacitor C1 are listed in table 2.4. C1 has the
following specifications that must be met over the device's operating temperature
range: C = 100µF ±20%, DCWV ≥63V, I

recommends the use of a high temperature rated capacitor (105°C minimum) due to
the increased component operating life available with this type of construction. The
application should determine the need for the extra expense.

Table 2.4 Examples of C1 Capacitor Selections (100µF, ≥63V) For Consideration

Manufacturer

(Series)

Panasonic EEUFC1J101 -40°C to +85°C

Vishay EKE00DC310J00 -40°C to +85°C

Part Number Temperature

Range

≥100mA

ripple

Part Number Temperature

@ 100kHz. Echelon

rms

Range

Manufacturers for the Vcc output capacitor C2 are listed in table 2.5. C2 has the
following key specifications that must be met over the device's operating
temperature range: C = 22µF ±20%, DCWV ≥ 10V DC Minimum, I

@ 100kHz, ESR (equivalent series resistance) ≤ 1.2Ω Maximum @ 100kHz. Echelon
recommends the use of a high temperature rated capacitor (105°C minimum) due to
the increased component operating life available with this type of construction. The
application should determine the need for the extra expense. Note that the DCWV of
capacitors that can meet the ESR requirement are typically rated at greater than 50
VDC. C3 is a small 0.1µF decoupling capacitor that should be placed near C2 to
minimize switching noise.

Table 2.5 Examples of C2 Capacitor Selections (22µF, ≥10V, Low ESR) for

Consideration

Manufacturer

(Series)

Vishay EKE00AA222H00 -40°C to +85°C

Nichicon (PL) UPW1A220MHD -40°C to +85°C

Part Number Temperature

Range

ripple

≥ 200mA

rms

2-8 Electrical Interface

Alternative Inductor and Capacitor Selection for Low­Current Applications

For applications which require no more than 25mA DC of sustained current, such as
a single physical layer repeater using an LPT-11 back-to-back with an FTT-10A,
smaller, less-costly surface mount components for L1, C1, and C2 may be
substituted for those components noted above. These components should have
ratings of -40°C to +85° C minimum. For the C1 and C2 components, Echelon
recommends the use of a high temperature rated capacitor (105°C minimum) due to
the increased component operating life available with this type of construction.

Table 2.6 Optional Component Selection for Low-Current Applications (up to 25mA)

Component Description

L1 1.0mH, 50mA, 25Ω

C1 22µF, 50V tantalum, 25 mA

C2 22µF, 10V tantalum

LONWORKS LPT-11 Transceiver User’s Guide 2-9

2-10 Electrical Interface

3

Mechanical Considerations

This chapter discusses the mechanical footprint and connectors of the
LPT-11 Link Power Transceiver. Details of mounting the transceiver
to an application electronics board containing a Neuron Chip
provided.

are

LONWORKS LPT-11 Transceiver User’s Guide 3-1

Mechanical Footprint

The LPT-11 transceiver mechanical dimensions are shown in figure 3.1. The
LPT-11 transceiver is generally mounted to the application board as a through-hole,
soldered component. Decisions about component placement on the application
electronics board must also consider electromagnetic interference (EMI) and
electrostatic discharge (ESD) issues as discussed in Chapter 6 of this document.

Figure 3.1 shows the maximum height of the LPT-11 transceiver as it is shipped
from the factory. The user has the option of constructing a fixture to bend the
connector pins to reduce the overall height of the printed circuit board assembly on
which the transceiver is mounted.

The LPT-11 has a notch on the top edge above Pin 1, as shown in figure 3.1. The
fourteen connector pins are fabricated of solder tinned steel alloy.

3-2 Mechanical Considerations

Figure 3.1 LPT-11 Transceiver Mechanical Footprint

4

Power Output

This section describes the power supply portion of the LPT-11 Link
Power Transceiver, and provides suggestions for using the 5V output
current.

LONWORKS LPT-11 Transceiver User’s Guide 4-1