Diodes AP9050 User Manual
AP9050
PROTECTION INTERFACE for PMICs with
INTEGRATED OVP CONTROL
Description
AP9050 is designed to protect the latest generation of PMICs
for portable applications such as UMPCs, smartphones and
others utilizing battery power.
The integrated LDO allows the PMIC to power up and
determine whether the connected power supply (USB or
AC-DC wall adapter) is valid and a safe operation can be
performed.
The PMIC controls the operation of the integrated n-channel
MOSFET to either pass the line voltage or disconnect the line
from the PMIC to protect its internal circuits in the event of an
over-voltage.
The AP9050 is available in a low-profile U-DFN2020-6
package.
NEW PRODUCT
Features
• Input Supply Range from 3V to 30V
• Lower Power Dissipation and Higher Efficiency as
compared to a Zener Shunt Regulator
• LDO is stable without a bypass capacitor on the output
and operates across the temperature range
• Available in a U-DFN2020-6 package with a typical
height of 0.575mm
Note: 1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website at
http://www.diodes.com/products/lead_free.html.
Pin Assignments
Applications
• Power Interface for New Generation PMICs
• Charger Front End Protection
• Smartphone
• Cell Phone
• Ultra Mobile PC
• Tablets
(Top View)
1
2
3
8
7
U-DFN2020-6
6
5
4
Typical Application Circuit
AP9050
Document number: DS35283 Rev. 1 - 2
Figure 1. Typical Application Circuit
1 of 9
www.diodes.com
March 2011
© Diodes Incorporated
PROTECTION INTERFACE for PMICs with
Pin Descriptions
Pin # Name Description
1 Source Source of the n-channel power FET. Pass-switch’s output pin.
2 Gate Gate of the FET switch. Pass-switch’s control pin.
V
V
IN
OUT
Input voltage to the internal LDO.
Output of the LDO.
3, 7
4 Ground LDO ground connection.
5
6, 8 Drain Drain of the power FET. Pass-switch’s input pin.
Functional Block Diagram
AP9050
INTEGRATED OVP CONTROL
NEW PRODUCT
Figure 2. Functional Block Diagram
AP9050
Document number: DS35283 Rev. 1 - 2
2 of 9
www.diodes.com
March 2011
© Diodes Incorporated
PROTECTION INTERFACE for PMICs with
INTEGRATED OVP CONTROL
Absolute Maximum Ratings (Note 2, 3)
Symbol Parameter Rating Unit
VIN
VGS
I
Dpk
ID
P
max
TJ
NEW PRODUCT
Semiconductor devices are ESD sensitive and may be damaged by exposure to ESD events. Suitable ESD precautions should be taken when handling and
transporting these devices.
Notes: 2. Exceeding these ratings may damage the device.
3. Mounted on FR4 Board using 30 mm
TJ
TL
4. Dual die operation (equally−heated).
Supply Voltage
Gate-to-Source Voltage ±12 V
Drain Current, Peak (10µs pulse) 19 A
Drain Current, Continuous
(Note 4, Steady-State)
= 25ºC
T
A
T
= 85ºC
A
Total Power Dissipation @ TA = 25°C
(Note 3, 4)
Junction Temperature Range −40 to +125 °C
Non-operating Temperature Range −55 to +150 °C
Maximum Lead Temperature for Soldering
Purposes
2
, 2 oz Cu.
−0.3 to 30
3.7
2.7
750 mW
260 °C
AP9050
V
A
Thermal Resistance
Symbol Parameter Rating Unit
θ
JA
θ
JC
Note: 5. Test condition for DFN2020-6: Mounted on FR4 Board using 30 mm2, 2 oz Cu.
Junction to Ambient (Note 5) 132 °C/W
Junction to Case 13 °C/W
Recommended Operating Conditions (Note 6)
Symbol Parameter Min Max Unit
VIN
TA
Note: 6. The device function is not guaranteed outside of the recommended operating conditions.
Supply Voltage
Operating Ambient Temperature Range
3
−40
30 V
+85 °C
AP9050
Document number: DS35283 Rev. 1 - 2
3 of 9
www.diodes.com
March 2011
© Diodes Incorporated
Loading...