ConnectCore™ 9M 2443
and Wi-9M 2443
Hardware Reference
90000952_B
Release date: August 2009
©2009 Digi International Inc.
All rights reserved.
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Information in this document is subject to change without notice and does not represent a commitment on the part
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This product could include technical inaccuracies or typographical errors. Changes are periodically made to the
information herein; these changes may be incorporated in new editions of the publication.
www.digiembedded.com
ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
This guide provides information about the Digi ConnectCore 9M 2443 embedded
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core module family. Visit the Digi support website:
www.digiembedded.com/support.
To access current technical documentation available for the S3C2443 processor,
please visit the Samsung website.
. . . . .
Conventions used
in this guide
This table describes the typographic conventions used in this guide:
This convention Is used for
italic type Emphasis, new terms, variables, and document titles.
monospaced type Filenames, pathnames, and code examples.
Digi information
Documentation
updates
Please always check the product specific section on the Digi support website for the
most current revision of this document: www.digiembedded.com/support.
Change Log
Revision B Added WLan information for the ConnectCore Wi-9M 2443.
Added WLan information under environmental specifications in Appendix A.
Added a new drawing on page 136.
Made minor document updates.
www.digiembedded.com
Chapter 1
Contact
information
For more information about your Digi products, or for customer service and
technical support, contact Digi International.
To contact Digi International by Use
Mail Digi International
11001 Bren Road East
Minnetonka, MN 55343
U.S.A
World Wide Web http://www.digiembedded.com/support/
email http://www.digiembedded.com/support/
Telephone (U.S.) (952) 912-3444 or (877) 912-3444
Telephone (other locations) +1 (952) 912-3444 or (877) 912-3444
6 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Contents
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. . . . . . .
Change Log....................................................................................... 5
Revision B ................................................................................. 5
Chapter 1:
Features and functionality ...................................................................12
Block diagrams .................................................................................16
Detailed module description .................................................................18
Memory ..........................................................................................23
Configuration pins - CPU module ............................................................24
Chip selects .....................................................................................25
Multiplexed GPIO pins .........................................................................26
Interfaces ....................................................................................... 32
About the Module ............................................................... 12
CPU........................................................................................16
Module .................................................................................... 17
Configuration ............................................................................18
Power Supply ............................................................................ 18
Power management.....................................................................19
NORMAL mode ...........................................................................20
IDLE mode ................................................................................20
STOP mode ...............................................................................20
SLEEP mode ..............................................................................20
Wake-up event ..........................................................................21
Reset ......................................................................................22
DDR SDRAM memory ....................................................................23
NAND Flash memory ....................................................................23
Chip select memory map ..............................................................25
S3C2443X Port Configuration..........................................................26
RTC ........................................................................................32
UART interface ..........................................................................32
SPI interface .............................................................................34
I2C interface .............................................................................35
USB interface ............................................................................35
Ethernet interface ......................................................................36
WLAN interface..........................................................................37
A/D converter and touch screen interface..........................................37
Touch screen interface modes ........................................................37
Reset controller .........................................................................38
Chapter 2
JTAG ......................................................................................38
Common features .......................................................................38
Watchdog timer .........................................................................39
IIS-Bus interface .........................................................................39
IIS block diagram: .......................................................................40
IIS-Bus format............................................................................40
Camera interface........................................................................41
.............................................................................................41
AC97 Controller..........................................................................42
SD host interface ........................................................................44
PWM timer................................................................................44
Clock output .............................................................................45
CF/ATA....................................................................................45
PC card controller.......................................................................46
ATA controller ...........................................................................46
High-speed MMC .........................................................................46
High speed SPI ...........................................................................47
External address/data bus.............................................................47
WLAN connectors........................................................................47
LCD controller display features ..............................................................49
STN LCD displays ........................................................................49
TFT LCD displays ........................................................................49
Common features .......................................................................49
Module pinout ..................................................................................50
System connector X1 ...................................................................50
System connector X2 ...................................................................56
Configuration pins - CPU ......................................................................61
Chapter 2:
About the Development Board .........................................62
What’s on the development board? ..................................................62
The development board................................................................63
User interface ..................................................................................64
Power management.....................................................................64
General information ...........................................................................64
Power supply.............................................................................64
3.3VDC power controller - VLIO.......................................................65
Power LEDs ...............................................................................65
Coin cell for RTC ........................................................................65
Current measuring option..............................................................65
Reset ......................................................................................65
JTAG interface ..........................................................................65
I²C interface .............................................................................65
PoE connectors ..........................................................................65
Peripheral application connector.....................................................66
LCD Application Kit Connector ........................................................66
8 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
VGA interface ........................................................................... 66
UARTs .................................................................................... 66
UART A - console ....................................................................... 66
UART B - UART / MEI................................................................... 66
UART C - TTL interface ................................................................ 66
UART D - TTL interface ................................................................ 66
SPI interface(s) ......................................................................... 67
Camera interface.............................................................................. 68
Switches and push-buttons .................................................................. 69
Reset control, S1 ....................................................................... 69
Power switch, S2 ....................................................................... 69
Legend for multi-pin switches........................................................ 70
Module configuration switches, S4................................................... 70
Serial port B MEI configuration switches............................................ 70
Test points ..................................................................................... 71
Numbers and description.............................................................. 71
Factory default interface configuration for development board ...................... 72
LEDs ............................................................................................. 73
WLAN, LE10.............................................................................. 73
Power LEDs, LE1, LE4, and LE7....................................................... 73
User LEDs, LE5 and LE6 ................................................................ 74
Serial status LEDs....................................................................... 74
Status LEDs Serial port A .............................................................. 75
Status LEDs Serial port B .............................................................. 75
Debug, LE3 .............................................................................. 75
Battery and battery holder .................................................................. 76
Serial UART ports.............................................................................. 77
Serial port A, RS232, X27.............................................................. 77
Serial port B, MEI interface, X16..................................................... 79
Serial port C, TTL interface, X19 .................................................... 79
Serial port D, TTL interface, X22 .................................................... 80
I2C interface ................................................................................... 81
I2C connector, X22 ..................................................................... 81
SPI interface ................................................................................... 82
X8-SPI connector........................................................................ 83
Current Measurement Option................................................................ 84
Measurement options .................................................................. 84
How the CMO works .................................................................... 85
PoE module connectors - IEEE802.3af...................................................... 86
The PoE module ........................................................................ 87
PoE connector (power in), X17 ....................................................... 87
PoE connector (power out), X26 ..................................................... 87
POE_GND................................................................................. 87
VGA connector ................................................................................. 88
VGA connector, X18.................................................................... 88
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www.digiembedded.com 9
Chapter 2
USB connectors .................................................................................90
USB device connector, X15 ............................................................90
USB host connector, X14 ...............................................................90
Digital I/O .......................................................................................91
I2C digital I/O expansion, X44 ........................................................91
JTAG interface .................................................................................92
Standard JTAG ARM connector, X13..................................................93
Peripheral (extension) headers ..............................................................94
LCD application header, X5............................................................95
Peripheral application header, X3....................................................96
Module connectors and signal rails ..........................................................97
Signal rails................................................................................97
X10 pinout ................................................................................98
X11 pinout ................................................................................99
X20 pinout .............................................................................. 100
X21 pinout .............................................................................. 101
Power connector ............................................................................. 102
Jumpers ....................................................................................... 103
Jumpers................................................................................. 104
Ethernet interface ........................................................................... 105
RJ-45 pin allocation, X7 .............................................................. 106
WLAN Interface............................................................................... 108
Interfaces without special connectors.................................................... 109
ADC signals ............................................................................. 109
CF signals ............................................................................... 109
I2S/AC97 signals ....................................................................... 110
SPI1 signal .............................................................................. 110
Module and test connectors ................................................................ 111
X1 pinout ............................................................................... 111
X2 pinout ............................................................................... 121
Network interface ........................................................................... 128
WLAN interface............................................................................... 128
Environmental specifications............................................................... 130
ConnectCore
9M 2443 ................................................................................. 130
ConnectCore
Wi-9M 2443 ............................................................................. 130
Thermal specifications ...................................................................... 131
Standard Operating Temperature Ranges ......................................... 131
recommendations ..................................................................... 132
Power requirements ......................................................................... 133
Typical Power Requirements ............................................................... 133
ConnectCore 9M 2443 ................................................................ 133
ConnectCore “Wi-9M 2443”.......................................................... 134
Mechanical specifications................................................................... 136
10 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
ConnectCore 9M 2443................................................................. 136
ConnectCore
Wi-9M 2443 ............................................................................. 138
Connector Reference Parts ................................................................. 139
Base Board Connector X1, X2 ........................................................139
Base Board Connector X3, X4 ........................................................139
Cable specification : U.FL/W.FL to RP-SMA FEMALE.................................... 140
Attributes............................................................................... 140
Dimensions ............................................................................. 140
Antenna specification: 802.11a/b/g antenna............................................ 141
Attributes............................................................................... 141
Dimensions ............................................................................. 141
Antenna Specification: 802.11b/g antenna .............................................. 142
Attributes............................................................................... 142
Dimensions ............................................................................. 142
Polar Plots ..................................................................................... 143
Safety statements ............................................................................ 144
........................................................................................... 144
FCC Part 15 Class B .......................................................................... 145
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www.digiembedded.com 11
About the Module
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CHAPTER 1
The network-enabled ConnectCore 9M 2443 core module family delivers leading
performance, low power operation, and rich peripheral interface support for a wide
variety of applications, including medical devices, transportation, security/access
control, networked displays, and more.
The modules utilize an innovative and power-efficient Samsung S3C2443 processor
with up to 533 MHz and a multilayered memory bus architecture that allows
simultaneous data transfer between processor, memory and peripherals. This
optimized design eliminates the traditional bus bandwith bottlenecks that are
common on other platforms. For example, updating graphical information through
the LCD controller and retrieving relevant data from memory at the same time can
now be realized without compromising overall performance and user experience.
Designed from the ground up with power budget conscious applications in mind, the
ConnectCore 9M 2443 module family is an ideal system platform for mobile and
battery-operated product designs with full off-the-shelf hard- and software support
for all power management modes. The modules also offer a wide variety of onboard peripherals such as network connectivity options, a TFT/CSTN LCD controller,
camera interface, audio codec interfaces, hi-speed USB device, full-speed USB host,
high-speed memory card support, external mass storage, and other interfaces.
Features and functionality
32-bit Samsung S3C2443 processor
ARM920T core at 400/533 MHz
16 KB of instruction/data cache
Up to 133 MHz memory bus speed
Up to 1 GB of NAND Flash
Up to 256 MB DDR SDRAM
www.digiembedded.com 12
Chapter 1
LCD controller (CSTN/TFT)
Up 1024x1024 pixels resolution
Up to 16 grey levels/4096 colors (STN)
Up to 24 bpp, two overlay windows (TFT)
Camera interface
ITU-R BT 601/656 8-bit mode support
4096x4096 pixels / 2048x2048 scaling
Mirror, 180° rotation, digital zoom in
RGB 16/24-bit, YCbCr 4:2:0/4:2:2 output
I2S and AC’97 audio codec controllers
USB support with integrated PHYs
USB 2.0 device, 1-port, high-/full-speed
USB 1.1 host, 2-port, low-/full-speed
Ethernet interface
– 10/100 Mbit Ethernet MAC and PHY
WLAN interface
– 802.11a/b/g WLAN interface with dual-diversity antenna setup
4-channel UART
Up to 921 kbps, IrDA 1.0 SIR mode
2-port SPI/Single-port HS-SPI
Master and slave mode
Up to 33 MHz
I2C-Bus Interface
1-ch Multi-Master IIC-Bus
Serial, 8-bit oriented and bi-directional data transfers up to 100 Kbit/s in
Standard mode or up to 400 Kbit/s in fast mode
13 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
SD/SDIO/MMC
1-/4-bit and block/stream, up to 25 MHzHigh-Speed (HS) MMC
SD HC 1.0, SD MC 2.1, SDIO 1.0, MMC 4.2
1-/4-/8-bit modes, up to 50 MHz
CE-ATA mode support
CF/ATA
Compact Flash 3.0 PC card mode
ATA/ ATAP I-6 mo de w it h PI O/ UDM A
10-bit ADC & Touch Screen Interface
10-channel multiplexed, 500k samples/s
Timer s /P W M
4-ch 16-bit timer/PWM, 1-ch 16-bit internal
8-/16-bit external memory bus interface
Power management modes
Normal, idle, stop, and sleep
Ext IRQ, RTC alarm, tick interrupt wake-up
GPIO options
Up to 15 external IRQs
Up to 134 GPIOs
Watchdog Timer (16-bit)
Real-time clock with calendar function
Two 120-pin board-to-board connectors
www.digiembedded.com 14
Chapter 1
JTAG signals available on module connectors
Standard module variants
The ConnectCore 9M 2443 module is currently available in the standard variants
below.
Speed Flash SDRAM Operating
temperature
533 MHz 128 MB 64 MB -40 to 85C CC-9M-NA37-Z1
533 MHz 64MB 32 MB -40 to 85C CC-9M-NA26-Z1
400 MHz 64 MB 32 MB -20 to 70C CC-9M-QA25-Z1
533 MHz 128 MB 64 MB -40 to 65C* CC-W9M-NA37-XE
533 MHz 64MB 32 MB -40 to 65C* CC-W9M-NA26-XE
400 MHz 64 MB 32 MB -20 to 65C* CC-W9M-QA25-XE
P/N
* See section "Thermal specifications" in this document for details.
Please visit the Digi website, www.digiembedded.com/support, or contact Digi for
additional population options.
15 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
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Block diagrams
CPU
www.digiembedded.com 16
Chapter 1
S3C2443
Et he rn et -I/ F,
PHY
120pi n
Co nn 1
2 b anks
DDR
SDRAM
NAND
Flash
Reset
Generator
Flash Control
Address Bus
COM 0/COM 1
JTAG
+3.3V
RSTOUT#
RSTIN#
120pin
Conn 2
PWRGOOD
GND
VRTC
LEDLNK
LEDH0
Configurati on
LCD/TFT-I/F
Bus Control
U SB host1/device0
USB De te ct/PWR En abl e
Clock
Serial
EEP ROM
Ext. IN T
AGND
AVCC
I2C
SPI
Timer Out
Address Bus
Data Bus
AC97/ I2S-I/F
SD-I/F
DMA
Analog In
Touch Sc reen
Timer In
PWR Enable Core
USB host0
US B PWR Enable
Buffer
CLKOUT
RTC
VLIO
VRTC
Core
Voltage
VLIO
Batte ry Fault
Camera-I/F
PLL
Volta ge
SDRAM l/F
Wireless
PR IM . Antenna
SEC . Antenna
LED
Module
17 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
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Detailed module description
Configuration The ConnectCore 9M 2443 Module supports 8 configuration pins:
4 pins provided for software configuration, which are routed to standard pin
locations on the development board (CONF[7:4]).
4 pins provided for hardware configuration, routed to the base board at
standard pin locations, including debug enable (DEBUG_EN#) and NAND flash
write protect (NAND_FWP#).
Power Supply The common power supply for the module is 3.3VDC. VLIO has to be connected to
3.3V on the base board.
The CPU specific core voltage of 1.2V@300MHz (1.3V@400MHz) and the voltage for
VDD alive will be generated on the module from the VLIO input, while the voltage for
memory power supply and I/OS is fed directly from the 3.3V.
The following requirements have to be met by the power supply:
Power Supply @400MHz @533MHz
Module Power Supply 3.3V 3.3V ±5% 3.3V ± 5%
Module Power Supply VLIO 3.3V ±5% 3.3V ±5%
Core Voltage 1.3V (1.25V - 1.35V) 1.375 (1.325V - 1.425V)
VDD alive 1.15V - 1.35V 1.15V - 1.2V
Voltage for internal RTC 3V (1.8V - 3.6V) 3V (1.8V - 3.6V)
Power Supply for ext. RTC
VRTC
Analog Voltage 3.3V (3V - 3.6V) 3.3V (3V - 3.6V)
VIN at common CPU pins -0.3V - 3.3V ± 0.3V -0.3V - 3.3V ± 0.3V
3V (e.g. Li-Battery) 3V (e.g. Li-Battery)
The voltage at pin RTCVDD has been connected to 3.3V, even though the RTC is not
used. If VDD_RTC is not used, it has to be high (VDD_RTC=3.3V).
The S3C2443 supports DVS (dynamic voltage scaling). This means that the core
voltage may be reduced to 1V in idle mode while clock frequency is also reduced.
VRTC is used to connect a battery on the base board for the external RTC on the
module. If the external RTC is not used, pin VRTC doesn't need to be connected. VRTC
is only used to power the external RTC on the module.
If a battery supplies the power for the module, the pin BATT_FLT# can be connected
to a comparator output on the base board. The comparator may supervise the battery
voltage on the base board. The CPU does not wake up at power-off mode in case of
www.digiembedded.com 18
Chapter 1
low battery state. If this feature is not used, the pin has to be left open, because a
10k pull up resistor is provided at the module.
Analog voltage AVCC and AGND, e.g. for a touch screen, are also provided on the
module system connector.
For the power control logic, the S3C2443 has various power management schemes
to keep optimal power consumption for a given task. These schemes are related to
PLL, clock control logics (ARMCLK, HCLK, and PCLK) and wakeup signals.
ARMCLK is used for ARM920T core.
HCLK is the reference clock for internal AHB bus and peripherals such as the
memory controller, the interrupt controller, LCD controller, the DMA, USB host
block, System Controller, Power down controller and etc.
PCLK is used for internal APB bus and peripherals such as WDT, IIS, I2C, PWM
timer, ADC, UART, GPIO, RTC and SPI etc.
The following figure shows the clock distribution:
Power
management
19 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
The power management block in the S3C2443 can activate four modes: NORMAL,
STOP, IDLE, and SLEEP. These are described below.
NORMAL mode In General Clock Gating mode, the On/Off clock gating of the individual clock
source of each IP block is performed by controlling each corresponding clock source
enable bit. The Clock Gating is applied instantly whenever the corresponding bit is
changed.
IDLE mode In IDLE mode, the clock to the CPU core is stopped. The IDLE mode is activated just
after the execution of the STORE instruction that enables the IDLE Mode bit. The
IDLE Mode bit should be cleared after wake-up from IDLE state.
STOP mode All clocks are stopped for minimum power consumption. Therefore, the PLL and
oscillator circuits are also stopped (oscillator circuit is controlled by PWRCFG
register). The STOP mode is activated after the execution of the STORE instruction
that enables the STOP mode bit. The STOP Mode bit should be cleared after wakeup from STOP state.
To exit from STOP mode, external interrupt, RTC alarm, RTC Tick, or BATT_FLT has
to be activated. During the wake-up sequence, the crystal oscillator and PLL may
begin to operate. The crystal oscillator settle-down time and the PLL lock-time is
required for a stable ARMCLK and automatically inserted by the hardware of
S3C2443X. During these lock and settle-down times, no clock is supplied to the
internal logic circuitry.
The following describes the sequence initiating STOP mode:
1 Set the STOP Mode bit (by the main CPU).
2 System controller requests bus controller to finish pending transaction.
3 Bus controller sends acknowledgement to system controller after bus
transactions are completed.
4 System controller requests memory controller to enter self-refresh mode,
preserving SDRAM contents.
5 System controller waits for self-refresh acknowledgement from memory
controller.
6 After receiving the self-refresh acknowledge, system controller disables system
clocks, and switches SYSCLK source to MPLL reference clock.
7 Disables PLLs and Crystal (XTI) oscillation. If OSC_EN_STOP bit in PWRCFG
register is 'high,' then system controller does not disable crystal oscillation.
Note: DRAM has to be in self-refresh mode during STOP and SLEEP mode to retain valid
memory data. LCD must be stopped before STOP and SLEEP mode, because DRAM can
not be accessed when it is in self-refresh mode.
SLEEP mode The block disconnects power to CPU, and the internal logic, with the exception of
the wake-up logic. Activating the SLEEP mode requires two independent power
sources. One of the two power sources supplies the power for the wake-up logic.
www.digiembedded.com 20
Chapter 1
The other power source supplies the CPU and internal logic, and should be
controlled for power on/off. In SLEEP mode, the second power supply source for the
CPU and internal logic will be turned off. The wake-up from SLEEP mode can be
issued by EINT[15:0].
In SLEEP mode, VDDi, VDDiarm, VDDMPLL and VDDEPLL will be turned off, and are
controlled by PWREN. If the PWREN signal is activated (H), VDDi and VDDiarm are
supplied by an external voltage regulator. If PWREN pin is inactive (L), VDDi and
VDDiarm are turned off.
In Power_OFF mode 1.2V have to be supplied to the VDD alive pin, and it is also
necessary to provide the I/O-voltages of 1.8V/3.3V. Therefore the LDO, which
supplies VDD alive will not be switched off.
The following describes the sequence of entering SLEEP mode:
1 One of the SLEEP Mode entering events is triggered by the system software or by
the hardware.
2 System controller requests bus controller to finish pending transaction.
3 Bus controller sends acknowledgement to system controller after bus
transactions are completed.
4 System controller requests memory controller to enter self-refresh mode,
preserving SDRAM contents.
5 System controller waits for self-refresh acknowledgement from memory
controller.
6 After receiving the self-refresh acknowledge, disables the XTAL and PLL
oscillation and also disables the external power source for the internal logic by
asserting the PWR_EN pin to low state. The PWR_EN pin is the regulator disable
control signal for the internal logic power source.
The SLEEP mode exit sequence is as follows.
1 System controller enables external power source by deasserting PWR_EN to high
state and initiates power settle down programmable through a register in the
PWRSETCNT field of RSTCON register.
2 System controller releases the System Reset (synchronously, relatively to the
system clock) after the power supply is stabilized.
Wake-up event When S3C2443X wakes up from the STOP Mode by an External Interrupt, an RTC
alarm interrupt and other interrupts, the PLL is turned on automatically. The initialstate of S3C2443X after wake-up from the SLEEP Mode is almost the same as the
Power-On-Reset state except for the contents of the external DRAM is preserved. In
contrast, S3C2443X automatically recovers the previous working state after wakeup from the STOP Mode. The following table shows the states of PLLs and internal
clocks after wake-ups from the power-saving modes.
21 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Mode before wake-up PLL on/off after wake-up SYSCLK after wake-up
Wake-up source
Wake-up source
Reset or restricted
wake-up events
and before the lock time
IDLE Unchanged PLL output PLL output
SYSCLK after the lock
time by internal logic
STOP PLL state ahead of entering STOP
mode (PLL ON or not)
SLEEP Off PLL reference clock PLL reference (input) clock
To enter sleep mode by BATT_FLT, BATF_CFG bits of PWRCFG register must be
PLL reference clock SYSCLK ahead of entering
STOP mode (PLL output or
not)
configured.
Do not exit from sleep mode when BATT_FLT is LOW; SLEEP_CFG bit of PWRCFG
register must be configured.
A Battery Fault Signal (BATT_FLT#) is provided at the CPU to recognize the battery
state of the battery at the base board, which powers the module. Therefore this pin
is routed to the system connector. At the base board a comparator has to supervise
the battery state and the output of the comparator delivers the BATT_FLT# signal.
The figure below shows the power management state diagram:
Reset There are 3 reset signals defined, which are routed to the system connector:
www.digiembedded.com 22
a reset input to the module (RSTIN#)
an output of the reset controller from the module (PWRGOOD)
a reset output from the CPU (RSTOUT#)
Chapter 1
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Memory
RSTIN# signal from the base board is connected to the reset generator device
on the module. At the base board there could be a reset switch connected to
the RSTIN# signal. A 10k pull up resistor is connected to the RSTIN# signal on
the module.
PWRGOOD must be held to low level at least 4 FCLKs to recognize the reset
signal.
The low active reset of the reset controller is connected to the system via a 470R
series resistor.
RSTOUT# can be used for external device reset control. RSTOUT# is a function of
Watchdog Reset and Software Reset (RSTOUT# = PWRGOOD & WDTRST# &
SW_RESET).
DDR SDRAM
memory
NAND Flash
memory
On the module there are two banks provided for DDR SDRAM memory. Both banks can
support a 16-bit mobile DDR memory chip. Bank 1 provides one part of a 16bit DDR
SDRAM in a FBGA60 package, with 1.8V power supply.
Total size of memory is possible from 16MB (only one bank) up to 256MB (128MB each
bank).
Both banks have to be populated with equal devices since they share all control
signals with the exception of their chip selects.These are defined in the bank control
registers BANKCFG and BANKCON1-3 and Refresh Control Register.
NAND Flash memory is provided, as a single Flash device. In order to support NAND
flash boot loader, the S3C2443 is equipped with an internal SRAM buffer called
Steppingstone. When booting, the first 4 KBytes of the NAND flash memory will be
loaded into Steppingstone and the boot code loaded into Steppingstone will be
executed.
Generally, the boot code will copy NAND flash content to DDR-SDRAM. Using hardware
ECC, the NAND flash data validity will be checked. Upon the completion of the copy,
the main program will be executed on the DDR-SDRAM.
Features:
NAND Flash memory I/F: Supports 512Bytes and 2KBytes Page.
Interface: 8-bit NAND flash memory interface bus.
Hardware ECC generation, detection and indication (Software correction).
23 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
SFR I/F: Supports Little Endian Mode, Byte/half word/word access to Data and
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ECC Data register, and Word access to other registers.
Steppingstone I/F: Supports Little/Big Endian, Byte/half word/word access.
The Steppingstone 4-KB internal SRAM buffer can be used for another purpose
after NAND flash booting.
The write protect pin of the Flash device is routed to the hardware configuration
pin of the system connector FWP#. The device can be write protected at the base
board by connecting this pin to GND. At the module, a pull-up resistor is equipped.
Configuration pins - CPU module
There are eight configuration pins provided on the system connector. Four of them
are provided as hardware configuration pins, and the other four can be used as
software configuration pins. A 10k pull up resistor is provided on each signal line of
the configuration pins.
The following pins on the connector are defined as hardware configuration pins:
Signal Description
DEBUGEN# Debug enable
FWP# Write protect of internal flash
CONF2 Hardware configuration 2 (not yet used)
CONF3 Hardware configuration 3 (not yet used)
The following port pins are defined as software configuration pins:
Signal Port Pin Description
CONF4 GPF2 Software configuration 0
CONF5 GPF3 Software configuration 1
CONF6 GPF4 Software configuration 2
CONF7 GPF5 Software configuration 3
The signal DEBUGEN# (CONF0) from the base board to the module is necessary to
allow switching a connection on and off between the system reset and the JTAG
reset.
Signal State Description
DEBUGEN# High Switch is on, TRST# and PWRGOOD are connecte d (defa ult)
DEBUGEN# Low Switch is off, TRST# and PWRGOOD are disconnected
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Chip selects
Chip select
memory map
At the module a pull up resistor is provided on the DEBUGEN# signal. Therefore only
a jumper to GND is necessary on the base board.
Name CPU Signal
name
Pin Address
Range
Size [Mb] Usage Comments
SCS0# SCS0# H15 0x3000_0000-
0x37FF_FFFF
SCS1# SCS1# D17 0x3800_0000-
0x3FFF_FFFF
RCS0# RCS0# A2 0x0000_0000-
0x03FF_FFFF
RCS1# RCS1# A1 0x0800_0000-
0x083F_FFFF
RCS2# RCS2# B3 0x1000_0000-
0x103F_FFFF
RCS3# RCS3# C1 0x1800_0000-
0x183F_FFFF
RCS4# RCS4# C4 0x2000_0000-
0x203F_FFFF
RCS5# RCS5# E4 0x2800_0000-
0x283F_FFFF
128 SDRAM bank 0 First bank on
module
128 SDRAM bank 1
64 not available
64 external, RCS1#
64 external, RCS2#
64 external, RCS3#
64 external, RCS4#
64 internal, RCS5# Used for Ethernet
Controller
25 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplexed GPIO pins
S3C2443X Port
Configuration
Port A Selectable Pin Functions On module,
GPA15 Output only nWE_CF - Output
GPA14 Output only RSMAVD - Output
GPA13 Output only RSMCLK - Output
GPA12 Output only nRCS5 - nRCS5
GPA11 Output only nOE_CF - Output
GPA10 RDATA_OEN RADDR25 - RADDR25
GPA9 Output only RADDR24 - RADDR24
GPA8 Output only RADDR23 - RADDR23
GPA7 Output only RADDR22 - RADDR22
GPA6 Output only RADDR21 - RADDR21
GPA5 Output only RADDR20 - RADDR20
GPA4 Output only RADDR19 - RADDR19
default used as
GPA3 Output only RADDR18 - RADDR18
GPA2 Output only RADDR17 - RADDR17
GPA1 Output only RADDR16 - RADDR16
GPA0 Output only RADDR0 - RADDR0
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Chapter 1
Port B Selectable Pin Functions On module,
default used as
GPB10 Input/Output nXDREQ0 XDREQ0 Input
GPB9 Input/Output nXDACK0 XDACK0 Input
GPB8 Input/Output nXDR EQ1 XDREQ1 Input
GPB7 Input/Output nXDACK1 XDACK1 Input
GPB6 Input/Output nXBREQ XBREQ Input
GPB5 Input/Output nXBACK XBACK Input
GPB4 Input/Output TCLK - Input
GPB3 Input/Output TOUT3 - not used, reserved
GPB2 Input/Output TOUT2 - Input
GPB1 Input/Output TOUT1 - Input
GPB0 Output only TOUT0 - Input
Port C Selectable Pin Functions On module,
default used as
GPC15 Input/Output VD7 - VD7
GPC14 Input/Output VD6 - VD6
GPC13 Input/Output VD5 - VD5
GPC12 Input/Output VD4 - VD4
GPC11 Input/Output VD3 - VD3
GPC10 Input/Output VD2 - VD2
GPC9 Input/Output VD1 - Input
GPC8 Input/Output VD0 - Input
GPC7 Input/Output LCD_VF[2] - LCD_VF[2]
GPC6 Input/Output LCD_VF[1] - LCD_VF[1]
GPC5 Input/Output LCD_VF[0] - LCD_VF[0]
GPC4 Input/Output VM - VM
GPC3 Input/Output VFRAME - VFRAME
GPC2 Input/Output VLINE - VLINE
GPC1 Input/Output VCLK - Output
GPC0 Input/Output LEND - Input
27 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Port D Selectable Pin Functions On module,
default used as
GPD15 Input/Output VD23 - VD23
GPD14 Input/Output VD22 - VD22
GPD13 Input/Output VD21 - VD21
GPD12 Input/Output VD20 - VD20
GPD11 Input/Output VD193 - VD193
GPD10 Input/Output VD18 - VD18
GDA9 Input/Output VD17 - Input
GPD8 I np ut/Outp ut VD16 - Input
GPD7 Input/Output VD15 - VD15
GPD6 Input/Output VD14 - VD14
GPD5 Input/Output VD13 - VD13
GPD4 Input/Output VD12 - VD12
GPD3 Input/Output VD11 - VD11
GPD2 Input/Output VD10 - VD10
GPD1 I np ut/Outp ut VD9 - Input
GPA0 I np ut/Outp ut VD8 - Input
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Port E Selectable Pin Functions On module,
default used as
GPE15 Input/Output IICSDA - IICSDA
GPE14 Input/Output IICSCL - IICSC L
GPE13 Input/Output SPICLK0 - SPICLK0
GPE12 Input/Output SPIMOSI0 - SPIMOSI0
GPE11 Input/Output SPIMISO0 - SPIMISO0
GPE10 Input/Output SD0_DAT3 - SD0_DAT3
GPE9 Input/Output SD0_DAT2 AC_nRESET SD0_DAT2
GPE8 Input/Output SD0_DAT1 AC_SYNC SD0_DAT1
GPE7 Input/Output SD0_DAT0 AC_SDO SD0_DAT0
GPE6 Input/Output SD0_CMD AC_SDI SD0_CMD
GPE5 Input/Output SD0_CLK AC_BIT_CLK SD0_CLK
GPE4 Input/Output I2SSDO AC_SDO Input
GPE3 Input/Output I2SSDI AC_SDI Input
GPE2 Input/Output CDCLK AC _BI T_CLK Input
GPE1 Input/Output I2SSCLK AC_SYNC Input
GPE0 Input/Output I2SLRCK AC_nRESET Input
Port F Selectable Pin Functions On module,
default used as
GPF7 Input/Output EINT7 - Input
GPF6 Input/Output EINT6 - Input
GPF5 Input/Output EINT5 - Input
GPA4 Input/Output EINT4 - Internal Input
GPF3 Input/Output EINT3 - Internal Input
GPF2 Input/Output EINT2 - Internal Input
GPF1 Input/Output EINT1 - Input
GPF0 Input/Output EINT0 - Input
Port G Selectable Pin Functions On module,
default used as
GPA15 Input/Output EINT23 CARD_PWREN Input
GPA14 Input/Output EINT22 RESET_CF Input
GPG13 Input/Output EINT21 nREG_CF Input
GPG12 Input/Output EINT20 nlNPACK Input
29 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Port G Selectable Pin Functions On module,
default used as
GPG11 Input/Output EINT19 nlREQ_CF Input
GPG10 Input/Output EINT18 - Input
GPG9 Input/Output EINT17 - Input
GPG8 Input/Output EINT16 - Input
GPG7 Input/Output EINT15 - Internal Input
GPG6 Input/Output EINT14 - Input
GPG5 Input/Output EINT13 - Input
GPG4 Input/Output EINT12 LCD_PWREN Internal Input
GPG3 Input/Output EINT11 - Input
GPG2 Input/Output EINT10 - Internal output
GPG1 Input/Output EINT9 - Internal Input
GPG0 Input/Output EINT8 - Input
Port H Selectable Pin Functions On module,
default used as
GPH14 Input/Output CLKOUT1 - CLKOUT1
GPH13 Input/Output CLKOUT0 - CLKOUT0
GPH12 Input/Output EXTUARTCLK - Internal Input
GPH11 Input/Output nRTS1 - nRTS1
GPH10 Input/Output nCTS1 - nCTS1
GPH9 Input/Output mRTS0 - mRTS0
GPH8 Input/Output nCTS0 - nCTS0
GPH7 Input/Output RXD3 nCTS2 RXD3
GPH6 Input/Output TXD2 nRTS2 TXD2
GPH5 Input/Output TXD2 - TXD2
GPH4 Input/Output RXD1 - RXD1
GPH3 Input/Output RXD1 - RXD1
GPH2 Input/Output TXD1 - TXD1
GPH1 Input/Output RXD0 - RXD0
GPH0 Input/Output TXD0 - TXD0
Port J Selectable Pin Functions On module,
default used as
GPJ15 Input/Output nSD1_WP - Input
GPJ14 Input/Output nSD1_CD - Input
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Port J Selectable Pin Functions On module,
default used as
GPJ13 Input/Output SD1_LED - Input
GPJ12 Input/Output CAMRESET - Input
GPJ11 Input/Output CAMCLKOUT - Input
GPJ10 Input/Output CAMHREF - Input
GPJ9 Input/Output CAMVSYNC - Input
GPJ8 Input/Output CAMPCLK - Input
GPJ7 Input/Output CAMDATA7 - Input
GPJ6 Input/Output CAMDATA6 - Input
GPJ5 Input/Output CAMDATA5 - Input
GPJ4 Input/Output CAMDATA4 - Input
GPJ3 Input/Output CAMDATA3 - Input
GPJ2 Input/Output CAMDATA2 - Input
GPJ1 Input/Output CAMDATA1 - Input
GPJ0 Input/Output CAMDATA0 - Input
Port L Selectable Pin Functions On module,
default used as
GPL14 Input/Output SS1 - Input
GPL13 Input/Output SS0 - Input
GPL12 Input/Output SPIMISO1 - Input
GPL11 Input/Output SPIMOSI1 - Input
GPL10 Input/Output SPICLK1 - Input
GPL9 Input/Output SD1_CLK - SD1_CLK
GPL8 Input/Output SD1_CMD - SD1_CMD
GPL7 Input/Output SD1_DAT7 - SD1_DAT7
GPL6 Input/Output SD1_DAT6 - SD1_DAT6
GPL5 Input/Output SD1_DAT5 - SD1_DAT5
GPL4 Input/Output SD1_DAT4 - SD1_DAT4
GPL3 Input/Output SD1_DAT3 - SD1_DAT3
GPL2 Input/Output SD1_DAT2 - SD1_DAT2
GPL1 Input/Output SD1_DAT1 - SD1_DAT1
GPL0 Input/Output SD1_DAT0 - SD1_DAT0
31 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
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Port M Selectable Pin Functions On module,
default used as
GPM1 Input FRnB - FRnB
GPM0 Input RSMBWAIT - Internal Input
Interfaces
RTC Instead of using the S3C2443-internal RTC, an external RTC (Dallas D1337) is
implemented on the module to optimize the power consumption characteristics in
sleep modes. Therefore the pin RTCVDD has to be connected to 3.3V and the pin
XTIrtc has also to be connected to 3.3V, while pin XTOrtc has to be left floating. An
external quartz is not necessary, if the internal RTC is not used.
The on-module RTC is connected to the I2C bus and powered by a 3V battery, which
has to be mounted on the base board. If no RTC is used, the pin VRTC at the system
connector can be left floating, because two Schottky diodes are used to power the
RTC either from 3.3V, or from the battery. The state of this battery will not be
supervised on the module.
The on-module RTC is a CMOS real time clock/calendar optimized for low power
consumption. An interrupt output is provided. All address and data are transferred
serially via a two-line bidirectional I2C-bus. Maximum bus speed is 400 kbit/s.
The low active interrupt output (CLK_INT#) of the RTC is connected to interrupt input
EINT7 of the CPU.
The I2C device address of the RTC is 0x68 (bits A7..A1), or 0xD0/0xD1 if expressed in
an 8-bit format, including the R/W bit at the end (bits A7..A1 + R/W bit).
UART interface The S3C2443 Universal Asynchronous Receiver and Transmitter (UART) provide four
independent asynchronous serial I/O (SIO) ports, each of which can operate in
Interrupt-based or DMA-based mode. In other words, the UART can generate an
interrupt or a DMA request to transfer data between CPU and the UART. The UART can
support bit rates up to 921.6K bps using system clock. Each UART channel contains
two 64-byte FIFOs for receiver and transmitter.
On the system connector, there are the signals for two UART interfaces provided.
Each interface consists of the data lines RXD/TXD and the handshake lines
RTS#/CTS#. The UARTs are part of the CPU. If the handshake lines of the third UART
interface (RTS2#/CTS2#) are not used, they could be used as data lines for a fourth
UART interface (TXD3/RXD3).
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The S3C2443 UART includes programmable baud rates, infrared (IR) transmit/receive,
one or two stop bit insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity
checking.
Each UART provides a baud-rate generator, transmitter, receiver and a control unit.
The baud-rate generator can be clocked by PCLK or EPLLCLK/n. UEXTCLK (external
input clock) is used on the module as GPIO. The transmitter and the receiver contain
64-byte FIFOs and data shifters. Data is written to FIFO and then copied to the
transmit shifter before being transmitted. The data is then shifted out by the
transmit data pin (TxDn). Meanwhile, received data is shifted from the receive data
pin (RxDn), and then copied to FIFO from the shifter.
The S3C2443 UART block supports also infra-red (IR) transmission and reception,
which can be selected by setting the Infra-red-mode bit in the UART line control
register (ULCONn).
There are four UART baud rate divisor registers including UBRDIV0, UBRDIV1, UBRDIV2
and UBRDIV3 in the UART block. The value stored in the baud rate divisor register
(UBRDIVn) and dividing slot register(UDIVSLOTn), are used to determine the serial
Tx/Rx clock rate (baud rate) as follows:
DIV_VAL = (SRCCLK / (baud rate x 16 ) ) -1
Where DIV_VAL should be from 1 to (216-1) and SRCCLK is either PCLK or divided EPLL
clock.
DIV_VAL can be programmed in the S3C2443 registers the following way:
DIV_VAL = UBRDIVn + (num of 1's in UDIVSLOTn)/16
33 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Where UBRDIVn is integer part of DIV_VAL - and UDIVSLOTn the floating point part of
DIV_VAL.
For example, if the baud rate is 115200 bps and SRCCLK is 66 MHz, UBRDIVn and
UDIVSLOTn are:
DIV_VAL = (66000000 / (115200 x 16)) -1
= 35.8 -1
= 34.8
* UBRDIVn = 34
(num of 1's in UDIVSLOTn)/16 = 0.8
(num of 1's in UDIVSLOTn) = 12.8=>13
The table below shows the recommended value table of UDIVSLOTn register.
Num of 1’s UDIVSLOTn Num of 1’s UDIVSLOTn
0 0x0000(0000_0000_0000_0000b) 8 0x5555(0101_0101_0101_0101b)
1 0x0080(0000_0000_0000_1000b) 9 0xD555(1101_0101_0101_0101b)
2 0x0808(0000_1000_0000_1000b) 10 0xD5D5(1101_0101_1101_0101b)
3 0x0888(0000_1000_1000_1000b) 11 0xDDD5(1101_1101_1101_0101b)
4 0x2222(0010_0010_0010_0010b) 12 0xDDDD(1101_1101_1101_1101b)
5 0x4924(0100_1001_0010_0100b) 13 0xDFDD(1101_1111_1101_1101b)
6 0x4A52(0100_1010_0101_0010b) 14 0xDFDF(1101_1111_1101_1111b)
7 0x54AA(0101_0100_1010_1010b) 15 0xFFDF(1111_1111_1100_1111b)
As a result, DIV_VAL = 34.8125 = 34+13x(1/16)
The baud rate is finally:
66000000/(34.8125+1)/16 = 115167.2 baud
SPI interface The S3C2443 provides two SPI-interfaces, each of which have two 8-bit shift registers
for transmission and receiving, respectively. During an SPI transfer, data is
simultaneously transmitted (shifted out serially) and received (shifted in serially).
Four I/O pin signals are associated with SPI transfers: SCK (SPICLK0,1), MISO
(SPIMISO0,1) data line, MOSI (SPIMOSI0,1) data line, and the active low /SS (nSS0,1)
pin.
Both 4-pin SPI interfaces are provided at the system connector (Clock, Chip-Select,
Data-In and Data-Out). SPI0 interface is located at the general pins of the system
connector, while SPI1 interface shares its pins with interrupt functions at the specific
pins of the system connector.
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Features:
SPI Protocol (ver. 2.11) compatible
8-bit Shift Register for transmit
8-bit Shift Register for receive
8-bit Prescaler logic
Polling, Interrupt, and DMA transfer mode
I2C interface The I2C signals clock and data are provided at the system connector.
USB interface The S3C2443 provides two USB ports. One port can only be used as host interface, the
other port can be configured either as host or device interface.
S3C2443 supports 2-port USB host interfaces as follows:
OHCI Rev 1.0 compatible
USB Rev1.1 compatible
Two down stream ports
Support for both LowSpeed and FullSpeed USB devices
The Samsung USB 2.0 Controller is designed to aid the rapid implementation of the
USB 2.0 peripheral device. The controller supports both High and Full speed mode.
Using the standard UTMI interface and AHB interface the USB 2.0 Controller can
support up to 9 Endpoints (including Endpoint0) with programmable Interrupt, Bulk
and Isochronous transfer mode.
Features:
Compliant to USB 2.0 specification
Supports FS/HS dual mode operation
EP 0 FIFO: 64 bytes
EP 1/2/3/4 FIFO: 512 bytes double buffering
EP 5/6/7/8 FIFO: 1024 bytes double buffering
Convenient Debugging
Support Interrupt, Bulk, Isochronous Transfer
One USB interface is provided at the general pins of the system connector, consisting
of the data lines USBP and USBN as well as the additional signal USB_DT/PW.
35 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Depending on the base board, the USB interface can be realized either as host1 or
device0, the signals have the following meaning:
Signal USB host1 USB device0
USBP Differential data+ DP1 Differential data + PDPO
USBN Differential data- DN1 Differential data- PDNO
USB_DT/PW USB Power Enable USB Detect
At the module specific pins of the system connector a second host interface (host0) is
provided with the differential data lines DP0 and DN0.
Ethernet interface The ConnectCore 9M 2443 module has a 10/100Mbit Ethernet controller with
integrated MAC and PHY on board.
Features:
Embedded 16Kbyte FIFO for packet buffers
Support burst-mode read for highest performance applications
Configurable Interrupt pin with programmable hold-off timer
Compatible with IEEE802.3, 802.3u standards
Integrate Fast Ethernet MAC/PHY transceiver in one chip
10Mbps and 100Mbps data rate
Full and half duplex operations
10/100Mbps Auto-negotiation operation
Twisted pair crossover detection and auto-correction (HP Auto-MDIX)
IEEE 802.3x flow control for full-duplex operation
Back-pressure flow control for half-duplex operation
Wake-on-LAN capabilities:
• Detection of a change in the network link state
• Receipt of a Magic Packet
LED pins for various network activity indications
The Ethernet controller is connected to CS5#. Its programmable polarity interrupt
output is connected to the interrupt input EINT9 of the CPU.
Global signals on the system connector only indicate the Link/Activity-LED is being
used.
On the base board a transformer with 1:1 turns ratio on TX and 1:1 on RX should be
used. For instance, PULSE H11022.
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WLAN interface In addition to the on-module wired Ethernet interface, the ConnectCore Wi-9M 2443
module also provides an integrated 802.11a/b/g WLAN interface. The WLAN interface
is based on the Digi WM500ABG baseband processor and specifically designed for
embedded products with long-term product availability requirements.
A/D converter and
touch screen
interface
The 10-bit /10-channels CMOS ADC (Analog to Digital Converter) converts the analog
input signal into 10-bit binary digital codes at a maximum conversion rate of 500KSPS
with 2.5MHz A/D converter clock. A/D converter operates with on-chip sample-andhold function and power down mode is supported.
The touch screen Interface can control/select pads (ConnectCore 9M 2443, XP, XM,
YP, YM) of the Touch Screen for X, Y position conversion. The touch Screen Interface
provides Touch Screen Pads control logic and ADC interface logic with interrupt
generation.
Features:
Resolution: 10-bit
Differential linearity error: 1.0 LSB
Integral linearity error: 2.0 LSB
Maximum conversion rate: 500 KSPS
Low power consumption
Power supply voltage: 3.3V
Analog input range: 0 ~ 3.3V
On-chip sample-and-hold function
Normal conversion mode
Separate X/Y position conversion mode
Auto (Sequential) X/Y position conversion mode
Waiting for interrupt mode
Touch screen
1. Normal conversion mode
interface modes
Single Conversion Mode is used for General Purpose ADC Conversion. This mode can
be activated by:
1 Set the ADCCON (ADC Control Register), and
2 Set the read and write to the ADCDAT0 (ADC Data Register 0).
2. Separate X/Y position conversion mode is activated as follows:
1 X-Position Mode writes X-Position Conversion Data to ADCDAT0, so Touch
Screen Interface generates the Interrupt source to Interrupt Controller.
2 Y-Position Mode writes Y-Position Conversion Data to ADCDAT1, so Touch
Screen Interface generates the Interrupt source to Interrupt Controller.
37 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
3. Auto (Sequential) X/Y Position Conversion Mode is activated as follows:
1 Touch Screen Controller sequentially converts the X-Position or Y-Position
that is touched.
2 After touch controller writes X-measurement data to ADCDAT0 and writes
Y-measurement data to ADCDAT1, the Touch Screen Interface generates
Interrupt source to Interrupt Controller in Auto Position Conversion Mode.
4. Waiting for Interrupt Mode is activated as follows:
1 The Touch Screen Controller generates an interrupt (INT_TC) signal when
the stylus is down. Waiting for Interrupt Mode setting value is
rADCTSC=0xd3; // XP_PU, XP_Dis, XM_Dis, YP_Dis, YM_En.
2 After the Touch Screen Controller generates interrupt signal (INT_TC), the
user must wait for the interrupt mode to be cleared (XY_PST sets to the No
operation Mode).
5. Standby Mode
Standby Mode is activated when ADCCON [2] is set to '1.'
In this mode, A/D conversion operation is halted and ADCDAT0, ADCDAT1 register
contains the previous converted data.
Reset controller On the module there is an Analog Devices ADM811SARTZ used. This device monitors
3.3V and has RSTIN# as debounced manual reset input and through a series resistor of
470R produces PWRGOOD as output. The voltage threshold is 2.93V. Reset output
length is typically 240ms.
JTAG The standard JTAG signals are provided at the system connector. A JTAG/Multi-ICE
connector has to be provided at the base board for debugging.
The signal DEBUGEN# (CONF0) from the base board to the module is necessary, to
be able to switch on and off a connection between the system reset and the JTAG
reset.
The pull-up resistors, belonging to the JTAG interface, are placed on the module.
Common features The LCD controller has a dedicated DMA that supports to fetch the image data from
video buffer located in system memory. Its features also include:
Dedicated interrupt functions (INT_FrSyn and INT_FiCnt)
The system memory is used as the display memory
Supports Multiple Virtual Display Screen (Supports Hardware
Horizontal/Vertical Scrolling)
Programmable timing control for different display panels
Supports little and big-endian byte ordering, as well as WinCE data formats
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Chapter 1
Wat chd og ti mer The S3C2443 watchdog timer is used to resume the controller operation whenever it
is disturbed by malfunctions such as noise and system errors. It can be used as a
normal 16-bit interval timer to request interrupt service. The watchdog timer
generates the reset signal for 128 PCLK cycles.
Features:
16-bit Watchdog Timer
Interrupt request or system reset at time-out
The prescaler value and the frequency division factor are specified in the watchdog
timer control (WTCON) register. Valid prescaler values range from 0 to 28-1. The
frequency division factor can be selected as 16, 32, 64, or 128.
Use the following equation to calculate the watchdog timer clock frequency and the
duration of each timer clock cycle:
t_watchdog = 1/( PCLK / (Prescaler value + 1) / Division_factor )
IIS-Bus interface IIS (Inter-IC Sound) interface transmits or receives sound data from or to external
stereo audio code cs. For transmit and receive data, two 32x16 FIFOs (First-In-FirstOut) data structures are included and DMA transfer mode for transmitting or
receiving samples can be supported. IIS-specific clock can be supplied from internal
system clock controller through IIS clock divider or direct clock source.
Features:
1-ch IIS-bus for audio interface with DMA-based operation
Serial, 8-/16-bit per channel data transfers
128 Bytes (64-Byte + 64-Byte) FIFO for Tx/Rx
Supports two IIS formats (MSB-justified or LSB-justified data format)
39 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
IIS block
diagram:
IIS-Bus format The IIS bus has four lines including serial data input I2SSDI, serial data output I2SSDO,
left/right channel select clock I2SLRCLK, and serial bit clock I2SBCLK; the device
generating I2SLRCLK and I2SBCLK is the master.
Serial data is transmitted in 2's complement with the MSB first with a fixed position,
whereas the position of the LSB depends on the word length. The transmitter sends
the MSB of the next word at one clock period after the I2SLRCLK is changed. Serial
data sent by the transmitter may be synchronized with either the trailing or the
leading edge of the clock signal. However, the serial data must be latched into the
receiver on the leading edge of the serial clock signal, and so there are some
restrictions when transmitting data that is synchronized with the leading edge.
The LR channel select line indicates the channel being transmitted. I2SLRCLK may be
changed either on a trailing or leading edge of the serial clock, but it does not need
to be symmetrical. In the slave, this signal is latched on the leading edge of the clock
signal. The I2SLRCLK line changes one clock period before the MSB is transmitted.
This allows the slave transmitter to derive synchronous timing of the serial data that
will be set up for transmission. Furthermore, it enables the receiver to store the
previous word and clear the input for the next word.
MSB (Left) Justified
MSB-Justified (Left-Justified) format is similar to IIS bus format, except that in MSBjustified format, the transmitter always sends the MSB of the next word at the same
time whenever the I2SLRCLK is changed.
LSB (Right) Justified
www.digiembedded.com 40
Chapter 1
LSB-Justified (Right-Justified) format is opposite to the MSB-justified format. In other
word, the transferring serial data is aligned with ending point of I2SLRCLK transition.
Camera interface The CAMIF (Camera Interface) within the S3C2443X consists of eight parts: pattern
mux, capturing unit, MSDMA (Memory Scaling DMA), preview scaler, codec scaler,
preview DMA, codec DMA, and SFR. The camera interface supports:
ITU R BT-601/656 YCbCr 8-bit standard and Memory
Maximum input size of 4096x4096 pixels (2048x2048 pixels for scaling)
Two scalers:
One is the preview scaler, which is dedicated to generating smaller size images for
previewing. The other one is the codec scaler, which is dedicated to generating codec
useful images like plane type YCbCr 4:2:0 or 4:2:2. Two master DMAs can do mirror
and rotate of the captured image for mobile environments. And test pattern
generation can be used to calibration of input sync signals as HREF, VSYNC. Also,
video sync signals and pixel clock polarity can be inverted in the camera interface
side with using register setting.
Features:
ITU-R BT 601/656 8-bit mode support
DZI (Digital Zoom In) capability
Programmable polarity of video sync signals
Max. 4096 x 4096 pixels input support (non-scaling)
Max. 2048 x 2048 pixels input support for codec scaling and 640 x 480 pixels
input support for preview scaling
Image mirror and rotation (X-axis mirror, Y-axis mirror and 180° rotation)
Preview DMA output image generation (RGB 16/24-bit format)
Codec DMA output image generation (RGB 16/24-bit format or YCbCr
4:2:0/4:2:2 format)
Capture frame control support in codec_path
Scan line offset support in codec_path (YCbCr)
YCbCr 4:2:2 codec image format interleave support
MSDMA supports memory data for preview path input
Image effect
CAMIF supports the following video standards:
ITU-R BT 601 YCbCr 8-bit mode
ITU-R BT 656 YCbCr 8-bit mode
41 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
The figure below provides an overview of the CAMIF interface signals.
All camera interface signals should have the same length.
Buffers should be Schmitt-triggered.
Below is the block diagram of the camera interface.
AC97 Controller The AC97 Controller Unit of the S3C2443 supports AC97 revision 2.0 features. AC97
Controller communicates with AC97 Codec using an audio controller link (AC-link).
Controller sends the stereo PCM data to Codec. The external digital-to-analog
converter (DAC) in the Codec then converts the audio sample to an analog audio
www.digiembedded.com 42
Chapter 1
waveform. Also, the Controller receives the stereo PCM data and the mono Mic data
from the Codec and then stores them in the memories. This chapter describes the
programming model for the AC97 Controller Unit. The information in this chapter
requires an understanding of the AC97 revision 2.0 specifications.
Note: The AC97 Controller and the IIS Controller must not be used at the same time.
Features:
Independent channels for stereo PCM In, stereo PCM Out, mono MIC In.
DMA-based operation and interrupt based operation.
All of the channels support only 16-bit samples.
Variable sampling rate AC97 Codec interface (48 KHz and below).
16-bit, 16 entry FIFOs per channel
Only Primary CODEC support
The following shows the functional block diagram of the S3C2443 AC97 Controller.
The AC97 signals form the AClink, which is a point-to-point synchronous serial
interconnect that supports full-duplex data transfers. All digital audio streams and
command/status information are communicated over the AC-link.
43 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
SD host interface The S3C2443 Secure Digital Interface (SDI) can interface for SD memory card, SDIO
device and Multi-Media Card (MMC).
Features:
SD Memory Card Spec. (ver. 1.0) / MMC Spec. (2.11) compatible
SDIO Card Spec (ver. 1.0) compatible
16 words (64 bytes) FIFO (depth 16) for data Tx/Rx
40-bit Command Register
136-bit Response Register
8-bit Prescaler logic (Freq. = System Clock / (P + 1))
Normal, and DMA Data Transfer Mode (byte, halfword, word transfer)
1bit / 4bit (wide bus) Mode & Block / Stream Mode Switch support
DMA burst4 access support (only word transfer)
The following shows the SD host block diagram:
PWM timer The S3C2443 has five 16-bit timers. Timer 0, 1, 2, and 3 have Pulse Width Modulation
(PWM) function. Timer 4 has an internal timer only with no output pins. The timer 0
has a dead-zone generator, which is used with a large current device. The timer 0 and
1 share an 8-bit prescaler, while the timer 2, 3 and 4 share other 8-bit prescaler. Each
timer has a clock divider, which generates 5 different divided signals (1/2, 1/4, 1/8,
1/16, and TCLK). Each timer block receives its own clock signals from the clock
divider, which receives the clock from the corresponding 8-bit prescaler. The 8-bit
prescaler is programmable and divides the PCLK according to the loading value,
which is stored in TCFG0 and TCFG1 registers.
The timer count buffer register (TCNTBn) has an initial value which is loaded into the
down-counter when the timer is enabled. The timer compare buffer register
www.digiembedded.com 44
Chapter 1
(TCMPBn) has an initial value which is loaded into the compare register to be
compared with the down-counter value. This double buffering feature of TCNTBn and
TCMPBn makes the timer generate a stable output when the frequency and duty ratio
are changed.
Each timer has its own 16-bit down counter, which is driven by the timer clock. When
the down counter reaches zero, the timer interrupt request is generated to inform
the CPU that the timer operation has been completed. When the timer counter
reaches zero, the value of corresponding TCNTBn is automatically loaded into the
down counter to continue the next operation. However, if the timer stops, for
example, by clearing the timer enable bit of TCONn during the timer running mode,
the value of TCNTBn will not be reloaded into the counter.
The value of TCMPBn is used for pulse width modulation (PWM). The timer control
logic changes the output level when the down-counter value matches the value of the
compare register in the timer control logic. Therefore, the compare register
determines the turn-on time (or turn-off time) of a PWM output.
Features:
Five 16-bit timers
Two 8-bit prescalers & Two 4-bit divider
Programmable duty control of output waveform (PWM)
Auto reload mode or one-shot pulse mode
Dead-zone generator
All of the Timer outputs are connected to the system connector.
Clock output At the global pins of the system connector there is a clock signal available
(BCLKOUT0), which is buffered by a clock buffer and can be chosen to be either MPLL
CLK, EPLL CLK, FCLK, HCLK, PCLK or DCLK. The source of this clock signal is the
CLKOUT0 port at the CPU, which can be programmed to different clocks, by the
CLKSEL0 register.
The following table shows the bits [6:4] of the CLKSEL0 register:
CLKSELO [6.4] 000 001 010 011 100 101 11x
CLKOUT0 MPLL CLK EPLL CLK FCLK HCLK PCLK DCLK0 Reserved
CF/ATA The single-slot CF controller consists of 2 parts - PC card controller & ATA controller.
They are multiplexing from or to PAD signals. Users can select either PC card or
True-IDE mode operation. Default mode is PC card mode. The CF controller has a
top level SFR with card power enable bit, output port enable bit & mode select
(True-IDE or PC card) bit.
45 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
PC card
controller
The PC card controller has 2 half-word (16 bit) write buffers & 4 half-word (16bits)
read buffers.
The PC card controller has 5 word-sized (32 bit) Special Function Registers.
Features:
3 timing configuration registers
Attribute memory
Common memory
I/O interface
1 status & control configuration register
1 interrupt source & mask register
Timing configuration register consists of 3 parts - Setup, Command & Hold
– IDLE, SETUP, COMMAND & HOLD
– Each part of register indicates the operation timing of each state
ATA controller Features:
Compatible with the ATA/ ATAP I-6 st and ar d
Thirty word-sized (32 bit) special function register
One FIFO that is 16 x 32 bit
Internal DMA controller (from ATA device to memory or from memory to ATA
device)
AHB master (DMA controller) supporting 8 burst & word size transfer
The control lines are available on X2.
High-speed MMC The HSMMC (High-speed MMC) / SD-MMC is a combo host for Secure Digital card and
MultiMedia Card. This host is compatible with SD Association's (SDA) Host Standard
Specification.
Interface a system with SD card and MMC card. The performance of this host is very
powerful, supporting 52 MHz clock rate and 8-bit access simultaneously.
Features:
SD Standard Host Spec (ver 1.0) compatible
SD Memory Card Spec (ver 2.1) / MMC Memory card Spec(4.2) compatible
SDIO Card Spec (ver 1.0) compatible
512 bytes FIFO for data Tx/Rx
48-bit Command Register
136-bit Response Register
www.digiembedded.com 46
Chapter 1
CPU Interface and DMA data transfer mode
1-bit / 4-bit / 8-bit mode switch support
Auto CMD12 support
Suspend / Resume support
Read Wait operation support
Card Interrupt support
CE-ATA mode support
The control lines are available on X2.
High speed SPI The High Speed Serial Peripheral Interface (HS_SPI) can interface the serial data
transfer. HS_SPI has two 8-bit shift registers for transmission and receiving,
respectively. During an SPI transfer, data is simultaneously transmitted (shifted out
serially) and received (shifted in serially). HS_SPI supports the protocols for National
Semiconductor Microwire and Motorola Serial Peripheral Interface.
External
address/data bus
Features:
Full duplex support
8-bit shift register for TX/RX
8-bit prescale logic
3 clock sources
8-bit/32-bit bus interface
Motorola SPI protocol and National Semiconductor Microwire compliant
Two independent transmit and receive FIFOs (16 samples deep/32-bits wide)
Master-mode and slave-mode
Receive-without-transmit operation
The external address/data bus supports:
64MB address space per external chip select
Programmable 8/16-bit data bus width
Four external chip selects
Complete programmable access cycles for all memory banks
External wait signals to expand the bus cycle
WLAN connectors In addition to the wired Ethernet interface, the ConnectCore Wi-9M 2443 module
also offers an integrated dual-diversity 802.11a/b/g interface with data rates up to
54 Mbps. Two U.FL antenna connectors are provided on the module. For the Connect
Core Wi-9M 2443, attach the antennas with the U.FL-RP-SMA FEMALE Cable to the
47 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
primary connector [X5] and the secondary connector [X4] on the module. You must
use only this cable and antennas to carry on the module.
Note
When disconnecting U.FL connectors, the use of U.FL plug extraction tool
(Hirose P/N U.FL-LP-N-2 or U.FL-LP(V)-N-2) is strongly recommended to
avoid damage to the U.FL connectors on the ConnectCore Wi-9M 2443
module.
To mate U.FL connectors, the mating axes of both connectors must be aligned. The
"click" will confirm fully mated connection. Do not attempt insertion at an extreme
angle.
www.digiembedded.com 48
Chapter 1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LCD controller display features
The LCD controller of the S3C2443 consists of the logic for transferring LCD image
data from a video buffer located in system memory to an external LCD driver. The
LCD controller supports monochrome, 2-bit per pixel (4-level gray scale) or 4-bit per
pixel (16-level gray scale) mode on a monochrome LCD, using a time-based dithering
algorithm and Frame Rate Control (FRC) method and it can be interfaced with a color
LCD panel at 8-bit per pixel (256-level color) and 12-bit per pixel (4096-level color)
for interfacing with STN LCD.
It can support 1-bit per pixel, 2-bit per pixel, 4-bit per pixel, and 8-bit per pixel for
interfacing with the palletized TFT color LCD panel, and 16-bit per pixel and 24-bit
per pixel for non-palletized true-color display. The LCD controller can be
programmed to support different requirements on the screen related to the number
of horizontal and vertical pixels, data line width for the data interface, interface
timing, and refresh rate.
STN LCD
displays
TFT LCD
displays
4-bit dual scan, 4-bit single scan, and 8-bit single scan display type
Monochrome, 4 gray levels, and 16 gray levels
256 colors and 4096 colors for color STN LCD panel
Multiple screen size:
– Typical actual screen size: 640 x 480, 320 x 240, 160 x 160, and others
– Maximum virtual screen size is 4Mbytes
– Maximum virtual screen size in 256 color mode: 4096 x 1024, 2048 x 2048,
1024 x 4096, and others
1, 2, 4 or 8-bpp (bit per pixel) palletized color displays
16, 24-bpp non-palletized true-color displays
Maximum 16M color TFT at 24bit per pixel mode
Multiple screen size:
– Typical actual screen size: 640 x 480, 320 x 240, 160 x 160, and others
– Maximum virtual screen size: 4Mbytes
– Maximum virtual screen size in 64K color mode: 2048 x 1024, and others
2 overlay windows for TFT
Common features The LCD controller has a dedicated DMA that supports fetching image data from
49 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
a video buffer located in system memory.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Its features include:
Dedicated interrupt functions (INT_FrSyn and INT_FiCnt)
System memory used as display memory
Multiple Virtual Display Screen (supports hardware horizontal/vertical
Programmable timing control for different display panels
Little and big-endian byte ordering, as well as Windows Embedded CE data
Module pinout
scrolling)
formats
System connector
I = Input
X1
O = Output
AI = Analog Input
P = Power
Pin Signal Type Signal name Description
X1-1 GND P GND
X1-2 RSTIN# I RSTIN# Input of a ADM811SARTZ supervisor which
produces PWRGOOD. 10k pull up on module
X1-3 PWRGOOD O PWRGOOD Output of a ADM811SARTZ supervisor. 470R
series resistor on module
X1-4 RSTOUT O RSTOUT# Softw + WDT + RSTIN#
X1-5 TCK I TCK JTAG
X1-6 TMS I TMS JTAG Mode Select
X1-7 TDI I TDI JTAG Data I n
X1-8 TDO O TDO JTAG Data Out
X1-12 Conf2 I VD0
GPC8
X1-13 Conf3 I VD1
GPC9
X1-14 Conf4 I VD8
GPD0
www.digiembedded.com 50
VD0 can be used for LCD or 24 bit TFT.
On JSCC9M2443 a DIP switch is connected
VD1 can be used for LCD or 24 bit TFT.
On JSCC9M2443 a DIP switch is connected
VD8 can be used for LCD or 24 bit TFT.
On JSCC9M2443 a DIP switch is connected
Chapter 1
Pin Signal Type Signal name Description
X1-15 Conf5 I VD9
GPD1
X1-16 Conf6 I VD16
GPD8
X1-17 Conf7 I VD17
GPD9
X1-18 TxDA O TXD0
GPH0
X1-19 RxDA I RXD0
GPH1
X1-20 RTSA# O RTS0#
GPH9
X1-21 CTSA# I CTS0#
GPH8
X1-22 I CAMPCLK
GPJ8
X1-23 I CAMHREF
GPJ10
X1-24 TxDB O TXD2
GPH4
VD9 can be used for LCD or 24 bit TFT.
On JSCC9M2443 a DIP switch is connected
VD16 can be used for LCD or 24 bit TFT.
On JSCC9M2443 a DIP switch is connected
VD17 can be used for LCD or 24 bit TFT.
On JSCC9M2443 a DIP switch is connected
Serial PORT A Transmit Data
Serial PORT A Receive Data
Serial PORT A Request to send
Serial PORT A Clear to Send
Pixel clock driven by the camera pr oc ess or
Horizontal sync driven by the camera processor
Serial PORT C Transmit Data
X1-25 RxDB I RXD2
GPH5
X1-26 RTSB# O TXD3
GPH6
RTS2#
X1-27 CTSB# I TXD3
GPH7
CTS2#
X1-28 CAMVSYNC I CAMVSYNC
GPJ9
X1-29 CAMDATA0 I CAMDATA0
GPJ0
X1-30 CAMDATA1 I CAMDATA1
GPJ1
X1-31 CAMDATA2 I CAMDATA2
GPJ2
X1-32 CAMDATA3 I CAMDATA3
GPJ3
Serial PORT C Receive Data
Handshake PORT C or PORT D Transmit Data
Handshake PORT C or PORT D Receive Data
Frame sync driven by camera processor
Pixel data driven by the camera processor
Pixel data driven by the camera processor
Pixel data driven by the camera processor
Pixel data driven by the camera processor
51 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Pin Signal Type Signal name Description
X1-33 CAMDATA4 I CAMDATA4
GPJ4
X1-34 CAMDATA5 I CAMDATA5
GPJ5
X1-35 CAMDATA6 I CAMDATA6
GPJ6
X1-36 CAMDATA7 I CAMDATA7
GPJ7
X1-37 USB_PWREN# O RSMVAD
GPA14
X1-38 EINT5
VBUSDET
I EINT5
GPF5
X1-39 P GND
X1-40 VD2 I/O VD2
GPC10
X1-41 VD3 I/O VD3
GPC11
X1-42 VD4 I/O VD4
GPC12
Pixel data driven by the camera processor
Pixel data driven by the camera processor
Pixel data driven by the camera processor
Pixel data driven by the camera processor
General purpose output
General purpose input/output
LCD/TFT Interface
LCD/TFT Interface
LCD/TFT Interface
X1-43 VD5 I/O VD5
GPC13
X1-44 VD6 I/O VD6
GPC14
X1-45 VD6
GPC14
I/O VD7
GPC15
X1-46 EINT18\CF_CD# I/O EINT18
GPG10
X1-47 EINT11 I/O EINT11
GPG3
X1-48 VD10 I/O VD10
GPD2
X1-49 VD11 I/O VD11
GPD3
X1-50 VD12 I/O VD12
GPD4
X1-51 VD13 I/O VD13
GPD5
X1-52 VD14 I/O VD14
GPD6
LCD/TFT Interface
LCD/TFT Interface
LCD/TFT Interface
LCD/TFT Interface
General purpose input / output
LCD/TFT Interface
LCD/TFT Interface
LCD/TFT Interface
LCD/TFT Interface
LCD/TFT Interface
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Chapter 1
Pin Signal Type Signal name Description
X1-53 VD15 I/O VD15
GPD7
X1-54 EINT14 I/O EINT14
GPG6
X1-55 TCLK0 I/O TCLK0
GPB4
X1-56 VD18 I/O VD18
GPD10
X1-57 VD19 I/O VD19
GPD11
X1-58 VD20 I/O VD20
GPD12
X1-59 VD21 I/O VD21
GPD13
X1-60 VD22 I/O VD22
GPD14
X1-61 VD23 I/O VD23
GPD15
X1-62 LCD_PWREN I/O EINT12
GPG4
LCD_PWREN
LCD/TFT Interface
General purpose input / output
General purpose input / output
LCD/TFT Interface
LCD/TFT Interface
LCD/TFT Interface
LCD/TFT Interface
LCD/TFT Interface
LCD/TFT Interface
LCD/TFT Interface
X1-63 VM I/O VM
GPC4
X1-64 VFRAME I/O VFRAME
GPC3
X1-65 VLINE I/O VLINE
GPC2
X1-66 VCLK I/O VCLK
GPC1
X1-67 LEND I/O LEND
GPC0
X1-68 LCD_LPCOE I/O LCDVF0
GPC5
X1-69 LCD_LPCREV I/O LCDVF1
GPC6
X1-70 LCD_LPCREVB I/O LCDVF2
GPC7
X1-71 TOUT0 I/O TOUT0
GPB0
LCD/TFT Interface
LCD/TFT Interface
LCD/TFT Interface
LCD/TFT Interface
LCD/TFT Interface
LCD/TFT Interface
LCD/TFT Interface
LCD/TFT Interface
Timer out
53 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Pin Signal Type Signal name Description
X1-72 TOUT1 I/O TOUT1
Timer out
GPB1
X1-73 NC I/O WLAN_DISABLE# Not connected; reserved for CCW9M
X1-74 NC I/O WLAN_LED# Not connected; reserved for CCW9M
X1-75 SDCLK I/O SD0_CLK
SD-interface
GPE5
AC_BIT_CLK
X1-76 SDCMD I/O SD0_CMD
SD-interface
GPE6
AC_SDI
X1-77 SDDATA0 I/O SD0_DAT[0]
SD-interface
GPE7
AC_SDO
X1-78 SDDATA1 I/O SD0_DAT[1]
SD-interface
GPE8
AC_SYNC
X1-79 GND P GND
X1-80 SDDATA2 I/O SD0_DAT[2]
SD-interface
GPE9
AC_RESET
X1-81 SDDATA3 I/O SD0_DAT[3]
GPE10
X1-82 EINT0 I/O EINT0
GPF0
X1-84 TOUT2 I/O TOUT2
GPB2
X1-85 SS1# I/O SS1
GPL14
X1-86 SPIMISO1 I/O SPIMISO1
GPL12
X1-87 SPIMOSI1 I/O SPIMOSI1
GPL11
X1-88 SPICLK1 I/O SPICLK1
GPL10
X1-89 EINT17 I/O EINT17
GPG9
X1-90 EINT1\SD_CD# I/O EINT1
GPF1
SD-interface
External interrupts
Timer out
SPI1 Interface
SPI1 Interface
SPI1 Interface
SPI1 Interface
General purpose input / output
General purpose input / output
www.digiembedded.com 54
Chapter 1
Pin Signal Type Signal name Description
X1-92 ROE# I/O ROE# Ext. bus control
X1-93 RWE# I/O RWE# Ext. bus control
X1-94 WAIT# I/O WAIT# Ext. bus control
X1-95 RCS1# I/O RCS1# Chip selects
X1-96 RCS2# I/O RCS2# Chip selects
X1-97 RCS3# I/O RCS3# Chip selects
X1-98 RCS4# I/O RCS4# Chip selects
X1-99 PWREN O PWREN 1.8V core power on-off control
X1-100 BATT_FLT# I BATT_FLT# Battery fault
X1-101 CAMCLKOUT O CAMCLKOUT
GPJ11
X1-102 CAMRESET O CAMRESET
GPJ12
X1-103 RBE0# O RBE0# Upper byte / lower byte enable
X1-104 RBE1# O RBE1# Upper byte / lower byte enable
X1-107 SS0# O SS0
GPL13
X1-108 SPIMISO0 I SPIMISO0
GPE1
X1-109 SPIMOSI0 O SPIMOSI0
GPE12
X1-110 SPICLK0 O SPICLK0
GPE13
X1-111 I2CSCL O I2CSCL I2C clock
X1-112 I2CSDA I/O I2CSDA I2C data
X1-113 EINT8
USB_DT/PW
I/O EINT8
GPG0
Master clock to the camera processo r
Software reset or power down to the camera
processor
SPI0 chip select
SPI_Master IN
SPI_Master OUT
SPI0 clock
Not used
X1-114 USBP I/O USBP USB data host1, device
X1-115 USBN I/O USBN USB data host1, device
X1-116 VRTC P VRTC Power for RTC
X1-117 GND P GND
X1-118 +3.3V P +3.3V +3.3V for peripherals
X1-119 VLIO P VLIO Power from Li-Ion battery for core
55 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Pin Signal Type Signal name Description
X1-120 +3.3V P +3.3V +3.3V for peripherals
System connector
X2
Pin Signal Type Signal name Description
X2-1 USBP0 I/O USBP0 USB data host0
X2-2 GND P GND
X2-3 USBN0 I/O USBN0 USB data host 0
X2-4 RADDR0 O RADDR0
GPA0
X2-5 RADDR1 O RADDR1 Address line
X2-6 RADDR2 O RADDR2 Address line
X2-7 RADDR3 O RADDR3 Address line
X2-8 RADDR4 O RADDR4 Address line
X2-9 RADDR5 O RADDR5 Address line
X2-10 RADDR6 O RADDR6 Address line
X2-11 RADDR7 O RADDR7 Address line
X2-12 RADDR8 O RADDR8 Address line
X2-13 RADDR9 O RADDR9 Address line
X2-14 RADDR10 O RADDR10 Address line
X2-15 RADDR11 O RADDR11 Address line
X2-16 RADDR12 O RADDR12 Address line
X2-17 RADDR13 O RADDR13 Address line
X2-18 RADDR14 O RADDR14 Address line
X2-19 RADDR15 O RADDR15 Address line
X2-20 RADDR16 O RADDR16
GPA1
X2-21 RADDR17 O RADDR17
GPA2
X2-22 RADDR18 O RADDR18
GPA3
X2-23 RADDR19 O RADDR19
GPA4
Address line
Address line
Address line
Address line
X2-24 RADDR20 O RADDR20
www.digiembedded.com 56
Address line
GPA5
Chapter 1
Pin Signal Type Signal name Description
X2-25 RADDR21 O RADDR21
GPA6
X2-26 RADDR22 O RADDR22
GPA7
X2-27 RADDR23 O RADDR23
GPA8
X2-28 RADDR24 O RADDR24
GPA9
X2-29 RADDR25 O RADDR25
RDATA_OEN
X2-30 NC - (A26) Pull down on module
X2-31 RxD1 I RXD1
GPH3
X2-32 TxD1 O TXD1
GPH2
X2-33 CTS1# I CTS1#
GPH10
X2-34 RTS1# O RTS1#
GPH11
Address line
Address line
Address line
Address line
Address line
Serial PORT B
Serial PORT B
Serial PORT B
Serial PORT B
X2-35 reserved
X2-36 XDREQ0# I/O XDREQ0#
GPB10
X2-37 XDREQ1# I/O XDREQ1#
GPB8
X2-38 XDACK0# I/O XDACK0#
GPB9
X2-39 XDACK1# I/O XDACK1#
GPB7
X2-40 GND P GND
X2-41 AIN4 AI AIN4 A/D converter
X2-42 AIN5 AI AIN5 A/D converter
X2-43 AIN0 AI AIN0 A/D converter
X2-44 AIN1 AI AIN1 A/D converter
X2-45 AIN2 AI AIN2 A/D converter
X2-46 AIN3 AI AIN3 A/D converter
X2-47 AIN6/YM AI AIN6/YM A/D converter or touch interface
DMA
DMA
DMA
DMA
X2-48 AIN7/YP AI AIN7/YP A/D converter or touch interface
57 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Pin Signal Type Signal name Description
X2-49 AIN8/XM AI AIN8/XM A/D converter or touch interface
X2-50 AIN9/XP AI AIN9/XP A/D converter or touch interface
X2-51 AVCC P AVCC Analog VCC
X2-52 AGND P AGND Analog GND
X2-53 NC Reserved for CCW9M CPLD_TDI
X2-54 NC Reserved for CCW9M CPLD_TCK
X2-55 NC Reserved for CCW9M CPLD_TMS
X2-56 NC Reserved for CCW9M CPLD_TDO
X2-57 XBREQ# I/O XBREQ#
Ext. bus control
BPG6
X2-58 XBACK# I/O XBACK#
Ext. bus control
GPB5
X2-59 EINT16
USBH0PEN
IEINT16
GPG8
USB0 host power fault if low
X2-60 PME O PME Ethernet controller power management event
X2-61 I2SSDO I/O I2SSDO
Audio interface
GPE4
AC_SDO0
X2-62 I2SSDI I/O I2SSDI
Audio interface
GPE3
AC_SDI0
X2-63 I2SSCDCLK I/O I2SCDCLK
Audio interface
GPE2
AC_BIT_CLK0
X2-64 I2SSCLK I/O I2SSCLK
Audio interface
GPE1
AC_SYNC
X2-65 I2SLRCK I/O I2SLRCK
Audio interface
GPE0
AC_nRESET
X2-66 TPIN I TPIN Ethernet 0 input
X2-67 LEDLNK O LEDLNK Ethernet 0 link/activity LED
X2-68 TPIP I TPIP Ethernet 0 input +
X2-69 LEDSPD O LEDSPD Ethernet 0 speed LED
X2-70 TPON O TPON Ethernet 0 output
X2-71 ETHGPIO2
O ETHGPIO2/LED3# Ethernet 0 full duple x LED
LED3#
www.digiembedded.com 58
Chapter 1
Pin Signal Type Signal name Description
X2-72 TPOP O TPOP Ethernet 0 output +
X2-73 OE_CF# O OE_CF#
GPA11
X2-74 WE_CF# O WE_CF#
GPA15
X2-75 IREQ_CF# I IREQ_CF#
EINT19
GPG11
X2-76 INPACK_CF# I INPACK_CF#
EINT20
GPG12
X2-77 REG_CF# O REG_CF#
EINT21
GPG13
X2-78 RESET_CF O RESET_CF
EINT22
GPG14
X2-79 PWEN_CF O PWEN_CF
EINT23
GPG15
X2-80 GND P GND
Compact Flash interface
Compact Flash interface
Compact Flash interface
Compact Flash interface
Compact Flash interface
Compact Flash interface
Compact Flash interface
X2-81 RDATA0 I/O RDATA0 Data Bus
X2-82 RDATA1 I/O RDATA1 Data Bus
X2-83 RDATA2 I/O RDATA2 Data Bus
X2-84 RDATA3 I/O RDATA3 Data Bus
X2-85 RDATA4 I/O RDATA4 Data Bus
X2-86 RDATA5 I/O RDATA5 Data Bus
X2-87 RDATA6 I/O RDATA6 Data Bus
X2-88 RDATA7 I/O RDATA7 Data Bus
X2-89 RDATA8 I/O RDATA8 Data Bus
X2-90 RDATA9 I/O RDATA9 Data Bus
X2-91 RDATA10 I/O RDATA10 Data Bus
X2-92 RDATA11 I/O RDATA11 Data Bus
X2-93 RDATA12 I/O RDATA12 Data Bus
X2-94 RDATA13 I/O RDATA13 Data Bus
X2-95 RDATA14 I/O RDATA14 Data Bus
59 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Pin Signal Type Signal name Description
X2-96 RDATA15 I/O RDATA15 Data Bus
X2-97 SD1_DAT0 I/O SD1_DAT0
GPL0
X2-98 SD1_DAT1 I/O SD1_DAT1
GPL1
X2-99 SD1_DAT2 I/O SD1_DAT2
GPL2
X2-100 SD1_DAT3 I/O SD1_DAT3
GPL3
X2-101 SD1_DAT4 I/O SD1_DAT4
GPL4
X2-102 SD1_DAT5 I/O SD1_DAT5
GPL5
X2-103 SD1_DAT6 I/O SD1_DAT6
GPL6
X2-104 SD1_DAT7 I/O SD1_DAT7
GPL7
X2-105 SD1_CMD I/O SD1_CMD
GPL8
X2-106 SD1_CLK I/O SD1_CLK
GPL9
SD card interface 1
SD card interface 1
SD card interface 1
SD card interface 1
SD card interface 1
SD card interface 1
SD card interface 1
SD card interface 1
SD card interface 1
SD card interface 1
X2-107 SD1_WP# I/O SD1_nWP
SD card interface 1
GPJ15
X2-108 SD1_CD# I/O SD1_nCD
SD card interface 1
GPJ14
X2-109 SD1_LED# I/O SD1_LED
SD card interface 1
GPJ13
X2-110 EINT6 I/O EINT6
General purpose input / output
GPF6
X2-111 EINT13 I/O EINT13
General purpose input / output
GPG5
X2-116 CLKOUT1 I/O CLKOUT1
Timer output
GPH14
X2-119 CLKOUT O BCLKOUT0 Buffered clockout0
X2-120 GND P GND
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Chapter 1
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Configuration pins - CPU
The following configuration pins are hardwired on the module: Default module CPU
configuration.
MCONF0
(GPF3)
SDRAM-Type 16 MB00xxx
32 MB01xxx
64 MB10xxx
128 MB11xxx
SDRAM-CL 2 xx00x
3 xx01x
4 xx10x
5 xx11x
CPU 400 MHzxxxx0
533 MHzxxxx1
MCONF1
(GPF4)
MCONF2
(GPM0)
MCONF3
(GPF2)
MCONF4
(GPH12)
x = don't care
OM0 is fixed to GND for setting XTAL.
OM4 is fixed to GND for setting NAND.
OM1-3 are depending of the FLASH type.
No pins are available on the module connectors.
61 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
About the Development Board
CHAPTER 2
The ConnectCore 9M 2443 Development Board supports the ConnectCore 9M 2443
and ConnectCore Wi-9M 2443 module. This chapter describes the different
components of the development board, which provides the following main features:
. . . . .
What’s on the
development
board?
RJ-45 Ethernet Connector
Connectors for Digi 802.3af PoE application board (sold separately)
1 x UART RS232 with status LEDs and SUB-D 9-pin connector
1 x UART MEI (RS232/RS4xx) with status LEDs and SUB-D 9-pin connectors
2 x UART with TTL levels
USB Host Connector
USB Device Connector
SPI, I2C headers
LCD Application Connector with Touch Screen Interface
VGA interface
2 x User LEDs (green)
2 x User Keys
1 x Debug LED
Screw-flange connector for GPIO
Peripheral application header 0
– Including access to 16-bit data /10-bit address bus signals
Connectors with 1:1 copies of module pins
Eight-position configuration DIP switch
Flexible 9-30VDC power supply
Test points and current measurement options (+3.3V & 5V)
3V coin cell battery
JTAG connector
www.ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference.com 62
Chapter 2
The development
board
63 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
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User interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The ConnectCore 9M 2443 development board implements two user buttons and two
user LEDs in addition to those provided on the module. The user LEDs on the
development board can be enabled or disabled by correctly setting jumper J5 and
J6. The table below shows which S3C22443 GPIO is available for implementing the
user interface.
Signal name GPIO used Comments
USER_BUTTON1 GPF0 100 Ohm serial resistors should be used to
USER_LED1# GPL11 Jumper JP5 as to be set.
USER_BUTTON2 GPF1 100 Ohm serial resistors are used to avoid
USER_LED2# GPL10 Jumper JP6 as to be set.
Both push-buttons can also be used for wake-up functions.
. . . . .
avoid conflicts with the CPU functions when
the buttons are pushed.
conflicts with the CPU functions when the
buttons are pushed.
Power
management
User buttons can also be used as a wake-up event for power management modes.
The user LEDs on the development board can be enabled or disabled by correctly
setting J5/J6.
General information
The integrated on-chip functions of the module are outlined below.
Signal name GPIO used
USER_LED_1 GPL11
USER_LED_2 GPL10
Power supply
ConnectCore 9M 2443 Development Board is powered by either the main 9-
30VDC power supply or by the PoE (IEEE 802.3af) module near to the Ethernet
connector.
Both power supply sources can be switched off through one power switch.
From the varying input voltage (9-30VDC), a stable base power supply is
created on the ConnectCore 9M 2443 development board. The 3.3VDC power
supply is provided to the module, where other power supplies can be
generated.
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Chapter 2
3.3VDC power
controller - VLIO
Power LEDs
Coin cell for RTC
Current
measuring option
The ConnectCore 9M 2443 module supports another external power source:
VLIO. This power source normally comes from a battery and is used in Mobile
application for generating the S3C2443 core voltage. On the ConnectCore 9M
2443 development board, VLIO is selectable by jumper setting onboard
+3.3VDC, or external VLIO.
Two power LEDs are available on the development board, and indicate:
– presence of 9-30VDC power supply,
– presence of +5V, or
– presence of 3.3VDC power supply.
All power LEDs are red.
A 3.0V coin cell should be used on the ConnectCore 9M 2443 development
board for powering the RTC unit on the module.
Measuring the current on the development board allows evaluation of power
needed for various board designs.
A current measuring option is implemented by adding a weak resistor in a
series with the power supply that needs to be measured.
Current measurement values might be performed for 3.3VDC, VLIO and VRTC.
Coin cell battery voltage can also be monitored by adding a jumper between
the coincell and the VRTC power supply on the ConnectCore 9M 2443 module.
Reset A push-button allows manual reset by connecting RSTIN# to ground. The reset
controller is located on the ConnectCore 9M 2443 module.
JTAG interface
The module JTAG interface is supported through a 20-pin Multi-ICE JTAG
connector, which is located on the ConnectCore 9M 2443 development board.
This connector supports RTCK signal (optional).
TRST# signal has a 2.2K pull-down resistor on module. This means a debugger
with push-pull output at TRST# is needed and open drain is not working.
I²C interface
The ConnectCore 9M 2443 module provides access to one I²C channel. 4k7 pull-
ups resistors are used on the module for these signals.
I²C signals are accessible on the 1:1 expansion connectors and on the
dedicated I²C header.
PoE connectors
65 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
The POE connectors support the PoE Application Module.
. . . . .
Peripheral
application
connector
LCD Application
Kit Connector
VGA interface
UARTs
UART A - console
The Peripheral application connector supports the JumpStart Application
Modules.
The LCD Application Kit Connector supports the JumpStart LCD modules.
A standard VGA Interface is provided to support an external monitor.
The ConnectCore 9M 2443 development board is supporting the 4 UARTs
available on the ConnectCore 9M 2443 module. Detailed usage, of each UART is
described in the following chapters.
The ConnectCore 9M 2443 UART A signals are used as the standard console.
This UART supports TXD, RXD and CTS#, RTS# handshake lines.
UART A signals are available on RS232 levels. This connector is a DSUB9 male
which will connect to the host via null modem cable.
UART A is providing status LEDs on TXD, RXD, RTS# and CTS# handshake signals.
UART B - UART /
MEI
UART C - TTL
interface
UART D - TTL
interface
UART A line drivers can be disabled if required.
The ConnectCore 9M 2443 UART B signals are full-function UART, providing
access to TXD, RXD and CTS#, RTS# handshake signals.
UART B signals are available on RS232 levels. This connector is a DSUB9 male
which will connect to the host via null modem cable.
UART B is providing status LEDs on TXD, RXD, RTS#, CTS#.
UART B is also the interface supporting the Digi MEI interface (RS422/RS485).
UART B line drivers can be disabled if required.
The ConnectCore 9M 2443 UART C signals provide access to TXD, RXD and CTS#,
RTS# (if UART D is not used, else TXD, RXD only).
UART C signals are available on TTL levels. Connector is a 2x5-pin 2.54mm
header compatible with TTL2RS232 adapter (P/N: FS-276).
The ConnectCore 9M 2443 UART D signals provide access to TXD and RXD signals
(if UART C handshake is not used).
UART D signals are available on TTL levels. This connector is a 2x5-pin 2.54mm
header compatible with TTL2RS232 adapter (P/N: FS-276).
www.ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference.com 66
Chapter 2
SPI interface(s) The ConnectCore 9M 2443 development board provides access to ConnectCore
9M 2443 module's SPI interfaces SPI0 and SPI1.
HS SPI0 signals are available on the dedicated SPI 6-pin header.
HS SPI0 and SPI1 are also available on the 1:1 extension connectors.
67 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
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Camera interface
Camera
interface,
X28
The camera interface supports ITU R BT-601/656 YCbCr 8-bit standard and Memory.
Maximum input size is 4096x4096 pixels (2048x2048 pixels for scaling).Two scalers
exist. One is the preview scaler, which is dedicated to generate smaller size images
for preview. The other one is the codec scaler, which is dedicated to generate codec
useful images like plane type YCbCr 4:2:0 or 4:2:2.
. . . . .
The Digi Multimedia Application Kit (Digi P/N CC-ACC-MMK-2443) provides a camera
www.ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference.com 68
sensor reference design. Please contact your distributor or Digi sales office for
details.
Chapter 2
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Configuration
switches, S4
Power switch, S2
Serial
port A
switch,
S7
Serial
port B
switch,
S6
Reset button, S1
User
button 1,
S3
User
button 2,
S5
Switches and push-buttons
Reset control, S1 The reset push-button S1, resets the module. On the module, RSTOUT# and
PWRGOOD are produced for peripherals. A push-button allows manual reset by
connecting RSTIN# to ground. The reset controller is located on the module.
Power switch, S2 The development board has an ON/OFF switch S2. The power switch S2 can switch
both 9V-30V input power supply and 12V coming out of the PoE module. However, if
a power plug is connected to the DC power jack, the PoE module is disabled. User
pushbuttons, S3 and S5.
69 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Use the user push-buttons to interact with the applications running on the module.
Use these module signals to implement the push-buttons:
Signal name Switch
(pushbutton
USER_PUSH_BUTTON_1 S3 GPF0
USER_PUSH_BUTTON_2 S5 GPF6
GPIO used
. . . . .
Legend for multipin switches
Module
configuration
switches, S4
Serial port B MEI
configuration
switches
Switches S4, S6, and S7 are multi-pin switches. In the description tables for these
switches, the pin is designated as S[switch number].[pin number]. For example, pin
1 in switch 2 is specified as S4.1.
Use S2 to configure the module:
Dipswitch
position
1 DEBUGEN#
2 Reserved
3OCD_EN
4Reserved
5 SW_CONF4
Usage
Use S6 to configure the line interface for serial port B MEI.
Switch
pin
Function Comments
S6.1 On = RS232 transceiver enabled
S6.2 On = Auto Power Down enabled
S6.3 On = 2 wire interface (RS422/RS485)
www.ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference.com 70
RS422/RS485 transceiver disabled
Off= RS232 transceiver disabled
RS422/RS485 transceivers enabled
Off = Auto Power Down disabled
Off = 4 wire interface (RS422)
Auto Power Down is not supported on
this board. This signal is only accessible
to permit the user to completely disable
the MEI interface for using signals for
other purposes. To disable the MEI
interface go in RS232 mode (S6.1 = ON)
and activate the Auto Power Down
feature (S6.2 = ON). Be sure that no
cable is connected to connector X3.
Chapter 2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test points
+5V and GND,
MPIO / MP30
Test points
+3.3V and
GND, MP13 /
MP2
Test points
Switch
pin
S6.4 On = Terminator on
Function Comments
Off = No termination
The development board provides four test points that can be identified by board
label or test point number.
Numbers and
description
71 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Test
point
MP10 +5V DC/DC regulator (U15) with 9-30VDC input
MP30 GND Common ground
MP13 +3.3V DC/DC regulator (U23) with 5VDC input
MP2 GND Common ground
Label Source / comment
Factory default interface configuration for development
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
board
These interfaces are enabled as shown per factory default configuration:
Interface Factory default status
LCD VGA Enabled
2
I
C Enabled
2
C user-driven I/Os Enabled
I
EIA-232 Serial Port A Enabled
EIA-485 Serial Port A Disabled
EIA-232 Serial Port B Enabled
TTL Serial Port C Disabled
TTL Serial Port D Disabled
SPI Serial Port B Disabled
. . . . .
www.ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference.com 72
Chapter 2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User LED1,LE5
SD/MMC activity LED, LE9
Serial
port A
status
LEDs
Serial
port B
status
LEDs
Debug
LED
LE3
Wireless
LAN
activity
LED,
LE10
Power
LED
+5V,
LE4
Power LED
3-3V, LE7
Power LED 9-30V, LEI
User LED2, LE6
Power LED
9-30V, LEI
LEDs
WLAN, LE10 LED indicating WLAN activity.
Power LEDs,
LE1, LE4, and
LE7
The power LEDs are all red. These power supplies must be present and cannot be
switched.
LE1 ON indicates +9VDC / +30VDC power is present
LE4 ON indicates +5VDC power is present
LE7 ON indicates +3.3VDC power is present
73 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
. . . . .
Serial port A
(R232), X27
Serial port B,
(MEI), X16
Serial port C,
TTL, X19
Serial port D,
TTL, X22
User LEDs, LE5
and LE6
Serial status
LEDs
The user LEDs are controlled through applications running on the modules if J6 and
J8 are set. Use these module signals to implement LEDs:
Signal name LED GPIO used
USER_LED1# LE5 GPL11
USER_LED2# LED6 GPL10
The development board has two sets of serial port LEDs - eight for serial port A and
eight for serial port B. The LEDs are connected to the TTL side of the RS232 or
RS422/485 transceivers.
Green means corresponding signal is high
Red means corresponding signal is low
www.ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference.com 74
Chapter 2
Status LEDs
Serial port A
Status LEDs
Serial port B
LED reference Function
RED GREEN
LE59 LE44 CTS0#/GPH8
LE58 LE43 RTS0#/GPH9
LE57 LE42 RXD0/GPH1
LE41 LE40 TXD0/GPH0
LED reference Function
RED GREEN
LE63 LE48 CTS1#/GPH10
LE62 LE47 RTS1#/GPH11
LE61 LE46 RXD1/GPH3
Debug, LE3
LE60 LE45 TXD01GPH2
Signal name LED GPIO used
DEBUG_LED LE8 GPB2/TOUT2
75 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
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Battery and battery holder
Battery and battery holder,
G1
. . . . .
Battery holder Battery
Coin-Cell Holder for CR2032 Battery Lithium coin cell
SMD 200mAh
Keystone 1061TR Renata CR2032
The development board provides a battery to back up the module integrated RTC
while the main power is disconnected.
The Jumper J1 controls whatever battery power is available. For more information
see the section, “Jumpers” on page 103 of this document.
www.ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference.com 76
Chapter 2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial port A
(R232), X27
Serial port B,
(MEI), X16
Serial port C,
TTL, X19
Serial port D,
TTL, X22
Serial UART ports
Serial port A,
RS232, X27
The serial (UART) port A connector, X27, is a DSUB9 male connector and is also used
as the standard console port. This asynchronous serial port is DTE and requires a
null-modem cable to connect to a computer serial port.
The serial port A interface corresponds to S3C2443 UART 0. The line driver is
enabled or disabled using S7.2.
Refer to page 68 for information about switch settings.
77 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Serial port A pins are allocated as shown below:
Pin Function Defaults to
1NC 2 RXD GPH1
3 TXD GPH0
4NC 5 GND 6NC 7RTS# GPH9
8CTS# GPH8
9NC -
By default, serial A signals are configured to their respective GPIO signals. It is the
responsibility of the driver to configure them properly.
. . . . .
www.ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference.com 78
Chapter 2
Serial port B,
MEI interface,
X16
The serial (UART) port B connector X16 is a DSUB9 male connector. This
asynchronous serial port is DTE and requires a null modem cable to connect to a
computer serial port.
The serial port B MEI (multiple electrical interface) interface corresponds to
S3C2443 UART port B. The line drivers are configured using switch S6.
Note that all port B pins are allocated as shown:
Pin RS232
function
1CTS-n/a
2 RXD GPH3 RX+ GPH3
3 TXD GPH2 TX+ GPH2
4RTS-n/a
5 GND - GND 6RX-n/a
7 RTS# GPH11 RTS+ GPIO11
8 CTS# GPH10 CTS+ GPH10
RS232
default
RS485
function
RS485
default
Serial port C,
TTL interface,
X19
9TX-n/a
By default serial B signals are configured to their respective GPIO signals. It is the
responsibility of the driver to configure them properly.
Pin Function Defaults to
1NC
2NC
3 RXD2 GPH5
4 RTS2#/TXD3 GPH6
5 TXD2 GPH4
6 CTS2#/RXD3 GPH7
7NC
8NC
9GND
10 +3.3V
79 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Serial port D,
TTL interface,
X22
. . . . .
Pin Function Defaults to
1NC
2NC
3CTS2#/RXD3GPH7
4NC
5RTS2#/TXD3GPH6
6NC
7NC
8NC
9 GND
10 +3.3V
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Chapter 2
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I2C header, X22
I2C interface
I2C connector,
X22
The table below provides the pinout of the I2C header.
Pin Function Comment
1 I2C_SDA GPE15
2+3.3V
3I2C_SCL GPE14
4GND
See page 91 for information about I/O expander I2C device on the development
board.
81 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
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SPI interface
SPI header, X8
. . . . .
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Chapter 2
X8-SPI connector The following table provides the pinout of the SPI header:
Pin Function Comment
1+3.3V
2 SPIMOSI0 GPE12 or High speed SPI Master Out Slave In
3 SPI_MISO0 GPE12 or High speed SPI Master In Slave Out
4 SPI_CLK0 GPE12 or High speed SPI clock
5 SS0# GPE13 or High speed SPI Chip Select
6GND
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Current Measurement Option
Current
Measurement
Option (CMO)
+5V development
board and
module, R80
Current
Measurement
Option (CMO)
+3.3V
development
board and
module, R39
Current Measurement Option
(CMO) +3.3V, R70
VLIO, R76
. . . . .
Measurement
options
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The Current Measurement Option uses 0.025R ohm series resistors to measure the
current. The ConnectCore 9M 2443 Development board can measure:
the +5V current used by the development board and module (through R80),
the +3.3V current into the +3.3V regulator U23 (through R39),
the +3.3V current into the module (through R70), and
the VLIO current into the module (through R76).
Chapter 2
How the CMO
works
To measure the load current used on different power supplies, measure DC voltage
across the sense (CMO) resistor. The value of the resistor is 0.025R ± 1%.
Calculate the current using this equation: I = U/R
where
I = current in Ampere
U = measured voltage in Volt
R = 0.025 Ohm
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PoE module connectors - IEEE802.3af
PoE header, X26
PoE header, X17
The development board has two PoE module connectors, X9 and X26. The PoE
module is an optional accessory item that can be plugged on the development board
through the two connectors:
X26, output connector: Provides the output power supply from the PoE module.
X17, input connector: Provides access to the PoE signals coming from the
Ethernet interface.
. . . . .
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Chapter 2
PoE module
Jump Start
development board
The PoE module Plug in the PoE module at a right angle to the development board, as shown in this
drawing:
PoE connector
(power in), X17
Pin Function
1POE_TX_CT
2POE_RX_CT
3 POE_RJ45_4/5
4 POE_RJ45_7/8
PoE connector
(power out), X26
Pin Function
1+12V
2+12V
3GND
4GND
5 POE_GND
6 POE_GND
POE_GND The development board provides access to POE_GND allowing it to be turned off
when power is provided through Power Jack X26.9 and X26.5.
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VGA connector
VGA connector, X18
. . . . .
VGA connector,
X18
The VGA connector is a 15-pin female connector, labeled X18.
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Chapter 2
X18 pin
assignment
Pin Signal Comment
1 VGA_RED
2 VGA_GREEN
3 VGA_BLUE
4 NC (Monitor ID2) Monitor ID2 is not implemented on the
development board
5 GND
6 VGA_GND (RED_RETURN)
7 VGA_GND (GREEN_RETURN)
8 VGA_GND (BLUE_RETURN)
9NC
10 GND (SYNC_RETURN)
11 NC (Monitor ID0) Monitor ID0 is not implemented on the
development board
12 NC
13 HSYNC
14 VSYNC
15 NC
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USB connectors
USB host
connector,
X14
USB device
connector,
X15
. . . . .
USB device
connector, X15
USB host
connector, X14
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This standard type B receptacle provides access to the module USB device
interface. The module supports low, full, and high speed USB2.0 connectivity.
This standard type A receptacle provides access to the module USB host interface.
The module supports USB 2.0 device connectivity using low and full speed data
rates.
Chapter 2
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Digital I/O
connector, X44
Digital I/O
Manufacturer part number: BlockMaster MTS0900T
I2C digital I/O
expansion, X44
91 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
The development board provides a 3.81mm (1.50”) green terminal block, X44, for
additional digital I/Os. The I2C I/O port chip is on-chip ESD-protected, 5V tolerant,
and provides an open drain interrupt output.
The I/O expander is a Philips PCA9554D at I2C address 0x20 (bits A7..A1), or
0x40/0x41 if expressed in 8-bit format including the R/W bit at the end (bits A7..A1
+ R/W bit)."
The pins are allocated as shown below:
Pin Function Pin Function
1IO_0 6IO_5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Function Pin Function
JTAG connector, X13
R76 R70
2IO_1 7IO_6
3IO_2 8IO_7
4 IO_3 9 GND
5IO_4
JTAG interface
. . . . .
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Chapter 2
Standard JTAG
ARM connector,
X13
The standard JTAG ARM connector is a 20-pin header and can be used to connect
development tools such as Digi JTAG Link, ARM Multi-ICE, Abatron BDI2000 and
others.
Pin Signal Pin Signal
1+3.3V 2+3.3V
3TRST# 4GND
5 TDI 6 GND
7TMS 8GND
9 TCK 10 GND
11 RTCK (optional) 12 GND
13 TDO 14 GND
15 SRESET# 16 GND
17 No connect 18 GND
19 No connect 20 GND
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Peripheral (extension) headers
Peripheral application
header, X33
LCD application header, X5
. . . . .
The development board provides two, 2x25-pin, 0.10” (2.54mm) pitch headers for
supporting application-specific daughter cards/expansion boards:
X5, LCD application header. Provides access to the LCD signals and SPI signals
for touch controller purposes. Use with a Digi-provided application kit or
attach your own application board.
X33, Peripheral application header. Provides access to an 8/16 bit data bus, 8-
2
bit address bus, and control signals (such as CE#, WE#), as well as I
power. Using these signals, you can connect Digi-specific extension modules or
your own daughter card to the module’s address/data bus.
C and
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Chapter 2
LCD application
header, X5
Pin Signal Pin Signal
1G ND 2VD18
3 VD19 4 VD20
5 VD21 6 GND
7 VD22 8 VD23
9 VD10 10 VD11
11 GND 12 VD12
13 VD13 14 VD14
15 VD15 16 GND
17 VD21 18 VD3
19 VD4 20 VD5
21 GND 22 VD6
23 VD7 24 Reserved (LCD_D18)
25 Reserved (LCD_D19) 26 GND
27 Reserved (LCD_D20) 28 Reserved (LCD_D21)
29 I2C_SDA 30 I2C-SCL
31 GND 32 VCLK
33 VM 34 VLINE
35 VFRAME 36 EINT13
37 LCD_PWREN# 38 +3.3V
39 TSXP 40 TSYP
41 TSXM 42 TSYM
43 +3.3V 44 +3.3V
45 NC 46 NC
47 NC 48 +3.3V
49 +3.3V 50 GND
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Peripheral
application
header, X 3
3
Pin Signal Pin Signal
1G ND 2D0
3D1 4D2
5 D3 6 GND
7D4 8D5
9D6 10D7
11 GND 12 D8
13 D9 14 D10
15 D11 16 GND
17 D12 18 D13
19 D14 20 D15
21 GND 22 8 bit / 16 bit
+3.3V selects 8-bit data bus
23 GND 24 +3.3V
25 +3.3V 26 A0
27 A1 28 A2
29 A3 30 GND
31 A4 32 A5
33 A6 34 A7
35 GND 36 A8
37 A9 38 GND
39 CS1# 40 I2C_SDA
41 WE# 42 OE#
43 I2C_SCL 44 EINT13
45 +3.3V 46 +3.3V
47 USBPO 48 USBNO
49 No comment 50 GND
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Chapter 2
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Module
connectors
X1 and X2
Signal rails
X10, X11,
X30 and
X31
Signal rails
X20, X21,
X40 and
X41
Extended
module
connectors
X3 and X4
Module connectors and signal rails
Signal rails The development board provides two 4x32 pin signal rails, labeled x10/X11 and
X20/X21. These connectors are 1:1 copies of the modules pins and can be used for
measurement or development purposes.
X10 and X11 correspond to module connector X1.
X20 and X21 corresponds to module connector X2.
The development board also provides two 4x20 pin test connectors for extended
footprint modules:
X30 and X31 correspond to extended module connector X3.
X40 and X41 correspond to extended module connector X4.
97 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
X10 pinout
. . . . .
Pin Signal Pin Signal
A1 G ND B1 RSTIN#
A2 TCK B2 TMS
A3 TRST# B3 DEBUGEN#
A4 CONF4/VD1 B4 CONF4/VD8
A5 CONF7/VD17 B5 TXDO
A6 CTS0# B6 NC
A7 RXD2 B7 RTS2#/TXD3
A8 CAMDATA0 B8 CAMDATA1
A9 CAMFDATA4 B9 CAMDATA5
A10 USB_PWREN# B10 VBUSDET
A11 VD3 B11 VD4
A12 VD7 B12 CF_CD#
A13 VD11 B13 VD12
A14 VD15 B14 EINT14
A15 VD19 B15 VD20
A16 VD23 B16 LCD_PWREN#
A17 VLINE B17 VCLK
A18 LCDVF1 B18 LCDVF2
A19 WLAN_DISABLE# B19 WACT_LED#
A20 SDDATA0 B20 SDDATA1
A21 SDDATA3 B21 USERKEY1/EINT0
A22 SS1# B22 SPIMISO1
A23 SD_WP# B23 SD_CD#
A24 WE# B24 WAIT#
A25 CS3# B25 CS4#
A26 NC B26 NC
A27 DQM2 B27 DQM3
A28 SPIMOS10 B28 SPICLK0
A29 USB_DT/PW B29 USBP
A30 GND B30 GND
A31 NC B31 NC
A32 +3.3V B32 +3.3V
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Chapter 2
X11 pinout
Pin Signal Pin Signal
C1 PWRGOOD D1 RSTOUT#
C2 TDI D2 TDO
C3 NAND_FWP# D3 CONF2/VD0
C4 CONF5/VD9 D4 CONF6/VD16
C5 RXD0 D5 RTS0#
C6 NC D6 TXD2
C7 RXD2 D7 NC
C8 CTS2#/RXD3 D8 CAMDATA3
C9 CAMDATA6 D9 CAMDATA7
C10 GND D10 VD2
C11 VD5 D11 VD6
C12 EINT11 D12 VD10
C13 VD13 D13 VD14
C14 TCLK0 D14 VD18
C15 VD21 D15 VD22
C16 VM D16 VFRAME#
C17 LEND D17 LCDVF0
C18 TOUT0 D18 TOUT1
C19 SDCLK D19 SDCMD
C20 GND D20 SDDATA2
C21 X1.83 D21 DEBUG_LED
C22 USERLED1/SPIMOSI1 D22 USERLED2/SPICLK1
C23 X1.91 D23 OE#
C24 CS1# D24 CS2#
C25 PWREN D25 BATT_FLT#
C26 DQM0 D26 DQM1
C27 SS0# D27 SPIMISO0
C28 I2C_SCL D28 I2C_SDA
C29 USBN D29 VRTC
C30 VLIO D30 VLIO
C31 NC D31 NC
C32 +3.3V D32 +3.3V
99 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
X20 pinout
. . . . .
Pin Signal Pin Signal
A1 USBP0 B1 GND
A2 A1 B2 A2
A3 A5 B3 A6
A4 A9 B4 A10
A5 A13 B5 A14
A6 A17 B6 A18
A7 A21 B7 A22
A8 A25 B8 X2-30
A9 RXD1 B9 RTS1#
A10 XDREQ1# B10 XDACK0#
A11 AIN4 B11 AIN5
A12 AIN2 B12 AIN3
A13 AIN8/XM B13 AIN9/XP
A14 NC B14 NC
A15 XBREQ# B15 XBACK#
A16 I2SSDO/ACDO B16 I2SSDI/ACDI
A17 I2SLRCK/AC_RESET#GPEO B17 NC
A18 LEDSPD B18 NC
A19 OE_CF# B19 WE_CF#
A20 REG_CF# B20 SDDATA1
A21 D0 B21 D1
A22 D4 B22 D5
A23 D8 B23 D9
A24 D12 B24 D13
A25 SD1_DAT0 B25 SD1_DAT1
A26 SD1_DAT4 B26 SD1_DAT5
A27 SD1_CMD B27 SD1_CLK
A28 SD1_LED# B28 USERKEY2/EINT6
A29 X2.113 B29 X2.114
A30 X1.117 B30 X2.118
A31 VLIO B31 VRTC
A32 +3.3V B32 +3.3V
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