DFI CH960-CM246, CH960-HM370, CH960-QM370 User Manual
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CH960-CM246/QM370/HM370
COM Express Basic Module
User’s Manual
A48600910
Preliminary
Version
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2
Copyright
This publication contains information that is protected by copyright. No part of it may be reproduced in any form or by any means or used to make any transformation/adaptation without
the prior written permission from the copyright holders.
This publication is provided for informational purposes only. The manufacturer makes no
representations or warranties with respect to the contents or use of this manual and specifically disclaims any express or implied warranties of merchantability or fitness for any particular
purpose. The user will assume the entire risk of the use or the results of the use of this document. Further, the manufacturer reserves the right to revise this publication and make changes
to its contents at any time, without obligation to notify any person or entity of such revisions
or changes.
Changes after the publication’s first release will be based on the product’s revision. The website
will always provide the most updated information.
© 2019. All Rights Reserved.
Trademarks
Product names or trademarks appearing in this manual are for identification purpose only and
are the properties of the respective owners.
COM Express Specification Reference
PICMG® COM Express ModuleTM Base Specification.
https://www.picmg.org/
FCC and DOC Statement on Class B
This equipment has been tested and found to comply with the limits for a Class B digital
device, pursuant to Part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference
to radio communications. However, there is no guarantee that interference will not occur in a
particular installation. If this equipment does cause harmful interference to radio or television
reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and the receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver
is connected.
• Consult the dealer or an experienced radio TV technician for help.
Notice:
1. The changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment.
2. Shielded interface cables must be used in order to comply with the emission limits.
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Table of Contents
Copyright ........................................................................................................... ..2
Trademarks ........................................................................................................2
COM Express Specification Reference ................................................... 2
FCC and DOC Statement on Class B ..................................................... 2
Warranty .............................................................................................................. 4
Static Electricity Precautions ...................................................................... 4
Safety Measures ..............................................................................................4
About the Package .........................................................................................5
Optional Items..................................................................................................5
Before Using the System Board ............................................................... 5
Chapter 1 - Introduction .............................................................................6
Specifications ................................................................................................6
Features ..........................................................................................................7
Chapter 2 - Concept ....................................................................... 8
COM Express Module Standards .............................................................. 8
Specification Comparison Table ...............................................................9
Chapter 3 - Hardware Installation .............................................. 10
Board Layout ............................................................................................... 10
Block Diagram ............................................................................................. 11
System Memory .......................................................................................... 12
Installing the SODIMM Module ...................................................................12
Connectors ................................................................................................... 13
CPU Fan Connector ..................................................................................... 13
COM Express Connectors ............................................................................14
COM Express Connectors Signals and Descriptions ....................................... 16
Standby Power LED ................................................................................... 27
Cooling Option ............................................................................................ 27
Heat Sink with Fan .....................................................................................27
Installing CH960-CM246/QM370/HM370 onto a Carrier Board .... 28
Chapter 4 - BIOS Setup ............................................................... 30
Overview....................................................................................................... 30
AMI BIOS Setup Utility ............................................................................. 31
Main .......................................................................................................... 31
Advanced ................................................................................................... 32
Chipset ...................................................................................................... 44
Security ...................................................................................................... 47
Boot........................................................................................................... 48
Save & Exit ................................................................................................49
Updating the BIOS .................................................................................... 49
Notice: BIOS SPI ROM ............................................................................. 50
Chapter 5 - Supported Software ........................................................... 51
Chapter 6 - RAID (CH960-CM246/QM370 only)........................58
Chapter 7 - Intel AMT Settings (CH960-CM246/QM370 only)
............................................................................................................................... 60
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Warranty
1. Warranty does not cover damages or failures that arised from misuse of the product, inability to use the product, unauthorized replacement or alteration of components and product specifications.
2. The warranty is void if the product has been subjected to physical abuse, improper installation, modification, accidents or unauthorized repair of the product.
3. Unless otherwise instructed in this user’s manual, the user may not, under any circumstances, attempt to perform service, adjustments or repairs on the product, whether in or
out of warranty. It must be returned to the purchase point, factory or authorized service
agency for all such work.
4. We will not be liable for any indirect, special, incidental or consequential damages to the
product that has been modified or altered.
Static Electricity Precautions
It is quite easy to inadvertently damage your PC, system board, components or devices even
before installing them in your system unit. Static electrical discharge can damage computer
components without causing any signs of physical damage. You must take extra care in handling them to ensure against electrostatic build-up.
1. To prevent electrostatic build-up, leave the system board in its anti-static bag until you are
ready to install it.
2. Wear an antistatic wrist strap.
3. Do all preparation work on a static-free surface.
4. Hold the device only by its edges. Be careful not to touch any of the components, contacts
or connections.
5. Avoid touching the pins or contacts on all modules and connectors. Hold modules or connectors by their ends.
Safety Measures
To avoid damage to the system:
• Use the correct AC input voltage range.
To reduce the risk of electric shock:
• Unplug the power cord before removing the system chassis cover for installation or servicing. After installation or servicing, cover the system chassis before plugging the power
cord.
Important:
Electrostatic discharge (ESD) can damage your processor, disk drive and other components. Perform the upgrade instruction procedures described at an ESD workstation only. If such a station is not available, you can provide some ESD protection by
wearing an antistatic wrist strap and attaching it to a metal part of the system chassis. If a wrist strap is unavailable, establish and maintain contact with the system
chassis throughout any procedures requiring ESD protection.
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About the Package
The package contains the following items. If any of these items are missing or damaged,
please contact your dealer or sales representative for assistance.
• One CH960-CM246/QM370/HM370 board
• One Cooler (Height: 36.58mm)
Optional Items
• COM332-B carrier board kit
• Heat spreader (Height: 11mm)
The board and accessories in the package may not come similar to the information listed
above. This may differ in accordance with the sales region or models in which it was sold. For
more information about the standard package in your region, please contact your dealer or
sales representative.
Before Using the System Board
Before using the system board, prepare basic system components.
If you are installing the system board in a new system, you will need at least the following
internal components.
• Memory module
• Storage devices such as hard disk drive, etc.
You will also need external system peripherals you intend to use which will normally include at
least a keyboard, a mouse and a video display monitor.
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Chapter 1 - Introduction
Specifications
Chapter 1
AUDIO Interface HD Audio
ETHERNET Controller CH960-CM246/QM370:
1 x Intel® I219LM with iAMT12.0 PCIe (10/100/1000Mbps)
CH960-HM370:
1 x Intel® I219LM PCIe (10/100/1000Mbps)
I/O USB 4 x USB 3.1
8 x USB 2.0
SATA CH960-CM246/QM370:
4 x SATA 3.0 (up to 6Gb/s)
RAID 0/1/5/10
CH960-HM370:
4 x SATA 3.0 (up to 6Gb/s)
DIO 1 x 8-bit DIO (Default 4 inputs and 4 outputs)
WATCHDOG
TIMER
Output &
Interval
System Reset, Programmable via Software from 1 to 255 Seconds
SECURITY TPM Available upon request
POWER Type 12V, 5VSB, VCC_RTC (ATX mode)
12V, VCC_RTC (AT mode)
OS SUPPORT Windows: Windows 10 IoT Enterprise 64-bit
Linux: Ubuntu 18.04
ENVIRONMENT Temperature Operating: 0 to 60°C or -40 to 85°C (with heat spreader)
Storage: -40 to 85°C
Humidity Operating: 5 to 90% RH
Storage: 5 to 90% RH
MECHANICAL Dimensions COM Express® Basic
95mm (3.74") x 125mm (4.9")
Compliance PICMG COM Express
®
R2.1, Type 6
SYSTEM Processor CH960-CM246/QM370:
8th Generation Intel
®
Core™ Processors, BGA 1440
Intel
®
Xeon® E-2176M Processor, 6 Cores, 12M Cache, 2.7GHz (4.4GHz), 45W
Intel
®
Core™ i7-8850H Processor, 6 Cores, 12M Cache, 2.6GHz (4.3GHz), 45W
Intel
®
Core™ i5-8400H Processor, 4 Cores, 8M Cache, 2.5GHz (4.2GHz), 45W
CH960-HM370:
8th Generation Intel
®
Core™ Processors, BGA 1440
Intel
®
Core™ i5-8400H Processor, 4 Cores, 8M Cache, 2.5GHz (4.2GHz), 45W
Chipset Intel
®
CM246/QM370/HM370 Chipset
Memory CH960-CM246/QM370:
Two 260-pin SODIMM up to 32GB
Dual Channel DDR4 2666MHz (ECC Support with CM246)
CH960-HM370:
Two 260-pin SODIMM up to 32GB
Dual Channel DDR4 2666MHz
BIOS AMI SPI 128Mbit
GRAPHICS Controller Intel® HD Graphics
Feature OpenGL up to 4.5, DirectX 11, OpenCL 2.1
HW Decode: HEVC/H.265, H.264, M/JPEG, MPEG2, VC1/WMV9, VP8 (8-bit), VP9 (10-bit)
HW Encode: HEVC/H.265, M/JPEG, MPEG2, VP8
Display 1 x VGA/DDI (DDI available upon request)
1 x LVDS/eDP (eDP available upon request)
2 x DDI (HDMI/DVI/DP++)
VGA: resolution up to 1920x1200 @ 60Hz
LVDS: dual channel 24-bit, resolution up to 1920x1200 @ 60Hz
HDMI: resolution up to 4096x2160 @ 30Hz 24bpp
DVI: resolution up to 1920x1200 @ 60Hz
DP++/eDP: resolution up to 4096x2304 @ 60Hz
Triple
Displays
VGA + LVDS + DDI or VGA + DDI1 + DDI2
eDP + 2 DDI (available upon request)
EXPANSION Interface 1 x PCIe x16 or 2 x PCIe x8 (Gen 3)
8 x PCIe x1 or 2 x PCIe x4 or 4 x PCIe x2 (Gen 3)
1 x LPC
1 x I²C
1 x SMBus
2 x UART (TX/RX)
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Chapter 1
Features
• Watchdog Timer
The Watchdog Timer function allows your application to regularly “clear” the system at the set
time interval. If the system hangs or fails to function, it will reset at the set time interval so
that your system will continue to operate.
• DDR4
DDR4 delivers increased system bandwidth and improves performance at a lower power than
DDR3/DDR2.
• Graphics
The integrated Intel® HD engine delivers an excellent blend of graphics performance and features to meet business needs. It delivers enhanced media conversion rates and higher frame
rates on 4K Ultra HD videos. These enhancements deliver the performance and compatibility
to meet the demand for business and home entertainment applications. The system supports 1
x VGA/DDI (DDI available upon request), 1 x LVDS/eDP (eDP available upon request) and 2 x
DDI (HDMI/DVI/DP++) display outputs.
• Serial ATA
Serial ATA is a storage interface that is compliant with SATA 1.0a specification. With speed of
up to 6Gb/s (SATA 3.0), it improves hard drive performance faster than the standard parallel ATA whose data transfer rate is 100MB/s. However, the bandwidth of the SATA 3.0 will be
limited by carrier board design.
• Gigabit LAN
The Intel® I219LM Gigabit LAN PHY controller features up to 1Gbps data transmission.
• USB
The system board supports the new USB 3.1 Gen2. It is capable of running at a maximum
transmission speed of up to 10 Gbit/s (1280 MB/s) and is faster than USB 3.1 Gen1 (5 Gbit/s,
or 625 MB/s), USB 2.0 (480 Mbit/s, or 60 MB/s) and USB 1.1 (12 Mbit/s). USB 3.1 reduces the
time required for data transmission, reduces power consumption, and is backward compatible
with USB 2.0. It is a marked improvement in device transfer speeds between your computer
and a wide range of simultaneously accessible external Plug and Play peripherals.
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Chapter 2
Chapter 2 - Concept
COM Express Module Standards
The figure below shows the dimensions of the different types of COM Express modules.
CH960-CM246/QM370/HM370 is a COM Express Basic module. Its dimension is 95mm x 125mm.
106.00
91.00
70.00
51.00
4.00
18.00
6.00
0.00
16.50
4.00
0.00
Extended
BasicCompact
Mini
74.20
80.00
91.00
121.00
151.00
Common for all Form Factors
Extended only
Basic only
Compact only
Compact and Basic only
Mini only
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Chapter 2
Specification Comparison Table
• 5 Indicates 12V-tolerant features on former VCC_12V signals.
•
6
Cells in the connected columns spanning rows provide a rough approximation of features
sharing connector pins.
The table below shows the COM Express standard specifications and the corresponding specifications supported on the CH960-CM246/QM370/HM370 module.
Connector Feature
COM Express Module Base Specification
Type 6
(No IDE or PCI, add DDI+ USB3) Min / Max
DFI CH960
Type 6
A-B
A-B PCI Express Lanes 0 - 5 1 / 6 6
A-B LVDS Channel A 0 / 1 1
A-B LVDS Channel B 0 / 1 1
A-B eDP on LVDS CH A pins 0 / 1 1
A-B VGA Port 0 / 1 1
A-B TV-Out NA NA
A-B DDI 0 NA NA
A-B
5
Serial Ports 1 - 2 0 / 2 2
A-B CAN interface on SER1 0 / 1 0
A-B SATA / SAS Ports 1 / 4 4
A-B AC’97 / HDA Digital Interface 0 / 1 1
A-B USB 2.0 Ports 4 / 8 8
A-B USB Client 0 / 1 0
A-B USB 3.0 Ports NA NA
A-B LAN Port 0 1 / 1 1
A-B Express Card Support 1 / 2 2
A-B LPC Bus 1 / 1 1
A-B SPI 1 / 2 1
A-B
SDIO (muxed on GPIO) 0 / 1 NA
General Purpose I/O 8 / 8 8
A-B SMBus 1 / 1 1
A-B I2C 1 / 1 1
A-B Watchdog Timer 0 / 1 1
A-B Speaker Out 1 / 1 1
A-B External BIOS ROM Support 0 / 2 1
A-B Reset Functions 1 / 1 1
A-B
6
System I/O
System Management
Module Pin-out - Required and Optional Features C-D Connector.
Module Pin-out - Required and Optional Features A-B Connector.
Connector Feature
COM Express Module Base Specification
Type 6
(No IDE or PCI, add DDI+ USB3) Min / Max
DFI CH960
Type 6
A-B
A-B Thermal Protection 0 / 1 1
A-B Battery Low Alarm 0 / 1 1
A-B Suspend/Wake Signals 0 / 3 2
A-B Power Button Support 1 / 1 1
A-B Power Good 1 / 1 1
A-B VCC_5V_SBY Contacts 4 / 4 4
A-B
5
Sleep Input 0 / 1 1
A-B
5
Lid Input 0 / 1 1
A-B
5
Fan Control Signals 0 / 2 1
A-B Trusted Platform Modules 0 / 1 1 (optional)
A-B
A-B VCC_12V Contacts 12 / 12 12
Power Management
Power
Connector Feature
COM Express Module Base Specification
Type 6
(No IDE or PCI, add DDI+ USB3) Min / Max
DFI CH960
Type 6
C-D
PCI Express Lanes 16 - 31 0 / 16 16
PCI Express Graphics (PEG) 0 / 1 1
Muxed SDVO Channels 1 - 2 NA NA
PCI Express Lanes 6 - 15 0 / 2 2
PCI Bus - 32 Bit NA NA
PATA Port NA NA
LAN Ports 1 - 2 NA NA
DDIs 1 - 3 0 / 3 3 (DDI3 option)
USB 3.1 Ports 0 / 4 4
C-D
C-D VCC_12V Contacts 12 / 12 12
Power
C-D
6
C-D
6
System I/O
qp
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Chapter 3
Chapter 3 - Hardware Installation
Board Layout
Top View
Bottom View
SPI Flash BIOS
BGA 1440
Core
Intel
CPU fan
Standby Power LED
Intel
CM246/QM370/HM370
DDR4_1 SODIMM
DDR4_2 SODIMM
Standby
Power LED
CPU fan
1
Intel
I219LM
CH7517
PTN3460
D110
D1
C110
C1
B110
B1
TPM (optional)
iTE
IT8528E
A110
A1
COM Express Connector
COM Express Connector
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Chapter 3
Block Diagram
Mobile
Intel
®
HM370
Chipset
USB 3.0 4x
Processor
2x Graphics
CORES
Memory
Controller
A / B
8th Generation
Intel
®
Core™ i7 (6 CORE)
DMI
DDI Port 1
USB 3.0 4x
PCIe (2 x1/1 x2)
C / D
PCIe (2 x1/1 x2)
DDR4 2666MHz
SODIMM
Channel A
DDR4 2666MHz
SODIMM
Channel B
DDI Port 2
EEPROM
SMBus
LPC Bus
LPC Bus
8-bit DIO
WDT
I
2
C Bus
Serial Port 0,1
Fan PWM/
TACH_IN
SLP/LID
SLP/LID
TCA6408A
Embedded
Controller
IT8528E
,
EEPROM
SMBus
t DIO8
O
TCA6408A
SPI Flash
SPI Bus
SATA 3.0 4x
SATA 3.0 4x
Intel®GLAN
I219LM
MDI
PCIe x1
PCIe (4 x1/1 x4)
PCIe (4 x1/1 x4)
HDA
HDA
USB 2.0 8x
USB 2.0 8x
DDI Port 3 (optional)
PCIe x16 (PEG)
CH7517
VGA
PCIe (2 x1/1 x2)
PCIe
(2
x1/1
x2)
D
MI
D
DI Port 3 (optional
)
D
eDP
PTN3460
LVDS
(optional)
8th Generation
Intel
®
Core™ i5/i3 (4 CORE)
Mobile
Intel
®
CM246/QM370
Chipset
USB 3.1 4x
Processor
2x Graphics
CORES
Memory
Controller
A / B
8th Generation
Intel
®
Xeon® E3 / Core™ i7 (6 CORE)
DMI
DDI Port 1
USB 3.1 4x
PCIe (2 x1/1 x2)
C / D
PCIe (2 x1/1 x2)
DDR4 2666MHz
SODIMM
Channel A
DDR4 2666MHz
SODIMM
Channel B
DDI Port 2
EEPROM
SMBus
LPC Bus
LPC Bus
8-bit DIO
WDT
I
2
C Bus
TPM 1.2/2.0
(optional)
Serial Port 0,1
Fan PWM/
TACH_IN
SLP/LID
SLP/LID
TCA6408A
T
T
(
Embedded
Controller
IT8528E
,
EEPROM
SMBus
t DIO8
O
TCA
640
8A
SPI Flash
SPI Bus
SATA 3.0 4x
SATA 3.0 4x
Intel®GLAN
I219LM
MDI
PCIe x1
PCIe (4 x1/1 x4)
PCIe(4x1/1
x4)
HDA
HDA
USB 2.0 8x
USB 2.0 8x
DDI Port 3 (optional)
PCIe x16 (PEG)
CH7517
VGA
PCIe (2 x1/1 x2)
PCIe (2 x1/1 x2)
D
MI
D
DI Port
3 (
opti
onal
)
D
eDP
PTN3460
LVDS
(optional)
8th Generation
Intel
®
Core™ i5/i3 (4 CORE)
CH960-HM370
CH960-CM246/QM370
Chapter 3 Hardware Installation
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Chapter 3
CPU fan
Standby Power LED
System Memory
DDR4_2
Standby
Power LED
DDR4_1
Important:
Electrostatic discharge (ESD) can damage your board, processor, disk drives, add-in
boards, and other components. Perform installation procedures at an ESD workstation
only. If such a station is not available, you can provide some ESD protection by wearing an antistatic wrist strap and attaching it to a metal part of the system chassis. If
a wrist strap is unavailable, establish and maintain contact with the system chassis
throughout any procedures requiring ESD protection.
Important:
When the Standby Power LED is red, it indicates that there is power on the board.
Power off the PC then unplug the power cord prior to installing any devices. Failure to
do so will cause severe damage to the board and components.
Installing the SODIMM Module
1. Make sure the PC and all other peripheral devices connected to it has been powered down.
2. Disconnect all power cords and cables.
3. Locate the SODIMM socket on the system board.
4. Note the key on the socket. The key ensures that the module can be plugged into the
socket in only one direction.
Note:
The system board used in the following illustrations may not resemble the actual one.
These illustrations are for reference only.
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Chapter 3
CPU fan
Standby Power LED
Connectors
CPU Fan Connector
Connect the CPU fan’s cable connector to the CPU fan connector on the board. The cooling fan
will provide adequate airflow throughout the chassis to prevent overheating the CPU and board
components.
BIOS Setting
Configure the speed of the CPU fan in the “PC Health Status” submenu in the Advanced menu
of the BIOS.
3
1
Sense
+12V
Ground
6. Push down the module until the clips at each end of the socket lock into position. You will
hear a distinctive “click”, indicating the module is correctly locked into position.
Clip
Clip
5. Grasping the module by its edges, align the module into the socket at an approximately 30
degrees angle. Apply firm even pressure to each end of the module until it slips down into
the socket. The contact fingers on the edge of the module will almost completely disappear
inside the socket.
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Chapter 3
COM Express Connectors
The COM Express connectors are used to interface the CH960-CM246/QM370/HM370 COM
Express board to a carrier board. Connect the COM Express connectors (located on the solder
side of the board) to the COM Express connectors on the carrier board.
Refer to the “Installing CH960-CM246/QM370/HM370 onto a Carrier Board” section for more
information.
COM Express Connectors
Refer to the following page for the pin functions of these connectors.
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Chapter 3
COM Express Connectors-Continued
A1 GND (FIXED) B1 GND (FIXED) A56 PCIE_TX4- B56 PCIE_RX4- C1 GND (FIXED) D1 GND (FIXED) C56 PEG_RX1- D56 PEG_TX1A2 GBE0_MDI3- B2 GBE0_ACT# A57 GND B57 GPO2 C2 GND D2 GND C57 NC D57 GND
A3 GBE0_MDI3+ B3 LPC_FRAME# A58 PCIE_TX3+ B58 PCIE_RX3+ C3 USB_SSRX0- D3 USB_SSTX0- C58 PEG_RX2+ D58 PEG_TX2+
A4 GBE0_LINK100# B4 LPC_AD0 A59 PCIE_TX3- B59 PCIE_RX3- C4 USB_SSRX0+ D4 USB_SSTX0+ C59 PEG_RX2- D59 PEG_TX2A5 GBE0_LINK1000# B5 LPC_AD1 A60 GND (FIXED) B60 GND (FIXED) C5 GND D5 GND C60 GND (FIXED) D60 GND (FIXED)
A6 GBE0_MDI2- B6 LPC_AD2 A61 PCIE_TX2+ B61 PCIE_RX2+ C6 USB_SSRX1- D6 USB_SSTX1- C61 PEG_RX3+ D61 PEG
_TX3+
A7 GBE0_MDI2+ B7 LPC_AD3 A62 PCIE_TX2- B62 PCIE_RX2- C7 USB_SSRX1+ D7 USB_SSTX1+ C62 PEG_RX3- D62 PEG_TX3A8 GBE0_LINK# B8 LPC_DRQ0# A63 GPI1 B63 GPO3 C8 GND D8 GND C63 RSVD D63 RSVD
A9 GBE0_MDI1- B9 LPC_DRQ1# A64 PCIE_TX1+ B64 PCIE_RX1+ C9 USB_SSRX2- D9 USB_SSTX2- C64 RSVD D64 RSVD
A10 GBE0_MDI1+ B10 LPC_CLK A65 PCIE_TX1- B65 PCIE_RX1- C10 USB_SSRX2+ D10 USB_SSTX2+ C65 PEG_RX4+ D65 PEG_TX4+
A11 GND (FIXED) B11 GND (FIXED) A66 GND B66 WAKE0# C11 GND (FIXED) D11 GND (FIXED) C66 PEG_RX4- D66 PEG_TX4A12 GBE0_MDI0- B12 PWRBTN# A67 GPI2 B67 WAKE1# C12 USB_SSRX3- D12 USB_SSTX3- C67 RSVD D67 GND
A13 GBE0_MDI0+ B13 SMB_CK A68 PCIE_TX0+ B68 PCIE_RX0+ C13 USB_SSRX3+ D13 USB_SSTX3+ C68 PEG_RX5+ D68 PEG_TX5+
A14 NC B14 SMB_DAT A69 PCIE_TX0- B69 PCIE_RX0- C14 GND D14 GND C69 PEG_RX5- D69 PEG_TX5-
A15 SUS_S3# B15 SMB_ALERT# A70 GND (FIXED) B70 GND (FIXED) C15 NA, no support D15 DDI1_CTRLCLK_AUX+ C70 GND (FIXED) D70 GND (FIXED)
A16 SATA0_TX+ B16 SATA1_TX+ A71 LVDS_A0+/eDP_TX2+ B71 LVDS_B0+ C16 NA, no support D16 DDI1_CTRLDATA_AUX- C71 PEG_RX6+ D71 PEG_TX6+
A17 SATA0_TX- B17 SATA1_TX- A72 LVDS_A0-/eDP_TX2- B72 LVDS_B0- C17 RSVD D17 RSVD C72 PEG_RX6- D72 PEG_TX6A18 SUS_S4# B18 SUS_STAT# A73 LVDS_A1+/eDP_TX1+ B73 LVDS_B1+ C18 RSVD D18 RSVD C73 GND D73 GND
A19 SATA0_RX+ B19 SATA1_RX+ A74 LVDS_A1-/eDP_TX1- B74 LVDS_B1- C19 PCIE_RX6+ D19 PCIE_TX6+ C74 PEG_RX7+ D74 PEG_TX7+
A20 SATA0_RX- B20 SATA1_RX- A75 LVDS_A2+/eDP_TX0+ B75 LVDS_B2+ C20 PCIE_RX6- D20 PCIE_TX6- C75 PEG_RX7- D75 PEG_TX7A21 GND (FIXED) B21 GND (FIXED) A76 LVDS_A2-/eDP_TX0- B76 LVDS_B2- C21 GND (FIXED) D21 GND (FIXED) C76 GND D76 GND
A22 SATA2_TX+ B22 SATA3_TX+ A77 LVDS_VDD_EN/eDP_VDD_EN B77 LVDS_B3+ C22 PCIE_RX7+ D22 PCIE_TX7+ C77 RSVD D77 RSVD
A23 SATA2_TX- B23 SATA3_TX- A78 LVDS_A3+ B78 LVDS_B3- C23 PCIE_RX7- D23 PCIE_TX7- C78 PEG_RX8+ D78 PEG_TX8+
A24 SUS_S5# B24 PWR_OK A79 LVDS_A3- B79 LVDS_BKLT_EN/eDP_BKLT_EN C24 DDI1_HPD D24 RSVD C79 PEG_RX8- D79 PEG_TX8A25 SATA2_RX+ B25 SATA3_RX+ A80 GND (FIXED) B80 GND (FIXED) C25 NA, no support D25 RSVD C80 GND (FIXED) D80 GND (FIXED)
A26 SATA2_RX- B26 SATA3_RX- A81 LVDS_A_CK+/eDP_TX3+ B81 LVDS_B_CK+ C26 NA, no support D26 DDI1_PAIR0+ C81 PEG_RX9+ D81 PEG_TX9+
A27 BATLOW# B27 WDT A82 LVDS_A_CK-/eDP_TX3- B82 LVDS_B_CK- C27 RSVD D27 DDI1_PAIR0- C82 PEG_RX9- D82 PEG_TX9A28 (S)ATA_ACT# B28 NC A83 LVDS_I2C_CK/eDP_AUX+ B83 LVDS_BKLT_CTRL/eDP_BKLT_CTRL C28 RSVD D28 RSVD C83 RSVD D83 RSVD
A29 AC/HDA_SYNC B29 AC/HDA _SDIN1 A84 LVDS_I2C_DAT/eDP_AUX- B84 VCC_5V_SBY C29 NA, no support D29 DDI1_PAIR1+ C84 GND D84 GND
A30 AC/HDA _RST# B30 AC/HDA _SDIN0 A85 GPI3 B85 VCC_5V_SBY C30 NA, no support D30 DDI1_PAIR1- C85 PEG_RX10+ D85 PEG_TX10+
A31 GND (FIXED) B31 GND (FIXED) A86 RSVD B86 VCC_5V_SBY C31 GND (FIXED) D31 GND (FIXED) C86 PEG_RX10- D86 PEG_TX10A32 AC/HDA _BITCLK B32 SPKR A87 RSVD/eDP_HPD B87 VCC_5V_SBY C32 DDI2_CTRLCLK_AUX+ D32 DDI1_PAIR2+ C87 GND D87 GND
A33 AC/HDA _SDOUT B33 I2C_CK A88 PCIE0_CLK_REF+ B88 BIOS_DIS1# C33 DDI2_CTRLDATA_AUX- D33 DDI1_PAIR2- C88 PEG_RX11+ D88 PEG_TX11+
A34 BIOS_DIS0# B34 I2C_DAT A89 PCIE0_CLK_REF- B89 VGA_RED C34 DDI2_DDC_AUX_SEL D34 DDI1_DDC_AUX_SEL C89 PEG_RX11- D89 PEG_TX11A35 THRMTRIP# B35 THRM# A90 GND (FIXED) B90 GND (FIXED) C35 RSVD D35 RSVD C90 GND (FIXED) D90 GND (FIXED)
A36 USB6- B36 USB7- A91 SPI_POWER B91 VGA_GRN C36 DDI3_CTRLCLK_AUX+ D36 DDI1_PAIR3+ C91 PEG_RX12+ D91 PEG_TX12+
A37 USB6+ B37 USB7+ A92 SPI_MISO B92 VGA_BLU C37 DDI3_CTRLDATA_AUX- D37 DDI1_PAIR3- C92 PEG_RX12- D92 PEG_TX12A38 USB_6_7_OC# B38 USB_4_5_OC# A93 GPO0 B93 VGA_HSYNC C38 DDI3_DDC_AUX_SEL D38 RSVD C93 GND D93 GND
A39 USB4- B39 USB5- A94 SPI_CLK B94 VGA_VSYNC C39 DDI3_PAIR0+ D39 DDI2_PAIR0+ C94 PEG_RX13+ D94 PEG_TX13+
A40 USB4+ B40 USB5+ A95 SPI_MOSI B95 VGA_I2C_CK C40 DDI3_PAIR0- D40 DDI2_PAIR0- C95 PEG_RX13- D95 PEG_TX13A41 GND (FIXED) B41 GND (FIXED) A96 TPM_PP B96 VGA_I2C_DAT C41 GND (FIXED) D41 GND (FIXED) C96 GND D96 GND
A42 USB2- B42 USB3- A97 NC B97 SPI_CS# C42 DDI3_PAIR1+ D42 DDI2_PAIR1+ C97 RSVD D97 RSVD
A43 USB2+ B43 USB3+ A98 SER0_TX B98 RSVD C43 DDI3_PAIR1- D43 DDI2_PAIR1- C98 PEG_RX14+ D98 PEG_TX14+
A44 USB_2_3_OC# B44 USB_0_1_OC# A99 SER0_RX B99 RSVD C44 DDI3_HPD D44 DDI2_HPD C99 PEG_RX14- D99 PEG_TX14A45 USB0- B45 USB1- A100 GND (FIXED) B100 GND (FIXED) C45 RSVD D45 RSVD C100 GND (FIXED) D100 GND (FIXED)
A46 USB0+ B46 USB1+ A101 SER1_TX B101 FAN_PWMOUT C46 DDI3_PAIR2+ D46 DDI2_PAIR2+ C101 PEG_RX15+ D101 PEG_TX15+
A47 VCC_RTC B47 EXCD1_PERST# A102 SER1_RX B102 FAN_TACHIN C47 DDI3_PAIR2- D47 DDI2_PAIR2- C102 PEG_RX15- D102 PEG_TX15A48 EXCD0_PERST# B48 EXCD1_CPPE# A103 LID# B103 SLEEP# C48 RSVD D48 RSVD C103 GND D103 GND
A49 EXCD0_CPPE# B49 SYS_RESET# A104 VCC_12V B104 VCC_12V C49 DDI3_PAIR3+ D49 DDI2_PAIR3+ C104 VCC_12V D104 VCC_12V
A50 LPC_SERIRQ B50 CB_RESET# A105 VCC_12V B105 VCC_12V C50 DDI3_PAIR3- D50 DDI2_PAIR3- C105 VCC_12V D105 VCC_12V
A51 GND (FIXED) B51 GND (FIXED) A106 VCC_12V B106 VCC_12V C51 GND (FIXED) D51 GND (FIXED) C106 VCC_12V D106 VCC_12V
A52 PCIE_TX5+ B52 PCIE_RX5+ A107 VCC_12V B107 VCC_12V C52 PEG_RX0+ D52 PEG_TX0+ C107 VCC_12V D107 VCC_12V
A53 PCIE_TX5- B53 PCIE_RX5- A108 VCC_12V B108 VCC_12V C53 PEG_RX0- D53 PEG_TX0- C108 VCC_12V D108 VCC_12V
A54 GPI0 B54 GPO1 A109 VCC_12V B109 VCC_12V C54 NC D54 PEG_LANE_RV# C109 VCC_12V D109 VCC_12V
A55 PCIE_TX4+ B55 PCIE_RX4+ A110 GND (FIXED) B110 GND (FIXED) C55 PEG_RX1+ D55 PEG_TX1+ C110 GND (FIXED) D110 GND (FIXED)
Row C Row DRow A Row B Row C Row DRow A Row B
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Chapter 3
COM Express Connectors Signals and Descriptions
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
AC/HDA_RST# A30 O CMOS 3.3V Suspend/3.3V series 33 ɏ
resistor Reset output to CODEC, active low. CODEC Reset.
AC/HDA_SYNC A29 O CMOS 3.3V/3.3V series 33ɏ
resistor Sample-synchronization signal to the CODEC(s). Serial Sample Rate Synchronization.
AC/HDA_BITCLK A32 I/O CMOS 3.3V/3.3V series 33ɏ resistor Serial data clock generated by the external CODEC(s). 24 MHz Serial Bit Clock for HDA CODEC.
AC/HDA_SDOUT A33 O CMOS 3.3V/3.3V series 33ɏ
resistor Serial TDM data output to the CODEC. Audio Serial Data Output Stream.
AC/HDA_SDIN0 B30 I/O CMOS 3.3V Suspend/3.3V
AC/HDA_SDIN1 B29 I/O CMOS 3.3V Suspend/3.3V
AC/HDA_SDIN2 B28 I/O CMOS 3.3V Suspend/3.3V NC
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
GBE0_MDI0+ A13 I/O Analog 3.3V max Suspend
GBE0_MDI0- A12 I/O Analog 3.3V max Suspend
GBE0_MDI1+ A10 I/O Analog 3.3V max Suspend
GBE0_MDI1- A9 I/O Analog 3.3V max Suspend
GBE0_MDI2+ A7 I/O Analog 3.3V max Suspend
GBE0_MDI2- A6 I/O Analog 3.3V max Suspend
GBE0_MDI3+ A3 I/O Analog 3.3V max Suspend
GBE0_MDI3-
A
2I
/
O Analog3.3V max Suspend
GBE0_ACT# B2 OD CMO
S
3.3V Suspend/3.3V Gigabit Ethernet Controller 0 activity indicator, active low. Ethernet controller 0 activity indicator, active low.
GBE0_LINK# A8 OD CMOS 3.3V Suspend/3.3V Gigabit Ethernet Controller 0 link indicator, active low. Ethernet controller 0 link indicator, active low.
GBE0_LINK100#
A
4OD CMOS3.3V Suspend/3.3V Gigabit Ethernet Controller 0 100 Mbit / sec link indicator, active low. Ethernet controller 0 100Mbit/sec link indicator, active low.
GBE0_LINK1000#
A
5OD CMOS3.3V Suspend/3.3V Gigabit Ethernet Controller 0 1000 Mbit / sec link indicator, active low. Ethernet controller 0 1000Mbit/sec link indicator, active low.
GBE0_CTREF A14 REF GND min 3.3V max NC
Reference voltage for Carrier Board Ethernet channel 0 magnetics center
tap. The reference voltage is determined by the requirements of the
Module PHY and may be as low as 0V and as high as 3.3V.
The reference voltage output shall be current limited on the Module. In
the case in which the reference is shorted to ground, the current shall be
limited to 250 mA or less.
Reference voltage for Carrier Board Ethernet channel 0
magnetics center tap.
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
SATA0_TX+ A16 O SATA AC coupled on Module AC Coupling capacitor
SATA0_TX- A17 O SATA AC coupled on Module AC Coupling capacitor
SATA0_RX+ A19 I SATA AC coupled on Module AC Coupling capacitor
SATA0_RX- A20 I SATA AC coupled on Module AC Coupling capacitor
SATA1_TX+ B16 O SATA AC coupled on Module AC Coupling capacitor
SATA1_TX- B17 O SATA AC coupled on Module AC Coupling capacitor
SATA1_RX+ B19 I SATA AC coupled on Module AC Coupling capacitor
SATA1_RX- B20 I SATA AC coupled on Module AC Coupling capacitor
SATA2_TX+ A22 O SATA AC coupled on Module AC Coupling capacitor
SATA2_TX- A23 O SATA AC coupled on Module AC Coupling capacitor
SATA2_RX+ A25 I SATA AC coupled on Module AC Coupling capacitor
SATA2_RX- A26 I SATA AC coupled on Module AC Coupling capacitor
SATA3_TX+ B22 O SATA AC coupled on Module AC Coupling capacitor
SATA3_TX- B23 O SATA AC coupled on Module AC Coupling capacitor
SATA3_RX+ B25 I SATA AC coupled on Module AC Coupling capacitor
SATA3_RX- B26 I SATA AC coupled on Module AC Coupling capacitor
(S)ATA_ACT# A28 I/O CMOS 3.3V / 3.3V PU 10K: to 3.3V ATA (parallel and serial) or SAS activity indicator, active low.
Serial ATA activit
y
LED. Open collector output pin driven durin
g
SATA command activity.
Pin Types
I Input to the Module
O Output from the Module
I/O Bi-directional input / output signal
OD Open drain output
RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD pins together.
Serial ATA channel 2
Transmit output differential pair.
Serial ATA channel 0
Transmit output differential pair.
Serial ATA channel 0
Receive input differential pair.
Serial ATA channel 1
Transmit output differential pair.
Serial ATA channel 3
Receive input differential pair.
Serial ATA channel 2
Receive input differential pair.
Serial ATA channel 3
Transmit output differential pair.
A
C97/HDA Signals Description
s
Serial TDM data inputs from up to 3 CODECs.
Gigabit Ethernet Signals Description
s
Serial ATA or SAS Channel 0 transmit differential pair.
Serial ATA or SAS Channel 0 receive differential pair.
Serial ATA or SAS Channel 3 transmit differential pair.
Serial ATA or SAS Channel 3 receive differential pair.
Serial ATA or SAS Channel 2 receive differential pair.
Serial ATA or SAS Channel 2 transmit differential pair.
Gigabit Ethernet Controller 0: Media Dependent Interface Differential
Pairs 0,1,2,3. The MDI can operate in 1000, 100 and 10 Mbit / sec
modes. Some pairs are unused in some modes, per the following:
1000BASE-T 100BASE-TX 10BASE-T
MDI[0]+/- B1_DA+/- TX+/- TX+/ MDI[1]+/- B1_DB+/- RX+/- RX+/ MDI[2]+/- B1_DC+/ MDI[3]+/- B1_DD+/-
Serial ATA or SAS Channel 1 receive differential pair.
SATA Signals Description
s
Serial ATA or SAS Channel 1 transmit differential pair.
Audio Serial Data Input Stream from CODEC[0:2].
Media Dependent Interface (MDI) differential pair 0.
Media Dependent Interface (MDI) differential pair 1.
Media Dependent Interface (MDI) differential pair 2.
Only used for 1000Mbit/sec Gigabit Ethernet mode.
Media Dependent Interface (MDI) differential pair 3.
Only used for 1000Mbit/sec Gigabit Ethernet mode.
Serial ATA channel 1
Receive input differential pair.
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Chapter 3
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
PCIE_TX0+ A68 AC Coupling capacitor
PCIE_TX0- A69 AC Coupling capacitor
PCIE_RX0+ B68
PCIE_RX0- B69
PCIE_TX1+ A64 AC Coupling capacitor
PCIE_TX1- A65 AC Coupling capacitor
PCIE_RX1+ B64
PCIE_RX1- B65
PCIE_TX2+ A61 AC Coupling capacitor
PCIE_TX2- A62 AC Coupling capacitor
PCIE_RX2+ B61
PCIE_RX2- B62
PCIE_TX3+ A58 AC Coupling capacitor
PCIE_TX3- A59 AC Coupling capacitor
PCIE_RX3+ B58
PCIE_RX3- B59
PCIE_TX4+ A55 AC Coupling capacitor
PCIE_TX4- A56 AC Coupling capacitor
PCIE_RX4+ B55
PCIE_RX4- B56
PCIE_TX5+ A52 AC Coupling capacitor
PCIE_TX5- A53 AC Coupling capacitor
PCIE_RX5+ B52
PCIE_RX5- B53
PCIE_TX6+ D19 AC Coupling capacitor
PCIE_TX6- D20 AC Coupling capacitor
PCIE_RX6+ C19
PCIE_RX6- C20
PCIE_TX7+ D22 AC Coupling capacitor
PCIE_TX7- D23 AC Coupling capacitor
PCIE_RX7+ C22
PCIE_RX7- C23
PCIE_CLK_REF+ A88
PCIE_CLK_REF- A89
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
PEG_TX0+ D52 AC Coupling capacitor
PEG_TX0- D53 AC Coupling capacitor
PEG_RX0+ C52
PEG_RX0- C53
PEG_TX1+ D55 AC Coupling capacitor
PEG_TX1- D56 AC Coupling capacitor
PEG_RX1+ C55
PEG_RX1- C56
PEG_TX2+ D58 AC Coupling capacitor
PEG_TX2- D59 AC Coupling capacitor
PEG_RX2+ C58
PEG_RX2- C59
PEG_TX3+ D61 AC Coupling capacitor
PEG_TX3- D62 AC Coupling capacitor
PEG_RX3+ C61
PEG_RX3- C62
PEG_TX4+ D65 AC Coupling capacitor
PEG_TX4- D66 AC Coupling capacitor
PEG_RX4+ C65
PEG_RX4- C66
PEG_TX5+ D68 AC Coupling capacitor
PEG_TX5- D69 AC Coupling capacitor
PEG_RX5+ C68
PEG_RX5- C69
PCIe channel 4. Receive Input differential pair.
PCIe channel 5. Transmit Output differential pair.
PCIe channel 6. Transmit Output differential pair.
PCIe channel 6. Receive Input differential pair.
PCIe channel 7. Transmit Output differential pair.
PCIe channel 7. Receive Input differential pair.
PCIe Reference Clock for all COM Express PCIe lanes, and for
PEG lanes.
PEG channel 5, Receive Input differential pair.I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 5
PEG channel 5, Transmit Output differential pair.O PCIE AC coupled on Module
PCI Express Graphics transmit differential pairs 4
I PCIE AC coupled off Module
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 3
PCI Express Graphics transmit differential pairs 5
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 2
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 3
PCI Express Graphics receive differential pairs 4
O PCIE AC coupled on Module
PEG channel 2, Receive Input differential pair.
PEG channel 3, Transmit Output differential pair.
PEG channel 3, Receive Input differential pair.
PEG channel 4, Transmit Output differential pair.
PEG channel 4, Receive Input differential pair.
PCI Express Graphics transmit differential pairs 2
PEG Signals Description
s
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 0
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 0
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 1
AC coupled off Module PCI Express Graphics receive differential pairs 1
PEG channel 0, Transmit Output differential pair.
PEG channel 0, Receive Input differential pair.
PEG channel 1, Transmit Output differential pair.
PEG channel 1, Receive Input differential pair.
PEG channel 2, Transmit Output differential pair.O PCIE AC coupled on Module
I PCIE
PCI Express Differential Receive Pairs 7
O PCIE PCIE Reference clock output for all PCI Express and PCI Express Graphics lanes.
PCI Express Differential Receive Pairs 6
O PCIE AC coupled on Module PCI Express Differential Transmit Pairs 7
PCI Express Differential Transmit Pairs 4
PCIe channel 5. Receive Input differential pair.
PCIe channel 4. Transmit Output differential pair.
I PCIE AC coupled off Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module PCI Express Differential Transmit Pairs 6
I PCIE AC coupled off Module PCI Express Differential Receive Pairs 5
O PCIE AC coupled on Module PCI Express Differential Transmit Pairs 5
PCI Express Differential Receive Pairs 4
O PCIE AC coupled on Module
I PCIE AC coupled off Module
PCIe channel 3. Receive Input differential pair.
O PCIE AC coupled on Module PCI Express Differential Transmit Pairs 1
PCI Express Differential Receive Pairs 1
PCI Express Differential Receive Pairs 3
I PCIE AC coupled off Module PCI Express Differential Receive Pairs 2
PCI Express Differential Transmit Pairs 3O PCIE AC coupled on Module PCIe channel 3. Transmit Output differential pair.
PCIe channel 2. Transmit Output differential pair.
PCIe channel 2. Receive Input differential pair.
PCIe channel 1. Transmit Output differential pair.
PCIe channel 1. Receive Input differential pair.
I PCIE AC coupled off Module
O PCIE AC coupled on Module PCI Express Differential Transmit Pairs 0
O PCIE AC coupled on Module PCI Express Differential Transmit Pairs 2
I PCIE AC coupled off Module
I PCIE AC coupled off Module PCI Express Differential Receive Pairs 0
PCIe channel 0. Transmit Output differential pair.
PCIe channel 0. Receive Input differential pair.
PCI Express Lanes Signals Description
s
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Chapter 3
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
PEG Signals Description
s
PEG_TX6+ D71 AC Coupling capacitor
PEG_TX6- D72 AC Coupling capacitor
PEG_RX6+ C71
PEG_RX6- C72
PEG_TX7+ D74 AC Coupling capacitor
PEG_TX7- D75 AC Coupling capacitor
PEG_RX7+ C74
PEG_RX7- C75
PEG_TX8+ D78 AC Coupling capacitor
PEG_TX8- D79 AC Coupling capacitor
PEG_RX8+ C78
PEG_RX8- C79
PEG_TX9+ D81 AC Coupling capacitor
PEG_TX9- D82 AC Coupling capacitor
PEG_RX9+ C81
PEG_RX9- C82
PEG_TX10+ D85 AC Coupling capacitor
PEG_TX10- D86 AC Coupling capacitor
PEG_RX10+ C85
PEG_RX10- C86
PEG_TX11+ D88 AC Coupling capacitor
PEG_TX11- D89 AC Coupling capacitor
PEG_RX11+ C88
PEG_RX11- C89
PEG_TX12+ D91 AC Coupling capacitor
PEG_TX12- D92 AC Coupling capacitor
PEG_RX12+ C91
PEG_RX12- C92
PEG_TX13+ D94 AC Coupling capacitor
PEG_TX13- D95 AC Coupling capacitor
PEG_RX13+ C94
PEG_RX13- C95
PEG_TX14+ D98 AC Coupling capacitor
PEG_TX14- D99 AC Coupling capacitor
PEG_RX14+ C98
PEG_RX14- C99
PEG_TX15+ D101 AC Coupling capacitor
PEG_TX15- D102 AC Coupling capacitor
PEG_RX15+ C101
PEG_RX15- C102
PEG_LANE_RV# D54 I CMOS 3.3V / 3.3V PU 10Kɏ
to 3V3
PCI Express Graphics lane reversal input strap.
Pull low on the Carrier board to reverse lane order.
PCI Express Graphics lane reversal input strap.
Pull low on the carrier board to reverse lane order.
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
EXCD0_CPPE# A49 I CMOS 3.3V /3.3V PU 10k to 3.3V
PCI Ex
p
ressCard: PCI Express capable card request, active low, one per
card
PCI ExpressCard0: PCI Express capable card request, active low,
one
p
er card
EXCD0_PERST#
A
48 O CMOS3.3V /3.3V PCI ExpressCard: reset, active low, one per card PCI ExpressCard0: reset, active low, one per card
EXCD1_CPPE# B48 I CMOS 3.3V /3.3V PU 10k to 3.3V PCI ExpressCard: PCI Express capable card request, active low, one percard
PCI Ex
p
ressCard1: PCI Express capable card request, active low,
one
p
er card
EXCD1_PERST# B47 O CMO
S
3.3V /3.3V PCI ExpressCard: reset, active low, one per card PCI ExpressCard1: reset, active low, one per card
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
USB0+ A46 USB Port 0, data + or D+
USB0- A45 USB Port 0, data - or D-
USB1+ B46 USB Port 1, data + or D+
USB1- B45 USB Port 1, data - or D-
I PCIE
PEG channel 15, Transmit Output differential pair.
PCI Express Graphics transmit differential pairs 12
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 11
PEG channel 15, Receive Input differential pair.
I PCIE AC coupled off Module
O PCIE AC coupled on Module
I/O USB
PEG channel 12, Transmit Output differential pair.
3.3V Suspend/3.3V USB differential pairs, channel 1
I PCIE AC coupled off Module
PCI Express Graphics receive differential pairs 14
PCI Express Graphics receive differential pairs 12
ExpressCard Signals Description
s
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 14
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 15
PEG channel 12, Receive Input differential pair.
PEG channel 13 Transmit Output differential pair.
PEG channel 13, Receive Input differential pair.
USB Signals Description
s
I/O USB 3.3V Suspend/3.3V USB differential pairs, channel 0
PEG channel 14, Transmit Output differential pair.
PEG channel 14, Receive Input differential pair.
PEG channel 9, Transmit Output differential pair.
PEG channel 9, Receive Input differential pair.
PEG channel 10, Transmit Output differential pair.O PCIE AC coupled on Module
PCI Express Graphics receive differential pairs 13
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 15
I PCIE AC coupled off Module
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 13
AC coupled off Module
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 11
PCI Express Graphics receive differential pairs 10 PEG channel 10, Receive Input differential pair.
PEG channel 11, Transmit Output differential pair.
PEG channel 11, Receive Input differential pair.
O PCIE
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 6
PCI Express Graphics transmit differential pairs 10
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 9
O PCIE AC coupled on Module PCI Express Graphics transmit differential pairs 9
PEG channel 6, Transmit Output differential pair.
PEG channel 6, Receive Input differential pair.
PEG channel 7, Transmit Output differential pair.
PEG channel 7, Receive Input differential pair.
PEG channel 8, Transmit Output differential pair.O PCIE AC coupled on Module
PCI Express Graphics receive differential pairs 8
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 7
AC coupled on Module PCI Express Graphics transmit differential pairs 7
I PCIE AC coupled off Module PCI Express Graphics receive differential pairs 6
PEG channel 8, Receive Input differential pair.I PCIE AC coupled off Module
PCI Express Graphics transmit differential pairs 8
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USB2+ A43 USB Port 2, data + or D+
USB2- A42 USB Port 2, data - or D-
USB3+ B43 USB Port 3, data + or D+
USB3- B42 USB Port 3, data - or D-
USB4+ A40 USB Port 4, data + or D+
USB4- A39 USB Port 4, data - or D-
USB5+ B40 USB Port 5, data + or D+
USB5- B39 USB Port 5, data - or D-
USB6+ A37 USB Port 6, data + or D+
USB6- A36 USB Port 6, data - or D-
USB7+ B37 USB Port 7, data + or D+
USB7- B36 USB Port 7, data - or D-
USB_0_1_OC# B44 I CMOS 3.3V Suspend/3.3V
PU 10K: to 3.3V
Suspend
USB over-current sense, USB channels 0 and 1. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
USB over-current sense, USB ports 0 and 1.
USB_2_3_OC# A44 I CMOS 3.3V Suspend/3.3V
PU 10K: to 3.3V
Suspend
USB over-current sense, USB channels 2 and 3. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
USB over-current sense, USB ports 2 and 3.
USB_4_5_OC# B38 I CMOS 3.3V Suspend/3.3V
PU 10K: to 3.3V
Suspend
USB over-current sense, USB channels 4 and 5. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
USB over-current sense, USB ports 4 and 5.
USB_6_7_OC# A38 I CMOS 3.3V Suspend/3.3V
PU 10K: to 3.3V
Suspend
USB over-current sense, USB channels 6 and 7. A pull-up for this line
shall be present on the Module. An open drain driver from a USB
current monitor on the Carrier Board may drive this line low. Do not
pull this line high on the Carrier Board.
USB over-current sense, USB ports 6 and 7.
USB_SSTX0+ D4 AC Coupling capacitor USB Port 0, SuperSpeed TX +
USB_SSTX0- D3 AC Coupling capacitor USB Port 0, SuperSpeed TX -
USB_SSRX0+ C4 USB Port 0, SuperSpeed RX +
USB_SSRX0- C3 USB Port 0, SuperSpeed RX -
USB_SSTX1+ D7 AC Coupling capacitor USB Port 1, SuperSpeed TX +
USB_SSTX1- D6 AC Coupling capacitor USB Port 1, SuperSpeed TX -
USB_SSRX1+ C7 USB Port 1, SuperSpeed RX +
USB_SSRX1- C6 USB Port 1, SuperSpeed RX -
USB_SSTX2+ D10 AC Coupling capacitor USB Port 2, SuperSpeed TX +
USB_SSTX2- D9 AC Coupling capacitor USB Port 2, SuperSpeed TX -
O PCIE AC coupled on Module
Additional receive signal differential pairs for the SuperSpeed USB data
path.
I/O USB 3.3V Suspend/3.3V USB differential pairs, channel 2
Additional transmit signal differential pairs for the SuperSpeed USB data
path.
O PCIE AC coupled on Module
Additional transmit signal differential pairs for the SuperSpeed USB data
path.
I PCIE AC coupled off Module
O PCIE AC coupled on Module
Additional transmit signal differential pairs for the SuperSpeed USB data
path.
I/O USB 3.3V Suspend/3.3V USB differential pairs, channel 6
Additional receive signal differential pairs for the SuperSpeed USB data
path.
I PCIE AC coupled off Module
I/O USB 3.3V Suspend/3.3V USB differential pairs, channel 5
I/O USB 3.3V Suspend/3.3V
USB differential pairs, channel 7.
USB7 may be configured as a USB client or as a host, or both, at the
Module designer's discretion. (CH960 default set as a host)
3.3V Suspend/3.3V USB differential pairs, channel 4
I/O USB 3.3V Suspend/3.3V USB differential pairs, channel 3
I/O USB
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
USB Signals Description
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Chapter 3
USB_SSRX2+ C10 USB Port 2, SuperSpeed RX +
USB_SSRX2- C9 USB Port 2, SuperSpeed RX -
USB_SSTX3+ D13 AC Coupling capacitor USB Port 3, SuperSpeed TX +
USB_SSTX3- D12 AC Coupling capacitor USB Port 3, SuperSpeed TX -
USB_SSRX3+ C13 USB Port 3, SuperSpeed RX +
USB_SSRX3- C12 USB Port 3, SuperSpeed RX -
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
LVDS_A0+/eDP_TX2+ A71
LVDS_A0-/eDP_TX2- A72
LVDS_A1+/eDP_TX1+ A73
LVDS_A1-/eDP_TX1- A74
LVDS_A2+/eDP_TX0+ A75
LVDS_A2-/eDP_TX0- A76
LVDS_A3+ A78
LVDS_A3- A79
LVDS_A_CK+/eDP_TX3+ A81
LVDS_A_CK-/eDP_TX3- A82
LVDS_B0+ B71
LVDS_B0- B72
LVDS_B1+ B73
LVDS_B1- B74
LVDS_B2+ B75
LVDS_B2- B76
LVDS_B3+ B77
LVDS_B3- B78
LVDS_B_CK+ B81
LVDS_B_CK- B82
LVDS_VDD_EN/eDP_VDD_EN A77 O CMOS 3.3V / 3.3V LVDS/eDP: PD 100K : LVDS panel power enable
LVDS flat panel power enable.
eDP power enable
LVDS_BKLT_EN/eDP_BKLT_EN B79 O CMOS 3.3V / 3.3V LVDS/eDP: PD 100K: LVDS panel backlight enable
LVDS flat panel backlight enable high active signal
eDP backlight enable
LVDS_BKLT_CTRL/eDP_BKLT_CTRL B83 O CMOS 3.3V / 3.3V LVDS/eDP: PD 100K : LVDS panel backlight brightness control
LVDS flat panel backlight brightness control
EDP backlight brightness control
LVDS_I2C_CK/eDP_AUX+ A83 I/O OD CMOS 3.3V / 3.3V PU 4.7K: to 3.3V I2C clock output for LVDS display use
DDC I2C clock signal used for flat panel detection and control.
eDP auxiliary lane +
LVDS_I2C_DAT/eDP_AUX- A84 I/O OD CMOS 3.3V / 3.3V PU 4.7K: to 3.3V I2C data line for LVDS display use
DDC I2C data signal used for flat panel detection and control.
eDP auxiliary lane -
RSVD/eDP_HPD A87 I CMOS 3.3V / 3.3V
LVDS: RSV series resistor
to PCH EDP HPD
eDP: Connect to PCH
EDP HPD w
/
PD 100K:
eDP_HPD:Detection of Hot Plug / Unplug and notification of the link layer
eDP_HPD: Detection of Hot Plug / Unplug and notification of the
link layer
O LVDS LVDS
O PCIE
I PCIE AC coupled off Module
LVDS
O LVDS LVDS
Additional receive signal differential pairs for the SuperSpeed USB data
path.
LVDS Signals Description
s
O LVDS
LVDS
EDP: AC coupled off
Module
LVDS channel A differential signal pair 0
eDP lane 2, TXƲ
differential signal pair
LVDS Channel A differential pairs
Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-.
LVDS_A_CK+/-, LVDS_B_CK+/-) shall have 100ƻ terminations across the
pairs at the destination. These terminations may be on the Carrier Board if
the Carrier Board implements a LVDS deserializer on-board.
eDP: eDP differential pairs
O LVDS
LVDS channel A differential signal pair 1
eDP lane 1, TXƲ
differential signal pair
O LVDS
LVDS
EDP: AC coupled off
Module
LVDS channel A differential signal pair 3
LVDS
EDP: AC coupled off
Module
LVDS channel A differential signal pair 2
eDP lane 0, TX Ʋ
differential signal pair
O LVDS
LVDS
EDP: AC coupled off
Module
LVDS channel B differential signal pair 2
LVDS Channel A differential clockO LVDS LVDS
LVDS channel A differential clock pair
eDP lane 3, TXƲ
differential pair
O LVDS
LVDS channel B differential signal pair 0
LVDS channel B differential signal pair 1
LVDS Channel B differential clock
LVDS Channel B differential pairs
Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-.
LVDS_A_CK+/-, LVDS_B_CK+/-) shall have 100ƻ terminations across the
pairs at the destination. These terminations may be on the Carrier Board if
the Carrier Board implements a LVDS deserializer on-board.
O LVDS LVDS LVDS channel B differential signal pair 3
O LVDS LVDS LVDS channel B differential clock pair
AC coupled on Module
Additional transmit signal differential pairs for the SuperSpeed USB data
path.
I PCIE AC coupled off Module
Additional receive signal differential pairs for the SuperSpeed USB data
path.
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
USB Signals Description
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Chapter 3
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
LPC_AD0 B4
LPC_AD1 B5
LPC_AD2 B6
LPC_AD3 B7
LPC_FRAME# B3 O CMOS 3.3V / 3.3V LPC frame indicates the start of an LPC cycle
LPC frame indicates start of a new cycle or termination of a
broken cycle.
LPC_DRQ0# B8
PU 10K to 3.3V, not
support.
LPC_DRQ1# B9
PU 10K to 3.3V, not
support.
LPC_SERIRQ A50 I/O CMOS 3.3V / 3.3V PU 10K to 3.3V LPC serial interrupt LPC serialized IRQ.
LPC_CLK B10 O CMOS 3.3V / 3.3V series 22ƻ resistor LPC clock output - 33MHz nominal LPC clock output 33MHz.
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
SPI_CS# B97 O CMOS 3.3V Suspend/3.3V
Chip select for Carrier Board SPI - may be sourced from chipset SPI0 or
SPI1
Chip select for Carrier Board SPI – may be sourced from chipset
SPI0 or SPI1
SPI_MISO A92 I CMOS 3.3V Suspend/3.3V Data in to Module from Carrier SPI
Data in to Module from Carrier SPI
SPI_MOSI A95 O CMOS 3.3V Suspend/3.3V Data out from Module to Carrier SPI
Data out from Module to Carrier SPI
SPI_CLK A94 O CMOS 3.3V Suspend/3.3V Clock from Module to Carrier SPI
Clock from Module to Carrier SPI
SPI_POWER A91 O 3.3V Suspend/3.3V
Power supply for Carrier Board SPI – sourced from Module – nominally
3.3V. The Module shall provide a minimum of 100mA on SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER. SPI_POWER
shall only be used to power SPI devices on the Carrier Board.
Power supply for Carrier Board SPI – sourced from Module –
nominally 3.3V. The Module shall provide a minimum of 100mA
on SPI_POWER. Carriers shall use less than 100mA of
SPI_POWER. SPI_POWER shall only be used to power SPI
devices on the Carrier.
BIOS_DIS0# A34 PU 10Kɏ
to 3V3 Suspend.
Selection strap to determine the BIOS boot device.
The Carrier should only float these or pull them low, please refer
to for strapping options of BIOS disable signals.
BIOS_DIS1# B88 PU 10Kɏ
to 3V3 Suspend.
Selection strap to determine the BIOS boot device.
The Carrier should only float these or pull them low.
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
VGA_RED B89 O Analog Analog PD 150: to GND
Red for monitor. Analo
g
DAC output, designed to drive a 37.5ƻ equivalent
load.
Red component of analog DAC monitor output, designed to drive
a 37.5ƻ e
q
uivalent load.
VGA_GRN B91 O Analog Analog PD 150: to GND
Green for monitor. Analo
g
DAC output, designed to drive a 37.5ƻ
e
q
uivalent load.
Green com
p
onent of analog DAC monitor output, designed to
drive a 37.5ƻ e
q
uivalent load.
VGA_BLU B92 O Analog Analog PD 150: to GND
Blue for monitor. Analo
g
DAC output, designed to drive a 37.5ƻ equivalent
load.
Blue component of analog DAC monitor output, designed to
drive a 37.5ƻ e
q
uivalent load.
VGA_HSYNC B93 O CMOS 3.3V / 3.3V Horizontal sync output to VGA monitor Horizontal sync output to VGA monitor.
VGA_VSYNC B94 O CMOS 3.3V / 3.3V Vertical sync output to VGA monitor Vertical sync output to VGA monitor.
VGA_I2C_CK B95 I/O OD CMOS 3.3V / 3.3V PU 2.2K: to 3.3V DDC clock line (I2C port dedicated to identify VGA monitor capabilities)
DDC clock line (I2C port dedicated to identify VGA monitor
capabilities).
VGA_I2C_DAT B96 I/O OD CMOS 3.3V / 3.3V PU 2.2K: to 3.3V DDC data line. DDC data line.
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
DDI1_PAIR0+ D26 DP1_LANE0+ for DP / TMDS1_DATA2+ for HDMI or DVI
DDI1_PAIR0- D27 DP1_LANE0- for DP / TMDS1_DATA2- for HDMI or DVI
DDI1_PAIR1+ D29 DP1_LANE1+ for DP / TMDS1_DATA1+ for HDMI or DVI
DDI1_PAIR1- D30 DP1_LANE1- for DP / TMDS1_DATA1- for HDMI or DVI
DDI for Display Port: DP1_LANE 0 differential pairs
DDI for SDVO: SDVO1_RED± differential pair (Serial Digital Video red
output)
DDI for HDMI/DVI: TMDS1_DATA lanes 2 differential pairs
O PCIE AC coupled off Module
LPC multiplexed command, address and data.
LPC encoded DMA/Bus master request.
SPI Signals Description
s
3.3V / 3.3V LPC serial DMA request
I/O CMOS 3.3V / 3.3V
V
GA Signals Description
s
NA
Selection straps to determine the BIOS boot device.
The Carrier should only float these or pull them low, please refer to
COM Express Module Base Specification Revision 2.1 for strapping options
of BIOS disable signals.
LPC Signals Description
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I CMOS
I CMOS
LPC multiplexed address, command and data bus.
O PCIE AC coupled off Module
DDI Signals Description
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DDI for Display Port: DP1_LANE 1 differential pairs
DDI for SDVO: SDVO1_GRN± differential pair (Serial Digital Video green
output)
DDI for HDMI/DVI: TMDS1_DATA lanes 1 differential pairs
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Chapter 3
DDI1_PAIR2+ D32 DP1_LANE2+ for DP / TMDS1_DATA0+ for HDMI or DVI
DDI1_PAIR2- D33 DP1_LANE2- for DP / TMDS1_DATA0- for HDMI or DVI
DDI1_PAIR3+ D36 DP1_LANE3+ for DP / TMDS1_CLK+
DDI1_PAIR3- D37 DP1_LANE3- for DP / TMDS1_CLK-
DDI1_PAIR4+ C25 NA,no spport NA
DDI1_PAIR4- C26 NA,no spport NA
DDI1_PAIR5+ C29 NA,no spport NA
DDI1_PAIR5- C30 NA,no spport NA
DDI1_PAIR6+ C15 NA,no spport NA
DDI1_PAIR6- C16 NA,no spport NA
I/O PCIE AC coupled on Module
PD 100K to GND
(S/W IC between
Rpu/PCH)
DDI for Display Port: DP1_AUX+ Differetial pairs
(DP AUX+ function if DDI1_DDC_AUX_SEL is no connect)
Half-duplex bi-directional AUX channel for services such as link
configuration or maintenance and EDID access
DP1_AUX+ for DP
I/O OD CMOS 3.3V / 3.3V
PU 2.2K to 3.3V, PD 100K
to GND
(S/W IC between
Rpu/Rpd resistor)
DDI for SDVO: SDVO1_CTRLCLK (SDVO I2C clock line - to set up SDVO
peripherals.)
DDI for HDMI/DVI: HDMI1_CTRLCLK
(HDMI/DVI I2C CTRLCLK if DDI1_DDC_AUX_SEL is pulled high)
HDMI1_CTRLCLK for HDMI or DVI
I/O PCIE AC coupled on Module
PU 100K to 3.3V
(S/W IC between
Rpu/PCH)
DDI for Display Port: DP1_AUX- Differetial pairs
(DP AUX- function if DDI1_DDC_AUX_SEL is no connect)
Half-duplex bi-directional AUX channel for services such as link
configuration or maintenance and EDID access
DP1_AUX- for DP
I/O OD CMOS 3.3V / 3.3V
PU 2.2K to 3.3V/PU 100K
to 3.3V
(S/W IC between
2.2K/100K resistor)
DDI for SDVO: SDVO1_CTRLDATA (SDVO I2C data line - to set up SDVO
peripherals.)
DDI for HDMI/DVI: HDMI1_CTRLDATA
(HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high)
HDMI1_CTRLDATA for HDMI or DVI
DDI1_HPD C24 I CMOS 3.3V / 3.3V PD 1M to GND
DDI for Display Port: DP1_HPD (DP Hot-Plug Detect)
DDI for HDMI/DVI: HDMI1_HPD (HDMI Hot-Plug Detect)
DP1_HPD for DP / HDMI1_HPD for HDMI or DVI
DDI1_DDC_AUX_SEL D34 I CMOS 3.3V / 3.3V PD 1M to GND
Selects the function of DDI1_CTRLCLK_AUX+ and
DDI1_CTRLDATA_AUX-. This pin shall have a 1M pull-down to
logic ground on the Module. If this input is floating the AUX pair is
used for the DP AUX+/- signals. If pulled-high the AUX pair contains the
CRTLCLK and CTRLDATA signals.
Selects the function of DP1 AUXƲ(Low) or HDMI1 DDC
CLK/DATA(High)
The DDC_AUX_SEL pin should be routed to pin 13 of the
DisplayPort connector, to enable Dual-Mode.
When HDMI/DVI is directly done on the Carrier Board, this pin
shall be pulled to 3.3V with a 100k Ohm resistor to configure the
AUX pairs as DDC channels.
DDI2_PAIR0+ D39 DP2_LANE0+ for DP / TMDS2_DATA2+ for HDMI or DVI
DDI2_PAIR0- D40 DP2_LANE0- for DP / TMDS2_DATA2- for HDMI or DVI
DDI2_PAIR1+ D42 DP2_LANE1+ for DP / TMDS2_DATA1+ for HDMI or DVI
DDI2_PAIR1- D43 DP2_LANE1- for DP / TMDS2_DATA1- for HDMI or DVI
DDI2_PAIR2+ D46 DP2_LANE2+ for DP / TMDS2_DATA0+ for HDMI or DVI
DDI2_PAIR2- D47 DP2_LANE2- for DP / TMDS2_DATA0- for HDMI or DVI
DDI2_PAIR3+ D49 DP2_LANE3+ for DP / TMDS2_CLK+
DDI2_PAIR3- D50 DP2_LANE3- for DP / TMDS2_CLK-
I/O PCIE AC coupled on Module
PD 100K to GND
(S/W IC between
Rpu/PCH)
DDI for Display Port: DP2_AUX+ Differetial pairs
(DP AUX+ function if DDI2_DDC_AUX_SEL is no connect)
Half-duplex bi-directional AUX channel for services such as link
configuration or maintenance and EDID access
DP2_AUX+ for DP
I/O OD CMOS 3.3V / 3.3V
PU 2.2K to 3.3V, PD 100K
to GND
(S/W IC between
Rpu/Rpd resistor)
DDI for HDMI/DVI: HDMI2_CTRLCLK
(HDMI/DVI I2C CTRLCLK if DDI2_DDC_AUX_SEL is pulled high)
HDMI2_CTRLCLK for HDMI or DVI
I PCIE
O PCIE AC coupled off Module
DDI for Display Port: DP2_LANE 2 differential pairs
DDI for HDMI/DVI: TMDS2_DATA lanes 0 differential pairs
O PCIE AC coupled off Module
AC coupled off Module
DDI for SDVO: SDVO1_FLDSTALL± differential pair
(Serial Digital Video Field Stall input differential pair.)
O PCIE
O PCIE AC coupled off Module
I PCIE
I PCIE AC coupled off Module
DDI for SDVO: SDVO1_TVCLKIN± differential pair
(Serial Digital Video TVOUT synchronization clock input differential pair.)
AC coupled off Module
DDI for Display Port: DP2_LANE 1 differential pairs
DDI for HDMI/DVI: TMDS2_DATA lanes 1 differential pairs
DDI for Display Port: DP2_LANE 3 differential pairs
DDI for HDMI/DVI: TMDS2_CLK differential pairs
DDI1_CTRLCLK_AUX+ D15
DDI1_CTRLDATA_AUX- D16
DDI2_CTRLCLK_AUX+ C32
DDI for Display Port: DP2_LANE 0 differential pairs
DDI for HDMI/DVI: TMDS2_DATA lanes 2 differential pairs
AC coupled off Module
DDI for SDVO: SDVO1_INT± differential pair
(Serial Digital Video B interrupt input differential pair)
O PCIE AC coupled off Module
O PCIE AC coupled off Module
DDI for Display Port: DP1_LANE 2 differential pairs
DDI for SDVO: SDVO1_BLU± differential pair (Serial Digital Video blue
output)
DDI for HDMI/DVI: TMDS1_DATA lanes 0 differential pairs
DDI for Display Port: DP1_LANE 3 differential pairs
DDI for SDVO: SDVO1_CK± differential pair (Serial Digital Video clock
output)
DDI for HDMI/DVI: TMDS1_CLK differential pairs
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
DDI Signals Description
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