DENSITRON DD-25664BE-1A Product Specification

OLED DISPLAY MODULE
Product Specification
CUSTOMER
PRODUCT
CUSTOMER
APPROVAL
Standard
DD-25664BE-1A
INTERNAL APPROVALS
Product Mgr Doc. Control Electr. Eng
Bruno
Recaldini
Date: 11 August 2006
Anthony
Perkins
Bazile
Peter
Date
Appr ov al f or Spe ci f icati on onl y
Appr ov al for Speci fi ca t i on a nd Sam pl e
Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data
FORM No. DT-029
TABLE OF CONTENTS
1 MAIN FEATURES .....................................................................................................4
2 MECHANICAL SPECIFICATION..........................................................................5
2.1 MECHANICAL CHARACTERISTICS ............................................................... 5
2.2 MECHANICAL DRAWING ................................................................................ 6
3 ELECTRICAL SPECIFICATION............................................................................ 7
3.1 ABSOLUTE MAXIMUM RATINGS .................................................................. 7
3.2 ELECTRICAL
3.3 INTERFACE
3.4 BLOCK DIAGRAM ........................................................................................... 13
3.5 TIMING CHARACTERISTICS ......................................................................... 14
4 OPTICAL SPECIFICATION..................................................................................16
CHARACTERISTICS ................................................................. 7
PIN ASSIGNMENT ....................................................................... 9
4.1 OPTICAL CHARACTERISTICS....................................................................... 16
5 FUNCTIONAL SPECIFICATION.........................................................................17
5.1 COMMANDS ..................................................................................................... 17
5.2 POWER DOWN AND UP SEQUENCE............................................................. 17
5.3 RESET CIRCUIT................................................................................................ 17
6 PACKAGING AND LABELLING SPECIFICATION.........................................18
6.1 PACKAGING ..................................................................................................... 18
6.2 LABELLING & MARKING............................................................................... 18
7 QUALITY ASSURANCE SPECIFICATION........................................................19
7.1 CONFORMITY .................................................................................................. 19
7.2 DELIVERY
7.3 DEALING
ASSURANCE ................................................................................ 19
WITH CUSTOMER COMPLAINTS ............................................... 24
8 RELIABILITY SPECIFICATION .........................................................................25
8.1 RELIABILITY TESTS ....................................................................................... 25
8.2 LIFE
TIME.......................................................................................................... 25
9 HANDLING PRECAUTIONS.................................................................................26
Product No.
Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data
DD-25664BE-1A REV. C
Page 2 / 26
REVISION RECORD
Rev. Date Page Chapt. Comment ECR no.
A 03-Feb-06 -- -- Initial DCA Release E3004
B 22-Mar-06 5
C 11-Aug-06
8
19
3.2
7.2.1
Remove pin out details from Drawing
Addition of current consumption Removed AQL refernces
Product No.
Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data
DD-25664BE-1A REV. C
Page 3 / 26
1 MAIN FEATURES
ITEM CONTENTS
Display Format 256 x 64 Dots
Colour Blue Monochrome
Overall Dimensions
88.00 (W) × 27.80 (H) × 2.20 (D) mm
Viewing Area 78.78 (W) x 21.18 (H) mm
Screen Size 3.12”
Mode Passive Matrix, with 16 grey scales
Duty ratio 1/64
Driver IC STV8105
Operating temperature -20°C ~ +70°C
Storage temperature -30°C ~ +80°C
Product No.
Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data
DD-25664BE-1A REV. C
Page 4 / 26
2 MECHANICAL SPECIFICATION
2.1 MECHANICAL CHARACTERISTICS
ITEM CHARACTERISTIC UNIT
Display Format 256 x 64 Dots
Overall Dimensions
88.00 (W) × 27.80 (H) × 2.20 (D)
mm
Viewing Area 78.78 (W) x 21.18 (H) mm mm
Active Area 76.78 (W) x 19.18 (H) mm
Dot Size 0.28 (W) 0.28 (H) mm
Dot Pitch 0.30 (W) x 0.30 (H) mm
Weight 9.6 g
IC Controller/Driver STV8105
Product No.
Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data
DD-25664BE-1A REV. C
Page 5 / 26
2.2 MECHANICAL DRAWING
N.C.
Symbol
1
0.15 Max
5.00±0.30 (Tag)
Pin
Display Pattern
Scale (10:1)
8.00±0.30 (Remove Tape)
0.30
0.28
0.28
0.30
1.10
0.70
2.20 Max
0.25
KVM2
SCLK_OUT
3
15.20 Ref
VDC
GATE
ISENSE
VCOMP
VSENSE
FSYNC_OUT
LSYNC_OUT
6
9
8
7
542
10
24.70 Ref
10.00±0.30
78.78 (View Area)
81.00±0.30 (Polarizer)
88.00±0.30 (Cap Size)
88.00±0.30 (Panel Size)
P0.30X256-0.02=76.78 (Active Area)
x 64 Pixels
256
Active Area 3.12"
VF
VSS
VPP
VH1
VH2
VHSENSE
11
13
1215171614
PXS
VSS
VDD
AVM1
AVM2
VREF1
VREF2
21
20
18
19
VDD
XRES
TONXF
CMODE
SELCLK
MSEL<1>
23
272829
25
24
26
22
DIN<3>
DIN<4>
DIN<5>
DIN<6>
DIN<7>
MSEL<0>
31
33
35
30
34
32
VSS
N.C.
CRC
CRR
CRG
XCS1
XWR
XCS2
XCMD
DIN<2>
DIN<0>
DIN<1>
36
3941403837
KVM1
FSYNC_IN
LSYNC_IN
43
42
4950464748
45
44
1.35 Ref
( Row 1 )
K_OUT1
( Row 63 )
3.95 Ref
4.00 (Stiffener)
Glue
4.60
0.80
1.60
0.80
Contact Side
1.00 Max
0.30±0.03
0.10
K_OUT63
A_OUT1
( Column 256 )
A_OUT128
( Column 129 )
A_OUT129
( Column 128 )
A_OUT256
( Column 1 )
K_OUT64
( Row 64 )
K_OUT2
( Row 2 )
14.00±0.20
N.C.
N.C.
K_OUT1
K_OUT3
K_OUT5
K_OUT7
K_OUT9
K_OUT11
K_OUT13
K_OUT15
K_OUT17
K_OUT19
K_OUT21
K_OUT23
K_OUT25
K_OUT27
K_OUT29
K_OUT31
K_OUT33
K_OUT35
K_OUT37
K_OUT39
K_OUT41
K_OUT43
K_OUT45
K_OUT47
K_OUT49
K_OUT51
K_OUT53
K_OUT55
K_OUT57
K_OUT59
K_OUT61
K_OUT63
K_OUT65
K_OUT67
K_OUT69
K_OUT71
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A_OUT1
A_OUT2
A_OUT3
A_OUT4
A_OUT5
A_OUT6
A_OUT7
A_OUT8
A_OUT9
A_OUT10
A_OUT11
A_OUT12
A_OUT13
A_OUT14
A_OUT15
A_OUT16
A_OUT17
A_OUT18
A_OUT19
A_OUT20
A_OUT21
A_OUT22
A_OUT23
A_OUT24
A_OUT25
A_OUT26
A_OUT27
A_OUT28
A_OUT29
A_OUT30
A_OUT31
A_OUT32
A_OUT33
A_OUT34
A_OUT35
A_OUT36
A_OUT37
A_OUT38
A_OUT39
A_OUT40
A_OUT41
A_OUT42
A_OUT43
A_OUT44
A_OUT45
A_OUT46
A_OUT47
A_OUT48
A_OUT49
A_OUT50
A_OUT51
A_OUT52
A_OUT53
A_OUT54
A_OUT55
A_OUT56
A_OUT57
A_OUT58
A_OUT59
A_OUT60
A_OUT61
A_OUT62
A_OUT63
A_OUT64
A_OUT65
A_OUT66
A_OUT67
A_OUT68
A_OUT69
A_OUT70
A_OUT71
A_OUT72
A_OUT73
A_OUT74
A_OUT75
A_OUT76
A_OUT77
A_OUT78
A_OUT79
A_OUT80
A_OUT81
A_OUT82
A_OUT83
A_OUT84
A_OUT85
A_OUT86
A_OUT87
A_OUT88
A_OUT89
A_OUT90
A_OUT91
A_OUT92
A_OUT93
A_OU
T94
A_OUT95
A_OUT96
A_OUT97
A_OUT98
A_OUT99
A_OUT100
A_OUT101
A_OUT102
A_OUT103
A_OUT104
A_OUT105
A_OUT106
A_OUT107
A_OUT108
A_OUT109
A_OUT110
A_OUT111
A_OUT112
A_OUT113
A_OUT114
A_OUT115
A_OUT116
A_OUT117
A_OUT118
A_OUT119
A_OUT120
A_OUT121
A_OUT122
A_OUT123
A_OUT124
A_OUT125
A_OUT126
A_OUT127
A_OUT128
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A_OUT129
A_OUT130
A_OUT131
A_OUT132
A_OUT133
A_OUT134
A_OUT135
A_OUT136
A_OUT137
A_OUT138
A_OUT139
A_OUT140
A_OUT141
A_OUT142
A_OUT143
A_OUT144
A_OUT145
A_OUT146
A_OUT147
A_OUT148
A_OUT149
A_OUT150
A_OUT151
A_OUT152
A_OUT153
A_OUT154
A_OUT155
A_OUT156
A_OUT157
A_OUT158
A_OUT159
A_OUT160
A_OUT161
A_OUT162
A_OUT163
A_OU
T164
A_OUT165
A_OUT166
A_OUT167
A_OUT168
A_OUT169
A_OUT170
A_OUT171
A_OUT172
A_OUT173
A_OUT174
A_OUT175
A_OUT176
A_OUT177
A_OUT178
A_OUT179
A_OUT180
A_OUT181
A_OUT182
A_OUT183
A_OUT184
A_OUT185
A_OUT186
A_OUT187
A_OUT188
A_OUT189
A_OUT190
A_OUT191
A_OUT192
A_OUT193
A_OUT194
A_OUT195
A_OUT196
A_OUT197
A_OUT198
A_OUT199
A_OUT200
A_OUT201
A_OUT202
A_OUT203
A_OUT204
A_OUT205
A_OUT206
A_OUT207
A_OUT208
A_OUT209
A_OUT210
A_OUT211
A_OUT212
A_OUT213
A_OUT214
A_OUT215
A_OUT216
A_OUT217
A_OUT218
A_OUT219
A_OUT220
A_OUT221
A_OUT222
A_OUT223
A_OUT224
A_OUT225
A_OUT226
A_OUT227
A_OUT228
A_OUT229
A_OUT230
A_OUT231
A_OUT232
A_OUT233
A_OUT234
A_OUT235
A_OUT236
A_OUT237
A_OUT238
A_OUT239
A_OUT240
A_OUT241
A_OUT242
A_OUT243
A_OUT244
A_OUT245
A_OUT246
A_OUT247
A_OUT248
A_OUT249
A_OUT250
A_OUT251
A_OUT252
A_OUT253
A_OUT254
A_OUT255
A_OUT256
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
K_OUT72
K_OUT70
K_OUT68
K_OUT66
K_OUT64
K_OUT62
K_OUT60
K_OUT58
K_OUT56
K_OUT54
K_OUT52
K_OUT50
K_OUT48
K_OUT46
K_OUT44
K_OUT42
K_OUT40
K_OUT38
K_OUT36
K_OUT34
K_OUT32
K_OUT30
K_OUT28
K_OUT26
K_OUT24
K_OUT22
K_OUT20
K_OUT18
K_OUT16
K_OUT14
K_OUT12
K_OUT10
K_OUT8
K_OUT6
K_OUT4
K_OUT2
N.C.
N.C.
2-R0.50±0.05
N.C.
50
KVM1
CRC
CRR
CRG
LSYNC_IN
FSYNC_IN
VSS
XCS2
XCS1
XWR
XCMD
DIN<0>
DIN<1>
DIN<2>
DIN<3>
DIN<4>
DIN<5>
DIN<6>
DIN<7>
XRES
VDD
MSEL<0>
MSEL<1>
SELCLK
CMODE
TONXF
PXS
60.00±0.20
40.00±0.10
25.50±0.20
VSS
VDD
VREF1
VREF2
VF
AVM1
AVM2
VH1
VHSENSE
P0.50X(50-1)=24.50±0.10 (W0.30±0.05)
VH2
VPP
VSS
GATE
VDC
ISENSE
VCOMP
VSENSE
LSYNC_OUT
FSYNC_OUT
SCLK_OUT
KVM2
N.C.
1
Display Pattern
Notes:
8-bit 68XX/80XX Parallel, 4-wire SPI
The actual assembled total thickness with above materials should be 2.35 Max
2. Die Size: 12748um x 1868um
4. Interface:
3. TCP Number: UT-0505-T01
5. General Tolerance: ±0.30
6. The total thickness (2.20 Max) is without polarizer protective film & remove tape.
1. Driver IC: STV8105
Page 6 / 26
Product No.
3.50±0.50
4.61
5.61
1.00±0.50
3.00
2.00
P0.30X64-0.02=19.18 (Active Area)
21.18 (View Area)
23.30±0.30 (Polarizer)
25.30±0.30 (Cap Size)
27.80±0.30 (Panel Size)
9.38
10.50
11.50
14.00
20.00±0.30
DD-25664BE-1A REV. C
3.00
Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data
3 ELECTRICAL SPECIFICATION
3.1 ABSOLUTE MAXIMUM RATI NG S
VSS = 0 V, Ta = 25 °C
Item Symbol Min Max Unit Note
Supply Voltage VDD -0.3 4.6 V 1, 2
DC/DC Supply Voltage
-0.3 12 V 1, 2
V
DC
Driver Supply Voltage VPP -0.3 27 V 1, 2
Program Voltage V
-0.3 20 V 1, 2
PRG
Operating Temperature Top -20 +70 °C
Storage Temperature Tst -30 +80 °C
Static Electricity Be sure that you are grounded when handling displays.
Note 1: All the above voltages are on the basis of “GND = 0V”. Note 2: When this module is used beyond the above absolute maximum ratings,
permanent breakage of the module may occur. Also, for normal operations, it is desirable to use this module under the conditions according to Section 3.2 “Electrical Characteristics”. If this module is used beyond these conditions, malfunctioning of the module can occur and the reliability of the module may deteriorate.
3.2 ELECTRICAL CHARACTERISTICS
VSS = 0 V, Ta = 25 °C
Item Symbol Condition Min Typ Max Unit
Supply Voltage VDD Ta = 25°C 3.0 3.3 3.6 V
DC/DC Supply Voltage VDC Ta = 25°C 3.0 5.0 10.0 V
Driver Supply Voltage VPP Ta = 25°C 13 14 15 V
Program Voltage V
Ta = 25°C 14 -- 18 V
PRG
High Level Input VIH Logic 0.8xVDD -- -- V
Low Level Input VIL Logic -- -- 0.2xVDD V
Product No.
Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data
DD-25664BE-1A REV. C
Page 7 / 26
Product No.
DD-25664BE-1A REV. C
Page 8 / 26
3.3 INTERFACE PIN ASSIGNMENT
No. Symbol I/O Function
RReesseerrvveedd PPiinn ((SSuuppppoorrttiinngg PPiinn))..
1 N.C. --
The supporting pins can reduce the influences from stresses on the function pins.
PPoowweerr SSuuppppllyy ffoorr OOdddd ((11)) && EEvveenn ((22)) RRooww DDrriivveerr..
2 VROWOFF2 I
3 SCLKOUT O
4 VSYNCOUT O
5 HSYNCOUT O
6 VSENSE I
7 VCOMP I/O
These are the constant voltage supply pins. When display is not active, the row output pins are pulled-up to the voltage supplied on the two pins. They are supplied externally.
SSyysstteemm CClloocckk OOuuttppuutt.
This pin is outputted to slave device and/or the specified row driver. It should be left open individually.
.
VVeerrttiiccaall//HHoorriizzoonnttaall SSYYNNCC IInnppuutt//OOuuttppuutt.
The “VSYNC” and “HSYNC” pins, both inputs and outputs, are connected for synchronous operation. These should be left open individually.
FFeeeeddbbaacckk SSiiggnnaall
This pin is the feedback signal for voltage regulation loop. It is used to adjust the booster output voltage level (VPP). In case of VSENSE feedback disconnection the Driver is switched off.
CCoommppeennssaattiioonn PPiin
The output of the amplifier VCOMP is externally available for compensation. It is necessary when the DC/DC converter works in PWM constant frequency mode. PFM constant ton mode does not need a compensation network.
n
.
OOvveerr CCuurrrreenntt SSeennssee SSiiggnnaall ffoorr EExxtteerrnnaall SSwwiittcchhiinngg FFEETT
8 ISENSE I
9 VDC I
10 VDRIVE O
11 VSS I
This pin is the feedback signal for current sense. It is used for over current protection on the external FET.
PPoowweerr SSuuppppllyy ffoorr GGaattee DDrriivvee OOuuttppuutt BBuuffffeerr
This is the power supply pin for the internal buffer of the DC/DC voltage converter. It must be floated when the converter is not used.
GGaattee DDrriivvee SSiiggnnaall ffoorr EExxtteerrnnaall SSwwiittcchhiinngg FFEETT
This output pin drives the gate of external power FET.
GGrroouunndd
It also acts as the reference for the logic pins. It must be connected to external ground.
PPoowweerr SSuuppppllyy ffoorr NNoonn--VVoollaattiillee OOTTPP MMeemmoorryy
12 VPRG I
PPrrooggrraammmmiinngg
This is the NVM programming voltage supply pin. It is supplied externally.
PPoowweerr SSuuppppllyy ffoorr OOdddd ((11)) && EEvveenn ((22)) CCoolluummnn DDrriivveerr
13 VPP2 I
14 VHSENSE II
These are the constant current supply pins. They are supplied externally.
VVPPPP SSeennssee IInnppuutt
This pin is the feedback signal for voltage regulation loop. It is used to adjust the booster output voltage level (VPP). In case of VHSENSE feedback disconnection, VPP voltage rises up to the value fixed by the external resistor divider.
Product No.
Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data
DD-25664BE-1A REV. C
Page 9 / 26
No. Symbol I/O Function
PPoowweerr SSuuppppllyy ffoorr OOdddd ((11)) && EEvveenn ((22)) CCoolluummnn DDrriivveerr
15 VPP1 I
16 VCOLPRE2 I
17 VCOLPRE1 I
PPiinn ffoorr VVFF DDeetteeccttiioonn
18 VFDET I/O
19 VREF2 I/O
RReeffeerreennccee VVoollttaaggee
20 VREF1 I/O
PPoowweerr SSuuppppllyy ffoorr LLooggiicc CCiirrccuuiitt
21 VDD I
GGrroouunndd
22 VSS I
CCoommmmuunniiccaattiinngg PPrroottooccooll SSeelleecctt
23 P/S I
DDCC//DDCC CCoonnvveerrtteerr MMooddee SSeelleecctt
24 TON/F I
CCoolloorr MMooddee SSeelleecctt
25 CMODE I
IInntteerrnnaall//EExxtteerrnnaall SSyysstteemm CClloocckk SSoouurrccee SSeelleecctt
26 SELCLK I
PPrriimmaarryy//SSeeccoonnddaarryy SSeelleecctt
27 MSEL[1] I
MMaasstteerr//SSllaavvee SSeelleecctt
28 MSEL[0] I
These are the constant current supply pins They are supplied externally.
PPoowweerr SSuuppppllyy ffoorr OOdddd ((11)) && EEvveenn ((22)) CCoolluummnn PPrree-
a
rrggee
CChha
These are the constant voltage supply pins. They are supplied externally.
-
This pin is the detection of voltage difference between C1 and C256.
These are the current reference pins. It is possible to set two different reference current values for the odd (1) and even (2) outputs by connecting two different resistor values. With input CMODE, it is also to use only the reference current established on pin VREF1. These are supplied externally.
This is the voltage supply pins. It must be connected to external source.
It also acts as the reference for the logic pins. It must be connected to external ground.
This pin is MCU interface selection input. The parallel interface is active when P/S is high; the serial interface activates when P/S is
low
.
This pin is the control schemes selection input of the embedded booster circuit. The DC/DC converter works in PFM constant ton mode while it is connected to VDD. The DC/DC converter works in PWM constant frequency mode while it is connected to ground.
This pin is the display colors selection input. It corresponds to “Two” color display panel. A setup of another output current value is possible for an odd number pin and the even number pins of each with two reference current.
This pin is internal clock enable. When this pin is pulled high, an internal oscillation stable circuit is used. The internal clock will be disabled when it is pulled low, an external clock source must be connected for normal operation.
This pin is the Primary/Secondary selection input. The function is synchronous operation, which is the direction of the cathode. This pin must be pulled high to enable the chip function as primary.
This pin is the Master/Slave selection input. The function is synchronous operation, which is the direction of the anode. This pin must be pulled high to enable the chip function as master.
Product No.
Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data
DD-25664BE-1A REV. C
Page 10 / 26
No. Symbol I/O Function
29 VDD I
30 RST I
31
32
33
34
35
36
37
38
DIN[7]
DIN[6]
DIN[5]
DIN[4]
DIN[3]
DIN[2]
DIN[1]
DIN[0]
I
I
I
I
I
I
I
I
39 SD/C I
40 WR I
41 CS1 I
42 CS2 I
43 VSS I
44 VSYNCIN I
45 HSYNCIN I
PPoowweerr SSuuppppllyy ffoorr LLooggiicc CCiirrccuuiitt
This is the voltage supply pins. It must be connected to external source.
PPoowweerr RReesseett ffoorr CCoonnttrroolllleerr aanndd DDrriivveerr
This pin is reset signal input. When the pin is low, initialization of the chip is executed.
HHoosstt DDaattaa IInnppuutt BBuuss
These pins are 8-bit parallel bus to be connected to the microprocessor’s data bus. When serial mode is selected, DIN[7] will be the serial data input (SIN) and DIN[6] will be the serial clock input (SCLI).
DDaattaa//CCoommmmaanndd CCoonnttrrooll
This pin is Data/Command control pin. When the pin is pulled high, the data at DIN[7]~DIN[0] is treated as display data. When the pin is pulled low, the data at DIN[7]~DIN[0] will be transferred to the command register. For detail relationship to MCU interface signals, please refer to the Timing Characteristics Diagrams.
WWrriittee PPuullssee
This pin is MCU interface input. Data write operation is initiated when this pin is pulled low and the chip is selected.
CChhiipp SSeelleecctt
The two pins are the chip select input. The CS1 is activated for Primary/Secondary Master devices. The CS2 is activated for Primary/Secondary Slave devices.
GGrroouunndd
It also acts as the reference for the logic pins. It must be connected to external ground.
VVeerrttiiccaall//HHoorriizzoonnttaall SSYYNNCC IInnppuutt//OOuuttppuutt.
The “VSYNC” and “HSYNC” pins, both inputs and outputs, are connected for synchronous operation. These should be left open individually.
.
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No. Symbol I/O Function
EExxtteerrnnaall SSyysstteemm CClloocckk SSoouurrccee
46 CLKIN I
This pin is activated for the external RC/Crystal connection or Clock input.
EExxtteerrnnaall SSyysstteemm CClloocckk SSoouurrccee
47 ROSC O
This pin is activated for the external RC oscillator or Crystal oscillation. A resistor would be connected.
EExxtteerrnnaall SSyysstteemm CClloocckk SSoouurrccee
48 COSC O
This pin is activated for the external RC oscillator. A capacitor would be connected.
PPoowweerr SSuuppppllyy ffoorr OOdddd ((11)) && EEvveenn ((22)) RRooww DDrriivveerr..
49 VROWOFF1 I
These are the constant voltage supply pins. When display is not active, the row output pins are pulled-up to the voltage supplied on the two pins. They are supplied externally.
RReesseerrvveedd PPiinn ((SSuuppppoorrttiinngg PPiinn))..
50 N.C. --
The supporting pins can reduce the influences from stresses on the function pins.
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3.4 BLOCK DIAGRAM
Active Area 3.12"
x 64 Pixels
256
~
R2
R64
C256
VROWOFF2
HSYNCOUT
VSYNCOUT
VSENSE
VDC
ISENSE
VCOMP
VDRIVE
VHSENSE
VPP2
VPRG
VSS
SCLKOUT
VPP1
VCOLPRE2
VREF2
VCOLPRE1
VFDET
~
~~
STV8105
VREF1
~
C1
R63
R1
VSYNCIN
VSSWRHSYNCIN
ROSC
RST
MSEL[0]
VDD
MSEL[1]~DIN[0]
DIN[7]
VSS
VDD
P/S
TON/F
CMODE
SELCLK
VROWOFF1
CS1
CS2
CLKIN
COSC
SD/C
MCU Interface Selection: P/S Pins connected to MCU interface: RST, DIN[7]~DIN[0], SD/C, WR, and CS1
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3.5 TIMING CHARACTERISTICS
3.5.1 4.2.1 Parallel Interface Timing Characteristics:
Symbol Description Min Max Unit
Tah Address Hold Time 10 - ns
Taw Address Setup Time 0 - ns
T
System Cycle Time 200 - ns
cyc
Tds Data Setup Time 60 - ns
Tdh Data Hold Time 10 - ns
T
Write Pulse Width 60 - ns
cclw
* All the timings should be based on 30% and 70% of VDD-GND.
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3.5.2 4.2.2 Serial Interface Timing Characteristics:
Symbol Description Min Max Unit
T
Serial Clock Cycle Time 200 - ns
scyc
T
Address Setup Time 20 - ns
sas
T
Address Hold Time 20 - ns
sah
T
Chip Select Setup Time 20 - ns
css
T
Chip Select Hold Time 20 - ns
csh
T
Data Setup Time 20 - ns
sds
T
Data Hold Time 20 - ns
sdh
T
Pulse Width (Low) 90 - ns
slw
T
Pulse Width (High) 90 - ns
shw
* All the timings should be based on 30% and 70% of VDD-GND.
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Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data
4 OPTICAL SPECIFICATION
4.1 OPTICAL CHARACTERISTICS
Characteristics Symbol Conditions Min Typ Max Unit
Ta = 25 °C
Brightness Lbr With Polarizer 60 80 - cd/m
C.I.E. (Blue)
(x) (y)
Without Polarizer
Dark Room Contrast CR -
0.12
0.22
0.16
0.26
>1:100
0.20
0.30
View Angle >160 - -
Note 3: Optical measurement taken at 1/64 duty, 100Hz Frame Rate,
7Fh Luminance Adjustment Setting.
2
-
degree
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i
DDD
D
PPP
P
DDi
PPP
P
fff
5 FUNCTIONAL SPECIFICATION
5.1 COMMANDS
Refer to the Technical Manual for the STV8105.
5.2 POWER DOWN AND UP SEQUENCE
To protect the panel and extend the panel life time, the driver IC power up/down routine should include a delay period between high voltage and low voltage power sources during turn on/off. Such that panel has enough time to charge up or discharge before/after operation.
5.2.1 Power up Sequence:
1. Power up VDD
2. Send Display off command
3. Clear Screen
4. Power up V
PP
5. Delay 100ms (when VDD is stable)
6. Send Display on command
5.2.2 Power down Sequence:
1. Send Display off command
2. Power down VPP
3. Delay 100ms (when VPP is reach 0 and panel is completely discharges)
4. Power down VDD
5.3 RESET CIRCUIT
At the time of RST signal input…
Oscillator: Off DC/DC Converter: Off Column & Row Driver: V All Registers: Default Value
At the time of RST signal release or software reset completion (200ns maximum after F2h command sending)…
Oscillator: On DC/DC Converter: Off (Waiting for a Command) Column & Row Driver: VSS (Waiting for a Command) All Registers: Default Value (Waiting for a Command)
SS
VSS/Ground
V
V
oonn
V
V
V
V
oonn
issppllaayy oonn
D
D
V
PP
V
DD
issppllaayy ooffff
f
V
o
V
o
ooffff
V
V
D
DDD
PP
DD
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6 PACKAGING AND LABELLING SPECIFICATION
6.1 PACKAGING
6.2 LABELLING & MARKING
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7 QUALITY ASSURANCE SPECIFICATION
7.1 CONFORMITY
The performance, function and reliability of the shipped products conform to the Product Specification.
7.2 DELIVERY ASSURANCE
7.2.1 Delivery inspection standards
IPC-AA610 rev. C, class 2 electronic assemblies standard
7.2.2 Zone definition
A Viewing area
B Outside viewing area
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7.2.3 Visual inspection
Inspect under 30W fluorescent lamp leaving 50 cm between the module and the
lamp and 30 cm between the module and the eye (measuring position).
Appearance is inspected at the best contrast voltage (best contrast is adjusted
considering clearness and crosstalk on screen).
Inspect the module at 45° right and left, top and bottom.
Use the optimum viewing angle during the contrast inspection.
eye
45°45°
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7.2.3.1 Standard of appearance inspection
Units: mm
Class Item Criteria
Minor Outside & inside package Presence of product no., lot no., quantity
Critical
Major Dimension Product dimensions must be according to specification and drawing
Major Electrical Product electrical characteristics must be according to specification
Critical LCD
Minor Black spot,
Minor Polariser
Packing &
Label
Display
white spot,
dust
scratch
bubble
Product must not be mixed with others and quantity must not be different from that indicated on the label
Missing lines or wrong patterns on LCD display are not allowed
Round type: as per following drawing = (X+Y)/2 Acceptable quantity Size Zone A Zone B
Line type: as per following drawing Acceptable quantity Length Width Zone A Zone B
- - W0.05 Any number L≤2.0 W≤0.1 3 L>2.0 0
Total acceptable quantity: 3
Scratch on protective film is permitted Minor Polariser Scratch on polariser: same as No. 1 = (X+Y)/2 Acceptable quantity Size Zone A Zone B
Total acceptable quantity: 3
<0.1
0.1<∅<0.2
0.2<∅<0.25
0.25<
<0.5
>0.5
Any number
3 1 0
Any number
0
Any number
Any number
Any number
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Class Item Criteria
Minor Segment
deformation
Minor Panel
Chipping
1b. Pin hole on dot matrix display
Acceptable quantity
Size a,b<0.1 Any number (a+b)/20.1 Any number
0.5<∅<1.0
3
Total acceptable quantity: 7
2. Segments / dots with different width
Acceptable ab a/b4/3 a<b a/b>4/3
3. Alignment layer defect = (a+b)/2
Acceptable quantity
Size
0.4
0.4<1.0
1.0<1.5
1.5<2.0
Total acceptable quantity: 7
Any number
5 3 2
X 1/6 Panel length Y 1 Z T
Minor Panel
Cracking
Minor Cupper
Cracks not allowed
Not allowed if visible by eye inspection exposed (pin or film)
Minor Film or
Not allowed if affects electrical function Trace Damage
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Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data
Class Item Criteria
Minor Contact
Lead Twist Not allowed
Minor Contact
Lead
Not allowed Broken
Minor Contact
Lead Bent
Not allowed if
bent lead causes
short circuit
Not allowed if bent lead
extends horizontally
more than 50%
of its width
Minor Colour
Level of sample for approval set as limit sample uniformity
Major No unmelted solder paste should be present on PCB
PCB
Critical Cold solder joints, missing solder connections, or oxidation are not allowed Minor No residue or solder balls on PCB are allowed Critical Minor Tray
particles
Short circuits on components are not allowed
Size Quantity
On tray
On display
<0.2 >0.25 ∅≥0.25
L = 3 1
Any number
4 2
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7.3 DEALING WITH CUSTOMER COMPLAINTS
7.3.1 Non-conforming analysis
Purchaser should supply Densitron with detailed data of non-conforming sample. After accepting it, Densitron should complete the analysis in two weeks from receiving the sample. If the analysis cannot be completed on time, Densitron must inform the purchaser.
7.3.2 Handling of non-conforming display s
If any non-conforming displays are found during customer acceptance inspection which Densitron is clearly responsible for, return them to Densitron. Both Densitron and customer should analyse the reason and discuss the handling of non­conforming displays when the reason is not clear. Equally, both sides should discuss and come to agreement for issues pertaining to modification of Densitron quality assurance standard.
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8 RELIABILITY SPECIFICATION
8.1 RELIABILITY TESTS
Test Item Test Condition Evaluation and assessment
High Temperature Operation 85°C, 500 hrs
Low Temperature Operation -30°C, 500 hrs
High Temperature Storage 90°C, 500 hrs
Low Temperature Storage -40°C, 500 hrs
High Temperature & High Humidity Storage
Thermal Shock Storage
60°C, 90% RH, 500 hrs
-40°C ↔85°C, 100 cycles 30 min. dwell
The brightness should be greater than 50% of the initial brightness. The operational functions work.
All operation tests are conducted in all display on pattern.
The samples used for above tests do not include polarizer.
No moisture condensation is observed during tests.
8.1.1 FAILURE CHECK STANDARD
After the completion of the described reliability test, the samples were left at room temperature for 2 hrs prior to conducting the failure teat at 23±5 °C55±15% RH
8.2 LIFE TIME
Item Description
Function, performance, appearance, etc. shall be free from remarkable deterioration within 15,000 hours under ordinary operating and storage conditions of room
1
temperature (25±10 °C), normal humidity (45±20% RH), and in area not exposed to direct sunlight.
2 End of lifetime is specified as 50% of initial brightness.
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9 HANDLING PRECAUTIONS
Safety
If the panel breaks, be careful not to get the organic substance in your mouth or in your eyes. If the organic substance touches your skin or clothes, wash it off immediately using soap and plenty of water.
Mounting and Design
Place a transparent plate (e.g. acrylic, polycarbonate or glass) on the display surface to protect the display from external pressure. Leave a small gap between the transparent plate and the display surface. Design the system so that no input signal is given unless the power supply voltage is applied.
Caution during OLED cleaning
Lightly wipe the display surface with a soft cloth soaked with Isopropyl alcohol, Ethyl alcohol or Trichlorotriflorothane. Do not wipe the display surface with dry or hard materials that will damage the polariser surface. Do not use aromatic solvents (toluene and xylene), or ketonic solvents (ketone and acetone).
Caution against static charge
As the display uses C-MOS LSI drivers, connect any unused input terminal to V input any signals before power is turned on. Also, ground your body, work/assembly table and assembly equipment to protect against static electricity.
Packaging
Displays use OLED elements, and must be treated as such. Avoid strong shock and drop from a height. To prevent displays from degradation, do not operate or store them exposed directly to sunshine or high temperature/humidity.
Caution during operation
It is indispensable to drive the display within the specified voltage limit since excessive voltage shortens its life.
Other Precautions
When a display module is operated for a long of time with fixed pattern may remain as an after image or slight contrast deviation may occur. Nonetheless, if the operation is interrupted and left unused for a while, normal state can be restored. Also, there will be no problem in the reliability of the module.
Storage
Store the display in a dark place where the temperature is 25°C ± 10°C and the humidity below 50%RH. Store the display in a clean environment, free from dust, organic solvents and corrosive gases. Do not crash, shake or jolt the display (including accessories).
or VSS. Do not
DD
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Copyright ©2006 DENSITRON TECHNOLOGIES plc. All rights reserved. – Proprietary Data
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