DENSITRON DD-160128FC-1A, DD-160128FC-2A Application Notes

OLED DISPLAY MODULE

Application Notes

PRODUCT

NUMBER

DD-160128FC-1A/2A with EVK board

TABLE OF CONTENTS

1 EVK SCHEMATIC.......................................................................................................... 4

2 TIMING CHARACTERISTICS .................................................................................... 6

3 CONNECTION BETWEEN OLED AND EVK ......................................................... 11

4 HOW TO USE THE DD-160128FC-1A/2A ................................................................. 15

4.1 R

ECOMMENDED INITIAL CODE FOR 80 INTERFACE .................................................... 15

Product No.

DD-160128FC-1A/2A REV. B

Page 2 / 17

REVISION RECORD

Rev. Date Page Chapt. Comment ECR no.

A 30 Sep 06 First Issue

B 13 Jan 09 Second Issue

Product No.

DD-160128FC-1A/2A REV. B

Page 3 / 17

1 EVK Schematic

Product No.

DD-160128FC-1A/2A REV. B

Page 4 / 17

Symbol Definition

D17-D9：These pins are 9-bit bi-directional data bus to be connected to the MCU’s data bus.

D17-D10： These are for command and data inputs (8bit parallel interface).

CSB：These pins are CSB pins for master and slave driver IC. This pin is the chip select

input. The chip is enabled for MCU communication only when CSB is pulled low.

CPU： Selects the CPU type.

Low: 80-series CPU High: 68-Series CPU

PS： Selects parallel/Serial interface type.

Low: serial High: parallel.

RDB： For an 80-system bus interface, read strobe signal(active low).

For a 68-system bus interface, bus enable strobe (active high). When using SPI, fix it to VDD or VSS level.

WRB：For an 80-system bus interface, write strobe signal (active low).

For a 68-system bus interface, read/write select.

Low: Write High: Read.

When using SPI, fix it to VDD or VSS level.

RESB：Reset SEPS525F(active low).

VCC : External Column Driving Power Supply. VDD : Logic power supply. VSS : Power supply ground.

HV：External Column Driving Power Supply.

LV：Logic power supply.

GND：Power supply ground.

Note1: Please ground the unused data pins Note2: If you do not use RGB Interface, please ground VSYNC, HSYNC, Enable,

DOTCLK and floating VSYNCO.

Note3: If you do not use VDDIO, please connect it to LV (VDD).

Product No.

DD-160128FC-1A/2A REV. B

Page 5 / 17

2 Timing characteristics

80-Series MPU parallel Interface (write timing)

(VDD = 2.8V, Ta = 25˚C)

ITEM SYMBOL CONDITION MIN MAX UNIT PORT

Address hold

timing

Address setup

timing

System cycle

timing

Write “L” pulse

width

Write “H” pulse

width

Data setup timing tDS8 30 ns

Data hold timing tDH8

All the timing reference is 10% and 90% of VDD

Table 1 80-Series MPU Parallel Interface Timing Characteristics (Write)

tAH8 5 ns CSB

tAS8

‐

5

‐

ns RS

tCYC8 100 ns

tWRLW8 45 ns

tWRHW8

‐

45

‐

10

‐

ns

‐

ns

WRB

DB[17:0]

Figure 1 80-Series MPU parallel Interface Timing Diagram (Write)

Product No.

DD-160128FC-1A/2A REV. B

Page 6 / 17

80-Series MPU parallel Interface (Read timing)

(VDD = 2.8V, Ta = 25˚C)

ITEM SYMBOL CONDITION MIN MAX UNIT PORT

Address hold

timing

Address setup

timing

System cycle

timing

Read “L” pulse

width

Read “H” pulse

width

tAH8 5 ns CSB

tAS8

‐

5

‐

ns RS

tCYC8 200 ns

tWRLW8 90 ns

tWRHW8

‐

90

‐

ns

RDB

Data setup timing tDS8 - ns

Data hold timing tDH8

CL = 15 pF

0

60

ns

DB[17:0]

All the timing reference is 10% and 90% of VDD

Table 2 80-Series MPU Parallel Interface Timing Characteristics (Read)

Figure 2 80-Series MPU parallel Interface Timing Diagram (Read)

Product No.

DD-160128FC-1A/2A REV. B

Page 7 / 17

6800-Series MPU parallel Interface (write timing)

(VDD = 2.8V, Ta = 25˚C)

ITEM SYMBOL CONDITION MIN MAX UNIT PORT

Address hold

timing

Address setup

timing

System cycle

timing

Write “L” pulse

width

Write “H” pulse

width

tAH8 5 ns CSB

tAS8

‐

5

‐

ns RS

tCYC8 100 ns

tWRLW8 45 ns

tWRHW8

‐

45

‐

ns

E

Data setup timing tDS8 40 ns

Data hold timing tDH8

10

‐

ns

DB[17:0]

All the timing reference is 10% and 90% of VDD

Table 3 6800-Series MPU Parallel Interface Timing Characteristics (Write)

Figure 3 6800-Series MPU parallel Interface Timing Diagram (Write)

Product No.

DD-160128FC-1A/2A REV. B

Page 8 / 17

68-Series MPU parallel Interface (Read timing)

(VDD = 2.8V, Ta = 25˚C)

ITEM SYMBOL CONDITION MIN MAX UNIT PORT

Address hold

timing

Address setup

timing

System cycle

timing

Read “L” pulse

width

Read “H” pulse

width

tAH8 10 ns CSB

tAS8

‐

10

‐

ns RS

tCYC8 200 ns

tWRLW8 90 ns

tWRHW8

‐

90

‐

ns

E

Data setup timing tDS8 ns

Data hold timing tDH8

CL = 15 pF 0

70

ns

DB[17:0]

All the timing reference is 10% and 90% of VDD

Table 4 80-Series MPU Parallel Interface Timing Characteristics (Read)

Figure 4 6800-Series MPU parallel Interface Timing Diagram (Read)

Product No.

DD-160128FC-1A/2A REV. B

Page 9 / 17

SPI Interface

(VDD = 2.8V, Ta = 25˚C)

ITEM SYMBOL CONDITION MIN MAX UNIT PORT

Serial clock cycle tCYCS 60 ns

SCL “H” pulse

width

SCL “L” pulse

width

tSHW 25 ns

tSLW

‐

25

-

SCL

ns

Data setup timing tDSS 25 ns

Data hold timing tDHS

25

-

SDI

ns

CSBSCL timing tCSS ns

- 25 -

CSBhold timing tCSH

All the timing reference is 10% and 90% of VDD

Table 5 SPI Interface Timing Characteristics

Figure 5 SPI Interface Timing Characteristics

ns

CSB

Product No.

DD-160128FC-1A/2A REV. B

Page 10 / 17

3 Connection Between OLED and EVK

Figure 6 EVK PCB and DD-160128FC-1A/2A Module

Product No.

DD-160128FC-1A/2A REV. B

Page 11 / 17

Figure 7 DD-160128FC-1A/2A and EVK assembled (Top view)

The SEPS525F is a COF type package, which means that the connect pads are on the top of the display connector. When the EVK and display are assembled, finally push the locking pad to hold the display in place, see Figure 6 and Figure 7. User can use wires to connect the EVK with the system. The example is shown below in figure 8;

Product No.

DD-160128FC-1A/2A REV. B

Page 12 / 17

Figure 8 control MCU (not supplied) connected with EVK

Note 1：It is the external most positive voltage supply. In this sample it is connected to

power supply.

6. Power down and Power up Sequence

To protect OLED panel and to extend the panel life time, the driver IC power up/down routine should include a delay period between high voltage and low voltage power sources during turn on/off. Such that panel has enough time to charge up or discharge before/after operation.

Power up Sequence:

Product No.

DD-160128FC-1A/2A REV. B

Page 13 / 17

1. Power up VDD and VDDIO

2. Send Display off command

3. Driver IC Initial Setting

4. Clear Screen

5. Power up V

CC

6. Delay 100ms (when V

DD is stable)

7. Send Display on command

Power down Sequence:

1. Send Display off command

2. Power down V

CC

3. Delay 100ms

4. Power down VDD and VDDIO

Product No.

DD-160128FC-1A/2A REV. B

Page 14 / 17

4 How to use the DD-160128FC-1A/2A

Driver IC Initial Code

Reset Driver IC

RES#=0

Delay 100ms

RES#=1

Clear RAM

Display on

Start

Display

4.1 Recommended Initial code for 80 interface

write_c(0x06); // Display off write_d(0x00); write_c(0x02); // OSC_CTL write_d(0x01); write_c(0x03); // CLOC_DIV write_d(0x30); // 115Hz write_c(0x04); // REDUCE_CURRENT write_d(0x00); write_c(0x80); // IREF

Product No.

DD-160128FC-1A/2A REV. B

Page 15 / 17

write_d(0x00); write_c(0x08); // PRECHARGE_TIME_R write_d(0x01); write_c(0x09); // PRECHARGE_TIME_G write_d(0x01); write_c(0x0a); // PRECHARGE_TIME_B write_d(0x02); write_c(0x0b); // PRECHARGE_CURRENT_R write_d(0x0C); write_c(0x0C); // PRECHARGE_CURRENT_G write_d(0x19); write_c(0x0d); // PRECHARGE_CURRENT_B write_d(0x15); write_c(0x10); // DRIVING_CURRENT_R write_d(0x32); write_c(0x11); // DRIVING_CURRENT_G write_d(0x27); write_c(0x12); // DRIVING_CURRENT_B write_d(0x2B); write_c(0x13); // DISPLAY_MODE_SET write_d(0x00); write_c(0x14); // RGB_IF write_d(0x21); write_c(0x15); // RGB_POL write_d(0x00); write_c(0x16); // MEMORY_WRITE_MODE write_d(0x76); write_c(0x17); // MX1_ADDR write_d(0x00); write_c(0x18); // MX2_ADDR write_d(0x9f); write_c(0x19); // MY1_ADDR write_d(0x00); write_c(0x1a); // MY2_ADDR write_d(0x7f); write_c(0x20); // MEMORY_ACCESSPOINTER X write_d(0x00); write_c(0x21); // MEMORY_ACCESSPOINTER X write_d(0x00); write_c(0x28); // DUTY write_d(0x7f); write_c(0x29); // DISPLAY START LINE write_d(0x00); write_c(0x2e); // D1_DDRAM_FAC write_d(0x00); write_c(0x2f); // D1_DDRAM_FAR write_d(0x00); write_c(0x31); // D2_DDRAM_FAC write_d(0x00); write_c(0x32); // D2_DDRAM_FAR write_d(0x00); write_c(0x33); // SCR1_FX1 write_d(0x00); write_c(0x34); // SCR1_FX2 write_d(0x9f); write_c(0x35); // SCR1_FY1 write_d(0x00); write_c(0x36); // SCR1_FY1

Product No.

DD-160128FC-1A/2A REV. B

Page 16 / 17

write_d(0x7f); write_c(0x06); // Display on write_d(0x01);

Sub Function for 80 Interface

void write_c(unsigned char out_command) { RS=0; CS=0; WR=0; P1=out_command; WR=1; CS=1; RS=1; } void write_d(unsigned char out_data) { RS=1; CS=0; WR=0; P1=out_data; WR=1; CS=1; } void White_pattern() { write_c(0x20); // MEMORY_ACCESSPOINTER X write_d(0x00); write_c(0x21); // MEMORY_ACCESSPOINTER X write_d(0x00); write_c(0x22); for(i=0;i<128;i++) { for(j=0;j<160;j++) { write_d(0xfc); write_d(0xfc); write_d(0xfc); } } }

Recommended Initial Code and Sub Function Note：1.For 80 series CPU interface.

2. For 8bits Ttiple Transfer 262K support.

Product No.

DD-160128FC-1A/2A REV. B

Page 17 / 17

DENSITRON DD-160128FC-1A, DD-160128FC-2A Application Notes

Specifications and Main Features

Frequently Asked Questions

User Manual