Static Electricity Be sure that you are grounded when handling displays.
Note 1: All the above voltages are on the basis of “GND=0V”.
Note 2: When this module is used beyond the above absolute maximum ratings, permanent
damage to the module may occur. Also for normal operations it’s desirable to use
this module under the conditions according to Section 3.2 “Electrical
Characteristics”. If this module is used beyond these conditions the module may
malfunction and the reliability could deteriorate.
This is the ground pin. It also acts as a reference for the logic pins, the
OLED driving voltages and the analogue circuits. It must be connected to
external ground
Output for connected external NMOS
3
SW
This output pin drives the gate of the external NMOS of the booster
circuit.
Power supply for DC/DC converter circuit
4
VDD2
This is the power supply pin for the internal buffer of the DC/DC voltage
converter. It must be connected to VDD when the converter is used. It
must be floated when the converter is not used
Feedback Input for DC/DC converter circuit
5
FB
This pin is the feedback resistor input of the booster circuit. It is used to
adjust the booster output voltage level (VCC)
Input for connected External NMOS
6
SENSE
This pin connects to the source current pin of the external NMOS of the
booster circuit.
Voltage reference for DC/DC converter circuit
7
8
9 C86
10
VBREF
VDD1
PS
This pin is the internal voltage reference of booster circuit. A Stabilization
capacitor typ 1µF should be connected to VSS.
Power supply for logic circuit
This is a voltage supply pin. It must be connected to external source.
Communicating protocol select
These pins are MCU interface selection input. See the following table:
C86 0 1 0
PS 1 1 0
Chip select
11
CS
This pin is the chip select input. The chip is enabled for MCU communication
only when CS# is pulled low.
Power reset for controller and driver
12
RES
This pin is reset signal input. When the pin is low initialization of the chip is
executed.
Data/Command Control
This pin is data/command control pin. When the pin is pulled high, the input
13
A0
D7~D0 is treated as display data. When the pin is pulled low, the input at D7~D0
will be transferred to the command register. For detail relationship to MCU
interface signals please refer to the Timing Characteristics Diagrams
Read/Write select or write
This pin is MCU interface input. When interfacing to a 6800-series
microprocessor this pin will be used as Read/Write (R/W#) selection
14 WR
input. Pull this pin to “High” for Read mode and pull it to “Low” for Write
mode.
When 8080 interface mode is selcted this pin will be the Write (WR#)
input. Data write operation is initiated when this pin is pulled low and the
CS# is pulled low.
This pin is MCU interface input. When interfacing to a 6800-series
microprocessor this pin will be used as the Enable (E) signal. Read/Write
operation is initiated when this pin is pulled high and the CS# is pulled
low.
When connecting to a 8080-series microprocessor this pin receives the
Read (RD#) signal. Data read operation is initiated when this pin is pulled
low and CS# is pulled low
Voltage output high level for COM signal
This pin is the input pin for the voltage output high level for COM signals. A
capacitor should be connected between this pin and VSS.
Power Supply for OLED Panel
This is the most positive voltage supply pin of the chip. It can be supplied
externally or generated internally by using internal DC/DC voltage converter
Host data Input/Output bus
These pins are 8-bit bi-directional data bus to be connected to the
microprocessors data bus. When serial mode is selected D1 will be the serial data
input SDIN and D0 will be the serial clock input SCLK.
24
25
Current reference for brightness adjustment
26 IREF
This pin is segment current reference pin. A resistor should be connected
between this pin and VSS. Set the current at 10µA
MCU Interface Selection: PS and C86
Pins connected to MCU interface: D7~D0, RD, WR, A0, RES and CS.
*VBREF, SENSE, FB, VDD2 and SW should be left float when using external
DC/DC converter.
System cycle time tCYC6 300
Address setup timing tAS6 0
Address hold time tAH6 0
Write Data Setup time tDS6 40
Write Data Hold time tDH6 15
Output Disable time tOH6 10 70
Access time tACC6 - 140
Enable H pulse width (Write) tEWHW100 Enable H pulse width (Read) tEWHR 120 Enable L pulse width (Write) tEWLW100 -
Enable L pulse width (Read) tEWLR 100
Rise time tR - 15
Fall time tF - 15
All the timing should be based on 30% and 70% of V
System cycle time tCYC8 300
Address setup timing tAS8 0
Address hold time tAH8 0
Write Data Setup time tDS8 40
Write Data Hold time tDH8 15
Output Disable time tCH8 10 70
/RD Access time tACC8 - 140
Control L pulse width (WR) tCCLW 100 Control L pulse width (RD) tCCLR 120 Control H pulse width (WR) tCCHW 100 Control H pulse width (RD) tCCHR 100 -
Rise time tR - 15
Fall time tF - 15
All the timing should be based on 30% and 70% of V
Serial Clock Cycle Time TSCYC 250
Address Setup Time TSAS 150
Address Hold Time TSAH 150
Data Setup Time TSDS 100
Data Hold Time TSDH 100
/CS Setup Time TCSS 120 /CS Hold Time TCSH 60 Serial clock H pulse width TSHW 100 Serial clock L pulse width TSLW 100 Rise Time tR - 15
Fall Time tF - 15
* All the timing should be based on 30% and 70% of V
Please refer to the Technical Manual for the SH1101A
5.2 POWER UP/DOWN SEQUENCE
To protect panel and extend the panel lifetime, the driver IC power up/down routine should
include a delay period between high voltage and low voltage power sources during turn
on/off. It gives the panel enough time to complete the action of charge and discharge
before/after the operation.
5.2.1 POWER UP SEQUENCE
V
1. Power up V
DD1
2. Delay 100ms at least VPP
(when reset is finished)
3. Send Display off command
4. Clear Screen
5.Power up VPP V
6. Delay 100ms
(when VDD1 is stable) VSS Ground
7. Send Display on command
ON VPP ON
DD1
DD1
Display On
5.2.2 POWER DOWN SEQUENCE
Display off V
1. Send Display off command
2. Power down VPP VPP
3. Delay 100ms
(When VPP reach 0 and panel is
completely discharges) V
4. Power down V
V
DD1
SS Ground
DD1
5.3 RESET CIRCUIT
When RES# input is low, the chip is initialized with the following status:
1. Display is OFF
2. 132x64 Display mode
3. Normal segment and display data colume and row address mapping (SEG0 mapped to
column address ooH and COM0 mapped to row address 00H)
4. Shift register data clear in serial interface
5. Display start line is set at display RAM address 0
Command usage and explanation of an actual example
<Initialisation Setting>
Set Display Clock Divide Ratio / Oscillator Frequency
(11010101 with XXXXXXXX)
Set Display Offset
(11010011 with **XXXXXX)
Set Multiplex Ratio
(10101000 with **XXXXXX)
Set DC/DC On/Off
(10101101 with 1000101X)
10001010=>0x8A (Off)
Set Display Start Line
(01XXXXXX)
Set Segment Re-map
(1010000X)
Set COM Output Scan Direction
(1100X***)
Set COM Pins Hardware Configuration
(11011010 with 000X0010)
00010010=>0x12 (Alternative Mode)
Set Contrast Control Register
(10000001 with XXXXXXXX)
Set Entire Display On/Off (1010010X)
10100100=>0xA4 (Normal)
Set Normal/Inverse Display (1010011X)
10100110=>0xA6 (Normal)
Set Display On/Off (1010111X)
10101111=> 0xAF (Turns On)
<Display Boundary Settings>
Set Page Address (1011XXXX)
10110000=>0xB0
Set Lower Column Address
(0000XXXX)
Set Higher Column Address
(0001XXXX)
If the noise is accidentally occurred at the displaying window during the operation, please
reset the display in order to recover the display function.
Level of sample for approval set as limit sample
uniformity
Major No unmelted solder paste should be present on PCB
PCB
Critical Cold solder joints, missing solder connections, or oxidation are not allowed
Minor No residue or solder balls on PCB are allowed
Critical
Minor Tray
Purchaser should supply Densitron with detailed data of non-conforming sample.
After accepting it, Densitron should complete the analysis in two weeks from receiving the
sample.
If the analysis cannot be completed on time, Densitron must inform the purchaser.
7.3.2 Handling of non-conforming displays
If any non-conforming displays are found during customer acceptance inspection which
Densitron is clearly responsible for, return them to Densitron.
Both Densitron and customer should analyse the reason and discuss the handling of nonconforming displays when the reason is not clear.
Equally, both sides should discuss and come to agreement for issues pertaining to
modification of Densitron quality assurance standard.
Test Item Test Condition Evaluation and assessment
High Temperature Operation 70°C±2, 120 hours
Low Temperature Operation -30°C±2, 120 hours
High Temperature Storage 80°C±2, 120 hours
Low Temperature Storage -40°C±2, 120 hours
High Temperature & High
Humidity Storage(Operation)
60°C±2, 90%RH, 120 hours
24 cycle of
Thermal Shock
-40°C 1 Hour,
85°C 1 Hour. 60 Mins dwell
No abnormalities in function
and appearance
No abnormalities in function
and appearance
No abnormalities in function
and appearance
No abnormalities in function
and appearance
No abnormalities in function
and appearance
No abnormalities in function
and appearance
• The brightness should be greater than 50% of the initial brightness.
• The samples used for above tests do not include polarizer.
• No moisture condensation is observed during tests.
8.1.1 FAILURE CHECK STANDARD
After the completion of the described reliability test, the samples were left at room
temperature for 2 hrs prior to conducting the failure teat at 23±5 °C; 55±15% RH
8.2 LIFE TIME
Item Description
Function, performance, appearance, etc. shall be free from remarkable deterioration
more than 10,000 hours under 70 cd/m² brightness and storage conditions of room
1
temperature (25±10 °C), normal humidity (45±20% RH), and in area not exposed to
direct sunlight.
2 End of lifetime is specified as 50% of initial brightness.
If the panel breaks, be careful not to get the organic substance in your mouth or in your eyes.
If the organic substance touches your skin or clothes, wash it off immediately using soap and plenty of
water.
Mounting and Design
Place a transparent plate (e.g. acrylic, polycarbonate or glass) on the display surface to protect the
display from external pressure. Leave a small gap between the transparent plate and the display
surface.
Design the system so that no input signal is given unless the power supply voltage is applied.
Caution during OLED cleaning
Lightly wipe the display surface with a soft cloth soaked with Isopropyl alcohol, Ethyl alcohol or
Trichlorotriflorothane.
Do not wipe the display surface with dry or hard materials that will damage the polariser surface.
Do not use aromatic solvents (toluene and xylene), or ketonic solvents (ketone and acetone).
Caution against static charge
As the display uses C-MOS LSI drivers, connect any unused input terminal to V
input any signals before power is turned on.
Also, ground your body, work/assembly table and assembly equipment to protect against static
electricity.
Packaging
Displays use OLED elements, and must be treated as such. Avoid strong shock and drop from a
height.
To prevent displays from degradation, do not operate or store them exposed directly to sunshine or
high temperature/humidity.
Caution during operation
It is indispensable to drive the display within the specified voltage limit since excessive voltage
shortens its life.
Other Precautions
When a display module is operated for a long of time with fixed pattern may remain as an after image
or slight contrast deviation may occur.
Nonetheless, if the operation is interrupted and left unused for a while, normal state can be restored.
Also, there will be no problem in the reliability of the module.
Storage
Store the display in a dark place where the temperature is 25°C ± 10°C and the humidity below
50%RH.
Store the display in a clean environment, free from dust, organic solvents and corrosive gases.
Do not crash, shake or jolt the display (including accessories).