C0240QGLA-T
Preliminary Product Specification
Module name: C0240QGLA-T
Issue date: 2007/08/09
Version: 2.6
Customer
Approved by Customer
Approved by CMEL
PD Division ENG Division QA Dept
Note:
1. The information contained herein may be change without prior notice. It is therefore advisable to contact
Chi MEI ELCorp before designed your product based on this specification.
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C0240QGLA-T
Reversion History
Version Date Page Description
Ver.2.0
Ver.2.1
Ver.2.2
Ver.2.3
Ver.2.4
Ver.2.5
Ver.2.6
2007/07/20
2007/08/09
2007/11/13
2007/11/20
2007/11/22
2007/11/28
2007/12/04
All
4 & 10 &17
3
19
21
4
9
11
13
17
14
15
14
22
14
21
Preliminary specification was first issued
Operation temp. & modify optical characteristic
& RA
RoHS Compatible Expression
Mod External Dimension Drawing
Add Package Drawing
Mod Absolute Max. Ratings
Add Image Data Fomat
Add RS Note
Add Image Data Fomat
Mod Pin Assignment
Mod test Condition
Add viewing angle test condition note
Mod Electro-Optical Characteristic
Mod Package Drawing
Mod Electro-Optical Characteristic
Mod Reliability Test
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C0240QGLA-T
1. Purpose:
This documentation defines general product specification for OLED module supplied by
CMEL. The information described in this technical specification is tentative. Please Contact
CMEL’s representative while your product is modified.
2. General Description:
Driving Mode: Active Matrix.
Color Mode: Full Color (262K color)
Driver IC: S6E63D6, COG Assembly
Interface:
1. MPU i80-system 18-/16-/9-/8-bit bus interface
2. MPU i68-system 18-/16-/9-/8-bit bus interface
3. Serial data transfer interface
4. RGB 18-/16-/6-bit bus interface (DOTCLK,VSYNC,HSYNC,DE,DB17-0)
Application: Cell phone etc..
RoHS Compatible
3. Mechanical Data:
No. Items Specification Unit
1 Diagonal Size
2 Resolution
3 Pixel Pitch
4 Active Area
5 Outline Area(Glass)
6 Thickness
7 Weight
2.4” Inch
240 xRGBx320
0.051×0.153
36.72×48.96
42×58.6
mm
mm
mm
1.65 (Typ) mm
12 (Typ) g
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C0240QGLA-T
4. Absolute Maximum ratings:
(VSS=0V)
Item Symbol Unit Value Note
Power supply voltage 1 VDD3 V -0.3 ~ + 5.0
Power supply voltage 2 VCI V -0.3 ~ + 5.0
Input Voltage range Vin V -0.3 ~ VDD+0.5
Operating temperature Topr C -20 ~ + 60
Storage temperature Tstg C -40~ + 85
Notes:
(1) Absolute maximum rating is the limit value. When the IC is exposed operation environment beyond
this range, the IC do not assure operations and may be damaged permanently, not be able to be
recovered.
(2) Absolute maximum rating is guaranteed only when our company’s package used.
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C0240QGLA-T
5. Electrical Characteristic:
5.1 DC Characteristic
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C0240QGLA-T
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C0240QGLA-T
5.2 AC Characteristic
5.2.1 CPU interface M68
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C0240QGLA-T
5.2.2 CPU interface M80
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C0240QGLA-T
Image Data format for 18bit CPU interface (262k color)
Image Data format for 16bit CPU interface (65k color)
Image Data format for 9bit CPU interface (262k color)
Image Data format for 8bit CPU interface (65K color)
Case 1:
Case 2:
Image Data format for 8bit CPU interface (262K color)
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C0240QGLA-T
5.2.3 SPI
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C0240QGLA-T
(Note) RS=”0” : Index data
RS=”1” : Instruction data
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C0240QGLA-T
5.2.4 RGB Interface
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C0240QGLA-T
Image Data format for 18bit RGB interface (262k color)
Image Data format for 16bit RGB interface (65k color)
Image Data format for 6bit RGB interface (262k color)
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C0240QGLA-T
6. Electro-Optical Characteristic:
Items Symbol Min Typ. Max Unit Remark
Operating Luminance L 170 200 230 Cd/m
2
(1)(5)
Power Consumption Pon - 260 300 mW
30% pixels
on (1)
Response Time Tres - - 50 us (2)
CIEx (White) Wx 0.26 0.31 0.36 - (5)
CIEy( White) W y 0.28 0.33 0.38 - (5)
CIEx (Red) Rx 0.62 0.66 0.70 (5)
CIEy( Red) Ry 0.30 0.34 0.38 (5)
CIEx (Green) Gx 0.25 0.29 0.33 (5)
CIEy( Green) Gy 0.61 0.65 0.69 (5)
CIEx (Blue) Bx 0.11 0.15 0.19 (5)
CIEy( Blue) By 0.12 0.16 0.20 (5)
V iewing Angle VA 160 170 - Degree (3)
Contrast CR 5000:1 10000:1 (4)
Operation Lifetime LTop 20000 Hrs (1)(6)
Note:
Measuring surrounding: dark room
Surrounding temperature: 25oC
IOVCC = 1.65V ~ 3.3V
1. T est condition:
a. AR_VDD= 4.6V+/- 0.03V, AR_VSS= -4.4V+/- 0.03V
b. IC Initial Register Setting:
R03: 0x0030 // 16bit mode
R10: 0x0000 // IC stand by off
R18: 0x0028 // Frame Rate=80Hz
RF8: 0x000F // VGH=+5V
RF9: 0x000F // VGL=-5V
R05: 0x0001 // Display On
Gamma Register Setting:
R70: 0x1F00
R71: 0x2380
R72: 0x2A80
R73: 0x1511
R74: 0x1C11
R75: 0x1B15
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r
C0240QGLA-T
R76: 0x1A15
R77: 0x1C18
R78: 0x2115
2.response Time test condition
T
100%
90%
10%
3.Viewing angle test condition:
Tf
Time
Vss(GND)
ψ=270°
V iewing Angle= CR>10
4.Contrast
Luminance with all pixels white
CR =
Luminance with all pixels black
5.Optical tester: CA210
6. Brightness of 30% power consumption. Operating Life Time is defined when the
luminance has decayed to less than 50% of the initial measured luminance before life test.
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C0240QGLA-T
7. System Diagram:
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C0240QGLA-T
8. Pin Assignment:
PIN Symbol I/O Description Remarks
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AR_VDD
AR_VSS
VCI
VCI1
GND
C12M
C12P
C11M
C11P
VLOUT1
C31P
C31M
C32P
C32M
VLOUT3
VLOUT2
Positive voltage for OLED
I
Nagative voltage for OLED
I
Power supply for analog circuit(2.5v~3.3v)
I
A reference voltage for 1st booster r(connect a 1u/10v capacitance to
O
gnd)
Ground
I
I
External capacitance connect pin between C12M and C12P (1u/10V)
I
I
External capacitance connect pin between C11M and C11P (1u/10V)
I
1st booster output pin. (1u/10V)
O
I
External capacitance connect pin between C31M and C31P (1u/10V)
I
I
External capacitance connect pin between C32M and C32P (1u/10V)
I
3rd booster output pin. (1u/16V)
O
2nd booster output pin. (1u/16V)
O
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
C21P
C21M
VGS
IOVCC
SPB
ID_MIB
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
I
External capacitance connect pin between C21M and C21P. (1u/10V)
I
A reference level for the grayscale voltage generation circuit.
I
(connect to gnd)
I/O power supply
I
Select the CPU interface mode.
I
(0=parallel interface 1=serial interface)
Select the CPU type
I
(0=intel 80x-system 1=motorola 68x-system)
BI-directional data bus.
I/O
When CPU I/F,
18-bit interface : DB 17-0
I/O
16-bit interface : DB 17-10 , DB 8-1
9-bit interface : DB 8-0
I/O
8-bit interface : DB 8-1
I/O
When RGB I/F
I/O
18-bit interface : DB 17-0
18-bit interface : DB 17-0
I/O
16-bit interface : DB 17-10, DB 8-1
I/O
6-bit interface : DB 8-3
I/O
Fix unused pin to the VSS level
I/O
32
33
DB8
DB7
I/O
I/O
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C0240QGLA-T
34
35
36
37
38
39
40
41
42
43
44
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VSYNC
HSYNC
DOTCLK
ENABLE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Frame-synchronizing signal.
(VSPL=0 Low active, VSPL=1 High active)
I
FIX this pin at VSS level if the pin is not used
Line-synchronizing signal.
(HSPL=0 Low active, HSPL=1 High active)
I
FIX this pin at VSS level if the pin is not used
Input pin for clock signal of external interface : dot clock.
DPL=0 Display data is fetched at DOTCLK’s rising edge
I
DPL=1 Display data is fetched at DOTCLK’s falling edge
Fix this pin at VSS level if the pin is not used.
Data enablesignal pin for RGB interface.
EPL ENABLE GRAM write
I
0 0 Valid Updated
0 1 Invalid Held
GRAM
address
45
46
47
48
49
50
SDI
SDO
CSB
RW_WRB
RS
E_RDB
1 0 Invalid Held
1 1 Valid Updated
For a serial peripheral interface(SPI), input data is fetched at the
rising edge of the SCL signal, Fix SDI pin at VSS level if the pin
I
is not used.
For a serial peripheral interface (SPI), serves as the serial data
olutput pin(SDO), Successive bits are output at the falling edge
I
of the SCL signal.
Chip select signal input pin.
0= driver IC is selected and can be accessed.
I
1= driver IC is not selected and cannot be accessed.
Pin function CPU type Pin description
Read/Write operation
RW 68-system
I
WRB 80_system
SCL SPI The synchronous clock signal
Register select pin.
0=Index/status, 1=instruction parameter, GRAM data
I
Must be fixed at VDD3 level when not used.
Pin Function CPU type Pin description
E 68-system
I
RDB 80_system
When SPI mode is selected , fix this pin at VDD3 levle
selection pin
0=write 1=read
Write strobe signal.(Input pin)
Data is fetched at the rising
edge.
Read/Writeoperation enable
pin
Read strobe signal.
Read out data at the low level
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C0240QGLA-T
51
52
53
VREG1OUT
54
55
56
57
58
59
60
61
RESETB
MVDD
VCI
VGH
VGL
GND
X-
YX+
Y+
Reset pin initializes the IC when low. Should be reset after
I
power-on.
Internal power for RAM. Connect a capacitance to gnd. Connect a
O
capacitance(1u/10v) to gnd.
A reference level for the grayscale voltage. Connect a
O
capacitance(1u/10v) to gnd.
Power supply for analog circuit(2.5v~3.3v)
I
The positive voltage used in the gate driver. Connect a
O
capacitance(1u/10v) to gnd.
The negative voltage used in the gate driver. Connect a
O
capacitance(1u/10v) to gnd.
Ground
For touch screen
For touch screen
For touch screen
For touch screen
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C0240QGLA-T
9. External Dimension:
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C0240QGLA-T
10. Reliability Test:
No. Items Specification
1 High Temp. Storage 85°C, 240hrs
2 Low Temp. Storage -40°C, 240hrs
3 High Temp. Operation 60°C, 240hrs
4 Low Temp. Operation -20°C, 240hrs
5 High Temp / Humidity Storage 85°C, 85%RH, 240hrs
6 High Temp / Humidity Operation 60°C, 90%RH, 240hrs
-40°C ~85°C (-40°C /30min; transit/3min;
7 Thermal shock
85°C /30min; transit /3min)
1cycle: 66min, 100 cycles
Frequency: 5~50HZ, 0.5G
Scan rate : 1 oct/min
8 Vibration
Time : 2 hrs/axis
Test axis : X, Y, Z
Height: 76cm
Sequence : 1 angle、3 edges and 6
9 Drop
faces
Cycles: 1
10 ESD Air discharge model, ±8kV, 10 times
Evaluation Criteria
No damage to glass or encapsulation
No drastic change to display
Defects / Mura follow product specification
Luminance: Within +/-50% of initial value
Current consumption: within +/-50% of initial value
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C0240QGLA-T
11. Package:
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