Dell XPS M2010 Schematics

5

D D

4

3

2

1

Greenland

Napa

C C

REV : X03G
12/28/2005

@ : Nopop Component

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Cover Sheet

Greenland-LA2732P

163Wednesday, December 28, 2005

1

X03

http://hobi-elektronika.net

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Custom

Date: Sheet of

5

4

3

2

1

Compal confidential

Block Diagram

Pentium-M

D D

GUARDIAN II
EMC4000
/+2.5V

page 16

SMBus

Yonah

uFCPGA CPU

page 7,8,9

Clock Generator

CK410M

page 6

Fan Control

CRT CONN.

HA#(3..31)

& TV-OUT

page 20

VGA
Board

VGA CONN.

page 19

C C

PCI-E 16X

System Bus

FSB 533/667 MHz

INTEL

Calistoga

1466pin BGA

page 10,11,12,13,14,15

DMI

1.5V
100MHz

PCI BUS

IDSEL:AD17
(PIRQA/B#,GNT#2,REQ#2)

3.3V 33MHz

INTEL

ICH7-M

652pin BGA

CardBus Controller

B B

CF card

page35

A A

http://hobi-elektronika.net

page 23
page 36

page 31
page 36

5

RICHO R5C843

4-in-1 Conn

page34

Int.KBD

ST M25P80

ICH7M-Port1

Mini Card WLAN

WUSB

Mini Card TV

page 34,35

1394 Conn

page 39

page 37

USBPORT 0
USBPORT 1
USBPORT 2
USBPORT 3
USBPORT 4

SPI

page34

4

SPI

SMSC

MEC 5004

SMSC

ECE 5011

LPC BUS

3.3V 33MHz

page 37

BC BUS

page 38

21,22,23,24page

HD#(0..63)

PCI Express

48MHz / 480Mb

Memory

BUS(DDRII)

1.8V 533 / 667MHz

PORT1

PORT2

PORT4

PORT3

3.3V BitCLK

3.3V or 5V SATA

ATA100

Mini Card TV
Mini Card WLAN
Express card
LAN BCM5753

SATA

SO-DIMM X2

BANK 0, 1, 2, 3

page 36

page 36

page 40

page 32 page 33

page 17,18

USBPORT 4 of ECE5011

USBPORT 1 of ECE5011

USBPORT 2 of ICH7

RJ45 with Giga Magnetic

Azalia CODEC

STAC9220

page 26

CDROM

page 25

USB2.0

page 31

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

HDD X2

page 25

USBPORT 0
USBPORT 1
USBPORT 2
USBPORT 3
USBPORT 4
USBPORT 5
USBPORT 6
USBPORT 7

AMP &

Phone Jack

Blue Tooth

ECE USB[0]

Express Card

CIR
JUSB1
JUSB2
JUSB3
JUSB4

page 28

page 29
page 38
page 40
page 29
page 31
page 31
page 31
page 31

2

Azalia

Subwoofer

page 29

Power Control

Power Sequence

LED & PWR switch

DC IN

BATT IN

1.5V/1.05V(+VCCP)

MDC

page 29

5V/3.3V/12V

1.8V / 0.9V

VCORE

CHARGER

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Block Diagram

Greenland-LA2732P

1

page 16

page 42

page 43

page 41

page 45

page 46

page 47

page 48,49

page 50

page 51

page 52

263Wednesday, December 28, 2005

X03

of

5

4

3

2

1

PM TABLE

D D

power
plane

State

S0

S1

S3

C C

S5 S4/AC

S5 S4/AC don't exist

PCI EXPRESS

Lane 1
Lane 2

B B

Lane 3
Lane 4

+3VALW

ON

ON

ON

ON

+3VSUS
+5VSUS+5VALW
+1.8VSUS

DESTINATION
MINI CARD TV
MINI CARD WLAN
GIGA LAN
EXPRESS CARD

ON ON

ON

ON

OFF

OFFOFF

+12VRUN
+5VRUN
+3VRUN
+2.5VRUN
+1.8VRUN
+1.5VRUN
+VCC_CORE
+VCCP
+0.9V_DDR_VTT

ON

OFF

OFF

OFF

PCI TABLE

PCI DEVICE

CARD BUS

ICH7M USB TABLE
USB

PORT#

0
1
2
3
4
5
6
7

DESTINATION

BLUETOOTH
USB[0] of ECE5011
Express Card
CIR
JUSB1(M/B)
JUSB2(M/B)
JUSB3(USB/BD)
JUSB4(USB/BD)

IDSEL

AD17

REQ#/GNT# PIRQ

2

D,C

ECE5011 USB TABLE
USB

PORT#

0
1

DESTINATION

USB[1] of ICH7M

Mini Card WLAN

2

WUSB3

4

Mini Card TV

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Elec tronics, Inc.

Index and Config.

Greenland-LA2732P

363Wednesday, December 28, 2005

1

X03

http://hobi-elektronika.net

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet of

5

4

3

2

1

+5VALW

D D

ADAPTER

PWR_SRC

BATTERY

C C

MAX8734

SUS_ON

+5VSUS

Thermal: 6.3A
Peak: 8.4A
OCP: 10.5A

+3VALW

PL17, PL18

SI4825DT

L5973D

SUS_ON

+3VSRC

Thermal: 5A
Peak: 7.2A
OCP: 10.4A

SCL, SDA

RUN_ON

EN_KB_PRECHG_5V#

MAX8731

G_PWR_SRC

+VCHGR

+5V_Pre-charge

TPS51116 MAX8743 MAX1745

SUSPWROK_5V

+1.8VSUSP

Thermal: 8.2A
Peak: 9.7A
OCP: 12A

Thermal: 0.8A
Peak: 1A
OCP: 2.5~3A

RUN_ON

+0.9V_DDR_VTT

Thermal: 1.5A
Peak: 3A
OCP: 3.8A

RUN_ON

+1.5VRUNP

Thermal: 4.6A
Peak: 6.6A
OCP min: 6.7A

RUN_ON

+VCCP

Thermal: 4.5A
Peak: 6.4A
OCP min: 6.6A

+3.3VX

+12VALW_SLND

Thermal: 2.5A
Peak: 3.5A
OCP: 4.5A

ADP3207

RUNPWROK

+VCC_CORE

Thermal:
Peak: 44A
OCP: A

B B

SI3456DVSI4800DY

HDDC_EN#

+5VHDD

A A

MODC_EN#

+5VMOD

STS11NF30L

RUN_ON

+5VRUN

TPS793475

RUN_ON

+3VRUN

AUDIO_AVDD_ON

+VDDA

SI3456DV

STS11NF30L

SUS_ON

+3VSUS

PJP7

SI4435BDY

+1.5VRUN

RUNPWROK

+12RUN

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Power Rail
Greenland-LA2732P

463Wednesday, December 28, 2005

1

X03

of

http://hobi-elektronika.net

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

5

4

3

2

1

+3VSUS

2.2K 2.2K

ICH_SMBCLK

D D

ICH7M

C C

C22

ICH_SMBDATA

B22

+3VSUS

30 30

Mini Card

+3VALW

10K 10K

CLK_SMB

10

DAT_SMB +3VALW

9

TV

32

32 7 8

Mini Card

WLAN

Express
Card

7002

7002

8

7

GUARDIAN

+3VRUN

197 195 197 195

+3VRUN

2.2K 2.2K

CK_SCLK
CK_SDATA

16

CLK GEN.

17

DIMM1DIMM0

Device Address

+3VALW

DIM0 A0h

PBAT_SMBCLK

8

8.2K8.2K

100

3

ICH7M-SMBus

DIM1

CLK GEN.

A2h

D2h

PBAT_SMBDAT BATTERY+3VALW

7

SIO

B B

A A

http://hobi-elektronika.net

Macallan IV

5

SBAT_SMBCLK

112

SBAT_SMBDAT +3VALW VGA

111

DOCK_SMB_CLK

6

DOCK_SMB_DAT

5

+3VALW

8.2K8.2K

+5V_MEDIA

10K10K

4

Note. +5V_MEDIA is from
+5VRUN or +5VSUS

+5V_MEDIA

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

100

3

4

9

CHARGER

10

10

8

13

Media BTN BD

14

EC-SMBus

Mini WLAN

Express

GUARDIA N

Media BTN

VGA

Battery

Charger

h

h

5Eh

86h for Cypress
40h

98h

16h

12h

LED PWM C0h

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

2

Date: Sheet of

Compal Elec tronics, Inc.

SMBUS TOPOLOGY

Greenland-LA2732P

563Wednesday, December 28, 2005

1

X03

5

D
1

2

G

3

2N7002

ICH_SMBDATA23,36,40

D D

ICH_SMBCLK23,36,40

C C

FSC FSB FSA CPU

CLKSEL0 CLKSEL1 CLKSEL2

ICH_SMBDATA CK_SDATA

+3VRUN

ICH_SMBCLK

1

1

C540

2

2

4.7U_0805_6.3V6K~D

00
0
0
0
1
1
1

0

1

11

0

0

1

*

11

B B

A A

Table : ICS 9 54305AK / Silego SLG84450VTR

+3VRUN

12

R796
10K_0402_5%~D

FSA

12

R799
10K_0402_5%~D

@

+3VRUN

12

R471
10K_0402_5%~D

PCICLK4

12

R472
10K_0402_5%~D

@

http://hobi-elektronika.net

+3VRUN

S

+CK_VDD_48+CK_VDD_A

C529

0.047U_0402_16V4Z~D

R226

2.2K_0402_5%~D
Q53

D

S

1 3

2N7002_SOT23~D

G

2

2

G

2N7002_SOT23~D

1 3

D

S

Q52

1

C537

2

4.7U_0805_6.3V6K~D

1

2

SRC

MHz

MHz

100 33.30

266

1
0

0
1
0
0

133
200
166
333
100
400

100
100
100
100
100
100

RESERVED

12

C199

0.047U_0402_16V4Z~D

12

R227

2.2K_0402_5%~D

CK_SCLK

+CK_VDD_REF

PCI
MHz

33.3

33.3

33.3

33.3

33.3

33.3

CK_SDATA 17,18

CK_SCLK 17,18

1

C201

2

0.047U_0402_16V4Z~D

CPU_MCH_BSEL08,10
CPU_MCH_BSEL18,10

CPU_MCH_BSEL28,10

CLK_PCI_PCCARD34

27P_0402_50V8J~D

1 2

27P_0402_50V8J~D

1 2

CK_48M_CB34

CLK_ICH_48M23

CLK_PCI_SIO37

CLK_ICH_14M23

CK_33M_ICHPCI21

Note: Solder Thermal pad to GND minimun 9 GND VIA.

PCICLK4 = FCTSEL1

FCTSEL1 Pin 43 Pin 44 Pin 47 Pin 48

UMA

0 DOT96T DOT96C LCD100/96T LCD100/96C

Discrete

1 27MHz 27MHz SRC0_T SRC0_C

5

C220

C215

4

L46

1 2

BLM21PG600SN1D_0805~D

1

C520

2

L25

1 2

BLM21PG600SN1D_0805~D

0.1U_0402_16V4Z~D

Place crystal within
500 mils of CK410

CK_XTAL_IN

12

X3

14.31818MHz_20P_1BX14318CC1A~D

CK_XTAL_OUT

CK_48M_CB
CLK_ICH_48M
CPU_MCH_BSEL0
CPU_MCH_BSEL1

CPU_MCH_BSEL2

CLK_PCI_PCCARD
CLK_PCI_SIO

CLK_ICH_14M CK_14M

+3VRUN

4

+CK_VDD_MAIN2

R209 390_0402_5%~D
R875 15_0402_5%~D
R205 15_0402_5%~D
R795 8.2K_0402_5%~D

R534 8.2K_0402_5%~D

R221 33_0402_5%~D
R229 33_0402_5%~D

R223 33_0402_5%~D

R473 10K_0402_5%~D
R216 33_0402_5%~D

CLK_ENABLE#51

+CK_VDD_MAIN+3VRUN

1 2

R460 1_0603_5%~D

1 2

R459 2.2_0603_5%~D

1 2

12
12
12

12

12
12

12

12
12

1 2

R450 475_0402_1%~D

CK_XTAL_OUT_R

CLK_ENABLE#

CK_SCLK

CK_SDATA

3

2

C523
10U_0805_10V4Z~D

1

2

C551
10U_0805_10V4Z~D

1

U16

1

VDDSRC

49

VDDSRC

54

VDDSRC

65

VDDSRC

30

VDDPCI

36

VDDPCI

12

+CK_VDD_REF
+CK_VDD_48

FSA

FSC

PCICLK4
PCICLK3

PCICLKF0CK_33M_ICHPCI

CLKIREF

VDDCPU

18

VDDREF

40

VDD48

20

X1

19

X2

41

USB_48MHz/FSLA

45

FSLB/TEST_MODE

23

REF0/FSLC/TEST_SEL

34

PCICLK4/FCTSEL1

33

PCICLK3

32

PCICLK2

27

PCICLK1

22

REF1

43

DOTT_96MHz/27MHz

44

DOTC_96MHz/27MHz(SS)

37

ITP_EN/PCICLK_F0

39

Vtt_PwrGd#/PD

9

IREF

16

SMBCLK

17

SMBDAT

4

GNDSRC

15

GNDCPU

21

GNDREF

31

GNDPCI

35

GNDPCI

42

GND48

68

GNDSRC

73

THRM_PAD

74

THRM_PAD

75

THRM_PAD

76

THRM_PAD

SLG84450VTR_QFN72~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

1

C197

0.1U_0402_16V4Z~D

2

1

C217

0.1U_0402_16V4Z~D

2

R452

2.2_0603_5%~D

1 2

1

2

1

2

+CK_VDD_A

VDDA
GNDA

PCI_SRC_STOP#

CPU_STOP#

CPUT1
CPUC1

CPUT0
CPUC0

CPUT_ITP/SRCT10

CPUC_ITP/SRCC10

SRCT9
SRCC9

CLKREQ9#

SRCT8
SRCC8

CLKREQ8#

SRCT7
SRCC7

CLKREQ7#

SRCT6
SRCC6

CLKREQ6#

SRCT5
SRCC5

CLKREQ5#

SRCT4
SRCC4

CLKREQ4#

SRCT3
SRCC3

CLKREQ3#

SRCT2
SRCC2

CLKREQ2#

SRCT1
SRCC1

CLKREQ1#
LCD100/96/SRC0_T
LCD100/96/SRC0_C

C182

0.1U_0402_16V4Z~D

C204

0.1U_0402_16V4Z~D

7
8

H_STP_PCI#

25

H_STP_CPU#

24

CK_CPU1

11

CK_CPU1#

10

CK_CPU0

14

CK_CPU0#

13

CK_CPU_ITP

6

CK_CPU_ITP#

5

SRC9

3

SRC9#

2
72

SRC8

70

SRC8#

69
71

SRC7 CLK_PCIE_LOM

66

SRC7#

67

LOM_CLKREQ#

38

SRC6 CLK_PCIE_EXPR

63
64

EXPR_CARD_REQ#

62

SRC5

60

SRC5#

61

SATA_CLKREQ#

29

SRC4

58

SRC4# CLK_PCIE_ICH#

59
57

SRC3

55
56

MINI_CARD1_REQ#

28

SRC2

52
53

MINI_CARD2_REQ#

26
50
51
46
47
48

2

1

C187

0.1U_0402_16V4Z~D

2

1

2

Place near each pin
W>40 mil

Place near CK410M

H_STP_PCI# 23

H_STP_CPU# 23

1 2

R192 33_0402_5%~D

1 2

R188 33_0402_5%~D

1 2

R208 33_0402_5%~D

1 2

R204 33_0402_5%~D

1 2

R179 33_0402_5%~D

1 2

R174 33_0402_5%~D

1 2

R182 33_0402_5%~D

1 2

R176 33_0402_5%~D

1 2

R154 33_0402_5%~D

1 2

R149 33_0402_5%~D

1 2

R147 33_0402_5%~D

1 2

R140 33_0402_5%~D

1 2

R152 33_0402_5%~D

1 2

R146 33_0402_5%~D

1 2

R171 33_0402_5%~D

1 2

R165 33_0402_5%~D

1 2

R198 33_0402_5%~D

1 2

R189 33_0402_5%~D

1 2

R168 33_0402_5%~D

1 2

R159 33_0402_5%~D

1 2

R801 33_0402_5%~D

1 2

R802 33_0402_5%~D

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CK_ITP
CK_ITP#

CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

3GPLL_REQ#

CLK_PCIE_LOM#

LOM_CLKREQ#

CLK_PCIE_EXPR#SRC6#

EXPR_CARD_REQ# 40
CLK_PCIE_SATA
CLK_PCIE_SATA#

SATA_CLKREQ# 23
CLK_PCIE_ICH

CLK_PCIE_M INI_CARD1
CLK_PCIE_MI NI_CARD1#SRC3#

MINI_CARD1_REQ# 36

CLK_PCIE_M INI_CARD2
CLK_PCIE_MI NI_CARD2#SRC2#

MINI_CARD2_REQ# 36

2

1

CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CK_ITP
CK_ITP#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_LOM
CLK_PCIE_LOM#
CLK_PCIE_EXPR

CLK_PCIE_EXPR#
CLK_PCIE_M INI_CARD2
CLK_PCIE_MI NI_CARD2#
CLK_PCIE_M INI_CARD1
CLK_PCIE_MI NI_CARD1#

3GPLL_REQ#
EXPR_CARD_REQ#
SATA_CLKREQ#
MINI_CARD1_REQ#
MINI_CARD2_REQ#
LOM_CLKREQ#

1 2

10K_0402_5%~D

1 2

10K_0402_5%~D

1 2

10K_0402_5%~D

1 2

10K_0402_5%~D

1 2

10K_0402_5%~D

1 2

10K_0402_5%~D

C522

0.1U_0402_16V4Z~D

CLK_MCH_BCLK 10
CLK_MCH_BCLK# 10

CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7

CK_ITP 7
CK_ITP# 7

1

C954

0.1U_0402_16V4Z~D

2

CLK_PCIE_VGA 19

CLK_PCIE_VGA# 19

CLK_MCH_3GPLL 10

CLK_MCH_3GPLL# 10

3GPLL_REQ# 10

CLK_PCIE_LOM 32

CLK_PCIE_LOM# 32

CLK_PCIE_EXPR 40

CLK_PCIE_EXPR# 40

CLK_PCIE_SATA 22
CLK_PCIE_SATA# 22

CLK_PCIE_ICH 23
CLK_PCIE_ICH# 23

CLK_PCIE_MI N I_CARD1 36

CLK_PCIE_MI N I_CARD1# 36

CLK_PCIE_MI N I_CARD2 36

CLK_PCIE_MI N I_CARD2# 36

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.
Clock Generator

Greenland-LA2732P

1

49.9_0402_1%~D

49.9_0402_1%~D

49.9_0402_1%~D

49.9_0402_1%~D

49.9_0402_1%~D

49.9_0402_1%~D

1 2

49.9_0402_1%~D

1 2

49.9_0402_1%~D

1 2

49.9_0402_1%~D

1 2

49.9_0402_1%~D

1 2

49.9_0402_1%~D

1 2

49.9_0402_1%~D

1 2

49.9_0402_1%~D

1 2

49.9_0402_1%~D

1 2

49.9_0402_1%~D

1 2

49.9_0402_1%~D

1 2

49.9_0402_1%~D

1 2

49.9_0402_1%~D

1 2

49.9_0402_1%~D

1 2

49.9_0402_1%~D

1 2

49.9_0402_1%~D

1 2

49.9_0402_1%~D

R728
R539
R829
R538
R800
R890

663Wednesday, December 28, 2005

R191
R187
R207
R203
R178
R173

R148
R141

R822
R823
R167
R158

12
12
12
12
12

12

R172
R166
R199
R190
R155
R150
R183
R177

R151
R145

+3VRUN
+3VRUN
+3VRUN
+3VRUN
+3VRUN
+3VRUN

X03

of

5

4

3

2

1

H_A#[3..31]10

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

D D

H_REQ#[0..4]10

H_ADSTB#010

C C

R584

56_0402_5%~D

1 2

+VCCP

B B

Stuff R840 for
Yonah B0 and
forward, no stuff
for A1

R901 1K_0402_5%~D @

1 2

R840 51_0402_5%~D

1 2

H_THERMDA16

H_THERMDC16

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

A A

H_ADSTB#110

CLK_CPU_BCLK6
CLK_CPU_BCLK#6

H_ADS#10

H_BNR#10

H_BPRI#10

H_BR0#10

H_DEFER#10

H_DRDY#10
H_HIT#10
H_HITM#10

H_LOCK#10

H_RS#[0..2]10

2200P_0402_50V7K~D@

H_RESET#10

H_TRDY#10

ITP_DBRESET#23,37

H_DBSY#10

H_DPSLP#22
H_DPRSTP#22,51

H_DPWR#10

CPU_PROCHOT#38

H_PWRGOOD22

H_CPUSLP#10,22

1

C746

2

H_THERMTRIP#16

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22

H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5

CPU_PROCHOT#

H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC

H_THERMTRIP#

JCPU1A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

BCLK1

H1

ADS#

E2

BNR#

G5

BPRI#

F1

BR0#

H5

DEFER#

F21

DRDY#

G6

HIT#

E4

HITM#

D20

IERR#

H4

LOCK#

B1

RESET#

F3

RS0#

F4

RS1#

G3

RS2#

G2

TRDY#

AD4

BPM0#

AD3

BPM1#

AD1

BPM2#

AC4

BPM3#

C20

DBR#

E1

DBSY#

B5

DPSLP#

E5

DPRSTP#

D24

DPWR#

AC2

PRDY#

AC1

PREQ#

D21

PROCHOT#

D6

PWRGOOD

D7

SLP#

AC5

TCK

AA6

TDI

AB3

TDO

C26

TEST1

D25

TEST2

AB5

TMS

AB6

TRST#

A24

THERMDA

A25

THERMDC

C7

THERMTRIP#

FOX_PZ47903-2741-42_YONAH~D

YONAH

ADDR GROUP

HOST CLK

CONTROL

MISC

THERMAL
DIODE

DATA GROUP

LEGACY CPU

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#

D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#

LINT0
LINT1

STPCLK#

SMI#

E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26

J26
M26
V23
AC20

H23
M24
W24
AD23
G22
N25
Y25
AE24

A6
A5
C4
B3
C6
B4

D5
A3

H_D#0H_A#3
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20H_A#23
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#
H_SMI#

H_DINV#0 10
H_DINV#1 10
H_DINV#2 10
H_DINV#3 10

H_A20M# 22

H_FERR# 22

H_IGNNE# 22

H_INIT# 22

H_INTR 22

H_NMI 22

H_STPCLK# 22

H_SMI# 22

H_RESET#

ITP_TDO

H_D#[0..63] 10

R578

22.6_0402_1%~D

1 2

R579

22.6_0402_1%~D

1 2

H_DSTBN#[0..3] 10

H_DSTBP#[0..3] 10

+VCCP

ITP_DBRESET#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
CK_ITP

CK_ITP6

CK_ITP#

CK_ITP#6

ITP_TDO_R
ITP_TCK

ITP_TRST#

ITP_TMS
ITP_TDI

Check ITP connector.

+3VSUS

R575

+VCCP

150_0402_1%~D

1 2

R576

51_0402_5%~D

1 2

R577

51_0402_5%~D

1 2

R839

@

54.9_0402_1%~D

1 2

R581

39_0402_5%~D

1 2

R580

150_0402_5%~D

1 2

R583

680_0402_5%~D

1 2

R582

27_0402_5%~D

1 2

C956

0.1U_0402_16V4Z~D

ITP_DBRESET#

ITP_TDO_R

H_RESET#

ITP_BPM#5

ITP_TMS

ITP_TDI

This shall place near CPU

ITP_TRST#

This shall place near CPU

ITP_TCK

+VCCP

1

1

C686

2

2

0.1U_0402_16V4Z~D

29

JITP1

29

28

VTT1

27

VTT0

26

VTAP

25

DBR#

24

DBA#

23

BPM0#

22

GND5

21

BPM1#

20

GND4

19

BPM2#

18

GND3

17

BPM3#

16

GND2

15

BPM4#

14

GND1

13

BPM5#

12

RESET#

11

FBO

10

GND0

9

BCLKP

8

BCLKN

7

TDO

6

NC2

5

TCK

4

NC1

3

TRST#

2

TMS

1

TDI

30

MOLEX_52435-2891_28P~D@

30

Place near JITP1

R585

+VCCP

+VCCP

56_0402_5%~D

1 2

R781
75_0402_5%~D

1 2

H_THERMTRIP#

CPU_PROCHOT#

C746 close to CPU

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.
Yonah in mFCPGA479

Greenland-LA2732P

763Wednesday, December 28, 2005

1

X03

of

http://hobi-elektronika.net

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

5

4

3

2

1

Length match within 25 mils

R586

VCCSENSE51
VSSSENSE51

D D

+VCCP

R_A

12

V_CPU_GTLREF

R589
1K_0402_1%~D

R_B

12

R588
2K_0402_1%~D

Layout close CPU PIN AD26

+VCC_CORE

R590
100_0402_1%~D

1 2

R591
100_0402_1%~D

1 2

Layout close CPU

VCCSENSE

VSSSENSE

VCCSENSE
VSSSENSE VSSSENSE_R

+1.5VRUN

1

C688

2

10U_0805_10V4Z~D

C687
Layout close CPU PIN B26

0.5 inch (max)

C C

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25

12

12

R592

R593

27.4_0402_1%~D

B B

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

00

0

12

12

R594

27.4_0402_1%~D

54.9_0402_1%~D

mils away from any
other toggling signal.

R595

54.9_0402_1%~D

CPU_BSEL0

1

1

1

0_0402_5%~D

1 2
1 2

R587

0_0402_5%~D

1

C687

2

0.01U_0402_16V7K~D

H_PSI#51

VID051

VID151

VID251

VID351

VID451

VID551

VID651

V_CPU_GTLREF

CPU_MCH_BSEL06,10
CPU_MCH_BSEL16,10
CPU_MCH_BSEL26,10

+VCCP

+VCC_CORE

VCCSENSE_R

H_PSI#

VID0
VID1
VID2
VID3
VID4
VID5
VID6

CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2

COMP0
COMP1
COMP2
COMP3

JCPU1B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

YONAH

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

PSI#
VID0

VID1
VID2
VID3
VID4
VID5
VID6

GTLREF
BSEL0

BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

FOX_PZ47903-2741-42_YONAH~D

M21

W21

AD6

AD26

AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17

T6
R6

K21

J21

N21
T21
R21
V21

V6

G21

AE6

AF5
AE5
AF4
AE3
AF2
AE2

B22
B23
C21

R26
U26

U1
V1

E7

D2
F6
D3

C1
AF1
D22
C23
C24
AA1
AA4
AB2
AA3

M4

N5

T2

V3

B2

C3
T22
B25

AB26

VSS

AA25

VSS

AD25

VSS

AE26

VSS

AB23

VSS

AC24

VSS

AF24

VSS

AE23

VSS

AA22

VSS

AD22

VSS

AC21

VSS

AF21

VSS

AB19

VSS

AA19

VSS

AD19

VSS

AC19

VSS

AF19

VSS

AE19

VSS

AB16

VSS

AA16

VSS

AD16

VSS

AC16

VSS

AF16

VSS

AE16

VSS

AB13

VSS

AA14

VSS

AD13

VSS

AC14

VSS

AF13

VSS

AE14

VSS

AB11

VSS

AA11

VSS

AD11

VSS

AC11

VSS

AF11

VSS

AE11

VSS

AB8

VSS

AA8

VSS

AD8

VSS

AC8

VSS

AF8

VSS

AE8

VSS

AA5

VSS

AD5

VSS

AC6

VSS

AF6

VSS

AB4

VSS

AC3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

POWER, GROUNG, RESERVED SIGNALS AND NC

+VCC_CORE

JCPU1C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

AD12
AC12
AF12
AE12
AB10

AA10
AD10
AC10
AF10
AE10

AB9
AA9
AD9
AC9
AF9
AE9

AB7
AA7
AD7
AC7
B20
A20
F20
E20
B18
B17
A18
A17
D18
D17
C18
C17
F18
F17
E18
E17
B15
A15
D15
C15
F15
E15
B14
A13
D14
C13
F14
E13
B12
A12
D12
C12
F12
E12
B10

B9

A10

A9

D10

D9

C10

C9

F10

F9

E10

E9
B7
A7
F7

YONAH

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

POWER, GROUND

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

FOX_PZ47903-2741-42_YONAH~D

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Yonah in mFCPGA479

Greenland-LA2732P

863Wednesday, December 28, 2005

1

X03

of

http://hobi-elektronika.net

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

5

+VCC_CORE

Place these inside
socket cavity on L8
(North side

D D

C C

Secondary)

Place these inside
socket cavity on L8
(Sorth side
Secondary)

Place these inside
socket cavity on L8
(North side
Primary)

Place these inside
socket cavity on L8
(Sorth side
Primary)

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C689
10U_0805_4VAM~D

C699
10U_0805_4VAM~D

C709
10U_0805_4VAM~D

C715
10U_0805_4VAM~D

1

C690
10U_0805_4VAM~D

2

1

C700
10U_0805_4VAM~D

2

1

C710
10U_0805_4VAM~D

2

1

C716
10U_0805_4VAM~D

2

1

C691
10U_0805_4VAM~D

2

1

C701
10U_0805_4VAM~D

2

1

C711
10U_0805_4VAM~D

2

1

C717
10U_0805_4VAM~D

2

4

1

C692
10U_0805_4VAM~D

2

1

C702
10U_0805_4VAM~D

2

1

C712
10U_0805_4VAM~D

2

1

C718
10U_0805_4VAM~D

2

1

C693
10U_0805_4VAM~D

2

1

C703
10U_0805_4VAM~D

2

1

C713
10U_0805_4VAM~D

2

1

C719
10U_0805_4VAM~D

2

1

C694
10U_0805_4VAM~D

2

1

C704
10U_0805_4VAM~D

2

1

C714
10U_0805_4VAM~D

2

1

C720
10U_0805_4VAM~D

2

1

C695
10U_0805_4VAM~D

2

1

C705
10U_0805_4VAM~D

2

10uF 0805 X6S

3

1

C696
10U_0805_4VAM~D

2

1

C706
10U_0805_4VAM~D

2

1

C697
10U_0805_4VAM~D

2

1

C707
10U_0805_4VAM~D

2

1

C698
10U_0805_4VAM~D

2

1

C708
10U_0805_4VAM~D

2

2

1

High Frequence Decoupling

Near VCORE regulator.

+VCC_CORE

South Side Secondary

C721

@

B B

+VCCP

1

+

C727

@

2

330U_D2E_2.5VM~D

CRB was 270uF

A A

330U_D_2VM_R6~D

6mOhm
PS CAP

1

+

C722

2

330U_D_2VM_R6~D

6mOhm
PS CAP

1

C728

0.1U_0402_10V7K~D

2

1

+

C723

2

330U_D_2VM_R6~D

6mOhm
PS CAP

1

2

1

1

+

C724

2

2

330U_D_2VM_R6~D

6mOhm
PS CAP

C729

0.1U_0402_10V7K~D

+

1

+

C725

2

@

330U_D_2VM_R6~D

6mOhm
PS CAP

1

C730

0.1U_0402_10V7K~D

2

North Side Secondary

1

+

C726

2

330U_D_2VM_R6~D

6mOhm
PS CAP

1

2

C731

0.1U_0402_10V7K~D

1

C732

0.1U_0402_10V7K~D

2

ESR <= 1.5m ohm

1

C733

0.1U_0402_10V7K~D

2

Place these inside
socket cavity on L8
(North side
Secondary)

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

CPU Bypass

Greenland-LA2732P

963Wednesday, December 28, 2005

1

X03

of

http://hobi-elektronika.net

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

5

4

3

2

1

+VCCP

12

R596

H_SWNG1

221_0402_1%~D

+VCCP

+VCCP

R605

12

1

R597

2

C734

100_0402_1%~D

0.1U_0402_16V4Z~D

12

R598

H_SWNG0

221_0402_1%~D

12

1

R599

2

100_0402_1%~D

12

100_0402_1%~D

12

200_0402_1%~D

C735

0.1U_0402_16V4Z~D

R600

H_VREF

1

C736

2

DPRSLPVR23,51

PLTRST2#21,32,37

+1.8VSUS

0.1U_0402_16V4Z~D

R841
0_0402_5%~D

R606

100_0402_1%~D

V_DDR_MCH_REF17,18,50

DMI_MRX_ITX_N023
DMI_MRX_ITX_N123
DMI_MRX_ITX_N223
DMI_MRX_ITX_N323

DMI_MRX_ITX_P023
DMI_MRX_ITX_P123
DMI_MRX_ITX_P223
DMI_MRX_ITX_P323

DMI_MTX_IRX_N023
DMI_MTX_IRX_N123
DMI_MTX_IRX_N223
DMI_MTX_IRX_N323

DMI_MTX_IRX_P023
DMI_MTX_IRX_P123
DMI_MTX_IRX_P223
DMI_MTX_IRX_P323

M_CLK_DDR018
M_CLK_DDR118
M_CLK_DDR217
M_CLK_DDR317

M_CLK_DDR#018
M_CLK_DDR#118
M_CLK_DDR#217
M_CLK_DDR#317

DDR_CKE0_DIMMA18
DDR_CKE1_DIMMA18
DDR_CKE2_DIMMB17
DDR_CKE3_DIMMB17

DDR_CS0_DIMMA#18
DDR_CS1_DIMMA#18
DDR_CS2_DIMMB#17
DDR_CS3_DIMMB#17

T33 PAD~D
T36 PAD~D

R602 80.6_0402_1%~D

1 2

R601 80.6_0402_1%~D

1 2

PM_BMBUSY#23

12

12

V_DDR_MCH_REF

PM_EXTTS#018

THERMTRIP_MCH#16

ICH_PWRGD23,43

MCH_ICH_SYNC#21

C737

@

M_ODT018
M_ODT118
M_ODT217
M_ODT317

1

2

0.1U_0402_16V4Z~D

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDCOMP0
M_OCDCOMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

V_DDR_MCH_REF

PM_BMBUSY#
PM_E XTTS#0
PM_E XTTS#1
THERMTRIP_MCH#
ICH_PWRGD
PLTRST2#_R#

MCH_ICH_SYNC#

1

C738

2

@

0.1U_0402_16V4Z~D

D D

H_D#[0..63]7

C C

+VCCP

12

12

B B

R603

R604

54.9_0402_1%~D

54.9_0402_1%~D

12

12

R607

24.9_0402_1%~D

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8

H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60

H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

R608

24.9_0402_1%~D

U39A

F1

HD0#

J1

HD1#

H1

HD2#

J6

HD3#

H3

HD4#

K2

HD5#

G1

HD6#

G2

HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#

H4

HD12#

J3

HD13#

K11

HD14#

G4

HD15#

T10

HD16#

W11

HD17#

T3

HD18#

U7

HD19#

U9

HD20#

U11

HD21#

T11

HD22#

W9

HD23#

T1

HD24#

T8

HD25#

T4

HD26#

W7

HD27#

U5

HD28#

T9

HD29#

W6

HD30#

T5

HD31#

AB7

HD32#

AA9

HD33#

W4

HD34#

W3

HD35#

Y3

HD36#

Y7

HD37#

W5

HD38#

Y10

HD39#

AB8

HD40#

W2

HD41#

AA4

HD42#

AA7

HD43#

AA2

HD44#

AA6

HD45#

AA10

HD46#

Y8

HD47#

AA1

HD48#

AB4

HD49#

AC9

HD50#

AB11

HD51#

AC11

HD52#

AB3

HD53#

AC2

HD54#

AD1

HD55#

AD9

HD56#

AC1

HD57#

AD7

HD58#

AC6

HD59#

AB5

HD60#

AD10

HD61#

AD4

HD62#

AC8

HD63#

J13

HVREF0

K13

HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP

U1

HYSCOMP

E4

HXSWING

W1

HYSWING

CALISTOGA A0_FCBGA1466~D

H9

HA3#

C9

HA4#

E11

HA5#

G11

HA6#

F11

HA7#

G12

HA8#

F9

HA9#

H11

HA10#

J12

HA11#

G14

HA12#

D9

HA13#

J14

HA14#

H13

HA15#

J15

HA16#

F14

HA17#

D12

HA18#

A11

HA19#

C11

HA20#

A12

HA21#

A13

HA22#

E13

HA23#

G13

HA24#

F12

HA25#

B12

HA26#

B14

HA27#

C12

HA28#

A14

HA29#

C14

HA30#

D14

HA31#

D8

HREQ#0

G8

HREQ#1

B8

HREQ#2

F8

HREQ#3

A8

HREQ#4

B9

HADSTB#0

C13

HADSTB#1

HCLKN

HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#
HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

AG1
AG2

K4
T7
Y5
AC4
K3
T6
AA5
AC5

J7
W8
U3
AB10

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

B4
E6
D6

HOST

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

H_A#[3..31] 7

H_ADSTB#0 7
H_ADSTB#1 7

CLK_MCH_BCLK# 6

CLK_MCH_BCLK 6

H_DSTBN#[0..3] 7

H_DSTBP#[0..3] 7

H_DINV#0 7
H_DINV#1 7
H_DINV#2 7
H_DINV#3 7

H_RESET# 7

H_ADS# 7

H_TRDY# 7
H_DPWR# 7
H_DRDY# 7

H_DEFER# 7

H_HITM# 7
H_HIT# 7
H_LOCK# 7

H_BR0# 7
H_BNR# 7
H_BPRI# 7

H_DBSY# 7
H_CPUSLP# 7,22

H_RS#[0..2] 7

H_REQ#[0..4] 7

U39B

AE35

DMIRXN0

AF39

DMIRXN1

AG35

DMIRXN2

AH39

DMIRXN3

AC35

DMIRXP0

AE39

DMIRXP1

AF35

DMIRXP2

AG39

DMIRXP3

AE37

DMITXN0

AF41

DMITXN1

AG37

DMITXN2

AH41

DMITXN3

AC37

DMITXP0

AE41

DMITXP1

AF37

DMITXP2

AG41

DMITXP3

AY35

SM_CK0

AR1

SM_CK1

AW7

SM_CK2

AW40

SM_CK3

AW35

SM_CK0#

AT1

SM_CK1#

AY7

SM_CK2#

AY40

SM_CK3#

AU20

SM_CKE0

AT20

SM_CKE1

BA29

SM_CKE2

AY29

SM_CKE3

AW13

SM_CS0#

AW12

SM_CS1#

AY21

SM_CS2#

AW21

SM_CS3#

AL20

SM_OCDCOMP0

AF10

SM_OCDCOMP1

BA13

SM_ODT0

BA12

SM_ODT1

AY20

SM_ODT2

AU21

SM_ODT3

AV9

SM_RCOMPN

AT9

SM_RCOMPP

AK1

SM_VREF0

AK41

SM_VREF1

G28

PM_BMBUSY#

F25

PM_EXTTS0#

H26

PM_EXTTS1#

G6

PM_THERMTRIP#

AH33

PWROK

AH34

RSTIN#

K28

ICH_SYNC#

CALISTOGA A0_FCBGA1466~D

Description at page12

Note :
CFG3:17 has
internal pullup,
CFG18:19 has
internal pulldown

DMI

DDR MUXING

PM

CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

CFG

CFG18
CFG19
CFG20

G_CLKP
G_CLKN

D_REF_CLKN
D_REF_CLKP

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

CLK_REQ#

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

RESERVED

PM_EXTTS#0

PM_EXTTS#1

THERMTRIP_MCH#

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

CPU_MCH_BSEL0

K16

CPU_MCH_BSEL1

K18

CPU_MCH_BSEL2

J18

CFG3

F18

CFG4

E15

CFG5

F15

CFG6

E18

CFG7

D19

CFG8

D16

CFG9

G16

CFG10

E16

CFG11

D15

CFG12

G15

CFG13

K15

CFG14

C15

CFG15

H16

CFG16

G18

CFG17

H15

CFG18

J25

CFG19

K27

CFG20

J26

AG33
AF33

A27
A26

C40
D41

H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

10K_0402_5%~D

10K_0402_5%~D@

1 2

+1.5VRUN

R609

12

R610

12

R613
75_0402_5%~D

CPU_MCH_BSEL0 6,8
CPU_MCH_BSEL1 6,8
CPU_MCH_BSEL2 6,8

T26PAD~D

T31PAD~D

CFG5 12
CFG6 12
CFG7 12

T32PAD~D

CFG9 12
CFG10 12
CFG11 12
CFG12 12
CFG13 12

T29PAD~D

T28PAD~D

CFG16 12

T30PAD~D

CFG18 12
CFG19 12
CFG20 12

CLK_MCH_3GPLL 6

CLK_MCH_3GPLL# 6

3GPLL_REQ# 6

+3VRUN

+VCCP

close to AK1, AK41

A A

Layout Note:
H_XRCOMP & H_YRCOMP trace width
and spacing is 10/20

http://hobi-elektronika.net

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Calistoga(1 of 6)

Greenland-LA2732P

10 63W ed nes da y, De ce mber 28, 2005

1

of

X03

5

D D

4

3

2

1

U39D

DDR_A_BS018
DDR_A_BS118
DDR_A_BS218 DDR_B_BS217

DDR_A_DM[0..7]18

DDR_A_DQS[0..7]18

C C

B B

DDR_A_DQS#[0..7]18

DDR_A_MA[0..13]18

DDR_A_CAS#18
DDR_A_RAS#18
DDR_A_WE#18

PAD~D

T40

PAD~D

T42

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5

DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11 DDR_B_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

CALISTOGA A0 _ FCBGA1466~D

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR SYS MEMORY A

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

PAD~D
PAD~D

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6DDR_A_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10

DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

DDR_B_BS017
DDR_B_BS117

DDR_B_DM[0..7]17

DDR_B_DQS[0..7]17

DDR_B_DQS#[0..7]17

DDR_B_MA[0..13]17

DDR_B_CAS#17
DDR_B_RAS#17
DDR_B_WE#17

T41
T43

U39E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA A0 _ FCBGA1466~D

AK39

SB_DQ0

AJ37

SB_DQ1

AP39

SB_DQ2

AR41

SB_DQ3

AJ38

SB_DQ4

AK38

SB_DQ5

AN41

SB_DQ6

AP41

SB_DQ7

AT40

SB_DQ8

AV41

SB_DQ9

AU38

SB_DQ10

AV38

SB_DQ11

AP38

SB_DQ12

AR40

SB_DQ13

AW38

SB_DQ14

AY38

SB_DQ15

BA38

SB_DQ16

AV36

SB_DQ17

AR36

SB_DQ18

AP36

SB_DQ19

BA36

SB_DQ20

AU36

SB_DQ21

AP35

SB_DQ22

AP34

SB_DQ23

AY33

SB_DQ24

BA33

SB_DQ25

AT31

SB_DQ26

AU29

SB_DQ27

AU31

SB_DQ28

AW31

SB_DQ29

AV29

SB_DQ30

AW29

SB_DQ31

AM19

SB_DQ32

AL19

SB_DQ33

AP14

SB_DQ34

AN14

SB_DQ35

AN17

SB_DQ36

AM16

SB_DQ37

AP15

SB_DQ38

AL15

SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR SYS MEMORY B

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D[0..63] 17DDR_A_D[0..63] 18

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Calistogo(2 of 6)

Greenland-LA2732P

11 63W ed nes da y, De ce mber 28, 2005

1

X03

of

http://hobi-elektronika.net

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

5

D D

4

3

2

1

Strap Pin Table

T44 PAD~D

C C

B B

SDVOCTRL_DATA

+1.5VRUN

+VCCP

U39C

H27

SDVOCTRL_DATA

H28

SDVOCTRL_CLK

B37

LA_DATA0

B34

LA_DATA1

A36

LA_DATA2

C37

LA_DATA#0

B35

LA_DATA#1

A37

LA_DATA#2

F30

LB_DATA0

D29

LB_DATA1

F28

LB_DATA2

G30

LB_DATA#0

D30

LB_DATA#1

F29

LB_DATA#2

A32

LA_CLK

A33

LA_CLK#

E26

LB_CLK

E27

LB_CLK#

D32

LBKLT_CTL

J30

LBKLT_EN

H30

LCTLA_CLK

H29

LCTLB_DATA

G26

LDDC_CLK

G25

LDDC_DATA

F32

LVDD_EN

B38

LIBG

C35

LVBG

C33

LVREFH

C32

LVREFL

A16

TVDAC_A

C18

TVDAC_B

A19

TVDAC_C

J20

TV_IREF

B16

TV_IRTNA

B18

TV_IRTNB

B19

TV_IRTNC

J29

TV_DCONSEL1

K30

TV_DCONSEL0

C26

DDCCLK

C25

DDCDATA

H23

VSYNC

G23

HSYNC

E23

BLUE

D23

BLUE#

C22

GREEN

B22

GREEN#

A21

RED

B21

RED#

J22

CRT_IREF

CALISTOGA A0 _ FCBGA1466~D

EXP_COMPI

EXP_COMPO

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7

LVDS

TV CRT

EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

PCI-EXPRESS GRAPHICS

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D40
D38

PCIE_MRX_GTX_N0

F34

PCIE_MRX_GTX_N1

G38

PCIE_MRX_GTX_N2

H34

PCIE_MRX_GTX_N3

J38

PCIE_MRX_GTX_N4

L34

PCIE_MRX_GTX_N5

M38

PCIE_MRX_GTX_N6

N34

PCIE_MRX_GTX_N7

P38

PCIE_MRX_GTX_N8

R34

PCIE_MRX_GTX_N9

T38

PCIE_MRX_GTX_N10

V34

PCIE_MRX_GTX_N11

W38

PCIE_MRX_GTX_N12

Y34

PCIE_MRX_GTX_N13

AA38

PCIE_MRX_GTX_N14

AB34

PCIE_MRX_GTX_N15

AC38

PCIE_MRX_GTX_P0

D34

PCIE_MRX_GTX_P1

F38

PCIE_MRX_GTX_P2

G34

PCIE_MRX_GTX_P3

H38

PCIE_MRX_GTX_P4

J34

PCIE_MRX_GTX_P5

L38

PCIE_MRX_GTX_P6

M34

PCIE_MRX_GTX_P7

N38

PCIE_MRX_GTX_P8

P34

PCIE_MRX_GTX_P9

R38

PCIE_MRX_GTX_P10

T34

PCIE_MRX_GTX_P11

V38

PCIE_MRX_GTX_P12

W34

PCIE_MRX_GTX_P13

Y38

PCIE_MRX_GTX_P14

AA34

PCIE_MRX_GTX_P15

AB38

PCIE_MTX_GRX_N0

F36

PCIE_MTX_GRX_N1

G40

PCIE_MTX_GRX_N2

H36

PCIE_MTX_GRX_N3

J40

PCIE_MTX_GRX_N4

L36

PCIE_MTX_GRX_N5

M40

PCIE_MTX_GRX_N6

N36

PCIE_MTX_GRX_N7

P40

PCIE_MTX_GRX_N8

R36

PCIE_MTX_GRX_N9

T40

PCIE_MTX_GRX_N10

V36

PCIE_MTX_GRX_N11

W40

PCIE_MTX_GRX_N12

Y36

PCIE_MTX_GRX_N13

AA40

PCIE_MTX_GRX_N14

AB36

PCIE_MTX_GRX_N15

AC40

PCIE_MTX_GRX_P0

D36

PCIE_MTX_GRX_P1

F40

PCIE_MTX_GRX_P2

G36

PCIE_MTX_GRX_P3

H40

PCIE_MTX_GRX_P4

J36

PCIE_MTX_GRX_P5

L40

PCIE_MTX_GRX_P6

M36

PCIE_MTX_GRX_P7

N40

PCIE_MTX_GRX_P8

P36

PCIE_MTX_GRX_P9

R40

PCIE_MTX_GRX_P10

T36

PCIE_MTX_GRX_P11

V40

PCIE_MTX_GRX_P12

W36

PCIE_MTX_GRX_P13

Y40

PCIE_MTX_GRX_P14

AA36

PCIE_MTX_GRX_P15

AB40

PEGCOMP

R615

24.9_0402_1%~D

1 2

+1.5VRUN_PCIE

PCIE_MRX_GTX_N[0..15]

PCIE_MRX_GTX_P[0..15]

PCIE_MTX_GRX_N[0..15]

PCIE_MTX_GRX_P[0..15]

PCIE_MRX_GTX_N[0..15] 19

PCIE_MRX_GTX_P[0..15] 19

PCIE_MTX_GRX_N[0..15] 19

PCIE_MTX_GRX_P[0..15] 19

CFG5

CFG6

CFG7

CFG9

CFG10

CFG11

CFG[13:12]

CFG16

(FSB Dynamic ODT)

CFG18

(VCC Select)

CFG19

(DMI Lane Reversal)

SDVO_CTRLDATA

CFG20

(PCIE/SDVO select)

Low = DMI x 2
High = DMI x 4
Low = Moby Dick
High = Calistoga
Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane
High = Normal Operation

*

*

*

*

Low = Reserved
High = Mobility

PSB 4x Clock Enable
Low = Calistoga
High = Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

(Default)

*

*

*

Low = Disabled
High = Enabled

Low = 1.05V (Default)
High = 1.5V
Low = Normal

Operation (Default):
Lane number in Order

*

*

*

High = Reverse Lane

Low = No SDVO Device Present
High = SDVO Device Present

Low = Only PCIE or SDVO is
operational.

High = PCIE/SDVO are operating
simu.

(Default)

(Default)

*

*

R617 2.2K_0402_5%~D@

CFG510
CFG610
CFG710
CFG910
CFG1010
CFG1110
CFG1210
CFG1310
CFG1610

1 2

R622 2.2K_0402_5%~D@

1 2

R625 2.2K_0402_5%~D@

1 2

R618 2.2K_0402_5%~D@

1 2

R624 2.2K_0402_5%~D@

1 2

R619 2.2K_0402_5%~D@

1 2

R626 2.2K_0402_5%~D@

1 2

R620 2.2K_0402_5%~D@

1 2

R621 2.2K_0402_5%~D@

1 2

CFG[3:17] have internal pullup

R623 1K_0402_5%~D@

CFG1810
CFG1910
CFG2010

1 2

R627 1K_0402_5%~D@

1 2

R628 1K_0402_5%~D@

1 2

CFG[18:19] have internal pulldown

+3VRUN

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Calistoga(3 of 6)

Greenland-LA2732P

12 63W ed nes da y, De ce mber 28, 2005

1

X03

of

http://hobi-elektronika.net

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

5

4

3

2

1

+VCCP

D D

CRB 270uF

1

+

C747

2

330U_D2E_2.5VM~D

C C

B B

A A

1

C754

C755

2

4.7U_0805_10V4Z~D

2.2U_0603_6.3V6K~D

C763

0.47U_0402_10V4Z~D

1

C772

2

1

C773

0.22U_0402_10V4Z~D

2

0.22U_0402_10V4Z~D

+1.5VRUN

1

2

U39_A6

1

2

U39_D2

U39_AB1

1

C775

2

0.47U_0402_10V4Z~D

U39H

AC14

VTT0

AB14

VTT1

W14

VTT2

V14

VTT3

T14

VTT4

R14

VTT5

P14

VTT6

N14

VTT7

M14

VTT8

L14

VTT9

AD13

VTT10

AC13

VTT11

AB13

VTT12

AA13

VTT13

Y13

VTT14

W13

VTT15

V13

VTT16

U13

VTT17

T13

VTT18

R13

VTT19

N13

VTT20

M13

VTT21

L13

VTT22

AB12

VTT23

AA12

VTT24

Y12

VTT25

W12

VTT26

V12

VTT27

U12

VTT28

T12

VTT29

R12

VTT30

P12

VTT31

N12

VTT32

M12

L12
R11
P11
N11

M11

R10
P10
N10

M10

AB1

AG14
AF14
AE14

Y14
AF13
AE13
AF12
AE12
AD12

P9

N9
M9
R8

P8
N8
M8

P7
N7
M7
R6

P6
M6

A6
R5

P5
N5
M5

P4
N4
M4
R3

P3
N3
M3
R2

P2
M2
D2

R1

P1
N1
M1

P O W E R

VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
VTT52
VTT53
VTT54
VTT55
VTT56
VTT57
VTT58
VTT59
VTT60
VTT61
VTT62
VTT63
VTT64
VTT65
VTT66
VTT67
VTT68
VTT69
VTT70
VTT71
VTT72
VTT73
VTT74
VTT75
VTT76

VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

CALISTOGA A0_FCBGA1466~D

VCC_SYNC

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL

VCCA_3GBG
VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS

VSSA_LVDS

VCCA_MPLL
VCCA_TVBG

VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCDQ_TVDAC

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

W=30 mils

+1.5VRUN_3GPLL

0.1U_0402_16V4Z~D

+VCCP

+1.5VRUN_DPLLA
+1.5VRUN_DPLLB
+1.5VRUN_HPLL

+1.5VRUN_MPLL
+1.5VRUN

+1.5VRUN

C766

0.1U_0402_16V4Z~D

+1.5VRUN

1

2

Should be placed on top

+1.5VRUN_PCIE

1

1

+

C743

C744

2

+2.5VRUN

1

C740

2

Route +2.5VRUN from GMCH pinG41 to
decoupling cap (C740)<200mil to the edge.

1

2

C774

+3VRUN

1

C767

2

10U_0805_4VAM~D

0.1U_0402_16V4Z~D

2

220U_D2_4VM~D

+1.5VRUN_QTVDAC

C892

0.022U_0402_16V7K~D

1

C739

2

10U_0805_4VAM~D

1

1

2

2

BLM21PG600SN1D_0805~D

10U_0805_4VAM~D

C770

0.1U_0402_16V4Z~D

L58

12

+1.5VRUN

+1.5VRUN

L60

12

BLM18PG181SN1_0603~D

Should be placed in cavity

+1.5VRUN_3GPLL

1

C780

2

0.1U_0402_16V4Z~D

R651

0.5_0805_1%~D

1 2

1

C781

2

10U_0805_4VAM~D

+1.5VRUN_MPLL

45mA Max.

1

C778

2

0.1U_0402_16V4Z~D

+1.5VRUN_DPLLB

40mA Max.

10U_MLZ2012E100PTAIN_60mA_25%_0805~D

1

C896

2

0.1U_0402_16V4Z~D

+1.5VRUN_HPLL

45mA Max.

1

C776

2

0.1U_0402_16V4Z~D

+1.5VRUN_DPLLA

40mA Max.

10U_MLZ2012E100PTAIN_60mA_25%_0805~D

1

C895

2

+3GPLL_R

BLM21PG600SN1D_0805~D

1

2

1

2

0.1U_0402_16V4Z~D

L63

L62

12

BLM18AG121SN1D_0603~D

C779
22U_0805_6.3V6M~D

L73

12

L61

12

BLM18AG121SN1D_0603~D

C777
22U_0805_6.3V6M~D

L72

12

12

+1.5VRUN

+1.5VRUN

+1.5VRUN

1

C782

2

0.1U_0402_16V4Z~D

+1.5VRUN

+1.5VRUN

http://hobi-elektronika.net

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Elec tronics, Inc.

Calistoga(4 of 6)

Greenland-LA2732P

13 63Wednesday, December 28, 2005

1

of

X03

5

4

3

2

1

+VCCP

+VCCP

D D

1

1

C788

2

0.22U_0402_10V4Z~D

1

C C

C789

2

10U_0805_4VAM~D

C794

C792

C800

1

C791

2

2

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

1

1

C790

2

2

1U_0603_10V4Z~D

10U_0805_4VAM~D

1

+

2

330U_D2E_2.5VM~D

CRB 270uF

1

B B

A A

C804

+

2

330U_D2E_2.5VM~D

+VCCP

U39F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA A0 _ FCBGA1466~D

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37

P O W E R

VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100

VCC_SM101

VCC_SM102

VCC_SM103

VCC_SM104

VCC_SM105

VCC_SM106

VCC_SM107

+1.5VRUN

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

VCCSM_LF2
VCCSM_LF1

+1.8VSUS

C806

1

C807

2

0.47U_0402_10V4Z~D

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

Place near U39.AV1 & AJ1

1

2

0.47U_0402_10V4Z~D

U39G

AA33

VCC0

W33

VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5

AA32

VCC6

Y32

VCC7

W32

VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14

AA31

VCC15

W31

VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22

AA30

VCC23

Y30

VCC24

W30

VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

AA29

W29

M29

AB28
AA28

M28

M27

M25

M24
AB23
AA23

M23
AC22

AB22

W22

M22
AC21

AA21

W21

M21
AC20

AB20

W20

M20
AB19

AA19

L30
Y29
V29

U29
R29
P29

L29

Y28
V28
U28
T28
R28
P28
N28

L28
P27
N27

L27
P26
N26

L26
N25

L25
P24
N24

Y23
P23
N23

L23

Y22
P22

N22

L22

N21

L21

Y20
P20

N20

L20

Y19
N19

P O W E R

VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

CALISTOGA A0 _ FCBGA1466~D

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

+1.8VSUS

VCCSM_LF4
VCCSM_LF5

Place near U39.AT41 & AM41

1

C795

2

1

C799

2

0.47U_0402_10V4Z~D

Place near U39.BA23

1

C801

2

10U_0805_4VAM~D

1

C805

2

0.47U_0402_10V4Z~D

Place near U39.BA15

C787

0.1U_0402_16V4Z~D

1

1

C793

2

2

0.47U_0402_10V4Z~D

0.47U_0402_10V4Z~D

C796

C802

1

2

1

2

10U_0805_4VAM~D

1

C797

2

0.1U_0402_16V4Z~D

1

C798

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

http://hobi-elektronika.net

5

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Calistoga(5 of 6)

Greenland-LA2732P

14 63W ed nes da y, De ce mber 28, 2005

1

X03

of

5

4

3

2

1

U39I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

D D

C C

B B

A A

VSS4

M41

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

VSS9

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

P O W E R

VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99

CALISTOGA A0_FCBGA1466~D

AT38

AM38

AH38
AG38
AF38
AE38

AK37
AH37
AB37
AA37

W37

AY36

AW36

AN36
AH36
AG36
AF36
AE36
AC36

BA35
AV35
AR35
AH35
AB35
AA35

W35

AN34
AK34
AG34
AF34

L39

J39
H39
G39

F39
D39

C38

Y37

V37

T37
R37

P37
N37
M37

L37

J37
H37
G37

F37
D37

C36

B36

Y35

V35

T35
R35

P35
N35
M35

L35

J35
H35
G35

F35
D35

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

U39J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA A0_FCBGA1466~D

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

http://hobi-elektronika.net

5

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Calistoga(6 of 6)

Greenland-LA2732P

15 63W ed nes da y, De ce mber 28, 2005

1

X03

of

5

+3VRUN +3VRUN+12VRUN

12

R530
10K_0402_5%~D

D D

1

D22

@

RB751V_SOD323~D

1

C672

22U_1206_10V4Z~D

C671

2

@

1000P_0402_50V7K~D

2

2 1

MOLEX_53261-0371~D

1

@

2

JFAN1

1

1

2

2

4

3

3

5

FAN1 FAN2

FAN1 Control and Tachometer

Place C545 close to the Guardian

C C

B B

REM_DIODE3_N, REM_DIODE3_P routing together.
Trace width / Spacing = 10 / 10 mil

A A

2200P_0402_50V7K~D

Place near the bottom SODIMM

http://hobi-elektronika.net

H_THERMDA7

2200P_0402_50V7K~D

H_THERMDC7

+3VSUS

0.1U_0402_16V4Z~D

+3VSUS

C907

0.1U_0402_16V4Z~D

1

Q72

C923

2

@

PMBT3904_SOT23~D

49.9_0603_1%~D

1 2

1

2

5

pins as possible

C545

R810

1

C906

2

+RTC_CELL

0.1U_0402_16V4Z~D

R815

147K_0402_1%~D

R818

41.2K_0402_1%~D

E

31

B

2

C

C910

2200P_0402_50V7K~D

1

2

DAT_SMB37

+3VSUS

SUSPWROK23,43

1

C534

12

12

1

2

2200P_0402_50V7K~D

ICH_PWRGD#43
POWER_SW#37,39

2

1 2

R814 8.2K_0402_5%~D

1K_0402_5%~D

R817

C908

1

1 2

2

REM_DIODE3_N
REM_DIODE3_P

Place C910 close to the Guardian
pins as possible

4

FAN1_TACH 37 FAN2_TACH 37

C662
1000P_0402_50V7K~D

4
5

DAT_SMB
CLK_SMB

1 2

R811 7.5K_0402_5%~D

+3VSUS_THRM

1 2

R812 1K_0402_5%~D

1 2

R462 1K_0402_5%~D

THERMATRIP1#
THERMATRIP2#
THERMATRIP_VGA#

+FAN1_VOUT
FAN2_PWM

4

3

FAN2_PWM FAN2VREF

1 2

120K_0402_5%~D

Note: +3VRUN leakage issue from ATI M22

THERMATRIP_VGA#

+3VRUN

R175

2.2K_0402_5%~D

1 2

OTBMP#19

U51

7

SMDATA

8

SMBCLK

23

LDO_SHDN#_ADDR

35

DP2

34

DN2

12

+3V_SUS

21

VSUS_PWRGD

18

+RTC_PWR3V

13

+3V_PWROK#

38

POWER_SW#

14

THERMTRIP1#

15

THERMTRIP2#

16

THERMTRIP3#

39

VSET

29

HW_LOCK#

9

VSS

1

DP3

2

DN3

6

FAN_OUT

33

FAN_DAC

10

GPIO1

11

GPIO2

19

GPIO3

20

GPIO4

32

GPIO5

EMC4000_QFN40~D

C

Q23

2

B

PMBT3904_SOT23~D

E

3 1

R181

0_0402_5%~D@

1 2

Voltage margining circuit for LDO output.
For Vmargin, stuff R886 and R834=30K.
R834=1K for production

ATF_INT#

17

ATF_INT#

VCP1

3

VCP
VCP

LDO_POK

DN1
DP1

THERMTRIP_SIO

THERM_STP#

INTRUDER#

LDO_SET

LDO_OUT
LDO_OUT

LDO_IN
LDO_IN

VDD_5V

40

31

36
37

30
4

22

24
25

27

26
28

5

VCP2

2.5V_RUN_PW RGD

REM_DIODE1_N
REM_DIODE1_P

LDO_SET

+3VRUN_R

SMBUS ADDRESS : 2F

1

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

R551

VCP1 25
VCP2 25

R835 10K_0402_5%~D@

1

C916

C915

2

0.1U_0402_16V4Z~D

C921

1 2

0.1U_0402_16V4Z~D

8

U38B

5

P

FAN2_VFB

1

C679

2

0.22U_0603_10V7K~D

R553

1 2

120K_0402_5%~D

IN+

6

IN-

4

1 2

C680 2200P_0402_50V7K~D@

R552

78.7K_0402_1%~D

FAN2_ON

7

O

G

LM358M_SO8~D

12

RB751V_SOD323~D

D15

FAN2 Control and Tachometer

+2.5VRUN

12

R886

31.6K_0402_1%~D

LDO_SET

ATF_INT# 37CLK_SMB37

2.5V_RUN_PWRGD 43

Place C546 close to the Guardian
pins as possible

+3VALW

12

2200P_0402_50V7K~D
R816
10K_0402_5%~D

+5VRUN

10U_0805_10V4Z~D

1

C546

2

THERMTRIP_SIO 38

ACAV_IN 19,37,46,52

THERM_STP# 48

12

1

C913

2

@

1

C914

2

@

@

12

R834
1K_0402_5%~D

B

2

PMBT3904_SOT23~D

Place under CPU

+RTC_CELL

1

C909

2

0_1210_5%~D

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D

1

C911

2

1U_0603_10V4Z~D

0.1U_0402_16V4Z~D

E

31

Q11

C

+2.5VRUN

R826

@

12

2

G

3

2 1

2.21K_0603_1%~D

2200P_0402_50V7K~D

2.21K_0603_1%~D

2200P_0402_50V7K~D

1

C922

2

2200P_0402_50V7K~D

+3VRUN

2

1

+5VRUN

D

S

D

S

2

B

2

B

13

13

+3VSUS

+3VSUS

12

R529
10K_0402_5%~D

1

@

2

JFAN2

1

1

2

2

4

335

+5VSUS+5VSUS

2

G

Q86
2N7002_SOT23~D

+5VSUS+5VSUS

2

G

Q87
2N7002_SOT23~D

12

R219

8.2K_0402_5%~D

C

E

3 1

12

R220

8.2K_0402_5%~D

C

E

3 1

C661
1000P_0402_50V7K~D

4
5

12

R903
10K_0402_5%~D

12

R905
10K_0402_5%~D

THERMATRIP2#THERM_STP#

1

2

THERMATRIP1#

1

2

6

2

1

D

S

4 5

+FAN2_VOUT+FAN1_VOUT

1

C335

2

R902

VCP1

C958

R904

VCP2

C959

THERMTRIP_MCH#10

H_THERMTRIP#7

Q67

SI3456DV-T1-E3_TSOP6~D

1

C330

2

@

1000P_0402_50V7K~D

22U_1206_10V4Z~D

12

1

2

12

1

2

+VCCP

+VCCP

VCP1_R25

VCP2_R25

R186

2.2K_0402_5%~D

1 2

PMBT3904_SOT23~D

R184

2.2K_0402_5%~D

1 2

PMBT3904_SOT23~D

MOLEX_53398-0371~D

Q24

Q25

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Thermal Senser & Fan

Greenland-LA2732P

1

5V_CAL_SIO1# 38

5V_CAL_SIO2# 38

C209

0.1U_0402_16V4Z~D

C210

0.1U_0402_16V4Z~D

16 63Wednesday, December 28, 2005

of

X03

5

4

3

2

1

+1.8VSUS +1.8VSUS

JDIM1

1

VREF

3

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
203

2.2U_0603_6.3V6K~D
C269

VSS

5

DQ0

7

DQ1

9

VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
203

FOX_AS0A426-M2SN-7F~D

DIMMB

STANDARD

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0

D D

C C

DDR_CKE2_DIMMB10

DDR_B_BS211

DDR_B_BS011
DDR_B_WE#11

DDR_B_CAS#11

DDR_CS3_DIMMB#10

M_ODT310

B B

CK_SDATA6,18
CK_SCLK6,18

A A

http://hobi-elektronika.net

DDR_B_DQS0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59
CK_SDATA

CK_SCLK

+3VRUN

5

0.1U_0402_16V4Z~D
C270

1

1

2

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD
RAS#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

CK0

NC

A11

A7
A6

A4
A2

A0
BA1
S0#

NC

CK1

SA1

204

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204

V_DDR_MCH_REF

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_D14

DDR_B_D15

DDR_B_D20
DDR_B_D21

PM_EXTTS#0_R
DDR_B_DM2

DDR_B_D22
DDR_B_D23

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D30
DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

10K_0402_5%~D

12

R255

4

M_CLK_DDR3 10

M_CLK_DDR#3 10

PM_EXTTS#0_R 18

DDR_CKE3_DIMMB 10

DDR_B_BS1 11

DDR_B_RAS# 11
DDR_CS2_DIMMB# 10

M_ODT2 10

M_CLK_DDR2 10

M_CLK_DDR#2 10

R254

1 2

10K_0402_5%~D

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D

1

C276

2

+3VRUN

V_DDR_MCH_REF 10,18,50

1

C271

2

Layout Note:
Place near JDIM1

Layout Note:
Place one cap close to
every 2 pullup
resistors terminated to
+0.9V_DDR_VTT

Layout Note:
Place these resistor
closely JDIM1,all
trace length<750 mil

Layout Note:
Place these resistor
closely JDIM1,all
trace length Max=1.3"

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

DDR_B_DQS#[0..7]11

DDR_B_D[0..63]11
DDR_B_DM[0..7]11
DDR_B_DQS[0..7]11

DDR_B_MA[0..13]11

+1.8VSUS

2.2U_0603_6.3V6K~D

+0.9V_DDR_VTT

0.1U_0402_16V4Z~D

1

2

C249

DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12

M_ODT3
DDR_CS3_DIMMB#
DDR_B_CAS#
DDR_B_WE#

DDR_B_BS0
DDR_B_MA10
DDR_B_MA1
DDR_B_MA3

2.2U_0603_6.3V6K~D

C274

C238

1

2

0.1U_0402_16V4Z~D
C277

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C246

RP3

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

RP1

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

RP2

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

2.2U_0603_6.3V6K~D
C236

1

2

0.1U_0402_16V4Z~D
C235

1

2

0.1U_0402_16V4Z~D

1

2

C556

C557

+0.9V_DDR_VTT

2

2.2U_0603_6.3V6K~D
C275

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
C272

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C560

RP7

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

RP8

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

RP9

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

RP13

14
23

56_0404_4P2R_5%~D

2.2U_0603_6.3V6K~D
C237

1

2

C241

1

2

0.1U_0402_16V4Z~D

1

2

C561

C559

DDR_B_MA6
DDR_B_MA7
DDR_B_MA11
DDR_CKE3_DIMMB

DDR_B_BS1
DDR_B_MA0
DDR_B_MA2
DDR_B_MA4

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C558

0.1U_0402_16V4Z~D

1

1

2

2

C252

C248

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C251

C250

SPD Address Table

DDR_B_MA13
M_ODT2
DDR_CS2_DIMMB#
DDR_B_RAS#

DDR_B_BS2
DDR_CKE2_DIMMB

DIMM/Channel ADDR [1:0]

A

B

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRII DIMM B
Greenland-LA2732P

1

1

2

C247

[ 00 ]

[ 10 ]

17 63W ed nes da y, D ec em ber 28, 2005

of

X03

5

4

3

2

1

+1.8VSUS +1.8VSUS

JDIM2

1

VREF

3

C296

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
203

VSS

5

DQ0

7

DQ1

9

VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
203

FOX_AS0A426-M2R-TR~D

DIMMA

DDR_A_D0
DDR_A_D1

D D

C C

DDR_CKE0_DIMMA10

DDR_A_BS211

DDR_A_BS011
DDR_A_WE#11

DDR_A_CAS#11

DDR_CS1_DIMMA#10

M_ODT110

B B

CK_SDATA6,17

A A

CK_SCLK6,17

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1 M_CLK_DDR0
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
CK_SDATA

CK_SCLK

+3VRUN

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

C297

1

1

2

2

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#
DQ14

DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

SAO

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A11

BA1
S0#

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204

204

REVERSE

http://hobi-elektronika.net

5

V_DDR_MCH_REF

DDR_A_D4
DDR_A_D5

DDR_A_DM0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1

M_CLK_DDR#0
DDR_A_D14

DDR_A_D15

DDR_A_D20
DDR_A_D21

PM_EXTTS#0_R
DDR_A_DM2

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

10K_0402_5%~D

10K_0402_5%~D

12

R281

4

2.2U_0603_6.3V6K~D

M_CLK_DDR0 10

M_CLK_DDR#0 10

DDR_CKE1_DIMMA 10

DDR_A_BS1 11
DDR_A_RAS# 11
DDR_CS0_DIMMA# 10

M_ODT0 10

M_CLK_DDR1 10
M_CLK_DDR#1 10

R283

1 2

0.1U_0402_16V4Z~D

1

C294

2

R791

0_0402_5%~D

V_DDR_MCH_REF 10,17,50

1

C298

2

PM_EXTTS#0_R 17

12

PM_EXTTS#0 10

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Layout Note:
Place near JDIM2

Layout Note:
Place one cap close to
every 2 pullup
resistors terminated to
+0.9V_DDR_VTT

Layout Note:
Place these resistor
closely JDIM2,all
trace lengt h <750 mil

Layout Note:
Place these resistor
closely JDIM2,all
trace length Max=1.3"

3

DDR_A_DQS#[0..7]11

DDR_A_D[0..63]11
DDR_A_DM[0..7]11
DDR_A_DQS[0..7]11

DDR_A_MA[0..13]11

+0.9V_DDR_VTT

DDR_A_BS0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3

DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12

M_ODT1
DDR_CS1_DIMMA#
DDR_A_CAS#
DDR_A_WE#

+1.8VSUS

0.1U_0402_16V4Z~D

1

2

C643

2.2U_0603_6.3V6K~D
C299

1

2

0.1U_0402_16V4Z~D
C301

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C642

RP11

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

RP10

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

RP12

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

2.2U_0603_6.3V6K~D
C285

1

2

0.1U_0402_16V4Z~D

1

2

C644

+0.9V_DDR_VTT

2

2.2U_0603_6.3V6K~D
C300

1

2

0.1U_0402_16V4Z~D
C302

1

2

0.1U_0402_16V4Z~D

1

2

C645

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

56_1206_8P4R_5%~D

1 8
2 7
3 6
4 5

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D
C286

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C279

C280

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C648

C291

RP6

DDR_A_MA6
DDR_A_MA7
DDR_A_MA11

DDR_CKE1_DIMMA

56_1206_8P4R_5%~D
RP4

DDR_A_MA13

M_ODT0

DDR_CS0_DIMMA#

DDR_A_RAS#

RP5

DDR_A_BS1

DDR_A_MA0

DDR_A_MA2

DDR_A_MA4

56_1206_8P4R_5%~D

RP14

DDR_A_BS2

14

DDR_CKE0_DIMMA

23

56_0404_4P2R_5%~D

C287

1

2

1

2

0.1U_0402_16V4Z~D

1

2

C290

1

2

C292

0.1U_0402_16V4Z~D

1

2

C293

0.1U_0402_16V4Z~D

1

2

C647

1

2

C288

0.1U_0402_16V4Z~D

1

2

C289

0.1U_0402_16V4Z~D

1

2

C646

0.1U_0402_16V4Z~D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRII DIMM A

Greenland-LA2732P

18 63W ed nes da y, D ec em ber 28, 2005

1

of

X03

5

4

JVGA

3

2

1

1

1

+3VRUN

1

1

1

C394

C407

D D

+5VRUN

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0

PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1

PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2

PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3

PCIE_MTX_GRX_P4

C C

B B

PCIE_MTX_GRX_P[0..15]12

A A

http://hobi-elektronika.net

PCIE_MTX_GRX_N4
PCIE_MTX_GRX_P5

PCIE_MTX_GRX_N5
PCIE_MTX_GRX_P6

PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P7

PCIE_MTX_GRX_N7
PCIE_MTX_GRX_P8

PCIE_MTX_GRX_N8
PCIE_MTX_GRX_P9

PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P10

PCIE_MTX_GRX_N10
PCIE_MTX_GRX_P11

PCIE_MTX_GRX_N11
PCIE_MTX_GRX_P12

PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P13

PCIE_MTX_GRX_N13
PCIE_MTX_GRX_P14

PCIE_MTX_GRX_N14
PCIE_MTX_GRX_P15

PCIE_MTX_GRX_N15

+GFX_PWR_SRC

PCIE_MTX_GRX_N[0..15]12

PCIE_MTX_GRX_P[0..15]

5

2

0.047U_0402_10V7K~D

C118 0.1U_0402_16V4Z~D

1 2

C122 0.1U_0402_16V4Z~D

1 2

C135 0.1U_0402_16V4Z~D

1 2

C139 0.1U_0402_16V4Z~D

1 2

C141 0.1U_0402_16V4Z~D

1 2

C145 0.1U_0402_16V4Z~D

1 2

C150 0.1U_0402_16V4Z~D

1 2

C155 0.1U_0402_16V4Z~D

1 2

C158 0.1U_0402_16V4Z~D

1 2

C161 0.1U_0402_16V4Z~D

1 2

C172 0.1U_0402_16V4Z~D

1 2

C176 0.1U_0402_16V4Z~D

1 2

C178 0.1U_0402_16V4Z~D

1 2

C186 0.1U_0402_16V4Z~D

1 2

C190 0.1U_0402_16V4Z~D

1 2

C195 0.1U_0402_16V4Z~D

1 2

C386

2

0.047U_0402_10V7K~D

0.047U_0402_10V7K~D

1

C681

0.1U_0402_16V4Z~D

2

C121 0.1U_0402_16V4Z~D

1 2

C132 0.1U_0402_16V4Z~D

1 2

C138 0.1U_0402_16V4Z~D

1 2

C140 0.1U_0402_16V4Z~D

1 2

C144 0.1U_0402_16V4Z~D

1 2

C149 0.1U_0402_16V4Z~D

1 2

C154 0.1U_0402_16V4Z~D

1 2

C157 0.1U_0402_16V4Z~D

1 2

C160 0.1U_0402_16V4Z~D

1 2

C170 0.1U_0402_16V4Z~D

1 2

C175 0.1U_0402_16V4Z~D

1 2

C177 0.1U_0402_16V4Z~D

1 2

C185 0.1U_0402_16V4Z~D

1 2

C189 0.1U_0402_16V4Z~D

1 2

C194 0.1U_0402_16V4Z~D

1 2

C198 0.1U_0402_16V4Z~D

1 2

1

C213

0.1U_0603_25V7K~D

2

PCIE_MTX_GRX_N[0..15]

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15

2

DVI_TX0+20
DVI_TX0-20

DVI_TX1+20
DVI_TX1-20

DVI_TX2+20
DVI_TX2-20

DVI_CLK+20
DVI_CLK-20

1

C682

0.1U_0402_16V4Z~D

2

+3VSUS

1

C212

0.1U_0603_25V7K~D

2

+12VRUN

RUNPWROK37,38,42,43,47,51

+2.5VRUN

PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15

DVI_TX0+
DVI_TX0-

DVI_TX1+
DVI_TX1-

DVI_TX2+
DVI_TX2-

DVI_CLK+
DVI_CLK-

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0

PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1

PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3

PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4

PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5

PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6

PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7

PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8

PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9

PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10

PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11

PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12

PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13

PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14

PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

RUNPWROK

4

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

69

71

71

73

73

75

75

77

77

79

79

81

81

83

83

85

85

87

87

89

89

91

91

93

93

95

95

97

97

99

99

101

101

103

103

105

105

107

107

109

109

111

111

113

113

115

115

117

117

119

119

121

121

123

123

125

125

127

127

129

129

131

131

133

133

135

135

137

137

139

139

141

141

143

143

145

145

147

147

149

149

151

151

153

153

155

155

157

157

159

159

161

161

163

163

165

165

167

167

169

169

171

171

173

173

175

175

177

177

179

179

181

181

183

183

185

185

187

187

189

189

191

191

193

193

195

195

197

197

199

199

201

201

203

203

205

205

JAE_WB3M200VD1~D

2

2

4

4

6

6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206

Folsom / Greenland
used

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206

SBAT_SMBCLK
SBAT_SMBDAT

TV_Y
TV_CVBS
TV_C
VSYNC

HSYNC
VGA_BLU
VGA_GRN
VGA_RED

DVI_SCLK_L
DVI_SDAT_L
PLTRST_DELAY#

CLK_PCIE_VGA
CLK_PCIE_VGA#

YPRPB_DET#

T3 PAD~D@
T4 PAD~D@

PCIE_MRX_GTX_P0
PCIE_MRX_GTX_N0

PCIE_MRX_GTX_P1
PCIE_MRX_GTX_N1

PCIE_MRX_GTX_P2
PCIE_MRX_GTX_N2

PCIE_MRX_GTX_P3
PCIE_MRX_GTX_N3

PCIE_MRX_GTX_P4
PCIE_MRX_GTX_N4

PCIE_MRX_GTX_P5
PCIE_MRX_GTX_N5

PCIE_MRX_GTX_P6
PCIE_MRX_GTX_N6

PCIE_MRX_GTX_P7
PCIE_MRX_GTX_N7

PCIE_MRX_GTX_P8
PCIE_MRX_GTX_N8

PCIE_MRX_GTX_P9
PCIE_MRX_GTX_N9

PCIE_MRX_GTX_P10
PCIE_MRX_GTX_N10

PCIE_MRX_GTX_P11
PCIE_MRX_GTX_N11

PCIE_MRX_GTX_P12
PCIE_MRX_GTX_N12

PCIE_MRX_GTX_P13
PCIE_MRX_GTX_N13

PCIE_MRX_GTX_P14
PCIE_MRX_GTX_N14

PCIE_MRX_GTX_P15
PCIE_MRX_GTX_N15

OTBMP#
FPBACK_EN

C203

YPRPB_DET# 20,38

+5VALW

SBAT_SMBCLK 37

SBAT_SMBDAT 37
TV_Y 20
TV_CVBS 20
TV_C 20

VSYNC 20

HSYNC 20
VGA_BLU 20
VGA_GRN 20
VGA_RED 20

PLTRST_DELAY# 23
CLK_PCIE_VGA 6

CLK_PCIE_VGA# 6

+3VRUN

2

2

C229

1

1

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

GFX_PWR_LIMIT

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Not necessary to run CRT SMBus
trace to VGA card.
RGB signals are integrated to
DVI-I on M/B.

+3VRUN

C

2

B

E

3 1

Q13
PMBT3904_SOT23~D

10K_0402_5%~D

12

R121

PCIE_MRX_GTX_P0
PCIE_MRX_GTX_P1
PCIE_MRX_GTX_P2
PCIE_MRX_GTX_P3
PCIE_MRX_GTX_P4
PCIE_MRX_GTX_P5
PCIE_MRX_GTX_P6
PCIE_MRX_GTX_P7
PCIE_MRX_GTX_P8
PCIE_MRX_GTX_P9
PCIE_MRX_GTX_P10
PCIE_MRX_GTX_P11
PCIE_MRX_GTX_P12
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_P14
PCIE_MRX_GTX_P15

PCIE_MRX_GTX_N0
PCIE_MRX_GTX_N1
PCIE_MRX_GTX_N2
PCIE_MRX_GTX_N3
PCIE_MRX_GTX_N4
PCIE_MRX_GTX_N5
PCIE_MRX_GTX_N6
PCIE_MRX_GTX_N7
PCIE_MRX_GTX_N8
PCIE_MRX_GTX_N9
PCIE_MRX_GTX_N10
PCIE_MRX_GTX_N11
PCIE_MRX_GTX_N12
PCIE_MRX_GTX_N13
PCIE_MRX_GTX_N14
PCIE_MRX_GTX_N15

R942

0_0402_5%~D@

C216

BIA_PWM

2

C239

1

0.1U_0603_25V7K~D

+3VRUN

4

O

2

1

C211

1

2

0.1U_0603_25V7K~D

0.1U_0402_16V4Z~D

1 2

U19

5

74AHCT1G08GW_SSOP5~D

1

P

B

2

A

G

3

BIA_PWM 37

@

10U_1210_25V6M~D

C957

1 2

OTBMP# 16

+5VRUN

FPBACK_EN 38

3

R123

100K_0402_5%~D

1 2

PCIE_MRX_GTX_P[0..15]

PCIE_MRX_GTX_N[0..15]

+GFX_PWR_SRC

R253
0_0402_5%~D@

1 2

DVI_DETECT 20

Sullivan Used

R114

100K_0402_5%~D

1 2

+5VRUN

DVI_SCLK_L

DVI_SDAT_L

PCIE_MRX_GTX_P[0..15] 12

PCIE_MRX_GTX_N[0..15] 12

For +GFX_PWR_SRC surge current issue

C227

SIO_GFX_PWR 38
ACAV_IN 16,37,46,52

2

+5VRUN

12

12

R107

5.6K_0402_5%~D

DVI_SCLK

DVI_SDAT

1

1

C88220P_0402_50V7K~D

C100220P_0402_50V7K~D

2

2

RUN_ON_5V#42

1
2
3 6

S

4

GPWR_SRC_ON

12

PEG_PWRON#

13

D

2

G

S

5.6K_0402_5%~D

D

G

Q34
SI4825DY-T1-E3_SO8~D

R218
100K_0402_5%~D

Q29
2N7002_SOT23~D

S

2N7002_SOT23~D

2

1

0.1U_0603_25V7K~D

G

C221

R118

G

2

Q10

13

D

S

2N7002_SOT23~D

2

Q12

13

D

+PWR_SRC +GFX_PWR_SRC

2

R224

1

0.1U_0603_25V7K~D

1 2

100K_0402_5%~D

RUN_ON37,42,43,47,48,49,50

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

VGA CONN.
Greenland-LA2732P

1

DVI_SCLK 20

DVI_SDAT 20

+GFX_PWR_SRC

12

13

D

2

G

S

8
7

5

19 63Wednesday, December 28, 2005

R545
22_0805_5%~D@

Q65
2N7002_SOT23~D@

X03

of