Dell XPS M140 Schematics
Thermal Sensor
ENC 6N300
HDD
21
LINE OUT
INT.SPKR
33
IDE
MIC IN
27
200-PIN DDR2 SODIMM
UNBUFFERED
DDR2 SODIMM
Socket
UNBUFFERED
DDR2 SODIMM
Socket
SMBus
ODD Bay
Silicon Image SII3811
(MARVELL 8040)
OP AMP
MAX4411ETP
Azalia CODEC
STAC 9200
OP AMP
TAPA6017
Clock Generator
ICS954226/CV140PAG
11
12
21
27
26
26
3
DDRII 400/533MHz
Primary IDE
20
SATA
AZALIA
Intel Mobile CPU
Dothan: 1.6BGHz/1.73GHz
1.87GHz/2AGHz/2.1GHz
Celeron:1.4GHz/1.5GHz/1.6GHz
HOST BUS
400/533MHz
4.3GB/s
Alviso
GM(915)
AGTL+ CPU I/F
DDR Memory I/F
INTEGRATED GRAHPICS
LVDS, CRT I/F
DMI I/F
6,7,8,9
100MHz
Intel
ICH6-M
USB 2.0 (2+2+2+2)
ETHERNET(10/100Mb)
AC97 2.2/AZALIA
ATA 66/100
SATA
ACPI 1.1
LPC I/F
PCI/PCI BRIDGE
16,17,18,19
4,5
LVDS
RGB CRT
S-VIDEO
Barbados Block Diagram
Project code:91.4C401.001
PCB P/N :04242
REVISION :SD
14.1" WXGA
CRT Port
TV OUT
Power Switch
PCI Express/USB2.0
14
43
15
Richo 832
1394
7in1
PCI Bus / 33MHz
20
ATMEL
AT93C46
22,23
25
NewCard
SLOT
20
1394
7in1
BCM 4401
Mini-PCI
802.11a/b/g
24
1394
CONN
7in1
CONN
28
System DC/DC
MAX8734A
PWR_SRC
Battery Charger
RJ45
CONN
43
MAX1909
PWR_SRC BATT+
System DC/DC
MAX8743
PWR_SRC +1.05VRUN
23
CPU DC/DC
ISL6217
22
PWR_SRC
DDR2 DC/DC
TI 51116
PWR_SRC
39
OUTPUTSINPUTS
+5VSUS
+3VSRC
42
40
+1.5VS US
38
VCC_CORE
41
+1.8VS US
+0.9VRUN
+0.9VSUS_DDR2VREF
RJ11
CONN
MDC
Modem
43
1.5
32
USB*4
USB 2.0
32
KBC
SMSC LPC47354
MAC III
29,30
BIOS
MX29LV008BTC-90
31
Int. KB
Bluetooth
32
Touch Pad
34
PCB LAYER
L1:TOP
L2:Signal
L3:GND
L4:Signal
L5:Signal
L6:VCC
L7:GND
L8:BOT
<Core Design>
www.schematic-x.blogspot.com
Title
Size Document Number R ev
Custom
Date: Sheet of
Block diagram
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Barbados
144Thursday, May 12, 2005
SD
Alviso Strapping Signals and Configuration
Pin Name
CFG[2:0]
CFG[3:4]
CFG5
4 4
CFG6
CFG7
CFG[8:11]
CFG[12:13]
CFG[14:15]
CFG16
CFG17
CFG18
CFG19
CFG20
3 3
SDVOCRTL
_DATA
All strap signals are sampled with respect to the leading
NOTE:
edge of the Alviso GMCH PWORK In signal.
ICH6-M Strapping Signals and Configuration
Pin Name
ACZ_SDOUT
ACZ_SYNC
DPRSLPVR
EE_CS
EE_DOUT
GNT[5]#/GPO[17]#
2 2
GNT(6)#/GPO(16)#
GPIO[25]
INTVRMEN
LINKALERT#
REQ[4:1]
SATALED#
SPKR
TP[3]
All strap signals are sampled on the rising edge of the
NOTE:
1 1
PWR_SRC
VCCRTC
ICH6-M's PWROK signal.
BATT+
DC_IN+
A
Strap Description
FSB Frequency Select
Reversed
DMI x2 Select
DDR I / DDR II
CPU Strap
Reversed
XOR/ALL Z test
straps
Reversed
FSB Dynamic ODT 0 = Dynamic ODT Disabled
Reversed
CPU core VCC
Select
CPU VTT Select
Reversed
SDVO Present
Strap Description
0=Normal(default)
1=XOR Test mode
0=Normal(default)
0=Normal
0=Normal
0=PCI cycles to FWH
1=PCI cycles to LPC (default)
0="Top block swap" mode
1=Normal(default)
0=Internal 2.5V DISEN(default)
1=ENABLE Internal Vcc2_5VRM
0=Internal VccSus1.5V DISEN
(default)
1=ENABLE Internal VccSus1.5VVRM
1=Normal(requires external PU)
XOR Test Chain Selection
0=Normal(default)
0=Normal(default)
1=NO Reboot
0=Enter XOR Test mode
1=Normal(default)
BATT+ 42,43
DC_IN+ 42,43,44
PWR_ SRC 14,29,38,39,40,41,42,43,44
VCCRTC 16,18,29,33
Configuration
000 = Reserved
001 = FSB533
010 = FSB800
011-111 = Reversed
0 = DMI x2
1 = DMI x4
0 = DDR II
1 = DDR I
0 = Prescott
1 = Dothan
00 = Reserved
01 = XOR mode enabled
10 = All Z mode enabled
11 = Normal Operation
(Default)
1 = Dynamic ODT Enabled
(Default)
0 = 1.05V
1 = 1.5V
0 = 1.05V
1 = 1.2V
0 = No SDVO device present
(Default)
1= SDVO device present
(Default)
(Default)
(Default)
(Default)
+0.9VSUS_DDR2VREF
page 7
Note
1=Reserved
1=Reserved
1=Reserved0=Normal
1=Reserved
Selects memory
range to FWD to
out of PCI
"Top block swap"
inverts A16 on
cycles to FWH
0=Reserved
Requires external
resistors
1=Reserved
+5VSUS
+3VSUS
+1.5VSUS
B
For Dothan B stepping
NB
CFG1CFG2
10
100MHZ
133MHZ
CPU
BSEL0BSEL1
001
000
PCI TABLE
DEVICE
LAN Broadcom
BCM4401/BCM5507
MINIPCI SLOT
R5C832 AD17
XDP_TDI4
XDP_TMS4
XDP_TRST#4
XDP_TCK4
XDP_TDO4
ITP_CPU#3
ITP_CPU3
H_CPURST#4,6,44
Should place near conn.
R200 0R2-0.
R202 0R2-0.
R203 0R2-0.
R135 0R2-0.
1 2
R206
27D4R2F
IDSEL
AD16 PIRQC# REQ4# / GNT4#
AD19
R208
54D9R2F
1 2
1 2
1 2
12
XDP_DBRESET#4,35
ITP Debug Conn.
+0.9VSUS_DDR2VREF 7,11,12,41,44
+5VSUS 18,26,27,32 ,33,36,39,40,41,43,44
+3VSUS 14,17,18,19 ,20,24,25,27,28,32,33,35,36,39,40,41,43,44
+1.5VSUS 18,36,40,44
CFG0
+1.05VRUN
12
12
+3VSUS
12
R210
150R3
+2.5VRUN
+1.5VRUN
VCC_CORE
+1.05VRUN
LCDVDD
C
FS_C
1
1
IRQ
PIRQB#
PIRQD#
PIRQA#
PIRQC#
+1.05VRUN
R205
54D9R2F
R204 22D6R2F
1 2
R207 22 D6R2F
1 2
XDP_PREQ#4
XDP_PRDY#4
SD
+5VRUN
+12V
+3VRUN
ICH6-M Integrated Pull-up
D
and Pull-down Resistors
CLOCK
FS_B
0
1
0
0
REQ# / GNT#
REQ3# / GNT3#
REQ1# / GNT1#
FS_A
1
1
ACZ_BIT_CLK,
EE_DOUT, EE_CS, GNT[5]#/GPO[17],
GNT[6]#/GPO[16],
LAD[3:0]#/FB[3:0]#, LDRQ[0],
PME#, PWRBTN#,
LAN_RXD[2:0]
ACZ_RST#, ACZ_SDIN[2:0],ACZ_SYNC,
ACZ_SDOUT,ACZ_BITCLK,
SPKR
USB[7:0][P,N]
DD[7],
LAN_CLK
ICH6-M IDE Integrated Series
DPRSLP#, EE_DIN,
SDDREQ
Termination Resistors
DD[15:0],
DDACK#, IORDY,
IDEIRQ
DCS3#,
12
12
R199
R201
39D2R2F
XDP_BPM#34
XDP_BPM#24
XDP_BPM#14
XDP_BPM#04
+1.05VRUN
DY
150R3
XDP_TDI_FELX
XDP_TMS_FELX
XDP_TRST#_FELX
XDP_TCK_FELX
XDP_TDO_FELX
CPURST_FLEX#
C235
SCD1U10V2KX
CN3
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
30
MLX-CON28-U
20.K0113.028
SB
Dummy Conn
DY
+2.5VRUN 7,9,14,15,18,36,43,44
+5VRUN 14,15,18,20,21,26,28,30,33,34,36,38,43,44
+12V 14,23 ,33,36,43,44
+1.5VRUN 5,7,9,17,18,20,36,44
VCC_CORE 5,36,38,44
+1.05VRUN 3,4,5,6,7,9,10,16,18,33,36,40,44
LCDV DD 14,44
+3VRUN 3,4,9,11,12,14,15,17,18,19,20,21,22,23,26,27,28,29,30,32,33,35,36,38,43,44
LDRQ[1]/GPI[41],
TP[3]
DPRSLPVR,
DIOR#, DREQ,DIOW#,
DA[2:0],
DCS1#,
CPU
TCK(PIN A13)
+5VALW
+3VALW
E
ICH6-M EDS 14308 0.8V1
ICH6 internal 20K pull-ups
ICH6 internal 10K pull-ups
ICH6 internal 20K pull-downs
ICH6 internal 15K pull-downs
ICH6 internal 11.5K pull-downs
ICH6 internal 100K pull-downs
approximately 33 ohm
ITP Conn.
TCK(PIN 5)
FBO(PIN 11)
+5VALW 14,30 ,36,39,43,44
+3VALW 4,14, 20,22,29, 30,31,33,34,39,4 3,44
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Re v
A3
Date: Sheet
ITP CONN/Table Of Content
Barbados
244Thursday, May 12, 2005
of
SD
A
12
C225
SCD1U10V2KX
L19
1 2
MLB-201209-11
+3VRUN_APWR
C218
SC10U6D3V5MX
12
C523
SCD1U10V2KX
B
+3VRUN+3VRUN
1 2
12
C491
SCD1U10V2KX
L37
MLB-201209-11
+3VRUN_48MPWR
C514
SC10U6D3V5MX
12
C517
SCD1U10V2KX
C
+3VRUN
12
L34
1 2
MLB-201209-11
C475
SCD1U10V2KX
12
C222
SC10U6D3V5MX
12
C486
SC10U6D3V5MX
D
+3VRUN_CLKGEN
12
C487
SCD1U10V2KX
12
C515
SCD1U10V2KX
12
C209
SCD1U10V2KX
12
C521
SCD1U10V2KX
E
12
C525
SCD1U10V2KX
12
C524
SCD1U10V2KX
4 4
+3VRUN
12
R424
10KR2
PCLK_CBUS_1
3 3
R431 33R2
PCLK_CBUS22
PCLK_SIO30
PCLK_LAN24
PCLK_MINI28
PM_STPPCI#17,44
CLK_ICHPCI17
CLK_ENABLE#35,44
CLK48_ICH17
DREFCLK7
DREFCLK#7
SMBC_ICH11,12,19
SMBD_ICH11,12,19
2 2
CLK_ICH1417
CLK14_SIO30
+3VRUN_CLKGEN
12
R161
10KR2
1 1
R162
DUMMY-R2
12
12
12
SC27P50V2JN-L-GP
+1.05VRUN
12
R163
DUMMY-R2
12
R164
DUMMY-R2
A
C484
1 2
C485
12
SC27P50V2JN-L-GP
SC
Depop R30 for Dothan-B
R140
DUMMY-R2
FS_C
R143
0
0
DUMMY-R2
0
1
1 100M
1
1
1 2
R433 33R2
1 2
R440 33R2
1 2
R444 33R2
1 2
1 2
1 2
1
2 3
RN39 SRN33-2-U2
12
X2
XTAL-14D318M
R443
1 2
10R2
R437
1 2
10R2
FS_A
CPU_SEL1
CPU_SEL0
FS_B
FS_A
0
0
0
01200M
1
1
1
0
00333M
1
0
0
1
1 Reserved
1
R144 33R2
R152 33R2
+3VRUN_CLKGEN
+3VRUN_48MPWR
4
XOUT
XIN
CPU_SEL04,7
CPU_SEL14,7
R473
1 2
475R2F
CPU
266M
133M
166M
400M
+3VRUN_APWR
PCLK_CBUS_1
PCLK_SIO_1
PCLK_LAN_1
PCLK_MINI_1
DREFCLK_1
DREFCLK#_1
CKG_REF
B
+3VRUN
LCD_CLK_SEL
ITP_EN
FS_A
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_ICH
CLK_PCIE_ICH#
DREFSSCLK#
DREFSSCLK
DREFCLK
DREFCLK#
CLK_PCIE_NEW
CLK_PCIE_NEW#
12
R146
10KR2
ITP_EN
R145
0R2-0
DY
1 2
U48
37
VDDA
1
VDDPCI
7
VDDPCI
21
VDDPCIEX
28
VDDPCIEX
34
VDDPCIEX
42
VDDCPU
48
VDDREF
11
VDD48
56
PCICLK2/REQ_SEL**
3
PCICLK3
4
PCICLK4
5
PCICLK5
9
PCICLK_F1/**SELPCIEX_LCDCLK#
55
PCI/SRC_STOP#
8
ITP_EN/PCICLK_F0
10
VTT_PWRGD#/PD
12
USB_48MHZ/FS_A
14
DOTT_96MHZ
15
DOTC_96MHZ
46
SCLK
47
SDATA
49
X2
50
X1
53
REF1/FS_C/TEST_SEL
16
FS_B/TEST_MODE
39
IREF
52
REF0
ICS954226AGLFTGP
R183 49D9 R2F
1 2
R184 49D9 R2F
1 2
R466 49D9 R2F
1 2
R472 49D9 R2F
1 2
R449 49D9 R2F
1 2
R461 49D9 R2F
1 2
R177 49D9 R2F
1 2
R178 49D9 R2F
1 2
R172 49D9 R2F
1 2
R174 49D9 R2F
1 2
R170 49D9 R2F
1 2
R165 49D9 R2F
1 2
R153 49D9 R2F
1 2
R157 49D9 R2F
1 2
R181 49D9 R2F
1 2
R182 49D9 R2F
1 2
Mounting R442
CPU2_ITP on
Mounting
R438(down side)
--SRC7 on
CPU_STOP#
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
CPUCLKT2_ITP/PCIEXT6
CPUCLKC2_ITP/PCIEXC6
LCDCLK_SS/PCIEXT0
LCDCLK_SS/PCIEXC0
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
PCIEXT3
PCIEXC3
SATACLKT
SATACLKC
PCIEXT4
PCIEXC4
PEREQ1#*/PCIEXT5
PEREQ2#*/PCIEXC5
GND
GND
GND
GND
GND
GND
GNDA
54
CLK_MCH_BCLK_1
44
CLK_MCH_BCLK#_1
43
CLK_CPU_BCLK_1
41
CLK_CPU_BCLK#_1
40
XDP_CPU_1
36
XDP_CPU_1#
35
DREFSSCLK_1
17
DREFSSCLK#_1
18
CLK_PCIE_ICH_1
19
CLK_PCIE_ICH#_1
20
22
23
CLK_MCH_3GPLL_1
24
CLK_MCH_3GPLL#_1
25
CLK_PCIE_SATA_1
26
CLK_PCIE_SATA_1#
27
CLK_PCIE_NEW_1
31
CLK_PCIE_NEW#_1
30
33
32
13
51
45
29
2
6
38
C
SRN33-2-U2
RN38
1
2 3
1
2 3
RN40 SRN33-2-U2
2 3
1
2 3
1
RN42 SRN33-2-U2
RN43 SRN33-2-U2
2 3
1
1
2 3
RN46 SRN33-2-U2
1
2 3
RN45 SRN33-2-U2
4
4
RN41 SRN33-2-U2
1
2 3
RN44 SRN33-2-U2
4
4
4
4
4
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
CLK_CPU_BCLK 4,44
CLK_CPU_BCLK# 4
XDP_CPU_2
4
XDP_CPU_2#
CLK_PCIE_ICH 17
CLK_PCIE_ICH# 17
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
CLK_PCIE_SATA 16
CLK_PCIE_SATA# 16
CLK_PCIE_NEW 20,44
CLK_PCIE_NEW# 20
EXP_CLKREQ# 20
PM_STPCPU# 17,38,44
DY
R179 0R2-0
1 2
R476 0R2-0.
1 2
R475 0R2-0.
1 2
R180 0R2-0
1 2
DY
+3VRUN
R149
10KR2
DY
1 2
12
R148
10KR2
D
SD
XDP_CPU_2
XDP_CPU_2#
DY
R187 49D9 R2F
1 2
R188 49D9 R2F
1 2
DY
XDP_CPU 4
ITP_CPU 2
ITP_CPU# 2
XDP_CPU# 4
DREFSSCLK 7
DREFSSCLK# 7
Mounting R21 for LCDCLK_SS/PCIEX6=100Mhz
LCD_CLK_SEL
Mounting R27 for LCDCLK_SS/PCIEX6=96Mhz
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Re v
A3
Date: Sheet
Clock Generator (ICS954218)
Barbados
E
344Thursday, May 12, 2005
SD
of
A
H_A#[31..3]] 6
U47A
4 4
H_ADSTB#06
H_REQ#[4..0]6
3 3
H_ADSTB#16
H_A20M#16
H_FERR#16
H_IGNNE#16
R454 0R2-0.
H_STPCLK#16,44
1 2
H_INTR16
H_NMI16
H_SMI#16
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_STPCLK_R
P4
A3#
U4
A4#
V3
A5#
R3
A6#
V2
A7#
W1
A8#
T4
A9#
W2
A10#
Y4
A11#
Y1
A12#
U1
A13#
AA3
A14#
Y3
A15#
AA2
A16#
U3
ADSTB#0
R2
REQ0#
P3
REQ1#
T2
REQ2#
P1
REQ3#
T1
REQ4#
AF4
A17#
AC4
A18#
AC7
A19#
AC3
A20#
AD3
A21#
AE4
A22#
AD2
A23#
AB4
A24#
AC6
A25#
AD5
A26#
AE2
A27#
AD6
A28#
AF3
A29#
AE1
A30#
AF1
A31#
AE5
ADSTB#1
C2
A20M#
D3
FERR#
A3
IGNNE#
C6
STPCLK#
D1
LINT0
D4
LINT1
B4
SMI#
BGA479-SKT6-GPU1
62.10079.001
ADDR GROUP 0
ADDR GROUP 1
THERM XTP/ITP SIGNALS CONTROL
HCLK
DUMMY
R133
56R2J
R134
330R2
DY
+3VRUN
1
12
DY
R136
470R2
1
G
3
Q43
MMBT3904-7-F-GP
2
DY
+3VALW
12
R141
1KR2
DY
D
Q47
2N7002-8-GP
S
2 3
PROCHOT# 30
2 2
+1.05VRUN
12
CPU_PROCHOT#
1 2
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
HIT#
HITM#
BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
ITP_CLK1
ITP_CLK0
BCLK1
BCLK0
B
TP42 TPAD30
N2
L1
J3
L4
H2
M2
N4
A4
B5
J2
B11
H_RS#0
H1
H_RS#1
K1
H_RS#2
L2
M3
K3
K4
C8
B8
A9
C9
A10
B10
A13
C12
TDI
A12
C11
B13
A7
B17
B18
A18
C17
A15
A16
B14
B15
H_ADS# 6
H_BNR# 6
H_BPRI# 6
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_BREQ#0 6
H_INIT# 16
H_LOCK# 6
H_TRDY# 6
H_HIT# 6
H_HITM# 6
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_PRDY#
XDP_PREQ#
XDP_TCK
XDP_TDI
XDP_TDO
XDP_T MS
XDP_TRST#
XDP_DBRESET#
CPU_PROCHOT#
THERMTRIP# 33
XDP_CPU# 3
XDP_CPU 3
CLK_CPU_BCLK# 3
CLK_CPU_BCLK 3,44
THRMTRIP#
should connect to
ICH6 and Alviso
without T-ing
( No stub)
+1.05VRUN
R462
56R2J
1 2
H_IERR#
H_CPURST# 2,6,44
H_RS#[2..0] 6
BSEL[1:0] Freq.(MHz)
(A Stepping)
L L 100
L H 133
BSEL[1:0] Freq.(MHz)
(B Stepping)
L H 100
L L 133
12
R393
1KR2F
12
R390
2KR3F
Don't install R77 for
Dothan-A and install
for Dothan-B
+1.05VRUN
Place testpoint on
H_IERR# with a GND
0.1" away
H_THERMDA 33
H_THERMDC 33
C
TP32 TPAD30
TP37 TPAD30
TP36 TPAD30
TP39 TPAD30
TP33 TPAD30
12
R423
680R2
To V-CORE SWITCH
XDP_BPM#0 2
XDP_BPM#1 2
XDP_BPM#2 2
XDP_BPM#3 2
XDP_PRDY# 2
XDP_PREQ# 2
XDP_TCK 2
XDP_TDI 2
XDP_TDO 2
XDP_TMS 2
XDP_TRST# 2
XDP_DBRESET# 2 ,35
H_DSTBN#16
H_DSTBP#16
H_DINV#16
CPU_SEL03,7
CPU_SEL13,7
THERMTRIP#
H_DSTBN#06
H_DSTBP#06
H_DINV#06
TP46TPAD30
R130 0R2-0.
1 2
1 2
R418 0R2-0.
TP43TPAD30
TP40TPAD30
TP47TPAD30
TP17TPAD30
Layout Note:
0.5" max length.
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
PSI
R412
1 2
56R2J
A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
C23
C22
D25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
K24
L24
J26
E1
C16
C14
C3
AF7
AC1
E26
AD26
D
+1.05VRUN
U47B
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
DATA GRP 2
DATA GRP 0DATA GRP 1
D13#
D14#
D15#
DSTBN0#
DSTBN2#
DSTBP0#
DSTBP2#
DINV0#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
DATA GRP 3
D29#
D30#
D31#
DSTBN1#
DSTBN3#
DSTBP1#
DSTBP3#
DINV1#
PSI#
BSEL0
BSEL1
MISC
DPRSTP#
RSVD2
RSVD3
RSVD4
RSVD5
GTLREF0
BGA479-SKT6-GPU1
62.10079.001
DPSLP#
PWRGOOD
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DINV2#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DINV3#
COMP0
COMP1
COMP2
COMP3
DPWR#
SLP#
TEST1
TEST2
DY
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
W25
W24
T24
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
AE24
AE25
AD20
P25
P26
AB2
AB1
G1
B7
C19
E4
A6
C5
F23
COMP0
COMP1
COMP2
COMP3
TEST1CPU_GTLREF0
TEST2
R103
1KR2
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
1 2
H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6
R391 27D4 R2F
1 2
R392 54D9 R2F
1 2
R171 27D4 R2F
1 2
R173 54D9 R2F
1 2
H_DPRSLP# 16,44
H_DPSLP# 16,44
H_DPWR# 6
H_CPUSLP# 6,16,44
R156
DY
1KR2
1 2
H_D#[63..0] 6
+1.05VRUN
E
12
R160
200R2J
H_PW RGD 16,44
1 1
A
B
C
D
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Re v
A3
Date: Sheet
CPU (1 of 2)
Barbados
444Thursday, May 12, 2005
E
of
SD
A
VCC_CORE
U47C
AA11
VCC0
AA13
VCC1
AA15
VCC2
AA17
VCC3
AA19
VCC4
AA21
VCC5
AA5
VCC6
4 4
3 3
2 2
1 1
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC9
AD10
AD12
AD14
AD16
AD18
AD8
AE11
AE13
AE15
AE17
AE19
AE9
AF10
AF12
AF14
AF16
AF18
AF8
D18
D20
D22
D6
D8
E17
E19
E21
E5
E7
E9
F18
F20
F22
F6
F8
G21
Layout Note:
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
BGA479-SKT6-GPU1
62.10079.001
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCCA0
VCCA1
VCCA2
VCCA3
VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCQ0
VCCQ1
VID0
VID1
VID2
VID3
VID4
VID5
VCCSENSE
VSSSENSE
VCCSENSE and VSSSENSE lines
should be of equal length.
Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
G5
H22
H6
J21
J5
K22
U5
V22
V6
W21
W5
Y22
Y6
F26
B1
N1
AC26
D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L21
L5
M22
M6
N21
N5
P22
P6
R21
R5
T22
T6
U21
P23
W4
E2
F2
F3
G3
G4
H4
AE7
AF6
VCC_CORE
TP_VCCA1
TP_VCCA2
TP_VCCA3
CPU_D10
TP_VCCSENSE
TP_VSSSENSE
DY
NO STUFF NO STUFF
At Dothan 400Mhz CPU application, POWER is 1.8V.
At Dothan 533Mhz CPU application, POWER is 1.5V.
At Celeron CPU .13 application, POWER is 1.8V.
At Celeron CPU .09 application, POWER is 1.5V.
12
C130
SCD01U16V2KX
TP45 TPAD30
TP44 TPAD30
TP142 T PAD30
R139 0R2-0.
1 2
H_VID0 38
H_VID1 38
H_VID2 38
H_VID3 38
H_VID4 38
H_VID5 38
12
R151
54D9R2F
12
R147
54D9R2F
VCC_CORE
12
VCC_CORE
12
12
DY
12
C479
SC10U6D3V5MX
12
C194
SC10U6D3V5MX
B
R102
1 2
0R3-U
C128
SC10U6D3V5MX
+1.05VRUN
270u *4
10u *35
12
C493
C480
SC10U6D3V5MX
12
C195
C214
SC10U6D3V5MX
+1.5VRUN
12
SC10U6D3V5MX
12
SC10U6D3V5MX
C
+1.05VRUN
12
12
12
C184
C200
SC10U6D3V5MX
SC10U6D3V5MX
12
12
C168
C481
SC10U6D3V5MX
SC10U6D3V5MX
0.1u *10
12
C212
C211
SCD1U10V2KX
SCD1U10V2KX
12
12
C190
C163
SC10U6D3V5MX
SC10U6D3V5MX
12
12
C177
C175
SC10U6D3V5MX
SC10U6D3V5MX
150u *1
12
12
C210
C192
SCD1U10V2KX
12
C140
C164
SC10U6D3V5MX
SC10U6D3V5MX
12
C193
C169
SC10U6D3V5MX
SC10U6D3V5MX
12
C188
SCD1U10V2KX
12
C196
SC10U6D3V5MX
12
C191
SC10U6D3V5MX
12
12
C181
SCD1U10V2KX
Dummy 2 by layout
12
12
C151
SCD1U10V2KX
12
C167
C492
SC10U6D3V5MX
SC10U6D3V5MX
12
C201
C165
SC10U6D3V5MX
SC10U6D3V5MX
12
C152
SCD1U10V2KX
SCD1U10V2KX
12
12
C198
SC10U6D3V5MX
12
12
C170
SC10U6D3V5MX
12
C187
SCD1U10V2KX
12
C202
SC10U6D3V5MX
12
C180
SC10U6D3V5MX
12
12
C482
C171
TC9
ST220U2D5VD
C153
SCD1U10V2KX
12
12
C204
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
D
12
C495
C172
SC10U6D3V5MX
12
C494
SC10U6D3V5MX
SC10U6D3V5MX
BGA479-SKT6-GPU1
62.10079.001
12
C199
SC10U6D3V5MX
<Core Design>
A11
A14
A17
A20
A23
A26
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
B12
B16
B19
B22
B25
C10
C13
C15
C18
C21
C24
D11
U47D
A2
VSS0
A5
VSS1
A8
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
B3
VSS75
B6
VSS76
B9
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
C1
VSS83
C4
VSS84
C7
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
D2
VSS92
D5
VSS93
D7
VSS94
D9
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
E
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Re v
A3
A
B
C
D
Date: Sheet of
CPU (2 of 2)
Barbados
544Thursday, May 12, 2005
SD
E
A
H_XRCOMP
12
R413
24D9R2F
4 4
+1.05VRUN
R131
54D9R2F
1 2
H_XSCOMP
+1.05VRUN
12
R407
221R3F
H_XSWING
3 3
2 2
12
R409
100R2F
12
R398
24D9R2F
+1.05VRUN
R406
54D9R2F
1 2
+1.05VRUN
12
R402
221R3F
12
R401
100R2F
H_YRCOMP
H_YSCOMP
H_YSWING
12
C474
SCD1U10V2KX
12
C459
SCD1U10V2KX
B
H_D#[63..0]4
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
C
U43A
E4
HD0#
E1
HD1#
F4
HD2#
H7
HD3#
E2
HD4#
F1
HD5#
E3
HD6#
D3
HD7#
K7
HD8#
F2
HD9#
J7
HD10#
J8
HD11#
H6
HD12#
F3
HD13#
K8
HD14#
H5
HD15#
H1
HD16#
H2
HD17#
K5
HD18#
K6
HD19#
J4
HD20#
G3
HD21#
H3
HD22#
J1
HD23#
L5
HD24#
K4
HD25#
J5
HD26#
P7
HD27#
L7
HD28#
J3
HD29#
P5
HD30#
L3
HD31#
U7
HD32#
V6
HD33#
R6
HD34#
R5
HD35#
P3
HD36#
T8
HD37#
R7
HD38#
R8
HD39#
U8
HD40#
R4
HD41#
T4
HD42#
T5
HD43#
R1
HD44#
T3
HD45#
V8
HD46#
U6
HD47#
W6
HD48#
U3
HD49#
V5
HD50#
W8
HD51#
W7
HD52#
U2
HD53#
U1
HD54#
Y5
HD55#
Y2
HD56#
V4
HD57#
Y7
HD58#
W1
HD59#
W3
HD60#
Y3
HD61#
Y6
HD62#
W2
HD63#
C1
HXRCOMP
C2
HXSCOMP
D1
HXSWING
T1
HYRCOMP
L1
HYSCOMP
P1
HYSWING
71.0GMCH.08U
HCPURST#
HOST
HCPUSLP#
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HADSTB#0
HADSTB#1
HVREF
HBNR#
HBPRI#
HBREQ0#
HCLKINN
HCLKINP
HDBSY#
HDEFER#
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDPWR#
HDRDY#
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HEDRDY#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS0#
HRS1#
HRS2#
HTRDY#
G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13
F8
B9
E13
J11
A5
D5
E7
H10
AB1
AB2
C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4
G8
B5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
TP_H_EDRDY#
TP_H_PCREQ#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
D
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_CPURST# 2,4,44
CLK_MCH_BCLK# 3
CLK_MCH_BCLK 3
H_DBSY# 4
H_DEFER# 4
H_DPWR# 4
H_DRDY# 4
TP27 TPAD30
H_HIT# 4
H_HITM# 4
H_LOCK# 4
TP38 TPAD30
H_TRDY# 4
H_A#[31..3]] 4
12
H_DINV#0 4
H_DINV#1 4
H_DINV#2 4
H_DINV#3 4
H_DSTBN#0 4
H_DSTBN#1 4
H_DSTBN#2 4
H_DSTBN#3 4
H_DSTBP#0 4
H_DSTBP#1 4
H_DSTBP#2 4
H_DSTBP#3 4
+1.05VRUN
H_VREF
C154
SCD1U10V2KX
H_REQ#[4..0] 4
H_RS#[2..0] 4
H_CPUSLP# 4,16,44
E
12
R108
100R2F
12
R115
200R2F
1 1
A
Place them near to the chip
B
C
D
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Re v
A3
Date: Sheet
GMCH (1 of 5)
Barbados
644Thursday, May 12, 2005
E
of
SD
A
U43B
DMI_TXN0
4 4
TP12TPAD30
TP16TPAD30
3 3
40D2R2F
2 2
1 1
TP9TPAD30
TP15TPAD30
Layout Note:
Route as short
as possible
12
DY
40D2R2F
R94
+2.5VRUN
R109
1 2
10KR2
R119
1 2
10KR2
+1.8VSUS
12
R87
80D6R2F
12
R88
80D6R2F
12
DY
R93
+0.9VSUS_DDR2VREF
12
SC2D2U6D3V3MX-1
C108
PM_EXTTS#0
PM_EXTTS#1
M_RCOMPN
M_RCOMPP
M_CLK_DDR011
M_CLK_DDR111
M_CLK_DDR312
M_CLK_DDR412
M_CLK_DDR#011
M_CLK_DDR#111
M_CLK_DDR#312
M_CLK_DDR#412
M_OCDCOMP0
M_OCDCOMP1
12
SCD1U10V2KX
SC2D2U6D3V3MX-1
C101
A
DMI_RXN017
DMI_RXN117
DMI_RXN217
DMI_RXN317
DMI_RXP017
DMI_RXP117
DMI_RXP217
DMI_RXP317
M_CKE011,13
M_CKE111,13
M_CKE212,13
M_CKE312,13
M_CS#011,13
M_CS#111,13
M_CS#212,13
M_CS#312,13
M_ODT011,13
M_ODT111,13
M_ODT212,13
M_ODT312,13
12
C109
DMI_TXN017
DMI_TXN117
DMI_TXN217
DMI_TXN317
DMI_TXP017
DMI_TXP117
DMI_TXP217
DMI_TXP317
SCD1U10V2KX
DMI_TXP3
M_RCOMPN
M_RCOMPP
SMXSLEW
SMYSLEW
12
C105
Layout Note:
Keep SMXSLEW and SMYSLEW trace impendance=55 ohm
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
AA31
AB35
AC31
AD35
Y31
AA35
AB31
AC35
AA33
AB37
AC33
AD37
Y33
AA37
AB33
AC37
AM33
AL1
AE11
AJ34
AF6
AC10
AN33
AK1
AE10
AJ33
AF5
AD10
AP21
AM21
AH21
AK21
AN16
AM14
AH15
AG16
AF22
AF16
AP14
AL15
AM11
AN10
AK10
AK11
AF37
AD1
AE27
AE28
AF9
AF10
DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
DMITXN0
DMITXN1
DMITXN2
DMITXN3
DMITXP0
DMITXP1
DMITXP2
DMITXP3
SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5
SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT
71.0GMCH.08U
DMI
PM
DDR MUXING
DREF_SSCLKN
CLK
DREF_SSCLKP
NC
B
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG/RSVD
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PWROK
RSTIN#
DREF_CLKN
DREF_CLKP
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
B
G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25
J23
PM_EXTTS#0
J21
PM_EXTTS#1
H22
F5
AD30
1 2
AE29
A24
A23
C37
D37
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
+1.05VRUN
12
R106
10KR2
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
+1.05VRUN
R98
100R2
12
CPU_SEL1 3,4
CPU_SEL0 3,4
TP20 TPAD30
TP24 TPAD30
TP18 TPAD30
TP35 TPAD30
TP34 TPAD30
TP31 TPAD30
TP30 TPAD30
R128
56R2J
PM_BMBUSY# 17
THERMTRIP_GMCH# 33
PLT_RST1# 1 7,19,20,21,2 9,44
DREFCLK# 3
DREFCLK 3
DREFSSCLK# 3
DREFSSCLK 3
When Low choice
lower than 3.5K
Ohm
R468 DUMMY-R2
1 2
R166 DUMMY-R2
1 2
R158 DUMMY-R2
1 2
R471 2K2R2
1 2
R155 DUMMY-R2
1 2
R154 DUMMY-R2
1 2
R464 DUMMY-R2
1 2
R159 DUMMY-R2
1 2
R470 DUMMY-R2
1 2
R167 DUMMY-R2
1 2
R120 DUMMY-R2
1 2
R467 DUMMY-R2
1 2
R138 DUMMY-R2
1 2
R137 DUMMY-R2
1 2
R465 DUMMY-R2
1 2
C
CFG[2:0] Freq.(MHz)
101 400
001 533
and CTRLDATA pulldowns on-die
GMCH_TV_COMP15
GMCH_TV_LUMA15
GMCH_TV_CRMA15
Layout Note:
Place 150 Ohm
termination resistors
close to GMCH
R125150R2F
1 2
R426150R2F
1 2
R427150R2F
GMCH_VSYNC15
GMCH_HSYNC15
1 2
R116 255R2F
GBKLT_EN29
VGATE_PWRGD 17,35,38,44
3.3V Tolerant
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
C
Alviso will provide SDVO_CTRLCLK
SDVO_DATA
TP21TPAD30
SDVO_CLK
TP19TPAD30
CLK_MCH_3GPLL#3
CLK_MCH_3GPLL3
1 2
12
12
12
R428
R429
R430
150R2F
GMCH_DDCCLK15
GMCH_DDCDATA15
GMCH_BLUE43
GMCH_GREEN43
GMCH_RED43
R455 39R2J
1 2
R456 39R2J
1 2
1 2
R613
DY
1 2
Non Pop R613 For D05 InverterSD
BIA_PWM29
GMCH_BL_ON14,30
TP29TPAD30
TP25TPAD30
TP28TPAD30
CKG6 For DDR/DDR2
CFG[17:3] have internal pullup resistors
CFG[19:18] have internal pulldown resistors
150R2F
150R2F
VSYNC
HSYNC
CRTIREF
0R2-0
CLK_DDC_EDID14
DAT_DDC_EDID14
FPVCC14,30,44
NO STUFF
+2.5VRUN
TXACLK-14
TXACLK+14
TXBCLK-14
TXBCLK+14
TXAOUT0-14
TXAOUT1-14
TXAOUT2-14
TXAOUT0+14
TXAOUT1+14
TXAOUT2+14
TXBOUT0-14
TXBOUT1-14
TXBOUT2-14
TXBOUT0+14
TXBOUT1+14
TXBOUT2+14
When High 1K Ohm
R121 DUMMY-R2
1 2
R122 DUMMY-R2
1 2
R123 DUMMY-R2
1 2
LCTLA_CLK
LCTLB_DATA
LIBG
R113
4K99R2F
L_LVBG
L_VREFH
L_VREFL
H24
H25
AB29
AC29
A15
C16
A17
B15
B16
B17
E24
E23
E21
D21
C20
B20
A19
B19
H21
G21
E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27
B30
B29
C25
C24
B34
B33
B32
A34
A33
B31
C29
D28
C27
C28
D27
C26
J18
J20
CFG18
CFG19
CFG20
D
U43G
SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP
TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC
DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET
LBKLT_CRTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
LACLKN
LACLKP
LBCLKN
LBCLKP
LADATAN0
LADATAN1
LADATAN2
LADATAP0
LADATAP1
LADATAP2
LBDATAN0
LBDATAN1
LBDATAN2
LBDATAP0
LBDATAP1
LBDATAP2
71.0GMCH.08U
D
E
+1.5VRUN
R408
1 2
24D9R2F
LCTLA_CLK
LCTLB_DATA
CLK_DDC_EDID
DAT_DDC_EDID
BIA_PWM
GMCH_BL_ON
LIBG
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
GMCH (2 of 5)
Barbados
R450 2K2R2
1 2
R451 2K2R2
1 2
R452 2K2R2
1 2
R453 2K2R2
1 2
R460 100KR2
1 2
R457 100KR2
1 2
R448 1K5R2F
1 2
744Thursday, May 12, 2005
E
of
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
D36
D34
E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34
D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34
E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
EXP_COMPI
EXP_ICOMPO
MISCTVVGALVDS
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
PCI-EXPRESS GRAPHICS
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
<Core Design>
Title
Size Document Number Re v
A3
Date: Sheet
+2.5VRUN
SD
A
4 4
B
C
D
E
M_A_DQ[63..0]11
3 3
2 2
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
U43C
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
AK15
SA_BS0#
AK16
SA_BS1#
AL21
SA_BS2#
AJ37
SA_DM0
AP35
SA_DM1
AL29
SA_DM2
AP24
SA_DM3
AP9
SA_DM4
AP4
SA_DM5
AJ2
SA_DM6
AD3
SA_DM7
AK36
SA_DQS0
AP33
SA_DQS1
AN29
SA_DQS2
AP23
SA_DQS3
AM8
SA_DQS4
AM4
SA_DQS5
AJ1
SA_DQS6
AE5
SA_DQS7
AK35
SA_DQS0#
AP34
SA_DQS1#
AN30
SA_DQS2#
AN23
SA_DQS3#
AN8
SA_DQS4#
AM5
SA_DQS5#
AH1
SA_DQS6#
AE4
SA_DQS7#
AL17
SA_MA0
AP17
SA_MA1
AP18
SA_MA2
AM17
SA_MA3
AN18
SA_MA4
AM18
SA_MA5
AL19
SA_MA6
DDR SYSTEM MEMORY A
SA_RCVENIN#
SA_RCVENOUT#
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_CAS#
SA_RAS#
SA_WE#
AP20
AM19
AL20
AM16
AN20
AM20
AM15
AN15
AP16
AF29
AF28
AP15
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
TP11 TPAD30
TP10 TPAD30
Place Test PAD Near to Chip
as could as possible
M_A_BS#0 11,13
M_A_BS#1 11,13
M_A_BS#2 11,13
M_A_DM[7..0] 11
M_A_DQS[7..0] 11
M_A_DQS#[7..0] 11
M_A_A[13..0] 11,13
M_A_CAS# 11,1 3
M_A_RAS# 11,1 3
M_A_WE# 11,13
M_B_DQ[63..0]12
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
U43D
SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
AJ15
SB_BS0#
AG17
SB_BS1#
AG21
SB_BS2#
AF32
SB_DM0
AK34
SB_DM1
AK27
SB_DM2
AK24
SB_DM3
AJ10
SB_DM4
AK5
SB_DM5
AE7
SB_DM6
AB7
SB_DM7
AF34
SB_DQS0
AK32
SB_DQS1
AJ28
SB_DQS2
AK23
SB_DQS3
AM10
SB_DQS4
AH6
SB_DQS5
AF8
SB_DQS6
AB4
SB_DQS7
AF35
SB_DQS0#
AK33
SB_DQS1#
AK28
SB_DQS2#
AJ23
SB_DQS3#
AL10
SB_DQS4#
AH7
SB_DQS5#
AF7
SB_DQS6#
AB5
SB_DQS7#
AH17
SB_MA0
AK17
SB_MA1
AH18
SB_MA2
AJ18
SB_MA3
AK18
SB_MA4
AJ19
SB_MA5
AK19
SB_MA6
AH19
SB_MA7
AJ20
SB_MA8
DDR SYSTEM MEMORY B
SB_RCVENIN#
SB_RCVENOUT#
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_CAS#
SB_RAS#
SB_WE#
AH20
AJ16
AG18
AG20
AG15
AH14
AK14
AF15
AF14
AH16
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
TP14 TPAD30
TP13 TPAD30
Place Test PAD Near to Chip
ascould as possible
M_B_BS#0 12,13
M_B_BS#1 12,13
M_B_BS#2 12,13
M_B_DM[7..0] 12
M_B_DQS[7..0] 12
M_B_DQS#[7..0] 12
M_B_A[13..0] 12,13
M_B_CAS# 12,1 3
M_B_RAS# 12,1 3
M_B_WE# 12,13
71.0GMCH.08U
1 1
A
B
C
71.0GMCH.08U
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Re v
A3
D
Date: Sheet
GMCH (3 of 5)
Barbados
844Thursday, May 12, 2005
SD
E
of
A
D13
R142 10R2
1 2
L16 BLM18PG181SN1-1
1 2
+3VRUN
4 4
3 3
L43 BLM18PG181SN1-1
1 2
L44 BLM18PG181SN1-1
1 2
L17 BLM18PG181SN1-1
1 2
SCD1U10V2KX
GAP-CLOSE-PWR
Route ASSATVBG gnd from GMCH to
decoupling cap groung lead and
then connect to the gnd plane
C162
G29
1 2
+1.5V_TVDA
3D3V_TVDACA_S0
12
C197
SCD1U10V2KX
3D3V_TVDACB_S0
12
C518
SCD1U10V2KX
3D3V_TVDACC_S0
12
C522
SCD1U10V2KX
3D3V_ATVBG_S0
12
2 1
+1.5VRUN +1.5VRUN
SSM5818SLPT-GP
12
C203
SCD022U16V2KX
12
C520
SCD022U16V2KX
12
C519
SCD022U16V2KX
12
TVBG_GND
U43E
C512
SCD022U16V2KX
F17
E17
D18
C18
F18
E18
H18
G18
C516
SC10U6D3V5MX
+1.5VRUN_DLVDS
+2.5VRUN_ALVDS
H17
B26
B25
D19
B
1D5V_TVDAC_S0
12
C498
SCD022U16V2KX
VCCDQ_TVDAC_S0
12
C160
SCD022U16V2KX
A25
A35
B22
B21
A21
L35 BLM18PG181SN1-1
1 2
12
C499
SCD1U10V2KX
L36 BLM18PG181SN1-1
1 2
12
C501
SCD1U10V2KX
SCD1U10V2KX
12
C439
SCD1U10V2KX
12
C440
SCD1U10V2KX
V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5
AM37
AH37
AP29
AD28
AD27
AC27
1D5V_TVDAC_S0_1
12
C497
Note: All VCCSM
pins shorted
internally
C436
1 2
SCD1U10V2KX
AK26
AJ26
AP26
AN26
AM26
AL26
C
+1.5VRUN
R439
1 2
R442
1 2
0R3-U
+2.5VRUN
12
C506
SC10U6D3V5MX
12
C98
SCD1U10V2KX
12
12
C120
C117
SCD1U10V2KX
SCD1U10V2KX
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
0R3-U
C489
SCD1U10V2KX
+2.5VRUN +2.5VRUN_ALVDS
R432
1 2
0R3-U
C500
SCD1U10V2KX
12
12
C104
AE18
AE17
AE16
12
C116
SCD1U10V2KX
12
12
C434
SCD1U10V2KX
SC10U6D3V5MX
AE15
AE14
AP13
AN13
AM13
AL13
AK13
+1.5VRUN_DLVDS
12
12
TC14
ST330U2D5VDM
12
DY
TC15
ST330U2D5VDM
C435
SC10U6D3V5MX
AJ13
AH13
AG13
AF13
AE13
AP12
12
C509
SC10U6D3V5MX
12
C502
SCD01U50V3KX
+1.8VSUS
AN12
AM12
AL12
AK12
Note: All VCCSM
pins shorted
internally
C437
1 2
SCD1U10V2KX
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
D
12
SCD1U10V2KX
V1.8_DDR_CAP4
V1.8_DDR_CAP6
AB10
AB9
AP8
AM1
C444
SCD1U10V2KX
12
C102
SCD1U10V2KX
+2.5VRUN
C488
V1.8_DDR_CAP3
AE1
B28
A28
SC10U6D3V5MX
12
AF20
AP19
A27
+1.5VRUN _DDRDLL
C103
SCD1U10V2KX
C468
C510
SC10U6D3V5MX
SCD1U10V2KX
AE37
W37
AF19
AF18
12
+1.5VRUN_3G
12
C119
U37
R37
N37
L37
12
12
12
Y29
J37
L28
1 2
BLM11P300S
TC16
ST100U4VBM-U
12
C457
SC10U6D3V5MX
+1.5VRUN_3GPLL
12
C455
SC10U6D3V5MX
Y27
Y28
G37
F37
E
+1.5VRUN
1 2
TC19
ST220U2D5VD
1 2
12
C173
SCD1U10V2KX
0R1206
L31
+1.5VRUN
+1.5VRUN
+2.5VRUN
R380
BLM18PG181SN1-1
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
D27
VCCP_GMCH_CAP1
12
+1.05VRUN
VCC3G6
C490
SC10U6D3V5MX
VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VSSA_TVBG
VCCA_TVBG
VCCD_TVDAC
VCCA_TVDACC1
VCCDQ_TVDAC
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
0.1uF*6 22nF*6
0.1uF*3 10uF*3
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
2 2
+1.05VRUN
12
12
C150
SC10U6D3V5MX
12
C139
C137
SC10U6D3V5MX
Supply Icc-max
+1.8VRUN
12
SC10U6D3V5MX
Signal Group
VCCSM ?
J29
T29
R29
N29
C133
SCD1U10V2KX
M29
T28
K29
V28
P28
U28
R28
N28
12
C134
SCD1U10V2KX
+1.5VRUN_DDRDLL VCCA_SM 0.1A
+1.5VRUN_3G
/+1.5VRUN_3GPLL
VCC3G/VCCA_3GPLL 1A
+2.5VRUN VCCA_3GBG 0.01A
+1.5VRUN_DLVDS VCCD_LVDS 0.05A
+2.5VRUN_ALVDS VCCA_LVDS 0.02A
+2.5VRUN VCCTX_LVDS 0.05A
1 1
+1.05VRUN VTT 0.81A
+1.05VRUN
+2.5VRUN VCCA_CRTDAC
3D3V_TVDAC
/3D3V_ATVBG_S0
VCC
VCCA_TVDAC
/VCCA_TVBG
3.9A
68mA
120mA
1D5V_TVDAC_S0 VCCD_TVDAC 24mA
+2.5VRUN
VCCHV 0.01A
A
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
0.1uF*2
0.01uF*2
VCC12
VCC13
VCC14
VCC15
VCC16
J28
L28
K28
H28
M28
12
C127
SCD1U10V2KX
+1.5VRUN
VCCA_LVDS
VCC17
G28
V27
VCC18
U27
VCC19
0.1uF*1
10uF*1
VCC20
VCC21
VCC22
VCC23
T27
P27
R27
N27
L39
1 2
L32
1 2
L29
1 2
BLM11A121S
L30
1 2
BLM11A121S
B
M27
VCC24
L27
VCC25
K27
VCC26
J27
VCC27
H27
VCC28
K26
12
12
12
12
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
J25
K25
K24
K23
H26
TC23
ST470U2D5VDM
TC21
ST470U2D5VDM
TC17
ST470U2D5VDM
TC18
ST470U2D5VDM
0.1uF*6 10uF*2 330U*1
POWER
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
T20
K22
K21
K20
U20
W20
12
12
12
12
T18
V19
K19
V18
U19
W18
+1.5VRUN_DPLLA
C496
SCD1U10V2KX
+1.5VRUN_DPLLB
C477
SCD1U10V2KX
+1.5VRUN_HPLL
C118
SCD1U10V2KX
+1.5VRUN_MPLL
C122
SCD1U10V2KX
K18
K17
470u*4 0.1u*4
VCCH_MPLL1
VCCH_MPLL0
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_CRTDAC0
VCCA_CRTDAC1
F19
B23
AC2
AC1
C35
AA1
C
E19
AA2
+2.5VRUN_CRTDAC
10u*1
0.1uF*1
VSSA_CRTDAC
VCC_SYNC
H20
G19
CRTDAC_GND
0.22u*2 0.47u*2
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
J13
K13
K12
V11
U11
W11
SCD22U10V3KX
C513
12
C505
SC10U6D3V5MX
Layout Notes: VSSA_CRTDAC
Route caps within 250mil
of Alviso. Route FB
within 3" of Alviso.
T11
P11
R11
12
L11
N11
M11
BLM18PG181SN1-1
SCD1U10V2KX
C174
1 2
GAP-CLOSE-PWR
12
VTT11
VTT12
VTT13
VTT14
K11
V10
U10
W10
L40
1 2
G55
C161
SCD1U10V2KX
VTT15
VTT16
T10
R10
VCCSM64
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23Y9VTT24W9VTT25U9VTT26R9VTT27P9VTT28N9VTT29M9VTT30L9VTT31J9VTT32N8VTT33M8VTT34N7VTT35M7VTT36N6VTT37M6VTT38A6VTT39N5VTT40M5VTT41N4VTT42M4VTT43N3VTT44M3VTT45N2VTT46M2VTT47B2VTT48V1VTT49N1VTT50M1VTT51
J10
P10
K10
N10
M10
+2.5VRUN
R425
1 2
10R2
Route VSSA_CRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.
D
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
0.1uF*1
4.7uF*1
+1.05V_SYNC
VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3
220u*1
10u*2
100uF*1
0.1uF*1
2 1
SSM5818SLPT-GP
<Core Design>
Title
Size Document Number Re v
A3
Date: Sheet
0.1uF*1
VSSA_3GBG
VCCA_3GBG
VCCA_3GPLL2
VCCA_3GPLL0
VCCA_3GPLL1
10u*1
0.1uF*1
VCCP_GMCH_CAP3
VCCP_GMCH_CAP2
12
C478
SCD47U10VKX
SCD47U10VKX
+1.05VRUN
C149
GMCH (4 of 5)
Barbados
G1
VCCP_GMCH_CAP4
C456
C467
SCD22U10V3KX
12
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SCD22U10V3KX
C131
SC2D2U6D3V 3MX-1
944Thursday, May 12, 2005
E
of
SD
A
H29
G29
F29
E29
D29
A29
AC28
AB28
AA28
W28
E28
AN27
AL27
AJ27
AG27
AF27
AB27
AA27
W27
G27
E27
B27
J26
G26
E26
A26
AN24
U43F
4 4
AL24
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
B
V31
U31
T31
R31
P31
N31
M31
L31
K31
J31
H31
G31
F31
E31
D31
AP30
AE30
AC30
AB30
AA30
Y30
C30
AM29
AJ29
AG29
AD29
AA29
W29
V29
U29
P29
L29
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
W31
C
C34
AL33
AF33
AD33
W33
V33
U33
T33
R33
P33
N33
M33
L33
K33
J33
H33
G33
F33
E33
D33
AN32
AJ32
AD32
AC32
AB32
AA32
Y32
C32
A32
AL31
AG31
AD31
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
D
AJ36
AF36
AE36
AD36
AC36
AB36
AA36
C36
AE35
Y35
W35
V35
U35
T35
R35
P35
N35
M35
L35
K35
J35
H35
G35
F35
E35
D35
B35
AN34
AH34
AD34
AC34
AB34
AA34
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
E
AL36
K37
H37
E37
AN36
VSS7
VSS8
VSS9
VSS10
VSS11
M37
VSS6
P37
VSS5
T37
VSS4
V37
VSS3
Y37
VSS2
AG37
VSS1
VSS0
VSS
71.0GMCH.08U
3 3
2 2
VSSALVDS
B36
U43H
71.0GMCH.08U
Y1
VSS260L2VSS268J2VSS269G2VSS270D2VSS271
+1.8VSUS
AC12
AB12
VCCSM_NCTF30
VCCSM_NCTF31
VSS259P2VSS258T2VSS257V2VSS256
AB13
AD12
VCCSM_NCTF29
VCCSM_NCTF28
VSS255
AE2
AD2
AH2
AD14
AC14
AD13
AC13
VCCSM_NCTF25
VCCSM_NCTF26
VCCSM_NCTF27
+1.05VRUN
VSS254
VSS253
VSS252
VSS251A3VSS250C3VSS249
VSS248
VSS247
VSS246
VSS245C4VSS244H4VSS243L4VSS242P4VSS241U4VSS240Y4VSS239
AA3
AB3
AJ3
AC3
AL2
AN2
AF4
VSS238
VSS237E5VSS236W5VSS235
VSS234
VSS233B6VSS232J6VSS231L6VSS230P6VSS229T6VSS228
AL5
AP5
AN4
AA6
VSS227
VSS226
VSS225
VSS224G7VSS223V7VSS222
VSS221
VSS220
VSS219
VSS218C8VSS217E8VSS216L8VSS215P8VSS214Y8VSS213
AJ6
AE6
AA7
AC6
AK7
AN7
AG7
VSS212A9VSS211H9VSS210K9VSS209T9VSS208V9VSS207
AL8
AA9
VSS206
VSS205
VSS204
VSS203
VSS202
D10
AE9
AC9
AH9
AN9
Place these Hi-Freq decoupling caps near GMCH
VCC_NCTF75
VTT_NCTF1
T17
W13
VCC_NCTF74
VTT_NCTF0
U17
M18
L19
Y18
R18
P18
N18
L18
W17
V17
VCC_NTTF69
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72
VCC_NCTF73
L20
Y19
R19
P19
N19
M19
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
L21
Y20
R20
P20
N20
M20
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
NCTF
VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
L14
M14
N14
T14
P14
R14
U14
Y12
Y13
AA12
AA13
L15
V14
Y14
W14
AA14
AB14
AC15
VCCSM_NCTF13
VCCSM_NCTF14
VCCSM_NCTF15
VCCSM_NCTF16
VCCSM_NCTF17
VCCSM_NCTF18
VCCSM_NCTF19
VCCSM_NCTF20
VCCSM_NCTF21
VCCSM_NCTF22
VCCSM_NCTF23
VCCSM_NCTF24
AD23
AC23
AD22
AC22
VCCSM_NCTF7
VCCSM_NCTF8
VCCSM_NCTF9
VCCSM_NCTF10
VCCSM_NCTF11
VCCSM_NCTF12
VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
L12
T12
P12
N12
R12
M12
AC24
VCCSM_NCTF6
VTT_NCTF12
U12
AD24
VCCSM_NCTF5
VTT_NCTF11
V12
VCCSM_NCTF4
VTT_NCTF10
AC25
W12
VCCSM_NCTF3
VTT_NCTF9
AD26
AC26
AD25
VCCSM_NCTF2
VTT_NCTF8
L13
M13
VCCSM_NCTF1
VTT_NCTF7
N13
VCCSM_NCTF0
VTT_NCTF6
P17
N17
M17
L17
VCC_NCTF76
VCC_NCTF77
VCC_NCTF78
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
T13
P13
V13
R13
U13
AD21
AC21
AD20
AC20
AD19
AC19
AD18
AC18
AD17
AC17
AD16
AC16
AD15
L10
M21
M15
VSS196
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS201
VSS200
VSS199
VSS198
VSS197
J12
J14
F11
Y11
Y10
H11
AJ11
AL11
AF11
AA11
AA10
P21
N21
V21
U21
T21
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF47
VCC_NCTF48
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
T15
P15
N15
R15
U15
AN11
AG11
R22
P22
N22
M22
L22
W21
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
L16
V15
Y15
W15
AA15
AB15
F14
B12
A14
B14
D12
U22
T22
VCC_NCTF39
VCC_NCTF40
VSS_NCTF40
VSS_NCTF39
N16
M16
K14
P23
N23
M23
L23
W22
V22
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
T16
P16
V16
R16
U16
W16
K15
A16
K16
C15
D16
AJ14
AL14
AG14
U23
T23
R23
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
Y16
AA16
AB16
H16
AN14
R24
P24
N24
M24
L24
W23
V23
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
Y17
R17
AA17
AB17
AA18
AB18
AA19
A18
C17
G17
AJ17
AL16
AF17
AN17
N25
M25
L25
W24
V24
U24
T24
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
Y21
R21
AB19
AA20
AB20
AA21
AB21
J19
B18
P25
VCC_NCTF15
VSS_NCTF15
Y22
T19
U18
C19
H19
W19
AL18
V25
U25
T25
R25
VCC_NCTF14
VSS_NCTF14
AA22
M26
L26
W25
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
Y23
Y24
AB22
AA23
AB23
AA24
VCC_NCTF7
VSS_NCTF7
AG19
N26
AB24
VCC_NCTF6
VSS_NCTF6
F20
E20
U26
Y26
VCC_NCTF2
VSS_NCTF2
F21
V20
C21
G20
AK20
+1.05VRUN
W26
V26
VCC_NCTF0
VCC_NCTF1
VSS_NCTF1
VSS_NCTF0
AA26
AB26
A20
D20
AN19
T26
R26
P26
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
Y25
AA25
AB25
J22
A22
E22
D22
H23
AF21
AN21
AL22
AF23
AH22
VSS130
J24
F24
B24
D24
AJ24
AG24
1 1
A
B
C
D
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Re v
A3
Date: Sheet of
GMCH (5 of 5)
Barbados
10 44Thursday, May 12, 2005
E
SD
Please close to Pin 1 as close as possible
+0.9VSUS_DDR2VREF
C393
SC2D2U6D3V 3MX-1
12
12
C384
SCD1U10V2KX
DM1
MH1
M_A_A[13..0]8,13
M_A_BS#28,13
M_A_BS#08,13
M_A_BS#18,13
M_A_DQ[63..0]8
M_CS#07,13
M_CS#17,13
M_CKE07,13
M_CKE17,13
M_A_RAS#8,13
M_A_CAS#8,13
M_A_WE#8,13
SMBC_ICH3,12,19
SMBD_ICH3,12,19
M_ODT07,13
M_ODT17,13
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
SMBC_ICH
SMBD_ICH
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
107
106
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
50
69
83
120
163
110
115
79
80
108
113
109
197
195
114
119
1
201
MH1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16_BA2
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
CS0#
CS1#
CKE0
CKE1
RAS#
CAS#
WE#
SCL
SDA
ODT0
ODT1
VREF
GND
MH2
MH2
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
CK0
CK0#
CK1
CK1#
SA0
SA1
VDD_SPD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NORMAL TYPE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
M_A_DQS0
13
M_A_DQS1
31
M_A_DQS2
51
M_A_DQS3
70
M_A_DQS4
131
M_A_DQS5
148
M_A_DQS6
169
M_A_DQS7
188
M_A_DQS#0
11
M_A_DQS#1
29
M_A_DQS#2
49
M_A_DQS#3
68
M_A_DQS#4
129
M_A_DQS#5
146
M_A_DQS#6
167
M_A_DQS#7
186
M_A_DM0
10
M_A_DM1
26
M_A_DM2
52
M_A_DM3
67
M_A_DM4
130
M_A_DM5
147
M_A_DM6
170
M_A_DM7
185
30
32
164
166
198
200
199
81
82
87
88
95
96
103
104
111
112
117
118
2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
202
M_CLK_DDR0 7
M_CLK_DDR#0 7
M_CLK_DDR1 7
M_CLK_DDR#1 7
12
R361
10KR2
+1.8VSUS
DDR2-200P-8-GP-U
62.10017.861
M_A_DQS[7..0] 8
M_A_DQS#[7..0] 8
M_A_DM[7..0] 8
C364
12
SCD1U10V2KX
R362
10KR2
12
+1.8VSUS
12
12
(REVERSE TYPE)
DIMM 2(BOT side)
ALVISO
(BOT side)
+3VRUN
12
C357
SC2D2U6D3V 3MX-1
DY
SD
Place one cap to each power pin and as close as possible
C395
SC2D2U6D3V 3MX-1
C380
SCD1U10V2KX
12
C383
SC2D2U6D3V 3MX-1
12
C381
SCD1U10V2KX
12
C386
SC2D2U6D3V 3MX-1
12
C385
SCD1U10V2KX
<Core Design>
Title
Size Document Number Re v
A3
Date: Sheet of
DIMM 1(Top side)
12
12
C379
SCD1U10V2KX
12
C387
SC2D2U6D3V 3MX-1
DDR-2 SO-DIMM A
Barbados
(Normal Type)
C388
SC2D2U6D3V 3MX-1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
11 44Thursday, May 12, 2005
SD
??? Use +0.9VRUN or +0.9VSUS_DDR2VREF
Please close to Pin 1 as close as possible
+0.9VSUS_DDR2VREF
C356
SC2D2U6D3V 3MX-1
12
12
C359
SCD1U10V2KX
M_B_A[13..0]8,13
M_B_BS#28,13
M_B_BS#08,13
M_B_BS#18,13
M_B_DQ[63..0]8
M_B_DQS[7..0]8
M_B_DQS#[7..0]8
M_ODT27,13
M_ODT37,13
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
DM2
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
/DQS0
29
/DQS1
49
/DQS2
68
/DQS3
129
/DQS4
146
/DQS5
167
/DQS6
186
/DQS7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
ODT0
119
ODT1
1
VREF
2
VSS
202
GND
NC#163/TEST
108
/RAS
109
/WE
113
/CAS
110
/CS0
115
/CS1
79
CKE0
80
CKE1
30
CK0
32
/CK0
164
CK1
166
/CK1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
SCL
VDDSPD
SA0
SA1
NC#50
NC#69
NC#83
NC#120
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
REVERSE TYPE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
M_B_DM0
10
M_B_DM1
26
M_B_DM2
52
M_B_DM3
67
M_B_DM4
130
M_B_DM5
147
M_B_DM6
170
M_B_DM7
185
195
197
199
198
200
50
69
83
120
163
+1.8VSUS
81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
201
62.10017.871
DDR2-200P-9-GP-U
M_B_RAS# 8,1 3
M_B_WE# 8,13
M_B_CAS# 8,1 3
M_CS#2 7,13
M_CS#3 7,13
M_CKE2 7, 13
M_CKE3 7, 13
M_CLK_DDR3 7
M_CLK_DDR#3 7
M_CLK_DDR4 7
M_CLK_DDR#4 7
SMBD_ICH 3,11,19
SMBC_ICH 3,11,19
M_B_DM[7..0] 8
1 2
12
R338
10KR2
+1.8VSUS
+3VRUN
+3VRUN
12
12
C394
SCD1U10V2KX
C396
SC2D2U6D3V 3MX-1
DY
R337
10KR2
Place one cap to each power pin and as close as possible
12
C362
SC2D2U6D3V 3MX-1
12
C46
SCD1U10V2KX
12
C47
SC2D2U6D3V 3MX-1
12
C48
SCD1U10V2KX
12
C360
SC2D2U6D3V 3MX-1
12
C392
SCD1U10V2KX
<Core Design>
Title
Size Document Number Re v
A3
Date: Sheet of
12
C363
SC2D2U6D3V 3MX-1
12
C391
SCD1U10V2KX
12
C361
SC2D2U6D3V 3MX-1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
DDR-2 SO-DIMM B
Barbados
12 44Thursday, May 12, 2005
SD
PARALLEL TERMINATION
Decoupling Capacitor
Put decap near power(0.9V) and pull-up resistor
RN33 SRN56-2-U2
1
2 3
1
2 3
RN27 SRN56-2-U2
RN25 SRN56-2-U2
1
2 3
1
2 3
RN15 SRN56-2-U2
RN35 SRN56-2-U2
1
2 3
1
2 3
RN26 SRN56-2-U2
RN16 SRN56-2-U2
1
2 3
1
2 3
RN18 SRN56-2-U2
RN10 SRN56-2-U2
1
2 3
1
2 3
RN29 SRN56-2-U2
RN28 SRN56-2-U2
1
2 3
1
2 3
RN12 SRN56-2-U2
RN19 SRN56-2-U2
1
2 3
1
2 3
RN24 SRN56-2-U2
RN23 SRN56-2-U2
1
2 3
1
2 3
RN22 SRN56-2-U2
RN21 SRN56-2-U2
1
2 3
1
2 3
RN20 SRN56-2-U2
RN30 SRN56-2-U2
1
2 3
1
2 3
RN32 SRN56-2-U2
RN31 SRN56-2-U2
1
2 3
1
2 3
RN14 SRN56-2-U2
RN34 SRN56-2-U2
1
2 3
1
2 3
RN36 SRN56-2-U2
RN11 SRN56-2-U2
1
2 3
1
2 3
RN17 SRN56-2-U2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
M_A_A6
M_A_A4
M_B_A0
M_A_A0
M_B_A3
M_B_A1
M_A_A12
M_A_A8
M_A_A5
M_A_A9
M_A_A11
M_A_A7
M_A_A2
M_A_A3
M_B_A2
M_B_A4
M_A_A13
M_A_A10
M_B_A10
M_B_A6
M_B_A8
M_B_A12
M_B_A9
M_A_A1
M_B_A5
M_B_A11
M_B_A7
M_B_A13
M_B_WE# 8,12
M_B_RAS# 8,1 2
M_ODT2 7,12
M_A_WE# 8,11
M_CS#3 7,12
M_CS#0 7,11
M_B_BS#1 8,12
M_A_BS#0 8,11
M_CKE0 7, 11
M_CKE3 7, 12
M_CKE1 7, 11
M_A_BS#2 8,11
M_A_CAS# 8,1 1
M_ODT3 7,12
M_B_CAS# 8,1 2
M_B_BS#0 8,12
M_ODT0 7,11
M_CKE2 7, 12
M_B_BS#2 8,12
M_CS#1 7,11
M_CS#2 7,12
M_A_RAS# 8,1 1
M_A_BS#1 8,11
M_ODT1 7,11
M_A_A[13..0] 8,11
M_B_A[13..0] 8,12
+0.9VRUN+0.9VRUN
12
12
Put decap near power(0.9V)
and pull-up resistor
12
C408
SCD1U10V2KX
12
C418
SCD1U10V2KX
12
C407
C424
SCD1U10V2KX
C420
SCD1U10V2KX
12
C426
SCD1U10V2KX
12
SCD1U10V2KX
12
12
C419
SCD1U10V2KX
12
C429
SCD1U10V2KX
12
C410
SCD1U10V2KX
12
C425
SCD1U10V2KX
12
C411
SCD1U10V2KX
12
C430
C416
SCD1U10V2KX
12
C417
SCD1U10V2KX
12
C428
SCD1U10V2KX
SCD1U10V2KX
12
C402
SCD1U10V2KX
12
C422
SCD1U10V2KX
12
C403
SCD1U10V2KX
C405
12
12
C421
SCD1U10V2KX
<Core Design>
Title
Size Document Number Re v
Date: Sheet of
12
SCD1U10V2KX
12
C399
SCD1U10V2KX
A3
12
C390
SCD1U10V2KX
12
C415
C431
SCD1U10V2KX
DDR-2 TERMINATION / STRAPS
Barbados
12
C427
SCD1U10V2KX
C423
SCD1U10V2KX
SCD1U10V2KX
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
13 44Thursday, May 12, 2005
SD
CAP LED
CAPS_LED#30
NUM LED
NUM_LED#30
SCR LED
SRL_LED#30
HDD LED
HDD_LED#21
WIRLESS LED
LAN_R_ON28
Q29
R2
IN
2
R1
DTA114YKA-1-GP
Q31
R2
IN
2
R1
DTA114YKA-1-GP
Q30
R2
IN
2
R1
DTA114YKA-1-GP
Q32
R2
IN
2
R1
DTA114YKA-1-GP
Q19
R1
2
IN
R2
DDTC144EUA-7F-GP
+3VRUN
1
GND
CAPS_LED_1 CAPS_LED_C
3
OUT
1
GND
NUM_LED_1 NUM_LED_C
3
OUT
1
GND
SRL_LED_1 SRL_LED_C
3
OUT
1
GND
HDD_LED_1# HDD_LED_C#
3
OUT
OUT
3
GND
1
R77
1 2
470R2
+3VRUN
R84
1 2
470R2
+3VRUN
1 2
+3VRUN
1 2
12
C75
SC2200P50V2KX
R76
470R2
R83
1 2
470R2
R360
470R2
HDD_LED_C# 43
BREATH_LED30
BT LED
BT_ACTIVITY32
Q22
OUT
R1
2
IN
R2
DDTC144EUA-7F-GP
Q28
R1
2
IN
R2
DDTC144EUA-7F-GP
3
GND
1
OUT
3
GND
1
1 2
12
C378
SC2200P50V2KX
R78
1 2
680R2
12
C91
SC2200P50V2KX
HDD / BT / CAP / NUM / SCR LED
POWER LED
Q15
R2
IN
BAT1_LED#30
BAT2_LED#30
2
IN
2
1
R1
3
DTA114YKA-1-GP
Q23
R2
1
R1
3
DTA114YKA-1-GP
GND
OUT
GND
BAT2LED
OUT
+5VALW
+5VALW
R357
470R2
SC
BT_ACTIVITY_C#
R354
1 2
470R2
R359
1 2
470R2
BREATH_LED_C#
BAT1LED_C
BAT2LED_CLAN_R_ON_C#
BREATH_LED_C# 43
BAT1LED_C 43
BAT2LED_C 43
+3_3VRTC
+5VRUN
CN1
13
1
12
C92
SCD1U10V2KX
12
C93
SCD1U10V2KX
LID_CL#34
SC
LID_CL#
NUM_LED_C
CAPS_LED_C
SRL_LED_C
LAN_R_ON_C#
BT_ACTIVITY_C#
POWER_SW#29,34
2
3
4
5
6
7
9
8
10
11
12
MLX-CON12-10-GP
14
LAMP_STAT17
LCDVDD
12
+3VRUN
+5VALW
12
12
C376
SC1000P50V
1 2
PBAT_SMBDAT30,43
PBAT_SMBCLK30,43
12
C368
SCD1U10V2KX
C367
SCD1U10V2KX
LCD_TST29
12
+5VRUN
R347
10KR2
1 2
SD
C406
12
SCD1U10V2KX
R352 0R3-U.
C366
SCD1U10V2KX
12
C84
SC4D7U25V-U
SB.
For leakage
R350 0R3-U.
1 2
R348 0R3-U.
1 2
R339 0R3-U.
1 2
LCD_ON
C370
DUMMY-C2
12
12
12
C375
DUMMY-C2
C371
DUMMY-C2
1 2
12
DUMMY-C2
C372
LCD/INVERTER CONN
C389
SC4D7U25V-U
12
C377
SC1000P50V
PBAT_SMBDAT_LCD
PBAT_SMBCLK_LCD
LAMP_STAT_LCD
R336
0R3-U.
12
TXACLK+7
TXACLK-7
TXAOUT2+7
TXAOUT2-7
TXAOUT1+7
TXAOUT1-7
TXAOUT0+7
TXAOUT0-7
TXBCLK+7
TXBCLK-7
TXBOUT2+7
TXBOUT2-7
TXBOUT1+7
TXBOUT1-7
TXBOUT0+7
TXBOUT0-7
SB.
Swap pin define
INV_PWR_SRC
GMCH_BL_ON_LCD
DUMMY-C2
C369
CLK_DDC_EDID_1
DAT_DDC_EDID_1
LCD1
45 46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
JAE-CON44-3-GP
20.F0690.044
D
6
2
DDD
1
3
G
INV_PWR_ SRC_R1
MH1
47
SMB ADDRESS
50h
48
SB.
Swap pin define
49
(New)SMB
ADDRESS
58h
50
51
52
53
MH2
5455
GMCH_BL_ON7,30
FPBACK_EN29
DIFFERENTIAL GND MUST LAY AROUND SIGNAL
AND CAN'T USE THE SAME PATH WITH PWR
GND
Q26SI3457BDV-T1-1GP
45
S
C88
D
Q27
2N7002-8-GP
S
12
INV_PWR_ SRC_R2
1 2
2 3
U52C
9
10
R74
47KR3
1
G
1 2
+3VRUN
+3VSUS
147
PWR_SRC
R73
100KR2
8
SSLVC08APWR-GP
CLK_DDC_EDID7
DAT_DDC_EDID7
LCD_ON 44
LCD_ON
FPVCC7,30,44
SMBUS
Q65 & Q66 connect SMLINK and
SMBUS in S) for SMBus 2.0
compliance
+3VRUN +12V
12
C432
SCD1U10V2KX
+3VALW
1 2
Q64
3
R1
2
12
IN
R373
DUMMY-R3
1
R2
DDTC144EUA-7F-GP
+2.5VRUN
G
1
Q67 2N7002-8-GP
2 3
S
Q66 2N7002-8-GP
6
5 4
D
2
1
G
3
R372
10KR2
OUT
GND
D
G
1
2 3
S
D
Q61
SI3456DV-E3-GP
S
SRN4D7KJ
RN37
14
+3VRUN
3
R364
100KR2
C404
SCD1U16V
D
Q63
1
2N7002-8-GP
G
S
2 3
<Core Design>
Title
Size Document Number Re v
A3
Date: Sheet
R365
150R3
1 2
1 2
12
SC
1
G
2
CLK_DDC_EDID_1CLK_DDC_EDID_1CLK_DDC_EDID_1CLK_DDC_EDID_1CLK_DDC_EDID_1CLK_DDC_EDID_1CLK_DDC_EDID_1CLK_DDC_EDID_1CL K_DDC_EDID_1CLK_DDC_EDID_1
CLK_DDC_EDID_1CLK_DDC_EDID_1CLK_DDC_EDID_1CLK_DDC_EDID_1CLK_DDC_EDID_1
CLK_DDC_EDID_1 44
DAT_DDC_EDID_1DAT_D DC_EDID_1DAT_DDC_EDID_1
LCDVDD
caps place near LCD connector
NEED 60 MIL
12
C414
SC10U6D3V5MX
R366
150R3
1 2
D
Q62
2N7002-8-GP
S
2 3
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
LCD_INVERTER & LED
Barbados
SD
of
14 44Thursday, May 12, 2005
Loading...