Dell Vostro 14 5459 boardview
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Monet 14 " Intel Skylake Platform Block Diagram
8
Channel A
A A
DDR3L SO-DIMM
PAGE 17
1600 MT/s 1.35V
CPU
PEG x 4 (port 5/6)
Skylake - U
GPU
Nvidia
N16S-GM
23mm X 23mm (GB2b-64)
596 ball
PAGE 18~21
Dual Rank
DDR3L (2GB/4GB)
PAGE 22~25
Processor : Dual Core
HDD
PAGE 31
SATA3 6GB /S
Port 7
Power : 15 (Watt)
Package : BGA1356
Size : 42 x 24 * 1.16 (mm)
DMIC*2
B B
DB
HP+MIC Jack
DB
SPEAKER
DB
Audio Codec
Conexant
CX6008
2 Watt
DB
HDA
eDP (X2 lanes)
DDI
PCIE
PCIE
Port 9
Port 6
Giga LAN
Realtek
RTL8111GUS
PAGE 28
NGFF
14" eDP Panel
PAGE 26
HDMI CONN
PAGE 27
RJ45
PAGE 28
WLAN + BT
USB2.0
I2C
USB2.0
Flash ROM
C C
4 MB
PAGE 34
HSPI
Flash ROM
8 MB
Touch Pad
PAGE 34
PAGE 32
SPI
PS/2
EC
ITE
IT8528E
SPI
USB2.0
LPC
Package : LQPF128
K/B
PAGE 33
FAN
PAGE 37 PAGE 35
PAGE 2~16
D D
Port 6
PAGE 30
Card Reader
Port 4
Realtek
RTS5176E
SD3.0
Port 5 Port 7 Port 8
Fingerprint
PAGE 32
USB3.0 port 1/2
USB2.0 port 1/2
USB3.0 port 3
USB2.0 port 3
Camera
DB
PAGE 26
USB3.0 Re-driver
Touch Panel
PAGE 26
PS8713B
SD slot
DB
DB
USB 3.0 port x2
1 for power share
TPS2546ARTER
USB 3.0 CONN
Right
DB
PAGE 30
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4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
Date: Sheet of
Date: Sheet of
5
6
Date: Sheet of
7
PROJECT :
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
AM8
AM8
AM8
1 53
1 53
1 53
8
1A
1A
1A
5
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INT_HDMI_TXN227
INT_HDMI_TXP227
INT_HDMI_TXN127
INT_HDMI_TXP127
HDMI
D D
DDPB_CTRLDATA/ GPP_E19
Display Port B Detected
This signal has a weak internal pull-down.
0 = Port B is not detected.
1 = Port B is detected.
This signal has a weak internal pull-down.
0 = Port C and D is not detected.
1 = Port C and D is detected.
DDPD_CTRLDATA
C C
DDPC_CTRLDATA
R55 *10K_4_NC
R71 *10K_4_NC
eDP_COMPIO and ICOMPO signals should be shorted near
balls and routed with typical impedance <25 mohms
INT_HDMI_TXN027
INT_HDMI_TXP027
INT_HDMI_TXCN27
INT_HDMI_TXCP27
+1.0V_RUN
4
U17A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
HDMI_SCL27
HDMI_SDA27
DDPC_CTRLDATA
DDPD_CTRLDATA
R64 24.9/F_4
EDP_RCOMP
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
SKL_ULT
REV = 1
SKL_ULT
DDI
DISPLAY SIDEBANDS
3
?
Need apply PN
EDP
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
2
C47
INT_EDP_TXN0
C46
INT_EDP_TXP0
D46
INT_EDP_TXN1
C45
INT_EDP_TXP1
A45
B45
A47
B47
E45
INT_EDP_AUXN
F45
INT_EDP_AUXP
B52
EDP_DISP_UTIL
G50
F50
E48
F48
G46
F46
L9
INT_HDMI_HPD
L7
L6
N9
L10
EDP_HPD
R12
eDP_BL_EN
R11
LCD_PWM
U13
DP_ENVDD
?1 OF 20
INT_EDP_TXN0 26
INT_EDP_TXP0 26
INT_EDP_TXN1 26
INT_EDP_TXP1 26
INT_EDP_AUXN 26
INT_EDP_AUXP 26
TP49
INT_HDMI_HPD 27
EDP_HPD 26
eDP_BL_EN 26,35
LCD_PWM 26
DP_ENVDD 26
EDP_HPD
+3.3V_RUN
R56
*10K/F_4_NC
R72
100K_4
1
02
DVT1 CPU P/N list
AJ0QJFCUT04
AJ0QJ8NUT04
CPU(1356P)SKL I3-6100U 2.3G QJFC WINCON
CPU(1356P)SKL I5-6200U 2.3G QJ8N WINCON
AJ0QJ8LRT05 CPU(1356P)SKL I7-6500U 2.5G QJ8L WINCON
SKL_ULT
CPU MISC
?
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
XDP_TCK0
B61
D60
XDP_TDI_CPU
A61
XDP_TDO_CPU
C60
XDP_TMS_CPU
B59
XDP_TRST#_CPU
B56
XDP_TCK1
D59
XDP_TDI
A56
XDP_TDO
C59
XDP_TMS
C61
XDP_TRST#_CPU
A59
XDP_TCK0
XDP_TCK0 2,16
XDP_TDI_CPU 16
XDP_TDO_CPU 16
XDP_TMS_CPU 16
XDP_TRST#_CPU 2,16
XDP_TCK1 16
XDP_TDI 16
XDP_TDO 16
XDP_TMS 16
XDP_TRST#_CPU 2,16
XDP_TCK0 2,16
PDC
4 OF 20
3
2
PLACE NEAR CPU
XDP_TMS_CPU
XDP_TDI_CPU
XDP_TDO_CPU
XDP_TCK0
XDP_TRST#_CPU
XDP_TCK0
XDP_TMS
XDP_TDI
XDP_TDO
XDP_TCK1
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
R296 *51_4_NC
R295 *51_4
R264 51_4
R266 51_4
R265 *51_4_NC
R297*51_4
R26751_4
R29851_4
R29951_4
R272*51_4_NC
Close to Chipset
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
SKL U 1/15 eDP/DDI/MISC
SKL U 1/15 eDP/DDI/MISC
SKL U 1/15 eDP/DDI/MISC
U17D
CATERR#
H_PROCHOT#35,40,41,42
+VCCSTPLL
+1.0V_RUN
B B
+3.3V_SUS
Follow CRB
R294 49.9/F_4
R2901K_4
R37510K_4
CATERR#
H_PROCHOT#
PCH_TP_INTR#
PCH_TP_INTR#33
R250 499/F_4
EC_PECI35
XDP_BPM016
XDP_BPM116
R132 49.9/F_4
R133 49.9/F_4
TP87
TP88
TP50
TP48
TP77
EC_PECI
PROCHOT#
PM_THRMTRIP#
CPU_GP0
CPU_GP1
PCH_TP_INTR#
CPU_GP3
PROC_POPIRCOMP
PCH_OPI_RCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
D63
CATERR#
A54
PECI
C65
PROCHOT#
C63
THERMTRIP#
A65
SKTOCC#
C55
BPM#[0]
D55
BPM#[1]
B54
BPM#[2]
C56
BPM#[3]
A6
GPP_E3/CPU_GP0
A7
GPP_E7/CPU_GP1
BA5
GPP_B3/CPU_GP2
AY5
GPP_B4/CPU_GP3
AT16
PROC_POPIRCOMP
AU16
PCH_OPIRCOMP
H66
OPCE_RCOMP
H65
OPC_RCOMP
SKL_ULT
REV = 1
Close to EC
+VCCSTPLL
A A
R2931K_4
5
PM_THRMTRIP#
4
+1.0V_RUN
+1.0V_RUN
R242
2
112
*SJ0402_NC
AM8
AM8
AM8
1A
1A
2 53
2 53
1
2 53
1A
5
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03
SkyLake ULT Processor (DDR3L)
D D
?
U17B
AL71
M_A_DQ017
M_A_DQ117
M_A_DQ217
M_A_DQ317
M_A_DQ417
M_A_DQ517
M_A_DQ617
M_A_DQ717
M_A_DQ817
M_A_DQ917
M_A_DQ1017
M_A_DQ1117
M_A_DQ1217
M_A_DQ1317
M_A_DQ1417
M_A_DQ1517
C C
M_A_DQ1617
M_A_DQ1717
M_A_DQ1817
M_A_DQ1917
M_A_DQ2017
M_A_DQ2117
M_A_DQ2217
M_A_DQ2317
M_A_DQ2417
M_A_DQ2517
M_A_DQ2617
M_A_DQ2717
M_A_DQ2817
M_A_DQ2917
M_A_DQ3017
B B
M_A_DQ3117
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
IL NIL
SKL_ULT
REV = 1
SKL_ULT
IL:Interleave
NIL:Non-interleave
DDR3L LPDDR3 DDR4
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR3L LPDDR3 DDR4
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
NIL-DDR CH A
2 OF 20
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
IL NIL
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
M_A_A5
BB54
M_A_A9
BA52
M_A_A6
AY52
M_A_A8
AW52
M_A_A7
AY55
M_A_BS#2
AW54
M_A_A12
BA54
M_A_A11
BA55
M_A_A15
AY54
M_A_A14
AU46
M_A_A13
AU48
AT46
AU50
AU52
AY51
M_A_A2
AT48
AT50
M_A_A10
BB50
M_A_A1
AY50
M_A_A0
BA50
M_A_A3
BB52
M_A_A4
AM70
M_A_DQSN0
AM69
M_A_DQSP0
AT69
M_A_DQSN1
AT70
M_A_DQSP1
AH66
AH65
AG69
AG70
BA64
M_A_DQSN2
AY64
M_A_DQSP2
AY60
M_A_DQSN3
BA60
M_A_DQSP3
AR66
AR65
AR61
AR60
AW50
AT52
DDR0_PAR
AY67
SM_VREF
AY68
SMDDR_VREF_DQ0_M3
BA67
SMDDR_VREF_DQ1_M3
AW67
DDR_VTT_CNTL
M_A_CLKN0 17
M_A_CLKP0 17
M_A_CLKN1 17
M_A_CLKP1 17
M_A_CKE0 17
M_A_CKE1 17
M_A_CS#0 17
M_A_CS#1 17
M_A_DIM0_ODT0 17
M_A_DIM0_ODT1 17
M_A_A5 17
M_A_A9 17
M_A_A6 17
M_A_A8 17
M_A_A7 17
M_A_BS#2 17
M_A_A12 17
M_A_A11 17
M_A_A15 17
M_A_A14 17
M_A_A13 17
M_A_CAS# 17
M_A_WE# 17
M_A_RAS# 17
M_A_BS#0 17
M_A_A2 17
M_A_BS#1 17
M_A_A10 17
M_A_A1 17
M_A_A0 17
M_A_A3 17
M_A_A4 17
M_A_DQSN0 17
M_A_DQSP0 17
M_A_DQSN1 17
M_A_DQSP1 17
M_A_DQSN2 17
M_A_DQSP2 17
M_A_DQSN3 17
M_A_DQSP3 17
TP24
SM_VREF 17
SMDDR_VREF_DQ0_M3 17
TP30
DDR_VTT_CNTL 45
20mils width
U17C
IL NIL
AY39
M_A_DQ3217
M_A_DQ3317
M_A_DQ3417
M_A_DQ3517
M_A_DQ3617
M_A_DQ3717
M_A_DQ3817
M_A_DQ3917
M_A_DQ4017
M_A_DQ4117
M_A_DQ4217
M_A_DQ4317
M_A_DQ4417
M_A_DQ4517
M_A_DQ4617
M_A_DQ4717
M_A_DQ4817
M_A_DQ4917
M_A_DQ5017
M_A_DQ5117
M_A_DQ5217
M_A_DQ5317
M_A_DQ5417
M_A_DQ5517
M_A_DQ5617
M_A_DQ5717
M_A_DQ5817
M_A_DQ5917
M_A_DQ6017
M_A_DQ6117
M_A_DQ6217
M_A_DQ6317
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
SKL_ULT
REV = 1
?
SKL_ULT
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR3L LPDDR3 DDR4
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR3L LPDDR3 DDR4
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
NIL-DDR CH B
3 OF 20
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
IL NIL
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
PDC
DDR1_PAR
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
BA38
M_A_DQSN4
AY38
M_A_DQSP4
AY34
M_A_DQSN5
BA34
M_A_DQSP5
AT38
AR38
AT32
AR32
BA30
M_A_DQSN6
AY30
M_A_DQSP6
AY26
M_A_DQSN7
BA26
M_A_DQSP7
AR25
AR27
AR22
AR21
AN43
AP43
DDR1_PAR
AT13
DDR3_DRAMRST#
AR18
SM_RCOMP_0
AT18
SM_RCOMP_1
AU18
SM_RCOMP_2
M_A_DQSN4 17
M_A_DQSP4 17
M_A_DQSN5 17
M_A_DQSP5 17
M_A_DQSN6 17
M_A_DQSP6 17
M_A_DQSN7 17
M_A_DQSP7 17
TP22
R113 121/F_4
R162 80.6/F_4
R163 100/F_4
+1.35V_SUS
R125
470_4
DDR3_DRAMRST# 17
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
PROJECT :
SKL U 2/15(DDR3L)
SKL U 2/15(DDR3L)
SKL U 2/15(DDR3L)
1
AM8
AM8
AM8
3 53
3 53
3 53
1A
1A
1A
5
www.laptoprepairsecrets.com
4
3
2
1
PLTRST#(CLG)
PLTRST#
D D
R131
100K/F_4
PLTRST# 18,28,30,35
04
PCH Pull-high/low(CLG)
+3.3V_SUS
R12310K_4
R12010K_4
R1581K_4
C C
+3.3V_RUN
R12210K_4
R17110K_4
R154*100K/F_4_NC
*SJ0402_NC
2
B B
A A
R168
PCIE_WAKE#
SYS_RESET#
DSWROK_EC_R
112
5
SUSWARN#
SUSACK#
RSMRST#
DSWROK_EC_RRSMRST#
RSMRST#35
SYS_PWROK35
EC_PWROK35,37
SUSWARN#_EC35
System PWR_OK(CLG)
R305 *0_4_NC
R284 *10K_4_NC
C503 *0.1U/16V_4
R142 *0_4_NC
EC_PWROKSYS_PWROK
4
R143
*SJ0402_NC
2
PLTRST#
SYS_RESET#
RSMRST#
PROCPWRGD
H_VCCST_PWRGD
SYS_PWROK
EC_PWROK
DSWROK_EC_R
SUSWARN#
112
SUSACK#SUSWARN#
PCIE_WAKE#
R253
10K/F_4
U17K
SYSTEM POWER MANAGEMENT
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PW ROK
AR13
GPP_A13/SUSW ARN#/SUSPW RDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
SKL_ULT
REV = 1
SUS_3V3
SUS_3V3
DSW_3P3
DSW_3P3
DSW_3P3
3
SKL_ULT
HWPG16,35,38
?
SUS_3V3
11 OF 20
DSW_3P3
DSW_3P3
DSW_3P3
DSW_3P3
DSW_3P3
DSW_3P3
DSW_3P3
DSW_3P3
DSW_3P3
SUS_3V3
SUS_3V3
GPP_B11/EXT_PW R_GATE#
SUS_3V3
D5 MEK500V-40
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW #
GPP_A11/PME#
INTRUDER#
GPP_B2/VRALERT#
21
?
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
AM10
AM11
+1.0V_RUN
PCH_SLP_S0_N
SLP_SUS#_EC
GPD9
SLP_A#
SIO_PWRBTN#
AC_PRESENT
BATLOW#
INTRUDER#_R
GPP_B2
R261
1K_4
H_VCCST_PWRGD_R
C482
*10P/50V_4
TP94
TP32
TP31
TP21
R260 60.4_4
2
SIO_SLP_S3# 35,45,47
SIO_SLP_S4# 35,45
SIO_SLP_S5# 35,45
TP95
SIO_PWRBTN# 35
AC_PRESENT 35
R1411M_4
PCH Pull-high/low(CLG)
BATLOW#
AC_PRESENT
+RTC_CELL
H_VCCST_PWRGD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROJECT :
SKL U 3/15(PowerManger)
SKL U 3/15(PowerManger)
SKL U 3/15(PowerManger)
R124 10K_4
R159 *10K_4
1
AM8
AM8
AM8
+3.3V_SUS
4 53
4 53
4 53
1A
1A
1A
5
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4
3
2
1
?
SKL_ULT
A30
A34
A39
A44
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AM32
AM33
AM35
AM37
AM38
G30
K32
AK32
AB62
P62
V62
H63
G61
AC63
AE63
AE62
AG62
AL63
AJ62
C202
22U/6.3V_6
U17L
CPU POWER 1 OF 4
VCC_A30
VCC_A34
29A
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30
RSVD_K32
RSVD_AK32
VCCOPC_AB62
VCCOPC_P62
VCCOPC_V62
VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE
VSSOPC_SENSE
VCCEOPIO
VCCEOPIO
VCCEOPIO_SENSE
VSSEOPIO_SENSE
SKL_ULT
REV = 1
C189
22U/6.3V_6
12 OF 20
C227
22U/6.3V_6
C192
22U/6.3V_6
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
PDC
C232
22U/6.3V_6
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
?
C92
1U/6.3V_4
C93
1U/6.3V_4
H_CPU_SVIDALRT#
VR_SVID_CLK_R
H_CPU_SVIDDAT
C167
22U/6.3V_6
C180
1U/6.3V_4
C165
1U/6.3V_4
R65 100/F_4
R66 100/F_4
+VCCSTG
C153
1U/6.3V_4
C87
1U/6.3V_4
C68
1U/6.3V_4
C88
1U/6.3V_4
+VCC_CORE
VCC_SENSE 42
VSS_SENSE 42
C198
1U/6.3V_4
C138
1U/6.3V_4
C81
1U/6.3V_4
C152
1U/6.3V_4
C210
1U/6.3V_4
C69
1U/6.3V_4
C137
1U/6.3V_4
Layout note: need routing together and ALERT need between CLK and DATA.
+VCCSTPLL
CLOSE TO CPU
PLACE THE PU RESISTORS
H_CPU_SVIDALRT#
R263 220/F_4
R249
56.2/F_4
C478
*0.1U/16V_4
SVID ALERT
VR_SVID_ALERT# 42
+VCC_CORE +VCC_CORE
C47
C94
10U/6.3V_4
C59
22U/6.3V_6
C82
22U/6.3V_6
C61
10U/6.3V_4
C91
22U/6.3V_6
22U/6.3V_6
C80
10U/6.3V_4
C208
22U/6.3V_6
C74
22U/6.3V_6
C76
10U/6.3V_4
C474
22U/6.3V_6
C49
22U/6.3V_6
C476
10U/6.3V_4
C64
22U/6.3V_6
C240
10U/6.3V_4
C222
10U/6.3V_4
C58
22U/6.3V_6
22U/6.3V_6
D D
C C
C79
TP27
TP26
C75
22U/6.3V_6
C231
10U/6.3V_4
VCCEOPIO_SENSE
VSSEOPIO_SENSE
C66
22U/6.3V_6
Close U9052
+VCC_CORE
C219
22U/6.3V_6
+VCC_CORE
C166
22U/6.3V_6
05
C271
B B
A A
5
10U/6.3V_4
C272
10U/6.3V_4
4
C273
10U/6.3V_4
C263
10U/6.3V_4
C261
10U/6.3V_4
C262
10U/6.3V_4
C154
10U/6.3V_4
C155
10U/6.3V_4
3
PLACE THE PU RESISTORS
CLOSE TO VR
PULL UP IS IN THE VR MODULE
CLOSE TO CPU
PLACE THE PU RESISTORS
VR_SVID_CLK_R
H_CPU_SVIDDAT
2
R292 0_4
+VCCSTPLL
+VCCSTPLL
R274
*54.9/F_4
SVID CLK
VR_SVID_CLK 42
R251
100/F_4
R262 0_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
SVID DATA
VR_SVID_DATA 42
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
SKL U 4/15 (POWER-1)
SKL U 4/15 (POWER-1)
SKL U 4/15 (POWER-1)
AM8
AM8
AM8
5 53
5 53
1
5 53
1A
1A
1A
5
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4
3
2
1
06
C233
1U/6.3V_4
C144
10U/6.3V_4
+1.0V_RUN
C96
10U/6.3V_4
C50
1U/6.3V_4
+1.0V_RUN
C55
10U/6.3V_4
C83
10U/6.3V_4
C97
10U/6.3V_4
C54
10U/6.3V_4
Under U9052
D D
10U/6.3V_4
C372
C284
10U/6.3V_4
C288
10U/6.3V_4
C286
10U/6.3V_4
C352
10U/6.3V_4
C282
1U/6.3V_4
C356
10U/6.3V_4
Close U9052
+1.0V_RUN
R37 0_6
R117
2
C C
*SJ0603_NC
R34 0_6
+VCCPLL_OC+1.35V_SUS
112
+VCCSTG
+VCCPLL+VCCSTPLL
C354
1U/6.3V_4
*10U/6.3V_4
+1.35V_SUS
1U/6.3V_4
C285
C355
C283
1U/6.3V_4
C270
1U/6.3V_4
+VCCSTPLL
+VCCSTG
+VCCPLL_OC
+VCCPLL
120mA
AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51
AM40
AL23
A18
A22
K20
K21
U17N
VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51
VDDQC
VCCST
VCCSTG_A22
VCCPLL_OC
VCCPLL_K20
VCCPLL_K21
SKL_ULT
REV = 1
SKL_ULT
CPU POWER 3 OF 4
4.5A
0.12A
0.04A
3.5A
0.12A
?
14 OF 20
VCCIO
3.1A
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
4A
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
C65
1U/6.3V_4
+VCCSA
C160
1U/6.3V_4
VCCIO_VCCSENSE
VCCIO_VSSSENSE
VSSSA_SENSE
VCCSA_SENSE
Under U9052 Close U9052
C35
1U/6.3V_4
C245
1U/6.3V_4
C243
10U/6.3V_4
C211
10U/6.3V_4
C223
10U/6.3V_4
C274
1U/6.3V_4
Under U9052
C84
C86
1U/6.3V_4
C234
10U/6.3V_4
C71
C70
1U/6.3V_4
1U/6.3V_4
C224
C95
10U/6.3V_4
10U/6.3V_4
VSSSA_SENSE 42
VCCSA_SENSE 42
C85
1U/6.3V_4
C72
10U/6.3V_4
1U/6.3V_4
C53
10U/6.3V_4
VCCIO_VCCSENSE
VCCIO_VSSSENSE
C205
1U/6.3V_4
C244
10U/6.3V_4
C260
1U/6.3V_4
C98
10U/6.3V_4
Close U9052
R93 100/F_4
R140 100/F_4
Under U9052 Close U9052
+VCCSTG +VCCPLL_OC +VCCPLL
C139
1U/6.3V_4
C287
1U/6.3V_4
Close A18 Ball
+VCCSTPLL
B B
A A
*1U/6.3V_4
C67
*22U/6.3V_6
5
+VCCSTPLL
C52
1U/6.3V_4
1U/6.3V_4
Close to CPU
+1.35V_SUS
C369
10U/6.3V_6
C99
10U/6.3V_6
C336
C366
10U/6.3V_6
C358
10U/6.3V_6
VCCSA_SENSE
VSSSA_SENSE
C357
C360
10U/6.3V_6
10U/6.3V_6
4
C280
1U/6.3V_4
C279
1U/6.3V_4
1U/6.3V_4C51
C373
C353
1U/6.3V_4
3
2
R312 100/F_4
R311 100/F_4
+VCCSA
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROJECT :
SKL U 5/15 (POWER-2)
SKL U 5/15 (POWER-2)
SKL U 5/15 (POWER-2)
AM8
AM8
AM8
6 53
6 53
1
6 53
1A
1A
1A
5
www.laptoprepairsecrets.com
4
3
2
1
?
SKL_ULT
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
M62
N63
N64
N66
N67
N69
A48
A53
A58
A62
A66
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
J70
J69
U17M
CPU POWER 2 OF 4
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
SKL_ULT
REV = 1
31A
PDC
13 OF 20
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
+VCCGT
C214
10U/6.3V_4
C162
10U/6.3V_4
C195
1U/6.3V_4
C164
1U/6.3V_4
C196
10U/6.3V_4
C141
10U/6.3V_4
C212
1U/6.3V_4
C157
1U/6.3V_4
+VCCGT
VCCGT_SENSE42
VSSGT_SENSE42
C236
10U/6.3V_4
C258
10U/6.3V_4
C185
1U/6.3V_4
C228
1U/6.3V_4
C142
10U/6.3V_4
C163
10U/6.3V_4
C194
1U/6.3V_4
C143
1U/6.3V_4
R58100/F_4
R57100/F_4
C248
1U/6.3V_4
C213
1U/6.3V_4
C140
10U/6.3V_4
C247
10U/6.3V_4
C201
1U/6.3V_4
C156
1U/6.3V_4
D D
C C
B B
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
+VCCGT
Close U9052Under U9052
C187
22U/6.3V_6
C253
22U/6.3V_6
C186
22U/6.3V_6
C174
22U/6.3V_6
C254
22U/6.3V_6
C259
22U/6.3V_6
C207
22U/6.3V_6
C218
22U/6.3V_6
C242
22U/6.3V_6
C191
22U/6.3V_6
C221
22U/6.3V_6
C252
22U/6.3V_6
C226
22U/6.3V_6
C255
22U/6.3V_6
C217
22U/6.3V_6
C188
22U/6.3V_6
C251
22U/6.3V_6
C216
22U/6.3V_6
07
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
PROJECT :
SKL U 6/15 (POWER-3)
SKL U 6/15 (POWER-3)
SKL U 6/15 (POWER-3)
AM8
AM8
AM8
1A
1A
7 53
7 53
1
7 53
1A
5
www.laptoprepairsecrets.com
4
3
2
1
08
U17R
?
D D
C C
B B
SKL_ULT
GND 3 OF 3
F8
VSS
G10
VSS
G22
VSS
G43
VSS
G45
VSS
G48
VSS
G5
VSS
G52
VSS
G55
VSS
G58
VSS
G6
VSS
G60
VSS
G63
VSS
G66
VSS
H15
VSS
H18
VSS
H71
VSS
J11
VSS
J13
VSS
J25
VSS
J28
VSS
J32
VSS
J35
VSS
J38
VSS
J42
VSS
J8
VSS
K16
VSS
K18
VSS
K22
VSS
K61
VSS
K63
VSS
K64
VSS
K65
VSS
K66
VSS
K67
VSS
K68
VSS
K70
VSS
K71
VSS
L11
VSS
L16
VSS
L17
VSS
18 OF 20
SKL_ULT
REV = 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
?
AA65
AA68
AB15
AB16
AB18
AB21
AD13
AD16
AD19
AD20
AD21
AD62
AE64
AE65
AE66
AE67
AE68
AE69
AF10
AF15
AF17
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH63
AH64
AH67
AJ15
AJ18
AJ20
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AL28
AL32
AL35
AL38
AL45
AL48
AL52
AL55
AL58
AL64
A67
A70
AA2
AA4
AB8
AD8
AF1
AF2
AF4
AH6
AJ4
AK8
AL2
AL4
U17P
?
SKL_ULT
GND 1 OF 3
A5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
16 OF 20
SKL_ULT
REV = 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
?
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
BA10
BA14
BA18
BA23
BA28
BA32
BA36
BA45
U17Q
SKL_ULT
?
GND 2 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AV1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B10
VSS
B14
VSS
B18
VSS
B22
VSS
B30
VSS
B34
VSS
B39
VSS
B44
VSS
B48
VSS
B53
VSS
B58
VSS
B62
VSS
B66
VSS
B71
VSS
BA1
VSS
VSS
VSS
VSS
BA2
VSS
VSS
VSS
VSS
VSS
F68
VSS
VSS
17 OF 20
SKL_ULT
REV = 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PDC
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
?
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
PROJECT :
SKL U 7/15 (GND)
SKL U 7/15 (GND)
SKL U 7/15 (GND)
AM8
AM8
AM8
1A
1A
8 53
8 53
1
8 53
1A
5
www.laptoprepairsecrets.com
D D
5/13 Added test point
CFG0-19 need reserved TP
C C
B B
ITP_PMODE16
4
CFG016
CFG116
CFG216
TP96
TP97
CFG516
CFG616
CFG716
CFG816
CFG916
CFG1016
CFG1116
CFG1216
CFG1316
CFG1416
CFG1516
CFG1616
CFG1716
CFG1816
CFG1916
R63 49.9/F_4
ITP_PMODE
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG_RCOMP
E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
AY2
AY1
K46
K45
AL25
AL27
C71
B70
F60
A52
BA70
BA68
F65
G65
F61
E61
E8
D1
D3
J71
J68
U17S
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
SKL_ULT
REV = 1
SKL_ULT
RESERVED SIGNALS-1
PDC
3
?
19 OF 20
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
TP5
TP6
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
TP4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
TP1
TP2
VSS_AY71
ZVM#
RSVD_TP_AW71
RSVD_TP_AW70
MSM#
PROC_SELECT#
2
?
SKL_ULT
U17T
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
R374 0_4
AY3
D71
C70
C54
D54
AY4
BB3
AY71
AR56
AW71
AW70
AP56
C64
R291 *100K_4_NC
?
AW69
AW68
AU56
AW48
+VCCSTPLL
RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
C7
RSVD_C7
U12
RSVD_U12
U11
RSVD_U11
H11
RSVD_H11
REV = 1
PROC_SELECT# needs to be pulled to VCCST for
Cannon Lake support via 100K ohm resistor and
with no resistor populated (floating pin) for
Skylake.
SKL_ULT
SPARE
20 OF 20
RSVD_F6
RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
?
F6
E3
C11
B11
A11
D12
C12
F52
1
Processor Strapping
A A
5
CFG3
(Physcial Debug Enable)
DFX Privacy
CFG4
(DP Presence Strap)
The CFG signals have a default value of '1' if not terminated on the board.
1 0
Disable: Enable: Set DFX Enable in DFX interface MSR
Disable; No physical DP attached to eDP
4
Enable; An ext DP device is connected to eDP
3
CFG3
CFG4
Circuit
R289 *1K_4_NC
R330 1K_4
2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
SKL U 8/15 (RSV)
SKL U 8/15 (RSV)
SKL U 8/15 (RSV)
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
PROJECT :
1
AM8
AM8
AM8
9 53
9 53
9 53
1A
1A
1A
5
www.laptoprepairsecrets.com
4
3
2
1
?
SUS_3V3
SUS_3V3
SUS_3V3
SKL_ULT
LPC
SUS_3V3
SUS_3V3
SMBUS, SMLINK
SUS_3V3
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A5/LFRAME#/ESPI_CS#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
PDC
5 OF 20
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
?
R7
SMB_PCH_CLK
R8
SMB_PCH_DAT
R10
SMBALERT#
R9
SMB_ME0_CLK
W2
SMB_ME0_DAT
W1
SML0ALERT#
W3
SMB_ME1_CLK
V3
SMB_ME1_DAT
AM7
GPP_B23
AY13
BA13
BB13
AY12
BA12
BA11
AW9
CLK_PCI_EC_R
AY9
CLK_PCI_LPC_R
AW11
CLKRUN#
+3.3V_SUS
LAD0 30,35
LAD1 30,35
LAD2 30,35
LAD3 30,35
LFRAME# 30,35
CLKRUN# 35
SMBALERT# 11
SML0ALERT# 11
TP19
R121 22/F_4
R119 22/F_4
EC16 18P/50V_4
EC15 18P/50V_4
EMI(near PCH)
5/19 Changed resistor value from 2.2K to 4.7K
CLK_24M_KBC 35
LPC_CLK_DEBUG 30
GPIO Pull UP
SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME0_CLK
SMB_ME0_DAT
SMB_ME1_CLK
SMB_ME1_DAT
CLKRUN#
R301 4.7K_4
R300 4.7K_4
R75 499/F_4
R343 2.2K_4TP51
R340 2.2K_4
R134 8.2K/F_4
U17E
GPIO Pull UP
D D
+3.3V_RUN
R15310K_4 R349 499/F_4
EC_RCIN#
R17010K_4
SPI1_MOSI
SPI1_MISO
R331*10K_4_NC
C C
PCH_SPI_CLK34
PCH_SPI_SO34
PCH_SPI_SI34
PCH_SPI_IO234
PCH_SPI_IO334
PCH_SPI_CS0#34
PCH_SPI_CS1#34
SPI1_CLKSERIRQ
TP54
SPI1_MISO
TP52
SPI1_MOSI
SPI1_IO2
TP62
SPI1_IO3
TP64R329*10K_4_NC
SPI1_CS#
TP55
EC_RCIN#35
SERIRQ35
AV2
AW3
AV3
AW2
AU4
AU3
AU2
AU1
AW13
AY11
M2
M3
J4
V1
V2
M1
G3
G2
G1
SPI - FLASH
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - TOUCH
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
C LINK
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
SKL_ULT
REV = 1
10
+3.3V_SUS
+3.3V_RUN
SMBus/Pull-up(CLG)
Q14
B B
SMB_ME1_CLK
SMB_ME1_DAT
4 3
1
2N7002KDW
5
SMBCLK1 35
2
6
SMBDAT1 35
EC side
R2524.7K_4
Q11
4 3
XDP
+3.3V_RUN
SMB_RUN_DAT17
DDR3-L
1
2N7002KDW
A A
5
4
+3.3V_RUN
SMB_RUN_CLK17
R2414.7K_4
3
5
2
6
+3.3V_RUN
SMB_PCH_DAT
SMB_PCH_CLK
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
SKL U 9/15(SPI/LPC/SMBUS)
SKL U 9/15(SPI/LPC/SMBUS)
SKL U 9/15(SPI/LPC/SMBUS)
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
PROJECT :
1
AM8
AM8
AM8
10 53
10 53
10 53
1A
1A
1A
5
www.laptoprepairsecrets.com
4
3
2
1
11
D D
DESIGN NOTE:
WEAK PULL UP RESISTOR PRESENT ON THIS NET
ACZ_SPKR14,32
C C
SMBALERT#10 GPP_B1814
B B
GSPI1_MOSI14
ACZ_SPKR
GSPI1_MOSI
R383
*20K/F_4
+3.3V_SUS
R60
*1K_4_NC
R61
*20K/F_4_NC
R126
*20K/F_4
Functional Strap Definitions
ACZ_SDOUT14
PCH_MELOCK35
SML0ALERT#10
Change to 150K_1%
ACZ_SDOUT
R155 1K_4
GPP_B18SMBALERT#
+3.3V_SUS
SML0ALERT#
Top-Block Swap Override:
HIGH - TOP SWAP ENABLE
LOW-DISABLED
HIGH: LPC SELECTED FOR SYSTEM FLASH
WEAK INTERNAL PD
This signal has a weak internal pull-down.
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality). (Default)
1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). Must be
pulled up to support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS.
Notes:
1. The internal pull-down is disabled after RSMRST#
de-asserts.
2. This signal is in the primary well.
BIOS Strap Bit(BBS):
The signal has a weak internal pull-down.
This field determines the destination of accesses to the
BIOS memory range. Also controllable using Boot BIOS
Destination bit (Chipset Configuration Registers: Offset
3410h:Bit 10). This strap is used in conjunction with Boot
BIOS Destination Selection 0 strap.
Bit 10 Boot BIOS Destination
0 SPI
1 LPC
+3.3V_RUN
R156
*4.7K_4
ACZ_SDOUT
+3.3V_RUN
R138
*4.7K_4
R139
10K_4
R347
*10K_4
R344
20K/F_4
Flash Descriptor Security Override:
The signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash
Descriptor.
1 = Disable Flash Descriptor Security (override). This
strap should only be asserted high using external
pull-up in manufacturing/debug environments ONLY.
This function is useful when running ITP/XDP.
The signal has a weak internal pull-down.
0 = Disable “No Reboot” mode. (Default)
1 = Enable “No Reboot” mode (PCH will disable the TCO
Timer system reboot feature). This function is useful
when running ITP/XDP.
Notes:
1. The internal pull-down is disabled after PLTRST# deasserts.
2. This signal is in the primary well.
This signal has a weak internal pull-down.
0 = LPC Is selected for EC. (Default)
1 = eSPI Is selected for EC.
Notes:
1. The internal pull-down is disabled after RSMRST#
de-asserts.
2. This signal is in the primary well.
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
SKL U 10/15(HDA)
SKL U 10/15(HDA)
SKL U 10/15(HDA)
Monday, May 25, 2015
Monday, May 25, 2015
Monday, May 25, 2015
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
PROJECT :
AM8
AM8
AM8
1A
1A
11 53
11 53
1
11 53
1A
5
www.laptoprepairsecrets.com
PEG_RXN118
PEG_RXP118
PEG_TXN118
D D
dGPU
WLAN
HDD
C C
LAN
B B
PEG_TXP118
PEG_RXN218
PEG_RXP218
PEG_TXN218
PEG_TXP218
PEG_RXN318
PEG_RXP318
PEG_TXN318
PEG_TXP318
PEG_RXN418
PEG_RXP418
PEG_TXN418
PEG_TXP418
PCIE_RXN6_WLAN30
PCIE_RXP6_WLAN30
PCIE_TXN6_WLAN30
PCIE_TXP6_WLAN30
SATA_RXN032
SATA_RXP032
SATA_TXN032
SATA_TXP032
PCIE_RXN9_LAN28
PCIE_RXP9_LAN28
PCIE_TXN9_LAN28
PCIE_TXP9_LAN28
XDP_PRDY#_CPU16
XDP_PREQ#_CPU16
+3.3V_RUN
C488 Dis@0.22U/10V_4
C485 Dis@0.22U/10V_4
C507 Dis@0.22U/10V_4
C505 Dis@0.22U/10V_4
C501 Dis@0.22U/10V_4
C502 Dis@0.22U/10V_4
C491 Dis@0.22U/10V_4
C492 Dis@0.22U/10V_4
C493 0.1U/16V_4
C494 0.1U/16V_4
C504 0.1U/16V_4
C498 0.1U/16V_4
R321 100/F_4
R118 10K_4
PCIE_TXN6_WLAN_C
PCIE_TXP6_WLAN_C
PCIE_TXN9_LAN_C
PCIE_TXP9_LAN_C
PCIE_RCOMPN
PCIE_RCOMPP
PIRQA#
PEG_TXN1_C
PEG_TXP1_C
PEG_TXN2_C
PEG_TXP2_C
PEG_TXN3_C
PEG_TXP3_C
PEG_TXN4_C
PEG_TXP4_C
BB11
H13
G13
B17
A17
G11
F11
D16
C16
H16
G16
D17
C17
G15
F15
B19
A19
F16
E16
C19
D19
G18
F18
D20
C20
F20
E20
B21
A21
G21
F21
D21
C21
E22
E23
B23
A23
F25
E25
D23
C23
F5
E5
D56
D61
E28
E27
D24
C24
E30
F30
A25
B25
PCI-E Port Mapping Table
PCI-E Port
A A
5
4
U17H
PCIE/USB3/SATA
PCIE1_RXN/USB3_5_RXN
PCIE1_RXP/USB3_5_RXP
PCIE1_TXN/USB3_5_TXN
PCIE1_TXP/USB3_5_TXP
PCIE2_RXN/USB3_6_RXN
PCIE2_RXP/USB3_6_RXP
PCIE2_TXN/USB3_6_TXN
PCIE2_TXP/USB3_6_TXP
PCIE3_RXN
PCIE3_RXP
PCIE3_TXN
PCIE3_TXP
PCIE4_RXN
PCIE4_RXP
PCIE4_TXN
PCIE4_TXP
PCIE5_RXN
PCIE5_RXP
PCIE5_TXN
PCIE5_TXP
PCIE6_RXN
PCIE6_RXP
PCIE6_TXN
PCIE6_TXP
PCIE7_RXN/SATA0_RXN
PCIE7_RXP/SATA0_RXP
PCIE7_TXN/SATA0_TXN
PCIE7_TXP/SATA0_TXP
PCIE8_RXN/SATA1A_RXN
PCIE8_RXP/SATA1A_RXP
PCIE8_TXN/SATA1A_TXN
PCIE8_TXP/SATA1A_TXP
PCIE9_RXN
PCIE9_RXP
PCIE9_TXN
PCIE9_TXP
PCIE10_RXN
PCIE10_RXP
PCIE10_TXN
PCIE10_TXP
PCIE_RCOMPN
PCIE_RCOMPP
PROC_PRDY#
PROC_PREQ#
GPP_A7/PIRQA#
PCIE11_RXN/SATA1B_RXN
PCIE11_RXP/SATA1B_RXP
PCIE11_TXN/SATA1B_TXN
PCIE11_TXP/SATA1B_TXP
PCIE12_RXN/SATA2_RXN
PCIE12_RXP/SATA2_RXP
PCIE12_TXN/SATA2_TXN
PCIE12_TXP/SATA2_TXP
SKL_ULT
REV = 1
Function
Port1
Port2
Port3
Port4
Port5
Port6
Port7
Port8
Port9
Port10
dGPU
dGPU
dGPU
dGPU
NA
WLAN
HDD
NA
LAN
NA
4
?
SKL_ULT
SUS_3V3
PDC
8 OF 20
CLK RQ Port
Port0
Port1
Port2
Port3
Port4
Port5
SSIC / USB3
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB2
SUS_3V3
SUS_3V3
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
SUS_3V3
Function
NA
NA
WLAN
LAN
VGA
NA
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E8/SATALED#
?
3
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
AG4
A9
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
USB30_RX1USB30_RX1+
USB30_TX1USB30_TX1+
USB30_RX2USB30_RX2+
USB30_TX2USB30_TX2+
USB30_RX3USB30_RX3+
USB30_TX3USB30_TX3+
USB2_COMP
R82 113/F_4
USB2_ID
USB_VBUSSENSE
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
DEVSLP0
SIO_EXT_SMI#
SIO_EXT_SCI#
SATAGP0
SATAGP1
SATAGP2
SATA_LED#
USB30_RX1- 29
USB30_RX1+ 29
USB30_TX1- 29
USB30_TX1+ 29
USB30_RX2- 29
USB30_RX2+ 29
USB30_TX2- 29
USB30_TX2+ 29
USB30_RX3- 32
USB30_RX3+ 32
USB30_TX3- 32
USB30_TX3+ 32
5/8 Removed 3D camera function
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP1- 29
USBP1+ 29
USBP2- 29
USBP2+ 29
USBP3- 32
USBP3+ 32
USBP4- 32
USBP4+ 32
USBP5- 32
USBP5+ 32
USBP6- 30
USBP6+ 30
USBP7- 26
USBP7+ 26
USBP8- 26
USBP8+ 26
PLACE 'R10387' WITHIN 500 MILS
FROM USB2_COMP PIN WITH
TRACE IMPEDANCE LESS THAN 0.5 OHMS
USB_OC0# 29
USB_OC1# 32
DEVSLP0 32
SIO_EXT_SMI# 35
SIO_EXT_SCI# 35
SATA_LED# 32
Combo USB3.0 MB-1
Combo USB3.0 MB-2
Combo USB3.0 Small Board, check function
CardReader
FingerPrint
BT
Camera
Touch Screen
USB3.0 Port Mapping Table
USB3.0 Function
PORT-1
PORT-2
PORT-3
USB3.0 MB-1
USB3.0 MB-2 Combine USB3.0 MB-1
Combine USB3.0 Small Board
PORT-4 N/A
USB2.0 Overcurrent Pin Default Usage
Pin Default Port Mapping
USB_OC0#
USB_OC1#
USB_OC2#
Port 2, Port 1
Port 4, Port 3
Port 6, Port 5
USB_OC3# Port 8, Port 7
3
2
USB3.0 (M/B-1)
USB3.0 (M/B-2)
USB3.0 Small Board
2
SATA_LED#
DEVSLP0
SATAGP0
SATAGP1
SATAGP2
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB2_ID
USB_VBUSSENSE
SIO_EXT_SCI#
SIO_EXT_SMI#
R283 10K_4
R273 10K_4
R45 10K_4
R303 10K_4
USB2.0 Port Mapping Table
USB2.0 Function
PORT-1
Combine USB3.0 MB-1
PORT-2
PORT-3
PORT-4
PORT-5
PORT-6
PORT-7
PORT-8
PORT-9
PORT-10
Combine USB3.0 Small Board
CardReader
FingerPrint
BT
Camera
Touch Screen
NC
NC
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROJECT :
SKL U 11/15 (PCIE/USB/SATA)
SKL U 11/15 (PCIE/USB/SATA)
SKL U 11/15 (PCIE/USB/SATA)
1
R324 10K_4
R326 *10K_4_NC
R325 10K_4
R327 10K_4
R323 10K_4
R368 1K_4
R100 1K_4
R10810K_4
R328 10K_4
AM8
AM8
AM8
1
12
+3.3V_SUS
+3.3V_SUS
+3.3V_RUN
12 53
12 53
12 53
1A
1A
1A
5
www.laptoprepairsecrets.com
4
3
2
1
CLK_REQ/Strap Pin(CLG)
+3.3V_RUN
PCIE_CLKREQ_VGA#
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ_LAN#
PCIE_CLKREQ1#
PCIE_CLKREQ5#
D D
PCIE_CLKREQ4#
C C
B B
R128 10K_4
R137 10K_4
R127 10K_4
R129 10K_4
R136 10K_4
R135 10K_4
VGA
WLAN
LAN
?
SKL_ULT
SUS_1V8
SKL_ULT
CLOCK SIGNALS
SUS_3V3
SUS_3V3
SUS_3V3
SUS_3V3
SUS_3V3
SUS_3V3
?
SUS_3V3
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
9 OF 20
10 OF 20
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC_RCOMP
?
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST#
RTCRST#
TBT
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
EMMC_RCLK
AM3
EMMC_CLK
AP4
EMMC_CMD
AT1
EMMC_RCOMP
?
F43
CK_XDP_N_R
E43
CK_XDP_P_R
BA17
E37
XTAL24_IN
E35
XTAL24_OUT
E42
XCLK_BIASREF
AM18
RTC_X1
AM20
RTC_X2
AN18
SRTC_RST#
AM16
RTC_RST#
R44 100/F_4
TP74
TP73
TP76
R372 200/F_4
RP3 *0_4P2R_4_NC
2
1
4
3
R304 2.7K/F_4
+1.0V_SUS
CK_XDP_N 16
CK_XDP_P 16
U17J
A36
B36
C38
D38
C36
D36
A38
B38
C31
D31
C33
D33
A31
B31
A33
B33
A29
B29
C28
D28
A27
B27
C27
D27
D42
C42
AR10
B42
A42
AT7
D41
C41
AT8
D40
C40
AT10
B40
A40
AU8
E40
E38
AU7
CSI2_DN0
CSI2_DP0
CSI2_DN1
CSI2_DP1
CSI2_DN2
CSI2_DP2
CSI2_DN3
CSI2_DP3
CSI2_DN4
CSI2_DP4
CSI2_DN5
CSI2_DP5
CSI2_DN6
CSI2_DP6
CSI2_DN7
CSI2_DP7
CSI2_DN8
CSI2_DP8
CSI2_DN9
CSI2_DP9
CSI2_DN10
CSI2_DP10
CSI2_DN11
CSI2_DP11
U17I
CSI-2
SKL_ULT
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
GPP_B5/SRCCLKREQ0#
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
GPP_B6/SRCCLKREQ1#
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
GPP_B7/SRCCLKREQ2#
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
GPP_B8/SRCCLKREQ3#
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
GPP_B9/SRCCLKREQ4#
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#
SKL_ULT
REV = 1
REV = 1
CLK_VGA_N18
CLK_VGA_P18
PCIE_CLKREQ_VGA#18
CLK_PCIE_WLANN30
CLK_PCIE_WLANP30
PCIE_CLKREQ_WLAN#30
CLK_PCIE_LANN28
CLK_PCIE_LANP28
PCIE_CLKREQ_LAN#28
CLK_VGA_N
CLK_VGA_P
PCIE_CLKREQ_VGA#
PCIE_CLKREQ1#
CLK_PCIE_WLANN
CLK_PCIE_WLANP
PCIE_CLKREQ_WLAN#
CLK_PCIE_LANN
CLK_PCIE_LANP
PCIE_CLKREQ_LAN#
PCIE_CLKREQ4#
PCIE_CLKREQ5#
13
RTC Clock 32.768KHz
+RTC_CELL
C568
12
RTC_RST#
SRTC_RST#
C569
1U/6.3V_4
RTC_RST#
R388
100K_4
31
Q24
2
2N7002W
3
R400 20K/F_4
R403 20K/F_4
R371
10M_4
RTC_X1
1U/6.3V_4
RTC_X2
EC_RTC_RST35
C550 15P/50V_4
C544 15P/50V_4
A A
12
Y3
32.768KHZ
RTC RESET
5
4
External Crystal
2
5/12 Changed C495 and C496 values to 10pF
C495 10P/50V_4
1
XTAL24_IN
XTAL24_OUT
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
R314
24MHZ +-30PPM
1M_4
Y2
4
3
C496 10P/50V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
SKL U 12/15(CLK/EMMC/RTC)
SKL U 12/15(CLK/EMMC/RTC)
SKL U 12/15(CLK/EMMC/RTC)
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
1
AM8
AM8
AM8
13 53
13 53
13 53
1A
1A
1A
5
www.laptoprepairsecrets.com
4
3
2
1
Skylake (GPIO)
?
SUS_3V3
SUS_3V3
SUS_3V3
SUS_3V3
SUS_3V3
SUS_1V8
SUS_3V3
SUS_3V3
SKL_ULT
SUS_3V3
SKL_ULT
SUS_3V3
GPP_D5/ISH_I2C0_SDA
SUS_3V3
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
SUS_3V3
GPP_D8/ISH_I2C1_SCL
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
SUS_1V8
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
SUS_3V3
SUS_3V3
6 OF 20
?
SUS_3V3
SUS_3V3
7 OF 20
GPP_D15/ISH_UART0_RTS#
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_A12/BM_BUSY#/ISH_GP6
SDIO/SDXC
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_G7/SD_WP
GPP_A16/SD_1P8_SEL
SUS_1V8
?
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
SD_RCOMP
GPP_F23
P2
GPP_D9
GPP_D10
GPP_D11
GPP_D12
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
?
DGPU_PWR_EN
P3
DGPU_PWROK
P4
DGPU_HOLD_RST#
P1
M4
ISH_I2C0_SDA
N3
ISH_I2C0_SCL
N1
N2
AD11
AD12
U1
PCH_TEMPALERT#
U2
SML0BDATA
U3
SML0BCLK
U4
SML0BALERT#
AC1
UART1_RXD
AC2
UART1_TXD
AC3
UART1_RTS
AB4
UART1_CTS
AY8
BA8
BB7
BA7
AY7
AW7
AP13
KB_LED_DET
KB_DET#
DCR_EN
BT_RADIO_DIS#
WLAN_OFF#
5/7 Base on 3D CAMERA funciton removed, Removed FW_GPIO net too.
R88 200/F_4
GPP_F23
TP16
DGPU_PWR_EN 48
DGPU_PWROK 20
DGPU_HOLD_RST# 18
TP56
TP53
TP59
TP60
TP61
TP63
TP70
TP67
TP66
TP65
KB_LED_DET 33
KB_DET# 33
DCR_EN 26
BT_RADIO_DIS# 30
WLAN_OFF# 30
DGPU_PWR_EN
DGPU_PWROK
DGPU_HOLD_RST#
PCH_TEMPALERT#
DCR_EN
R333 10K_4
R332 *10K_4_NC
R335 10K_4
R337 *10K_4_NC
R91 *10K_4_NC
U17F
+3.3V_SUS
TP71
TP68
TP72
TP69
GPP_B18
GSPI1_MOSI
UART2_RXD
UART2_TXD
UART2_RTS#
UART2_CTS#
D D
R193 10K_4
R203 10K_4
R364 49.9K_4
R356 49.9K_4
R363 49.9K_4
R357 49.9K_4
I2C0_PCH_DAT
I2C0_PCH_CLK
UART2_RXD
UART2_TXD
UART2_RTS#
UART2_CTS#
Touch Pad
GPP_B1811
GSPI1_MOSI11
I2C0_PCH_DAT33
I2C0_PCH_CLK33
5/18 Removed TP11 and TP12
C C
AH10
AH11
AH12
AF11
AF12
AN8
AP7
AP8
AR7
AM5
AN7
AP5
AN5
AB1
AB2
W4
AB3
AD1
AD2
AD3
AD4
U7
U6
U8
U9
AH9
HDA Bus(CLG)
B B
A A
+3.3V_RUN
ACZ_SYNC_AUDIO32
ACZ_RST#_AUDIO32
ACZ_SDOUT_AUDIO32
BIT_CLK_AUDIO32
47P/50V_4
+3.3V_SUS
R308 10K_4
R276 *10K_4_NC
R169 *1K_4
R172 33_4
R185 33_4
R157 33_4
R176 47_4
C376
GPU_EVENT#
GC6_FB_EN
ACZ_SYNC
ACZ_SYNC
ACZ_RST#
ACZ_SDOUT
ACZ_BCLK
ACZ_SYNC
ACZ_BCLK
ACZ_SDOUT11
ACZ_SDIN032
TP18
TP23
TP17
TP15
GPU_EVENT#21
GC6_FB_EN21
ACZ_SPKR11,32
ACZ_SDOUT
ACZ_SDIN0
ACZ_RST#
SSP2_SFRM
SSP2_SCLK
SSP2_TXD
SSP2_RXD
GPU_EVENT#
GC6_FB_EN
ACZ_SPKR
LPSS ISH
GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI
GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI
GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP_C11/UART0_CTS#
GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS#
GPP_C23/UART2_CTS#
GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL
GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL
GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL
GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL
GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
SKL_ULT
REV = 1
BA22
AY22
BB22
BA21
AY21
AW22
J5
AY20
AW20
AK7
AK6
AK9
AK10
H5
D7
D8
C8
AW5
SUS_3V3
SUS_3V3
SUS_1V8
SUS_1V8
SUS_1V8
U17G
AUDIO
HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD
GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD
GPP_D19/DMIC_CLK0
GPP_D20/DMIC_DATA0
GPP_D17/DMIC_CLK1
GPP_D18/DMIC_DATA1
GPP_B14/SPKR
SKL_ULT
REV = 1
14
+3.3V_SUS
+3.3V_SUS
5
4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
PROJECT :
SKL U 13/15(I2C/GPIO/UART/HDA)
SKL U 13/15(I2C/GPIO/UART/HDA)
SKL U 13/15(I2C/GPIO/UART/HDA)
AM8
AM8
AM8
1A
1A
14 53
14 53
1
14 53
1A
5
www.laptoprepairsecrets.com
4
3
2
1
15
D D
U17O
C215 1U/6.3V_4
+1.0V_SUS
PCH Internal VRM
C C
5/14 For noise issue, added 0.1U decoupling caps(C616)
+3.3V_ALW
+3.3V_SUS
5/14 For noise issue, channged C337 value from 1uF to 0.1uF
B B
+V3.3DX_1.5DX_ADO +1.0V_SUS
+VCCDSW_1.0V
+1.0V_SUS
+1.0V_SUS
+1.0V_SUS
+1.0V_SUS
+1.0V_SUS
R164 *0_4_NC
R165 0_4
+V3.3DX_1.5DX_ADO
+3.3V_SUS
+1.0V_SUS
+3.3V_SUS
+1.0V_SUS
+1.0V_SUS
R130 0_4
C193 1U/6.3V_4
C548 1U/6.3V_4
R42 0_6
C62 1U/6.3V_4
C176 1U/6.3V_4
C56 22U/6.3V_6
R40 0_6
C168 1U/6.3V_4
R41 0_6
C616 0.1U/16V_4
R81 0_6
C241 1U/6.3V_4
C337 0.1U/16V_4
R145 0_6
R84 0_6
C237 1U/6.3V_4
R144 0_6
R336 0_6
R36 0_6
C42 1U/6.3V_4
+3.3V_RUN
C43
*1U/6.3V_4
+VCCPRIM
+VCCMPHYAON_1P0
+VCCAMPHYPLL_1P0
+VCCAPLL_1.0V
+VCCPRIM
+VCCHDA
+VCCSPI
+VCCSRAM_1.0V
+VCCPRIM_3.3V
+VCCPRIM_1.0V
+VCCAPLLEBB
C57
*22U/6.3V_6
AB19
AB20
AF18
AF19
AB17
AD17
AD18
AJ17
AJ19
AJ16
AF20
AF21
AJ21
AK20
P18
V20
V21
AL1
K17
L1
N15
N16
N17
P15
P16
K15
L15
V15
Y18
T19
T20
N18
REV = 1
CPU POWER 4 OF 4
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
DCPDSW_1P0
VCCMPHYAON_1P0
VCCMPHYAON_1P0
VCCMPHYGT_1P0_N15
VCCMPHYGT_1P0_N16
VCCMPHYGT_1P0_N17
VCCMPHYGT_1P0_P15
VCCMPHYGT_1P0_P16
VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0
VCCAPLL_1P0
VCCPRIM_1P0_AB17
VCCPRIM_1P0_Y18
VCCDSW_3P3_AD17
VCCDSW_3P3_AD18
VCCDSW_3P3_AJ17
0.068A
VCCHDA
0.011A
VCCSPI
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCPRIM_3P3_AJ21
VCCPRIM_1P0_AK20
VCCAPLLEBB
SKL_ULT
SKL_ULT
0.026A
0.642A
0.033A
2.574A
0.696A
0.118A
0.075A
0.696A
0.022A
0.154A
?
15 OF 20
VCCPRIM_3P3_V19
VCCPRIM_1P0_T1
0.006A
VCCATS_1P8
VCCRTCPRIM_3P3
VCCRTC_AK19
VCCRTC_BB14
0.035A
0.029A
0.024A
0.033A
0.004A
0.010A
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
?
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
+VCCPGPPA
+VCCPGPPB
+VCCPGPPC
+VCCPGPPD
+VCCPGPPE
+VCCPGPPF
+VCCPGPPG
+VCCPRIM_1.0V
+VCCATS_1.8V
+VCCRTCPRIM_3.3V
DCPRTC
+VCCCLK1
+VCCCLK2
+VCCCLK3
+VCCCLK4
+VCCCLK5
+VCCCLK6
CORE_VID0
CORE_VID1
+VCCPGPPA
+VCCRTCPRIM_3.3V+VCCATS_1.8V +RTC_CELL
C536
1U/6.3V_4
+VCCPGPPB
+VCCPGPPC
+VCCPGPPD
+VCCPGPPE
+VCCPGPPG
+VCCPGPPF
C146 1U/6.3V_4 R352 0_6
R341 0_6
R359 0_6
R360 0_6
C359 0.1U/16V_4
R14 0_6
R24 0_6
R38 0_6
R39 0_6
R25 0_6
R16 0_6
C45 1U/6.3V_4
TP29
TP28
1U/6.3V_4
C531
+3.3V_SUS
+1.0V_SUS
+1.8V_SUS
+3.3V_SUS
+RTC_CELL
+1.0V_SUS
0.1U/16V_4
C367
C368
1U/6.3V_4
C535
0.1U/16V_4
R353 0_6
R339 0_6
R346 0_6
R338 0_6
R345 0_6
R358 0_6
+3.3V_SUS
+1.8V_SUS
+VCCPGPPB +VCCPGPPC +VCCPGPPE
C530
1U/6.3V_4
A A
5
4
3
2
C522
1U/6.3V_4
C521
1U/6.3V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROJECT :
SKL U 14/15(PCH POWER)
SKL U 14/15(PCH POWER)
SKL U 14/15(PCH POWER)
AM8
AM8
AM8
1
15 53
15 53
15 53
1A
1A
1A
5
www.laptoprepairsecrets.com
+1.0V_RUN
4
3
2
+1.0V_SUS
1
"(Pin1-Pin60)" = Intel DG Pin1-Pin60 insch
R317
150/F_4
D D
+3.3V_SUS
+3.3V_RUN
C C
PWR_DEBUG
R227
*10K_4
R2201K_4
C470
*0.1U/16V_4_NC
R229*1K_4_NC
C467
0.1U/16V_4
SIO_PWRBTN#_XDP
SYS_RESET#_XDP
XDP_PREQ#_CPU12
XDP_PRDY#_CPU12
CFG09
CFG19
CFG29
XDP_BPM02
XDP_BPM12
CFG59
CFG69
CFG79
+1.0V_SUS +1.0V_SUS
R316 1K_4
R319 1K_4
TP91
TP90
TP86
TP83
CFG0 PWR_DEBUG
R318 1K_4
TP85
TP92
TP93
XDP_PRESENT_CPUCFG3_XDP
CFG3_XDP
CFG4_XDP
RSMRST#_XDP
SIO_PWRBTN#_XDP
PCH_SPI_SI_XDP
SMB_RUN_DAT_XDP
SMB_RUN_CLK_XDP
XDP_TCK1
XDP_TCK0
CN4
31
XDP Pin#1(PIN1)
32
OBSFN_A0(PIN3)
33
OBSFN_A1(PIN5)
34
GND2(PIN7)
35
OBSDATA_A0(PIN9)
36
OBSDATA_A1(PIN11)
37
GND4(PIN13)
38
OBSDATA_A2(PIN15)
39
OBSDATA_A3(PIN17)
40
GND6(PIN19)
41
OBSFN_B0(PIN21)
42
OBSFN_B1(PIN23)
43
GND8(PIN25)
44
OBSDATA_B0(PIN27)
45
OBSDATA_B1(PIN29)
46
GND10(PIN31)
47
OBSDATA_B2(PIN33)
48
OBSDATA_B3(PIN35)
49
GND12(PIN37)
PWRGOOD/HOOK0(PIN39)50(PIN40)ITPCLK/HOOK4
51
HOOK1(PIN41)
52
VCC_OBS_AB(PIN43)
53
HOOK2(PIN45)
54
HOOK3(PIN47)
55
GND14(PIN49)
56
SDA(PIN51)
57
SCL(PIN53)
58
TCK1(PIN55)
59
TCK0(PIN57)
60
GND16(PIN59)
*Samtec BSH-030-01_NC
CPU XDP
(PIN60)GND17(XDP_PRESENT)
(PIN4)OBSFN_C0
(PIN6)OBSFN_C1
(PIN10)OBSDATA_C0
(PIN12)OBSDATA_C1
(PIN14)GND5
(PIN16)OBSDATA_C2
(PIN18)OBSDATA_C3
(PIN20)GND7
(PIN22)OBSFN_D0
(PIN24)OBSFN_D1
(PIN26)GND9
(PIN28)OBSDATA_D0
(PIN30)OBSDATA_D1
(PIN32)GND11
(PIN34)OBSDATA_D2
(PIN36)OBSDATA_D3
(PIN38)GND13
(PIN42)ITPCLK#/HOOK5
(PIN44)VCC_OBS_CD
(PIN46)RESET#/HOOK6
(PIN48)DBR#/HOOK7
(PIN50)GND15
(PIN54)TRSTN
(PIN2)GND1
(PIN8)GND3
(PIN52)TDO
(PIN56)TDI
(PIN58)TMS
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ITP_PMODE
SYS_RESET#_XDP
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
PCH_SPI_IO2_XDP
CFG17 9
CFG16 9
CFG8 9
CFG9 9
CFG10 9
CFG11 9
CFG19 9
CFG18 9
CFG12 9
CFG13 9
CFG14 9
CFG15 9
TP89
TP84
C472
0.1U/16V_4
CK_XDP_P 13
CK_XDP_N 13
TP45
C471
0.1U/16V_4
ITP_PMODE
PCH_SPI_SI_XDP
ITP_PMODE 9
16
+1.0V_SUS
R30*1K_4_NC
+3.3V_RUN
R228 1K_4
+3.3V_RUN
C516
0.1U/16V_4
U15
14
B B
5/13 Removed APS connector and all signal net
A A
5
HWPG4,35,38
XDP_TDO
XDP_TDI
XDP_TMS
XDP_TRST#
4
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
*SN74CBTLV3126RGYR
1B
2B
3B
4B
DPAD
GND
3
To CPU
3
6
8
11
15
7
XDP_TDO_CPU 2
XDP_TDI_CPU 2
XDP_TMS_CPU 2
XDP_TRST#_CPU 2 XDP_TCK12
5/14 Modified XDP schematic
To PCH_JTAG
XDP_TCK02
XDP_TMS2
XDP_TDI2
XDP_TDO2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
+1.0V_RUN
SKL U 15/15(XDP/APS*)
SKL U 15/15(XDP/APS*)
Friday, May 22, 2015
Friday, May 22, 2015
Friday, May 22, 2015
SKL U 15/15(XDP/APS*)
R232 51_4
R221 *0_4_NC
R235 *0_4_NC
R234 *0_4_NC
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
XDP_TDO
XDP_TCK0
XDP_TMS
XDP_TDI
XDP_TDO
XDP_TDI
XDP_TCK0
XDP_TCK1
AM8
AM8
AM8
16 53
16 53
16 53
1A
1A
1A
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