Dell OptiPlex 7010 Schematics

5

4

3

2

1

Lainikai - MT / DT

1. Index / Block diagram

2. SMBus MAP

3. Clock Distribution

D D

4. Power Delivery Map

5. Power On Sequence

6. Reset / Power Good Map

7. Strap/IRQ/IDSel Table

8. GPIO Table

XDP

9-14. CPU 15-16. DDR3 Conn: CHA

PCIe 16x slot X1

17-18. DDR3 Conn: CHB

19. TBD

20. TBD 21-30. PCH

31. PCH MISC Conn/BUZ/ID 32-33. SIO:SMSC5544 34-35. LAN: INTEL LEWISVILLE

DISPLAY PORT

36-37 AUDIO:ALC269Q

C C

38. Slot1: PCIe 16x

DISPLAY PORT

39. Slot4: PCIe 4x

40. Display Port 1

41. Display Port 2

VGA CONN

42. VGA Conn

43. SATA Conn

PCI Slot X1

44. TBD

45. Rear USB

46. TPM & TCM

47. Thermal Sensor Conn

48. FAN

49. PS2 Conn

PCIe 16x Slot X1 (wired as 4x signal)

PCIe 1x Slot X1

50. COM1

51. SPI

B B

52. XDP

53. Pilot Run Conn

XDP

54. EMI

55. COM2 HDR

56. Front_Panel

57. Front USB 3.0

58. Slot3: PCI

SATA 3.0 CONN X2

59. Slot2: PCIe 1x

60. SATA_MT

SATA 2.0 CONN X1

61. Flexbay USB

62. TBD

63. Power Conn

SATA 2.0 CONN X1

64. Power Sequence 65-66. Power: Linear Power

A A

67-68. Power: Vcore PWM 69-70. Power: VCCIO/VCCSA

71. Power: DDR3/5Vdual/5VUSB

DESIGN APPROVECHECK

Hiko

5

IvanHiko

4

(MT)

SPI ROM 2M+8M

Page 65 ~ 70

VRD12 / VRM / Linear

Page 52

PCIe Gen3 16x

Page 38

DP Link

Page 40

DP Link

Page 41

VGA

Page 42

PCI

Page 58

PCIe Gen2 4x

Page 39

PCIe Gen2 1x

Page 59

Page 52

SATA Port 0/1

Page 43

SATA Port 2

Page 43

SATA Port 3

Page 60

SPI

Page 51

3

Intel PROCESSOR IVY BRIDGE LGA1155

Page 9-14

FDI

DMI

Intel PANTHER Point

Page 21-30

SMSC5545

2

PS2 KB/MS

SERIAL Port

Page 50 Page 49

CHANNEL A DDR3 SDRAM (1333/1600)

Page 15, 16

CHANNEL B DDR3 SDRAM (1333/1600)

Page 17, 18

PCIe 1x

Page 34

USB

HDA

Page 36

LPC

Page 32

Intel Lewisville

Port 8/9 Port 2 ~ 5

Page 45

Port 0/1/10/11

Page 56

Port 12/13

Page 61

ALC269Q

(TCM is just reserved because MRD has removed TCM requirement)

Title

Index / Block diagram

DWG NO Rev

Date: Sheet

Date: Sheet of

Index / Block diagram

Lanikai _MT/DT

DDR3 DIMM 1

DDR3 DIMM 3

DDR3 DIMM 2

DDR3 DIMM 4

Page 35

NIC + USB Ports X 2

Rear USB Ports

2.0x2 3.0x2

Front USB Ports

2.0x2 3.0x2

Internal USB Header X1

Page 37

Rear Audio CONN Line In (MIC In)/Line Out

Front Audio CONN HP Out/ MIC In

Page 56

TPM/TCM

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SMBUS DIAGRAM

SMdata2 SMdclk2

D D

Intel Lewisvillies

LOM

5545 SIO

SMdata1 SMdclk1

R015/RO16RO31/RO32

QO4/QO5

SMBus Controller

SMLINK0

SMLINK1

BUS Switch

RESUME SMBUS

C C

PCH

RX5/RX6

RX3/RX4

RX1/RX2

RX9/RX10

Main SMBUS

CPU-XDP

PCH-XDP

Mini-PCIe 1x

PCIE 16x SMBUS

B B

PCIE 1x SMBUS

PCIE 4x SMBUS

PCI EXPRESS 1x

PCI EXPRESS 16x (wired as 4x signal)

PCI EXPRESS 16x

SLOT 4

SLOT 2

SLOT 1

3

SLOT 3

Title

DWG NO Rev

Date: Sheet

2

Date: Sheet

BLOCK DIAGRAM

Lanikai _MT/DT

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PCI SMBUS

A A

5

PCI SLOT

DIMM SLOTS

4

DDR3 DIMM1 CHA

DDR3 DIMM3 CHA

DDR3 DIMM2 CHB

DDR3 DIMM4 CHB

Address : 0 X00

Address : 0 X02

Address : 0 X04

Address : 0 X06

5

4

3

2

1

H_ITPCLK/H_ITPCLK#

D D

RS204/RS205

CPU XDP

DIMM 2

Channel B

DIMM 4

C_PCH_ITP/C_PCH_ITP#

DIMM 1

Channel A

C_PCI_SB

DIMM 3

25 MHZ

C C

PCH

D3_MA_CLK/CLK#[0:3]

D3_MB_CLK/CLK#[0:3]

32.768 KHZ

Buffer Through Mode

C_PE_100M_MCP/MCP#

CPU

C_PCIEX1_1/C_PCIEX1#_1

C_PCI_SL1

C_PCIEX16_1/C_PCIEX16#_1

C_PCIEX1_2/C_PCIEX1#_2

C_PCIEX4_1/C_PCIEX4#_1

C_SRC1_PCH/C_SRC1_PCH#

MINI PCIe

PCI SLOT

PCI EXPRESS X16

PCI EXPRESS X1

PCI EXPRESS X4

SLOT 3

SLOT 1

SLOT 2

SLOT 4

PCH XDP

B B

25 MHZ

LAN 82579

SUPER IO

A A

5

C_PCIE_L1/L1#

C_LPC_SIO

C_14M_SIO

4

3

C_14M_TPM

C_TPM

C_LPC_TPM

TPM/TCM

LPC HEADER

2

Title

DWG NO Rev

Date: Sheet

Clock Distribution

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POWER DELIVERY MAP

PSU

2X12

S0

+5V

5V

10A

D D

-12V

Deep Sleep : Off

5VSB

3V

12V

+3V

2.4A

+12V

7A

-12V

+5VSB

S0

S5,S0,S3,S4

2X2

+12V_CPU

12V

10.6A

Current listed are for a typical 265W PSU

C C

S0

+5VSB

+3V

+5VSB

S0

S5,S0,S3,S4

+3V_Dual

S5,S0,S3,S4

+3V_Dual Linear Fairchild FAN5078D3 /N AOD452 +/-5% DC + AC

P-FET FDN340P Switch

SLP_SUS_FET#

P-FET FDN340P Switch

SLP_SUS_FET#

4

resistor, empty

H=Power on L=Power off

resistor, empty

H=Power on L=Power off

+3V_Dual

Deep Sleep : Off Default S5,S0,S3,S4

+3V_S5

Default S5,S0,S3,S4

+5V_S5

+3V_S5

S5,S0,S3,S4

+3V_S5

+3V

S0

3

P-FET FDN340P Switch

S_SLP_M#

P-FET FDN340P Switch

S_SLP_S4#

S_PCIAUX_GATE

P-FET SI4835DDY Switch

S_SLP_LAN#

LDO NCP1117STAT3G

resistor, empty

0.016A

H=Power on L=Power off

resistor, empty

S0=1.5A, S3~5=0.45A

H=Power on L=Power off

0.218A

H=Power on L=Power off

resistor, empty

H=Power on L=Power off

0.375A

Deep Sleep : Off

Default : S0 ME : Mx/Moff

+3V_EPW

Deep Sleep : Off Default S5,S0,S3,S4

+3V_PCIAUX

Deep Sleep : Off Default : S0 ME : Mx/Moff

+3V_LAN

+V_1.5V_PCIE

+12V_CPU

S0

2

VCC_CORE ON NCP6153+NCP5901

S0

VRD12 switcher, 4ph SVID 85A TDC; 112A ICCMAX LL = 1.7m ohms

+1P05V_VCCIO

VCC_AXG ON NCP6153+NCP5901 VRD12 switcher, 1ph SVID 25A TDC; 35A ICCMAX LL = 4.1m ohms

+1P05V_VCCIO

VCCIO ON NCP5230 Switcher, 1ph 17A Imax +/-0.5% DC, +/-4.5% AC 1-bit VID(1.05V/1.0V)

+1P05V_PCH

S_SLP_S3#

H=Power on L=Power off

H=Power on

L=Power off H=Power on L=Power off

H=Power on

L=Power off H=Power on L=Power off

1

+VCORE

+1P1V_AXG

+1P05V_VCCIO

S0

DDR3

H = +5V L = +5VSB

S0,S3

Fairchild FAN5078D3 Switcher, 1ph

1.5V, 25A Imax +/- 5% DC+ AC

S0

S_SLP_S4#

S3

H=Power on L=Power off

4

+1P5V_SM

Deep Sleep : Off

Default S5,S0,S3,S4

S0,S3,

+5V_S5

+5VSB

S5,S0,S3,S4

S0

+5V

B B

A A

P SI3457CDV-T1-E3 N AOD452 Switch

B_ATX_PWROK

S_SLP_S3#

5

+5V_DUAL

H=Power on L=Power off

DDR3 Vtt Fairchild FAN5078D3 Linear

0.75V, 1A TDC +/- 5% DC+ AC

PCH Core Linear OP LM358

1.05V,7.5A Imax +/- 5% DC+ AC

S_SLP_S3#

PCH ME (AMT only) Richtek RT8068 Switcher, 1ph

1.05V, 1.8A Imax +/- 5% DC+ AC

S_SLP_M#

H=Power on L=Power off

VCCSA Linear ON NCP102

+1P5V_SM_VTT

+1P05V_PCH

Non-AMT stuff resistor, empty for ME

Default S0 ME : Mx/Moff

+1P05V_ME

3

S0,S3,

S0

+3V

8.8A Imax +/-5% DC + AC 1-bit VID(0.925V/0.85V)

VCCIO_PWRGD

SFR

S0

2

Linear OP LM358

1.8V, 1.6A Imax +/-5% DC + AC

+V_VCCSA

S_SLP_S3#

H=Power on

L=Power off

H=Power on L=Power off

+1P8V_SFR

Title

Power Delivery Map

DWG NO Rev

Date: Sheet

Date: Sheet of

Power Delivery Map

Lanikai _MT/DT

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POWER ON Timing Diagram

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3

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G3 to S4/S5 Timing Diagram

VccRTC

D D

RTCRST#

t200

VCCSUS

RSMRST#

SUSCLK

SLP_S5#

C C

Deep Sleep Entry

DPWROK

SUSWARN#

SUS_PWR_ACK

SLP_SUS#

RSMRST#

+5VDUAL

+5V_S5/+3V_S5

B B

t226

t225

t201

t202

1.05V

Deep Sleep Exit

DPWROK

SLP_SUS#

RSMRST#

+5V_S5/+3V_S5

SUSWARN#

A A

SUS_PWR_ACK

O_PS_ON#

S_SLP_S3#

+12V/+5V

+1P5V_SM

+1P05V_VCCIO

+1P8V_SFR

H_VCCSA_VID

+V_VCCSA

SVIDs

(VIDSOUT/VIDCLK)

+VCORE

SAlert#I VIDALERT#

VR_Ready

Feed into PCH SYS_PWROK

+1P1V_AXG

Srtaps=CFG[x}

S_Thermtrip#

H_SM_DRAMPWRGD

(xxDRAM_PWROK)

D3_RESET#

PWRGD_3V

Feeds into PCH_PWROK

BCLK, PCIe CLKs

UNCOREPWRGOOD

(PROCPWRGD)

S_RLTRST#

DMI

Power rails rise

0.2 – 20ms

Power rails rise

+3V

0.2 – 20ms

=50ms

EN

Note4:Uncorepwergood must be at a valid level during all power states

PCI/PCIe:100ms min

PSU: <=20ms

=500ms

T

VCCSA VID[0] Buffers Output is stable after VccIO Ramp

Uncorepwrgd must be stable (low) at this time

Recommended that VccSA ramp after VCCIO has remped to ensure VCCSA_VID[0] is stable

VSABOOT=SNB Vmax

V

RC

Note5: Core and GT power supplies should not source current during this time.

Note:DDR spec reuqires that DDR_RESET# be asserted during power ramp cycle

IH

T

A

VR:5ms max

CPU SVID buffers are Hi-Z once VCCIO is stable and Uncorepowergood=0

Min 10 PCIe bclks

T

10

CPU:1ms min

PSU

100ms~500ms

T

2

CPU:5ms min, 650ms max

17

T

11

CPU:[x]ms min

PCH t34 (1ms)

Min 10 PCIe bclks

PCH t573

(1, 5, 50, or 100ms)

T

1 CPU: 500us max

T

Uncorepwrgood assertion

MAX TBDns

VCCUSA VID[0] FINAL

Ramp not to exceed 50mV/us

VSAFINAL

Typ 60us

Depends on exact SVID transactions between CPU and VR

MISC

13

Inactive / Disable

Note: PCH THERMAL WATCHDOG TIMER WILL BE DISABLED WITH SNB. SNB WILL NOT EXCEED VR IMAX UNTIL THERMTRIP# IS ENABLED

T

A C K 0

B

A

Set VID

A SLOW Packet

VR:5us max

A

C

K

T

D

0

1

VR:2ms max

T

C

T

VR:1us max

C K 1

GT Ramp will occur after PLTRST#

Strapping option

T

6

CPU:1ms min, 100ms max

E

GETReg status Packet

T

F

VR:min=Te,5ms max

T

12

CPUPWRGOOD

SYS_PWROK(VR_READY)

T

8 CPU: 400us min

A

C

Pay

K

load

0

1

=5ms PCH(t1001)

T

14

Min 10 PCIe bclks

Set VID Packet

T

VR:5us max

Satus Packet

CPU Packet

GT Packet

C

Enable

CPU:[x]ms min

BIOS will deassert DDR_RESET#

PCH: No min/max requirement

AND

PCH t1001 30us, 1, 2or 5ms

=PCH_PWROK & SYS_PWROK & t1001 Timer expired & internal_ready

T

?

DMI training CPU_RESET_DONE

CPU_RESET_DONE_ACK

+5VDUAL

Title

DWG NO Rev

Date: Sheet

5

4

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Date: Sheet

Power On Sequence

Lanikai _MT/DT

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RESET / Power Good MAP

Sequence Signal Name:

O_PWRBTN#IN

(1)

S_SLP_S4# S_SLP_S3#

(2)

D D

O_PSON#

(3)

B_ATX_PWROK

(4)

PCH_MEPWRGD

(5)

S_PCH_SYSPWROK P_VR_READY

(6)

PWRGD_3V

(7)

H_DRAMPWRGD

(8)

H_PWRGD

(9)

S_PLTRST#

(10)

X_PLTRST_PCIE_SLOT# K_PCIRST#_SLOT

(11)

A_Z_RST#

(12)

D3_RESET#

H_RESET#_R S_PLTRST#_R

CPU-XDP

C C

PCH-XDP

F_TP_XDP_RST

Front Panel

O_PWRBTN#IN

S_SLP_M#

(9)

(1)

PROCPWRGD

PWROK

> 1ms

UNCOREPWRGOOD

(9)

CPU-Ivy Bridge

SM_DRAMPWROK

RESET*

(10)

Buffer (UH2)

SM_DRAMRST*

Deep Sleep Exit MAP

Sequence Signal Name:

O_PWRBTN#IN

(D1)

S_SLP_SUS#

(D2)

S_RSMRST#

(D3)

S_SUSWARN#

(D4)

S_SUS_PWR_ACK#

(D5)

(8)

(10)

DDRIII Slots

D3_RESET#

LAN

PE_RST_N

TPM/TCM

LRESET#

(1)

Power On Botton

O_PWRBTN#IN

(1) (1)

(D1)

PWRBTN#

DRAMPWROK

PLTRST# LRESET#

PROCPWRGD

VRD 12

VR_RDY

B B

RESET BUTTON

FP_RST#

HD Audio

RESET#

(12)

(6)

SYS_PWROK

SYS_RESET#

HDA_RST#

AND

PCH

PWROK

SLP_S4# SLP_S4_S5#

SLP_A# IO_SMI#

RSMRST#

(8)

(10)

(2)

(7)

PWR_GOOD_3V

SLP_S3#SLP_S3#

PCI_RST_SYS#

PWRBTN#

SIO-5545

PS_ON#

PWRGD_PS

(4)

(3)

PWR_GOOD_3V

PWRGD_PS

ATX Power

PSON PWROK

100~120ms

(D3)

ME POWER-GOOD CIRCUIT

PCH_MEPWRGD

+1P05V_ME

A A

> 1ms

5

+5VDUAL

SUSACK#

(5)

APWROK

4

SUSACK#

Sequence Logic Circuit

Page.64

SUSWARN#

(D4)(D5)

SLP_SUS#

(D2)

+5V_S5/+3V_S5

SLP_SUS#

Sequence Logic Circuit

Page.64

3

Title

Reset / Power Good Map

DWG NO Rev

Lanikai _MT/DT

Date: Sheet

Date: Sheet of

2

Date: Sheet of

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IRQ Routing Table

INTA# INTB# INTC# INTD# IDSEL REQn# GNTn#

Slot3 A BCD 1800

D D

STRAPPING Table

CPU side

CFG[17:0] Description

[2]

[6:5]

C C

PIN NAME

PCI2/TME (PIN4)

PCI4/SRC5_EN (PIN6)

PCIF5/ITP_EN (PIN7)

B B

PCI3/CFGP (PIN5)

PCI Express static x16 lane numbering reversal

PCI Express Bifurcation

NET

C_CK505_33M_PCI2

C_CK505_33M_PCI4

C_CK505_33M_PCI5

C_CK505_33M_PCI3

1: normal 0: lane numbers reversed

00: 1x8, 2x4 PCI Express 01: reserved

10: 2x8 PCI Express 11: 1x16 PCI Express

Strapping description

Overclocking DISABLED

1

Overclocking ENABLED

0

SRC5

1

CPU_STOP# and PCI_STOP#

0

CPU_ITP

1

SRC8

0

See CFG Table (Set SATA and SRC come from PLL4)

Low

See CFG Table

Mid

See CFG Table

High

Default

DEFAULT

DEFAULT DEFAULT

SIO SMSC5545

PIN NAME

GP070 / PWM4 (PIN127)

DTR1# [TEST_EN] /GP051 (PIN104)

A A

NET

O_SPEAKER

O_DTR1#_R

Strapping description

Disable

Diag_En

1 0 1 0

Enable

Diag_En PE BOOT Loader Strap (DTR1#)= Load from SPI PE BOOT Loader Strap (DTR1#)= No Load from SPI

DEFAULT

PCH

On-Die PLL Voltage Regulator Voltage Select

HDA_SYNC

High

Low

On-Die PLL Voltage Regulator

GPIO28 (IN-PU)

High

Low

Topblock Swap Mode

GNT3#/GPIO55 (IN-PU)

High

Low

No Reboot Mode

SPKR (IN-PD)

High

Low

Integrated 1.05V VRM

INTVRMEN

High

Low

TLS Confidentiality

GPIO15 (IN-PD)

High

Low

Flash Descriptor Override Strap

HDA_SDO

High

Low

DMI Rx Termination Voltage

SPI_MOSI (IN-PD)

Low

DMI Termination Voltage

NV_CLE (IN-PU)

High

Description

1.5V

1.8V

Description

Regulator is enabled.

Regulator is disabled.

Description

Topblock swap mode: Disable

Topblock swap mode: Enable

Description

No reboot mode: Enable

No reboot mode: Disable

Description

Integrated 1.05V VRM: Enable

Integrated 1.05V VRM: Disable

Description

ME Crypto TLS cipher suite with confidentiality

ME Crypto TLS cipher suite with no confidentiality

Description

Flash descriptor security will be override

Disable ME in Manufacturing Mode

Description

DMI Rx Termination Voltage

Description

DMI and FDI Tx/Rx Termination Voltage

DEFAULT

Boot BIOS Destination Selection

GNT1# (IN-PU)

Low

High

Low

High

Deep S4/S5 Well on-die Voltage Regulator Enable

DSWVRMEN

High

Low

Digital Port C Strap

DDPC_CTRLDATA

High

Low

SATA1GP/GP19 (IN-PU)

Low

High

Description

Enable

Disable

Description

Configure Port C

Disable

Description

Flash cycle routed to LPC

Flash cycle routed to PCI

Flash cycle routed to NAND

Flash cycle routed to SPI

DEFAULT

Title

DWG NO Rev

Date: Sheet

Date: Sheet of

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Date: Sheet of

GPIO/IRQ/IDSEL Table

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D D

C C

4

3

2

1

B B

A A

Title

DWG NO Rev

Date: Sheet

5

4

3

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Date: Sheet

GPIO Table

Lanikai _MT/DT

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C_PE_100M_MCP27

C_PE_100M_MCP#27

H_VIDSCLK

RH2 change to 44.2 ;

D D

Change net name to H_RESET#-12/28/09

Add off-page toXDP; CRB 0.7 12/27/09

C C

H_PWRGD

B B

CRB0.7 12/07/09

H_CFG052

*

RH58

RH58 1K

1K

H_VIDSOUT H_VIDALERT#

+1P05V_VCCIO

H_PWRGD24,52,64

H_PM_SYNC23

H_PECI23,32

H_PROCHOT#32,67

H_THERMTRIP#23

H_SKTOCC#23,24

RH10 1.5KDummy

RH10 1.5KDummy RH11 1.5KDummy

RH11 1.5KDummy RH12 1.5KDummy

RH12 1.5KDummy RH13 1.5KDummy

RH13 1.5KDummy RH14 1.5KDummy

RH14 1.5KDummy RH15 1.5KDummy

RH15 1.5KDummy RH16 1.5KDummy

RH16 1.5KDummy RH19 1.5KDummy

RH19 1.5KDummy RH20 1.5KDummy

RH20 1.5KDummy RH22 1.5KDummy

RH22 1.5KDummy RH24 1.5KDummy

RH24 1.5KDummy RH26 1.5KDummy

RH26 1.5KDummy RH28 1.5KDummy

RH28 1.5KDummy RH29 1.5KDummy

RH29 1.5KDummy RH30 1.5KDummy

RH30 1.5KDummy RH31 1.5KDummy

RH31 1.5KDummy RH32 1.5KDummy

RH32 1.5KDummy RH33 1.5KDummy

RH33 1.5KDummy

H_CPU_DIMM_VREF_B18 H_CPU_DIMM_VREF_A16

RH2 44.2Ohm

RH2 44.2Ohm RH1 49.9

RH1 49.9

*

20100709: Reserve RH58 connect H_PWRGD to GND

H_VIDSCLK67

A A

H_VIDSOUT67

H_VIDALERT#67

Remove CH1,CH2-12/29/09

RH39 change to 110 ohm; CRB 0.7-11/30/09

5

*

+/-1%

*

+/-1%Dummy

H_RESET#_R

H_CATERR

H_PROC_SEL H_CFG0

H_CFG1 H_CFG2 H_CFG3 H_CFG4 H_CFG5 H_CFG6 H_CFG7 H_CFG8 H_CFG9 H_CFG10 H_CFG11 H_CFG12 H_CFG13 H_CFG14 H_CFG15 H_CFG16 H_CFG17

RH38

91 Ohm

+/-1%

Dummy

4

*

110Ohm

4

RH39

UH1E

W2

BCLK0

W1

BCLK0*

C37

VIDSCLK

B37

VIDSOUT

A37

VIDALERT*

J40

UNCOREPWRGOOD

F36

RESET*

E38

PM_SYNC

J35

PECI

E37

CATERR*

H34

PROCHOT*

G35

THERMTRIP*

AJ33

SKTOCC*

K32

PROC_SEL

H36

CFG0

J36

CFG1

J37

CFG2

K36

CFG3

L36

CFG4

N35

CFG5

L37

CFG6

M36

CFG7

J38

CFG8

L35

CFG9

M38

CFG10

N36

CFG11

N38

CFG12

N39

CFG13

N37

CFG14

N40

CFG15

G37

CFG16

G36

CFG17

A38

NCTF0

AU40

NCTF1

AW38

NCTF2

C2

NCTF3

D1

NCTF4

AH1

FC_AH1

AH4

FC_AH4

AV1

RSVD_NCTF0

AW2

RSVD_NCTF1

AY3

RSVD_NCTF2

R34

RSVD40

R36

RSVD41

R38

RSVD42

R40

RSVD43

J31

RSVD44

AD34

RSVD45

AD35

RSVD46

K31

RSVD47

PE115527-4041-0DF

+1P05V_VCCIO

*

RH40

75

+/-1%

3

TDO TCK

TMS

TRST* PRDY* PREQ*

DBR*

RSVD36

RSVD0

BPM0* BPM1* BPM2* BPM3* BPM4* BPM5* BPM6* BPM7*

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8

RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35

RSVD37 RSVD38 RSVD39

P34 T2

A36 B36

AB4 AB3

L32 M32

L39 L40

TDI

M40 L38 J39 K38 K40 E39 C40 D40

H40 H38 G38 G40 G39 F38 E40 F40

AB6 AB7 AD37 AE6 AF4 AG4 AJ11 AJ29 AJ30 AJ31 AN20 AP20 AT11 AT14 AU10 AV34 AW34 AY10 C38 C39 D38 H7 H8 J33 J34 J9 K34 K9 L31 L33 L34 L9 M34 N33 N34 P33 P35 P37 P39

20100107: Remove test points

H_VCCIO_SEL

+5V

*

RH37

RH37 10K

10K

*

RH34

4.7K

VCCSA_VID

VCCSA_SENSE

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSSIO_SENSE

VCCAXG_SENSE

VSSAXG_SENSE

MISC

VCCP_SELECT

5/10

*

H_VCCSA_VID 70 H_VCCSA_SENSE 70

H_VCC_SENSE 67 H_VSS_SENSE 67

H_VCCTT_SENSE 69 H_VSSTT_SENSE 69

H_VCCAGX_SENSE 67 H_VSSAGX_SENSE 67

H_TDO 52 H_TDI 52 H_TCK 52 H_TMS 52 H_TRST# 52 H_PRDY# 52 H_PREQ# 52

H_ITPCLK 52 H_ITPCLK# 52

H_BPM#0 52 H_BPM#1 52 H_BPM#2 52 H_BPM#3 52 H_BPM#4 52 H_BPM#5 52 H_BPM#6 52 H_BPM#7 52

H_VCCIO_SEL 69

RO40change reference to RH7 and move from SIO to CPU side ; CRB

0.7-12/29/09

+3V_S5

Add RH66 pull-up to +3V_DUAL; CRB 0.7-12/10/09

H_RESET#32

S_PLTRST#24,32,34,46,52,53

*

RH66

RH66 220

220

+/-5%

Dummy

2

RH4 usage 1kOhm ; CRB 0.7-12/10/09 Removed RH3; CRB 0.7-12/29/09 Dummy RH6 ; CRB 0.7-12/28/09

+1P05V_VCCIO

FP_RST# 24,52,53

RH35 0

*

+3V_DUAL

CH2 0.1uF

16V, X7R, +/-10%

53

UH2

1 2

74AHCT1G08GW

M_NVR_CLE25

RH17 change to 4.7k; CRB 0.7-11/30/09 20100709: Reserve CH11 connect H_PROC_SEL to GND

Removed RH7; CRB 0.7-12/10/09

*

RH7

RH7 51 Ohm

51 Ohm

H_TDO

H_TDI H_TMS H_TCK H_TRST#

RH61 750

4

Dummy

RH17

4.7K

*

+1P8V_SFR

*

RH5

RH4

51 Ohm

1K

Dummy

Close to XDP Conn

RH18 51 Ohm

RH21 51 Ohm

RH21 51 Ohm RH23 51 Ohm

RH23 51 Ohm RH25 51 Ohm

RH25 51 Ohm RH27 51 Ohm

RH27 51 Ohm

Close to CPU

*

+/-1%

RH62

*

316

316 +/-1%

+/-1%

Change H_RESET# source from SIO directly-12/28/09

20100104: add UH2 to prevent SIO can't use

*

RH60

2.2K

CH11

0.1uF

16V, X7R, +/-10%

Dummy

*

* *

*

H_PROC_SEL

RH6

RH6 51 Ohm

51 Ohm

Dummy

1

+1P05V_VCCIO

H_RESET#_R 52

H_PROCHOT# H_PECI

H_THERMTRIP#

H_CATERR

Add H_VCCIO_SEL circuit; CRB 0.7-12/03/09

Title

CPU-1: MISC

DWG NO Rev

Date: Sheet of

3

2

Date: Sheet

CPU-1: MISC

Lanikai _MT/DT

1

A00

of

971Wednesday, June 13, 2012

5

D D

H_FDI_FSYNC025 H_FDI_LSYNC025

H_FDI_FSYNC125 H_FDI_LSYNC125

H_FDI_INT25

RH41 24.9

*

+1P05V_VCCIO

C C

*

+/-1%

UH1D

AC5

FDI_FSYNC0

AC4

FDI_LSYNC0

AE5

FDI_FSYNC1

AE4

FDI_LSYNC1

AG3

FDI_INT

AE2

FDI_COMPIO

AE1

FDI_ICOMPO

PE115527-4041-0DF

FDI

4/10

FDI_TX0

FDI_TX0*

FDI_TX1

FDI_TX1*

FDI_TX2

FDI_TX2*

FDI_TX3

FDI_TX3*

FDI_TX4

FDI_TX4*

FDI_TX5

FDI_TX5*

FDI_TX6

FDI_TX6*

FDI_TX7

FDI_TX7*

AC8 AC7 AC2 AC3 AD2 AD1 AD4 AD3

AD7 AD6 AE7 AE8 AF3 AF2 AG2 AG1

4

X_1X16_RXP[15..0]38 X_1X16_RXN[15..0]38

H_FDI_TXP0 25 H_FDI_TXN0 25 H_FDI_TXP1 25 H_FDI_TXN1 25 H_FDI_TXP2 25 H_FDI_TXN2 25 H_FDI_TXP3 25 H_FDI_TXN3 25

H_FDI_TXP4 25 H_FDI_TXN4 25 H_FDI_TXP5 25 H_FDI_TXN5 25 H_FDI_TXP6 25 H_FDI_TXN6 25 H_FDI_TXP7 25 H_FDI_TXN7 25

3

X_1X16_RXP0

X_1X16_RXN0

X_1X16_RXP1

X_1X16_RXN1

X_1X16_RXP2

X_1X16_RXN2

X_1X16_RXP3

X_1X16_RXN3

X_1X16_RXP4

X_1X16_RXN4

X_1X16_RXP5

X_1X16_RXN5

X_1X16_RXP6

X_1X16_RXN6

X_1X16_RXP7

X_1X16_RXN7

X_1X16_RXP8

X_1X16_RXN8

X_1X16_RXP9

X_1X16_RXN9

X_1X16_RXP10

X_1X16_RXN10

X_1X16_RXP11

X_1X16_RXN11

X_1X16_RXP12

X_1X16_RXN12

X_1X16_RXP13

X_1X16_RXN13

X_1X16_RXP14

X_1X16_RXN14

X_1X16_RXP15

X_1X16_RXN15

B11 B12 D12 D11 C10

E10

C9 E9

B8 B7 C6 C5 A5 A6 E2 E1

G2 G1 H3 H4

K3 K4

M3 M4 N1 N2

F4 F3

J1 J2

L1 L2

UH1C

PEG_RX0 PEG_RX0* PEG_RX1 PEG_RX1* PEG_RX2 PEG_RX2* PEG_RX3 PEG_RX3* PEG_RX4 PEG_RX4* PEG_RX5 PEG_RX5* PEG_RX6 PEG_RX6* PEG_RX7 PEG_RX7* PEG_RX8 PEG_RX8* PEG_RX9 PEG_RX9* PEG_RX10 PEG_RX10* PEG_RX11 PEG_RX11* PEG_RX12 PEG_RX12* PEG_RX13 PEG_RX13* PEG_RX14 PEG_RX14* PEG_RX15 PEG_RX15*

PEG

PEG_TX0

PEG_TX0*

PEG_TX1

PEG_TX1*

PEG_TX2

PEG_TX2*

PEG_TX3

PEG_TX3*

PEG_TX4

PEG_TX4*

PEG_TX5

PEG_TX5*

PEG_TX6

PEG_TX6*

PEG_TX7

PEG_TX7*

PEG_TX8

PEG_TX8*

PEG_TX9 PEG_TX9* PEG_TX10

PEG_TX10*

PEG_TX11

PEG_TX011

PEG_TX12

PEG_TX12*

PEG_TX13

PEG_TX13*

PEG_TX14

PEG_TX14*

PEG_TX15

PEG_TX15*

C13 C14 E14 E13 G14 G13 F12 F11 J14 J13 D8 D7 D3 C3 E6 E5 F8 F7 G10 G9 G5 G6 K7 K8 J5 J6 M8 M7 L6 L5 N5 N6

2

X_1X16_TXP0

X_1X16_TXN0

X_1X16_TXP1

X_1X16_TXN1

X_1X16_TXP2

X_1X16_TXN2

X_1X16_TXP3

X_1X16_TXN3

X_1X16_TXP4

X_1X16_TXN4

X_1X16_TXP5

X_1X16_TXN5

X_1X16_TXP6

X_1X16_TXN6

X_1X16_TXP7

X_1X16_TXN7

X_1X16_TXP8

X_1X16_TXN8

X_1X16_TXP9

X_1X16_TXN9

X_1X16_TXP10

X_1X16_TXN10

X_1X16_TXP11

X_1X16_TXN11

X_1X16_TXP12

X_1X16_TXN12

X_1X16_TXP13

X_1X16_TXN13

X_1X16_TXP14

X_1X16_TXN14

X_1X16_TXP15

X_1X16_TXN15

1

X_1X16_TXP[15..0] 38 X_1X16_TXN[15..0] 38

H_DMI_RXP022 H_DMI_RXN022 H_DMI_RXP122 H_DMI_RXN122 H_DMI_RXP222 H_DMI_RXN222 H_DMI_RXP322 H_DMI_RXN322

B B

A A

W5

DMI_RX0

W4

DMI_RX0*

V3

DMI_RX1

V4

DMI_RX1*

Y3

DMI_RX2

Y4

DMI_RX2*

AA4

DMI_RX3

AA5

DMI_RX3*

P3

PE_RX0

P4

PE_RX0*

R2

PE_RX1

R1

PE_RX1*

T4

PE_RX2

T3

PE_RX2*

U2

PE_RX3

U1

PE_RX3*

PE115527-4041-0DF

3/10

DMI

GEN

PEG_COMPI

PEG_ICOMPO

PEG_RCOMPO

DMI_TX0

DMI_TX0*

DMI_TX1

DMI_TX1*

DMI_TX2

DMI_TX2*

DMI_TX3

DMI_TX3*

PE_TX0

PE_TX0*

PE_TX1

PE_TX1*

PE_TX2

PE_TX2*

PE_TX3

PE_TX3*

V7 V6 W7 W8 Y6 Y7 AA7 AA8

P8 P7 T7 T8 R6 R5 U5 U6

B4 B5 C4

RH42 24.9

*

+/-1%

H_DMI_TXP0 22 H_DMI_TXN0 22 H_DMI_TXP1 22 H_DMI_TXN1 22 H_DMI_TXP2 22 H_DMI_TXN2 22 H_DMI_TXP3 22 H_DMI_TXN3 22

+1P05V_VCCIO

Title

CPU-2: FDI/PCIe/DMI

DWG NO Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

CPU-2: FDI/PCIe/DMI

Lanikai _MT/DT

10 71Wednesday, June 13, 2012

1

A00

of

5

D D

C C

1 2

D3_RESET#15,16,17,18

Add RC filter;CRB

0.7-11/30/09

B B

A A

5

RH8 DummyRH8 Dummy

CH47

*

0.1uF

Dummy

16V, X7R, +/-10%

4

UH1A

D3_MAA[15..0]15,16

D3_WEA#15,16 D3_CASA#15,16 D3_RASA#15,16

D3_BAA[2..0]15,16

D3_SCS_A#015 D3_SCS_A#115 D3_SCS_A#216 D3_SCS_A#316

D3_CKE_A015 D3_CKE_A115 D3_CKE_A216 D3_CKE_A316

D3_ODT_A015 D3_ODT_A115 D3_ODT_A216 D3_ODT_A316

D3_MA_CLK015 D3_MA_CLK#015 D3_MA_CLK115 D3_MA_CLK#115 D3_MA_CLK216 D3_MA_CLK#216 D3_MA_CLK316 D3_MA_CLK#316

H_DRAMPWRGD24

D3_DQS_A815,16

D3_DQS_A#815,16

D3_ECC_CB_A[7..0]15,16

4

D3_MAA0 D3_MAA1 D3_MAA2 D3_MAA3 D3_MAA4 D3_MAA5 D3_MAA6 D3_MAA7 D3_MAA8 D3_MAA9 D3_MAA10 D3_MAA11 D3_MAA12 D3_MAA13 D3_MAA14 D3_MAA15

D3_BAA0 D3_BAA1 D3_BAA2

RH51 120Ohm

*

+/-5%

H_SM_VREF

D3_ECC_CB_A0 D3_ECC_CB_A1 D3_ECC_CB_A2 D3_ECC_CB_A3 D3_ECC_CB_A4 D3_ECC_CB_A5 D3_ECC_CB_A6 D3_ECC_CB_A7

UH1A

AV27

SA_MA0

AY24

SA_MA1

AW24

SA_MA2

AW23

SA_MA3

AV23

SA_MA4

AT24

SA_MA5

AT23

SA_MA6

AU22

SA_MA7

AV22

SA_MA8

AT22

SA_MA9

AV28

SA_MA10

AU21

SA_MA11

AT21

SA_MA12

AW32

SA_MA13

AU20

SA_MA14

AT20

SA_MA15

AW29

SA_WE*

AV30

SA_CAS*

AU28

SA_RAS*

AY29

SA_BS0

AW28

SA_BS1

AV20

SA_BS2

AU29

SA_CS0*

AV32

SA_CS1*

AW30

SA_CS2*

AU33

SA_CS3*

AV19

SA_CKE0

AT19

SA_CKE1

AU18

SA_CKE2

AV18

SA_CKE3

AV31

SA_ODT0

AU32

SA_ODT1

AU30

SA_ODT2

AW33

SA_ODT3

AY25

SA_CK0

AW25

SA_CK0*

AU24

SA_CK1

AU25

SA_CK1*

AW27

SA_CK2

AY27

SA_CK2*

AV26

SA_CK3

AW26

SA_CK3*

AW18

SM_DRAMRST*

AJ19

SM_DRAMPWROK

AJ22

SM_VREF

AV13

SA_DQS8

AV12

SA_DQS8*

AU12

SA_ECC_CB0

AU14

SA_ECC_CB1

AW13

SA_ECC_CB2

AY13

SA_ECC_CB3

AU13

SA_ECC_CB4

AU11

SA_ECC_CB5

AY12

SA_ECC_CB6

AW12

SA_ECC_CB7

PE115527-4041-0DF

3

DDR_A

1/10

3

SA_DQS0

SA_DQS0*

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7

SA_DQS1

SA_DQS1*

SA_DQ8

SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15

SA_DQS2

SA_DQS2*

SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23

SA_DQS3

SA_DQS3*

SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31

SA_DQS4

SA_DQS4*

SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39

SA_DQS5

SA_DQS5*

SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47

SA_DQS6

SA_DQS6*

SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55

SA_DQS7

SA_DQS7*

SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

AK3 AK2

AJ3 AJ4 AL3 AL4 AJ2 AJ1 AL2 AL1

AP3 AP2

AN1 AN4 AR3 AR4 AN2 AN3 AR2 AR1

AW4 AV4

AV2 AW3 AV5 AW5 AU2 AU3 AU5 AY5

AV8 AW8

AY7 AU7 AV9 AU9 AV7 AW7 AW9 AY9

AV37 AV36

AU35 AW37 AU39 AU36 AW35 AY36 AU38 AU37

AP38 AP39

AR40 AR37 AN38 AN37 AR39 AR38 AN39 AN40

AK38 AK39

AL40 AL37 AJ38 AJ37 AL39 AL38 AJ39 AJ40

AF38 AF39

AG40 AG37 AE38 AE37 AG39 AG38 AE39 AE40

D3_DQ_A0 D3_DQ_A1 D3_DQ_A2 D3_DQ_A3 D3_DQ_A4 D3_DQ_A5 D3_DQ_A6 D3_DQ_A7

D3_DQ_A8 D3_DQ_A9 D3_DQ_A10 D3_DQ_A11 D3_DQ_A12 D3_DQ_A13 D3_DQ_A14 D3_DQ_A15

D3_DQ_A16 D3_DQ_A17 D3_DQ_A18 D3_DQ_A19 D3_DQ_A20 D3_DQ_A21 D3_DQ_A22 D3_DQ_A23

D3_DQ_A24 D3_DQ_A25 D3_DQ_A26 D3_DQ_A27 D3_DQ_A28 D3_DQ_A29 D3_DQ_A30 D3_DQ_A31

D3_DQ_A32 D3_DQ_A33 D3_DQ_A34 D3_DQ_A35 D3_DQ_A36 D3_DQ_A37 D3_DQ_A38 D3_DQ_A39

D3_DQ_A40 D3_DQ_A41 D3_DQ_A42 D3_DQ_A43 D3_DQ_A44 D3_DQ_A45 D3_DQ_A46 D3_DQ_A47

D3_DQ_A48 D3_DQ_A49 D3_DQ_A50 D3_DQ_A51 D3_DQ_A52 D3_DQ_A53 D3_DQ_A54 D3_DQ_A55

D3_DQ_A56 D3_DQ_A57 D3_DQ_A58 D3_DQ_A59 D3_DQ_A60 D3_DQ_A61 D3_DQ_A62 D3_DQ_A63

2

D3_DQS_A0 15,16 D3_DQS_A#0 15,16

D3_DQ_A[63..0] 15,16

D3_DQS_A1 15,16 D3_DQS_A#1 15,16

D3_DQS_A2 15,16 D3_DQS_A#2 15,16

D3_DQS_A3 15,16 D3_DQS_A#3 15,16

D3_DQS_A4 15,16 D3_DQS_A#4 15,16

D3_DQS_A5 15,16 D3_DQS_A#5 15,16

D3_DQS_A6 15,16 D3_DQS_A#6 15,16

D3_DQS_A7 15,16 D3_DQS_A#7 15,16

2

1

+1P5V_SM

RH43

*

100 Ohm

+/-1%

H_SM_VREF

CH3

RH44

0.1uF

RH44

*

100 Ohm

+/-1%

RH43,RH44 is 1k in PDG; 100 in CRB

11 71Wednesday, June 13, 2012

1

*

16V, X7R, +/-10%

RH43,RH44 usage 100 Ohm follow CRB; CRB 0.7-12/10/09

Title

CPU-3: DDR3_CHA

DWG NO Rev

Date: Sheet

Date: Sheet of

CPU-3: DDR3_CHA

Lanikai _MT/DT

A00

of

5

D3_MAB[15..0]17,18

D D

D3_WEB#17,18 D3_CASB#17,18 D3_RASB#17,18

D3_BAB[2..0]17,18

D3_SCS_B#017 D3_SCS_B#117 D3_SCS_B#218 D3_SCS_B#318

D3_CKE_B017 D3_CKE_B117 D3_CKE_B218 D3_CKE_B318

C C

B B

A A

D3_ODT_B017 D3_ODT_B117 D3_ODT_B218 D3_ODT_B318

D3_MB_CLK017 D3_MB_CLK#017 D3_MB_CLK117 D3_MB_CLK#117 D3_MB_CLK218 D3_MB_CLK#218 D3_MB_CLK318 D3_MB_CLK#318

D3_DQS_B817,18

D3_DQS_B#817,18

D3_ECC_CB_B[7..0]17,18

5

D3_MAB0 D3_MAB1 D3_MAB2 D3_MAB3 D3_MAB4 D3_MAB5 D3_MAB6 D3_MAB7 D3_MAB8 D3_MAB9 D3_MAB10 D3_MAB11 D3_MAB12 D3_MAB13 D3_MAB14 D3_MAB15

D3_BAB0 D3_BAB1 D3_BAB2

D3_ECC_CB_B0 D3_ECC_CB_B1 D3_ECC_CB_B2 D3_ECC_CB_B3 D3_ECC_CB_B4 D3_ECC_CB_B5 D3_ECC_CB_B6 D3_ECC_CB_B7

AK24 AM20 AM19

AK18

AP19

AP18 AM18

AL18 AN18

AY17 AN23 AU17

AT18 AR26

AY16

AV16 AR25

AK25

AP24

AP23 AM24

AW17

AN25 AN26

AL25

AT26

AU16

AY15

AW15

AV15

AL26

AP26 AM26

AK26

AL21

AL22

AL20

AK20

AL23 AM22

AP21 AN21

AN16 AN15

AL16 AM16

AP16 AR16

AL15 AM15 AR15

AP15

4

UH1B

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

SB_WE* SB_CAS* SB_RAS*

SB_BS0 SB_BS1 SB_BS2

SB_CS0* SB_CS1* SB_CS2* SB_CS3*

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3

SB_CK0 SB_CK0* SB_CK1 SB_CK1* SB_CK2 SB_CK2* SB_CK3 SB_CK3*

SB_DQS8 SB_DQS8*

SB_ECC_CB0 SB_ECC_CB1 SB_ECC_CB2 SB_ECC_CB3 SB_ECC_CB4 SB_ECC_CB5 SB_ECC_CB6 SB_ECC_CB7

PE115527-4041-0DF

4

DDR_B

2/10

SB_DQS0

SB_DQS0*

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7

SB_DQS1

SB_DQS1*

SB_DQ8

SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15

SB_DQS2

SB_DQS2*

SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23

SB_DQS3

SB_DQS3*

SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31

SB_DQS4

SB_DQS4*

SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39

SB_DQS5

SB_DQS5*

SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47

SB_DQS6

SB_DQS6*

SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55

SB_DQS7

SB_DQS7*

SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

AH7 AH6

AG7 AG8 AJ9 AJ8 AG5 AG6 AJ6 AJ7

AM8 AL8

AL7 AM7 AM10 AL10 AL6 AM6 AL9 AM9

AR8 AP8

AP7 AR7 AP10 AR10 AP6 AR6 AP9 AR9

AN13 AN12

AM12 AM13 AR13 AP13 AL12 AL13 AR12 AP12

AN29 AN28

AR28 AR29 AL28 AL29 AP28 AP29 AM28 AM29

AP33 AR33

AP32 AP31 AP35 AP34 AR32 AR31 AR35 AR34

AL33 AM33

AM32 AM31 AL35 AL32 AM34 AL31 AM35 AL34

AG35 AG34

AH35 AH34 AE34 AE35 AJ35 AJ34 AF33 AF35

D3_DQ_B0 D3_DQ_B1 D3_DQ_B2 D3_DQ_B3 D3_DQ_B4 D3_DQ_B5 D3_DQ_B6 D3_DQ_B7

D3_DQ_B13 D3_DQ_B9 D3_DQ_B11 D3_DQ_B15 D3_DQ_B12 D3_DQ_B8 D3_DQ_B14 D3_DQ_B10

D3_DQ_B16 D3_DQ_B17 D3_DQ_B18 D3_DQ_B19 D3_DQ_B20 D3_DQ_B21 D3_DQ_B22 D3_DQ_B23

D3_DQ_B24 D3_DQ_B25 D3_DQ_B26 D3_DQ_B27 D3_DQ_B28 D3_DQ_B29 D3_DQ_B30 D3_DQ_B31

D3_DQ_B32 D3_DQ_B33 D3_DQ_B34 D3_DQ_B35 D3_DQ_B36 D3_DQ_B37 D3_DQ_B38 D3_DQ_B39

D3_DQ_B40 D3_DQ_B41 D3_DQ_B42 D3_DQ_B43 D3_DQ_B44 D3_DQ_B45 D3_DQ_B46 D3_DQ_B47

D3_DQ_B48 D3_DQ_B52 D3_DQ_B55 D3_DQ_B51 D3_DQ_B54 D3_DQ_B49 D3_DQ_B53 D3_DQ_B50

D3_DQ_B56 D3_DQ_B57 D3_DQ_B58 D3_DQ_B59 D3_DQ_B60 D3_DQ_B61 D3_DQ_B62 D3_DQ_B63

3

D3_DQS_B0 17,18 D3_DQS_B#0 17,18

D3_DQ_B[63..0] 17,18

D3_DQS_B1 17,18 D3_DQS_B#1 17,18

DQ REMAPPING IMPLEMENTED TO IMPROVE BREAKOUT AND MINIMIZE CH-2-CH COUPLING

D3_DQS_B2 17,18 D3_DQS_B#2 17,18

D3_DQS_B3 17,18 D3_DQS_B#3 17,18

D3_DQS_B4 17,18 D3_DQS_B#4 17,18

D3_DQS_B5 17,18 D3_DQS_B#5 17,18

D3_DQS_B6 17,18 D3_DQS_B#6 17,18

DQ REMAPPING IMPLEMENTED TO IMPROVE BREAKOUT AND MINIMIZE CH-2-CH COUPLING

D3_DQS_B7 17,18 D3_DQS_B#7 17,18

3

2

Title

CPU-4: DDR3_CHB

DWG NO Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet of

CPU-4: DDR3_CHB

Lanikai _MT/DT

1

A00

of

12 71Wednesday, June 13, 2012

1

5

+VCORE

UH1F

A12

VCC_1

A13

VCC_2

A14

VCC_3

A15

VCC_4

A16

VCC_5

D D

C C

B B

A18

VCC_6

A24

VCC_7

A25

VCC_8

A27

VCC_9

A28

VCC_10

B15

VCC_11

B16

VCC_12

B18

VCC_13

B24

VCC_14

B25

VCC_15

B27

VCC_16

B28

VCC_17

B30

VCC_18

B31

VCC_19

B33

VCC_20

B34

VCC_21

C15

VCC_22

C16

VCC_23

C18

VCC_24

C19

VCC_25

C21

VCC_26

C22

VCC_27

C24

VCC_28

C25

VCC_29

C27

VCC_30

C28

VCC_31

C30

VCC_32

C31

VCC_33

C33

VCC_34

C34

VCC_35

C36

VCC_36

D13

VCC_37

D14

VCC_38

D15

VCC_39

D16

VCC_40

D18

VCC_41

D19

VCC_42

D21

VCC_43

D22

VCC_44

D24

VCC_45

D25

VCC_46

D27

VCC_47

D28

VCC_48

D30

VCC_49

D31

VCC_50

D33

VCC_51

D34

VCC_52

D35

VCC_53

D36

VCC_54

E15

VCC_55

E16

VCC_56

E18

VCC_57

E19

VCC_58

E21

VCC_59

E22

VCC_60

E24

VCC_61

E25

VCC_62

E27

VCC_63

E28

VCC_64

E30

VCC_65

E31

VCC_66

E33

VCC_67

E34

VCC_68

E35

VCC_69

F15

VCC_70

F16

VCC_71

F18

VCC_72

F19

VCC_73

F21

VCC_74

F22

VCC_75

F24

VCC_76

F25

VCC_77

F27

VCC_78

F28

VCC_79

F30

VCC_80

PE115527-4041-0DF

CPU POWER

6/10

VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97 VCC_98

VCC_99 VCC_100 VCC_101 VCC_102 VCC_103 VCC_104 VCC_105 VCC_106 VCC_107 VCC_108 VCC_109 VCC_110 VCC_111 VCC_112 VCC_113 VCC_114 VCC_115 VCC_116 VCC_117 VCC_118 VCC_119 VCC_120 VCC_121 VCC_122 VCC_123 VCC_124 VCC_125 VCC_126 VCC_127 VCC_128 VCC_129 VCC_130 VCC_131 VCC_132 VCC_133 VCC_134 VCC_135 VCC_136 VCC_137 VCC_138 VCC_139 VCC_140 VCC_141 VCC_142 VCC_143 VCC_144 VCC_145 VCC_146 VCC_147 VCC_148 VCC_149 VCC_150 VCC_151 VCC_152 VCC_153 VCC_154 VCC_155 VCC_156 VCC_157 VCC_158 VCC_159 VCC_160 VCC_161

F31 F32 F33 F34 G15 G16 G18 G19 G21 G22 G24 G25 G27 G28 G30 G31 G32 G33 H13 H14 H15 H16 H18 H19 H21 H22 H24 H25 H27 H28 H30 H31 H32 J12 J15 J16 J18 J19 J21 J22 J24 J25 J27 J28 J30 K15 K16 K18 K19 K21 K22 K24 K25 K27 K28 K30 L13 L14 L15 L16 L18 L19 L21 L22 L24 L25 L27 L28 L30 M14 M15 M16 M18 M19 M21 M22 M24 M25 M27 M28 M30

4

+1P05V_VCCIO +1P5V_SM

UH1G

A11

VCCIO_1

A7

VCCIO_2

AA3

VCCIO_3

AB8

VCCIO_4

AF8

VCCIO_5

AG33

VCCIO_6

AJ16

VCCIO_7

AJ17

VCCIO_8

AJ26

VCCIO_9

AJ28

VCCIO_10

AJ32

VCCIO_11

AK15

VCCIO_12

AK17

VCCIO_13

AK19

VCCIO_14

AK21

VCCIO_15

AK23

VCCIO_16

AK27

VCCIO_17

AK29

VCCIO_18

AK30

VCCIO_19

B9

VCCIO_20

D10

VCCIO_21

D6

VCCIO_22

E3

VCCIO_23

E4

VCCIO_24

G3

VCCIO_25

G4

VCCIO_26

J3

VCCIO_27

J4

VCCIO_28

J7

VCCIO_29

J8

VCCIO_30

L3

VCCIO_31

L4

VCCIO_32

L7

VCCIO_33

M13

VCCIO_34

N3

VCCIO_35

N4

VCCIO_36

N7

VCCIO_37

R3

VCCIO_38

R4

VCCIO_39

R7

VCCIO_40

U3

VCCIO_41

U4

VCCIO_42

U7

VCCIO_43

V8

VCCIO_44

W3

VCCIO_45

7/10

PE115527-4041-0DF

3

H10

VCCSA_1

H11

VCCSA_2

H12

VCCSA_3

J10

VCCSA_4

K10

VCCSA_5

K11

VCCSA_6

L11

VCCSA_7

L12

VCCSA_8

M10

VCCSA_9

M11

VCCSA_10

M12

VCCSA_11

CPU POWER

AK11

VCCPLL_1

AK12

VCCPLL_2

+V_VCCSA

+1P8V_SFR

CH4

*

1uF

16V, X5R, +/-10%

+1P1V_AXG

2

UH1H

AB33

VAXG_1

AB34

VAXG_2

AB35

VAXG_3

AB36

VAXG_4

AB37

VAXG_5

AB38

VAXG_6

AB39

VAXG_7

AB40

VAXG_8

AC33

VAXG_9

AC34

VAXG_10

AC35

VAXG_11

AC36

VAXG_12

AC37

VAXG_13

AC38

VAXG_14

AC39

VAXG_15

AC40

VAXG_16

T33

VAXG_17

T34

VAXG_18

T35

VAXG_19

T36

VAXG_20

T37

VAXG_21

T38

VAXG_22

T39

VAXG_23

T40

VAXG_24

U33

VAXG_25

U34

VAXG_26

U35

VAXG_27

U36

VAXG_28

U37

VAXG_29

U38

VAXG_30

U39

VAXG_31

U40

VAXG_32

W33

VAXG_33

W34

VAXG_34

W35

VAXG_35

W36

VAXG_36

W37

VAXG_37

W38

VAXG_38

Y33

VAXG_39

Y34

VAXG_40

Y35

VAXG_41

Y36

VAXG_42

Y37

VAXG_43

Y38

VAXG_44

CH5

*

4.7uF

6.3V, X5R, +/-10%

MCH POWER

8/10

PE115527-4041-0DF

CH6

CH7

*

0.1uF

16V, X7R, +/-10%

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_6 VDDQ_4 VDDQ_5 VDDQ_7 VDDQ_8

VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20 VDDQ_21 VDDQ_22 VDDQ_23

AJ13 AJ14 AJ20 AJ23 AJ24 AR20 AR21 AR22 AR23 AR24 AU19 AU23 AU27 AU31 AV21 AV24 AV25 AV29 AV33 AW31 AY23 AY26 AY28

1

+1P5V_SM+1P05V_VCCIO

CH9

6.3V,X5R,+/-20%

CH9

*

22uF

6.3V,X5R,+/-20%

CH8

*

22uF

CLOSE TO CPU CLOSE TO CPU

A A

Title

CPU-5: Power

DWG NO Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

CPU-5: Power

Lanikai _MT/DT

1

A00

of

13 71Wednesday, June 13, 2012

5

UH1I

A17

VSS_1

A23

VSS_2

A26

VSS_3

A29

VSS_4

A35

VSS_5

AA33

VSS_6

AA34

VSS_7

D D

C C

B B

A A

AA35 AA36 AA37 AA38

AA6 AB5 AC1

AC6 AD33 AD36 AD38 AD39 AD40

AD5

AD8

AE3

AE33 AE36

AF1 AF34 AF36 AF37 AF40

AF5

AF6

AF7

AG36

AH2

AH3 AH33 AH36 AH37 AH38 AH39 AH40

AH5

AH8

AJ12 AJ15 AJ18 AJ21 AJ25 AJ27 AJ36

AJ5

AK1

AK10 AK13 AK14 AK16 AK22 AK28 AK31 AK32 AK33 AK34 AK35 AK36 AK37

AK4

AK40

AK5

AK6

AK7

AK8

AK9

AL11 AL14 AL17 AL19 AL24 AL27 AL30 AL36

AL5

AM1 AM11 AM14 AM17

AM2 AM21 AM23 AM25

5

VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90

9/10

PE115527-4041-0DF

VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130

GND

VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170

AM27 AM3 AM30 AM36 AM37 AM38 AM39 AM4 AM40 AM5 AN10 AN11 AN14 AN17 AN19 AN22 AN24 AN27 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AN5 AN6 AN7 AN8 AN9 AP1 AP11 AP14 AP17 AP22 AP25 AP27 AP30 AP36 AP37 AP4 AP40 AP5 AR11 AR14 AR17 AR18 AR19 AR27 AR30 AR36 AR5 AT1 AT10 AT12 AT13 AT15 AT16 AT17 AT2 AT25 AT27 AT28 AT29 AT3 AT30 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AT39 AT4 AT40 AT5 AT6 AT7

4

B39 update to RSVD48; PDG 0.7-12/07/09

EDS: B39 defined "VSS_NCTF" CRB: B39 defined "RSVD"

Pin_B39 follow CRB pin define; CRB 0.7-12/10/09

4

TPH99TPH99

AT8 AT9

AU1 AU15 AU26 AU34

AU4

AU6

AU8 AV10 AV11 AV14 AV17

AV3 AV35 AV38

AV6

AW10 AW11 AW14 AW16 AW36

AW6 AY11 AY14 AY18 AY35

AY4 AY6 AY8

C11 C12 C17 C20 C23 C26 C29 C32 C35

D17 D20

D23 D26 D29 D32 D37 D39

AV39 AY37

B10 B13 B14 B17 B23 B26 B29 B32 B35 B38

E11 E12 E17 E20 E23 E26 E29 E32 E36

F10 F13 F14 F17

F20 F23 F26 F29 F35

B39

B6

C7 C8

D2

D4 D5 D9

E7 E8 F1

F2

A4

B3

3

UH1J

VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256

RSVD48 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5

10/10

PE115527-4041-0DF

3

VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304

GND

VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360

F37 F39 F5 F6 F9 G11 G12 G17 G20 G23 G26 G29 G34 G7 G8 H1 H17 H2 H20 H23 H26 H29 H33 H35 H37 H39 H5 H6 H9 J11 J17 J20 J23 J26 J29 J32 K1 K12 K13 K14 K17 K2 K20 K23 K26 K29 K33 K35 K37 K39 K5 K6 L10 L17 L20 L23 L26 L29 L8 M1 M17 M2 M20 M23 M26 M29 M33 M35 M37 M39 M5 M6 M9 N8 P1 P2 P36 P38 P40 P5 P6 R33 R35 R37 R39 R8 T1 T5 T6 U8 V1 V2 V33 V34 V35 V36 V37 V38 V39 V40 V5 W6 Y5 Y8

2

UH1_1

Retention Module

MLH1MLH1

Title

DWG NO Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet of

ACA-ZIF-078-P05_A

2D lable

MLH2MLH2 MLH3MLH3 MLH4MLH4

CPU-6: GND

Lanikai _MT/DT

UH1_B

<LBL>

1

A00

of

14 71Wednesday, June 13, 2012

1

5

CHANNEL A BANK 1 SMB ADDRESS:000

D3_ECC_CB_A[7..0] 11,16

4

D3_DQS_A8 11,16 D3_DQS_A#8 11,16

3

2

1

143

144

DQS11

DQS10

DM2/DQS11

D3_DQS_A[7..0] 11,16 D3_DQS_A#[7..0] 11,16

212

203

152

153

DM3/DQS12

DQS12

204

DQS13

DM4/DQS13

+1P5V_SM

213

DQS14

DM5/DQS14

D3_DQ_A[63..0] 11,16

D3_DQ_A63

D3_DQ_A62

D3_DQ_A61

D3_DQ_A60

D3_DQ_A59

D3_DQ_A58

D3_DQ_A57

D3_DQ_A56

D3_DQ_A55

D3_DQ_A54

D3_DQ_A53

D3_DQ_A52

D3_DQ_A51

D3_DQ_A50

D3_DQ_A49

D3_DQ_A48

D3_DQ_A47

D3_DQ_A46

D3_DQ_A45

D3_DQ_A44

D3_DQ_A43

D3_DQ_A42

D3_DQ_A41

D3_DQ_A40

D3_DQ_A39

D3_DQ_A38

D3_DQ_A37

D3_DQ_A36

D3_DQ_A35

D3_DQ_A34

D3_DQ_A33

D3_DQ_A32

D3_DQ_A31

D3_DQ_A30

D3_DQ_A29

D3_DQ_A28

D3_DQ_A27

D3_DQ_A26

D3_DQ_A25

D3_DQ_A24

D3_DQ_A23

D3_DQ_A22

D3_DQ_A21

D3_DQ_A20

D3_DQ_A19

D3_DQ_A18

D3_DQ_A17

D3_DQ_A16

D3_DQ_A15

D3_DQ_A14

D3_DQ_A13

D3_DQ_A12

D3_DQ_A11

D3_DQ_A10

D3_DQ_A9

D3_DQ_A8

D3_DQ_A7

D3_DQ_A6

D3_DQ_A5

D3_DQ_A4

D3_DQ_A3

D3_DQ_A2

D3_DQ_A1

D3_DQ_A0

122

123

128

129

13

131

132

137

138

140

141

146

147

149

150

155

156

200

201

206

207

209

210

215

216

100

105

106

218

219

224

225

108

109

114

115

227

228

233

DQ57

A14

171

DQ58

A15

DQ59

168

DQ60

RESET

DQ61

CAS74RAS

192

234

DQ62

73

DQ63

WE

DIMM3

DIMM3 DDRIII

DDRIII

D3_WEA# 11,16 D3_RASA# 11,16 D3_CASA# 11,16 D3_RESET# 11,16,17,18

161

230

221

DM6/DQS15

S_SMBCLK_MAIN16,17,18,32,52

S_SMBDATA_MAIN16,17,18,32,52

162

231

222

DQ03DQ14DQ29DQ310DQ4

DQ5

DQ6

DQ7

DQ812DQ9

DQ1018DQ1119DQ12

DQ13

DQ14

DQ15

DQ1621DQ1722DQ1827DQ1928DQ20

DQ21

DQ22

DQ23

DQ2430DQ2531DQ2636DQ2737DQ28

DQ29

DQ30

DQ31

DQ3281DQ3382DQ3487DQ3588DQ36

DQ37

DQ38

DQ39

DQ4090DQ4191DQ4296DQ4397DQ44

DQ45

DQ46

DQ47

DQ4899DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS17

DQS15

NC/DQS16

DM8/DQS17

DM7/DQS16

VDDQ

197

194

191

189

186

183

182

179

D3_BAA[2..0]11,16

D3_CKE_A111 D3_CKE_A011

D3_SCS_A#111 D3_SCS_A#011

D3_MA_CLK#111 D3_MA_CLK111 D3_MA_CLK#011 D3_MA_CLK011

D3_MAA[15..0]11,16

DDRIII

VDDQ

VDD78VDD75VDD72VDD69VDD66VDD65VDD62VDD60VDD57VDD54VDD51VDDSPD

176

173

170

+3V

D3_CA_VREF_A D3_DQ_VREF_A

D3_BAA2 D3_BAA1 D3_BAA0

D3_MAA0 D3_MAA1 D3_MAA2 D3_MAA3 D3_MAA4 D3_MAA5 D3_MAA6 D3_MAA7 D3_MAA8 D3_MAA9 D3_MAA10 D3_MAA11 D3_MAA12 D3_MAA13 D3_MAA14 D3_MAA15

SA2

VREFDQ1SCL

SDA

SA1

SA0

BA071BA1

CKE050CKE1

S0

169

S176CK1/NU64CK1/NU63CK0*

193

VREFCA

67

236

118

238

BA2

52

119

237

117

190

CK0

185

184A0188A1181

A261A3

180

A459A558A6

178

A756A9

000

DQ56

A10/AP70A1155A12

A13

A8

175

174

196

177

172

D3_ODT_A1 11 D3_ODT_A0 11

D D

D3_DQS_A#7

D3_DQS_A#6

D3_DQS_A#5

D3_DQS_A#4

D3_DQS_A#3

D3_DQS_A#2

D3_DQS_A#1

D3_DQS_A#0

D3_DQS_A2

D3_DQS_A1

VSS

D3_DQS_A0

D3_ECC_CB_A5

D3_ECC_CB_A6

D3_ECC_CB_A7

24

15

6

159

164

165

DQS225DQS2

DQS116DQS1

DQS07DQS0

CB<5>

CB<6>

CB<7>

VSS

208

205

202

199

166

163

160

157

154

151

148

145

142

139

D3_ECC_CB_A2

D3_ECC_CB_A3

D3_ECC_CB_A4

D3_ECC_CB_A1

D3_ECC_CB_A0

79

RSVD

C C

FREE1

198

187

+1P5V_SM_VTT

195

ODT177ODT0

FREE2

FREE349FREE4

48

53

167

68

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

VSS

VTT

239

235

232

120

240

229

VSS

226

223

158

CB<0>39CB<1>40CB<2>45CB<3>46CB<4>

VSS

220

217

214

211

D3_DQS_A3

136

DQS334DQS3

VSS

D3_DQS_A5

D3_DQS_A4

84

33

DQS485DQS4

VSS

133

130

127

124

121

D3_DQS_A7

D3_DQS_A6

112

103

102

93

DQS6

DQS594DQS5

VSS

116

113

110

107

104

101

125

134

135

126

42

111

DQS9

DQS843DQS8

DQS7

DM0/DQS9

DM1/DQS10

VSS

VSS98VSS95VSS92VSS89VSS86VSS83VSS80VSS47VSS44VSS41VSS38VSS35VSS32VSS29VSS26VSS23VSS20VSS17VSS14VSS11VSS8VSS5VSS2VDDQ

CLOSE TO DIMM POWER PIN

+1P5V_SM

CD1

*

1uF

6.3V,X5R,+/-10%

B B

+1P5V_SM_VTT

CD8

*

4.7uF

6.3V, X5R, +/-10%

CD2

*

1uF

6.3V,X5R,+/-10%

CD9

*

0.1uF

16V, X7R, +/-10%

CD3

*

1uF

6.3V,X5R,+/-10%

CD10

*

0.1uF

16V, X7R, +/-10%

CD4

*

1uF

6.3V,X5R,+/-10%

+3V

*

20100104: Remove CD5 10uF

SA_BS[0]-->Pin 71 (BA0) SA_BS[1]-->Pin 190 (BA1) SA_BS[2]-->Pin 52 (BA2) ; CRB 0.7-12/10/09

CD6

1uF

16V, X5R, +/-10%

CD7

*

1uF

6.3V,X5R,+/-10%

PLAECE CLOSE TO CH-A DIMM

+1P5V_SM

RD1 1K

*

Dummy

*

CD11

0.1uF

16V, X7R, +/-10%

*

+/-1%

RD2

CD12

1K

+/-1%

CD12

*

0.1uF

16V, X7R, +/-10%

*

D3_DQ_VREF_A 16

Add CD52,CD53; follow CRB 0.7-12/28/09

A A

+1P5V_SM

RD3 1K

*

CD13

0.1uF

16V, X7R, +/-10%

Change to 0.1uF; PDG 0.7-12/07/09

*

+/-1%

RD4

*

1K

+/-1%

5

CD14

0.1uF

16V, X7R, +/-10%

Del CD52,CD53-12/29/09

D3_CA_VREF_A 16

CD51

*

2.2uF

6.3V, Y5V, +80%/-20%

Dummy

Add CD47 , CD48, CD49, CD50, CD51 and Dummy; CRB 0.7-12/10/09

Del CD47 , CD48, CD49, CD50, CD51 and Dummy; CRB 0.7-12/29/09

4

Title

DDR3 Conn: CHA_1 (DIMM3)

DWG NO Rev

Date: Sheet

Date: Sheet of

3

2

Date: Sheet of

DDR3 Conn: CHA_1 (DIMM3)

A00

Lanikai _MT/DT

1

15 71Wednesday, June 13, 2012

A00

of

5

CHANNEL A BANK 2 SMB ADDRESS:001

D3_ECC_CB_A[7..0] 11,15

4

D3_DQS_A8 11,15 D3_DQS_A#8 11,15

3

2

1

D3_ODT_A3 11 D3_ODT_A2 11

D D

D3_DQS_A#3

D3_DQS_A#2

D3_DQS_A#1

D3_DQS_A#0

D3_DQS_A1

VSS

D3_DQS_A0

D3_ECC_CB_A5

D3_ECC_CB_A6

D3_ECC_CB_A7

CB<5>

VSS

6

164

165

DQS07DQS0

CB<6>

CB<7>

VSS

205

202

199

166

163

160

157

154

159

208

D3_ECC_CB_A2

D3_ECC_CB_A3

D3_ECC_CB_A4

D3_ECC_CB_A1

D3_ECC_CB_A0

79

RSVD

C C

FREE1

198

187

+1P5V_SM_VTT

195

ODT177ODT0

FREE2

FREE349FREE4

48

53

167

68

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

VSS

VTT

239

235

232

229

120

240

CB<0>39CB<1>40CB<2>45CB<3>46CB<4>

VSS

226

223

158

VSS

220

217

214

211

DQS116DQS1

VSS

D3_DQS_A3

D3_DQS_A2

33

24

15

DQS334DQS3

DQS225DQS2

VSS

151

148

145

142

139

136

133

VSS

D3_DQS_A#5

D3_DQS_A#4

D3_DQS_A5

D3_DQS_A4

93

84

DQS594DQS5

DQS485DQS4

VSS

130

127

124

121

116

VSS

D3_DQS_A#7

D3_DQS_A#6

D3_DQS_A7

D3_DQS_A6

125

112

103

111

102

DQS7

DQS6

VSS

VSS98VSS95VSS92VSS89VSS86VSS83VSS80VSS47VSS44VSS41VSS38VSS35VSS32VSS29VSS26VSS23VSS20VSS17VSS14VSS11VSS8VSS5VSS2VDDQ

113

110

107

104

101

DQS843DQS8

134

135

126

42

DQS9

DM0/DQS9

DM1/DQS10

CLOSE TO DIMM POWER PIN

+1P5V_SM

CD18

CD17

CD16

CD15

1uF

*

6.3V,X5R,+/-10%

B B

+1P5V_SM_VTT

CD19

*

4.7uF

6.3V, X5R, +/-10%

CD16

1uF

*

6.3V,X5R,+/-10%

CD20

*

0.1uF

16V, X7R, +/-10%

CD17

1uF

*

6.3V,X5R,+/-10%

CD18

1uF

*

6.3V,X5R,+/-10%

SA_BS[0]-->Pin 71 (BA0) SA_BS[1]-->Pin 190 (BA1) SA_BS[2]-->Pin 52 (BA2) ; CRB 0.7-12/10/09

143

144

DQS11

DQS10

DM2/DQS11

D3_DQS_A[7..0] 11,15 D3_DQS_A#[7..0] 11,15

212

203

152

DM3/DQS12

213

204

153

DQS14

DQS13

DQS12

DM5/DQS14

DM4/DQS13

D3_DQ_A[63..0] 11,15

D3_DQ_A39

D3_DQ_A38

D3_DQ_A37

D3_DQ_A36

D3_DQ_A35

D3_DQ_A34

D3_DQ_A33

D3_DQ_A32

D3_DQ_A31

D3_DQ_A30

D3_DQ_A29

D3_DQ_A28

D3_DQ_A27

D3_DQ_A26

D3_DQ_A25

D3_DQ_A24

D3_DQ_A23

D3_DQ_A22

D3_DQ_A21

D3_DQ_A20

D3_DQ_A19

D3_DQ_A18

D3_DQ_A17

D3_DQ_A16

D3_DQ_A15

D3_DQ_A14

D3_DQ_A13

D3_DQ_A12

D3_DQ_A11

D3_DQ_A10

D3_DQ_A9

D3_DQ_A8

D3_DQ_A7

D3_DQ_A6

D3_DQ_A5

D3_DQ_A4

D3_DQ_A3

D3_DQ_A2

D3_DQ_A1

D3_DQ_A0

122

123

128

129

13

131

132

137

138

140

141

146

147

149

150

155

156

200

DQ31

DQ3281DQ3382DQ3487DQ3588DQ36

CKE050CKE1

169

201

S0

S176CK1/NU64CK1/NU63CK0*

193

221

222

DM6/DQS15

197

D3_CA_VREF_A15 D3_DQ_VREF_A15

S_SMBCLK_MAIN15,17,18,32,52

S_SMBDATA_MAIN15,17,18,32,52

162

231

DQ03DQ14DQ29DQ310DQ4

DQ5

DQ6

DQ7

DQ812DQ9

DQ1018DQ1119DQ12

DQ13

DQ14

DQ15

DQ1621DQ1722DQ1827DQ1928DQ20

DQ21

DQ22

DQ23

DQ2430DQ2531DQ2636DQ2737DQ28

DQ29

DQS15

D3_MAA[15..0]11,15

DQS17

NC/DQS16

DM8/DQS17

DM7/DQS16

VDDQ

194

191

189

186

183

182

179

D3_BAA[2..0]11,15

D3_CKE_A311 D3_CKE_A211

D3_SCS_A#311 D3_SCS_A#211

D3_MA_CLK#311 D3_MA_CLK311 D3_MA_CLK#211 D3_MA_CLK211

DDRIII

VDDQ

VDD78VDD75VDD72VDD69VDD66VDD65VDD62VDD60VDD57VDD54VDD51VDDSPD

176

173

170

+3V+1P5V_SM

D3_BAA2 D3_BAA1 D3_BAA0

D3_MAA0 D3_MAA1 D3_MAA2 D3_MAA3 D3_MAA4 D3_MAA5 D3_MAA6 D3_MAA7 D3_MAA8 D3_MAA9 D3_MAA10 D3_MAA11 D3_MAA12 D3_MAA13 D3_MAA14 D3_MAA15

SA2

VREFDQ1SCL

SDA

SA1

VREFCA

67

236

SA0

119

118

238

237

117

001

DQ30

BA071BA1

BA2

52

190

161

230

206

DQ37

207

DQ38

D3_DQ_A43

D3_DQ_A42

D3_DQ_A41

D3_DQ_A40

DQ39

DQ4090DQ4191DQ4296DQ4397DQ44

CK0

185

184A0188A1181

D3_DQ_A44

209

D3_DQ_A45

210

D3_DQ_A46

215

DQ45

A261A3

180

D3_DQ_A47

216

DQ46

D3_DQ_A49

D3_DQ_A48

100

DQ47

DQ4899DQ49

A459A558A6

178

D3_DQ_A50

105

D3_DQ_A52

D3_DQ_A51

106

218

DQ50

DQ51

A756A9

A8

175

177

D3_DQ_A53

219

DQ52

DQ53

A10/AP70A1155A12

D3_DQ_A54

224

D3_DQ_A55

225

DQ54

174

D3_DQ_A56

108

DQ55

196

DQ56

A13

D3_DQ_A57

109

172

D3_DQ_A58

114

DQ57

A14

171

D3_DQ_A59

115

DQ58

A15

D3_DQ_A60

227

DQ59

168

D3_DQ_A61

228

DQ60

RESET

D3_DQ_A62

233

DQ61

CAS74RAS

192

D3_DQ_A63

234

DQ62

73

DQ63

WE

DIMM1

DIMM1 DDRIII

DDRIII

D3_WEA# 11,15 D3_RASA# 11,15 D3_CASA# 11,15 D3_RESET# 11,15,17,18

A A

5

4

3

RD6 0

*

H_CPU_DIMM_VREF_A 9

D3_DQ_VREF_A 15

CD52

CD53

0.1uF

Dummy

CD53

*

0.1uF

Dummy

16V, X7R, +/-10%

*

16V, X7R, +/-10%

Add CD52,CD53; follow CRB 0.7-12/28/09

2

Title

DDR3 Conn: CHA_2 (DIMM1)

DWG NO Rev

Date: Sheet

Date: Sheet of

DDR3 Conn: CHA_2 (DIMM1)

Lanikai _MT/DT

16 71Wednesday, June 13, 2012

1

A00

of

5

CHANNEL B BANK 1

D3_ECC_CB_B[7..0] 12,18

SMB ADDRESS:010

D3_ODT_B1 12 D3_ODT_B0 12

D D

D3_DQS_B#3

D3_DQS_B#2

D3_DQS_B#1

D3_DQS_B#0

D3_DQS_B2

D3_DQS_B1

D3_ECC_CB_B2

D3_ECC_CB_B3

D3_ECC_CB_B1

D3_ECC_CB_B0

79

RSVD

FREE1

C C

198

187

195

ODT177ODT0

FREE2

FREE349FREE4

48

53

167

68

CB<0>39CB<1>40CB<2>45CB<3>46CB<4>

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

VSS

VTT

239

235

232

120

240

VSS

229

226

223

220

217

214

D3_DQS_B0

D3_ECC_CB_B4

D3_ECC_CB_B5

D3_ECC_CB_B6

D3_ECC_CB_B7

24

15

CB<5>

VSS

6

164

165

DQS225DQS2

DQS116DQS1

DQS07DQS0

CB<6>

CB<7>

VSS

205

202

199

166

163

160

157

154

151

148

145

142

158

159

VSS

211

208

VSS

D3_DQS_B#4

D3_DQS_B3

VSS

139

136

DQS334DQS3

VSS

D3_DQS_B5

D3_DQS_B4

84

33

DQS485DQS4

VSS

133

130

127

124

121

DQS594DQS5

D3_DQS_B#5

93

VSS

116

4

D3_DQS_B#7

D3_DQS_B#6

D3_DQS_B7

D3_DQS_B6

112

103

102

DQS6

VSS

113

110

107

104

101

125

42

111

DQS843DQS8

DQS7

VSS

VSS98VSS95VSS92VSS89VSS86VSS83VSS80VSS47VSS44VSS41VSS38VSS35VSS32VSS29VSS26VSS23VSS20VSS17VSS14VSS11VSS8VSS5VSS2VDDQ

143

134

144

135

126

DQS9

DM0/DQS9

DQS11

DQS10

DM2/DQS11

DM1/DQS10

D3_DQS_B8 12,18 D3_DQS_B#8 12,18

D3_DQS_B[7..0] 12,18 D3_DQS_B#[7..0] 12,18

212

203

152

153

DM3/DQS12

213

204

DQS14

DQS13

DQS12

DM5/DQS14

DM4/DQS13

3

D3_DQ_B26

D3_DQ_B25

D3_DQ_B24

D3_DQ_B23

D3_DQ_B22

D3_DQ_B21

D3_DQ_B20

D3_DQ_B19

D3_DQ_B18

D3_DQ_B17

D3_DQ_B16

D3_DQ_B15

D3_DQ_B14

D3_DQ_B13

D3_DQ_B12

D3_DQ_B11

D3_DQ_B10

D3_DQ_B9

D3_DQ_B8

D3_DQ_B7

D3_DQ_B6

D3_DQ_B5

D3_DQ_B4

D3_DQ_B3

D3_DQ_B2

D3_DQ_B1

D3_DQ_B0

122

123

128

129

13

131

132

137

138

140

141

146

161

230

221

222

DM6/DQS15

197

162

231

DQ03DQ14DQ29DQ310DQ4

DQ5

DQ6

DQ7

DQ812DQ9

DQ1018DQ1119DQ12

DQ13

DQ14

DQ15

DQS15

DQS17

NC/DQS16

DM8/DQS17

DM7/DQS16

VDDQ

194

191

189

186

183

182

179

DDRIII

VDDQ

VDD78VDD75VDD72VDD69VDD66VDD65VDD62VDD60VDD57VDD54VDD51VDDSPD

176

173

170

DQ1621DQ1722DQ1827DQ1928DQ20

236

147

DQ21

DQ22

DQ23

DQ2430DQ2531DQ2636DQ2737DQ28

SA2

VREFDQ1SCL

SDA

SA1

VREFCA

67

SA0

52

119

118

238

237

117

BA2

D3_DQ_B27

190

D3_DQ_B28

149

D3_DQ_B29

150

DQ29

BA071BA1

D3_DQ_B30

155

D3_DQ_B31

156

DQ30

169

D3_DQ_B32

DQ31

2

D3_DQ_B37

D3_DQ_B36

D3_DQ_B35

D3_DQ_B34

D3_DQ_B33

200

201

DQ3281DQ3382DQ3487DQ3588DQ36

CKE050CKE1

S0

S176CK1/NU64CK1/NU63CK0*

193

D3_DQ_B38

206

DQ37

DQ38

D3_DQ_B39

D3_DQ_B41

D3_DQ_B40

207

DQ39

DQ4090DQ4191DQ4296DQ4397DQ44

CK0

185

184A0188A1181

D3_DQ_B42

D3_DQ_B43

D3_DQ_B44

209

D3_DQ_B45

210

D3_DQ_B46

215

DQ45

A261A3

180

D3_DQ_B47

216

DQ46

D3_DQ_B49

D3_DQ_B48

100

DQ47

DQ4899DQ49

A459A558A6

178

D3_DQ_B50

105

DQ50

A756A9

D3_DQ_B51

106

177

D3_DQ_B52

218

DQ51

A8

175

D3_DQ_B53

219

DQ52

D3_DQ_B54

224

DQ53

DQ54

A10/AP70A1155A12

D3_DQ_B55

225

174

D3_DQ_B56

108

DQ55

196

D3_DQ_B57

109

DQ56

A13

172

D3_DQ_B58

114

DQ57

A14

171

D3_DQ_B59

115

DQ58

A15

D3_DQ_B60

227

DQ59

168

D3_DQ_B61

228

DQ60

RESET

D3_DQ_B62

233

DQ61

CAS74RAS

192

D3_DQ_B63

234

DQ62

73

DQ63

WE

1

DIMM4

DIMM4 DDRIII

DDRIII

D3_DQ_B[63..0] 12,18

+1P5V_SM_VTT

+1P5V_SM

CLOSE TO DIMM POWER PIN

+1P5V_SM

CD28

CD26

CD25

1uF

*

6.3V,X5R,+/-10%

+1P5V_SM_VTT

B B

CD29

*

4.7uF

6.3V, X5R, +/-10%

CD26

1uF

*

6.3V,X5R,+/-10%

CD30

*

0.1uF

16V, X7R, +/-10%

CD27

1uF

*

6.3V,X5R,+/-10%

CD28

1uF

*

6.3V,X5R,+/-10%

SB_BS[0]-->Pin 71 (BA0) SB_BS[1]-->Pin 190 (BA1) SB_BS[2]-->Pin 52 (BA2) ; CRB 0.7-12/10/09

S_SMBCLK_MAIN15,16,18,32,52

S_SMBDATA_MAIN15,16,18,32,52

D3_BAB[2..0]12,18

D3_CKE_B112 D3_CKE_B012

D3_SCS_B#112 D3_SCS_B#012

D3_MB_CLK#112 D3_MB_CLK112 D3_MB_CLK#012 D3_MB_CLK012

D3_MAB[15..0]12,18

PLAECE CLOSE TO CH-B DIMM

+1P5V_SM

RD13 1K

*

+/-1%

*

CD31

0.1uF

16V, X7R, +/-10%

Dummy

+/-1%

RD14

*

1K

+/-1%

Change to 0.1uF; PDG 0.7-12/07/09

+1P5V_SM

RD15 1K

*

A A

*

CD33

0.1uF

16V, X7R, +/-10%

*

+/-1%

RD16

*

1K

+/-1%

5

D3_DQ_VREF_B

*

CD32

0.1uF

16V, X7R, +/-10%

*

CD34

0.1uF

16V, X7R, +/-10%

D3_CA_VREF_B 18

CD56

*

2.2uF

6.3V, Y5V, +80%/-20%

Dummy

D3_DQ_VREF_B 18

Add CD54,CD55; follow CRB 0.7-12/28/09 Del CD54,CD5512/29/09

4

3

+3V

D3_CA_VREF_B D3_DQ_VREF_B

D3_BAB2 D3_BAB1 D3_BAB0

D3_MAB0 D3_MAB1 D3_MAB2 D3_MAB3 D3_MAB4 D3_MAB5 D3_MAB6 D3_MAB7 D3_MAB8 D3_MAB9 D3_MAB10 D3_MAB11 D3_MAB12 D3_MAB13 D3_MAB14 D3_MAB15

010

Title

DDR3 Conn: CHB_1 (DIMM4)

DWG NO Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet of

DDR3 Conn: CHB_1 (DIMM4)

Lanikai _MT/DT

D3_WEB# 12,18 D3_RASB# 12,18 D3_CASB# 12,18 D3_RESET# 11,15,16,18

17 71Wednesday, June 13, 2012

1

A00

of

5

CHANNEL B BANK 2 SMB ADDRESS:011

D3_ECC_CB_B[7..0] 12,17

4

D3_DQS_B8 12,17 D3_DQS_B#8 12,17

3

2

1

D3_ODT_B3 12 D3_ODT_B2 12

D D

D3_DQS_B#3

D3_DQS_B#2

D3_DQS_B#1

D3_DQS_B#0

D3_DQS_B1

VSS

D3_DQS_B0

D3_ECC_CB_B5

D3_ECC_CB_B6

D3_ECC_CB_B7

6

159

164

165

DQS07DQS0

CB<5>

CB<6>

CB<7>

VSS

208

205

202

199

166

163

160

157

154

D3_ECC_CB_B2

D3_ECC_CB_B3

D3_ECC_CB_B4

D3_ECC_CB_B1

D3_ECC_CB_B0

79

RSVD

C C

FREE1

198

187

+1P5V_SM_VTT

195

ODT177ODT0

FREE2

FREE349FREE4

48

53

167

68

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

VSS

VTT

239

235

232

120

240

229

VSS

226

223

158

CB<0>39CB<1>40CB<2>45CB<3>46CB<4>

VSS

220

217

214

211

DQS116DQS1

VSS

D3_DQS_B3

D3_DQS_B2

33

24

15

DQS334DQS3

DQS225DQS2

VSS

151

148

145

142

139

136

133

VSS

D3_DQS_B#5

D3_DQS_B#4

D3_DQS_B5

D3_DQS_B4

93

84

DQS594DQS5

DQS485DQS4

VSS

130

127

124

121

116

VSS

D3_DQS_B#7

D3_DQS_B#6

D3_DQS_B7

D3_DQS_B6

112

103

102

DQS6

VSS

113

110

107

104

101

125

134

135

126

42

111

DQS9

DQS843DQS8

DQS7

DM0/DQS9

DM1/DQS10

VSS

VSS98VSS95VSS92VSS89VSS86VSS83VSS80VSS47VSS44VSS41VSS38VSS35VSS32VSS29VSS26VSS23VSS20VSS17VSS14VSS11VSS8VSS5VSS2VDDQ

CLOSE TO DIMM POWER PIN

+1P5V_SM

CD37

CD35

1uF

*

6.3V,X5R,+/-10%

+1P5V_SM_VTT

B B

CD41

*

4.7uF

6.3V, X5R, +/-10%

CD36

1uF

*

6.3V,X5R,+/-10%

CD42

*

0.1uF

16V, X7R, +/-10%

CD37

1uF

*

6.3V,X5R,+/-10%

CD38

1uF

*

6.3V,X5R,+/-10%

S_SMBCLK_MAIN15,16,17,32,52 S_SMBDATA_MAIN15,16,17,32,52

Decouple Cap for all 4 DIMMs

SB_BS[0]-->Pin 71 (BA0) SB_BS[1]-->Pin 190 (BA1) SB_BS[2]-->Pin 52 (BA2) ; CRB 0.7-12/10/09

143

144

DQS11

DQS10

DM2/DQS11

D3_DQS_B[7..0] 12,17 D3_DQS_B#[7..0] 12,17

212

203

152

153

DM3/DQS12

DQS12

204

DQS13

DM4/DQS13

+1P5V_SM

50V, NPO, +/-5%

CD39

*

22pF

Dummy

213

DQS14

DM5/DQS14

*

221

DM6/DQS15

CD40

22pF

Dummy

D3_DQ_B[63..0] 12,17

D3_DQ_B39

D3_DQ_B38

D3_DQ_B37

D3_DQ_B36

D3_DQ_B35

D3_DQ_B34

D3_DQ_B33

D3_DQ_B32

D3_DQ_B31

D3_DQ_B30

D3_DQ_B29

D3_DQ_B28

D3_DQ_B27

D3_DQ_B26

D3_DQ_B25

D3_DQ_B24

D3_DQ_B23

D3_DQ_B22

D3_DQ_B21

D3_DQ_B20

D3_DQ_B19

D3_DQ_B18

D3_DQ_B17

D3_DQ_B16

D3_DQ_B15

D3_DQ_B14

D3_DQ_B13

D3_DQ_B12

D3_DQ_B11

D3_DQ_B10

D3_DQ_B9

D3_DQ_B8

D3_DQ_B7

D3_DQ_B6

D3_DQ_B5

D3_DQ_B4

D3_DQ_B3

D3_DQ_B2

D3_DQ_B1

D3_DQ_B0

122

123

128

129

13

131

132

137

138

140

141

146

147

149

150

155

156

200

201

206

161

230

162

231

222

DQ03DQ14DQ29DQ310DQ4

DQ5

DQ6

DQ7

DQ812DQ9

DQ1018DQ1119DQ12

DQ13

DQ14

DQ15

DQ1621DQ1722DQ1827DQ1928DQ20

DQ21

DQ22

DQ23

DQ2430DQ2531DQ2636DQ2737DQ28

DQ29

DQ30

DQ31

BA2

DQ3281DQ3382DQ3487DQ3588DQ36

BA071BA1

CKE050CKE1

190

169

DQS17

DQS15

NC/DQS16

DM8/DQS17

DM7/DQS16

VDDQ

197

194

191

189

186

183

182

179

50V, NPO, +/-5%

D3_MAB[15..0]12,17

DDRIII

VDDQ

VDD78VDD75VDD72VDD69VDD66VDD65VDD62VDD60VDD57VDD54VDD51VDDSPD

176

173

170

+3V

D3_CA_VREF_B17 D3_DQ_VREF_B17

D3_BAB[2..0]12,17

D3_CKE_B312 D3_CKE_B212

D3_SCS_B#312 D3_SCS_B#212

D3_MB_CLK#312 D3_MB_CLK312 D3_MB_CLK#212 D3_MB_CLK212

D3_MAB0 D3_MAB1 D3_MAB2 D3_MAB3 D3_MAB4 D3_MAB5 D3_MAB6 D3_MAB7 D3_MAB8 D3_MAB9 D3_MAB10 D3_MAB11 D3_MAB12 D3_MAB13 D3_MAB14 D3_MAB15

236

VREFCA

67

D3_BAB2 D3_BAB1 D3_BAB0

VREFDQ1SCL

SA2

SDA

SA1

SA0

52

119

118

238

237

117

011

207

DQ37

DQ38

S0

S176CK1/NU64CK1/NU63CK0*

193

D3_DQ_B43

D3_DQ_B42

D3_DQ_B41

D3_DQ_B40

DQ39

DQ4090DQ4191DQ4296DQ4397DQ44

CK0

185

184A0188A1181

D3_DQ_B44

209

D3_DQ_B45

210

D3_DQ_B46

215

DQ45

A261A3

180

D3_DQ_B47

216

DQ46

D3_DQ_B49

D3_DQ_B48

100

DQ47

DQ4899DQ49

A459A558A6

178

D3_DQ_B51

D3_DQ_B50

105

106

DQ50

A756A9

177

D3_DQ_B52

218

DQ51

A8

175

D3_DQ_B53

219

DQ52

D3_DQ_B54

224

DQ53

A10/AP70A1155A12

D3_DQ_B55

225

DQ54

DQ55

174

D3_DQ_B56

108

196

D3_DQ_B57

109

DQ56

A13

172

D3_DQ_B58

114

DQ57

A14

171

D3_DQ_B59

115

DQ58

A15

D3_DQ_B60

227

DQ59

168

D3_DQ_B61

228

DQ60

RESET

D3_DQ_B62

233

DQ61

CAS74RAS

192

D3_DQ_B63

234

DQ62

73

DQ63

WE

DIMM2

DIMM2 DDRIII

DDRIII

D3_WEB# 12,17 D3_RASB# 12,17 D3_CASB# 12,17 D3_RESET# 11,15,16,17

A A

D3_DQ_VREF_B_R

CD46

1uF

*

6.3V,X5R,+/-10%

Dummy

5

4

3

RD17 0

*

H_CPU_DIMM_VREF_B 9

0

*

RD19

Dummy

*

16V, X7R, +/-10%

CD55

0.1uF

Dummy

D3_DQ_VREF_B 17

CD54

*

0.1uF

Dummy

16V, X7R, +/-10%

Add CD54,CD55; follow CRB 0.7-12/28/09

2

Title

DDR3 Conn: CHB_2 (DIMM2)

DWG NO Rev

Date: Sheet

Date: Sheet of

DDR3 Conn: CHB_2 (DIMM2)

Lanikai _MT/DT

18 71Wednesday, June 13, 2012

1

A00

of

5

D D

4

3

2

1

20100106: Remove ONFI function since not support

C C

B B

A A

Title

TBD

DWG NO Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

TBD

Lanikai _MT/DT

1

A00

of

19 71Wednesday, June 13, 2012

5

D D

C C

4

3

2

1

B B

A A

Title

Clock GEN

DWG NO Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

Clock GEN

Lanikai _MT/DT

1

A00

of

20 71Wednesday, June 13, 2012

5

4

3

2

1

D D

US1A

K_GNT#1 K_GNT#2 K_GNT#3

K_REQ#0 K_REQ#1 K_REQ#2 K_REQ#3

BH8

PAR

BH9

DEVSEL#

BD15

CLKIN_PCILOOPBACK

AV14

PCIRST#

BF11

IRDY#

AV15

PME#

BR6

SERR#

BC12

STOP#

BA17

PLOCK#

BC8

TRDY#

BM3

PERR#

BC11

FRAME#

BA15

GNT0#

AV8

GNT1# / GPIO51

BU12

GNT2# / GPIO53

BE2

GNT3# / GPIO55

BG5

REQ0#

BT5

REQ1# / GPIO50

BK8

REQ2# / GPIO52

AV11

REQ3# / GPIO54

BK10

PIRQA#

BJ5

PIRQB#

BM15

PIRQC#

BP5

PIRQD#

BN9

PIRQE# / GPIO2

AV9

PIRQF# / GPIO3

BT15

PIRQG# / GPIO4

BR4

PIRQH# / GPIO5

BD82Q67

1/12

PCI

Change AV14 to K_PCIRST#_SLOT-12/28/09

K_PAR58 K_DEVSEL#58

C_PCI_SB27

K_PCIRST#_SLOT58

K_IRDY#58 K_PME#58 K_SERR#58 K_STOP#58 K_LOCK#58 K_TRDY#58 K_PERR#58 K_FRAME#58

GNT [3:0] have Internal Pull-High to 3.3V

K_GNT#058

K_REQ#058

C C

K_INTA#58 K_INTB#58 K_INTC#58

PCIE_MINI_CPUSB_DETECT#

PCIE_MINI_CPPE_DETECT#

K_INTD#58

V_DDSP_C_HPD26,41 V_GPI_VGA_CBL_DET#42

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8

AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

C/BE0# C/BE1# C/BE2# C/BE3#

BF15 BF17 BT7 BT13 BG12 BN11 BJ12 BU9 BR12 BJ3 BR9 BJ10 BM8 BF3 BN2 BE4 BE6 BG15 BC6 BT11 BA14 BL2 BC4 BL4 BC2 BM13 BA9 BF9 BA8 BF8 AV17 BK12

BN4 BP7 BG2 BP13

K_AD0K_AD0 K_AD1K_AD1 K_AD2K_AD2 K_AD3K_AD3 K_AD4K_AD4 K_AD5K_AD5 K_AD6K_AD6 K_AD7K_AD7 K_AD8K_AD8 K_AD9K_AD9 K_AD10K_AD10 K_AD11K_AD11 K_AD12K_AD12 K_AD13K_AD13 K_AD14K_AD14 K_AD15K_AD15 K_AD16K_AD16 K_AD17K_AD17 K_AD18K_AD18 K_AD19K_AD19 K_AD20K_AD20 K_AD21K_AD21 K_AD22K_AD22 K_AD23K_AD23 K_AD24K_AD24 K_AD25K_AD25 K_AD26K_AD26 K_AD27K_AD27 K_AD28K_AD28 K_AD29K_AD29 K_AD30K_AD30 K_AD31K_AD31

K_C/BE#0 K_C/BE#1 K_C/BE#2 K_C/BE#3

K_AD[31..0] 58

K_C/BE#[3..0] 58

K_INTF# change to V_DDSP_C_HPD-12/30/09

20100108: Remove V_DDSP_C_HPD pull-up

Left bioth SATA/GPIO19 and GNT1# floating. No pull up required for Default(SPI)

B B

+3V

*

RS171

RS14

10K

1K

Dummy

K_GNT#153 S_SATA1GP23,53

*

RS201

RS20

1K

Dummy

20091209: Have to check with Intel

20091230: Reserved RS171 and RS201 for Boot select

Boot BIOS Select

Boot Device

LPC PCI

NAND 0

SPI

GNT1 SATA1GP

00 1

11

0 1

K_INTA# K_INTB# K_INTC# K_INTD#

PCIE_MINI_CPUSB_DETECT# V_GPI_VGA_CBL_DET#

PCIE_MINI_CPPE_DETECT#

K_REQ#0 K_REQ#1 K_REQ#2 K_REQ#3

K_FRAME# K_IRDY# K_TRDY# K_DEVSEL#

K_STOP# K_LOCK# K_PERR# K_SERR#

K_PME#

K_PME# add RS198 to pull-up +3V_PCIAUX; 20100108:

CRB 0.7-12/28/09 Dummy RS198; PDG 0.8

RNK1

*

1 3 5 7 8

8.2K

*

RS7 8.2K +/-5%

*

RS8 8.2K +/-5%

*

RS9 8.2K +/-5%

*

RS10 8.2K+/-5%

*

RNK4

*

1 3 5 7 8

8.2K

RNK5

*

1 3 5 7 8

8.2K

RS198 8.2K +/-5%

GNT3# Internal pull-up.

K_GNT#2 K_GNT#3

DG 0.7 GNT3 is top block swap mode: connect to ground with 4.7k ohm weak pull down resistor for top block swap mode

GNT2#/GPIO53:ESI strap for server platform ONLY,Do not pull low.

RNK2

1 3 5 7 8

8.2K

*

2 4 6

+3V_PCIAUX

Dummy

RS15 1K

RS15 1K RS17 4.7K

RS17 4.7K

+3V

*

* *

*

Dummy

K_GNT#0

+3V

*

RS13

RS13 1K

1K

Dummy

*

RS18

RS18 1K

1K

Dummy

A A

Title

PCH-1: PCI

DWG NO Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

PCH-1: PCI

Lanikai _MT/DT

1

A00

of

21 71Wednesday, June 13, 2012

5

M41

M17 M15

D33 B33

H36 A36 B35 P38 R38 B37 C36 H38

E37 F38

P41 B31 E31

P33 R33

L20 P20 R20 H17

P17 N15

L15 H12

H10 F25

F23 C22 A22 E21 B21 F18 E17 B17 C16 A16 B15 F15 F13 B13 D13

J36

J38

J20

J17

J15 J12

J10

H_DMI_TXN010 H_DMI_TXP010 H_DMI_RXN010 H_DMI_RXP010 H_DMI_TXN110 H_DMI_TXP110 H_DMI_RXN110 H_DMI_RXP110 H_DMI_TXN210 H_DMI_TXP210 H_DMI_RXN210

D D

+1P05V_PCH

C C

H_DMI_RXP210 H_DMI_TXN310 H_DMI_TXP310 H_DMI_RXN310 H_DMI_RXP310

RS24 49.9 +/-1%

*

C_DMI_PCH#27 C_DMI_PCH27

TPS15TPS15 TPS16TPS16

X_2X1_RXN59 X_2X1_RXP59 X_L1X1_RXN34 X_L1X1_RXP34 X_1X4_RXN039 X_1X4_RXP039 X_1X4_RXN139 X_1X4_RXP139 X_1X4_RXN239 X_1X4_RXP239 X_1X4_RXN339 X_1X4_RXP339

TPS17TPS17 TPS26TPS26

X_2X1_TXN59 X_2X1_TXP59 X_L1X1_TXN34 X_L1X1_TXP34 X_1X4_TXN039 X_1X4_TXP039 X_1X4_TXN139 X_1X4_TXP139 X_1X4_TXN239 X_1X4_TXP239 X_1X4_TXN339 X_1X4_TXP339

S_DMI_COMP

L<0.5"

X_1X1_RXN X_1X1_RXP

TPS6TPS6

X_1X1_TXN X_1X1_TXP

US1B

DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP DMI_IRCOMP DMI_ZCOMP

CLKIN_DMI_N CLKIN_DMI_P

PERN1 PERP1 PERN2 PERP2 PERN3 PERP3 PERN4 PERP4 PERN5 PERP5 PERN6 PERP6 PERN7 PERP7 PERN8 PERP8 PETN1 PETP1 PETN2 PETP2 PETN3 PETP3 PETN4 PETP4 PETN5 PETP5 PETN6 PETP6 PETN7 PETP7 PETN8 PETP8

BD82Q67

4

DMI

PCI-E

2/12

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P

USB

USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

USBRBIAS#

USBRBIAS

CLKIN_DOT_96N CLKIN_DOT_96P

DMI2RBIAS

L_BKLTCTL

L_BKLTEN

L_VDD_EN

BF36 BD36 BC33 BA33 BM33 BM35 BT33 BU32 BR32 BT31 BN29 BM30 BK33 BJ33 BF31 BD31 BN27 BR29 BR26 BT27 BK25 BJ25 BJ31 BK31 BF27 BD27 BJ27 BK27

BM43 BD41 BG41 BK43 BP43 BJ41 BT45 BM45

BP25 BM25

BD38 BF38

A32 AG12

AG18 AG17

S_USBRBIAS_PCH

L <=200 MILS

TPS8TPS8 TPS9TPS9 TPS10TPS10

3

U_USB0N 57 U_USB0P 57 U_USB1N 57 U_USB1P 57 U_USB2N 45 U_USB2P 45 U_USB3N 45 U_USB3P 45 U_USB4N 45 U_USB4P 45 U_USB5N 45 U_USB5P 45

U_USB8N 35 U_USB8P 35 U_USB9N 35 U_USB9P 35 U_USB10N 56 U_USB10P 56 U_USB11N 56 U_USB11P 56 U_USB12N 61 U_USB12P 61 U_USB13N 61 U_USB13P 61

U_USB_OC_R_#0 57 U_USB_OC_R_#1 45 U_USB_OC_R_#2 45 U_USB_OC_R_#3 45 U_USB_OC_R_#4 35 U_USB_OC_R_#5 56 U_USB_OC_R_#6 61 GPO_WLOM 59

RS25 22.6

C_96M_PCH# 27 C_96M_PCH 27

RS26 750

*

+/-1%

2

20112012 Update USB 2.0 Distrubution for match USB 3.0

U_USB_OC_R_#6

+3V_S5

RS23

RS196

RS21

*

8.2K

+/-5%

*

8.2K

+/-5%

Dummy

*

RS196

8.2K

+/-5%

Dummy

U_USB_OC_R_#1 U_USB_OC_R_#2 U_USB_OC_R_#3

U_USB_OC_R_#4 U_USB_OC_R_#5

GPO_WLOM

RS82 10K

*

Dummy

CU1 0.1uF

16V, X7R, +/-10%

*

CU2 0.1uF

16V, X7R, +/-10%

*

CU3 0.1uF

16V, X7R, +/-10%

*

CU18 0.1uF

16V, X7R, +/-10%

*

CU4 0.1uF

16V, X7R, +/-10%

*

CU6 0.1uF

16V, X7R, +/-10%

*

1

+3V_S5

Dummy

Dummy Dummy

Dummy

Dummy Dummy

Dummy

B B

There are 4 oc pin in Controler 1 and USB 3.0 port number must be match USB 2.0,If 4*OC pin used for USB3.0, Port 4/5 will not has OC pin function can usage

A A

Intel

Title

PCH-2: DMI/PCIe/USB

DWG NO Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

PCH-2: DMI/PCIe/USB

Lanikai _MT/DT

22 71Wednesday, June 13, 2012

1

A00

of

5

4

3

2

1

S_INIT3_3VB

US1C

20100107:Remove test points

20100105:Remove Test

D D

20100107: Remove RS47, RS48 and connect S_PCH_MEPWROK_R to S_PCH_MEPWROK directly

20100104: Add TPS23,TPS25 and remove RS29,RS30,RS33, RS34 since useless this function

S_GPI_PCH_HS_DET#30

S_GPI_BRD_REV231

S_USB_HDR_DET#57 S_FP_CHAS_DET#56

Add RS 144 and pull-up to +3V; CRB

0.7-12/07/09

C C

Point

S_GPI_CHASSIS_ID131 S_GPI_CHASSIS_ID031

S_GPI_SKU231

V_DDSP_B_HPD26,40

S_GPI_CHASSIS_ID231

TPS45TPS45 TPS46TPS46 TPS47TPS47

PCH_MEPWRGD66

TPS23TPS23 TPS25TPS25 TPS18TPS18 TPS19TPS19

S_CLINK_CLK_LAN S_CLINK_DATA_LAN S_CLINK_RST_LAN#

S_TP_CPUFAN_PWM S_TP_CHAFAN1_PWM S_TP_CHAFAN2_PWM S_TP_CHAFAN3_PWM

RS144 10K

+3V

FAN control from SMSC 5544 without using SST

TPS30TPS30 TPS31TPS31 TPS32TPS32 TPS33TPS33

TPS28TPS28

S_PCH_CONFIG_JUMPER A_FP_PRES#

AE49

TP13

AE41

TP14

BA50

CL_CLK1

BF50

CL_DATA1

BF49

CL_RST1#

BC46

APWROK

BN21

PWM0

BT21

PWM1

BM20

PWM2

BN19

PWM3

BT17

TACH0 / GPIO17

BR19

TACH1 / GPIO1

BA22

TACH2 / GPIO6

BR16

TACH3 / GPIO7

BU16

TACH4 / GPIO68

BM18

TACH5/ GPIO69

BN17

TACH6 / GPIO70

BP15

*

TACH7 / GPIO71

BC43

SST

BA53

SCLOCK / GPIO22

BF55

SDATAOUT0 / GPIO39

AW53

SDATAOUT1 / GPIO48

BE54

SLOAD / GPIO38

A54

NC_1

A52

NC_2

F57

NC_3

D57

NC_4

AY20

NC_5

BD82Q67

3/12

CLINK FAN

SATA

CLKIN_SATA_N / CKSSCD_N

CLKIN_SATA_P / CKSSCD_P

GPIO

HOST

SATAICOMPI

SATAICOMPO

SATA0GP / GPIO21 SATA1GP / GPIO19 SATA2GP / GPIO36 SATA3GP / GPIO37 SATA4GP / GPIO16 SATA5GP / GPIO49

SATA3COMPI

SATA3RBIAS

SATA3RCOMPO

THRMTRIP#

SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA2RXN SATA2RXP SATA2TXN SATA2TXP SATA3RXN SATA3RXP SATA3TXN SATA3TXP SATA4RXN SATA4RXP SATA4TXN SATA4TXP SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATALED#

TP8

A20GATE

INIT3_3V#

RCIN#

SERIRQ

PECI

PMSYNCH

AC56 AB55 AE46 AE44 AA53 AA56 AG49 AG47 AL50 AL49 AL56 AL53 AN46 AN44 AN56 AM55 AN49 AN50 AT50 AT49 AT46 AT44 AV50 AV49 AF55 AG56

BF57 AJ55

AJ53 BC54

AY52 BB55 BG53 AU56 BA56

AE54 AC52 AE52

AB18 BB57

BN56 BG56 AV52 E56 H48 F55

TPS34TPS34 TPS52TPS52 TPS54TPS54 TPS56TPS56 TPS20TPS20 TPS21TPS21 TPS22TPS22 TPS24TPS24

S_SATARBIAS_PCH

S_TP_GPIO36 S_TP_GPIO37

H_SKTOCC_R_#

RS37 49.9

RS38 750

RS37 49.9

*

20100107:Remove test points

RS39 0

*

Dummy

T_SATA_RXN0 43 T_SATA_RXP0 43 T_SATA_TXN0 43 T_SATA_TXP0 43 T_SATA_RXN1 43 T_SATA_RXP1 43 T_SATA_TXN1 43 T_SATA_TXP1 43 T_SATA_RXN2 43 T_SATA_RXP2 43 T_SATA_TXN2 43 T_SATA_TXP2 43 T_SATA_RXN3 60 T_SATA_RXP3 60 T_SATA_TXN3 60 T_SATA_TXP3 60

C_SATA_PCH# 27 C_SATA_PCH 27

T_SATALED# 56

RS36 37.4 Ohm

*

+/-1%

S_GPI_BRD_REV0 31 S_SATA1GP 21,53

TMIN_SHIFT 32

+/-1%

O_GA20 32 S_INIT3_3VB 53 O_KB_RST# 32

F_SERIRQ# 32,46 H_THERMTRIP# 9 H_PECI 9,32 H_PM_SYNC 9

+/-1%

*

+/-1%

+1P05V_PCH

check : using 37.4 ohm in DG , 49.9 ohm in CRB

20091209: CRB0.7 and 20091214: RS36 change to 37.4

PDG0.7 are suggested ohm

37.4 ohm 20091209: CRB0.7 V_DDSP_C_HPD is connected

to PCH pin N2 only , no connected to

+1P05V_PCH

GPIO19,check whether RS35 need stuff for meet Intel PDG ?

20091230: Change to S_SATA1GP for Boot Select

Dummy RS39; SMSC suggestion-12/08/09

This signal should not be pulled low on EDS 0.5- Sherlock 10/27/09

O_KB_RST# O_GA20 F_SERIRQ#

S_GPI_PCH_HS_DET#

A_FP_PRES#56

S_TP_GPIO36

S_TP_GPIO37

RS27 1K

*

Dummy

RS28 10K

RS28 10K RS31 10K

RS31 10K RS32 10K

RS32 10K

RS58 10K

RS58 10K RS61 10K

RS61 10K

RS124 8.2K +/-5%

RS125 8.2K +/-5%

*

* *

*

Dummy

*

Dummy

+3V

B B

A A

5

PCH_CONFIG

S_PCH_CONFIG_JUMPER

4

+3V

*

RS55

RS55 1K

1K

RS60

4.7K

Dummy

20100107: Remove RS47, RS48 and connect S_PCH_MEPWROK_R to S_PCH_MEPWROK directly

3

H_SKTOCC_R_#

2

+3V

*

RS53

RS53 10K

10K

RS57 0

*

Dummy

*

RS59

STUFF RS57 FOR ME ON CPU

10K

PRESENT DETECTION

Dummy

Title

PCH-3: SATA/HOST/FAN

DWG NO Rev

Date: Sheet

Date: Sheet of

PCH-3: SATA/HOST/FAN

Lanikai _MT/DT

H_SKTOCC# 9,24

1

23 71Wednesday, June 13, 2012

A00

of

5

+3V +3V

+3V_DUAL

Dummy

RS81 10K

+3V_S5

RS72 10K

RS72 10K RS83 10K

RS83 10K

D D

RS73 10K

RS73 10K RS85 2.2K

RS85 2.2K RS86 2.2K

RS86 2.2K

Dummy

RS74 10K

RS74 10K RS76 10K

RS76 10K

Dummy

RS89 1K

CPT FLASH DESCRIPT OR OVERRIDE.HIGH FOR OVERRIDE

Dummy

RS91 1K

OD PLL VR SUPPLY SEL(internal pull down)

1.8V SUPPLY WHEN SAMPLED LOW

1.5V SUPPLY WHEB SAMPLED HIGH

S_SUSWARN#

C C

+3V_S5

RF1

*

10K

Dummy

S_GPIO57_PD

*

RF2

RF2 47K

47K

B B

+3V

RF3

*

8.2K

+/-5%

Dummy

F_SPI_MOSI_PRI_SEC_FLSH

A A

20091223: signal rename to S_SUSWARN#

S_SUSWARN#

*

S_MFG_MODE_OR

*

S_SMLINK1_CLK

*

S_SMLINK1_DATA

*

S_SMLINK0_CLK

*

S_SMLINK0_DATA

*

F_SPI_CS1#_ISOLATE

*

X4_WAKE#

*

RS197

RS197 1K

1K

Dummy

S_SMBDATA_PCI32,38,39,58,59

Integrated TPM High to Enable Low to Disable Internal pull-down

+5VSB

A_Z_SDOUT 31,36

A_Z_SYNC_R

20091223: Add RS151, RS197 DS mode: 20100104: Remove RS151, P.64 has same circuit

S_SMBCLK_PCI32,38,39,58,59

CS2

22pF

*

Dummy

50V, NPO, +/-5%

O_RSMRST#32

SMSC recommend 01/13/11

4.7K

RS115

*

4 3

*

5

CS3

22pF

*

Dummy

F_SPI_MOSI_PRI_SEC_FLSH51

F_SPI_CLK_PRI_SEC_FLSH51

RS116

*

2KOhm

+/-1%

16

2

5

S_PCH_DPWROK

RS120 1K

RS120 1K CS8

CS8

1uF

+/-10%

Dummy

F_LAD032,46,53 F_LAD132,46,53 F_LAD232,46,53 F_LAD332,46,53 F_LDRQ#32 F_FRAME#32,46,53

RS77 33

*

A_Z_BITCLK36 A_Z_RST#36

A_Z_SDIN036

TPS35TPS35 TPS36TPS36

TPS37TPS37

A_Z_SDOUT31,36 A_Z_SYNC36

50V, NPO, +/-5%

20091223: BU49 signal name change to X_WLAN_WAKE#

F_SPI_MISO51

F_SPI_CS0#_ISOLATE51 F_SPI_CS1#_ISOLATE51

*

RS112

QS2

SMSC recommend

MMDT5551

01/13/11

RS121 5.6K

*

RS122

*

1.1KOhm

+/-1%

*

RS78 33

*

RS90 0

*

RS92 33

*

FVS

Dummy

TEST POINT

S_RTCRST#29,31,53

X4_WAKE#39

GPIO_WIRELESS_DISABLE#

S_SMLINK0_CLK34

S_SMLINK0_DATA34

S_MFG_MODE_OR31

S_SMLINK1_CLK32

S_SMLINK1_DATA32

CLOSE TO PCH 0 OHM FOR DEFENSIVE DESIGN 66MHZ SPI TOPOLOGY,

1K

RS113

*

10K

+/-1%

*

+/-1%

1

CA

Dummy

+5VSB

RS65

*

10K

Dummy

A_Z_BITCLK_R A_Z_RST#_R

A_Z_SDOUT_R A_Z_SYNC_R

L_DRQ1#

S_PCH_RTCX1 S_PCH_RTCX2

S_SRTRST#

S_PCH_DPWROK

BAT54HT1G

BAT54HT1G DS3

DS3

S_RSMRST#

B

*

RS123

RS123 2KOhm

2KOhm

+/-1%

4

Internal pull-up

RS66

*

10K

Dummy

L_DRQ1#

RS117

*

10K

+/-1%

QS3

QS3 MMBT3904-7-F

MMBT3904-7-F

E C

4

SPKR Control Option of SIO / PCH

S_SPKR_OUT31

US1D

BA20

LDRQ1# / GPIO23

BK15

FWH0 / LAD0

BJ17

FWH1 / LAD1

BJ20

FWH2 / LAD2

BG20

FWH3 / LAD3

BK17

LDRQ0#

BG17

FWH4 / LFRAME#

BU22

HDA_BCLK

BC22

HDA_RST#

BD22

HDA_SDIN0

BF22

HDA_SDIN1

BK22

HDA_SDIN2

BJ22

HDA_SDIN3

BT23

HDA_SDO

BP23

HDA_SYNC

BR39

RTCX1

BN39

RTCX2

BT41

RTCRST#

BN37

SRTCRST#

BN49

SMBALERT# / GPIO11

BT47

SMBCLK

BR49

SMBDATA

BU49

SML0ALERT# / GPIO60

BT51

SML0CLK

BM50

SML0DATA

BR46

SML1ALERT#/PCHHOT#/GPIO74

BJ46

SML1CLK / GPIO58

BK46

SML1DATA / GP75

AU53

SPI_MOSI

AT55

SPI_MISO

AT57

SPI_CS0#

AR54

SPI_CLK

AR56

SPI_CS1#

BD82Q67

S_INTVRMEN

Internal 1.1V and VCCME regulator enable(high)/disable(low)

*

DSWODVREN

RS107 390KOhm

RS107 390KOhm RS108

RS108 1K

1K

Dummy

RS114 390KOhm

RTC

S_PCH_RTCX2

S_PCH_RTCX1

X'TAL

CS9

*

10pF

50V, NPO, +/-5%

RS118 10M

3

S_SPKR Pop To Enable No-Reboot Iinternal pull-down.

SUSWARN# / SUSPWRDNACK / GPIO30

LAN_PHY_PWR_CTRL / GPIO12

LPC AUDIO RTC SMB SPI

4/12

+VCCRTC

*

+/-5%

*

+/-5%

XTAL 32.768KHz

XS1

1 4

2

3

BMBUSY# / GPIO0

SLP_LAN# / GPIO29

HDA_DOCK_RST# / GPIO13

PCIECLKRQ2# / GPIO20

MEM_LED / GPIO24

CLKRUN#/GPIO32

HDA_DOCK_EN#/GPIO33

STP_PCI# / GPIO34

PCIECLKRQ5# / GPIO44 PCIECLKRQ6# / GPIO45 PCIECLKRQ7# / GPIO46

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

BATLOW#/GPIO72

JTAG_RST/TP12

+VCCRTC

+/-5%

CS10

*

10pF

50V, NPO, +/-5%

3

RS63 1K

Dummy

GPIO8

GPIO15

GPIO27 GPIO28 GPIO31

GPIO35

GPIO57

PROCPWRGD

SLP_SUS#

SYS_PWROK

PWRBTN#

SYS_RESET#

PLTRST#

WAKE#

INTRUDER#

PWROK

RSMRST#

INTVRMEN

SPKR

SUSACK#

SLP_S3# SLP_S4#

SLP_A#

DSWVRMEN

DRAMPWROK

DPWROK

JTAG_TCK

JTAG_TDI JTAG_TDO JTAG_TMS

+3V+3V

*

AW55 BP51

S_TP_GP8

BH49 BU46 BK50 BA25 BM55

S_PCH_GP15

AV43 BP53

BJ43

S_GP27_PD

BJ55

S_PCH_GP28_PU

BG43 BC56 BC25 BL56

PCH_GPIO34

BJ57 BL54 AV44 BP55

BT53

S_GPIO57_PD

D53

BD43 BJ53

P_VR_READY

BT43 BJ48

RI#

BN54

S_LPCPD#

BA47 BE52 BK48 BC44 BM38 BJ38 BK38 BN41

S_INTVRMEN

BE56

S_SPKR_OUT

BP45

S_SUS_PWR_ACK#

BM53 BN52 BH50 BC41

BR42

DSWODVREN

AV46

S_PCH_GP72_PU

BG46 BT37

S_PCH_DPWROK

BC49 BA43 BC52 BF47 BC50

20091224: S_TP_SLP_S5# change to S_PEG_B_CLKREQ#

*

RS67

RS67 10K

10K

S_LPCPD#

CLR_SRTC

20091214: CS4 stuffed

S_SRTRST#

+VCCRTC

*

RS105

RS105 20K

20K

CS4

*

1uF

16V, X5R, +/-10%

2

CLOCK VALIDATION STRAP EMPTY JUMPER FOR BUFFER THROUGH MODE High: Disable Intergrated Clock Chip Low: Enable Intergrated Clock Chip Has a weak Internal Pull-High

S_PECI_REQ# 32

TPS40TPS40

S_SLP_LAN# 35 S_SUSWARN# 64 L_LAN_DISABLE# 34 X1_WAKE# 59

S_FLEXBAY_HDR_CBL_DET# 27,61 H_SKTOCC# 9,23

S_PSWD_CLR 31 S_GPI_SKU0 31

TPS38TPS38

S_GPI_SKU1 31 S_INTRUD_CBL_DET# 27,31 O_COM_SER2_DET# 27 S_GPI_BRD_REV1 31

H_PWRGD 9,52,64

S_SLP_SUS# 64,65 O_PWRBTN#IN 32,52,53,56

O_IO_PME# 32 S_SUSCLK 32

FP_RST# 9,52,53 S_PLTRST# 9,32,34,46,52,53 S_WAKE# 38 S_INTRUDER# 31 PWRGD_3V 32,52

S_RSMRST# 52,64

S_SUS_PWR_ACK# 64 S_SLP_S3# 32,53,64,66,70,71

S_SLP_S4# 32,53,65,71 S_PCIAUX_GATE 65 S_SLP_M# 32,53,65,66

H_DRAMPWRGD 11

F_PCH_JTAG_RST# 52 F_PCH_JTAG_TCK_FILTER 52 F_PCH_JTAG_TDI 52 F_PCH_JTAG_TDO 52 F_PCH_JTAG_TMS 52

+3V_S5

RO1 8.2K+/-5%

*

Dummy

+3V

Near to Pch

CS5

CS6

CS7

*

0.1uF

16V, X7R, +/-10%

0.1uF

16V, X7R, +/-10%

2

CS7

*

0.1uF

S_GP27_PD

20091223: BP53 signal name change to H_SKTOCC# .

20091221: BD43 removed TPS38 and rename signal to S_SLP_SUS# ; BT37 rename S_RSMRST# to S_PCH_DPWROK_R ; BP45 rename to S_SUS_PWR_ACK

16V, X7R, +/-10%

RS71 1K

*

Dummy

20091223: BU46 signal rename to S_SUSWARN#

P_VR_READY33,52,64,67

+3V_S5

*

H_DRAMPWRGD

Title

PCH-4: LPC/HDA/RTC/SMB/SPI

DWG NO Rev

Date: Sheet of

Date: Sheet

1

H_SKTOCC# O_IO_PME# X1_WAKE# S_PCIAUX_GATE

20100106: Add RS173

S_WAKE#

20091221: Dummy RS80 follow CRB0.7

S_SUS_PWR_ACK#

S_PCH_GP72_PU S_SLP_LAN#

P_VR_READY

S_PCH_GP28_PU

20100106: Reserved RS151 for Disable 1.05V Regulator

High: Enable 1.05V Regulator Low: Disable 1.05V Regulator Has a weak Internal Pull-High Reserved for CPU VR and TPM type

20091216: RS87 used 1k , PDG0.7

S_PCH_GP15

S_GP27_PD

PCH_GPIO34 FP_RST#

20100104: Dummy RS87; follow CRB 0.7

RX8

8.2K

+/-5%

Dummy

GPIO_WIRELESS_DISABLE#

+1P5V_SM

RS93

RS93 200 Ohm

200 Ohm

+/-1%

RS94

*

3KOhm

+/-1%

Dummy

Lanikai _MT/DT

RS64 100K

RS64 100K RS68 10K

RS68 10K RS69 10K

RS69 10K RS173 10K

RS173 10K

RS79 1K

RS79 1K RS80 10K

RS80 10K

RS174 10K

RS174 10K RS75 1K

RS75 1K

RS193 10K

RS84 10K

RS84 10K RS151 1K

RS151 1K

RS119 10K

RS119 10K RS199 10K

RS199 10K

20091224: change to +3V

P_VR_READY

RS194

*

10K

Dummy

PWRGD_3V

CS72

470pF

Dummy

50V, X7R, +/-10%

1

Dummy

RS87 1K

RS88 10K

*

24 71Wednesday, June 13, 2012

*

* *

*

Dummy

*

Dummy

*

Dummy

*

* *

*

* *

*

CS43

22uF

6.3V,X5R,+/-20%

Dummy

of

+3V_S5

+3V_DUAL

+3V

A00

5

D D

4

3

2

1

20100106: Remove ONFI function since not support

S_NVR_CLE internal pull-down.

US1E

M48

NV_ALE

M_NVR_CLE9

20100107:remove test points

C C

R47

Y41 M50 M49 U43

J57

NV_CLE NV_RB# NV_RE#_WRB0 NV_RE#_WRB1 NV_WE#_CK0 NV_WE#_CK1

NVRAM

5/12

BD82Q67

NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15

NV_RCOMP

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

NV_DQS0 NV_DQS1

AB50 Y50 AB49 AB44 U49 R44 U50 U46 U44 H50

20100107:remove test points

K46 L56 J55 F53 H52 E52

K50 K49 AB46 G56

Y44 L53

R50

S_TP_NV_RCOMP

TPS29TPS29

US1G

B B

FDI_FSYNC0

FDI_LSYNC0

FDI_FSYNC1

FDI LINK

FDI_LSYNC1

7/12

BD82Q67

A A

5

4

FDI_RXN0

FDI_RXP0

FDI_RXN1

FDI_RXP1

FDI_RXN2

FDI_RXP2

FDI_RXN3

FDI_RXP3

FDI_RXN4

FDI_RXP4

FDI_RXN5

FDI_RXP5

FDI_RXN6

FDI_RXP6

FDI_RXN7

FDI_RXP7

FDI_INT

C42 B43 F45 F43 H41 J41 C46 D47 B45 A46 B47 C49 J43 H43 M43 P43

B51 E49 C52 D51

H46

H_FDI_TXN0 10 H_FDI_TXP0 10 H_FDI_TXN1 10 H_FDI_TXP1 10 H_FDI_TXN2 10 H_FDI_TXP2 10 H_FDI_TXN3 10 H_FDI_TXP3 10 H_FDI_TXN4 10 H_FDI_TXP4 10 H_FDI_TXN5 10 H_FDI_TXP5 10 H_FDI_TXN6 10 H_FDI_TXP6 10 H_FDI_TXN7 10 H_FDI_TXP7 10

H_FDI_FSYNC0 10 H_FDI_LSYNC0 10 H_FDI_FSYNC1 10 H_FDI_LSYNC1 10

H_FDI_INT 10

Title

PCH-5/7: NVRAM/FDI

DWG NO Rev

Lanikai _MT/DT

Date: Sheet

Date: Sheet of

3

2

Date: Sheet of

Lanikai _MT/DT

1

25 71Wednesday, June 13, 2012

A00

of

5

D D

V_DDSP_B_HPD23,40

*

RS128 1K

+/-1% Dummy

C C

B B

V_DDSP_C_HPD21,41

V_DDSP_B_AUX_DP40 V_DDSP_B_AUX_DN40 V_DDSP_C_AUX_DP41 V_DDSP_C_AUX_DN41

TPS42TPS42 TPS43TPS43

V_DDSP_B_DP_0_DP40 V_DDSP_B_DP_0_DN40 V_DDSP_B_DP_1_DP40 V_DDSP_B_DP_1_DN40 V_DDSP_B_DP_2_DP40 V_DDSP_B_DP_2_DN40 V_DDSP_B_DP_3_DP40 V_DDSP_B_DP_3_DN40 V_DDSP_C_DP_0_DP41 V_DDSP_C_DP_0_DN41 V_DDSP_C_DP_1_DP41 V_DDSP_C_DP_1_DN41 V_DDSP_C_DP_2_DP41 V_DDSP_C_DP_2_DN41 V_DDSP_C_DP_3_DP41 V_DDSP_C_DP_3_DN41

TPS62TPS62 TPS64TPS64

TPS66TPS66 TPS68TPS68

TPS69TPS69

4

S_DDPD_HPD_PD

TP_DDPD_AUXP TP_DDPD_AUXN

TP_SDVO_INTN TP_SDVO_STALLP

TP_SDVO_STALLN TP_SDVO_TVCLKINP

TP_SDVO_TVCLKINN

M11 M12

U14 U12

R14 R12

E11 B11

W3

T1 N2

M1

R8 R9

N6 R6

H8 K8 L5

M3

L2

G2 G4

F3 F5 E4 E2 D5 B5 C6 D7 B7 C9

U2 T3

U5 U8

U9

J3

US1F

BD82Q67

DDPB_HPD DDPC_HPD DDPD_HPD

DDPB_AUXP DDPB_AUXN DDPC_AUXP DDPC_AUXN DDPD_AUXP DDPD_AUXN

DDPB_0P DDPB_0N DDPB_1P DDPB_1N DDPB_2P DDPB_2N DDPB_3P DDPB_3N DDPC_0P DDPC_0N DDPC_1P DDPC_1N DDPC_2P DDPC_2N DDPC_3P DDPC_3N DDPD_0P DDPD_0N DDPD_1P DDPD_1N DDPD_2P DDPD_2N DDPD_3P DDPD_3N

SDVO_INTP SDVO_INTN

SDVO_STALLP SDVO_STALLN

SDVO_TVCLKINP SDVO_TVCLKINN

CRT_HSYNC CRT_VSYNC

CRT_GREEN

CRT_DDC_DATA

CRT_DDC_CLK

DISPLAY

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPD_CTRLCLK

DDPD_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

6/12

3

CRT_RED

CRT_BLUE

CRT_IRTN

DAC_IREF

AR4 AR2

AN6 AN2 AM1

AM6

AW1 AW3

AT3

AL12 AL14

AL9 AL8

AL15 AL17

V_HSYNC V_VSYNC

V_DACREFSET

RS130 1KOhm

+/-0.5%

V_DDPC_CTRL_CLK 41 V_DDPC_CTRL_DATA 41

V_DDPB_CTRL_CLK 40 V_DDPB_CTRL_DATA 40

V_RED 42 V_GREEN 42 V_BLUE 42

V_DDCA_DATA 42 V_DDCA_CLK 42

2

1

V_RED V_GREEN V_BLUE

RS135

*

RS134

RS134 150

150

+/ -1%

*

RS135 150

150

+/ -1%

4

RS133

A A

5

*

RS133 150

150

+/ -1%

V_HSYNC V_VSYNC

RS131 33

*

RS132 33

*

3

*

RS136

RS136 0

0

Dummy

*

RS137

RS137 0

0

Dummy

V_HSYNC_3V 42 V_VSYNC_3V 42

Intel

Title

PCH-6: Display

DWG NO Rev

Lanikai _MT/DT

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Lanikai _MT/DT

1

26 71Wednesday, June 13, 2012

A00

of

5

D D

20100106: Remove RS96; CRB 0.7 20100106: Swap C_PCH_PCI0_R and C_PCI_SL1_R; CRB 0.7 20100106: Disconnect AT11 and left Test point; CRB 0.7

RC103 22

C_LPC53 C_TPM46

C_PCI_SB21 C_LPC_SIO32 C_PCI_SL158

TPS129TPS129

C_14M_SIO32

TPS130TPS130

20100108: Change Power Source

C C

B B

C_14M_TPM46

+1P05V_PCH

20091216 PCIECLKRQ1#/GPIO18 is mobile chip only, RC110, RC111 and signal net "S_PCIECLKREQ#1" removed.

20100106: GPO_WLOM move to GPIO14

RC103 22 RC97 22

RC97 22 RC98 22

RC98 22 RC99 22

RC99 22 RC100 22

RC100 22

20100107: Swap CLKOUTFLEX CLK out; PDG 0.8

RC101 22

RC101 22 RC102 22

RC102 22

RC104 91 Ohm

C_14M_MCH

RC107

1M

*

XC2

+/-1%

1 2

XTAL 25MHz

CC36

*

27pF

50V, NPO, +/-5%

*

C_LPC_R

*

C_TPM_R

*

C_PCI_PCH_R

*

C_LPC_SIO_R

*

C_PCI_SL1_R

*

S_TP_CLKOUTFLEX0 C_14M_SIO_R

*

S_TP_CLKOUTFLEX2 C_14M_TPM_R

*

50V, NPO, +/-5%

+/-1%

XCLK_RCOMP

C_XTAL_25M_OUT C_XTAL_25M_IN

*

DON'T CHANGE TO 0402

CC37

27pF

+3V

RC108 10K

+3V_S5

4

AT11 AN14 AT12 AT17 AT14

AT9 BA5

AW5

BA2

AL2

AN8

AJ5 AJ3

*

RC116 10K

*

RC118 10K

*

US1H

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

XCLK_RCOMP REFCLK14IN

XTAL25_OUT XTAL25_IN

BD82Q67

S_FLEXBAY_HDR_CBL_DET# 24,61

S_INTRUD_CBL_DET# 24,31 O_COM_SER2_DET# 24

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

CLKOUT_PCIE7N CLKOUT_PCIE7P

CLKOUT_DP_N / CLKOUT_BCLK1_N

CLKOUT_DP_P / CLKOUT_BCLK1_P

CLKOUT_PCIE0N CLKOUT_PCIE0P

CLKOUT_PCIE1N CLKOUT_PCIE1P

CLOCK

8/12

CLKOUT_PCIE2N CLKOUT_PCIE2P

CLKOUT_PCIE3N CLKOUT_PCIE3P

CLKOUT_PCIE4N CLKOUT_PCIE4P

CLKOUT_PCIE5N CLKOUT_PCIE5P

CLKOUT_PCIE6N CLKOUT_PCIE6P

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

S_FLEXBAY_HDR_CBL_DET#

S_INTRUD_CBL_DET# O_COM_SER2_DET#

3

CLKIN_GND0_N CLKIN_GND0_P

CLKOUT_DMI_N

CLKOUT_DMI_P CLKIN_GND1_N

CLKIN_GND1_P

W53 V52

R52 N52

AE2 AF1

P31

C_PE_100M_MCP#_R

R31

C_PE_100M_MCP_R

R27 P27

N56

S_TP_CK_DP_PCH_DN

M55

S_TP_CK_DP_PCH_DP

AE6 AC6

S_TP_CK_SRC0_PCH_DP

AA5 W5

AB12 AB14

AB9

S_TP_CK_SRC3_PCH_DN

AB8

S_TP_CK_SRC3_PCH_DP

Y9

S_TP_CK_SRC4_PCH_DN

Y8

S_TP_CK_SRC4_PCH_DP

AF3

C_PCIEX1#_2_R

AG2

C_PCIEX1_2_R

AB3 AA2

C_PCIEX1_1

AG8

C_PCIEX16#_1_R

AG9

C_PCIEX16_1_R

AE12

C_PCIEX4#_1_R

AE11

C_PCIEX4_1_R

RC109 10K Dummy

RC117 10K Dummy

RC117 10K Dummy RC119 10K Dummy

RC119 10K Dummy

RS212 0

RS212 0 RS211 0

RS211 0

RS205 0

RS205 0 RS204 0

RS204 0 RS210 0

RS210 0 RS209 0

RS209 0

*

* *

*

C_PCH_CSI# C_PCH_CSI

RS202 0

*

RS203 0

*

C_DMI2_PCH# C_DMI2_PCH

TPS126TPS126 TPS125TPS125

TPS72TPS72 TPS73TPS73

TPS74TPS74 TPS75TPS75

*

TPS77TPS77

*

* *

*

C_PCH_ITP# 52 C_PCH_ITP 52

C_PE_100M_MCP# 9 C_PE_100M_MCP 9

TPS124TPS124

C_SRC1_PCH# 52 C_SRC1_PCH 52

C_PCIE_L1# 34 C_PCIE_L1 34

C_PCIEX1#_2 59 C_PCIEX1_2 59

C_PCIEX16#_1 38 C_PCIEX16_1 38

C_PCIEX4#_1 39 C_PCIEX4_1 39

2

CC14

CC13

CC12

10pF

Dummy

50V, NPO, +/-5%

CC13

*

10pF

Dummy

50V, NPO, +/-5%

10pF

Dummy

CC10

*

10pF

Dummy

50V, NPO, +/-5%

*

1

C_TPM C_14M_TPM C_14M_SIO C_LPC_SIO C_PCI_SB

CC15

10pF

Dummy

50V, NPO, +/-5%

RC129 10K

*

A A

Pull-down for Integrated clock gen-11/25/09 20100105: Dummy all pull-down resistors since

use buffer thru mode 20100106: Reserved RC123,RC124; CRB 0.7

20100107: RC121,RC122 mount; PDG 0.8

5

C_96M_PCH#22

C_96M_PCH22

C_DMI_PCH#22

C_DMI_PCH22

C_SATA_PCH#23

C_SATA_PCH23

4

*

RC130 10K

*

RC131 10K

*

RC132 10K

*

RC133 10K

*

RC134 10K

*

C_14M_MCH C_PCH_CSI# C_PCH_CSI C_DMI2_PCH# C_DMI2_PCH

3

RC120 10K

*

RC121 10K

*

RC122 10K

*

RC123 10K

*

RC124 10K

*

Title

PCH-8: Clock

DWG NO Rev

Date: Sheet of

2

Date: Sheet

PCH-8: Clock

Lanikai _MT/DT

1

A00

of

27 71Wednesday, June 13, 2012

5

+1P05V_PCH

16V, X5R, +/-10%

CS12

1uF

*

Dummy

D D

Dummy

*

CS13

1uF

Dummy

16V, X5R, +/-10%

*

PLACE SOLDER SIDE

+1P05V_PCH

CS79

*

1uF

16V, X5R, +/-10%

Close to AL40

C C

+1P05V_PCH

LS2 10uH

*

LS3 1uH

*

B B

+1P05V_PCH

*

Dummy

RS140

*

LS4 1uH

*

Dummy

+1P05V_PCH +V_1.05_PCH_LR_10

LS1

*

10uH

*

VCCSATAPLL_L_10

CS22

10uF

*

Dummy

10V, X5R, +/-10%

CS25

*

1uF 6.3V,X5R,+/-10%

Dummy

VCCFDIPLL_R_10

VCCAPLLDMI2_LR_10

CS26

*

10uF

Dummy

*

RS139

Dummy

CS27

1uF

Dummy

6.3V,X5R,+/-10%

0

Dummy

VCCAPLLEXP_L_10

RS141

*

CS24

*

10uF

10V, X5R, +/-10%

Dummy

0

Dummy

10V, X5R, +/-10%

*

10V, X5R, +/-10%

Dummy

CS31

1uF

16V, X5R, +/-10%

*

4

16V, X5R, +/-10%

CS14

1uF

Dummy

CS19

*

10uF

+1P05V_VCCIO

*

+V_1.05_PCH_LR_10

CS23

1uF

16V, X5R, +/-10%

Dummy

0

*

CS20

1uF

6.3V,X5R,+/-10%

CS21

1uF

16V, X5R, +/-10%

+1P05V_PCH

VCCAPLLEXP_LR_10

AV24 AV26 AY25 AY27 AC20 AE20 AG41

AL40 AN40 AN41

AJ38

AE15 AE17 AG15 AE40 BA38 AG38 AG40 AA34 AA36

B41

AJ20

U56

B53 C54 A19 AL5

Y36 V36 Y28

F20 F30 V25 V27 V31 V33

E41

Y24 Y26 Y30 Y32 Y34 V22 Y20 Y22

US1I

VCCIO_1 VCCIO_2 VCCIO_3 VCCIO_4 VCCSC_1 VCCSC_2 VCCIO_7 VCCIO_8 VCCIO_9 VCCIO_10 VCCIO_11 VCCIO_12 VCCIO_13 VCCIO_14 VCCDIFFCLKN_1 VCCDIFFCLKN_2 VCCDIFFCLKN_3 VCCIO_18 VCCIO_19 VCCIO_20 VCCIO_21 VCCIO_22 VCCIO_23 VCCIO_24 VCCIO_25 VCCIO_26 VCCIO_27 VCCIO_28 VCCIO_29

VCCDMI_01 VCCDMI_02

VCCIO_30 VCCIO_31 VCCIO_32 VCCIO_33 VCCIO_34 VCCIO_35 VCCIO_36 VCCIO_37 VCCCLKDMI

VCCAPLLSATA

VCCAPLLEXP VCCFDIPLL VCCAPLLDMI2 VCCACLK

BD82Q67

POWER

9/12

3

VCCCORE_1 VCCCORE_2 VCCCORE_3 VCCCORE_4 VCCCORE_5 VCCCORE_6 VCCCORE_7 VCCCORE_8

VCCCORE_9 VCCCORE_10 VCCCORE_11 VCCCORE_12 VCCCORE_13 VCCCORE_14 VCCCORE_15 VCCCORE_16 VCCCORE_17 VCCCORE_18 VCCCORE_19 VCCCORE_20 VCCCORE_21 VCCCORE_22

TP15 TP16 TP17 TP18 TP19 TP20 TP21 TP22 TP23 TP24 TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36

VSS_NCTF_14

TP1 TP2 TP3 TP4 TP5 TP6 TP7

TP9 VSS_296 VSS_295 VSS_293 VSS_292 VSS_291

TP10 TP11

VSS_294

AC24 AC26 AC28 AC30 AC32 AE24 AE28 AE30 AE32 AE34 AE36 AG32 AG34 AJ32 AJ34 AJ36 AL32 AL34 AN32 AN34 AR32 AR34

AE43 AE50 BA36 AY36 Y14 Y12 H31 J27 J25 L22 J31 L27 L25 J22 C29 F28 C26 B25 E29 E27 B27 D25 BP1

P22 L31 L33 M38 L36 Y18 Y17 AB17 P25 R25 R36 AL44 AL43 BM46 BA27 P36

+1P05V_PCH+1P05V_PCH

CS11

CS15

*

CS15

*

1uF

16V, X5R, +/-10%

20110211 USB 3.0 Ball for PPT

USB3_RX1_PCH_DN 57 USB3_RX2_PCH_DN 57 USB3_RX3_PCH_DN 45 USB3_RX4_PCH_DN 45 USB3_RX1_PCH_DP 57 USB3_RX2_PCH_DP 57 USB3_RX3_PCH_DP 45

USB3_RX4_PCH_DP 45 USB3_TX1_PCH_DN 57 USB3_TX2_PCH_DN 57 USB3_TX3_PCH_DN 45 USB3_TX4_PCH_DN 45 USB3_TX1_PCH_DP 57 USB3_TX2_PCH_DP 57 USB3_TX3_PCH_DP 45 USB3_TX4_PCH_DP 45

CS16

*

10uF

10V, X5R, +/-10%

CS17

*

10uF

10V, X5R, +/-10%

2

1

USB 3.0 Ball for PPT

A A

RS142

0

*

Dummy

5

VCCACLK_R_10

Intel

Title

PCH-9: Power 1

DWG NO Rev

Date: Sheet of

4

3

2

Date: Sheet

PCH-9: Power 1

Lanikai _MT/DT

1

A00

of

28 71Wednesday, June 13, 2012

5

4

3

2

1

Coherent with GPIO28

US1J

+REF5V

BF1

BT25 AV28

AF57

BC17

AU32 AV36

AU34 AG24 AG26 AG28

AJ24 AJ26 AJ28 AL24

AL28 AN22 AN24 AN26 AN28 AR24 AR26 AR28 AR30 AR36 AR38 AU30 AU36

AV40

AT1

AB1

AC2

BD82Q67

CS81

*

22uF

6.3V,X5R,+/-20%

V5REF

V5REF_SUS VCCSUSHDA

VCC3P3_1 VCC3P3_2

VCCASW_1 VCCASW_2 VCCASW_3 VCCASW_4 VCCASW_5 VCCASW_6 VCCASW_7 VCCASW_8 VCCASW_9 VCCASW_10 VCCASW_11 VCCASW_12 VCCASW_13 VCCASW_14 VCCASW_15 VCCASW_16 VCCASW_17 VCCASW_18 VCCASW_19 VCCASW_20 VCCASW_21 VCCASW_22 VCCASW_23

VCCDSW3_3

VCCADAC

VCCADPLLA

VCCADPLLB

CS82

*

22uF

6.3V,X5R,+/-20%

Dummy

CS84

CS83

*

22uF

6.3V,X5R,+/-20%

Dummy

4

POWER

10/12

S_VCCADAC_LR_10

6.3V,X5R,+/-20%

+REF5V_SUS

CS37

0.1uF

16V, X7R, +/-10%

Close to BC17

Near AJ24,AN22

CS77

*

1uF

6.3V,X5R,+/-10%

L<100 MILS

CS55

*

0.1uF

16V, X7R, +/-10%

S_VCCADPLLA_LR_10

ECS1

220uF

*

16V, +/-20%

S_VCCADPLLB_LR_10

ECS2

220uF

*

16V, +/-20%

+3V_S5

*

CS76

1uF

6.3V,X5R,+/-10%

*

CS34

0.1uF

16V, X7R, +/-10%

+3V

CS38

*

0.1uF

16V, X7R, +/-10%

+1P05V_ME

+3V_DUAL

CS64

1uF

16V, X5R, +/-10%

CS66

1uF

16V, X5R, +/-10%

*

D D

+3V

CS46

*

0.1uF

16V, X7R, +/-10%

Close to AF57

20100104- Change to

0.1uF; follow CRB 0.8

Dummy for Cost down-11/23

Delet LS5,RS151,CS46,CS47; follow CRB 0.7-11/30

C C

20100104- Add CS78,CS80 and CS76,CS77 change to 0403; follow CRB 0.8

+1P05V_ME

CS78

CS80

CS71

*

1uF

Dummy

16V, X5R, +/-10%

+3V

FBS1

*

FB 600 Ohm

20100106:- FBS1 change to FB: PDG 0.8

B B

+1P05V_PCH

LS6

*

10uH

LS7

*

10uH

A A

*

10uF

6.3V, X5R, +/-20%

RS1521RS152

CS53

*

2.2uF

6.3V, Y5V, +80%/-20%

+3V_DUAL

*

1uF

6.3V,X5R,+/-10%

1

CS54

*

10uF

10V, X5R, +/-10%

CS70

0.1uF

16V, X7R, +/-10%

Close to AV40

RS156

Dummy

5

*

S_VCCADAC_LR_10

0

VCCVRM_1 VCCVRM_4 VCCVRM_3 VCCVRM_2

VCCPNAND_1 VCCPNAND_2

VCC3P3_3 VCC3P3_4

VCC3P3_5 VCC3P3_6 VCC3P3_7 VCC3P3_8 VCC3P3_9

VCC3P3_10

VCCSUS3P3_1 VCCSUS3P3_2

VCCSUS3P3_3 VCCSUS3P3_4 VCCSUS3P3_5 VCCSUS3P3_6 VCCSUS3P3_7 VCCSUS3P3_8

VCCSUS3P3_9 VCCSUS3P3_10 VCCSUS3P3_11

V_PROC_IO_1

V_PROC_IO_NCTF_1

VCCSPI

VCCRTC

DCPRTC_NCTF

DCPRTC DCPSUS_1 DCPSUS_2 DCPSUS_3

DCPSUSBYP

DCPSST

Delet RS144,RS146,RS149 and 1.05V power source; follow CRB 0.7-11/30

AJ1 R2 R54 R56

+1P8V_SFR

T55 T57

BD17 BD20

AL38 AN38 AU22 A12 AU20

AV20

U31 AV30

AV32 AY31 AY33 BJ36 BK36 BM36 AT40 AU38 BT35

D55 B56

AN52 BU42 BT56 BR54 AA32 AT41 A39 AV41 BA46

CS32 0.1uF

16V, X7R, +/-10%

*

+3V

CS35 0.1uF

16V, X7R, +/-10%

*

Dummy

CS36 0.1uF

16V, X7R, +/-10%

*

CS40 0.1uF

16V, X7R, +/-10%

*

CS44 0.1uF

16V, X7R, +/-10%

*

Dummy

CS45 0.1uF

16V, X7R, +/-10%

*

Dummy

Near AV30

+3V_S5

CS51

*

0.1uF

25V, X7R, +/-10%

CS52 0.1uF

Near BT35

+1P05V_VCCIO

CS58 4.7uF

CS58 4.7uF CS59 0.1uF

CS59 0.1uF CS60 0.1uF

CS60 0.1uF

Near D55

+3V_EPW

TPS117TPS117 TPS118TPS118

TPS119TPS119

+3V_EPW

CS29

*

1uF

6.3V,X5R,+/-10%

Near AN52

20100104: CS29 change to 1uF; follow PDG 0.8

3

16V, X7R, +/-10%

*

6.3V, X5R, +/-10%

*

16V, X7R, +/-10%

*

16V, X7R, +/-10%

*

+VCCRTC

CS62 0.1uF 16V, X7R, +/-10%

CS63 0.1uF 16V, X7R, +/-10%

CS63 0.1uF 16V, X7R, +/-10% CS65 0.1uF 16V, X7R, +/-10%

CS65 0.1uF 16V, X7R, +/-10%

+1P8V_SFR +1P8V_SFR

+1P8V_SFR

Near T55

20100106- Dummy CS35,CS44,CS45; follow CRB 0.8

Near AL38

Near A12

20100104- CS73,CS75 change to 1uF; follow CRB 0.8

20100104- CS56 change to

2.2uF; follow CRB 0.8

CS51 NEAR U31

CS56

*

Dummy

CS56 NEAR AV30,AT40

2.2uF

6.3V, Y5V, +80%/-20%

*

+3V

Near AU20

CS73

*

1uF

16V, X5R, +/-10%

Dummy

20100104- Remove CS74 follow CRB

0.8

+3V

*

Near BR54

Change to 1uF; follow CRB 0.7-12/03 20100104: Change to 0.1uF; follow PDG 0.8

+5V

CS75

1uF

16V, X5R, +/-10%

Dummy

2

+3V

DS1

*

RS150

RS150 10

10

+VCCRTC

+1P8V_SFR

*

DS1 SD103AW

SD103AW

C A

CS33

*

1uF

16V, X5R, +/-10%

CS41

CS42

*

CS48

1uF

16V, X5R, +/-10%

Dummy

CS42

*

1uF

6.3V,X5R,+/-10%

0.1uF

16V, X7R, +/-10%

20100104- Remove CS49,CS50 follow CRB 0.8

VBAT

+VCCRTC_SIO

+3V_DUAL

QS4

BAT54C

3

Battery

1 2

*

BATTERY_1

LITHIUM BATT

*

- +

Title

DWG NO Rev

Date: Sheet

Date: Sheet of

+REF5V

QS5

QS5 BAT54C

BAT54C

1 2

RS154

RS154 1K

1K

BATTERY

BATTERY Battery Holder

Battery Holder

+5V_S5

+3V_S5

DS2

*

RS147

RS147 10

10

Near BU42

3

*

Lanikai _MT/DT

DS2 SD103AW

SD103AW

Dummy

C A

CS39

*

0.1uF

16V, X7R, +/-10%

+VCCRTC

CS57

RS153

1uF

16V, X5R, +/-10%

*

20K

S_RTCRST#

CS61

*

1uF

10V, X5R, +/-10%

PCH-10: Power 2

+REF5V_SUS

S_RTCRST# 24,31,53

1

A00

of

29 71Wednesday, June 13, 2012

5

D D

4

3

2

1

2011_1115 By Dell request remove US1_1 PCH heatsink detect for RTCSRST net spacing

BC31

BC14

BC27

BB6

BC20

BC15

BB52

VSS_128

VSS_124

VSS_127

VSS_123

VSS_126

VSS_125

VSS_122

C C

VSS_7

VSS_6

VSS_5

VSS_4

VSS_3

VSS_2

VSS_1

A42

A29

A26

C12

AY22

AE56

BR36

B B

BF12

BD33

BD25

BC38

BC36

BC47

BC9

VSS_134

VSS_133

VSS_130

VSS_129

VSS_131

VSS_132

VSS_13

VSS_12

VSS_11

VSS_10

VSS_9

VSS_8

A9

A49

AA28

AA26

AA24

AA22

AA20

BF20

VSS_135

VSS_14

AA30

BF25

VSS_136

VSS_15

AA38

BF33

VSS_137

VSS_16

AB11

BF41

VSS_138

VSS_17

AB15

BF43

VSS_139

VSS_18

AB40

BF46

VSS_140

VSS_19

AB41

BF52

VSS_141

VSS_20

AB43

BF6

VSS_142

VSS_21

AB47

BG22

VSS_143

VSS_22

AB52

BG25

VSS_144

VSS_23

AB57

BG27

VSS_145

VSS_24

AB6

BG31

VSS_146

VSS_25

AC22

VSS_147

VSS_26

BK41

BK20

BJ15

BJ1

BH6

BH52

BG33

BG36

BG38

VSS_156

VSS_155

VSS_154

VSS_153

VSS_152

VSS_151

VSS_148

VSS_149

VSS_150

VSS_33

VSS_29

VSS_28

VSS_32

VSS_27

VSS_31

VSS_35

VSS_30

VSS_34

AC4

AE18

AE14

AE26

AE22

AC38

AC36

AC34

AC54

BM23

BK6

BM22

BK52

BM10

VSS_158

VSS_157

VSS_37

VSS_36

AE4

AE47

AE38

BM12

VSS_159

VSS_38

AE8

BM16

VSS_160

VSS_39

AE9

VSS_161

VSS_40

AF52

VSS_162

VSS_41

AF6

VSS_163

VSS_42

BM28

BM26

BM32

BM48

BM42

BM40

VSS_165

VSS_164

VSS_166

VSS_168

VSS_167

VSS_46

VSS_44

VSS_43

VSS_45

VSS_47

AG36

AG22

AG14

AG11

AG20

AG30

BM5

VSS_169

VSS_48

AG43

BN31

VSS_170

VSS_49

AG44

BN47

VSS_171

VSS_50

AG46

VSS_172

VSS_51

BP33

BP3

BN6

BR52

BR22

BP35

VSS_175

VSS_174

VSS_173

VSS_178

VSS_177

VSS_176

GND

VSS_57

VSS_55

VSS_54

VSS_53

VSS_52

VSS_56

AH6

AG5

AJ22

AH52

AG53

AG50

C32

BU29

BU26

BU36

BU19

VSS_181

VSS_180

VSS_179

VSS_59

VSS_58

VSS_60

AK6

AJ57

AJ30

AK52

BU39

VSS_182

VSS_61

AL11

C19

VSS_183

VSS_62

AL18

VSS_184

VSS_63

AL20

C39

VSS_185

VSS_64

AL22

C4

VSS_186

VSS_65

AL26

D15

VSS_187

VSS_66

AL30

VSS_188

VSS_67

D23

AL36

D3

VSS_189

VSS_68

AL41

D35

VSS_190

VSS_69

AL46

D43

VSS_191

VSS_70

AL47

D45

VSS_192

VSS_71

AM3

E19

VSS_193

VSS_72

AM52

E39

VSS_194

VSS_73

AM57

VSS_195

VSS_74

F22

F16

F12

F10

E9

E6

VSS_200

VSS_199

VSS_198

VSS_197

VSS_196

VSS_75

VSS_79

VSS_78

VSS_77

VSS_76

AN11

AN20

AN18

AN17

AN15

AN12

VSS_201

VSS_80

F40

F32

F36

F26

F33

VSS_203

VSS_202

VSS_204

VSS_82

VSS_81

VSS_83

AN4

AN36

AN30

F35

AN43

VSS_205

VSS_84

F50

F48

F46

F42

VSS_207

VSS_206

VSS_210

VSS_209

VSS_208

VSS_89

VSS_88

VSS_85

VSS_86

VSS_87

AN9

AR22

AR20

AR52

AN47

AN54

E54

VSS_211

VSS_90

AR6

F8

VSS_212

VSS_91

AT15

G54

VSS_213

VSS_92

AT18

H15

VSS_214

VSS_93

AT43

H20

VSS_215

VSS_94

AT47

H22

VSS_216

VSS_95

AT52

H25

VSS_217

VSS_96

AT6

VSS_218

VSS_97

H27

AT8

H33

VSS_219

VSS_98

AU24

H6

VSS_220

VSS_99

AU26

VSS_221

VSS_100

J5

J48

K52

J46

J33

J1

J53

L17

L12

K9

K6

L38

VSS_226

VSS_225

VSS_228

VSS_224

VSS_223

VSS_222

VSS_227

VSS_232

VSS_231

VSS_230

VSS_229

VSS_111

VSS_110

VSS_109

VSS_104

VSS_108

VSS_107

VSS_103

VSS_106

VSS_105

VSS_102

VSS_101

AY6

AU5

AV12

AU28

AV6

AV18

AV22

AY38

AV47

AV38

AV34

AW57

VSS_233

VSS_112

M27

M25

M22

M20

L43

L41

VSS_236

VSS_235

VSS_234

VSS_113

VSS_115

VSS_114

B23

BA12

BA31

BA11

VSS_237

VSS_116

BA41

VSS_238

VSS_117

M46

M33

M31

M57

M52

M36

VSS_239

VSS_241

VSS_240

VSS_242

VSS_119

VSS_118

VSS_121

VSS_120

BB3

BB1

BA49

BA44

VSS_243

VSS_244

VSS_245

US1K

US1K BD82Q67

BD82Q67

11/12

Pin Y6 connect to GND-11/27

U15

U17

U20

U22

U25

U27

U33

U36

U38

R46

U53

V20

V38

W55

W57

Y11

Y15

Y38

Y40

R49

Y43

Y46

Y47

Y49

Y52

Y6

US1L

US1L BD82Q67

BD82Q67

VSS_263

VSS_264

VSS_265

VSS_266

VSS_267

VSS_268

VSS_269

VSS_270

VSS_271

VSS_272

VSS_273

VSS_274

VSS_275

VSS_276V6VSS_277W1VSS_278

VSS_279

VSS_280

VSS_281

VSS_282

VSS_283

VSS_284

VSS_285

VSS_286

VSS_287

VSS_288

VSS_289

VSS_290

GND

12/12

VSS_249

VSS_246M6VSS_247M8VSS_248M9VSS_250

VSS_251

VSS_252

VSS_253

VSS_254

N4

N54

R11

R15

R17

A A

R22

5

VSS_NCTF_1A4VSS_NCTF_4

VSS_NCTF_3

VSS_255R4VSS_256

VSS_NCTF_2

VSS_257

B2

A6

R41

R43

20091209: CRB0.7 pin A4,BM57 are test points

BM1

VSS_NCTF_9

VSS_NCTF_7

VSS_NCTF_5

BM57

VSS_NCTF_11

VSS_NCTF_10

VSS_NCTF_6

VSS_NCTF_8

VSS_NCTF_13

VSS_NCTF_12

VSSADAC

F1

D1

BT2

BU6

BU4

BP57

BU52

BU54

AU2

VSS_258

VSS_262

VSS_259

VSS_260

VSS_261

T6

T52

U41

U11

U47

Title

PCH-11: GND

DWG NO Rev

Date: Sheet

Date: Sheet of

4

3

2

Date: Sheet of

PCH-11: GND

Lanikai _MT/DT

1

A00

of

30 71Wednesday, June 13, 2012

5

4

3

2

1

Clear Password

+3V_DUAL

1-2: NORMAL EMPTY: CLEAR PASSWORD

D D

PSWD_JUMPER(1-2)

Jumper_2P_Blu

S_PSWD_CLR24

*

RS159

8.2K

+/-5%

PSWD

1 2

Header_1X2

CLR_CMOS

S_RTCRST#24,29,53

*

2 1

4.7K

4.7K RS166

RS166

Header_1X2

RTCRST

Jumper Dummy

Type Default

Pop CLR_CMOS

Chassis Intruder

+VCCRTC

*

RS158

RS158 1M

1M

S_INTRUD_CBL_DET#24,27

S_INTRUDER#24

CS67

*

0.1uF

16V, X7R, +/-10%

Dummy

RS160 10K

*

Header_1X3

3

2

1

INTRUDER

SERVICE_MODE

BEEP

+3V_S5 +3V_S5

C C

RS162 10K

S_MFG_MODE_OR24

A_Z_SDOUT24,36

RS162 10K

*

RS206

*

1K

+/-5%

EC

QS6

B

MMBT3906

RS161

*

1K

+/-5%

SERVICE_MODE

1 2

Header_1X2

+5VSB

BEEP

RNS1

*

1

2

3

4

5

6

7 8

100 Ohm

RS164 1K +/-1%

*

S_SPKR_OUT24 O_SPEAKER32,33

*

RS165 1K +/-1%

*

B

QS7

QS7 MMBT3904-7-F

MMBT3904-7-F

E C

CS68

*

1uF

25V, X5R, +/-10%

BEEP

+

BUZZER

-

Buzzer

B B

S_GPI_SKU223 S_GPI_SKU124 S_GPI_SKU024

A A

SKU0SKU1 0 TPM 0

11

SKU ID BOARD ID

+3V

RS95

RS96

*

10K

@Z

*

RS100

RS100 220

220

+/-5%

@S,J,N

0 1 01

5

*

10K

RS98

RS98 220

220

+/-5%

@N

@S,Z,J

RS97

RS97 10K

10K

Dummy

*

RS99

RS99 220

220

+/-5%

SKU ID

Type

TCM non TPM/TCM Reserved

check : need to update table

ID0 TypeID1ID2

1

0

11

4

Chassis ID

SFF

10

0

Comoros

00

MT/DT

USFF

S_GPI_BRD_REV223

+3V

*

RS44

RS44 10K

10K

Dummy

S_GPI_CHASSIS_ID023 S_GPI_CHASSIS_ID123 S_GPI_CHASSIS_ID223

Dummy

*

RS49

1K

3

*

RS45

RS46

10K

Dummy

*

RS50

1K

RS51

RS51 10K

10K

Rev2

0 0 0 0 1 1 1 1

0

Default

10

Reserved 1 1

0 1 1

0 1 00 1 0 1

2

Reserved

Title

DWG NO Rev

Date: Sheet

Date: Sheet of

Rev0 Type

Rev1

S_GPI_BRD_REV124 S_GPI_BRD_REV023

20100106: change to 1k since have internal pull-up 10k

PCH MISC Conn/BUZ/ID

+3V

*

RS106

10K

Dummy

RS111

*

220

+/-5%

Lanikai _MT/DT

1

RS40

RS40 10K

10K

Dummy

RS42

1K

31 71Wednesday, June 13, 2012

+3V+3V_S5

RS41

*

10K

Dummy

*

RS43

RS43 10K

10K

A00

of

5

Delet RO2; SMSC suggestion-12/08/09

D D

H_PECI_R

S_SLP_S3#

78 76

75 74 73 72 71 70 68 67 66 65 64 63 62

9 10 11 12 13 14 15 16 17 18

1 77

27 28 29 30

4

5

7

8 36

21 25 26 52 53 54 55 56 58 59 60

123 124 125 126 127 128

33 32 31

Place Near SIO pin.123

CO16

*

1nF

50V, X7R, +/-10%

Dummy

T_ESATA_DET#

S_SMBDATA_PCI S_SMBCLK_PCI

C C

S_SMLINK1_DATA24

S_SMLINK1_CLK24

O_INDEX#33

O_TRK0#33

O_WPT#33

O_RDATA#33

O_DSKCHG#33

C_14M_SIO27

F_LAD024,46,53 F_LAD124,46,53 F_LAD224,46,53 F_LAD324,46,53

F_FRAME#24,46,53

F_LDRQ#24

S_PLTRST#9,24,34,46,52,53

C_LPC_SIO27 F_SERIRQ#23,46

O_IO_PME#24

SPI_DI

Delet RO33,RO34; SMSC suggestion-12/08/09

O_PWRBTN#IN24,52,53,56

S_SUSCLK24

O_YELLOW#56

O_GREEN#56

O_FP_CBL_DET#56

H_RESET#9

O_PSON#63

B B

A A

O_AUD_PCSPKR_DET#37

Net change to H_RESET#-12/28/09

+1P05V_VCCIO

CO12

0.1uF

16V, X7R, +/-10%

+12V_CPU

CO15

0.1uF

Dummy

16V, X7R, +/-10%

X_PLTRST_PCIE_SLOT#_R

PWRGD_3V24,52

O_RSMRST#24

S_SLP_S3#24,53,64,66,70,71 S_SLP_S4#24,53,65,71

B_ATX_PWROK63,71

O_SPEAKER31,33

S_SLP_M#24,53,65,66

O_GP73_PU33

H_PECI9,23

TRST#

RO35 33+/-5%

*

Reserved RO35; SMSC suggestion-12/08/09

TRST#

RO39

*

1K

+/-5%

5

4

close to Pin 6

UO1

GP42 / DRVDEN0 INDEX#

MTR0# GP40 / SMBDAT1 DS0# GP36 / SMBCLK1 DIR# STEP# WDATA# WGATE# TRK0# WRTPRT# RDATA# HDSEL# DSKCHG#

CLOCKI LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ# LRESET# SPI_DO / GP04 PCICLK SER_IRQ GP41 / IO_PME#

SMBDAT2 / GP10 SMBCLK2 / GP11 SPI_DI / GP12 SPI_CK / GP13

GP00 GP01 GP02 GP03 PWRBTN# / GP15

CLK32 YELLOW# / GP06 GREEN# / GP07 GP25 / BC_DAT PCI_RST_SYS# / GP26 PCI_RST_SLOTS# / GP27 PS_ON# / GP30 GP31 / BC_INT# SPI_CS# / GP32 PWR_GOOD_3V / GP33 RSMRST# SLP_S3# SLP_S4_S5# / GP66 PWRGD_PS TRST# SPEAKER/GP70 GP71 / IO_SMI#

PECI_READY/ LVSMB_DAT1 PECI / LVSMB_CLK1 PECI VREF

O_BC_CLK

X_PLTRST_PCIE_SLOT#_R

4

+3V

CO9

0.1uF

16V, X7R, +/-10%

6

VCC

SCH5545-NS

LPCFloppy Miscellaneous

SMB

SPI PECI

CAP1

GP35/BC_CLK

2

69

CO13

*

4.7uF

6.3V, X5R, +/-10%

122

VSS_13VSS_219VSS_337VSS_4

+VCCRTC_SIO

+3V_DUAL

106

VTR_6

61

23

VBAT

VTR_124VTR_234VTR_357VTR_479VTR_5

Parallel PortSerial Port 1KB / MSHW Monitor

Serial Port 2

PROCHOT_IN# /PROCHOT_OUT#

AVSS

HVSS

VSS_5

VSS_6

20

42

92

119

1

OE#

2

A

RO40 0 +/-5%

3

+3V_DUAL

close to Pin 47

0.1uF

0.1uF CO11

CO11

16V, X7R, +/-10%

47

HVTR

DTR1# [TEST_EN] /GP51

GP05 / PECI_REQUEST#

REMOTE2a+/REMOTE2bREMOTE2a-/REMOTE2b+

+3V_DUAL

5

VCC

GND

74LVC1G125GW

3

*

SLCT

BUSY ACK#

PD7 PD6 PD5

PD4 PD3 / TMS PD2 / TDO

PD1 / TDI

PD0 / TCK

SLCTIN#

INIT#

ERROR#

ALF#

STROBE#

DCD1# / GP43 DSR1# / GP44

RXD1 / GP45

RTS1# / GP46

GP47 / TXD1

CTS1# / GP50

RI1# / GP52

GP53 / DCD2# GP54 / DSR2#

GP55 / RXD2

GP56 / RTS2#

GP57 / TXD2 GP60 / CTS2# GP61 / DTR2#

GP62 / RI2#

GP64 / A20M

GP63 / KBDRST#

MDAT MCLK KDAT KCLK

TACH1 / GP17 TACH2 / GP20 TACH3 / GP21

GP22 / PWM1 GP23 / PWM2 GP24 / PWM3

V_IN

REMOTE1+

REMOTE1-

GP14

UO4

Dummy

4

Y

3

2

+3V_DUAL

Reserved for pin 24,34,57,79,106,122

RO8

*

2MOhm

+/-5%

80 81

PE

82 83 84 85 86 87 88 89 90 91 93 94 95 96 97

98 99 100 101 102 103 104 105

107 108 109 110 111 112 113 114

121 120 118 117 116 115

39 40 41 49 50 51

22 48

43 44 45 46 35 38

Delet RO36,RO37 and connect Tmin_Shift to PCH directly; SMSC suggestion-12/08/09

RO41

CO10

*

1uF

16V, X5R, +/-10%

O_SLCT O_PE O_BUSY O_ACK#

O_ERR#

O_DCD1#_R 50 O_DSR1#_R 50 O_RXD1_R 50 O_RTS1#_R 50 O_TXD1_R 50 O_CTS1#_R 50 O_DTR1#_R 33,50 O_RI1#_R 50

O_DCD2#_R 55 O_DSR2#_R 55

O_RTS2#_R

O_PECI_REQ# O_CPUFAN_ID

22 Ohm

*

+/-1%

O_RXD2_R 55 O_TXD2_R 33,55

O_CTS2#_R 55 O_DTR2#_R 33 O_RI2#_R 55

O_GA20 23 O_KB_RST# 23 O_MS_DATA 49 O_MS_CLK 49 O_KB_DATA 49 O_KB_CLK 49

O_SEN_CPUFAN 48 O_SEN_CHAFAN 48

O_CPUFAN_PWM 48 O_CHAFAN_PWM 48

O_TR_CPU+ 47 O_TR_CPU- 47 O_TR_MB+ 47 O_TR_MB- 47

X_PLTRST_PCIE_SLOT# 38,39,59

RO109RO109

RNO4

4 2

1K

+/-5%

1K+/-5%

1 2

TMIN_SHIFT 23 H_PROCHOT# 9,67

CO2

0.1uF

16V, X7R, +/-10%

5786 3

*

1

RO53

*

20100111: Remove PSU PWM control

CO4

CO5

0.1uF

16V, X7R, +/-10%

+5V

S_SMBCLK_MAIN15,16,17,18,52

S_SMBDATA_MAIN15,16,17,18,52

+12V_CPU

*

RO23

8.2K

+/-5%

*

RO28

RO28 698

698

+/-1%

RO12 30K

CO14

*

100pF

CO17

*

100pF

2

CO5

0.1uF

16V, X7R, +/-10%

Add SMBus switch circuit-11/25/09

20100105: Mount SMBus control circuit by B_ATX_PWROK

*

+/-1%

RO29 8.2K +/-5%

O_TR_MB+

50V, NPO, +/-5%

O_TR_MB-

O_TR_CPU+

50V, NPO, +/-5%

O_TR_CPU-

CO3

0.1uF

16V, X7R, +/-10%

+3V_DUAL

DO1 change to RO109; SMSC suggestion-12/08/09

S_PECI_REQ# 24

close to 5544 pin45,46

close to 5544 pin43,44

CO6

0.1uF

*

16V, X7R, +/-10%

43

CO7

0.1uF

16V, X7R, +/-10%

B_ATX_PWROK63,71

S_SMB_SW

+3V

5

2

Delet RO6; SMSC

CO8

suggestion-12/08/09

0.1uF

16V, X7R, +/-10%

+3V_DUAL

*

MMDT5551

QO16

1 6

RO108 10K

*

QO4

G

2N7002

DS

S_SMBCLK_PCI 24,38,39,58,59

QO5

G

2N7002

DS

S_SMBDATA_PCI 24,38,39,58,59

*

RO19

RO19 30K

30K

+/-1%

O_RTS2#_R

MMDT5551

QO2

+3V_DUAL

1 6

RO20 8.2K+/-5%

RO20 8.2K+/-5% RO21 8.2K+/-5%

RO21 8.2K+/-5% RO22 8.2K+/-5%

RO22 8.2K+/-5% RO38 100K+/-5%

RO38 100K+/-5%

+3V

RO24 4.7K+/-5%

RO24 4.7K+/-5% RO25 4.7K+/-5%

RO25 4.7K+/-5% RO26 30K +/-1%

RO26 30K +/-1% RO27 8.2K+/-5%

RO27 8.2K+/-5%

+3V_S5

RO13 4.7K+/-5%

RO13 4.7K+/-5% RO14 4.7K+/-5%

RO14 4.7K+/-5%

Title

SIO-SCH5544-1

DWG NO Rev

Date: Sheet

Date: Sheet of

SIO-SCH5544-1

Lanikai _MT/DT

1

PWRGD_3V

CO1

100pF

50V, NPO, +/-5%

20100107: change to +3V_DUAL for layout

RO107

RO107 10K

10K

+/-1%

43

5

2

S_SMB_SW

*

* *

*

Dummy

*

1

*

O_AUD_PCSPKR_DET# O_BC_CLK

SPI_DI T_ESATA_DET#

S_SMBDATA_MAIN S_SMBCLK_MAIN O_TXD1_R TMIN_SHIFT

S_SMBDATA_PCI S_SMBCLK_PCI

32 71Wednesday, June 13, 2012

+12V

of

*

RO106

8.2K

A00

RO3

8.2K

+/-5%

5

A

SCH5544 Decoupling

+3V_DUAL

CO19

CO18

*

0.1uF

16V, X7R, +/-10%

Dummy

D D

Dummy

CO19

*

0.1uF

16V, X7R, +/-10%

Dummy

+VCCRTC_SIO

CO20

*

0.1uF

16V, X7R, +/-10%

+3V

CO21

*

0.1uF

16V, X7R, +/-10%

4

3

+3V +3V

RO43

*

30K

+/-1%

O_TXD2_R O_DTR2#_R

2

RO44

*

30K

+/-1%

1

+1P05V_VCCIO

O_TXD2_R32,55

+3V

RO51

*

2KOhm

+/-1%

*

RO55

RO55 33KOhm

33KOhm

+/-1%

MMDT5551

QO6

+3V_EPW

43

5

1 6

2

C C

+1P05V_PCH

O_TXD2_R

43

5

1 6

2

+1P05V_ME

MMDT5551

QO7

*

O_TXD2_R

+3V

O_TXD2_R

RO45

8.25K

+/-1%

RO49

7.15K

+/-1%

*

+3V

RO56

8.25K

+/-1%

RO57

6.8K

+/-1%

+3V_DUAL +3V_DUAL

RO46

*

8.2K

+/-5%

Dummy

O_SPEAKER 31,32 O_DTR1#_R 32,50

RO52

*

8.25K

+/-1%

20100107: Remove RO47, RO53 and O_RTS1#_R strapping, SMSC suggestion

SPEAKER

Diag_En Flash_en

PULL HIGH

PULL LOW

Disable

Enable

DTR1#

Flash Enable

Parallel Enable

*

RO54

*

SIO STRAPING

RO48

8.2K

+/-5%

Dummy

30K

+/-1%

+5V

135

*

RNO1

RO50

1K

+/-5%

RO50

*

1K

+/-5%

O_INDEX# 32

O_DSKCHG# 32 O_TRK0# 32 O_WPT# 32 O_RDATA# 32

642

7 8

B B

+1P5V_SM

O_TXD2_R

43

+3V

MMDT5551

QO9

*

RO62

30K

+/-1%

P_VR_READY24,52,64,67

5

1 6

2

5544 PRE-POST DIAG PG GENERATION

+3V

*

RO58

8.25K

+/-1%

RO61

RO61 10K

10K

+/-1%

O_DTR2#_R 32

20100104: Removed useless dummied components, and only left O_PECI_READY pull-up

+1P05V_VCCIO

*

RO60

RO60 1K

1K

O_GP73_PU 32

Title

SIO-SCH5544-2 (MISC)

DWG NO Rev

Date: Sheet

Date: Sheet of

SIO-SCH5544-2 (MISC)

Lanikai _MT/DT

33 71Wednesday, June 13, 2012

A

A00

of

5

20091216 Intel 82579 schematic check list 0.5:

D D

C C

Change net name from CLK_REQ_N to S_FLEXBAY_HDR_CBL_DET# 20100105: Remove RL2 and S_FLEXBAY_HDR_CBL_DET#

connection since useless; PDG 0.8

near the PCIe transmitter.

X_L1X1_RXP22 X_L1X1_RXN22 X_L1X1_TXP22 X_L1X1_TXN22

20091216 CRB0.7 :Connect a series CL24 (10 pF) capacitor to XTAL_OUT (pin 9).

CL1 0.1uF

16V, X7R, +/-10%

*

CL3 0.1uF

16V, X7R, +/-10%

*

CL2 0.1uF

16V, X7R, +/-10%

*

CL4 0.1uF

16V, X7R, +/-10%

*

RL15 0

XL1

1 2

XTAL 25MHz

CL7

*

33pF

50V, NPO, +/-10%

*

S_PLTRST#9,24,32,46,52,53

C_PCIE_L1#27

S_SMLINK0_CLK24

S_SMLINK0_DATA24

L_ACTLEDN35

L_LINK100#35

+3V_LAN

less than 325 mils

CL8

*

33pF

50V, NPO, +/-10%

C_PCIE_L127

L_LINK10#35

+3V_LAN

RL12 1K

4

L_LAN_DISABLE#

ALWAYS DUMMY

RL6 10K

RL7 10K

*

Dummy

RL8 10K

*

Dummy

*

RL13 3.01K

+3V_LAN

X_L1X1_RXP_C X_L1X1_RXN_C

X_L1X1_TXP_C X_L1X1_TXN_C

*

Dummy

TPL1

Dummy

L_LAN_TESTEN

*

+/-1%

*

RL1

RL1 10K

10K

UL1

48

CLK_REQ_N

36

PE_RST_N

44

PE_CLKP

45

PE_CLKN

38

PETP

39

PETN

41

PERP

42

PERN

28

SMB_CLK

31

SMB_DATA

3

LAN_DISABLE_N

26

LED0

27

LED1

25

LED2

32

JTAG_TDI

34

JTAG_TDO

33

JTAG_TMS

35

JTAG_TCK

9

XTAL_OUT

10

XTAL_IN

30

TEST_ENABLE

12

RBIAS

21040FE00-187-G

LED

JTAG

PCIESMBUS

3

MDI_PLUS_0

MDI_MINUS_0

MDI_PLUS_1

MDI_MINUS_1

MDI_PLUS_2

MDI

MDI_MINUS_2

MDI_PLUS_3

MDI_MINUS_3

RSVD_NC

RSVD_1/VCCP3P3_1 RSVD_2/VCCP3P3_2

VDD3P3_IN

VDD3P3_OUT

VDD3P3_1 VDD3P3_2 VDD3P3_3

VDD1P0_7 VDD1P0_8 VDD1P0_9

VDD1P0_1 VDD1P0_2 VDD1P0_3

VDD1P0_4 VDD1P0_5 VDD1P0_6

CTRL_1P0

VSS_EPAD

13 14

17 18

20 21

23 24

6 1

2 5

4

VDD3P3

15 19 29

47 46 37

43 11 40

22 16 8

7 49

CL5

*

1uF

6.3V,X5R,+/-10%

L_LAN_1P0_CTRL

Net VDD1P0 and L1_LAN_1P0_CTRL keep short and wide

CL6

*

1uF 6.3V,X5R,+/-10%

Dummy

Place close to PHY

VDD1P0

L_MDI_0+ 35 L_MDI_0- 35

L_MDI_1+ 35 L_MDI_1- 35

L_MDI_2+ 35 L_MDI_2- 35

L_MDI_3+ 35 L_MDI_3- 35

+3V_LAN

+1P05V_PCH

LL1

4.7uH

*

CL9

*

22uF

6.3V,X5R,+/-20%

20100107: Dummy RL9 and Mount LL1; CRB 0.7

2

+3V_LAN

*

RL4

3.3K

Place near pin

RL9

0

+/-5%

Dummy

CL10

*

0.1uF

16V, X7R, +/-10%

1

*

RL5

3.3K

+3V_LAN

*

RL10

RL10 10K

10K

L_LAN_DISABLE#24

*

RL14

RL14 10K

10K

Dummy

B B

Close to PIN5 (VDD)

+3V_LAN

CL24

CL15

CL16

*

10uF

10V, X5R, +/-10%

Dummy

A A

5

CL16

*

22uF

0.1uF

16V, X7R, +/-10%

6.3V,X5R,+/-20%

4

3

2

20091216 follow CRB0.7 and 82579 cheklist: does not require any MDI termination.(delete => RL15, RL16, RL17, RL18, RL19, RL20, RL21, RL22, CL11, CL12, CL13, CL14)

Title

LAN:Intel Lewisvillies

DWG NO Rev

Date: Sheet of

Date: Sheet

LAN:Intel Lewisvillies

Lanikai _MT/DT

1

34 71Wednesday, June 13, 2012

A00

of

5

4

3

2

1

LAN CONNECTOR

+3V_LAN

D D

L_LINK10#34 L_LINK100#34

CL20

*

470pF

50V, X7R, +/-10%

+3V_LAN

L_ACTLEDN34

C C

50V, X7R, +/-10%

*

CL21

*

470pF

50V, X7R, +/-10%

CL22

470pF

CL19

0.1uF

16V, X7R, +/-10%

RL23 150 +/ -1%

RL23 150 +/ -1% RL24 150 +/ -1%

RL24 150 +/ -1%

*

L_MDI_0+34

L_MDI_0-34

L_MDI_1+34

L_MDI_1-34

L_MDI_2+34

L_MDI_2-34

L_MDI_3+34

L_MDI_3-34

CL23

470pF

50V, X7R, +/-10%

VCT

*

RL25 150

*

+/ -1%

CL17

*

1uF

25V, X5R, +/-10%

CL18

0.1uF

16V, X7R, +/-10%

14

13 15

6 2 3 4 5 7 8 9

10

1

12 11

GRN_LED

ORG_LED

YLW_LED

USB-2

RJ45-MJ2

CONN-USBX2_RJ45

NIC_USB

USB-1

28 29 30 31

16 20

17 21

18 22

19 23

24 25 26 27

U_USB9N_R U_USB8N_R

U_USB9P_R U_USB8P_R

USBPWR6_F_50

1 2

*

Fuse 2A

U_USB8N_R U_USB8P_R

U_USB9N_R U_USB9P_R

FU1

U_USB8N_R

U_USB9N_R

USBPWR6_F_50+5V_DUAL_USBKB

ECU1

*

470uF

6.3V, +/-20%

1 2 3

CU7

*

0.1uF

16V, X7R, +/-10%

LU1

Common Choke 90 Ohm

LU2

1 2 3

Common Choke 90 Ohm

1 6 2 3

RU3 0

*

RU4 0

*

RU5 0

*

RU6 0

*

UU1

IP4220CZ6

4

Dummy

Dummy Dummy

Dummy

Dummy Dummy

Dummy

RU1 10K

*

4

USBPWR6_F_50

U_USB8P_R

5 4

U_USB9P_R

+/-1%

1

RU2

RU2 15K

15K

+/-1%

2

U_USB8N 22 U_USB8P 22

U_USB9N 22 U_USB9P 22

U_USB_OC_R_#4 22

LAN POWER

B B

RL29 4.7K

*

S_SLP_LAN#24

A A

5

*

B

RL31

RL31 100K

100K

Dummy

+5V_S5

*

E C

RL26

RL26 1K

1K

QL2

QL2 MMBT3904-7-F

MMBT3904-7-F

L_VREG_LANDUAL_PCH

4

RL30

*

1K

+/-1%

CL26

*

1uF

6.3V,X5R,+/-10%

+3V

*

CL27

1uF

16V, X5R, +/-10%

3

+3V_S5

L_VREG_Gate

+3V_S5

*

SI4835DDY-T1-E3

SI4835DDY-T1-E3 QL1

QL1

3 2 1

4

CL28

1uF

16V, X5R, +/-10%

8 7 6 5

+3V_LAN

12

ECL1

*

120uF

16V, +/-20%

2

CL25

*

0.1uF

16V, X7R, +/-10%

Intel

Title

LAN Power & LAN/USB Conn

DWG NO Rev

Lanikai _MT/DT

Date: Sheet

Date: Sheet of

Lanikai _MT/DT

1

A00

of

35 71Wednesday, June 13, 2012

5

A

4

3

2

1

+5V +5VA

FBA1

FB 600 Ohm

CA2

CA1

*

10uF

6.3V, X5R, +/-20%

0.1uF

16V, X7R, +/-10%

D D

*

Amplifer Power from 5V

close to pin 39

CA4

CA3

*

0.1uF

10uF

16V, X7R, +/-10%

6.3V, X5R, +/-20%

A_BIAS_MIC1_L

CA5 10uF 6.3V, X5R, +/-20%

*

close to pin 28

A_GND

VCC_AUD

+5V_S5

FBA2 FB 600 Ohm*FBA2 FB 600 Ohm

*

Dummy

C C

+3V

Digital Power from 3V

FBA4

*

FB 600 Ohm

CA12

*

0.1uF

16V, X7R, +/-10%

Dummy

*

CA16

0.1uF

16V, X7R, +/-10%

CLASSD_R+37

CLASSD_R-37

+3V_VA

close to pin 1

CA15

CA14

*

10uF

6.3V, X5R, +/-20%

0.1uF

16V, X7R, +/-10%

B B

PD#

+3V_VA

A_Z_RST#

RA9 0 +/-5%

*

Dummy

RA10 0 +/-5%

*

Dummy

Cap-saving, if HP-OUT port no use

6.3V, Y5V, +80%/-20%

37 38 39 40 41 42 43 44 45 46 47 48

49

+3V_VA

+5VA

A_GND

VCC_AUD

TPA2TPA2 TPA3TPA3

TPA4TPA4 TPA5TPA5

A_Z_SDOUT24,31

A_Z_BITCLK24

CA6

*

2.2uF

A_GND

AVSS2 AVDD2 PVDD1 SPK-L+ SPK-LPVSS1 PVSS2 SPK-RSPK-R+ PVDD2 SPDIFO2/EAPD SPDIFO

GND

PD#

6.3V, Y5V, +80%/-20%

CA7

*

2.2uF

35

36

34

33

CBP

CBN

CPVEE

DVDD11GPIO0/DMIC-DATA2GPIO1/DMIC-CLK3PD#4SDATA-OUT5BIT-CLK6DVSS27SDATA-IN8DVDD-IO9SYNC10RESET#11PCBEEP

TPA7TPA7

TPA6TPA6

HP-OUT-R

31

32

HP-OUT-L

*

30

CPVREF

BIT_CLK

CA20

22pF

Dummy

50V, NPO, +/-5%

29

MIC2-VREFO

MIC1-VREFO-R

A_Z_SDIN0_R

27

28

26

VREF

MIC1-VREFO-L

RA13 33+/-5%

25

AVSS1

AVDD1

MONO-OUT

12

TPA8TPA8

*

VCC_AUD

LINE1-R

LINE1-L

MIC1-R

MIC1-L

JDREF

Sense-B

MIC2-R

MIC2-L

LINE2-R

LINE2-L

Sense A

Front HP

A_FRONT_L 37 A_FRONT_R 37

A_BIAS_MIC1_L_VB 37

A_BIAS_MIC1_R 37

A_BIAS_MIC2 37 A_BIAS_MIC1_L 37

A_GND

UA1

24 23 22 21 20 19 18 17 16 15 14 13

A_GND

TPA1TPA1

RA8 20K +/-1%

*

ANALOG DIGITAL

ALC269Q-VB3-GR

A_Z_RST# 24 A_Z_SYNC 24

+3V_VA

A_Z_SDIN0 24

40 mils

CA9

CA10

0.1uF

16V, X7R, +/-10%

*

Dummy

CA10

10uF

6.3V, X5R, +/-20%

close to pin 25

VCC_AUD decouple

VCC_AUD

close to pin 38

CA17

*

0.1uF

16V, X7R, +/-10%

A_GND A_GND

CA18

*

0.1uF

16V, X7R, +/-10%

*

A_GND

CA19

10uF

6.3V, X5R, +/-20%

*

CA8

*

10uF

6.3V, X5R, +/-20%

A_MIC1_R 37 A_MIC1_L 37

A_GND

A_MIC2_R 37 A_MIC2_L 37 A_LOUT_R 37 A_LOUT_L 37 A_SENSE 37

Front MIC

B_SENSE 37

Rear

*

A_GND A_GND

Dummy

Pop RA10: always H Pop RA11 : control by BIOS (GPIO) Pop RA9 : for De-pop during powr on.

PD#= L : Power down Class D SPK amplifer PD#= H : Power up Class D SPK amplifer

+3V_VA

Dummy

A_Z_RST#

RA14 4.7K+/-5%

*

Pop is RST signal glitched

QA1

QA1 2N7002

2N7002

G

RA12 reserved for co-layout ALC269-VC

+5V_S5+3V_S5

*

RA41

RA41 1K

1K

DS

*

RA12

RA12 10K

10K

Dummy

PD#A_Z_RST#

Title

Audio ALC269Q

DWG NO Rev

Date: Sheet

Date: Sheet of

Audio ALC269Q

Lanikai _MT/DT

36 71Wednesday, June 13, 2012

of

A00

A

5

A

4

3

2

1

Front Audio Rear Audio Jack

A_BIAS_MIC1_R36 A_BIAS_MIC1_L36

A_BIAS_MIC1_L_VB36

*

RA17

2.2KOhm

+/-1%

RA18

2.2KOhm

+/-1%

Dummy

D D

6.3V, X5R, +/-10%

1 2

CA23 4.7uF

A_FRONT_R36 A_FRONT_L36

Dummy

CA23 4.7uF

1 2

CA24 4.7uF

6.3V, X5R, +/-10%

Port A Support Capless HP

Change to 22ohm; follow Wembley-12/25/09

2

1

DA6

A_MIC1_R36

A_MIC1_L36

Improve HP-OUT 32-Ohm’s Cross-Talk and THD+N

C C

A_MIC1_R_L A_MIC1_L_L

B B

PESD5V0L2BT

A_MIC1_R_C

RA22 1K +/-1%

*

A_MIC1_L_C

*

RA32 22 Ohm +/-1%

*

RA34 22 Ohm +/-1%

*

A_SENSE36

A_FRONT_R_L A_FRONT_L_L A_JD_MIC2

DA7

PESD5V0L2BT

Dummy

*

RA24 1K +/-1%

*

RA36 39.2K +/-1%

RA36 39.2K +/-1% RA37 20K +/-1%

RA37 20K +/-1%

2

1

*

* *

*

Close to Pin 33

It can be reserved if output de-coupled cap used SMD type.

close to codec

*

RA19

2.2KOhm

+/-1%

*

A_GND A_GND

A_JD_FRONT 56 A_JD_MIC1 56

*

A_GND A_GND

CA33

*

470pF

50V, X7R, +/-10%

CA25

470pF

50V, X7R, +/-10%

CA34

470pF

50V, X7R, +/-10%

Front HP Front MIC

25V,+/-20%

A_GND

A_LOUT_L_C

A_LOUT_R_C

RA28 1K

RA30 1K

CPA2

COPPER

Dummy

CPA4

COPPER

Dummy

CPA5

COPPER

Dummy

CA21 10uF

1 2

*

1 2

*

CA21 10uF

*

CA22 10uF

25V,+/-20%

*

A_BIAS_MIC236

A_MIC2_L_C

A_MIC2_R_C

A_LOUT_L36

A_LOUT_R36

Front MIC

A_MIC1_R_L 56 A_MIC1_L_L 56

CA26

*

470pF

50V, X7R, +/-10%

6.3V, X5R, +/-10%

CA27 4.7uF

CA35 10nF

25V, X7R, +/-10%

*

CA36 10nF

25V, X7R, +/-10%

*

CA37 10nF

25V, X7R, +/-10%

*

CA38 10nF

25V, X7R, +/-10%

*

CA39 10nF

25V, X7R, +/-10%

*

CA27 4.7uF

CA28 4.7uF

6.3V, X5R, +/-10%

Front HP

A_FRONT_R_L 56 A_FRONT_L_L 56

A_MIC2_L36

A_MIC2_R36

A_GND

*

* *

*

4.7KOhm

+/-1%

12

B_SENSE36

RA15 75+/-1%

*

RA20 75+/-1%

*

Rear Line In / Mic

close to codec

3

2

1

*

RA26

+/-1%

DA3

DA3 BAT54A

BAT54A

RA27

4.7KOhm

+/-1%

470pF

A_LOUT_L_L A_LOUT_R_L

PESD5V0L2BT

Close to Pin 33

CA29

*

50V, X7R, +/-10%

A_GNDA_GND A_GNDA_GND

Dummy

RA38 20K +/-1%

RA38 20K +/-1% RA39 39.2K +/-1%

RA39 39.2K +/-1%

A_LOUT_L_L

A_LOUT_R_L

A_JD_LOUT

A_MIC2_L_L

A_JD_MIC2 A_MIC2_R_L

CA30

CA31

*

2

*

470pF

50V, X7R, +/-10%

A_MIC2_L_L A_MIC2_R_L

PESD5V0L2BT

Dummy

470pF

50V, X7R, +/-10%

1

3

A_GND A_GND

DA5

*

* *

*

Audio Jack

D

C

CA32

*

470pF

50V, X7R, +/-10%

A_GND

1

DA4

3

A_JD_LOUT

AUDIO

22 23 24 25

2 3 4 5 1

CONN-Audio Port

2

Rear MIC In/LINE IN Rear Line out

LINE_OUT

LINE_IN / MIC_IN

INSULATOR

26 27 28 29

A_GND

3

A_GND A_GND

CLASSD_R-36

CLASSD_R+36

close to AR12, AR13

Place near Audio Chip

CA43 1uF

*

10V, X5R, +/-10%Dummy

3

CA41

*

1nF

50V, X7R, +/-10%

CA45

*

1nF

50V, X7R, +/-10%

CLASSD_R-

CLASSD_R+

Place connector

CA42

*

100pF

50V, NPO, +/-5%

Dummy

INT_SPKR

1 3

O_AUD_PCSPKR_DET#32

*

4 5

Header_1X5_K2

CA44

100pF

50V, NPO, +/-5%

Dummy

Place connector

Header 1x5 cut2

Pin.1--> LeftPin.2--> NC key Pin.3--> GND Pin.4--> SPK det# Pin.5--> Left+

CHASSIS SPEAKER

Title

Audio Conn

DWG NO Rev

Date: Sheet

Date: Sheet of

Audio Conn

Lanikai _MT/DT

37 71Wednesday, June 13, 2012

A

A00

of

5

X_1X16_TXP[15..0]10

D D

C C

B B

A A

X_1X16_TXN[15..0]10

RX1 0 Dummy

*

S_SMBCLK_PCI24,32,39,58,59

S_SMBDATA_PCI24,32,39,58,59

X_1X16_TXP0 X_1X16_TXN0

X_1X16_TXP1 X_1X16_TXN1

X_1X16_TXP2 X_1X16_TXN2

X_1X16_TXP3 X_1X16_TXN3

X_1X16_TXP4 X_1X16_TXN4

X_1X16_TXP5 X_1X16_TXN5

X_1X16_TXP6 X_1X16_TXN6

X_1X16_TXP7 X_1X16_TXN7

X_1X16_TXP8 X_1X16_TXN8

X_1X16_TXP9 X_1X16_TXN9

X_1X16_TXP10 X_1X16_TXN10

X_1X16_TXP11 X_1X16_TXN11

X_1X16_TXP12 X_1X16_TXN12

X_1X16_TXP13 X_1X16_TXN13

X_1X16_TXP14 X_1X16_TXN14

X_1X16_TXP15 X_1X16_TXN15

5

CX36 220nF 16V,X7R,+/-10%

CX36 220nF 16V,X7R,+/-10% CX37 220nF 16V,X7R,+/-10%

CX37 220nF 16V,X7R,+/-10%

CX34 220nF 16V,X7R,+/-10%

CX34 220nF 16V,X7R,+/-10% CX35 220nF 16V,X7R,+/-10%

CX35 220nF 16V,X7R,+/-10%

CX32 220nF 16V,X7R,+/-10%

CX32 220nF 16V,X7R,+/-10% CX33 220nF 16V,X7R,+/-10%

CX33 220nF 16V,X7R,+/-10%

CX30 220nF 16V,X7R,+/-10%

CX30 220nF 16V,X7R,+/-10% CX31 220nF 16V,X7R,+/-10%

CX31 220nF 16V,X7R,+/-10%

CX28 220nF 16V,X7R,+/-10%

CX28 220nF 16V,X7R,+/-10% CX29 220nF 16V,X7R,+/-10%

CX29 220nF 16V,X7R,+/-10%

CX26 220nF 16V,X7R,+/-10%

CX26 220nF 16V,X7R,+/-10% CX27 220nF 16V,X7R,+/-10%

CX27 220nF 16V,X7R,+/-10%

CX24 220nF 16V,X7R,+/-10%

CX24 220nF 16V,X7R,+/-10% CX25 220nF 16V,X7R,+/-10%

CX25 220nF 16V,X7R,+/-10%

CX22 220nF 16V,X7R,+/-10%

CX22 220nF 16V,X7R,+/-10% CX23 220nF 16V,X7R,+/-10%

CX23 220nF 16V,X7R,+/-10%

CX20 220nF 16V,X7R,+/-10%

CX20 220nF 16V,X7R,+/-10% CX21 220nF 16V,X7R,+/-10%

CX21 220nF 16V,X7R,+/-10%

CX18 220nF 16V,X7R,+/-10%

CX18 220nF 16V,X7R,+/-10% CX19 220nF 16V,X7R,+/-10%

CX19 220nF 16V,X7R,+/-10%

CX15 220nF 16V,X7R,+/-10%

CX15 220nF 16V,X7R,+/-10% CX17 220nF 16V,X7R,+/-10%

CX17 220nF 16V,X7R,+/-10%

CX13 220nF 16V,X7R,+/-10%

CX13 220nF 16V,X7R,+/-10% CX14 220nF 16V,X7R,+/-10%

CX14 220nF 16V,X7R,+/-10%

CX11 220nF 16V,X7R,+/-10%

CX11 220nF 16V,X7R,+/-10% CX12 220nF 16V,X7R,+/-10%

CX12 220nF 16V,X7R,+/-10%

CX7 220nF 16V,X7R,+/-10%

CX7 220nF 16V,X7R,+/-10% CX10 220nF 16V,X7R,+/-10%

CX10 220nF 16V,X7R,+/-10%

CX5 220nF 16V,X7R,+/-10%

CX5 220nF 16V,X7R,+/-10% CX6 220nF 16V,X7R,+/-10%

CX6 220nF 16V,X7R,+/-10%

CX3 220nF 16V,X7R,+/-10%

CX3 220nF 16V,X7R,+/-10% CX4 220nF 16V,X7R,+/-10%

CX4 220nF 16V,X7R,+/-10%

*

RX2 0 Dummy

*

S_WAKE#24

*

* *

*

* *

*

* *

*

* *

*

* *

*

* *

*

* *

*

* *

*

* *

*

* *

*

* *

*

* *

*

+3V_PCIAUX

X_EXP_A_TX_C_DP0 X_EXP_A_TX_C_DN0

X_EXP_A_TX_C_DP1 X_EXP_A_TX_C_DN1

X_EXP_A_TX_C_DP2 X_EXP_A_TX_C_DN2

X_EXP_A_TX_C_DP3 X_EXP_A_TX_C_DN3

X_EXP_A_TX_C_DP4 X_EXP_A_TX_C_DN4

X_EXP_A_TX_C_DP5 X_EXP_A_TX_C_DN5

X_EXP_A_TX_C_DP6 X_EXP_A_TX_C_DN6

X_EXP_A_TX_C_DP7 X_EXP_A_TX_C_DN7

X_EXP_A_TX_C_DP8 X_EXP_A_TX_C_DN8

X_EXP_A_TX_C_DP9 X_EXP_A_TX_C_DN9

X_EXP_A_TX_C_DP10 X_EXP_A_TX_C_DN10

X_EXP_A_TX_C_DP11 X_EXP_A_TX_C_DN11

X_EXP_A_TX_C_DP12 X_EXP_A_TX_C_DN12

X_EXP_A_TX_C_DP13 X_EXP_A_TX_C_DN13

X_EXP_A_TX_C_DP14 X_EXP_A_TX_C_DN14

X_EXP_A_TX_C_DP15 X_EXP_A_TX_C_DN15

4

X16_TCLK

4

2010317: Slot1 change to Blue, Foxconn P/N: 34030EK00-600-G

SLOT1

B10 B11

B12 B13 B14 B15 B16 B17 B18

B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32

B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49

B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82

B1 B2 B3 B4 B5 B6 B7 B8 B9

12V1 12V2 RSVD8 GND1 SMCLK SMDAT GND2

3.3V3 JTAG1

3.3VAUX WAKE#

RSVD1 GND3 HSOP0 HSON0 GND4 PRSNT2_B17# GND5

HSOP1 HSON1 GND6 GND7 HSOP2 HSON2 GND8 GND9 HSOP3 HSON3 GND10 RSVD2 PRSNT2_B31# GND11

HSOP4 HSON4 GND12 GND13 HSOP5 HSON5 GND14 GND15 HSOP6 HSON6 GND16 GND17 HSOP7 HSON7 GND18 PRSNT2_B48# GND19

HSOP8 HSON8 GND20 GND21 HSOP9 HSON9 GND22 GND23 HSOP10 HSON10 GND24 GND25 HSOP11 HSON11 GND26 GND27 HSOP12 HSON12 GND28 GND29 HSOP13 HSON13 GND30 GND31 HSOP14 HSON14 GND32 GND33 HSOP15 HSON15 GND34 PRSNT2_B81# RSVD3

PRSNT1#

PWRGD

KEY

REFCLK+

REFCLK-

Slot-PCIE-16X

12V3 12V4

GND68

JTAG2 JTAG3 JTAG4 JTAG5

3.3V1

3.3V2

GND67

GND66

HSIP0

HSIN0

GND65

RSVD7 GND64

HSIP1

HSIN1 GND63 GND62

HSIP2

HSIN2 GND61 GND60

HSIP3

HSIN3 GND59 RSVD6

RSVD5 GND58

HSIP4

HSIN4 GND57 GND56

HSIP5

HSIN5 GND55 GND54

HSIP6

HSIN6 GND53 GND52

HSIP7

HSIN7 GND51

RSVD4 GND50

HSIP8

HSIN8

GND49 GND48

HSIP9

HSIN9

GND47 GND46

HSIP10

HSIN10

GND45 GND44 HSIP11

HSIN11

GND43 GND42 HSIP12

HSIN12

GND41 GND40 HSIP13

HSIN13

GND39 GND38 HSIP14

HSIN14

GND37 GND36 HSIP15

HSIN15

GND35

+12V+12V+3V +3V

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32

A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

3

20100513: RNX1 pin1 change connection to GND and pin5 change connection to +3V

+3V

X16_TRST X16_TDI

X16_TMS

X_1X16_RXP0 X_1X16_RXN0

X_1X16_RXP1 X_1X16_RXN1

X_1X16_RXP2 X_1X16_RXN2

X_1X16_RXP3 X_1X16_RXN3

X_1X16_RXP4 X_1X16_RXN4

X_1X16_RXP5 X_1X16_RXN5

X_1X16_RXP6 X_1X16_RXN6

X_1X16_RXP7 X_1X16_RXN7

X_1X16_RXP8 X_1X16_RXN8

X_1X16_RXP9 X_1X16_RXN9

X_1X16_RXP10 X_1X16_RXN10

X_1X16_RXP11 X_1X16_RXN11

X_1X16_RXP12 X_1X16_RXN12

X_1X16_RXP13 X_1X16_RXN13

X_1X16_RXP14 X_1X16_RXN14

X_1X16_RXP15 X_1X16_RXN15

340303U00-600-G 340304R00-278-G 340304J00-317-G 340306Y00-GRS-G

3

20100108: Swap pin for layout

Dummy

RNX1

1 3 5 7 8

4.7K Ohm

+/-5%

2 4 6

X16_TRST X16_TDI X16_TMS X16_TCLK

*

X_PLTRST_PCIE_SLOT# 32,39,59

C_PCIEX16_1 27 C_PCIEX16#_1 27

2

X_1X16_RXP[15..0] 10 X_1X16_RXN[15..0] 10

+12V

CX1

ECX1

*

470uF

16V, +/-20%

+3V

Dummy

ECX2

*

470uF

+/-20%

+3V_PCIAUX

ECX3

*

470uF

+/-20%

20100121: update footprint 20100204: Need to update part # 20100317: Link 2EG00211-T7L-4F from M disk

SLOT1_LATCH

GG

Date: Sheet

Date: Sheet of

2

Date: Sheet of

CX1

*

0.1uF

16V, X7R, +/-10%

CX8

*

0.1uF

16V, X7R, +/-10%

CX16

*

0.1uF

16V, X7R, +/-10%

112

Retention Module

2

Title

DWG NO Rev

1

CX2

*

0.1uF

16V, X7R, +/-10%

CX9

*

0.1uF

16V, X7R, +/-10%

Slot1: PCIe 16x

Lanikai _MT/DT

38 71Wednesday, June 13, 2012

1

A00

of

5

+3V

RNX2

*

4.7K Ohm

+/-5%

Dummy

D D

C C

B B

SLOT4_LATCH

GG

112

Retention Module

A A

Retention Module

2

Dummy

X_1X4_TXP022 X_1X4_TXN022

X_1X4_TXP122 X_1X4_TXN122

X_1X4_TXP222 X_1X4_TXN222

X_1X4_TXP322 X_1X4_TXN322

5

1 3 5 7 8

X4_TDI

2

X4_TMS

4

X4_TCLK

6

X4_TRST

+3V_PCIAUX

RX4

0 Dummy

*

RX3

*

0 Dummy

S_SMBCLK_PCI24,32,38,58,59

S_SMBDATA_PCI24,32,38,58,59

X4_WAKE#24

CX47 0.1uF 16V, X7R, +/-10%

CX47 0.1uF 16V, X7R, +/-10% CX49 0.1uF 16V, X7R, +/-10%

CX49 0.1uF 16V, X7R, +/-10%

*

CX40 0.1uF 16V, X7R, +/-10%

CX40 0.1uF 16V, X7R, +/-10% CX41 0.1uF 16V, X7R, +/-10%

CX41 0.1uF 16V, X7R, +/-10%

*

CX42 0.1uF 16V, X7R, +/-10%

CX42 0.1uF 16V, X7R, +/-10% CX43 0.1uF 16V, X7R, +/-10%

CX43 0.1uF 16V, X7R, +/-10%

*

CX44 0.1uF 16V, X7R, +/-10%

CX44 0.1uF 16V, X7R, +/-10% CX45 0.1uF 16V, X7R, +/-10%

CX45 0.1uF 16V, X7R, +/-10%

*

4

X4_TCLK

X_1X4_TXP0_C X_1X4_TXN0_C

X_1X4_TXP1_C X_1X4_TXN1_C

X_1X4_TXP2_C X_1X4_TXN2_C

X_1X4_TXP3_C X_1X4_TXN3_C

4

Change SLOT4 for Cost down-12/07/09

SLOT4

B10 B11

B12 B13 B14 B15 B16 B17 B18

B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32

B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49

B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82

B1 B2 B3 B4 B5 B6 B7 B8 B9

12V1 12V2 RSVD8 GND1 SMCLK SMDAT GND2

3.3V3 JTAG1

3.3VAUX WAKE#

RSVD1 GND3 HSOP0 HSON0 GND4 PRSNT2_B17# GND5

HSOP1 HSON1 GND6 GND7 HSOP2 HSON2 GND8 GND9 HSOP3 HSON3 GND10 RSVD2 PRSNT2_B31# GND11

HSOP4 HSON4 GND12 GND13 HSOP5 HSON5 GND14 GND15 HSOP6 HSON6 GND16 GND17 HSOP7 HSON7 GND18 PRSNT2_B48# GND19

HSOP8 HSON8 GND20 GND21 HSOP9 HSON9 GND22 GND23 HSOP10 HSON10 GND24 GND25 HSOP11 HSON11 GND26 GND27 HSOP12 HSON12 GND28 GND29 HSOP13 HSON13 GND30 GND31 HSOP14 HSON14 GND32 GND33 HSOP15 HSON15 GND34 PRSNT2_B81# RSVD3

PRSNT1#

PWRGD

KEY

REFCLK+

REFCLK-

Slot-PCIE-16X

12V3 12V4

GND68

JTAG2 JTAG3 JTAG4 JTAG5

3.3V1

3.3V2

GND67

GND66

HSIP0 HSIN0

GND65

RSVD7 GND64

HSIP1

HSIN1 GND63 GND62

HSIP2

HSIN2 GND61 GND60

HSIP3

HSIN3 GND59 RSVD6

RSVD5 GND58

HSIP4

HSIN4 GND57 GND56

HSIP5

HSIN5 GND55 GND54

HSIP6

HSIN6 GND53 GND52

HSIP7

HSIN7 GND51

RSVD4 GND50

HSIP8

HSIN8 GND49 GND48

HSIP9

HSIN9 GND47 GND46 HSIP10

HSIN10

GND45 GND44 HSIP11

HSIN11

GND43 GND42 HSIP12

HSIN12

GND41 GND40 HSIP13

HSIN13

GND39 GND38 HSIP14

HSIN14

GND37 GND36 HSIP15

HSIN15

GND35

+12V+12V+3V +3V

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32

A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

3

X4_TRST X4_TDI

X4_TMS

X_PLTRST_PCIE_SLOT# 32,38,59

C_PCIEX4_1 27 C_PCIEX4#_1 27

X_1X4_RXP0 22 X_1X4_RXN0 22

X_1X4_RXP1 22 X_1X4_RXN1 22

X_1X4_RXP2 22 X_1X4_RXN2 22

X_1X4_RXP3 22 X_1X4_RXN3 22

3

Dummy ECX5 for Cost down-11/23/09

2

Dummy ECX4,CX38 for Cost

+12V

down-11/23/09

ECX4

*

470uF

16V, +/-20%

Dummy

+3V

ECX5

*

470uF

6.3V, +/-20%

Dummy

+3V_PCIAUX

CX50

*

0.1uF

16V, X7R, +/-10%

2

CX38

*

0.1uF

16V, X7R, +/-10%

Dummy

CX46

*

0.1uF

16V, X7R, +/-10%

1

CX39

*

0.1uF

16V, X7R, +/-10%

CX48

*

0.1uF

16V, X7R, +/-10%

Title

Slot4: PCIe 4x

DWG NO Rev

Date: Sheet

Date: Sheet of

Slot4: PCIe 4x

Lanikai _MT/DT

1

39 71Wednesday, June 13, 2012

A00

of

5

CV41 0.1uF 16V, X7R, +/-10%

V_DDSP_B_DP_0_DP26 V_DDSP_B_DP_0_DN26

V_DDSP_B_DP_1_DP26 V_DDSP_B_DP_1_DN26

D D

C C

V_DDSP_B_DP_2_DP26 V_DDSP_B_DP_2_DN26

V_DDSP_B_DP_3_DP26 V_DDSP_B_DP_3_DN26

CV41 0.1uF 16V, X7R, +/-10%

*

CV35 0.1uF 16V, X7R, +/-10%

*

CV40 0.1uF 16V, X7R, +/-10%

*

CV43 0.1uF 16V, X7R, +/-10%

CV43 0.1uF 16V, X7R, +/-10% CV48 0.1uF 16V, X7R, +/-10%

CV48 0.1uF 16V, X7R, +/-10%

*

CV34 0.1uF 16V, X7R, +/-10%

*

CV47 0.1uF 16V, X7R, +/-10%

*

CV27 0.1uF 16V, X7R, +/-10%

*

V_DPB_AUX_DN V_DPB_AUX_DP

DPB_P13 V_DPB_HPD_SINK

UV7

6

O2

5

O1

4

GND_2

RCLAMP0522P.TCT

Dummy

UV8

6

O2

5

O1

4

GND_2

RCLAMP0522P.TCT

Dummy

IN1 IN2

GND_1

IN1 IN2

GND_1

Dummy for Cost down-11/23/09

CV42 0.1uF 16V, X7R, +/-10%

V_DDSP_B_AUX_DN26 V_DDSP_B_AUX_DP26

+3V

FV2

*

FUSE_1.1A

16V,X5R,+/-20%

B B

Display Port Hotplug Detect

A A

V_DPB_HPD_SINK

+5V

*

CV42 0.1uF 16V, X7R, +/-10% CV39 0.1uF 16V, X7R, +/-10%

CV39 0.1uF 16V, X7R, +/-10%

Close to Connector

CV44

CV26

1uF

+5V

*

RV43

RV43 100K

100K

CV26

10uF

Dummy

10V,X5R,+/-20%

G

*

RV50

RV50 1K

1K

Dummy

5

*

V_DPB_PWR

CV36

*

470pF

50V, X7R, +/-10%

V_DPB_HPD_SINK

DS

QV21

FDV301N

V_DDSP_B_AUX_DN_C

V_DDSP_B_AUX_DP_C

CV38

*

22uF

6.3V,X5R,+/-20%

V_DDPB_CTRL_CLK26

V_DDPB_CTRL_DATA26

V_DDSP_B_HPD 23,26

V_DPB_TX0_DP V_DPB_TX0_DN

V_DPB_TX1_DP V_DPB_TX1_DN

V_DPB_TX2_DP V_DPB_TX2_DN

V_DPB_TX3_DP V_DPB_TX3_DN

1 2 3

1

DPB_P13

2

V_DPB_HPD_SINK

3

4

V_DPB_AUX_DN V_DPB_AUX_DP

V_DDPB_CTRL_CLK V_DDPB_CTRL_DATA

+3V +3V_DUAL

*

RV56

RV56 100KOhm

100KOhm

+/-1%

V_DPB_AUX_DN V_DPB_AUX_DP

4

Dummy for Cost down-11/23/09

UV9

10

O1

9

O2

8

GND_2

7

O3

6

O4

RCLAMP0524P.TCT Dummy

10

O1

9

O2

8

GND_2

7

O3

6

O4

RCLAMP0524P.TCT Dummy

UV10

*

RV48

RV48 100KOhm

100KOhm

+/-1%

Dummy

*

RV42

RV42 100KOhm

100KOhm

+/-1%

Dummy

RV45

2.2K

+/-5%

GND_1

RV52

*

1M

*

+3V

*

IN1 IN2

IN3 IN4

IN1 IN2

IN3 IN4

+3V+3V

RV51

RV51 100KOhm

100KOhm

+/-1%

Dummy

RV44

RV44 100KOhm

100KOhm

+/-1%

1 2 3 4 5

RV57

2.2K

+/-5%

*

RV55

RV55 100K

100K

Close to Connector

*

3

RV11

RV11 1M

1M

+/-5%

3

V_DPB_TX0_DP V_DPB_TX0_DN

V_DPB_TX1_DP V_DPB_TX1_DN

V_DPB_TX2_DP V_DPB_TX2_DN

V_DPB_TX3_DP V_DPB_TX3_DN

DPB_P13 V_DPB_AUX_DP V_DPB_AUX_DN

V_DPB_HPD_SINK V_DPB_PWR

V_DDPB_CTRL_CLK

2

V_DPB_AUX_DP

61

6 1

DPB_P13

DP_PORT1

23

HOLE3

1

ML_Lane0_P

2

GND1

3

ML_Lane0_N

4

ML_Lane1_P

5

GND2

6

ML_Lane1_N

7

ML_Lane2_P

8

GND3

9

ML_Lane2_N

10

ML_Lane3_P

11

GND4

12

ML_Lane3_N

13

GND5

14

GND6

15

AUX_CH_P

16

GND7

17

AUX_CH_N

18

H_P_DETECT

19

RETURN

20

DP_PWR

24

HOLE4

CONN - Display port

V_DDPB_CTRL_DATA

3

QV1

5

2N7002DW

4

2N7002DW

5

QV5

3

V_DPB_AUX_DN

+5V

*

RV41

RV41 1K

1K

Dummy

*

RV53

RV53 1M

1M

+/-5%

22

HOLE2

21

HOLE1

*

RV47

RV47 1M

1M

+/-5%

RV46 8.2K

*

+/-5%

2

*

CV37

0.1uF

16V, X7R, +/-10%

2

RV58

4.7K

+/-5%

5

+12V

*

V_DDSP_B_AUX_DN_CV_DDSP_B_AUX_DP_C

61

3

DPB_P13_INVDPB_P13_POSDPB_P13_POS

*

RV59

RV59 1M

1M

+/-5%

+12V

*

RV40

8.2K

+/-5%

DPB_P13_POS

DPB_P13_INV

61

3

4

QV10

QV10 2N7002DW

2N7002DW

2

Title

DWG NO Rev

Date: Sheet of

Date: Sheet

2

6 1

V_DPB_AUX_DP

DVI-D+VGA Conn

Lanikai _MT/DT

4

3

1

QV3

5

2N7002DW

5

QV7

V_DPB_AUX_DN

1

DPB_P13_INV

of

40 71Wednesday, June 13, 2012

*

RV54

1M

+/-5%

A00

5

CV1 0.1uF 16V, X7R, +/-10%

V_DDSP_C_DP_0_DP26 V_DDSP_C_DP_0_DN26

V_DDSP_C_DP_1_DP26 V_DDSP_C_DP_1_DN26

D D

C C

V_DDSP_C_DP_2_DP26 V_DDSP_C_DP_2_DN26

V_DDSP_C_DP_3_DP26 V_DDSP_C_DP_3_DN26

CV1 0.1uF 16V, X7R, +/-10%

*

CV2 0.1uF 16V, X7R, +/-10%

*

CV3 0.1uF 16V, X7R, +/-10%

*

CV4 0.1uF 16V, X7R, +/-10%

*

CV5 0.1uF 16V, X7R, +/-10%

*

CV6 0.1uF 16V, X7R, +/-10%

*

CV7 0.1uF 16V, X7R, +/-10%

*

CV8 0.1uF 16V, X7R, +/-10%

*

V_DPC_TX0_DP V_DPC_TX0_DN

V_DPC_TX1_DP V_DPC_TX1_DN

V_DPC_TX2_DP V_DPC_TX2_DN

V_DPC_TX3_DP V_DPC_TX3_DN

4

UV1

V_DPC_TX0_DP V_DPC_TX0_DN V_DPC_TX0_DN

V_DPC_TX1_DP V_DPC_TX1_DN

V_DPC_TX2_DP V_DPC_TX2_DN

V_DPC_TX3_DP V_DPC_TX3_DN V_DPC_TX3_DN

V_DPC_AUX_DN V_DPC_AUX_DP

DP_P13 V_DPC_HPD_SINK

10

O1

9

O2

8

GND_2

7

O3

6

O4

RCLAMP0524P.TCT Dummy

10

O1

9

O2

8

GND_2

7

O3

6

O4

RCLAMP0524P.TCT Dummy

UV2

UV3

6

O2

5

O1

4

GND_2

RCLAMP0522P.TCT

Dummy

UV4

6

O2

5

O1

4

GND_2

RCLAMP0522P.TCT

Dummy

GND_1

1

IN1

2

IN2

3 4

IN3

5

IN4

1

IN1

2

IN2

3 4

IN3

5

IN4

1

IN1

2

IN2

3

1

IN1

2

IN2

3

V_DPC_TX0_DP

V_DPC_TX1_DP V_DPC_TX1_DN

V_DPC_TX2_DP V_DPC_TX2_DN

V_DPC_TX3_DP

V_DPC_AUX_DN V_DPC_AUX_DP

DP_P13 V_DPC_HPD_SINK

2

DP_PORT2

23

HOLE3

V_DPC_TX0_DP V_DPC_TX0_DN

V_DPC_TX1_DP V_DPC_TX1_DN

V_DPC_TX2_DP V_DPC_TX2_DN

V_DPC_TX3_DP V_DPC_TX3_DN

DP_P13 V_DPC_AUX_DP V_DPC_AUX_DN

V_DPC_HPD_SINK

RV1

*

1M

*

RV2

RV2 100K

100K

V_DPC_PWR

1

ML_Lane0_P

2

GND1

3

ML_Lane0_N

4

ML_Lane1_P

5

GND2

6

ML_Lane1_N

7

ML_Lane2_P

8

GND3

9

ML_Lane2_N

10

ML_Lane3_P

11

GND4

12

ML_Lane3_N

13

GND5

14

GND6

15

AUX_CH_P

16

GND7

17

AUX_CH_N

18

H_P_DETECT

19

RETURN

20

DP_PWR

24

HOLE4

CONN - Display port

HOLE2

HOLE1

1

22

21

Close to Connector

V_DDPC_CTRL_CLK

CV9 0.1uF 16V, X7R, +/-10%

V_DDSP_C_AUX_DN26 V_DDSP_C_AUX_DP26

+3V

FV1 FUSE_1.1A

B B

A A

FV1 FUSE_1.1A

*

16V,X5R,+/-20%

Display Port Hotplug Detect

V_DPC_HPD_SINK

+5V

*

CV9 0.1uF 16V, X7R, +/-10% CV10 0.1uF 16V, X7R, +/-10%

CV10 0.1uF 16V, X7R, +/-10%

Close to Connector

CV12

CV11

*

RV15

RV15 1K

1K

Dummy

5

1uF

+5V

*

RV19

RV19 100K

100K

10uF

Dummy

10V,X5R,+/-20%

G

*

V_DPC_PWR

CV13

*

470pF

50V, X7R, +/-10%

V_DPC_HPD_SINK

DS

QV11

FDV301N

V_DDSP_C_AUX_DN_C

V_DDSP_C_AUX_DP_C

CV14

*

22uF

6.3V,X5R,+/-20%

V_DDPC_CTRL_CLK26

V_DDPC_CTRL_DATA26

V_DDSP_C_HPD 21,26

V_DDPC_CTRL_CLK V_DDPC_CTRL_DATA

+3V +3V_DUAL

*

RV16

RV16 100KOhm

100KOhm

+/-1%

V_DPC_AUX_DN V_DPC_AUX_DP

4

*

RV3

RV3 1M

1M

+/-5%

+3V+3V

*

RV7

RV8

2.2K

+/-5%

+3V

*

RV20

RV20 100KOhm

100KOhm

+/-1%

Dummy

RV17

RV17 100KOhm

100KOhm

+/-1%

Dummy

*

RV18

RV18 100KOhm

100KOhm

+/-1%

Dummy

RV21

RV21 100KOhm

100KOhm

+/-1%

V_DPC_AUX_DP

61

2

6 1

DP_P13

3

QV2

5

2N7002DW

4

2N7002DW

5

QV6

3

V_DPC_AUX_DN

+5V

*

V_DDPC_CTRL_DATA

RV12

RV12 1K

1K

Dummy

RV13 8.2K

RV14

RV14 1M

1M

+/-5%

61

DP_P13_INVDP_P13_POSDP_P13_POS

*

RV4

RV4 1M

1M

+/-5%

*

+/-5%

*

CV15

0.1uF

16V, X7R, +/-10%

*

RV5

RV5 1M

1M

+/-5%

+12V+12V

RV9

*

5

2

RV10

4.7K

8.2K

+/-5%

61

3

2

4

2

6 1

V_DPC_AUX_DP

DP_P13_POS

QV9

QV9 2N7002DW

2N7002DW

DP_P13_INV

Title

DWG NO Rev

Date: Sheet

Date: Sheet of

V_DDSP_C_AUX_DN_CV_DDSP_C_AUX_DP_C

3

QV4

5

2N7002DW

4

2N7002DW

5

QV8

3

V_DPC_AUX_DN

Display Port

Lanikai _MT/DT

DP_P13_INV

1

*

RV6

1M

+/-5%

A00

of

41 71Wednesday, June 13, 2012

5

4

3

2

1

VGA Connector

CV16

*

0.1uF

16V, X7R, +/-10%

21

3

QV12

QV12 BAV99

BAV99

21

3

QV14

QV14 BAV99

BAV99

21

3

QV15

QV15 BAV99

BAV99

+3V

+5V

DV1

1N4148W

C A

+5V_DDC

*

RV24

2.2K

DS

QV13

QV13 2N7002

2N7002

DS

QV16

QV16 2N7002

2N7002

2.2K

+/-5%

*

RV29

2.2K

+/-5%

V_DDCA_CLK_5V

+5V_DDC

V_DDCA_DATA_5V

G

V_RED26

V_GREEN26

V_BLUE26

Dummy for Cost down-11/23/09

V_RED

RV25

*

150

+/ -1%

V_GREEN

RV27

*

150

+/ -1%

V_BLUE

RV31

*

150

+/ -1%

+5V+5VSB

QV17

QV17 BAV99

BAV99

21

3

QV20

QV20 BAV99

BAV99

21

3

21

3

QV18

QV18 BAV99

BAV99

21

3

QV19

QV19 BAV99

BAV99

CV17

*

3.3pF

50V, NPO, +/-0.25pF

CV20

*

3.3pF

50V, NPO, +/-0.25pF

CV23

*

3.3pF

50V, NPO, +/-0.25pF

+5V

FV4

CV45

*

0.1uF

16V, X7R, +/-10%

LV1

LV2

LV3

*

FUSE_1.1A

21

D D

V_DDCA_CLK26

C C

V_DDCA_DATA26

+3V

*

RV23

2.2K

+/-5%

*

RV28

2.2K

+/-5%

Change to short pad and remove VC19, CV22,CV25 for cost down-11/23/09

RV22

1 2

Dummy

47ohm 100MHz

Dummy

CV18

*

3.3pF

50V, NPO, +/-0.25pF

RV26

1 2

Dummy

CV21

*

3.3pF

50V, NPO, +/-0.25pF

RV30

1 2

Dummy

CV24

*

3.3pF

50V, NPO, +/-0.25pF

VGAPWR_F_20

*

CV32

*

0.1uF

16V, X7R, +/-10%

CV19

10pF

50V, NPO, +/-5%

Dummy

CV22

10pF

50V, NPO, +/-5%

Dummy

CV25

10pF

50V, NPO, +/-5%

Dummy

+3V

VGA_SERIALA

+3V

RV36

B B

V_VSYNC_3V26

V_HSYNC_3V26

A A

RV36

*

4.7K

+/-5%

*

RV37

RV37 100

100

+/-5%

Dummy

+3V

RV38

*

4.7K

+/-5%

*

RV39

RV39 100

100

+/-5%

Dummy

5

+5V

CV29

*

0.1uF

UV5

4

74AHCT1G08GW

UV6

4

74AHCT1G08GW

0.1uF

16V, X7R, +/-10%

V_VSYNC_5V

V_HSYNC_5V

4

53

1 2

+5V

53

1 2

V_DDCA_CLK_5V V_VSYNC_5V V_HSYNC_5V V_DDCA_DATA_5V

RV33 100 +/-1%RV33 100 +/-1% RV32 0

RV32 0

*

RV34 0

*

RV35 100 +/-1%RV35 100 +/-1%

CV46

CV31

12pF

*

3

100pF

50V, NPO, +/-5%

+/-5%

12pF

CV30

*

CV33

*

+/-5%

100pF

50V, NPO, +/-5%

2

VGA_SERIALA

VGA

B15 B10 B14

B13 B12 B11

SCL

SCL GND

GND

VSYNC

NC

B9

HSYNC

GND

B8

SDA

SDA GND

GND

B7

ID1

ID1 GND

GND

B6

GND

B5

ID0

B4

B

B3

V_BLUE_R

G

B2

R

CONN - Dual port

1

2

Title

DWG NO Rev

Date: Sheet

Date: Sheet of

V_GREEN_R

B1

V_RED_R

VGA Conn

Lanikai _MT/DT

V_GPI_VGA_CBL_DET# 21

CV28

*

100pF

50V, NPO, +/-5%

1

A00

of

42 71Wednesday, June 13, 2012

5

4

3

2

1

SATA x 3

SATA0

CT1 10nF 25V, X7R, +/-10%

D D

C C

T_SATA_TXP023 T_SATA_TXN023

T_SATA_RXN023

T_SATA_RXP023

T_SATA_TXP123 T_SATA_TXN123

T_SATA_RXN123

T_SATA_RXP123

CT1 10nF 25V, X7R, +/-10%

*

CT2 10nF 25V, X7R, +/-10%

*

CT3 10nF 25V, X7R, +/-10%

*

CT4 10nF 25V, X7R, +/-10%

*

CT5 10nF 25V, X7R, +/-10%

*

CT6 10nF 25V, X7R, +/-10%

*

CT7 10nF 25V, X7R, +/-10%

*

CT8 10nF 25V, X7R, +/-10%

*

T_SATA_TXP0_C T_SATA_TXN0_C

T_SATA_RXN0_C T_SATA_RXP0_C

T_SATA_TXP1_C T_SATA_TXN1_C

T_SATA_RXN1_C T_SATA_RXP1_C

2

TX+

3

TX-

5

RX-

6

RX+

1

GND

4

GND#4

7

GND#7

CONN-SATA

SATA1

2

TX+

3

TX-

5

RX-

6

RX+

1

GND

4

GND#4

7

GND#7

CONN-SATA

NC#8

NC#9

NC#8

NC#9

8

9

8

9

Just SATA port 0/1 support Gen3 ; PDG0.7

T_SATA_TXP223 T_SATA_TXN223

T_SATA_RXN223

T_SATA_RXP223

B B

A A

5

4

CT9 10nF 25V, X7R, +/-10%

*

CT10 10nF 25V, X7R, +/-10%

*

CT11 10nF 25V, X7R, +/-10%

*

CT12 10nF 25V, X7R, +/-10%

*

T_SATA_TXP2_C T_SATA_TXN2_C

T_SATA_RXN2_C T_SATA_RXP2_C

3

SATA2

2

TX+

3

TX-

5

RX-

6

RX+

1

GND

4

GND#4

7

GND#7

CONN-SATA

NC#8

NC#9

8

9

Title

SATA Conn

DWG NO Rev

Date: Sheet of

2

Date: Sheet

SATA Conn

Lanikai _MT/DT

1

A00

of

43 71Wednesday, June 13, 2012

5

D D

C C

4

3

2

1

B B

A A

Title

TBD

DWG NO Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

TBD

Lanikai _MT/DT

1

A00

of

44 71Wednesday, June 13, 2012

5

D D

LU3

U_USB2N22

U_USB2P22

C C

U_USB3N22

U_USB3P22

1 2 3

Common Choke 90 Ohm

RU8 0

RU8 0 RU7 0

RU7 0

LU4

1 2 3

Common Choke 90 Ohm

RU12 0

RU12 0 RU11 0

RU11 0

*

* *

*

* *

*

Dummy

Dummy Dummy

Dummy

Dummy Dummy

Dummy

4

U_USB2N_R U_USB2P_R

4

U_USB3N_R U_USB3P_R

4

1 2

*

1 2

*

FU3

Fuse 2A

FU5

Fuse 2A

FU9

1 2

*

Fuse 2A

3

USBPWR3_F_50+5V_DUAL_USBKB

RU27 10K

*

+/-1%

ECU3

*

470uF

6.3V, +/-20%

USBPWR4_F_50+5V_DUAL_USBKB

ECU5

*

470uF

6.3V, +/-20%

USBPWR5_F_50+5V_DUAL_USBKB

ECU9

*

470uF

6.3V, +/-20%

CU9

*

0.1uF

16V, X7R, +/-10%

CU12

*

0.1uF

16V, X7R, +/-10%

CU13

*

0.1uF

16V, X7R, +/-10%

RU30 10K

RU36 10K

1

RU44

RU44 15K

15K

+/-1%

2

*

+/-1%

1

RU63

RU63 15K

15K

+/-1%

2

*

+/-1%

1

RU35

RU35 15K

15K

+/-1%

2

U_USB_OC_R_#1 22

U_USB_OC_R_#2 22

U_USB_OC_R_#3 22

2

USBPWR5_F_50

USBPWR3_F_50

USBPWR4_F_50

U_USB5N_R U_USB5P_R

U_USB4N_R U_USB4P_R

U_USB2N_R U_USB2P_R

USB3_RX3_ESD_DN USB3_RX3_ESD_DP

USB3_TX3_ESD_DN USB3_TX3_ESD_DP

U_USB3N_R U_USB3P_R

USB3_RX4_ESD_DN USB3_RX4_ESD_DP

USB3_TX4_ESD_DN USB3_TX4_ESD_DP

USB

D1

VBUS1

D2

D-1

D3

D+1

D4

GND1

C1

VBUS2

C2

D-2

C3

D+2

C4

GND2

B1

VBUS3

B2

D-3

B3

D+3

B4

GND3

B5

STDA_SSRX-1

B6

STDA_SSRX+1

B7

GND_DRAIN1

B8

STDA_SSTX-1

B9

STDA_SSTX+1

A1

VBUS4

A2

D-4

A3

D+4

A4

GND4

A5

STDA_SSRX-2

A6

STDA_SSRX+2

A7

GND_DRAIN2

A8

STDA_SSTX-2

A9

STDA_SSTX+2

CONN-USBX4

1

UP

Second

Third

Down

GND5 GND6 GND7 GND8 GND9

GND10

1 2 3 4 5 6

LU24

U_USB4P22 U_USB4N22

B B

U_USB5N22

U_USB5P22

U_USB2N_R

U_USB3N_R

A A

U_USB4N_R

U_USB5N_R

1 6 2 3

LU14

2 3 1

Common Choke 90 Ohm

RU13 0

RU13 0 RU28 0

RU28 0

UU8

IP4220CZ6

UU3

IP4220CZ6

5

4

Common Choke 90 Ohm

RU48 0 Dummy

RU48 0 Dummy RU50 0 Dummy

RU50 0 Dummy

*

Dummy

*

Dummy

USBPWR3_F_50

5 4

USBPWR5_F_50

5 4

*

* *

*

23 1

4

U_USB2P_R

U_USB3P_R

U_USB4P_R

U_USB5P_R

U_USB4P_R U_USB4N_R

U_USB5N_R U_USB5P_R

UU9

USB3_RX3_ESD_DP

Common Choke 67 Ohm

*

USB3_TX3_PCH_DP28

USB3_TX3_PCH_DN28

USB3_TX4_PCH_DP28

USB3_TX4_PCH_DN28

4

CO770.1uF*CO770.1uF

*

CO750.1uF*CO750.1uF

*

CO760.1uF*CO760.1uF

*

CO740.1uF*CO740.1uF

USB3_TX3_PCH_DP_C USB3_TX3_PCH_DN_C USB3_TX3_ESD_DN

USB3_RX3_PCH_DP28

USB3_RX3_PCH_DN28

USB3_TX4_PCH_DP_C USB3_TX4_ESD_DP

USB3_RX4_PCH_DP28

USB3_RX4_PCH_DN28

3

Common Choke 67 Ohm

2

Common Choke 67 Ohm

2

Common Choke 67 Ohm

2

Common Choke 67 Ohm

2

*

Dummy

*

Dummy

*

Dummy

*

Dummy

LU5

LU16

RU840

RU830

RU860

RU850

LU6

LU15

43 1

USB3_TX3_ESD_DP

USB3_RX3_ESD_DP USB3_RX3_ESD_DN

USB3_TX4_ESD_DNUSB3_TX4_PCH_DN_C

USB3_RX4_ESD_DP USB3_RX4_ESD_DN

2

USB3_RX3_ESD_DN

USB3_RX4_ESD_DP USB3_RX4_ESD_DN

USB3_TX4_ESD_DN USB3_TX4_ESD_DP USB3_TX4_ESD_DP

USB3_TX3_ESD_DN USB3_TX3_ESD_DP

Intel

Title

DWG NO Rev

Date: Sheet of

Date: Sheet

9 8

GND

3 7

ESD3V3U4ULC

UU7

9 8

GND

3 7

ESD3V3U4ULC

Rear USB

Lanikai _MT/DT

I/O

1

USB3_RX3_ESD_DP

2

USB3_RX3_ESD_DN

4

USB3_RX4_ESD_DP

56

USB3_RX4_ESD_DN

1

USB3_TX4_ESD_DN

2

4

USB3_TX3_ESD_DN

56

USB3_TX3_ESD_DP

1

A00

of

45 71Wednesday, June 13, 2012

5

TPM, TCM

(Default)

ST Micro ZTE Jetway

D D

C C

POP S POP Z POP J

(TCM is just reserved because MRD has removed TCM requirement)

CF4 CF2,CF4,CF7,RF10,RF19,RF20,RF21 CF2,CF8,RF10,RF16,RF21

20100510: UF1 TPM IC change to ST33ZP24 20100519: UF1 TPM IC change to SB19NP18ER28PVMT 20101001: UF1 usage TCM_SSX44-B-D-T

C_TPM27

F_FRAME#24,32,53

S_PLTRST#_R

F_LAD324,32,53

+3V

F_LAD224,32,53 F_LAD124,32,53 F_LAD024,32,53

RF27 4.7K

*

F_SERIRQ#23,32

+/-5%@S,Z,J

F_PWRDWN#

4

+3V +3V

24

UF1

21 22 16 17

20 23 26

28 27

LCLK LFRAME# LRESET# LAD3

LAD2 LAD1 LAD0

LPCPD# SERIRQ

VPS110VPS2

GND318GND211GND1

GPIO5 GPIO4

PP

GPIO3

VNC GPIO2 GPIO1

NC1 NC2 NC3 NC4 NC5 NC6 NC7

SSX44-B-D-T

4

@Z

15 9 7 6 3 2 1 5 8 12 13 14 19 25

F_TPM_CLKRUN# F_TPM_PIN9 F_TPM_PIN7 F_TPM_PIN6 F_TPM_PIN3 F_TPM_PIN2 F_TPM_PIN1 F_TPM_PIN5 F_TPM_PIN8 F_TPM_PIN12

RF16 0

*

RF10 0

*

+/-5%@J

+/-5%@Z,J

3

CF1

*

0.1uF

16V, X7R, +/-10%

close to Pin 10

TPF1TPF1 TPF2TPF2 TPF3TPF3 TPF4TPF4 TPF5TPF5

TPF6TPF6 TPF7TPF7

C_14M_TPM 27

CF7

*

1uF

6.3V,X5R,+/-10%

@Z

CF2

*

0.1uF

16V, X7R, +/-10%

@Z,J

close to Pin 19

RF17

*

Dummy

+3V

*

16V, X7R, +/-10%

0

CF3

*

0.1uF

close to Pin 24

+3V

2

CF4

10uF

6.3V, X5R, +/-20%

@S,Z

+12V

CF5

*

0.1uF

Dummy

16V, X7R, +/-10%

CF6

*

0.1uF

Dummy

16V, X7R, +/-10%

S_PLTRST#9,24,32,34,52,53

20101001: add UF2 usage TPM_SB19NP18ER28PVMK

UF2

15

GPIO5

1

GPIO1

+12V

*

G

D S

RF6 33

*

Dummy

RF4

8.2K

+/-1%

@S,Z,J

QF1

QF1 2N7002

2N7002

@S,Z,J

1

S_PLTRST#_R

*

RF5

8.2K

+/-1%

@S,Z,J

B B

ST33ZP24AR28PVSH

@S,J

A A

F_TPM_PIN5 F_TPM_PIN9 F_TPM_CLKRUN#F_TPM_PIN3

RF20

*

RF19

CF8

*

0.1uF

16V, X7R, +/-10%

@J

5

4

RF19 1K

1K

@Z

3

*

1K

@Z

*

RF21

4.7K

+/-5%

@Z,J

2

Title

TPM & TCM

DWG NO Rev

Date: Sheet of

Date: Sheet

TPM & TCM

Lanikai _MT/DT

1

46 71Wednesday, June 13, 2012

A00

of

5

A

4

3

2

1

D D

For B00 test only

RO103 0

*

Header_1X2

2 1

THRM_3

Dummy

50V, NPO, +/-5%

Header_1X2

2

C C

Dummy THRM2,CO23; ME suggestion-12/04/09

THRM_2

Dummy

1

50V, NPO, +/-5%

CO25

*

330pF

Dummy

CO23

*

330pF

Dummy

*

Dummy

RO104 0

*

Dummy

RO105 0

*

Dummy

RO110 0

*

Dummy

O_TR_CPU+ 32

O_TR_CPU- 32

O_TR_CPU+ 32

O_TR_CPU- 32

Header_1X2

THRM_1

O_TR_MB+

2 1

CO24

*

330pF

50V, NPO, +/-5%

O_TR_MB-

O_TR_MB+ 32

O_TR_MB- 32

THERMAL SENSOR

B B

Title

Thermal Sensor Conn

DWG NO Rev

Date: Sheet

Date: Sheet of

Thermal Sensor Conn

Lanikai _MT/DT

47 71Wednesday, June 13, 2012

A00

of

A

5

4

3

2

1

CPU Fan

*

RO72

4.7K

+/-5%

D D

O_SEN_CPUFAN32

O_CPUFAN_PWM32

C C

RO77 220

*

SYS Fan

*

RO83

4.7K

+/-5%

RO88 220

*

O_SEN_CHAFAN32

O_CHAFAN_PWM32

B B

*

+3V

*

RO73

RO74

4.7K

1K

+/-5%

QO11

5 4 3

MMDT5551

+3V

*

RO85

RO84

4.7K

1K

+/-5%

QO13

5 4 3

MMDT5551

16 2

O_CPUFAN_PWM_R

16 2

RO76 0

*

RO78 4.7K

*

RO87 0

*

RO89 4.7K

*

+/-5%

O_CHAFAN_PWM_R

*

RO75

4.7K

+/-5%

+/-5%Dummy

*

+/-1%

CO31

4.7uF

Dummy

CO35

4.7uF

Dummy

+12V

*

FAN_CPU

1 2 3 4 5

Header-1X5

CO32

*

0.1uF

16V, X7R, +/-10%

Dummy

+12V

*

FAN_SYS

1 2 3 4 5

Header-1X5

12

ECO2

120uF

+/-20%

+12V

*

12

ECO1

120uF

+/-20%

+/-5%

CO29

*

0.1uF

16V, X7R, +/-10%

RO80 100 Ohm

25V,Y5V,+80/-20%

+3V

*

RO86

4.7K

+/-5%

+/-5%Dummy

CO34

*

0.1uF

16V, X7R, +/-10%

RO90 100

+/-5%

25V,Y5V,+80/-20%

A A

Title

FAN

DWG NO Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

FAN

Lanikai _MT/DT

48 71Wednesday, June 13, 2012

1

A00

of

5

4

3

2

1

KB/MS

D D

+5V_DUAL_USBKB

*

C C

+5V_DUAL_USBKB

FUSE_1.1A

FO1

*

CO36

*

0.1uF

16V, X7R, +/-10%

KYBD_MOUSE

3

16 12

10

8 7 9

11 17

CONN - KB_MS

KYBD_MOUSE

UP DOWN

UO3

1 2 3

IP4220CZ6

13

6 4 2 14 1 3 5

15

Dummy

RNO3

642

2K

*

+/-5%

O_MS_DATA32 O_MS_CLK32 O_KB_CLK32 O_KB_DATA32

B B

A A

5

*

135

7 8

FBO1 FB 600 Ohm

*

FBO2 FB 600 Ohm

*

FBO3 FB 600 Ohm

*

FBO4 FB 600 Ohm

*

O_MS_DATA_L O_MS_CLK_L O_KB_CLK_L O_KB_DATA_L

CNO3

180pF

*

4

180pF

50V, NPO, +/-10%

Dummy

O_MS_DATA_L O_MS_CLK_L

Close to Pin 10 (EMI) Close to Pin 4 (EMI)

O_KB_DATA_L O_KB_CLK_L

+5V_DUAL_USBKB

6 5 4

O_MS_CLK_LO_MS_DATA_L

O_KB_CLK_LO_KB_DATA_L

2

CO37

*

0.1uF

16V, X7R, +/-10%

CO38

*

0.1uF

16V, X7R, +/-10%

Title

DWG NO Rev

Date: Sheet

Date: Sheet of

PS2 Conn

Lanikai _MT/DT

1

A00

of

49 71Wednesday, June 13, 2012

5

4

3

2

1

Serial Port 1

D D

VGA_SERIALB

4

O_DCD1# O_DSR1# O_RXD1

O_DCD1# O_DSR1# O_RXD1 O_RTS1# O_TXD1 O_CTS1# O_DTR1# O_RI1#

O_RTS1# O_TXD1 O_CTS1# O_DTR1# O_RI1#

*

CNO4

180pF

50V, NPO, +/-10%

Dummy

UO2

20

VCC

O_RTS1#_R32

C C

B B

O_DTR1#_R32,33

O_TXD1_R32

O_RI1#_R32

O_CTS1#_R32

O_DSR1#_R32

O_RXD1_R32

O_DCD1#_R32

20100326: UO2 will be changed TI/GD75232DBR to main source in X00 build.

CO41

*

0.1uF

16V, X7R, +/-10%

16 15 13 19 18 17 14 12

11

GD75232

-12V+12V

*

DA1 DA2 DA3 RY1 RY2 RY3 RY4 RY5

GND

CO42

0.1uF

16V, X7R, +/-10%

+12V

DY1 DY2 DY3 RA1 RA2 RA3 RA4 RA5

-12V

1 5

6 8 2 3 4 7 9

10

O_RTS1# O_DTR1# O_TXD1

O_RI1# O_CTS1# O_DSR1# O_RXD1 O_DCD1#

+5V

CO43

*

0.1uF

16V, X7R, +/-10%

+12V+5V

-12V

placed near connector

T1 T6 T2 T7 T3 T8 T4 T9 T5

3

CONN - Dual port

*

CNO5

180pF

50V, NPO, +/-10%

Dummy

A A

Title

COM1

DWG NO Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

COM1

Lanikai _MT/DT

1

A00

of

50 71Wednesday, June 13, 2012

5

4

+3V_S5

3

2

1

SPI

CF10

*

0.1uF

16V, X7R, +/-10%

SPI_1

D D

F_SPI_CS1#_ISOLATE24

20091225: Change net name for Dual SPI

F_SPI_CLK_PRI_SEC_FLSH_R1 F_SPI_MOSI_PRI_SEC_FLSH_R1 F_SPI_MISO_R1

SPI1

1

CS# SCK6HOLD#

5

SI

2

SO

SPI SOCKET

@PR

20110530: Change to 4M

MX25L3206EM2I-12G

RF22 33

F_SPI_MISO24

C C

F_SPI_CLK_PRI_SEC_FLSH24

F_SPI_MOSI_PRI_SEC_FLSH24

B B

RF22 33 RF23 33

RF23 33

RF28 33

RF28 33 RF29 33

RF29 33

RF30 33

RF30 33 RF31 33

RF31 33

20091225: RF23 change to 33ohm for Dual SPI 20091225: Add RF28, RF29,RF30,RF31 for Dual SPI

20100309: SPI2 Package Type change to DIP from SMD, , when usage SPI_2 socket

20100930: SPI2 change to MXIC_MX25L6445EMI-10G

F_SPI_MISO_R

*

F_SPI_MISO_R1

*

F_SPI_CLK_PRI_SEC_FLSH_R

*

F_SPI_CLK_PRI_SEC_FLSH_R1

*

F_SPI_MOSI_PRI_SEC_FLSH_R

*

F_SPI_MOSI_PRI_SEC_FLSH_R1

*

F_SPI_CS0#_ISOLATE24

SPI2

MX25L6445EMI-10G

8

VCC

7

F_SPI_HOLD1#

3

F_SPI_WP1#

WP#

4

GND

CLOSE TO SPI

If socket not use ,need change to SMD Tpye

F_SPI_HOLD# F_SPI_WP# F_SPI_HOLD1# F_SPI_WP1#

F_SPI_HOLD#

+3V_S5

F_SPI_MISO_R

20091225: Change net name for Dual SPI

16V, X7R, +/-10%

+3V_S5

*

RNF1

135

78

1K

+/-5%

642

SPI_2

1

HOLD#

2

VCC

3

DU1

4

DU2

5

DU3

6

DU4

7

S#

8

Q

ACA-SPI-006-K01

@PR

F_SPI_CS0#_ISOLATE F_SPI_CLK_PRI_SEC_FLSH_R F_SPI_MOSI_PRI_SEC_FLSH_R F_SPI_MISO_R

DU8 DU7 DU6 DU5 VSS

16

C

15

D

14 13 12 11 10 9

W#

+3V_S5

F_SPI_CLK_PRI_SEC_FLSH_R F_SPI_MOSI_PRI_SEC_FLSH_R

F_SPI_WP#

SPI_3

1

CS#

VCC

SCK6HOLD#

5

SI SO

SPI SOCKET

Dummy

WP# GND

2

CF11

*

1uF

6.3V,X5R,+/-10%

8 7 3 4

*

20091225: Change net name for Dual SPI

F_SPI_HOLD# F_SPI_WP#

CF12

0.1uF

16V, X7R, +/-10%

+3V_S5

A A

Title

SPI

DWG NO Rev

Date: Sheet of

5

4

3

2

Date: Sheet of

SPI

Lanikai _MT/DT

1

A00

51 71Wednesday, June 13, 2012

5

XDP Connector - CPU

+1P05V_VCCIO

H_PREQ#9 H_PRDY#9

H_BPM#09

D D

C C

H_BPM#19 H_BPM#29 H_BPM#39

H_BPM#49 H_BPM#59 H_BPM#69 H_BPM#79

S_SMBDATA_MAIN15,16,17,18,32

S_SMBCLK_MAIN15,16,17,18,32

For debugging

XDP_CPU

43

VCC_OBS_AB

44

VCC_OBS_CD

3

OBSFN_A0

5

OBSFN_A1

9

OBSDATA_A_0

11

OBSDATA_A_1

15

OBSDATA_A_2

17

OBSDATA_A_3

21

OBSFN_B0

23

OBSFN_B1

27

OBSDATA_B_0

29

OBSDATA_B_1

33

OBSDATA_B_2

35

OBSDATA_B_3

51

SDA

53

SCL

4

OBSFN_C0

6

OBSFN_C1

10

OBSDATA_C_0

12

OBSDATA_C_1

16

OBSDATA_C_2

18

OBSDATA_C_3

22

OBSFN_D_0

24

OBSFN_D_1

28

OBSDATA_D_0

30

OBSDATA_D_1

34

OBSDATA_D_2

36

OBSDATA_D_3

XDP

4

TCK1 TCK0

TDO

TRSTn

TMS

HOOK0 HOOK1 HOOK2 HOOK3

ITPCLK/HOOK4 ITPCLKB/HOOK5 RESETB/HOOK6

DBRB/HOOK7

GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8

GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17

GND18_XDP_PRESENTB

@PR

3

55 57 52 54 56

TDI

58 39

41 45 47 40 42 46 48

1 7 13 19 25 31 37 49 59 2 8 14 20 26 32 38 50

60

F_XDP_PWRGD F_XDP_PLTRST# H_TAPPWRGOOD

H_ITPCLK_R H_ITPCLK#_R F_RSTOUT_XDP_N

@PR

RH45 249 Ohm

*

RH68 1K @PR

*

1 2

RH67

Dummy

@PR

RH50 1K

*

Remove RH51

-12/29/09

F_XDP_PLTRST#

Add RH69 to O_PWRBTN#IN and dummy RH48; follow CRB0.7-12/27/09

H_TCK 9 H_TDO 9 H_TRST# 9 H_TDI 9 H_TMS 9

H_PWRGD 9,24,64 H_CFG0 9

P_VR_READY 24,33,64,67

H_RESET#_R 9

Change net name to H_RESET#_R -12/28/09

FP_RST# 9,24,53

Remove RH58,RH59

-12/29/09

RH69 3.3K

*

@PR

RH48 1K

*

Dummy

Remove RH46 and option connection to H_TAPPWRGOOD; follow CRB0.7-12/27/09

Add RH68 to H_CFG0; follow CRB0.7-12/27/09

Pin 47 add RH67 to P_VR_READY; follow CRB

0.7-12/27/09

Dummy RH52,RH53; follow CRB 0.7-12/27/09

H_ITPCLK_R H_ITPCLK#_R

O_PWRBTN#IN 24,32,53,56

S_PLTRST# 9,24,32,34,46,53

RH52 0 Dummy

RH52 0 Dummy RH53 0 Dummy

RH53 0 Dummy RH54 0 @PR

RH54 0 @PR RH55 0 @PR

RH55 0 @PR

2

*

* *

*

20100226: Change clock source form PCH

+1P05V_VCCIO

*

RH47

1.5K

Dummy

F_XDP_PWRGD

F_XDP_PLTRST#

H_TAPPWRGOOD

20091209: CRB0.7 empty RH47 and RH45 use 249 ohm

Add RH70 to +1P05V_VCCIO; follow CRB0.7-12/27/09

Dummy

H_ITPCLK 9 H_ITPCLK# 9

C_PCH_ITP 27 C_PCH_ITP# 27

RH49

3.3K

Dummy

*

RH70

RH70 0

0

Dummy

1

XDP Connector - PCH

20091230:TP8,TP9 change to Test Point; 20091230:Add pull-up to

follow CRB 0.7 +1P05V_PCH; follow CRB 0.7

@PR

RS200 0

+1P05V_PCH

B B

20091231: Add RS35 pull-up to +1P05_PCH; CRB 0.7

F_PCH_JTAG_RST#

20091221: Rename F_PCH_JTAG_RST#_NC to F_PCH_JTAG_RST#_R

A A

F_PCH_FILTER_TCK

RS200 0

C_SRC1_PCH27 C_SRC1_PCH#27

S_SMBDATA_MAIN15,16,17,18,32

S_SMBCLK_MAIN15,16,17,18,32

+1P05V_PCH

F_PCH_JTAG_TDO24

F_PCH_JTAG_TDI24

F_PCH_JTAG_TMS24

RS187 0

Dummy

TPS120TPS120 TPS121TPS121

FP_RST#9,24,53

RS208 0

Dummy

5

*

RS35 51 Ohm

TPS133TPS133 TPS134TPS134 TPS135TPS135 TPS136TPS136 TPS137TPS137 TPS138TPS138 TPS139TPS139 TPS140TPS140 TPS141TPS141 TPS142TPS142

F_SINAI_JTAG_VREF

F_TP_XDP_PWRGD F_TP_XDP_RST

*

@PR

F_PCH_FILTER_TCK F_PCH_JTAG_RST#_R

US2

1

NC

2

A

3

GND

SN74LVC1G17DCKR

Dummy

TP_0 TP_1 TP_2 TP_3 TP_4 TP_5 TP_6 TP_7 TP_8 TP_9

RS186 0

For debugging

XDP_PCH

10

TP_0

12

TP_1

16

TP_2

18

TP_3

28

TP_4

30

TP_5

34

TP_6

36

TP_7

4

TP_8

6

TP_9

40

XDP_H_CLK_DP

42

XDP_H_CLK_DN

45

100M_CLK_DP

47

100M_CLK_DN

51

SDA

53

SCL

39

PWRGOOD

46

RESET#

48

DBR#

41

TESTINB

52

TDO

56

TDI

58

TMS

57

TCK

54

TRST#

21

NC_1

22

NC_2

23

NC_3

24

NC_4

55

NC_5

XDP

*

@PR

+3V

5

VCC

4

RS190 140Ohm

Y

BPM1_0/TP_13# BPM1_1/TP_12# BPM1_2/TP_11# BPM1_3/TP_10#

BPM2_0#/TP_17 BPM2_1#/TP_16 BPM2_2#/TP_15 BPM2_3#/TP_14

XDP_PRESENT#

+/-1%Dummy

BPM1_4# BPM1_5#

PROC_VTT_1 PROC_VTT_2

GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17

@PR

RS191

*

0

Dummy

4

GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9

17 15 11 9 5 3

35 33 29 27

60 43

44 1

2 7 8 13 14 19 20 25 26 31 32 37 38 49 50 59

CS69

0.1uF

*

16V, X7R, +/-10%

Dummy

20091230: Remove all USB OC connection; follow CRB 0.7

@PR

RS172 0

*

20091230: change to 0ohm pull-up to +3_DSW

20100105: Mount RS175 and change to 20100709: Reserve RS207 for

0ohm; CRB 0.7 S_RSMRST# connect to

20100712: Removed RS207 and

F_TP_XDP_RST S_RSMRST#

F_PCH_JTAG_TCK_FILTER 24

O_PWRBTN#IN24,32,53,56

S_PLTRST#9,24,32,34,46,53

S_RSMRST#24,64

RS175 0

*

RS176 1K

*

@PR

RS207 1K

*

3

+3V_S5

Dummy

F_TP_XDP_PWRGD

F_TP_XDP_RST

20091221: updated JTAG stuffing table

20091231: RS188 cahnge to 1k and pullup to +3V_DSW; CRB 0.7

@PR

RS188 1K

*

RS189 1K

*

RS192

RS192 0

0

Dummy

* *

*

Dummy

+3V_S5

PWRGD_3V 24,32

2

20091221: RS184 change to 20k ; Stuff-up RS177, RS178, RS185 follow JTAG Enable option.

+3V_S5

20100503: RS177, RS179, RS181 pull-up change to +3V_S5, follow CRB1.0

@PR

RS177 200Ohm +/-5%

@PR

RS179 200Ohm +/-5%

@PR

RS181 200Ohm +/-5%

+3V_S5

@PR

RS184 20K

*

* *

*

+/-1%

Title

DWG NO Rev

Date: Sheet of

F_PCH_JTAG_TDO F_PCH_JTAG_TDI F_PCH_JTAG_TMS F_PCH_FILTER_TCK

F_PCH_JTAG_RST#

@PR

RS178 100 Ohm +/-1%

@PR

RS180 100 Ohm +/-1%

@PR

RS182 100 Ohm +/-1%

@PR

RS183 51 Ohm+/-5%

RS183 51 Ohm+/-5% RS185 10K +/-1%

RS185 10K +/-1%

F_PCH_JTAG_RST# 24

XDP

Lanikai _MT/DT

*

* *

*

1

CLOSE TO PCH

52 71Wednesday, June 13, 2012

A00

5

4

3

2

1

Reset BottomPower Bottom

+3V_DUAL

RO99

*

@PR

D D

20091216: Signal name change to O_PWRBTN#IN

O_PWRBTN#IN24,32,52,56

RO100 0

*

@PR

20101118: Dummy RO101

@PR

1K

+/-5%

@PR

@PR PWR_SWH

RO101 100

*

+/-5%

For debugging

@PR

PWR_SWH

SYS_PWRBT#

56

1 3

2 4

CONN-Switch

@PR

RO102 100 Ohm

*

FP_RST#9,24,52

20101118: Dummy RO102, CO49 20101118: Stuffed RO102, CO49

*

+/-1%

@PR

CO49

*

470pF

For debugging

@PR

RST_SWH

56

2

1

4

3

CONN-Switch

LPC DEBUG

C C

+5V

RF25 0

*

@PR

RF26 0

*

@PR

20101118: Dummy RF25, RF26

20100512: change RS12, RS16 to 1k

K_GNT#1

@PR

RS19 8.2K +/-5%

*

F_LPC_DEBUG

S_INIT3_3VB 23

K_GNT#1 21

3

5

2

CS1

1uF

+/-10%

@PR

*

16

+3V

@PR

RS12

RS12 1K

1K

+/-5%

QS1

QS1 MMDT5551

MMDT5551

@PR

4

For debugging

@PR

20101118: Dummy RF24

@PR

RF24 0

*

C_LPC27

S_PLTRST#9,24,32,34,46,52

F_LAD024,32,46 F_LAD124,32,46 F_LAD224,32,46 F_LAD324,32,46

F_FRAME#24,32,46

B B

+3V

Dummy

CF14

*

0.1uF

16V, X7R, +/-10%

S_SATA1GP21,23

+5V

A A

Dummy

CF13

*

0.1uF

16V, X7R, +/-10%

*

+/-5%

@PR

CF15

*

22pF

50V, NPO, +/-5%

20100909: Dummy CF15 20101118: Dummy CF16 20101118: Stuffed CF16

F_LPC_DEBUG

20100512: change RS12, RS16 to 1k

5

@PR

LPC_DEBUG

1 2 3 5 6 7 8 9

X

11 13

Header_2X7_K10

@PR

CF16

CF16 10nF

10nF

25V, X7R, +/-10%

@PR

RS11 8.2K +/-5%

S_SATA1GP

@PR

RS16 1K

*

+/-5%

4

12 14

*

4 3

*

APS Connector

+3V_S5+3V_DUAL

RF34 0 @PR

*

RF33 0 @PR

*

RF36 0 @PR

*

S_SLP_S4#24,32,65,71 S_RTCRST#24,29,31

O_PWRBTN#IN24,32,52,56

FP_RST#9,24,52

*

RF38 0 @PR

*

RF39 0 @PR

*

RF40 0 @PR

*

2

@PR

METS

1 2 3 5 6 7 8

9 11 13

RF32 0 @PR

*

4

RF35 0 @PR

*

RF37 0 @PR

*

10 12 14

Header_2X7

Title

Pilot Run Conn

DWG NO Rev

Date: Sheet of

Pilot Run Conn

Lanikai _MT/DT

1

+3V_S5

S_SLP_S3# 24,32,64,66,70,71 S_SLP_M# 24,32,65,66

A00

53 71Wednesday, June 13, 2012

Dummy

IMPEDANCE_1

1 2

Header_1X2

5

+5V

Dummy

IMPEDANCE_2

1 2

Header_1X2

Dummy

FD1

FD1 FMARK

FMARK

FD40

4

Dummy

FD2

FD2 FMARK

FMARK

FD40

1

Dummy

FD3

FD3 FMARK

FMARK

FD40

1

Dummy

FD4

FD4 FMARK

FMARK

FD40

1

3

2

1

Dummy

IMPEDANCE_5

1 2

Header_1X2

4 3 2

mh40x80_8_dell

+5V

MH2

MH2 Mounting Hole

Mounting Hole

6

7 8 9

Dummy

IMPEDANCE_3

D D

C C

1 2

DIFF_5/5+ DIFF_5/5-

MH1

MH1 Mounting Hole

Mounting Hole

7 8 9

mh40x80_8_dell

Header_1X2

5

6

1

20100108: Add for EMI

+1P05V_VCCIO +1P05V_VCCIO +1P05V_VCCIO

CP222

*

0.1uF

16V, X7R, +/-10%

+3V

B B

CP229

*

0.1uF

16V, X7R, +/-10%

5

1

A_GND

Dummy

IMPEDANCE_4

1 2

Header_1X2

4 3 2

mh40x80_8_dell

*

CP230

*

0.1uF

16V, X7R, +/-10%

Dummy

IMPEDANCE_6

1 2

Header_1X2

MH3

MH3 Mounting Hole

Mounting Hole

5

6

7 8 9

1

CP224

0.1uF

16V, X7R, +/-10%

4 3 2

mh40x80_8_dell

CP225

*

0.1uF

16V, X7R, +/-10%

+5V

CP231

*

0.1uF

16V, X7R, +/-10%

+3V

MH4

MH4 Mounting Hole

Mounting Hole

5

6

7 8 9

1

Dummy

FD5

FD5 FMARK

FMARK

FD40

4 3 2

mh40x80_8_dell

+5V

CP232

*

0.1uF

16V, X7R, +/-10%

+3V

1

MH5

MH5 Mounting Hole

Mounting Hole

5

6

7 8 9

1

Dummy

FD6

FD6 FMARK

FMARK

FD40

4 3 2

mh40x80_8_dell

1

MH6

MH6 Mounting Hole

Mounting Hole

7 8 9

Dummy

FD7

FD7 FMARK

FMARK

FD40

6

A_GND

5

1

Dummy

FD8

FD8 FMARK

FMARK

FD40

1

4 3 2

mh40x80_8_dell

+5V

*

1

MH7

MH7 Mounting Hole

Mounting Hole

5

6

7 8 9

1

CP228

0.1uF

16V, X7R, +/-10%

Dummy

FD9

FD9 FMARK

FMARK

FD40

4 3 2

mh40x80_8_dell

Dummy

FD10

FD10 FMARK

FMARK

FD40

1

MH8

MH8 Mounting Hole

Mounting Hole

5

6

7 8 9

1

Dummy

FD11

FD11 FMARK

FMARK

FD40

1

4 3 2

*

CP237

*

0.1uF

16V, X7R, +/-10%

+12V

+3V +3V

CP233

*

0.1uF

16V, X7R, +/-10%

Dummy

FD12

FD12 FMARK

FMARK

FD40

1

CP287

0.1uF

16V, X7R, +/-10%

Dummy

1

+5V+1P05V_PCH +1P05V_PCH +1P05V_PCH

CP284

*

+3V+3V

CP236

*

0.1uF

16V, X7R, +/-10%

CP235

*

0.1uF

16V, X7R, +/-10%

CP284

0.1uF

16V, X7R, +/-10%

Dummy

+5V

CP238

*

0.1uF

16V, X7R, +/-10%

+3V

+3V +5V +1P05V_PCH

CP240

*

0.1uF

16V, X7R, +/-10%

CP283

*

0.1uF

16V, X7R, +/-10%

Dummy

CP288

*

0.1uF

16V, X7R, +/-10%

Dummy

CP247

*

0.1uF

16V, X7R, +/-10%

+3V_S5

+1P05V_VCCIO +3V

CP289

*

0.1uF

16V, X7R, +/-10%

Dummy

+3V

CP242

*

0.1uF

16V, X7R, +/-10%

+1P05V_PCH

+1P05V_ME

CP251

*

0.1uF

16V, X7R, +/-10%

*

+12V

CP249

*

0.1uF

16V, X7R, +/-10%

CP239

0.1uF

16V, X7R, +/-10%

Dummy

+12V+1P05V_PCH+12V+1P05V_PCH+1P05V_PCH

CP250

CP255

CP276

CP291

*

+5V_DUAL_USBKB+12V+5V_DUAL_USBKB+5V_DUAL_USBKB

CP246

CP285

*

0.1uF

16V, X7R, +/-10%

A A

5

4

CP268

*

0.1uF

16V, X7R, +/-10%

+3V_S5

*

3

CP246

0.1uF

16V, X7R, +/-10%

CP244

*

0.1uF

16V, X7R, +/-10%

*

0.1uF

16V, X7R, +/-10%

2

CP276

*

0.1uF

16V, X7R, +/-10%

+3V

Date: Sheet

Date: Sheet of

CP255

*

0.1uF

16V, X7R, +/-10%

Dummy

Title

DWG NO Rev

Lanikai _MT/DT

*

EMI

CP250

0.1uF

16V, X7R, +/-10%

Dummy

1

CP248

*

0.1uF

16V, X7R, +/-10%

54 71Wednesday, June 13, 2012

A00

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5

D D

Move PWR_SW conn to page56 20091126

C C

4

3

2

1

Serial Port 2 Header

+3V

RO95

RO94

RO93

*

Dummy

RO93

*

2.2K

+/-5%

*

2.2K

+/-5%

CO22

10pF

Dummy

50V, NPO, +/-5%

B B

A A

O_DCD2#_R32 O_DSR2#_R32 O_RXD2_R32

O_TXD2_R32,33 O_CTS2#_R32

5

RO33 0 +/-5%

RO97

RO96

*

2.2K

+/-5%

2.2K

+/-5%

O_DCD2#_R O_DSR2#_R O_RXD2_R O_CTS2#_R O_RI2#_R

Dummy Serial Port2 header from X01

4

O_RI2#_R 32

+5V+12V -12V

CO46

CO44

*

0.1uF

16V, X7R, +/-10%

Dummy

3

CO45

*

0.1uF

16V, X7R, +/-10%

Dummy

CO46

*

0.1uF

16V, X7R, +/-10%

Dummy

Title

COM2 HDR

DWG NO Rev

Date: Sheet of

2

Date: Sheet

COM2 HDR

Lanikai _MT/DT

1

A00

of

55 71Wednesday, June 13, 2012

5

Front USB/LED Header

D D

Pitch 2.0mm

+3V

RNO2

642

8.2KOhm

+/-5%

135

7 8

*

O_FIO_SATA_LED# T_SATALED# OQ14_C S_FP_CHAS_DET#

4

20110212 Change to 2x13 for Front USB x2 port.

3

U_USB_OC_R_#522

20110212 Change to 2x13 for Front USB x2 port.

CU14

0.1uF

25V, X7R, +/-10%

2

+5V_DUAL_USBKB

RU29

*

0

+/-5%

Dummy

RU31 10K +/-1%

*

1

RU33

2

RU33 15K

15K

+/-1%

*

+5V_DUAL_USBKB

*

12

FU6

FU6 Fuse 2A

Fuse 2A

*

1

ECU6

470uF

6.3V, +/-20%

USBPWR7_F_50

CU15

*

0.1uF

16V, X7R, +/-10%

MT/DT CHASSIS

FP_CHAS_DET#

0MT

MT/DT

DT1

U_USB11P_RU_USB11N_R

U_USB10N_R U_USB10P_R

U_USB11N_R U_USB11P_R

USBPWR7_F_50

U_USB10P 22 U_USB10N 22

U_USB11N 22 U_USB11P 22

O_PWRBTN#IN24,32,52,53

4

CU16

*

0.1uF

16V, X7R, +/-10%

A_MIC1_L_L37

A_JD_MIC137

A_FRONT_L_L37

USBPWR7_F_50

O_FIO_SATA_LED#

U_USB10N_R U_USB10P_R

FRONTPANEL

1

3

5

7

9

11

13

15

17

Header_2X10_K19

2

4

6

8

10

12

14

16

18

20

POWER SWITCH Header

+5VSB +5VSB

*

RO34

499

+/-1%

PWR_SW

RO67 100 +/-5%

*

O_GREEN#32

*

1 2 3

X

Header_2X3_K5

4 6

CU17

*

0.1uF

16V, X7R, +/-10%

U_USB11N_R U_USB11P_R

RO37

*

499

+/-1%

3

A_MIC1_R_L 37 A_JD_FRONT 37 A_FRONT_R_L 37 A_FP_PRES# 23

USBPWR7_F_50

S_FP_CHAS_DET# 23

O_FP_CBL_DET# 32 O_YELLOW# 32

+5V

*

O_FP_CBL_DET#

O_GREEN#

O_YELLOW#

O_PWRBTN#IN

CO27

470pF

CO50

0.1uF

16V, X7R, +/-10%

CO54

*

470pF

50V, X7R, +/-10%

Dummy

2

+3V_DUAL

*

Dummy

50V, X7R, +/-10%

RO70

8.2K

+/-5%

CO52

470pF

RO71 1K

*

T_SATALED#23

CA40

*

0.1uF

16V, X7R, +/-10%Dummy

O_FIO_SATA_LED#

Intel

*

50V, X7R, +/-10%

Intel

Title

DWG NO Rev

Date: Sheet

Date: Sheet of

*

QO10

MMDT5551

OQ14_C

A_FP_PRES# 23

CO53

470pF

Dummy

50V, X7R, +/-10%

Front_Panel

Lanikai _MT/DT

2

5

1

O_FIO_SATA_LED#

4 3

+5VSB

CO26

*

0.1uF

16V, X7R, +/-10%

56 71Wednesday, June 13, 2012

A00

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16

*

RU38 0 Dummy

*

U_USB10N22

C C

B B

U_USB10P_R U_USB10N_R

A A

U_USB11N_R U_USB11P_R

U_USB10P22

U_USB11N22

U_USB11P22

UU5

1 6 2

U_USB10N_R U_USB10P_R

3

IP4220CZ6

LU11

1 2 3

Common Choke 90 Ohm

LU12

2 3 1

Common Choke 90 Ohm

5

*

RU39 0 Dummy

*

RU41 0 Dummy

*

RU42 0 Dummy

*

5 4

4

5

+3V_DUAL

RU34

*

10K

+/-1%

U_USB_OC_R_#022

D D

+/-1%

3

2

1

BAT54A

BAT54A DU2

DU2

CU19

0.1uF

25V, X7R, +/-10%

*

Front USB/LED Header

RU54

*

2KOhm

RU58

+/-1%

3.01K

+/-1%

4

+5V_DUAL_USBKB

*

12

FU7

FU7 Fuse 2A

Fuse 2A

*

+5V_DUAL_USBKB

ECU7

470uF

6.3V, +/-20%

USBPWR1_F_50

CU20

*

0.1uF

16V, X7R, +/-10%

+5VSB

*

CO51

0.1uF

16V, X7R, +/-10%

3

S_USB_HDR_DET#23

+3V

2

*

RU87

8.2K

+/-5%

USB3_RX2_ESD_DN USB3_RX2_ESD_DP

USB3_TX2_ESD_DN USB3_TX2_ESD_DP

U_USB1N_R U_USB1P_R

USBPWR2_F_50USBPWR1_F_50

FRONT_USB

1

19

2

18

3

17

4

16

5

156 7 14 8

13 9

12

10

11

PUB200-2017-B5-10-HF

1

USB3_RX1_ESD_DN USB3_RX1_ESD_DP

USB3_TX1_ESD_DN USB3_TX1_ESD_DP

U_USB0N_R U_USB0P_R

ECU10

470uF

6.3V, +/-20%

USBPWR2_F_50

CU24

*

0.1uF

16V, X7R, +/-10%

UU12

9 8

GND

3 7

ESD3V3U4ULC

UU10

9 8

GND

3 7

ESD3V3U4ULC

1

I/O

2

I/O

4

I/O

56

I/O

1

I/O

2

I/O

4

I/O

56

I/O

USB3_RX2_ESD_DPUSB3_RX2_ESD_DP

USB3_RX1_ESD_DPUSB3_RX1_ESD_DP

USB3_TX1_ESD_DN USB3_TX1_ESD_DP

RU56 0

*

Common Choke 67 Ohm

*

USB3_TX2_PCH_DN28 USB3_TX2_PCH_DP28

CO780.1uF*CO780.1uF

*

CO810.1uF*CO810.1uF

USB3_TX2_PCH_DP_C USB3_TX2_ESD_DP

Common Choke 67 Ohm

2

Dummy

RU60 0

LU20

*

43 1

USB3_TX2_ESD_DNUSB3_TX2_PCH_DN_C

*

RU820*RU820

Common Choke 67 Ohm

USB3_RX2_PCH_DP28

USB3_RX2_PCH_DN28

*

USB3_TX1_PCH_DN28

USB3_TX1_PCH_DP28

CO830.1uF*CO830.1uF

*

CO800.1uF*CO800.1uF

USB3_TX1_PCH_DN_C USB3_TX1_ESD_DN

Common Choke 67 Ohm

2

Dummy

Common Choke 67 Ohm

4 3 1

Dummy

LU21

*

RU810*RU810

RU61 0

*

LU18

RU62 0

*

43 1

2

USB3_RX2_ESD_DP USB3_RX2_ESD_DN

USB3_TX1_ESD_DPUSB3_TX1_PCH_DP_C

*

RU570*RU570

Common Choke 67 Ohm

USB3_RX1_PCH_DN28

USB3_RX1_PCH_DP28

4 3 1

Dummy

LU17

*

RU530*RU530

2

USB3_RX1_ESD_DN USB3_RX1_ESD_DP

FU10

FU10 Fuse 2A

Fuse 2A

*

RU67

*

RU66

23 1

RU66

*

3.01K

+/-1%

U_USB1P_R U_USB1N_R

U_USB1P_R

U_USB0N_R

U_USB0N_R U_USB0P_R

CU23

*

C C

U_USB1P22 U_USB1N22

U_USB0N22 U_USB0P22

B B

U_USB1N_R

U_USB0P_R

25V, X7R, +/-10%

LU13

2 3 1

Common Choke 90 Ohm

RU51 0

RU51 0 RU52 0

RU52 0

4

RU55 0 Dummy

RU55 0 Dummy RU59 0 Dummy

RU59 0 Dummy

UU13

1 6 2 3

IP4220CZ6

*

0.1uF

4

*

Dummy

*

Dummy

LU19

Common Choke 90 Ohm

*

* *

*

5 4

1 2

2KOhm

+/-1%

USBPWR1_F_50

*

USB3_RX2_ESD_DN USB3_RX2_ESD_DN

USB3_RX1_ESD_DN USB3_RX1_ESD_DN

USB3_TX2_ESD_DP USB3_TX2_ESD_DP USB3_TX2_ESD_DN USB3_TX2_ESD_DN

USB3_TX1_ESD_DN USB3_TX1_ESD_DP

A A

Intel

Title

TBD

DWG NO Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

TBD

Lanikai _MT/DT

1

A00

of

57 71Wednesday, June 13, 2012

5

IRQ: CDAB IDSEL: AD18 REQ/GNT: 0

D D

K_INTD#21 K_INTB#21

C_PCI_SL127

K_REQ#021

C C

K_IRDY#21

K_DEVSEL#21

K_LOCK#21 K_PERR#21

K_SERR#21

B B

+5V

K_AD31 K_AD29

K_AD27 K_AD25

K_C/BE#3 K_AD23

K_AD21 K_AD19

K_AD17 K_C/BE#2

K_IRDY# K_DEVSEL# K_LOCK#

K_PERR# K_SERR# K_C/BE#1

K_AD14 K_AD12

K_AD10

K_AD8 K_AD7

K_AD5 K_AD3

K_AD1

RK2 2.7KRK2 2.7K

4

+5V

K_TCK

-12V

B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49

B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62

B1 B2 B3 B4 B5 B6 B7 B8 B9

SLOT3

-12V TCK GND1 TDO +5V1 +5V3 INTB# INTD# PRSNT1# RSV2 PRSNT2# GND2 GND4 RSV4 GND6 CLK GND7 REQ# +5V7 AD(31) AD(29) GND9 AD(27) AD(25) +3.3V2 C/BE#(3) AD(23) GND11 AD(21) AD(19) +3.3V4 AD(17) C/BE#(2) GND13 IRDY# +3.3V6 DEVSEL# GND16 LOCK# PERR# +3.3V8 SERR# +3.3V9 C/BE#(1) AD(14) GND18 AD(12) AD(10) GND20

AD(8) AD(7) +3.3V12 AD(5) AD(3) GND22 AD(1) +5V8 ACK64# +5V10 +5V12

Slot-PCI

TRST#

+12V

TMS

+5V2 INTA# INTC#

+5V4 RSV1

+5V5 RSV3 GND3 GND5

SB3V

RESET#

+5V6 GNT# GND8

PCI_PME#

AD(30) +3.3V1 AD(28) AD(26) GND10 AD(24)

IDSEL

+3.3V3 AD(22) AD(20) GND12 AD(18) AD(16) +3.3V5

FRAME#

GND14 TRDY# GND15 STOP# +3.3V7

SDONE

SBO#

GND17

PAR

AD(15)

+3.3V10

AD(13) AD(11) GND19

AD(9)

C/BE#(0)

+3.3V11

AD(6) AD(4)

GND21

AD(2) AD(0)

+5V9

REQ64#

+5V11 +5V13

TDI

+3V

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62

3

K_TRST K_TMS

K_TDI

+12V

+5V

+3V

RK1 330

*

+3V_PCIAUX

+/-1%

RK4 0 Dummy

RK4 0 Dummy RK5 0 Dummy

RK5 0 Dummy

RK3 2.7KRK3 2.7K

K_AD30 K_AD28

K_AD26 K_AD24

K_AD18 K_AD22

K_AD20 K_AD18

K_AD16

*

K_AD15 K_AD13

K_AD11 K_AD9

K_C/BE#0 K_AD6

K_AD4 K_AD2

K_AD0

2

+5V

For pci slot used

RNK3

*

4.7K Ohm

+/-5%

Moved from PCH section-12/30/09

Dummy

K_INTC# 21 K_INTA# 21

K_PCIRST#_SLOT 21

K_GNT#0 21

K_PME# 21

K_FRAME# 21 K_TRDY# 21 K_STOP# 21 S_SMBCLK_PCI 24,32,38,39,59

S_SMBDATA_PCI 24,32,38,39,59 K_PAR 21

+5V

1 3 5 7 8

1

K_TDI

2

K_TMS

4

K_TCK

6

K_TRST

K_AD[31..0] 21 K_C/BE#[3..0] 21

+5V

ECK1

12

470uF

*

A A

+3V

*

5

6.3V, +/-20%

ECK3

470uF

6.3V, +/-20%

*

Dummy for Cost down-11/23/09

CK1

ECK2

120uF

16V, +/-20%

Dummy

CK5

0.1uF

16V, X7R, +/-10%

CK1

0.1uF

*

16V, X7R, +/-10%

Dummy

CK6

0.1uF

*

16V, X7R, +/-10%

CK2

0.1uF

*

16V, X7R, +/-10%

Dummy

CK7

0.1uF

*

16V, X7R, +/-10%

CK4

CK3

0.1uF

*

16V, X7R, +/-10%

Dummy

+12V

CK8

*

0.1uF

25V, X7R, +/-10%

4

CK4

0.1uF

*

16V, X7R, +/-10%

Dummy

12

*

ECK4

120uF

16V, +/-20%

CK9

0.1uF

25V, X7R, +/-10%

-12V

*

3

+3V_PCIAUX

CK10

0.1uF

*

16V, X7R, +/-10%

Title

Slot3: PCI

DWG NO Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Slot3: PCI

Lanikai _MT/DT

1

A00

of

58 71Wednesday, June 13, 2012

5

D D

RX6 0 Dummy

S_SMBCLK_PCI24,32,38,39,58

S_SMBDATA_PCI24,32,38,39,58

C C

X_2X1_TXN22

RX6 0 Dummy RX5 0 Dummy

RX5 0 Dummy

CX51 0.1uF 16V, X7R, +/-10%

CX51 0.1uF 16V, X7R, +/-10% CX52 0.1uF 16V, X7R, +/-10%

CX52 0.1uF 16V, X7R, +/-10%

4

+3V_PCIAUX

*

X1_WAKE#24

*

+3V

X1_TCLK

X_2X1_TXP_C X_2X1_TXN_C

+12V +12V

SLOT2

B1

+12V#B1

B2

+12V#B2

B3

RSVD#B3

B4

GND#B4

B5

SMCLK

B6

SMDAT

B7

GND#B7

B8

+3.3V#B8

B9

JTAG1

B10

3.3Vaux

B11

WAKE#

B12

RSVD#B12

B13

GND#B13

B14

PETp0

B15

PETn0

B16

GND#B16

B17

PRSNT2#B17

B18

GND#B18

Slot-PCIE-1X

3

Mechanical Key

PRSNT1#

+12V#A2 +12V#A3 GND#A4

JTAG2 JATG3 JATG4 JATG5

+3.3V#A9

+3.3V#A10

PERST#

GND#A12 REFCLK+

REFCLK-

GND#A15

PERp0 PERn0

GND#A18

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

+3V

X1_TRST X1_TDI

RX7 0 Dummy

*

2

+3V

RX17 4.7K +/-5%

*

RX18 4.7K +/-5%

*

RX19 4.7K +/-5%

*

Dummy

Dummy Dummy

Dummy

20100111: Remove net X_WIRELESS_LED#

GPO_WLOM 22

X_PLTRST_PCIE_SLOT# 32,38,39

C_PCIEX1_2 27 C_PCIEX1#_2 27X_2X1_TXP22

X_2X1_RXP 22 X_2X1_RXN 22

X1_TDI X1_TRST X1_TCLK

1

+3V +3V_PCIAUX

CX53

B B

CX53

0.1uF

*

16V, X7R, +/-10%

Dummy

CX54

0.1uF

*

16V, X7R, +/-10%

Dummy

CX55

0.1uF

*

16V, X7R, +/-10%

Dummy

Dummy for Cost down-11/23/09

A A

Title

Slot2: PCIe 1x

DWG NO Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

Slot2: PCIe 1x

Lanikai _MT/DT

1

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5

D D

C C

4

3

2

1

B B

SATA port 3 only for MT

SATA3

CT13 10nF 25V, X7R, +/-10%

T_SATA_TXP323 T_SATA_TXN323

A A

5

T_SATA_RXN323

T_SATA_RXP323

4

CT13 10nF 25V, X7R, +/-10%

@MT

*

CT14 10nF 25V, X7R, +/-10%

@MT

*

CT15 10nF 25V, X7R, +/-10%

@MT

*

CT16 10nF 25V, X7R, +/-10%

@MT

*

T_SATA_TXP3_C T_SATA_TXN3_C

T_SATA_RXN3_C T_SATA_RXP3_C

3

2

TX+

3

TX-

5

RX-

6

RX+

1

GND

4

GND#4

7

GND#7

CONN-SATA

@MT

NC#8

NC#9

8

9

Title

SATA_MT

DWG NO Rev

Date: Sheet of

2

Date: Sheet

SATA_MT

Lanikai _MT/DT

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60 71Wednesday, June 13, 2012

5

4

3

2

1

FLEXBAY

D D

+5V_DUAL_USBKB

*

12

FU4

FU4 Fuse 2A

Fuse 2A

RU19 10K +/-1%

*

C C

U_USB_OC_R_#622

CU10

*

0.1uF

25V, X7R, +/-10%

RU21 0 +/-5%

U_USB12N22

U_USB12P22

RU21 0 +/-5% RU23 0 +/-5%

RU23 0 +/-5%

1

2

*

RU20

RU20 15K

15K

+/-1%

INT_USB

1 2

U_USB12N_R U_USB12P_R U_USB13P_R

3 5 7

X

Header_2X5_K9

Pitch 2.54mm

4 6 8 10

U_USB13N_R

*

USBPWR8_F_50

CU11

ECU4

470uF

6.3V, +/-20%

CU11

*

0.1uF

16V, X7R, +/-10%

RU22 0 +/-5% Dummy

*

RU24 0 +/-5% Dummy

*

U_USB13N 22 U_USB13P 22

S_FLEXBAY_HDR_CBL_DET# 24,27

B B

Dummy

LU7

U_USB12N_R U_USB12P_R

UU4

U_USB13N_R

U_USB12P_R

A A

5

1 6 2 3

IP4220CZ6

U_USB13P_R

5 4

USBPWR8_F_50

U_USB12N_R

stuff on 20100723-EMC request

4

U_USB13N_R U_USB13P_R

CO-LAY with 4 Serial resistors RU21, RU22, RU23, & RU24

1 2 3

Common Choke 90 Ohm

LU8

1 2 3

Common Choke 90 Ohm

3

4

U_USB12N 22 U_USB12P 22

U_USB13N 22 U_USB13P 22

Intel

Title

Flexbay USB_MT

DWG NO Rev

Date: Sheet of

2

Date: Sheet

Flexbay USB_MT

Lanikai _MT/DT

1

A00

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61 71Wednesday, June 13, 2012

5

D D

C C

4

3

2

1

B B

A A

Title

PRT Port

DWG NO Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

PRT Port

Lanikai _MT/DT

1

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62 71Wednesday, June 13, 2012

5

4

3

2

1

ATX POWER CONNECTOR

+5V

CP7

*

0.1uF

16V, X7R, +/-10%

Dummy

+3V

13

+3.3V3

14

-12V

15

GND4

16

PSON

17

GND5

18

GND6

19

GND7

20

RSVD

21

+5V3

22

+5V4

23

+5V5

24

GND8

CP8

*

0.1uF

16V, X7R, +/-10%

Dummy

POWER

+3.3V1 +3.3V2

GND1

+5V1

GND2

+5V2

GND3

PWR0K

+5V_AUX

+12V_1 +12V_2

+3.3V4

Header_2x12

*

1 2 3 4 5 6 7 8 9 10 11 12

ECP1

470uF

6.3V, +/-20%

+3V

CP9

*

0.1uF

16V, X7R, +/-10%

Dummy

CP10

*

0.1uF

16V, X7R, +/-10%

Dummy

+5VSB+3V

@PR

*

RP4

RP4 330

330

+/-1%

AC

AUX_PWR

AUX_PWR LED_Yellow

LED_Yellow

@PR

+5VSB

CP11

*

0.1uF

16V, X7R, +/-10%

Dummy

+5V

*

RP1

1K

+/-1%

CP1

*

0.1uF

16V, X7R, +/-10%

Dummy

B_ATX_PWROK 32,71

+3V

ECP2

*

470uF

6.3V, +/-20%

*

ECP3

470uF

6.3V, +/-20%

*

ECP4

470uF

6.3V, +/-20%

+12V+5V

-12V

D D

O_PSON#32

C C

-12V +12V

CP5

CP4

*

0.1uF

25V, X7R, +/-10%

Dummy

CP5

*

0.1uF

25V, X7R, +/-10%

Dummy

+5VSB

*

CP6

*

0.1uF

25V, X7R, +/-10%

Dummy

RP3

4.7K

+/-5%

CP3

0.1uF

16V, X7R, +/-10%

Dummy

+5V

B B

A A

Title

Power Conn

DWG NO Rev

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

Power Conn

Lanikai _MT/DT

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63 71Wednesday, June 13, 2012

5

For Deep Sleep

D D

*

RP685

RP685 1K

1K

QP96

QP96 MMBT3904-7-F

MMBT3904-7-F

E C

RP682

RP682 10K

10K

*

S_SUSWARN#24

+5VSB +5V_DUAL

B

*

C C

S_SLP_SUS#24,65

RP687

4.7K

*

RP683

5.6K

+/-1%

4

+5VSB

*

RP680

RP680 1K

1K

SUS_WARN_5VDUAL

4 3

5

SLP_SUS_R

G

3

+5VSB

*

RP669

RP669 10K

10K

RP674

*

10K

*

RP684

RP684 10K

10K

4 3

CP524

*

0.1uF

Dummy

16V, Y5V, +80%/-20%

*

RP681

RP681 10K

10K

16

2

MMDT5551

MMDT5551 QP99

QP99

QP76

DS

2N7002

+5VSB

*

S_RSMRST#_R

RP678

RP678 10K

10K

SUS_ACK_CTRL

RP673

RP673 10K

10K

RP679

RP679 1K

1K

+/-1%

Dummy

*

RP677

RP677 10K

10K

Dummy

16

2

MMDT5551

MMDT5551 QP100

QP100

5

+5VSB

*

S_SUSWARN#24

RP666

RP666 10K

10K

2

S_SUS_PWR_ACK# 24

CP522

RP675

*

0.1uF

20K

16V, Y5V, +80%/-20%

Dummy

*

RP695

0

Dummy

S_SUS_PWR_ACK# 24

1

RESUME RESET Logic

+5VSB +5VSB +5VSB +5VSB +5VSB

1

RP273

RP273 22K

22K

+/-5%

2

16

2

MMDT5551

MMDT5551 QP17

B B

+3V_S5

A A

S_RSMRST#_R

*

5

RP711

*

24.9KOhm

+/-1%

CP282

1uF

+/-10%

S_SLP_SUS#24,65

1 2

RP274

RP274 22K

22K

+/-5%

1

2

UP3

OE#

A

4 3

*

+3V_DUAL

VCC

GND

4

QP17

5

RP275

RP275 1M

1M

+/-5%

Dummy

CP269

*

0.1uF

16V, X7R, +/-10%

5

Y

SN74LVC1G17DCKR

3

*

4

RP290 33

RP276

RP276 1M

1M

+/-5%

Dummy

*

RP277

RP277 22K

22K

+/-5%

*

1

2

RP279

*

MMBT3906

10K

RP278

*

1M

+/-5%

Dummy

S_RSMRST# 24,52

RP280

RP280 0

0

B

QP18

CP529

1uF

+/-10%

*

EC

CP530

2.2uF

*

6.3V, Y5V, +80%/-20%

EC

*

1

2

RP282

RP282 22K

22K

+/-5%

RP281

RP281 18K

18K

+/-1%

3

B

QP20

QP20 MMBT3906

MMBT3906

RP283

*

10K

S_SLP_SUS#24,65

1

RP284

RP284 22K

22K

+/-5%

2

MMDT5551

QP27

1 2

RP285

RP285 22K

22K

+/-5%

*

RP289

*

RP289 10K

10K

RP288

4.7K

+/-5%

Dummy

16

2

4 3

5

1

RP286

RP286 15K

15K

+/-1%

2

VR_READY DEFENSIVE

S_SLP_S3#24,32,53,66,70,71

SLP_SUS_FET 65

S_RSMRST# 24,52

16

QP7

MMDT5551

*

H_PWRGD9,24,52

2

*

RP21

RP21 100 Ohm

100 Ohm

+/-1%

Dummy

*

RP16

RP16 10K

10K

16

QP6

MMDT5551

+3V_S5

*

RP19

RP19 10K

*

RP18

RP18 10K

10K

2

5

*

RP23

RP23 10K

10K

Title

DWG NO Rev

Date: Sheet

Date: Sheet of

10K

*

RP20

RP20 100 Ohm

100 Ohm

+/-1%

4 3

Power Sequence

Lanikai _MT/DT

*

2

4 3

5

*

RP17

RP17 10K

10K

P_VR_READY 24,33,52,67

1

CP12

1uF

+/-10%

Dummy

P_CORE_EN 67

64 71Wednesday, June 13, 2012

A00

of

5

+3V_EPW

*

RP27

RP27 10K

10K

RP676 10K

C A

SLP_SUS_FET

*

+/-1%

Dummy

DP10

BAT54HT1G

Dummy

FDN340P

+3V_S5

*

S_SLP_M#24,32,53,66

RP211

RP211 0

0

Dummy

+3V_EPW

S_SLP_SUS#24,64

D D

C C

+3V_S5

SLP_SUS_FET64

B B

+5V_S5

SLP_SUS_FET

FDN340P

A A

5

FDN340P

+3V_S5 +3V_S5

*

RP24

RP24 10K

10K

B

QP10

CP165

1uF

+/-10%

Dummy

+3V_DUAL

SD

+5VSB

SD

QP10 MMBT3904-7-F

MMBT3904-7-F

E C

G

QP53

FDN340P

Dummy

G

+5VSB

SD

RP262

RP262 0

0

Dummy

+5V_S5

*

QP50

QP61

CP18

1uF

+/-10%

Dummy

*

G

*

RP667

RP667 10K

10K

SLP_SUS_FET_R SLP_SUS_FET

DS

Dummy

CP120

4.7uF

Dummy

6.3V, X5R, +/-10%

CP16

1uF

+/-10%

Dummy

QP95

QP95 2N7002

2N7002

RP178

RP178 0

0

Dummy

*

4

SD

G

*

+3V_S5

CP157

4.7uF

*

Dummy

6.3V, X5R, +/-10%

CP146

4.7uF

Dummy

6.3V, X5R, +/-10%

4

QP8

QP8 FDN340P

FDN340P

+3V_EPW

CP156

4.7uF

Dummy

6.3V, X5R, +/-10%

*

RP672

RP672 1K

1K

Dummy

CP43

*

4.7uF

Dummy

6.3V, X5R, +/-10%

CP130

*

0.1uF

Dummy

16V, X7R, +/-10%

*

CP44

0.1uF

Dummy

CP27

4.7uF

Dummy

6.3V, X5R, +/-10%

CP523

*

0.47uF

10V, X5R, +/-10%

Dummy

16V, X7R, +/-10%

3

CP42

*

0.1uF

Dummy

16V, X7R, +/-10%

5VDUAL_S3#O71

*

RP175

1K

+/-1%

2

B

RP176

RP176 33 Ohm

33 Ohm

+/-1%

+12V

E C

*

QP49

QP49 MMBT3904-7-F

MMBT3904-7-F

*

RP177

RP177 0

0

Dummy

+12V_UP1

1

+3V_PCIAUX(FOR PCI/PCIE SLOT)

16V, X7R, +/-10%

*

+3V_S5

RP172

CP45

4.7uF

Dummy

G

6.3V, X5R, +/-10%

SD

RP172 0

0

Dummy

QP73

QP73 FDN340P

FDN340P

Title

Power-1:Linear Power-1

DWG NO Rev

Lanikai _MT/DT

Date: Sheet

Date: Sheet of

Lanikai _MT/DT

*

RP600

RP600 1K

1K

1

CP151

4.7uF

*

65 71Wednesday, June 13, 2012

6.3V, X5R, +/-10%

CP152

22uF

*

Dummy

6.3V,X5R,+/-20%

A00

of

+5VSB +3V_PCIAUX

RP170

*

10K

*

RP171

RP171 20K

20K

+/-1%

61

3

QP71

S_PCIAUX_GATE24

S_SLP_S4#24,32,53,71

3

2

2N7002DW

4

5

CP132

*

0.1uF

CP144

1uF

*

+/-10%

2

5

+V_1.05_PCH

+3V

RP32

*

16.2K

+/-1%

P_1P05V_PCH_ADJ

CP30

D D

C C

+V_1.05_PCH

*

RP35

7.5K

+/-1%

RP295

RP295 0

0

CP30

1uF

*

+/-10%

ENABLE CIRCUIT

S_SLP_S3#24,32,53,64,70,71

+12V_UP1

84

5

+

6

-

P_1P05V_PCH_COMP

B

*

RP48

RP48 10K

10K

+5V_S5

7

UP1B

UP1B LM358DR

LM358DR

CP32

220pF

+/-10%

*

RP41

+/-1%

*

RP47

RP47 10K

10K

QP16

QP16 MMBT3904-7-F

MMBT3904-7-F

E C

P_1P05V_PCH_OUT

*

1K

P_1P05V_PCH_ADJ

DS

G

RP37

RP37 1K

1K

+/-1%

QP15

QP15 2N7002

2N7002

G

*

4

+1P5V_SM +1P5V_SM

CP24

4.7uF

DS

QP11

AOD452AL

4.7uF

*

6.3V, X5R, +/-10%

1.065V/6.2A

+1P05V_PCH

240mil

ECP6

CP34

0.1uF

*

Dummy

16V, X7R, +/-10%

*

+1P05V_PCH +1P05V_ME

CP35

4.7uF

*

6.3V, X5R, +/-10%

1

*

3 5 7 8

ECP6

470uF

+/-20%

RNP1

0

+/-5%

Dummy

CP25

0.1uF

*

Dummy

2 4 6

16V, X7R, +/-10%

3

+V_1.05_ME

PCH_MEPWRGD23

+5V_S5

*

CPP33

COPPER

Dummy

FBP7

*

30 Ohm@100MHz

CP28

22uF

6.3V,X5R,+/-20%

S_SLP_M#24,32,53,65

+3V_S5

12

*

RP36

*

30.1KOhm

+/-1%

CP33

0.47uF

PCH_MEPWRGD_RT8068

10V, X5R, +/-10%

RP43

*

10K

Dummy

+/-1%

RP49

Dummy

*

10K

+/-1%

2

1

1.05V/1.8A

LP1

UP2

4

PGOOD

9

PVIN1

10

PVIN2

8

SVIN

5

CP29

1uF

*

+/-10%

CP37

1uF

*

+/-10%

Dummy

EP_GND

EN

+3V_S5

Dummy

4 3

LX1 LX2 LX3

FB NC

RT8068AZQW

RP55

*

10K

+/-1%

5

P_1P05V_ME_LX_80

1 2 3 6

P_1P05V_ME_FB

7 11

16

2

QP14

QP14 MMDT5551

MMDT5551

PCH_MEPWRGD

LP1

1 2

*

2.2uH

*

RP39

*

10K

+/-1%

CP22

22uF

RP33

*

6.3V,X5R,+/-20%

7.5K+/-1%

*

CP31

33pF

50V, NPO, +/-5%

CP23

*

22uF

6.3V,X5R,+/-20%

80mil

CP26

*

10uF

6.3V,X5R,+/-10%

CPP34

COPPER

Dummy

+1P05V_ME

12

+V_1P8_SFR

B B

A A

+3V

RP25

12.7KOhm

+/-1%

1

RP28

RP28 15K

15K

+/-1%

2

RP296

*

0

1P8V_SFR_ADJ

CP17

1uF

*

+/-10%

5

+12V_UP1

84

3

+

2

-

1P8V_SFR_COMP

CP13

1uF

*

+/-10%

1

1P8V_SFR_OUT

UP1A

UP1A LM358DR

LM358DR

*

CP19

1nF

50V, X7R, +/-10%

*

RP31

RP31 1K

1K

+/-1%

RP29

RP29 1K

1K

+/-1%

+3V

DS

G

*

CP20

*

0.1uF

16V, X7R, +/-10%

QP9

AOD452AL

Dummy

4

CP14

*

4.7uF

6.3V, X5R, +/-10%

Dummy

1.812V/1.8A

80mil

CP21

*

10uF

6.3V,X5R,+/-10%

*

+1P8V_SFR

ECP5

220uF

*

CP15

0.1uF

16V, X7R, +/-10%

16V, +/-20%

+1P05V_ME

3

*

RP54

30.1KOhm

+/-1%

Dummy

RP56

*

301KOhm

Dummy

*

CP40

0.47uF

Dummy

10V, X5R, +/-10%

CP41

100pF

Dummy

*

+3V_S5

RP51

*

0

Dummy

RP52

RP52 33K +/-5%

33K +/-5%

Dummy

50V, NPO, +/-5%

1 6

2

RP53

*

+/-1%

5.6K

Dummy

PCH_MEPWRGD

43

5

QP19

QP19 MMDT5551

MMDT5551

Dummy

Title

DWG NO Rev

Date: Sheet

Date: Sheet of

PCH_MEPWRGD 23

CP38

0.1uF

*

Dummy

16V, X7R, +/-10%

Power-2:Linear Power-2

Lanikai _MT/DT

1

A00

of

66 71Wednesday, June 13, 2012

5

4

3

2

1

+1P05V_VCCIO

+3V

VCC_CORE

D D

+5V

P_VR_READY

+VCORE

*

RP76

RP76 100 Ohm

100 Ohm

+/-1%

*

RP80

RP80 100 Ohm

100 Ohm

+/-1%

NCP6151_GND NCP6151_GNDNCP6151_GND

RP88

*

RP90

0

Dummy

30.1KOhm

P_VR_READY

*

RP125

0

Dummy

34.8KOhm

NCP6151_GND NCP6151_GND

+/-1%

NCP6151_GND

+1P1V_AXG

*

NCP6151_GND

RP128

+/-1%

5

*

RP115

RP115 100 Ohm

100 Ohm

+/-1%

RP120

RP120 100 Ohm

100 Ohm

+/-1%

*

RP101

Dummy

*

P_VR_READY24,33,52,64

H_VCC_SENSE9

H_VSS_SENSE9

C C

B B

A A

VCC_AXG

H_VCCAGX_SENSE9

H_VSSAGX_SENSE9

RP70

47

+/-5%

NCP6151_GND

CP59

0.1uF

16V, X7R, +/-10%

*

0

NCP6151_GND

CPP27

COPPER

Dummy

CP77

0.1uF

16V, X7R, +/-10%

RP58

*

1K

+/-5%

*

RP181 402KOhm

CPP26

COPPER

Dummy

RP104

*

47

+/-5%

RP208 150KOhm

12

CP47

0.1uF

Dummy

RP73

*

1K

+/-1%

12

RP107

*

1K

Dummy

+5V

16V, X7R, +/-10%

+/-1%

RP59

*

1K

+/-5%

CP80

680pF

50V, X7R, +/-10%

*

+/-1%

NCP6151_GND

*

+3V

RP95

*

1K

+/-5%

*

Dummy

CP64

680pF

50V, X7R, +/-10%

*

+/-1%

*

NCP6151_GND

Maho Bay VR12 POWER - 4+1 PHASE

+12V_CPU

RP60

2.2

+/-5%

CP51

4.7uF

6.3V, X5R, +/-10%

7X7 SINGLE ROW QFN

V_GT PORTION

NCP6151_GND

10

11

ROSC

*

VCC

ROSC

RP134

RP134 12KOhm

12KOhm

+/-1%

*

50V,X7R,+/-10%

12

NCP6151_GND

VRMP

PWM2/VBOOT

EPAD

53

*

RP61

RP61 1K

1K

+/-1%

CP48

10nF

SDIO

SCLK

ALERT#

DRON

PWM1/ADDR

CSN1 CSP1

CSN2 CSP2

PWM3/IMAX

CSN3 CSP3

PWM4

CSN4 CSP4

CSSUM

CSCOMP

ILIM

DROOP

CSREF

PWMA/IMAXA

CSNA

CSPA

CSSUMA

CSCOMPA

ILIMA

DROOPA

VR_HOT#

TSENSE

NCP6151_GND

BOTTOM PAD CONNECT TO GND Through 4 VIAs

*

RP137

RP137 1K

Dummy

1K

Dummy

+/-1%

NCP6151_GND

4 5 6

33 32 35 34

30 39 38

31 37 36

29 40 41

44

CSSUM

45

CSCOMP

RP91

40.2K

47

ILIM

*

+/-1%

46

DROOP

42

CSREF

28 26 25

24

CSSUMA P_CSPA

22

CSCOMPA

20

ILIMA

21

DROOPA

3

VRHOT#

2

TSENSE

16V, X7R, +/-10%

NCP6151_GND

*

CP46

0.1uF

16V, X7R, +/-10%

RP66

*

24.9KOhm

+/-1%

CP55

0.1uF

Dummy

16V, X7R, +/-10%

CP62

0.1uF

Dummy

16V, X7R, +/-10%

RP110

*

24.9KOhm

+/-1%

CP74

0.1uF

Dummy

16V, X7R, +/-10%

RP126

*

1K

+/-1%

Dummy

RP71

*

4.99K+/-1%

*

RP74

RP74 402 Ohm

402 Ohm

+/-1%

*

CP90

5.6nF

50V,X7R,+/-10%

*

* *

*

NCP6151_GND

RP105

4.32K Ohm

*

+/-1%

CP66 22pF

RP109

402 Ohm

+/-1%

CP69

*

5.6nF

50V,X7R,+/-10%

NCP6151_GND

*

* *

*

NCP6151_GND

RP129

*

10K

+/-1%

NCP6151_GND

*

RTP6

T

10K

+/-1%

P_CORE_EN 64

CP82

2.2nF

50V, X7R,+/-10%

*

CP53

68pF

50V,NPO,+/-5%

*

RP67

*

1.2KOhm

+/-1%

CP50

1nF

Dummy

50V, X7R, +/-10%

CP56

0.1uF

Dummy

16V, X7R, +/-10%

CP65

2.2nF

*

50V, X7R,+/-10%

50V, NPO, +/-5%

*

RP111

*

1.2KOhm

+/-1%

CP92

1nF

Dummy

50V, X7R, +/-10%

CP75

0.1uF

Dummy

16V, X7R, +/-10%

RP130

*

3.3KOhm

+/-1%

RP132

*

7.5K

+/-1%

NCP6151_GND

DIFFOUT COMP

FB

CP52

4.7nF

*

TRBST

VSP

50V, X7R, +/-10%

VR_RDYA

DIFFOUTA COMPA

FBA

CP68

4.7nF 50V, X7R, +/-10%

*

TRBSTA

VSPA

VBOOTA

TSENSEA

CP79

*

0.1uF

16V, X7R, +/-10%

NCP6151_GND

4

+5V

*

UP4 NCP6153MNTWG

9

ENABLE

7

VR_RDY

52

DIFFOUT

48

COMP

49

FB

50

TRBST

1

VSP

51

VSN

43

IOUT

VCORE PORTION

8

VR_RDYA

17

DIFFOUTA

19

COMPA

16

FBA

18

TRBSTA

15

VSPA

14

VSNA

23

IOUTA

27

VBOOTA

13

TSENSEA

RP117

60.4K

*

+/-1%

RP118

7.5K

+/-1%

CP78

0.1uF

P_CSP1

P_CSP2

P_CSP3

P_CSP4

*

NCP6151_GND

P_CSPA

*

3

RP72

*

CP49 47nF

13.7K +/-1%

RP68

*

CP58 47nF

13.7K +/-1%

RP79

*

CP54 47nF

13.7K +/-1%

RP82

*

CP57 47nF

13.7K +/-1%

RP85 30.1KOhm

*

+/-1%

*

RP188

RP188 1K

1K

RP96

+/-1%

3.83KOhm

+/-1%

CP207

1nF

*

50V, X7R, +/-10%

CP63

1nF

50V, X7R, +/-10%

RP106 100KOhm

RP108

*

6.8K

+/-1%

RP113 150KOhm

RP113 150KOhm RTP3 100K

RTP3 100K

+/-1%

*

RP203

*

1K

+/-1%

CP208

560pF

*

+/-10%

RP131

*

3.3KOhm

+/-1%

RP133

T

*

7.5K

+/-1%

NCP6151_GND

*

16V,X7R,+/-10%

*

16V,X7R,+/-10%

*

16V,X7R,+/-10%

*

16V,X7R,+/-10%

RTP1

100K

+/-1%

T

*

+/-1%

T

*

RTP4

10K

+/-1%

+1P05V_VCCIO

RP62

RP62 110Ohm

110Ohm

+/-1%

RP69

RP69 100KOhm

100KOhm

+/-1%

Dummy

RP75

RP75 100KOhm

100KOhm

+/-1%

Dummy

RP77

RP77 100KOhm

100KOhm

+/-1%

Dummy

RP81

RP81 100KOhm

100KOhm

+/-1%

Dummy

CP67

0.1uF

*

16V, X7R, +/-10%

RP63

*

54.9

+/-1%

CP204

*

0.1uF

Dummy

16V, X7R, +/-10%

NCP6151_GND

CP205

*

0.1uF

Dummy

16V, X7R, +/-10%

NCP6151_GND

CP206

*

0.1uF

Dummy

16V, X7R, +/-10%

NCP6151_GND

CP223

*

0.1uF

Dummy

16V, X7R, +/-10%

RP86 80.6kohm

*

+/-1%

CP71 5.6nF

50V,X7R,+/-10%

*

CP60 120pF

50V,NPO,+/-5%

*

1 2

CP61 150pF

50V, NPO, +/-5%

*

RP98 13.7K

*

RP114 200KOhm

+/-1%

CP70

2.2nF

50V, X7R,+/-10%

*

CP72 1.2nF

+/-10%

*

CP73 680pF

RP124 5.36KOhm

RP64

RP64 91 Ohm

91 Ohm

+/-1%

Dummy

+/-1%

*

50V, X7R, +/-10%

*

+/-1%

RP112

*

20K

+/-1%

NCP6151_GND

CPP11

12

COPPER

Dummy

P_CSN1 P_CSP1

P_CSN2 P_CSP2

P_CSN3 P_CSP3

P_CSN4 P_CSP4

RP84 32.4K Ohm

RP84 32.4K Ohm RP87 32.4K Ohm

RP87 32.4K Ohm RP89 32.4K Ohm

RP89 32.4K Ohm RP92 32.4K Ohm

RP92 32.4K Ohm

RP94 10 Ohm

RP94 10 Ohm RP97 10 Ohm

RP97 10 Ohm RP99 10 Ohm

RP99 10 Ohm RP100 10 Ohm

RP100 10 Ohm

*

RP121

RP121 10 Ohm

10 Ohm

+/-1%

CP76

*

1nF

50V, X7R, +/-10%

NCP6151_GND

2

H_VIDSOUT 9 H_VIDSCLK 9 H_VIDALERT# 9

P_DRVON 68 P_PWM1 68

P_CSN1 68 P_CSP1 68

P_PWM2 68 P_CSN2 68 P_CSP2 68

P_PWM3 68 P_CSN3 68 P_CSP3 68

P_PWM4 68 P_CSN4 68 P_CSP4 68

*

+/-1%

*

+/-1%

*

+/-1%

*

+/-1%

*

+/-1%

*

+/-1%

*

+/-1%

*

+/-1%

P_PWMA 68 P_CSNA 68

P_CSPA 68

P_CSNA

P_CSP1 P_CSP2 P_CSP3 P_CSP4

P_CSNA 68

H_PROCHOT# 9,32

PWM ADDRESS

RESISTOR VALUE

10K 25K 45K 70K

95K 125K 165K

SVID ADDRESS FOR VCORE RAIL

0000 0010 0100 0110 1000 1010 1011 1100

BOOT VOLTAGE

RESISTOR VALUE

+5V

3PHASE OPTION

RP83

RP83 0

0

Dummy

P_PWM4

P_CSN1 P_CSN2 P_CSN3 P_CSN4

P_PWM2

VCORE VBOOT SET AT 0V

P_PWM1

PWM ADDRESS

Title

DWG NO Rev

Date: Sheet

10K 25K 45K

*

70K

95K 135K 1.35V 165K

RP102

*

NCP6151_GND NCP6151_GND

*

NCP6151_GND NCP6151_GND

V_GT

10K

IMAX SET

+/-1%

AT 35A

VCORE

RP122

IMAX SET

10K

+/-1%

AT 120A

Power-3: Vcore PWM

Lanikai _MT/DT

SVID ADDRESS FOR V_GT RAIL

0001 0011 0101 0111 1001

1101

BOOT VOLTAGE

0V

0.9V

1.0V

1.1V

1.2V

1.5V

P_PWMA

*

P_PWM3

*

1

RP103

27.4K

+/-1%

RP123

93.1K

+/-1%

A00

of

67 71Wednesday, June 13, 2012

of

67 71Wednesday, June 13, 2012

of

67 71Wednesday, June 13, 2012

5

4

3

2

1

RP145

2.2Ohm

+/-1%

RP157

2.2Ohm

+/-1%

HGA_R_25

+12V_CPU

RP136

2.2

VCC2_20

*

+12V_CPU

RP148

2.2

VCC4_20

*

+12V_VIN

5

QP36

D

G

4

1

S

2 3

NTMFS4927NT1G

SWA_25

5

D

4

G

1

S

2

QP37

3

NTMFS4925NT1G

3

RP138

+/-5%

4

VCC

2

PWM

3

EN

CP88

1uF

+/-10%

RP150

+/-5%

4

VCC

2

PWM

3

EN

CP108

1uF

+/-10%

QP62

D

G

4

S

NTMFS4927NT1G

D

4

G

S

QP38

NTMFS4925NT1G

2.2

PAD

9

2.2

PAD

9

5

1 2 3

5

1 2 3

25V, X7R, +/-10%

BST2_25

1

DRVH

BST

SW

DRVL

GND

NCP5901BMNTBG

6

BOTTOM PAD CONNECT TO GND Through 4 VIAs

BST4_25BST3_25

1

DRVH

BST

SW

DRVL

GND

NCP5901BMNTBG

6

BOTTOM PAD CONNECT TO GND Through 4 VIAs

CP267

3.3nF

*

+/-10%

RP187

*

1

+/-5%

CP128

*

3.3nF

50V, X7R, +/-10%

RP164

*

1

+/-1%

P_CSPA67 P_CSNA67

CP85

*

220nF

UP6

8

7 5

*

CP95

220nF

25V, X7R, +/-10%

UP8

8

7 5

CP188

10uF

*

16V,X5R,+/-10%

CPP9

CPP9 COPPER

COPPER

Dummy

HG2_25 69

+/-5%

2.2

RP140

*

RP142

RP142 10K

10K

Dummy

+/-5%

2.2

2.2 RP152

RP152

*

RP154

RP154 10K

10K

Dummy

LG4_25

CP189

10uF

*

12

LP7

*

Choke 470nH

1 2

4

HG2_R_25HG2_25

SW2_25

D

4

G

S

QP25

NTMFS4925NT1G

4

HG4_R_25HG4_25

SW4_25

D

4

G

S

QP33

NTMFS4925NT1G

CP121

*

0.1uF

Dummy

16V, X7R, +/-10%

16V,X5R,+/-10%

ECP17

820uF

*

+/-20%

CPP10

CPP10 COPPER

COPPER

Dummy

+12V_VIN

5

QP22

D

G

1

S

2 3

5

NTMFS4927NT1G

4

G

1 2

QP26

3

NTMFS4925NT1G

+12V_VIN

5

QP30

D

G

1

S

2 3

5

NTMFS4927NT1G

4

G

1 2

QP34

3

NTMFS4925NT1G

ECP18

820uF

*

+/-20%

+1P1V_AXG

CP131

22uF

Dummy

*

6.3V,X5R,+/-20%

CP264

3.3nF

*

+/-10%

RP184

*

1

+/-5%

5

D

CP89

3.3nF

50V, X7R, +/-10%

1

S

2

RP146

3

1

+/-1%

P_CSP267 P_CSN267

CP266

3.3nF

*

+/-10%

RP186

*

1

+/-5%

5

D

CP109

3.3nF

50V, X7R, +/-10%

1

S

2

RP158

3

1

+/-1%

P_CSP467 P_CSN467

Bottom side

CP117

22uF

*

Dummy

6.3V,X5R,+/-20%

ECP19

820uF

*

+/-20%

Dummy

Bottom side

CP210

22uF

Dummy

*

6.3V,X5R,+/-20%

2

CP184

10uF

*

16V,X5R,+/-10%

*

CPP3

*

COPPER

Dummy

CP186

10uF

*

16V,X5R,+/-10%

*

CPP7

*

COPPER

Dummy

CP101

22uF

*

Dummy

6.3V,X5R,+/-20%

ECP20

820uF

*

+/-20%

Dummy

CP185

10uF

CP83

*

Choke 300nH

16V,X5R,+/-10%

LP3

12

*

1 2

0.1uF

Dummy

16V, X7R, +/-10%

*

CPP4

CPP4 COPPER

COPPER

Dummy

LL=1.7m ohms

0.25V~1.55V/112A MAX

OS-CON

ECP9

820uF

+/-20%

TDC=85A

ECP10

820uF

*

+/-20%

ECP12

820uF

*

+/-20%

ECP8

820uF

+/-20%

ECP11

820uF

+/-20%

Ceramic / 0805/X5R

CP116

CP96

22uF

*

CP187

10uF

*

16V,X5R,+/-10%

LP5

12

*

Choke 300nH

1 2

+VCORE

CP161

CP162

22uF

*

Dummy

6.3V,X5R,+/-20%

ECP22

ECP27

820uF

*

+/-20%

Title

DWG NO Rev

Date: Sheet of

Date: Sheet

*

CP93

*

0.1uF

Dummy

6.3V,X5R,+/-20%

CP102

22uF

*

16V, X7R, +/-10%

6.3V,X5R,+/-20%

CPP8

CPP8 COPPER

COPPER

Dummy

1 2

6.3V,X5R,+/-20%

+1P1V_AXG

6.3V,X5R,+/-20%

CP110

22uF

*

6.3V,X5R,+/-20%

Inside processor socket

CP97

22uF

*

6.3V,X5R,+/-20%

Dummy

0.25V~1.55V/35AMax

CP124

22uF

*

RP179

*

220

+/-5%

Dummy

Power-4: Vcore Driver

Lanikai _MT/DT

CP116

CP115

22uF

*

6.3V,X5R,+/-20%

CP103

CP104

22uF

*

6.3V,X5R,+/-20%

CP112

CP111

22uF

*

6.3V,X5R,+/-20%

CP98

CP100

22uF

*

6.3V,X5R,+/-20%

Dummy

LL=4.1m ohms

TDC=25A

CP126

CP125

22uF

*

6.3V,X5R,+/-20%

1

*

Dummy

*

6.3V,X5R,+/-20%

RP182

*

220

+/-5%

Dummy

CP99

CP118

22uF

*

6.3V,X5R,+/-20%

CP114

CP105

22uF

*

6.3V,X5R,+/-20%

CP113

22uF

6.3V,X5R,+/-20%

CP119

22uF

6.3V,X5R,+/-20%

CP178

22uF

*

6.3V,X5R,+/-20%

of

68 71Wednesday, June 13, 2012

+VCORE

6.3V,X5R,+/-20%

CP153

CP160

22uF

*

6.3V,X5R,+/-20%

A00

+12V_CPU

QP21

G

4

5

NTMFS4927NT1G

D

1

S

2 3

QP29

4

HG3_R_25

SW3_25

D

4

G

S

QP31

NTMFS4925NT1G

+12V_CPU

P_DRVON

+12V_VIN

*

16V, +/-20%

+12V_VIN

*

5

D

*

1

S

2 3

5

D

4

G

1

S

2

QP24

3

NTMFS4925NT1G

+12V_VIN

5

D

G

1

S

2 3

5

NTMFS4927NT1G

D

4

G

1

S

2

QP32

3

NTMFS4925NT1G

RP159

2.2

*

RP163

2.2Ohm

+/-1%

ECP16

470uF

CP263

3.3nF

+/-10%

RP183

RP183 1

1

+/-5%

CP87

3.3nF

50V, X7R, +/-10%

RP144

1

+/-1%

P_CSP167 P_CSN167

CP265

3.3nF

*

+/-10%

RP185

*

1

+/-5%

5

CP107

3.3nF

50V, X7R, +/-10%

1 2 3

VCCA_20

CP127

1uF

*

+/-10%

4

*

RP156

1

+/-1%

P_CSP367 P_CSN367

4

2 3

CP190

10uF

16V,X5R,+/-10%

CPP1

CPP1 COPPER

COPPER

Dummy

CP181

10uF

*

RP160

2.2

+/-5%

VCC

PWM EN

PAD

9

CP183

10uF

*

16V,X5R,+/-10%

LP2

12

*

Choke 300nH

1 2

CP182

10uF

*

16V,X5R,+/-10%

LP4

Choke 300nH

CPP5

CPP5 COPPER

COPPER

Dummy

1 2

CP122

220nF

25V, X7R, +/-10%

BSTA_25

1

DRVH

BST

SW

DRVL

GND

NCP5901BMNTBG

6

BOTTOM PAD CONNECT TO GND Through 4 VIAs

CP81

*

0.1uF

Dummy

16V, X7R, +/-10%

+VCORE

CPP2

CPP2 COPPER

COPPER

Dummy

1 2

*

Dummy

16V, X7R, +/-10%

16V,X5R,+/-10%

12

*

CPP6

CPP6 COPPER

COPPER

Dummy

1 2

*

UP9

8

HGA_25

7 5

P_PWM267

P_DRVON LG2_25

CP91

0.1uF

P_PWM467

+VCORE

P_DRVON

+/-5%

2.2

2.2 RP161

RP161

*

RP162

RP162 10K

10K

Dummy

LGA_25

25V, X7R, +/-10%

BST1_25

1

DRVH

BST

SW

DRVL

GND

NCP5901BMNTBG

6

BOTTOM PAD CONNECT TO GND Through 4 VIAs

2.2

1

BST

GND

PAD

NCP5901BMNTBG

6

9

BOTTOM PAD CONNECT TO GND Through 4 VIAs

LP6

*

Choke 1uH

25V, X7R, +/-10%

220nF

CP84

*

UP5

8

HG1_25

7 5

*

CP94

220nF

25V, X7R, +/-10%

UP7

8

DRVH

7

SW

5

DRVL

*

+/-5%

2.2

2.2 RP139

RP139

*

RP141

RP141 10K

10K

Dummy

LG1_25

HG3_25

LG3_25

P_PWMA67

P_DRVON67

ECP14

470uF

16V, +/-20%

HG1_R_25

SW1_25

4

G

QP23

NTMFS4925NT1G

+/-5%

2.2

RP151

*

RP153

RP153 10K

10K

Dummy

ECP15

470uF

*

16V, +/-20%

RP135

2.2

+/-5%

RP271

2.2

VCC1_20

CP86

1uF

*

+/-10%

+12V_CPU

RP147

2.2

*

4

2 3

VCC3_20

CP106

1uF

+/-10%

*

5

2.2

+/-5%

VCC

PWM EN

PAD

9

RP149

+/-5%

4

VCC

2

PWM

3

EN

1 2

CP123

0.1uF

16V, X7R, +/-10%

D D

P_PWM167

P_DRVON

C C

B B

A A

P_PWM367

P_DRVON

+12V_CPU

4 2

*

RP143

2.2Ohm

+/-1%

RP155

2.2Ohm

+/-1%

12V_PWRCONN

3 1

Header_2X2

*

5

4

3

2

1

RP167

2.2

+/-5%

VCCP

+/-5%

+5V

RP350

2.2

+/-5%

VCCIO_VCC

15

VCC

VSEN

10

VCCIO_VSEN

RP354 0 +/-5%

RP353

*

0

+/-5%

Dummy

BOOT

CSP

CSN/VO

11

*

CP350

*

1uF

16V, X5R, +/-10%

4

5

UG

3

LX

2

LG

13

12

FBG

VCCIO_FBG

Dummy

VCCIO_BST_25

CP139

0.1uF 25V, X7R, +/-10%

VCCIO_UG_25

VCCIO_LX_25

VCCIO_LG_25

VCCIO_CSP

VCCIO_CNS

*

16V, X7R, +/-10%

*

RP190 2.2

RP166

*

2.1KOhm

+/-1%

CP301

0.1uF

VCCIO_UG_R_25

+/-5%

CP351

*

0.1uF

16V, X7R, +/-10%

+12V_VIN

+1P05V_VCCIO

CP134

0.1uF

*

Dummy

CP135

10uF

ECP21

470uF

*

+/-20%

1.05V or 1.0V/17A MAX

Dummy

CP147

22uF

*

6.3V,X5R,+/-20%

Dummy

CP148

22uF

6.3V,X5R,+/-20%

Dummy

CP149

22uF

*

6.3V,X5R,+/-20%

Bottom side

Dummy

CP241

22uF

*

6.3V,X5R,+/-20%

Dummy

CP252

CP262

22uF

*

6.3V,X5R,+/-20%

Dummy

CP270

CP271

22uF

*

6.3V,X5R,+/-20%

Ceramic / 0805/X5R

CP261

CP258

22uF

*

5

QP39

D

G

4

1

S

NTMFS4927NT1G

D

4

G

S

QP40

NTMFS4925NT1G

*

2 3

5

1 2 3

+1P05V_VCCIO

*

RP202

RP202 100 Ohm

100 Ohm

+/-1%

RP198

RP198 100 Ohm

100 Ohm

+/-1%

*

RP191

RP191 10K

10K

Dummy

RP357

RP357 12KOhm

12KOhm

+/-1%

CPP29

12

COPPER

CPP28

Dummy

12

COPPER

Dummy

3

16V, X7R, +/-10%

*

CP142

2.2nF

50V, X7R, +/-10%

RP195

2.2

+/-5%

16V,X5R,+/-10%

LP9

*

330nH

12

CPP12

CPP12 COPPER

COPPER

Dummy

H_VCCTT_SENSE 9

H_VSSTT_SENSE 9

12

CPP13

CPP13 COPPER

COPPER

Dummy

2

*

6.3V,X5R,+/-20%

ECP26

ECP13

820uF

*

+/-20%

ECP26

ECP23

820uF

*

+/-20%

Dummy

+1P05V_VCCIO

Title

DWG NO Rev

Date: Sheet of

Date: Sheet

CP260

CP256

22uF

*

6.3V,X5R,+/-20%

ECP24

820uF

+/-20%

*

6.3V,X5R,+/-20%

ECP25

820uF

*

+/-20%

Dummy

CP278

22uF

*

6.3V,X5R,+/-20%

Bottom side

CP214

CP215

22uF

0.1uF

*

0.1uF

*

Dummy

6.3V,X5R,+/-20%

CP218

CP219

0.1uF

*

Dummy

16V, X7R, +/-10%

Power-5: VCCIO

Lanikai _MT/DT

CP257

CP259

22uF

*

6.3V,X5R,+/-20%

Bottom side

Dummy

CP277

CP280

22uF

*

6.3V,X5R,+/-20%

Bottom side

Dummy

CP279

CP281

22uF

*

6.3V,X5R,+/-20%

CP216

0.1uF

*

Dummy

16V, X7R, +/-10%

CP221

0.1uF

*

Dummy

16V, X7R, +/-10%

CP254

CP275

22uF

*

6.3V,X5R,+/-20%

Dummy

CP272

22uF

*

6.3V,X5R,+/-20%

Dummy

CP273

22uF

*

6.3V,X5R,+/-20%

CP217

0.1uF

*

Dummy

16V, X7R, +/-10%

CP220

0.1uF

*

Dummy

16V, X7R, +/-10%

1

CP274

22uF

*

6.3V,X5R,+/-20%

Dummy

CP253

22uF

*

6.3V,X5R,+/-20%

A00

of

69 71Wednesday, June 13, 2012

+3V +5V

*

RP180

RP180 10K

10K

D D

HG2_2568

+1P05V_PCH +5VSB

*

RP200

C C

1K

+/-1%

CP136

*

0.1uF

Dummy

16V, X7R, +/-10%

VCCIO VID control

B B

*

RP206

RP206 10K

10K

Dummy

QP74

MMDT5551

16

2

4 3

5

A A

RP201

1K

*

+/-1%

Dummy

H_VCCIO_SEL High ->+1P05V_VCCIO=1.05V H_VCCIO_SEL Low ->+1P05V_VCCIO=1.0V

B

+5V+5V

*

VCCIO_PWRGD70

*

RP199

RP199 10K

10K

+/-1%

*

QP70

E C

MMBT3904-7-F

RP209

RP209 10K

10K

Dummy

CP150

*

0.1uF

Dummy

16V, X7R, +/-10%

H_VCCIO_SEL 9

5

*

2N7002

CP137

0.1uF

Dummy

G

RP355

39.2K

+/-1%

Dummy

RP356

RP356 0

0

+/-5%

QP69

G

16V, X7R, +/-10%

Dummy

DS

CP138

*

0.1uF

16V, X7R, +/-10%

DS

CP380

*

0.1uF

16V, X7R, +/-10%

Dummy

RP212

17.4kohm

*

+/-1%

Dummy

QP46

QP46 2N7002

2N7002

RP226

17.4kohm

VCCIO_VSEN

*

+/-1%

Dummy

QP48

QP48 2N7002

2N7002

Dummy

VCCIO_FBG

VCCIO_ROSE/EN

RP351

*

49.9K

+/-1%

RP193

4.53K Ohm

+/-1%

CP141

*

0.1uF

16V, X7R, +/-10%

RP205

*

3.16K

+/-1%,

*

RP207

RP207 0

0

Dummy

VCCIO_PWRGD

VCCIO_SYN

VCCIO_COMP

*

RP192

RP192 100 Ohm

100 Ohm

*

+/-1%

CP133

*

1uF

16V, X5R, +/-10%

UP10

6

PGOOD

7

SYNCH

14

ROSC/EN

16

GND

17

Thermal PAD

8

COMP

CP143

100pF

50V, NPO, +/-5%

RP194

RP194 1K

1K

*

+/-1%

VCCIO_VCCP

1

NCP5230MNTWG

FB

9

VCCIO_FB

RP168 0

*

CP140

1nF

50V, X7R, +/-10%

*

4

5

4

3

2

1

D D

+12V

G

CP159

*

22nF

Dummy

RP221

*

100 Ohm +/-1%

CPP30

12

COPPER

Dummy

+1P05V_VCCIO

DS

QP41

AOD452AL

H_VCCSA_SENSE 9

*

CP163

0.1uF

Dummy

16V, X7R, +/-10%

CP158

10uF

*

c0805h14

6.3V,X5R,+/-10%

0.929V or 0.855V/8.8A

+V_VCCSA

ECP41

CP359

10uF

*

6.3V,X5R,+/-10%

ECP41

CP362

820uF

10uF

*

+/-20%

6.3V,X5R,+/-10%

CP360

10uF

*

6.3V,X5R,+/-10%

H_VCCSA_VID9

*

RP213

2.2

CP191

1uF

UP11

C C

VCCSA_COMP_EN

VCCSA_FB

RP263

*

20.5K

+/-1%

B B

UP11

1

EN

2

GND

3

FB

NCP102SNT1G

VCC DRV

SOFT-S

6 5 4

1uF

*

+/-10%

RP196

*

100 Ohm

CP164

CP192

15nF

*

+/-10%

RP238

RP238 10K

10K

Dummy

100pF

*

50V, NPO, +/-5%

Dummy

*

+/-1%

RP236

3.24K Ohm

*

+/-1%

16V, X7R, +/-10%

+5V

VCCSA VID control

+5V

*

RP220

RP220 10K

10K

Dummy

*

RP224

RP224 1K

1K

+/-1%

Dummy

VCCSA sequencing circuit

16

2

*

RP297

QP44

10K

MMDT5551

Dummy

VCCSA_COMP_EN

MMDT5551

RP225

*

100 Ohm

+/-1%

Dummy

RP222

*

100

+/-5%

Dummy

QP45

4 3

16

1

2

RP216

RP216 15K

15K

+/-1%

Dummy

5

2

5

16

MMDT5551

RP217

RP217 10K

10K

4 3

10K

10K RP230

RP230

RP218

10K

4 3

VCCIO_PWRGD

+5V+5V

*

QP43

Dummy

*

+5V_S5

*

S_SLP_S3# 24,32,53,64,66,71

*

+5V_S5

VCCIO_PWRGD 69

RP219

RP219 10K

10K

Dummy

G

CP155

*

0.1uF

Dummy

16V, X7R, +/-10%

RP233

*

35.7KOhm

DS

+/-1% Dummy

QP42

QP42 2N7002

2N7002

Dummy

VCCSA_FB

A A

Title

Power-6: VCCSA

DWG NO Rev

Lanikai _MT/DT

5

4

3

2

Date: Sheet

1

Date: Sheet of

Lanikai _MT/DT

Date: Sheet of

70 71Wednesday, June 13, 2012

A00

of

5

CP227

*

0.1uF

16V, X7R, +/-10%

Dummy

B_ATX_PWROK32,63

D D

CP226

*

0.1uF

16V, X7R, +/-10%

Dummy

CPP35

1 2

COPPER

Dummy

CP292

*

0.1uF

16V, X7R, +/-10%

Dummy

+5V

CP293

*

0.1uF

16V, X7R, +/-10%

Dummy

S_SLP_S3#24,32,53,64,66,70

+3V_DUAL

3.3V/1.5A MAX

CP166

*

C C

10uF

Dummy

6.3V,X5R,+/-10%

*

CP167

0.1uF

16V, X7R, +/-10%

CP168

*

4.7uF

6.3V, X5R, +/-10%

+5VSB

CP169

*

1uF

Dummy

16V, X5R, +/-10%

CP170

0.1uF

Dummy

16V, X7R, +/-10%

CP171

*

4.7uF

6.3V, X5R, +/-10%

+5V_DUAL_USB

RP267

5VDUAL_USBSW

5VDUAL_S3#O

B B

+5VDUAL

5VDUAL_SBSW

5VDUAL_S3#O

A A

RP267

*

1M

+/-5%

2 1

DP3

BAT54C

CP179

2.2nF

50V, X7R, +/-10%

5

3

CP177

2.2nF

50V, X7R, +/-10%

+5VSB

3

125

*

G

3

125

*

QP59

G

AOD452AL

4

QP65

QP65 SI3457CDV-T1-E3

SI3457CDV-T1-E3

6

DS

QP67

AOD452AL

+5V

4

QP64

QP64 SI3457CDV-T1-E3

SI3457CDV-T1-E3

6

DS

QP60

G

AOD452AL

+5V

RP265

*

1K

+/-1%

DS

*

RP266

RP266 1K

1K

+/-1%

*

+5V_DUAL

*

RP268

RP268 1K

1K

+/-1%

CP180

4.7uF

6.3V, X5R, +/-10%

4

+5V_DUAL +5VSB

*

CPP36 COPPER

Dummy

+5V_DUAL_USBKB

*

+5VSB +1P5V_SM

RP241

3.24K Ohm

+/-1%

Dummy

VT_5078_5VMAIN

1 2

S_SLP_S4#24,32,53,65

5VDUAL_S3#O65

S_SLP_S4#24,32,53,65

VT_5078_ILIM

RP248

200KOhm

+/-1%

RP269

RP269 1K

1K

+/-1%

+3V+12V

RP270

*

8.2K

+/-5%

G

ECP37

470uF

6.3V, +/-20%

+3V_DUAL

Max. output current = 1.5A

4

RP242

*

8.2K

+/-5%

VT_5078_PG

VT_5078_S3#I

5VDUAL_SBSW

5VDUAL_S3#O

5VDUAL_USBSW

VT_5078_SS

CP172

*

0.1uF

16V, X7R, +/-10%

*

AOD452AL

AOD452AL QP75

QP75

D S

*

13

4 14 17 18

3 15 16

1

2

20 21

ECP40

1000uF

Dummy

6.3V, +/-20%

ECP38

470uF

6.3V, +/-20%

3

+V_1.5_SM Power(DDRIII)

8

ISNS

FB

GND

VT_5078_BOOT_25

9

VT_5078_HDRV_25

10 11

VT_5078_ISNS

12

VT_5078_LDRV_25

23

VT_5078_FB

22

VT_5078_COMP

7 24

VT_5078_REF_IN

6 5

VT_5078_VTT_SNS

19 25

3

25V, X7R, +/-10%

*

FBP3

30 Ohm@100MHz

QP52

G

4

NTMFS4927NT1G

4

G

QP55

NTMFS4925NT1G

RP250

*

4.99K

+/-1%

CP196

10nF

*

Dummy

25V, X7R, +/-10%

CP197

*

10nF

Dummy

+5V_DUAL

*

FBP2

FBP2 30 Ohm@100MHz

30 Ohm@100MHz

5

D

1

S

2 3

5

D

4

G

1

S

2

QP56

3

NTMFS4925NT1G

*

CP173

0.1uF

16V, X7R, +/-10%

*

RP257

1K

+/-1%

*

RP258

1K

+/-1%

+V_1.5_SM Power(DDRIII)

*

FBP1

FBP1 30 Ohm@100MHz

30 Ohm@100MHz

*

5

D

1

S

2 3

PGOOD 5V_MAIN VCC S3I# EN

5VSB_DRV 3VSB_OUT VCC_EN

5VUSB_DRV S4ST#

ILIM SS

UP12

UP12 RT9646AZQW

RT9646AZQW

CP243

10uF

*

Dummy

6.3V,X5R,+/-10%

BOOT UGATE PHASE

LGATE

COMP

VDDQ_IN

REF_IN VTT_OUT VTT_SNS

GND1

VT_5078_HDRV_25

VT_5078_PHASE_25

VT_5078_LDRV_25

VT_5078_PHASE_25

CP175

*

4.7nF

50V, X7R, +/-10%

RP254

*

18K

+/-1%

2

12

CPP31

CPP31 COPPER

COPPER

Dummy

CP174

470pF

*

Dummy

50V, X7R, +/-10%

RP252

*

1.27K

+/-1%

RP255

CP176

47pF

*

50V, NPO, +/-5%

RP255 33K

33K

+/-5%

Dummy

RP256

*

1.82KOhm

+/-1%

50V, X7R, +/-10%

RP253

*

1K

+/-1%

Dummy

1

+V_SM_VTT Power(DDR VTT)

+1P5V_SM_VTT

0.75V/1.5A MAX

CP199

CPP32

1 2

COPPER

Dummy

*

FBP4

Dummy

FBP4

Dummy

30 Ohm@100MHz

CP200

1uF

*

Dummy

16V, X5R, +/-10%

LP12

Choke 1uH

CP202

2.2nF

50V, X7R, +/-10%

+1P5V_SM

RP261

Bottom side

2.2

+/-5%

CP203

22uF

*

Dummy

CP201

10uF

6.3V,X5R,+/-10%

*

6.3V,X5R,+/-20%

2

Dummy

12

*

CP212

22uF

Dummy

6.3V,X5R,+/-20%

*

ECP31

1000uF

CP198

0.1uF

16V, X7R, +/-10%

ECP29

470uF

6.3V, +/-20%

*

6.3V, +/-20%

CP209

22uF

*

Dummy

CP199

*

4.7uF

6.3V, X5R, +/-10%

ECP30

470uF

*

6.3V, +/-20%

ECP33

ECP32

1000uF

820uF

*

+/-20%

6.3V, +/-20%

Title

6.3V,X5R,+/-20%

DWG NO Rev

Date: Sheet of

Date: Sheet

ECP36

*

470uF

+1P5V_SM

470uF

6.3V, +/-20%

RP260

*

100 Ohm

+/-5%

Dummy

1.5V/25A MAX

CP213

ECP35

CP129

1000uF

22uF

*

22uF

*

6.3V, +/-20%

6.3V,X5R,+/-20%

Power-7: DDR3/5Vdual/5VUSB

Lanikai _MT/DT

CP211

22uF

6.3V,X5R,+/-20%

CP213

22uF

*

6.3V,X5R,+/-20%

1

*

71 71Wednesday, June 13, 2012

+/-20%

Dummy

A00

of

ECP43

ECP34

820uF

*

Dell OPTIPLEX 7010 Schematics