Dell Latitude XPS 13 9000 Schematics

A

B

C

D

E

MODEL NAME :

PCB NO :

LA-H811P

BOM P/N :

1 1

ZZZ LA-H811P

Modena

451AHT31L01 ~ L32

Dell/Compal Confidential

2 2

Schematic Document

CPU Option

UC1

SRG0S@

SA0000CTD2L

ICE LAKE SRG0S I3 32EUs

UC1

SRGKL@

SA0000CTB2L

ICE LAKE SRGKL I5 32EUs

UC1

SRG0N@

SA0000CT62L

ICE LAKE SRG0N I7 64EUs

(MODENA ICE Lake U)

3 3

TBT Option

URT1

SA0000CAH3L

JHL8040R QURW

PD Option

UPD1

SA0000CM71L

SN1806026RSHR

WLAN Option

UWL1

4 4

PK29S009L0L

KILLER1650S.01

BB@

MP@

CNV@

URT2

BB@

SA0000CAH3L

JHL8040R QURW

UPD2

MP@

SA0000CM71L

SN1806026RSHR

UWL1

DAR@

PK29S00B60L

WBQ76QOUS01

TPM Option

U712

ST@

SA0000C5G10

ST33HTPH2032AHC1_VQFN32_5X5

2019-12-16

Rev: 1.0 (A00)

EC Option

UE1

5105@

SA00009GL30

MEC5105_WFBGA169_11X11

UE1

5106C@

SA0000C5D00

MEC5106K-D2-TN-TR

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2020/10/01 2018/10/01

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size

Date: Sheet of

Compal Electronics, Inc.

P001 - Cover

Document Number Re v

LA-H811P

E

1 100Tuesday, December 24, 2019

0.1 (X00)

A

TPM2.0

ST/Nuvoton TPM chip

M.2 SSD-Key M

1 1

WLAN/BT 5.1 Solder down Killer 1650-S 1216 SIP

uSD Connector

SD4.0/SDXC

SD_WP

p.67

1 6 1 2

p.52

Card Reader 4.0 RealTek RTS5242 PCIe to SD

GPIO (BIOS Controlled )

TBT

2SBU

TPS65987-DD J

VBUS

PP_HV1

PP_HV2

CC

2CC VCONN

p.42

USB2/I2C MUXES_L

p.50

2SBU

TPS65987-DD J

VBUS

PP_HV1

PP_HV2

CC

VCONN2CC

p.44

USB2/I2C MUXES_R

p.50

Fingerprint module

I2C2

I2C1

SPI

I2C2

I2C1

SPI

Fingerprint Controller GOODIX GF5288+HT32

p.43

VBUS

USB (Top)

USB (Bottom)

USB Type-C

TBT with PD

2 2

(Left)

TBT

p.45

VBUS

USB (Top)

USB (Bottom)

USB Type-C

TBT with PD (Right)

3 3

EC UART Debug/80 port

SPI Programmer

PD Programmer/I2C

BIOS UART Debug

DCI Debug

4 4

RT Programmer

I2C

USB

I2C

USB

Power Button

MIPI60 Debug

APS Debug

JESPI Debug

Burnside Bridge TBT Re-Timer

CHRG_IN

5VALW

to EC

Burnside Bridge TBT Re-Timer

CHRG_IN

5VALWB

to EC

p.77

p.46,47

p.48,49

PWRBTN#

to PD & USB2/I2C MUXES

Coin Cell

A

B

PCH SPI Flash ROM 32M

p.70p.70

SMBUS

TBT

LSx / AUX

I2C

RT SPI Flash ROM 1M

PD SPI Flash ROM 1M

SMBUS

TBT

LSx / AUX

I2C

RT SPI Flash ROM 1M

PD SPI Flash ROM 1M

to Battery Gauge FPC

VCCIN Controller MP2940 AGRT

Charger ISL9538B

Battery Connector

B

SPI

p.9

p.66

SPI#0

DDI#A

PCIe Gen3 x 4lanes PCIe#9,10, 11,12

PCIe Gen2 x 1lane

USB2.0

CNVi Gen2

PCIe Gen2 x 1lane

p.46

PCIe#3

USB2#3

CNVi Gen2

PCIe#16

SML#0

TBT#0

LSx / AUX

SML#1

USB2#8

USB2#9

ISH_I2C#1

IceLake-U

USB2.0

4+2

TBT#2

LSx / AUX

USB2#4

USB2#5

GPP_D13 GPP_D14

SMBUS

SMB#03 eSPI

GPIO

EC MEC5106D

SMB#04

SMB#05

SMB#10

p.58

USB2#1

USB3#2

SMB

GPIO 1 61 (VCI_IN2#)

eSPI

SMB#01

BCM#1

PWM#0

PWM#1

SMB#00

p.42

p.48

p.44

BATBTN#

SMBUS

p.91

SMBUS

p.83

p.82

Hinge Down

I2C#0

DMIC

HDA

I2C#1

eSPI

GPIO

PS/2

LEDs

C

eDP x4 lanes

I2C

LPDDR4 4GB X32x4 Memory Down LPDDR4x 8/16/32 GB X32x4 Memory Down

Memory Bus (LPDDR4/ x)

Dual Channel 3733MHz

Memory Bus (LPDDR4/ x)

Dual Channel 3733MHz

LPDDR4/x - ChA

LPDDR4/x - ChB

USB2.0

ISH_I2C

DMIC

HDA

USB2.0

USB3.1

SMB

Audio Codec ALC3281 -CG

I2S

I2C

SPK Amp TI TAS2770

USB DCI Debug

MIPI60 Debug

Universal Headset Jack

p.56

p.57

p.79

NB_LID#

I2C

KB Transfer Board

BC Bus

PWM

PS/2

SMBUS

Fan 1

Fan 2

Touchpad

p.77

p.63

C

KB Controller ECE111 7

Acceleromet er LNG2D MTR

Acceleromet er MCube MC3451

p.23,24

2xSpeaker

+3VLP

Hall Sensor YB825 1

D

E

Hinge up

13.3" FHD+/UHD+ Panel eDP v1.4b

Touch Screen Controller

Middle Board

RGBIR Camera Contrlller

p.57

Keyboard

+3VLP

Battery Gauge

Acceleromet er MCube MC3451

p.63

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2020/10/01 2018/10/01

p.38

enable

IR SW

p.39

Compal Secret Data

Deciphered Date

CAM module

CSI

RGBIR Camera

ALS

DMIC FPC

DMIC

2xDMIC

IR LED

P-sensor

Title

P002 - Bl ock Diagra m

Size Document Number Rev

LA-H811P

Date: Sheet of

E

Compal El ectronics, I nc.

2 100Tuesday, December 24, 2019

0.1 (X00)

A

Board ID Table

3.3V +/- 5%Vcc

Board ID

0 1 2 3 4 5 6 7

R

240K +/- 1% 4700p 130K +/- 5% 62K +/- 5% 33K +/- 5%

8.2K +/- 5%

4.3K +/- 5% 2K +/- 5% 1K +/- 5% 4700p

SMBUS Control Table

SOURCE

PCH_SML0CL K

PCH_SML0DATA

PCH_SML1CL K

PCH_SML1DATA

SMBCLK

SMBDATA

EC_SMB03_CLK EC_SMB03_DAT

EC_SMB04_CLK EC_SMB04_DAT

EC_SMB05_CLK EC_SMB05_DAT

EC_SMB10_CLK EC_SMB10_DAT

EC_SMB00_CLK EC_SMB00_DAT

EC_SMB01_CLK EC_SMB01_DAT

1 1

USB 2.0

PCH

MEC5106

DESTINATIONUSB 2.0 PORT#

1

2

3

4

5

6

7

8

9

10

USB DCI Debug

None

Type-C_R

FPR

None

Type-C_L

CAM

BT

4700p 4700p 4700p 4700p 4700p 4700p

C

REV

X00 X01 X02

N/A

PCB Revision

0.1

0.2

0.3

N/A

Check

BATT

PCH

Connec tor

Charger

VCCIN Control lerPDControl ler

V

MIPI6 0

USB/I2C

MUX

BurnSid e Bridge

Reserve

V

Accel

TI Amp.

V

Reserve

V

CLK

DESTINATIONDIFFERENTIAL

WLAN

M.2 SSD

None

Card Reader

None

EC eSPI

CLK

CLKOUT_PCIE 0

CLKOUT_PCIE 1

CLKOUT_PCIE 2

CLKOUT_PCIE 3

CLKOUT_PCIE 4

CLKOUT_PCIE 5

FLEX CLOCKS DESTINATION

ESPI_CLK

PCIE/USB3.1

Flexible I/O

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Interface DESTINATION

PCI-E#1 / USB 3.1#1

PCI-E#2 / USB 3.1#2

PCI-E#3 / USB 3.1#3

PCI-E#4 / USB 3.1#4

PCI-E#5 / USB 3.1#5

PCI-E#6 / USB 3.1#6

PCI-E#7

PCI-E#8

PCI-E#9

PCI-E#10

PCI-E#11 / SATA#0

PCI-E#12 / SATA#1a

PCI-E#13

PCI-E#14

PCI-E#15 / SATA#1b

PCI-E#16 / SATA#2

Thunderbolt

TBT PORT# DESTINATION

0

TBT

1

2

3

Displayport

DDI PORT# DESTINATION

DDI

A

B

None

USB DCI Debug

WLAN PCIe Gen2

None

M.2 SSD

None

Card Reader PCIE GEN2

USB Type-C_L

None

USB Type-C_R

None

4 Lane eDP

None

Symbol Note :

: means de-po p

@

: means Digital Ground

: means Analog Ground

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

2020/10/01 2018/10/01

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

P003 - Notes List

Size

Document Number Re v

LA-H811P

Date : Sheet of

3 100Tuesday, December 24, 2019

0.1 (X00)

5

4

3

2

1

Power Rail

Audio Power Rail

D D

Type-C Port-L

Type-C Port-R

C C

VCCIN

IMVP_VR_ON _EN

1.8V_PRIM_P G

B B

0.6V_VDDQ_EN _P

1.1V_MEM_EN

PL2 TDC 36A Peak Current 62A (MP294 0A) Page: 91,9 2,93

+VCC1.05_OUT_FET

VCCIN_AUX TDC 10A Peak Current 26A (MP29 41) Page: 89,90

+0.6V_VDDQ (LPDDR4X only)

TDC 0.5A Peak C urrent 0.72A (NB691) Page:8 7

+1.1V_MEM

TDC 4.2A Peak Current 6A (RT6243B ) Page:8 6

PD1

Controller TPS65987D H

EC_I2C

PD2

Controller TPS65987D H

UC13 AOZ1334DI-01

UC12 AOZ1334DI-01

UC27 AOZ1334DI-01

VCCST_EN

VCCSTG_EN

VCC_SFR_OC_E N

Modena POWER BLOCK DIAGRAM

B+B+

+VCCST_CPU

+VCCSTG_CPU

+VCC_SFR_OC

2S2P Battery 51W

Buck-boost Charger ISL9538B

(NVDC) Page: 83

B+

ALWON_5VALW

PCH_PRIM_E N

ALWON_3VALW

+5VALW

TDC 5.1A Peak Current 7.3A (NB502) Page:8 5

+1.8VPRIM

TDC 1.9A Peak Current 2.8A (NB691) Page:8 8

+3VALW

TDC 7.4A Peak C urrent 10.5A (NB502) Page:8 4

UPD1 TPS65987D H

UC28 AOZ1336DI

UC22 AOZ1334DI-01

UC25 AOZ1336DI

UC24 AOZ1336DI

UC23 AOZ1334DI-01

U7 SY628 8

U31 AOZ1331DI

U34 AOZ1331DI

UC30 AOZ1336DI

US1 AOZ1336D I

UC31 SY6288

UT1 AOZ1336D I

UT2 AOZ1336D I

U713 AOZ1336DI

U55 SY6288

RUN_ON_P

CPU_C10_GATE#

AUD_PW R_EN

RUN_ON_P

SUS_ON_P

ENVDD

VCCDSW_EN_GPIO

WLAN_PW R_EN

TS_EN_R

RUN_ON_P

RUN_ON_P_R

SD_PWR_EN

3.3V_TBT_L_EN

3.3V_TBT_R _EN

TP_EN

3.3V_CAM_EN

+5VALWB_L_TBT

+5VS

+VCC1P8A

+1.8VS_AUDIO

+1.8VS

+1.8V_MEM

+LCDVDD

+3V_PRIM

+3VALW_DSW

+3VS_WLAN

+3VS_TS

+3VS

+3VS_SSD

+3VS_CR

+3.3V_TBT_ L

+3.3V_TBT_R

+3VS_TP

+CAM_PWR

Q15 SI3457BDV

A A

5

QZ10 SI3457BDV

EN_INVPWR

IRCAM_EN

+INV_PWR_SRC

B+_CAM

4

ALWON_5VALWB

+5VALWB

TDC 3.5A Peak Current 5A (NB502) Page:8 5

3

U60 AOZ1336DI

UPD2 TPS65987D H

U36 AOZ1336DI

RUN_ON_P

AUD_PW R_EN

+5VBS

+5VALWB_R_TBT

+5VS_AUDIO

Security C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2020/10/01 2018/10/01

Deciphered Date

Compal Electronics, Inc.

Title

P004 - Power MAP

Size

Document Number Rev

LA-H811P

Date: S heet of

1

4 100Tuesday, December 24, 2019

0.1 (X00)

5

[AC in] for VBU_L/VBU_R

TBT_VBUS

+3V_LDO

+CHG_VIN_20V

B+

ACAV_INEC Input

ALWON

+3VALW

+5VALW (+5VALWB)

ALW_PWRGD_3V_5V

POWER_SW_IN#

Ta

Tb

Tc

Td

Te

Tf

Tg Tg

Th

200ms < Th

PD Output

CHR Output

D D

EC Output

VR Output

EC Input

[Battery only, AC absent]

CHR Output

B+

PWR_SW_IN#

EC Output

ALWON

VR Output

+3VALW

VR Output

+5VALW (+5VALWB)

VR Output

ALW_PWRGD_3V_5V

EC pay attention timing

VCCDSW_EN_GPIO

+3VALW_DSW/+3V_PRIM(U31 )

EC Output

PCH_DPWROK

PCH Output

SIO_SLP_SUS#

VR Output

+1.8V_PRIM(PU500)

PCH Output

+VCC1.05_OUT _PCH

PCH Output

+VCC1.05_OUT _FET

+VCCST_CPU(U C13)

VR Output

C C

B B

1.8V_PRIM_PG

+VCCIN_AUX( PU900)

PCH Output

VR Output

VCCIN_AUX_VR_PG

PCH_RSMRS T#

EC Output

PCH Output

ESPI_RESET#

EC Output AC_PRES ENT

POWER_SW_IN# 16ms < T < 4s

PCH Output

SIO_SLP_S5#

PCH Output

SIO_SLP_S4#

PCH Output

SIO_SLP_S3#

PCH Output

CPU_C10_GATE#

PCH Output

SIO_SLP_S0#

RUN_ON_ECEC Output

VR Output

+1.1V_MEM(PU700)

+0.6V_VDDQ( PU800)

VR Output

+1.8V_MEM(U C23)

+VCCSTG_CPU (UC12)

+VCC1P8A(UC2 2)

+VCC_SFR_OC( UC27)

+3VS(UC30 )

+1.8VS(UC24)

+5VS(UC28)/+5VBS(U60)

+3VS_SSD(US1)

RUNPWROK(ALL_SYS_PWRGD)EC Input

EC Output

IMVP_VR_ON_P(VCCST_PWRGD)

VR Output

+VCCIN(PU1100)

VR Output

PCH_PWROK_P

CPUPWRGD

EC Output

SYS_PWROK

PCH_PLTRST #_ECPCH Output

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

T27

T28

T29

T30

4

200ms < Th

Td

Te

Tf

T31

T32

T33

T34

T35

3

Power On Sequence

ITEM

Ta Tb Tc Td Te Tf Tg

Th

ITEM

T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37

TBT_VBUS

+3V_LDO

+CHG_VIN_2 0V

B+

ALWON

+3VALW

Measure Point

VCCDSW_EN_GPIO

+3VALW_DSW/+3V_PR IM

PCH_DPWROK

SIO_SLP_SUS#

+1.8V_PRIM

+VCC1.05_OUT_ FET

+1.8V_PRIM

1.8V_PRIM_PG

+VCCIN_AUX

VCCIN_AUX_VR_P G

PCH_RSMRS T#

ESPI_RESET#

SIO_SLP_S5#

SIO_SLP_S4#

RUN_ON_EC

+3VS

RUNPWR OK

IMVP_VR_ON_P

+VCCIN

PCH_PWROK_P

CPUPWR GD

SYS_PWRO K

[AC in]

+3V_LDO

To

+CHG_VIN_2 0V

To

B+

To

ACAV_IN

To

ALWONACAV_IN

To

+3VALW

To

+5VALW ( +5VALWB) ALWON

To

ALW_PWRGD_3V_5V

To

+3VALW_DSW/+3V_P RIM

To

PCH_DPWROK

To

SIO_SLP_SUS#

To

+1.8V_PRIM

To

+VCC1.05_OUT_ PCH

To

+VCC1.05_OUT_ FET

To

+VCCST_CPU

To

1.8V_PRIM_PG

To

+VCCIN_AUX

To

VCCIN_AUX_VR_P G

To

PCH_RSMRS T#

To

ESPI_RESET#

To

AC_PRESENT

To

SIO_SLP_S4#

To

SIO_SLP_S3#

To

CPU_C10_GATE #

To

SIO_SLP_S0#

To

RUN_ON_EC

To

+1.1V_MEM

To

+0.6V_VDDQ

To

+1.8V_MEM

To

+1.8V_MEM

To

+VCC1P8A

To

+VCC_SFR_OC

To

+3VS

To

+1.8VS

To

+5VS/+5V BS

To

+3.3VDX_SSD

To

+SSD_PWR2

To

+SSD_PWR3

To

RUNPWR OK

To

IMVP_VR_ON_P

To

+VCCIN

To

PCH_PWROK_P

To

CPUPWR GD

To

SYS_PWRO K

To

PCH_PLTRST#_E C

To

TimeMeasure Point

Time

[Battery only, AC absent]

ITEM

Measure Point

B+

Tc

POWER_SW_IN# Low pluse width

Th

POWER_SW_IN#

Td

ALWON +3VALW

Te Tf

+3VALW ALW_PWRGD_3V_5V

Tg

To

To To To To

2

POWER_SW_IN#

ALWON

+5VALW ( +5VALWB)

1

Power Down Sequence

EC pay attention timing

Time

PCH_PLTRST#

CPUPWRGD

PCH_CLK_OUTP UTS

SIO_SLP_S3#

CPU_C10_GATE#

SYS_PWROK

PCH_PWROK_P

IMVP_VR_ON_P(VCCST_PWRGD)

RUNPWROK(ALL_SYS_PWRGD)

+VCCIN

3VS/+1.8VS/+5V S/+5VBS

+VCCSTG_CPU

SIO_SLP_S4#

+1.1V_MEM

+0.6V_VDDQ

+1.8V_MEM

+VCC_SFR_OC

SIO_SLP_S5#

+VCC1P05_OUTPUT_PLL

PCH_RSMRS T#

PCH_DPWROK

+3VALW_DSW/+3 V_PRIM

SIO_SLP_SUS#

ESPI_RESET#

SIO_SLP_S0#

+1.8V_PRIM

+VCC1.05_OUT _PCH

+VCCIN_AUX

+VCCST_CPU

SUSCLK

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2020/10 /01 2018/10 /01

Deciphered Date

Compal Electronics, Inc.

Title

P005 - Power Sequence

Size

Document Number Rev

LA-H811P

Date: Sheet of

1

0.1 (X00)

5 100Tuesday, December 24, 2019

5

D D

+3V_PRIM

C C

DVT1_5 7

RH74210K_0201_5%

12

RH60310K_0201_5%

12

RH675100K_0201_5%

12

RH717100K_0201_5% @

12

RH718100K_0201_5% @

12

USB_OC1#

USB_OC2#

EDP_HPD

CPU_TCP0_HPD

USB_OC1#

eDP

4

UC1A

EDP_TXN0<38>

EDP_TXP0<38> EDP_TXN1<38> EDP_TXP1<38> EDP_TXN2<38> EDP_TXP2<38> EDP_TXN3<38> EDP_TXP3<38>

EDP_AUXN<38> EDP_AUXP<38>

TBT_0_LSX_TX<46> TBT_0_LSX_RX<46>

TBT_2_LSX_TX<48> TBT_2_LSX_RX<48>

EDP_HPD<38,58>

TS_DET#<38>

TS_INT#<38>

ENVDD_PCH<38> PANEL_BKLEN<10,38> EDP_BIA_PWM<38>

TP99

TP69

TBT_0_LSX_RX

TBT_2_LSX_RX

EDP_HPD

CPU_TCP0_HPD

USB_OC1# USB_OC2#

PAD~D

1

PAD~D

1

RC3150_0201_1%

12

TP@

Y5

DDIA_TXN_0

Y3

DDIA_TXP_0

Y1

DDIA_TXN_1

Y2

DDIA_TXP_1

V2

DDIA_TXN_2

V1

DDIA_TXP_2

V3

DDIA_TXN_3

V5

DDIA_TXP_3

W4

DDIA_AUX_N

W3

DDIA_AUX_P

AE3

DDIB_TXN_0

AE5

DDIB_TXP_0

AE2

DDIB_TXN_1

AE1

DDIB_TXP_1

AC5

DDIB_TXN_2

AC3

DDIB_TXP_2

AC1

DDIB_TXN_3

AC2

DDIB_TXP_3

AD3

DDIB_AUX_N

AD4

DDIB_AUX_P

DP15

GPP_E22/DDPA_CTRLCLK/PCIE_LNK_DOWN

DJ17

GPP_E23/DDPA_CTRLDATA/BK4/SBK4

DL40

GPP_H16/DDPB_CTRLCLK

DP42

GPP_H17/DDPB_CTRLDATA

DL17

GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD

DK17

GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD

DN17

GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD

DP17

GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD

DK34

GPP_D9/ISH_SPI_CS_N/DDP3_CTRLCLK/GSPI2_CS0_N/TBT_LSX2_TXD

DL34

GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/GSPI2_CLK/TBT_LSX2_RXD

DN33

GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/GSPI2_MISO/TBT_LSX3_TXD

DL33

GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/GSPI2_MOSI/TBT_LSX3_RXD

DW11

GPP_E14/DPPE_HPDA/DISP_MISCA

CV42

GPP_A18/DDSP_HPDB/DISP_MISCB

CV39

GPP_A19/DDSP_HPD1/DISP_MISC1

CY43

GPP_A20/DDSP_HPD2/DISP_MISC2

CR41

GPP_A14/USB_OC1_N/DDSP_HPD3/DISP_MISC3

CT41

GPP_A15/USB_OC2_N/DDSP_HPD4/DISP_MISC4

DV14

GPP_E17

DN21

EDP_VDDEN

DL19

EDP_BKLTEN

DU19

J3

D2 R2

ICL-U_BGA1526

@

EDP_BKLTCTL RSVD_1

DISP_UTILS DISP_RCOMP

RSVD_1

DISP_UTILS KB_DET# DP_RCOMP

3

BB5

TCP0_TX_N0

BB6

TCP0_TX_P0

AV6

TCP0_TX_N1

AV5

TCP0_TX_P1

BH2

TCP0_TXRX_N0

BH1

TCP0_TXRX_P0

BF1

TCP0_TXRX_N1

BF2

TCP0_TXRX_P1

AY5

TCP0_AUX_N

AY6

TBT / USB / DP

GPP_A17/DISP_MISCC

TCP0_AUX_P

TCP1_TX_N0 TCP1_TX_P0 TCP1_TX_N1

TCP1_TX_P1 TCP1_TXRX_N0 TCP1_TXRX_P0 TCP1_TXRX_N1 TCP1_TXRX_P1

TCP1_AUX_N TCP1_AUX_P

TCP2_TX_N0

TCP2_TX_P0

TCP2_TX_N1

TCP2_TX_P1 TCP2_TXRX_N0 TCP2_TXRX_P0 TCP2_TXRX_N1 TCP2_TXRX_P1

TCP2_AUX_N TCP2_AUX_P

TCP3_TX_N0

TCP3_TX_P0

TCP3_TX_N1

TCP3_TX_P1 TCP3_TXRX_N0 TCP3_TXRX_P0 TCP3_TXRX_N1 TCP3_TXRX_P1

TCP3_AUX_N TCP3_AUX_P

TC_RCOMP_N TC_RCOMP_P

GPP_A21 GPP_A22

AR5 AR6 AL5 AL3 BD2 BD1 BB1 BB2

AN3 AN5

BF6 BF5 BJ5 BJ6 BL1 BL2 BM2 BM1

BG6 BG5

BP6 BP5 BV5 BV6 BR1 BR2 BT2 BT1

BT6 BT5

TCRCOMP_DN

AY1

TCRCOMP_DP

AY2

CT38

DVT1_42 : remove RTC

CV43 CV41

DDI

1 0f 19

2

RC1 150_0201_1%

1 2

TBT_0_TTX_DRX_N0<46> TBT_0_TTX_DRX_P0<46> TBT_0_TTX_DRX_N1<46> TBT_0_TTX_DRX_P1<46> TBT_0_TRX_DTX_N0<46> TBT_0_TRX_DTX_P0<46> TBT_0_TRX_DTX_N1<46> TBT_0_TRX_DTX_P1<46>

TBT_0_AUXN <46> TBT_0_AUXP <46>

TBT_2_TTX_DRX_N0<48> TBT_2_TTX_DRX_P0<48> TBT_2_TTX_DRX_N1<48> TBT_2_TTX_DRX_P1<48> TBT_2_TRX_DTX_N0<48> TBT_2_TRX_DTX_P0<48> TBT_2_TRX_DTX_N1<48> TBT_2_TRX_DTX_P1<48>

TBT_2_AUXN <48> TBT_2_AUXP <48>

DVT1_31, DVT1_67

3.3V_CAM_EN <71> KB_DET# <63>

TBT_L

TBT_R

1

RH672 10K_0201_5%

1 2

+3V_PRIM

B B

TBT LSX #0 PINS VCCIO CONFIGURATION

+3V_PRIM +3V_PRIM

12

R6172

@

4.7K_0201_5%

TBT_0_LSX_RX TBT_2_LSX_RX

RC691 20K_0201_5%

1 2

HIGH

LOW

3.3V

1.8V

12

R6174

@

4.7K_0201_5%

RC693 20K_0201_5%

1 2

TBT LSX #2 PINS VCCIO CONFIGURATION

HIGH

LOW

3.3V

1.8V

PLACE CLOSE TO THE SIGNAL TO AVOID STUB

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

2020/10/01 2018/10/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

P006 - ICL-U(1/13)TCSS,EDP

Size

Document Number Re v

LA-H811P

Date : Sheet of

1

6 100Tuesday, December 24, 2019

0.1 (X00)

5

4

3

2

1

Memory connection refer 573975 Rev1P1

D D

UC1B

LP4(NIL) / DDR4(NIL) LP4(NIL) / DDR4(NIL)

DDR_A_D0_0<23> DDR_A_D0_1<23> DDR_A_D0_2<23> DDR_A_D0_3<23> DDR_A_D0_4<23> DDR_A_D0_5<23> DDR_A_D0_6<23> DDR_A_D0_7<23> DDR_A_D1_0<23> DDR_A_D1_1<23> DDR_A_D1_2<23> DDR_A_D1_3<23> DDR_A_D1_4<23> DDR_A_D1_5<23> DDR_A_D1_6<23> DDR_A_D1_7<23> DDR_A_D2_0<23> DDR_A_D2_1<23> DDR_A_D2_2<23> DDR_A_D2_3<23>

C C

B B

A A

DDR_A_D2_4<23> DDR_A_D2_5<23> DDR_A_D2_6<23> DDR_A_D2_7<23> DDR_A_D3_0<23> DDR_A_D3_1<23> DDR_A_D3_2<23> DDR_A_D3_3<23> DDR_A_D3_4<23> DDR_A_D3_5<23> DDR_A_D3_6<23> DDR_A_D3_7<23> DDR_B_D0_0<23> DDR_B_D0_1<23> DDR_B_D0_2<23> DDR_B_D0_3<23> DDR_B_D0_4<23> DDR_B_D0_5<23> DDR_B_D0_6<23> DDR_B_D0_7<23> DDR_B_D1_0<23> DDR_B_D1_1<23> DDR_B_D1_2<23> DDR_B_D1_3<23> DDR_B_D1_4<23> DDR_B_D1_5<23> DDR_B_D1_6<23> DDR_B_D1_7<23> DDR_B_D2_0<23> DDR_B_D2_1<23> DDR_B_D2_2<23> DDR_B_D2_3<23> DDR_B_D2_4<23> DDR_B_D2_5<23> DDR_B_D2_6<23> DDR_B_D2_7<23> DDR_B_D3_0<23> DDR_B_D3_1<23> DDR_B_D3_2<23> DDR_B_D3_3<23> DDR_B_D3_4<23> DDR_B_D3_5<23> DDR_B_D3_6<23> DDR_B_D3_7<23>

DDR_COMP_0

RC12100_0201_1%

12

DDR_COMP_1

RC13100_0201_1%

12

DDR_COMP_2

RC14100_0201_1%

12

CA48

DDRA_DQ0_0/DDR0_DQ0_0

CA47

DDRA_DQ0_1/DDR0_DQ0_1

CA49

DDRA_DQ0_2/DDR0_DQ0_2

BV49

DDRA_DQ0_3/DDR0_DQ0_3

CA45

DDRA_DQ0_4/DDR0_DQ0_4

BV47

DDRA_DQ0_5/DDR0_DQ0_5

BV45

DDRA_DQ0_6/DDR0_DQ0_6

BV48

DDRA_DQ0_7/DDR0_DQ0_7

CC42

DDRA_DQ1_0/DDR0_DQ1_0

CC39

DDRA_DQ1_1/DDR0_DQ1_1

CC43

DDRA_DQ1_2/DDR0_DQ1_2

CE38

DDRA_DQ1_3/DDR0_DQ1_3

CC38

DDRA_DQ1_4/DDR0_DQ1_4

CE39

DDRA_DQ1_5/DDR0_DQ1_5

CE42

DDRA_DQ1_6/DDR0_DQ1_6

CE43

DDRA_DQ1_7/DDR0_DQ1_7

BT48

DDRA_DQ2_0/DDR0_DQ2_0

BT47

DDRA_DQ2_1/DDR0_DQ2_1

BT49

DDRA_DQ2_2/DDR0_DQ2_2

BN49

DDRA_DQ2_3/DDR0_DQ2_3

BT45

DDRA_DQ2_4/DDR0_DQ2_4

BN47

DDRA_DQ2_5/DDR0_DQ2_5

BN45

DDRA_DQ2_6/DDR0_DQ2_6

BN48

DDRA_DQ2_7/DDR0_DQ2_7

BV42

DDRA_DQ3_0/DDR0_DQ3_0

BV39

DDRA_DQ3_1/DDR0_DQ3_1

BV43

DDRA_DQ3_2/DDR0_DQ3_2

BW38

DDRA_DQ3_3/DDR0_DQ3_3

BV38

DDRA_DQ3_4/DDR0_DQ3_4

BW39

DDRA_DQ3_5/DDR0_DQ3_5

BW42

DDRA_DQ3_6/DDR0_DQ3_6

BW43

DDRA_DQ3_7/DDR0_DQ3_7

AY48

DDRB_DQ0_0/DDR0_DQ4_0

AY47

DDRB_DQ0_1/DDR0_DQ4_1

AY49

DDRB_DQ0_2/DDR0_DQ4_2

AU45

DDRB_DQ0_3/DDR0_DQ4_3

AY45

DDRB_DQ0_4/DDR0_DQ4_4

AU47

DDRB_DQ0_5/DDR0_DQ4_5

AU48

DDRB_DQ0_6/DDR0_DQ4_6

AU49

DDRB_DQ0_7/DDR0_DQ4_7

AY42

DDRB_DQ1_0/DDR0_DQ5_0

AY38

DDRB_DQ1_1/DDR0_DQ5_1

AY43

DDRB_DQ1_2/DDR0_DQ5_2

BB39

DDRB_DQ1_3/DDR0_DQ5_3

AY39

DDRB_DQ1_4/DDR0_DQ5_4

BB38

DDRB_DQ1_5/DDR0_DQ5_5

BB42

DDRB_DQ1_6/DDR0_DQ5_6

BB43

DDRB_DQ1_7/DDR0_DQ5_7

AR48

DDRB_DQ2_0/DDR0_DQ6_0

AR47

DDRB_DQ2_1/DDR0_DQ6_1

AR49

DDRB_DQ2_2/DDR0_DQ6_2

AM45

DDRB_DQ2_3/DDR0_DQ6_3

AR45

DDRB_DQ2_4/DDR0_DQ6_4

AM47

DDRB_DQ2_5/DDR0_DQ6_5

AM48

DDRB_DQ2_6/DDR0_DQ6_6

AM49

DDRB_DQ2_7/DDR0_DQ6_7

AT42

DDRB_DQ3_0/DDR0_DQ7_0

AT39

DDRB_DQ3_1/DDR0_DQ7_1

AR43

DDRB_DQ3_2/DDR0_DQ7_2

AT38

DDRB_DQ3_3/DDR0_DQ7_3

AR38

DDRB_DQ3_4/DDR0_DQ7_4

AR39

DDRB_DQ3_5/DDR0_DQ7_5

AR42

DDRB_DQ3_6/DDR0_DQ7_6

AT43

DDRB_DQ3_7/DDR0_DQ7_7

D47

DDR_RCOMP_0

E46

DDR_RCOMP_1

C47

DDR_RCOMP_2

ICL-U_BGA1526

@

2 of 19

DDRA_CLK_N/DDR0_CLK_N_0 DDRA_CLK_P/DDR0_CLK_P_0 DDRB_CLK_N/DDR0_CLK_N_1 DDRB_CLK_P/DDR0_CLK_P_1

DDRA_CKE0/DDR0_CKE0

DDRA_CKE1/NC DDRB_CKE0/NC

DDRB_CKE1/DDR0_CKE1

DDRA_CS_0/DDR0_CS#0

DDRA_CS_1/NC DDRB_CS_0/NC

DDRB_CS_1/DDR0_CS#1

DDRB_CA4/DDR0_BA0

NC/DDR0_BA1

DDRA_CA5/DDR0_BG0

NC/DDR0_BG1

NC/DDR0_MA0 NC/DDR0_MA1

DDRB_CA5/DDR0_MA2

NC/DDR0_MA3

NC/DDR0_MA4 DDRA_CA0/DDR0_MA5 DDRA_CA2/DDR0_MA6 DDRA_CA4/DDR0_MA7 DDRA_CA3/DDR0_MA8 DDRA_CA1/DDR0_MA9

NC/DDR0_MA10 NC/DDR0_MA11 NC/DDR0_MA12

DDRB_CA0/DDR0_MA13

DDRB_CA2/DDR0_MA14WE# DDRB_CA1/DDR0_MA15CAS# DDRB_CA3/DDR0_MA16RAS#

NC/DDR0_ODT_0 NC/DDR0_ODT_1

DDRA_DQSN_0/DDR0_DQSN_0 DDRA_DQSP_0/DDR0_DQSP_0 DDRA_DQSN_1/DDR0_DQSN_1 DDRA_DQSP_1/DDR0_DQSP_1 DDRA_DQSN_2/DDR0_DQSN_2 DDRA_DQSP_2/DDR0_DQSP_2 DDRA_DQSN_3/DDR0_DQSN_3 DDRA_DQSP_3/DDR0_DQSP_3 DDRB_DQSN_0/DDR0_DQSN_4 DDRB_DQSP_0/DDR0_DQSP_4 DDRB_DQSN_1/DDR0_DQSN_5 DDRB_DQSP_1/DDR0_DQSP_5 DDRB_DQSN_2/DDR0_DQSN_6 DDRB_DQSP_2/DDR0_DQSP_6 DDRB_DQSN_3/DDR0_DQSN_7 DDRB_DQSP_3/DDR0_DQSP_7

NC/DDR0_PAR

NC/DDR0_ACT#

NC/DDR0_ALERT#

DDR0_VREF_CA DDR1_VREF_CA

DDR_VTT_CTL

DRAM_RESET#

RSVD_73

BL48 BL47 BF42 BF43

BG49 BJ47 BF38 BF41

BM38 BM42 BP42 BG42

BM43 BG39

BB49 BD47

BB48 BL49 BG38 BL45 BJ46 BG48 BE45 BG45 BG47 BE47 BJ38 BB47 BE48 BM39 BG43 BJ42 BM41

BJ39 BB45

BY47 BY46 CC41 CE41 BR47 BR46 BV41 BW41 AV46 AV47 AY41 BB41 AN46 AN47 AR41 AT41

BF39

BF39,BE49 SDS CRB P.8 NC

BE49

M_0_ALERT_N

BD46

M38 C44

M38,C44,B45 SDS CRB P.8 NC

B45 M39 DK47

DDR_DRAMRST#

DDR_A_CLK# <23> DDR_A_CLK <23> DDR_B_CLK# <23> DDR_B_CLK <23>

DDR_A_CKE0 <23> DDR_A_CKE1 <23> DDR_B_CKE0 <23> DDR_B_CKE1 <23>

DDR_A_CS#0 <23> DDR_A_CS#1 <23> DDR_B_CS#0 <23> DDR_B_CS#1 <23>

DDR_B_CA4 <23>

DDR_A_CA5 <23>

DDR_B_CA5 <23>

DDR_A_CA0 <23> DDR_A_CA2 <23> DDR_A_CA4 <23> DDR_A_CA3 <23> DDR_A_CA1 <23>

DDR_B_CA0 <23> DDR_B_CA2 <23> DDR_B_CA1 <23> DDR_B_CA3 <23>

DDR_A_DQS#0 <23> DDR_A_DQS0 <23> DDR_A_DQS#1 <23> DDR_A_DQS1 <23> DDR_A_DQS#2 <23> DDR_A_DQS2 <23> DDR_A_DQS#3 <23> DDR_A_DQS3 <23> DDR_B_DQS#0 <23> DDR_B_DQS0 <23> DDR_B_DQS#1 <23> DDR_B_DQS1 <23> DDR_B_DQS#2 <23> DDR_B_DQS2 <23> DDR_B_DQS#3 <23> DDR_B_DQS3 <23>

RH11 0_0201_5%@

1 2

M39 (DDR_VTT_CTL) is DDR4 System Memory Power Gate Control Buf f er use , L PDDR4/x don' t use. Processor EDS Rev0p7 P.118,119 #572795 SDS CRB NC

C44(DDR0_VREF_CA),B45(DDR1_VREF_CA) for DDR4 used only LPDDR4/4x has all Vref Internal inside the DRAMS Rev.0.91 PDG P.112 #572907

+1.1V_MEM

1 2

RH42 0_0201_5%@

RH12 470_0201_1%

1 2

DDR_DRAMRST#_R < 23,24>

1

CC740

@

0.1U_0201_10V6K

2

Security Classification

2020/10/ 01 2018/10/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2020/10/ 01 2018/10/ 01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

P007 - ICL-U(2/13)LPDDR4/x

LA-H811P

7 100Tuesday, December 24, 2019

1

0.1 (X00)

5

D D

4

3

2

1

Memory connection refer 573975 Rev1P1

UC1C

LP4(NIL) / DDR4(NIL)

DDR_C_D0_0<24> DDR_C_D0_1<24> DDR_C_D0_2<24> DDR_C_D0_3<24> DDR_C_D0_4<24> DDR_C_D0_5<24> DDR_C_D0_6<24> DDR_C_D0_7<24> DDR_C_D1_0<24> DDR_C_D1_1<24> DDR_C_D1_2<24> DDR_C_D1_3<24> DDR_C_D1_4<24> DDR_C_D1_5<24> DDR_C_D1_6<24> DDR_C_D1_7<24>

C C

B B

DDR_C_D2_0<24> DDR_C_D2_1<24> DDR_C_D2_2<24> DDR_C_D2_3<24> DDR_C_D2_4<24> DDR_C_D2_5<24> DDR_C_D2_6<24> DDR_C_D2_7<24> DDR_C_D3_0<24> DDR_C_D3_1<24> DDR_C_D3_2<24> DDR_C_D3_3<24> DDR_C_D3_4<24> DDR_C_D3_5<24> DDR_C_D3_6<24> DDR_C_D3_7<24> DDR_D_D0_0<24> DDR_D_D0_1<24> DDR_D_D0_2<24> DDR_D_D0_3<24> DDR_D_D0_4<24> DDR_D_D0_5<24> DDR_D_D0_6<24> DDR_D_D0_7<24> DDR_D_D1_0<24> DDR_D_D1_1<24> DDR_D_D1_2<24> DDR_D_D1_3<24> DDR_D_D1_4<24> DDR_D_D1_5<24> DDR_D_D1_6<24> DDR_D_D1_7<24> DDR_D_D2_0<24> DDR_D_D2_1<24> DDR_D_D2_2<24> DDR_D_D2_3<24> DDR_D_D2_4<24> DDR_D_D2_5<24> DDR_D_D2_6<24> DDR_D_D2_7<24> DDR_D_D3_0<24> DDR_D_D3_1<24> DDR_D_D3_2<24> DDR_D_D3_3<24> DDR_D_D3_4<24> DDR_D_D3_5<24> DDR_D_D3_6<24> DDR_D_D3_7<24>

AK48

DDRC_DQ0_0/DDR1_DQ0_0

AK45

DDRC_DQ0_1/DDR1_DQ0_1

AK49

DDRC_DQ0_2/DDR1_DQ0_2

AG47

DDRC_DQ0_3/DDR1_DQ0_3

AK47

DDRC_DQ0_4/DDR1_DQ0_4

AG45

DDRC_DQ0_5/DDR1_DQ0_5

AG48

DDRC_DQ0_6/DDR1_DQ0_6

AG49

DDRC_DQ0_7/DDR1_DQ0_7

AJ38

DDRC_DQ1_0/DDR1_DQ1_0

AL39

DDRC_DQ1_1/DDR1_DQ1_1

AJ39

DDRC_DQ1_2/DDR1_DQ1_2

AL43

DDRC_DQ1_3/DDR1_DQ1_3

AL38

DDRC_DQ1_4/DDR1_DQ1_4

AJ42

DDRC_DQ1_5/DDR1_DQ1_5

AL42

DDRC_DQ1_6/DDR1_DQ1_6

AJ43

DDRC_DQ1_7/DDR1_DQ1_7

AB49

DDRC_DQ2_0/DDR1_DQ2_0

AB48

DDRC_DQ2_1/DDR1_DQ2_1

AE49

DDRC_DQ2_2/DDR1_DQ2_2

AE47

DDRC_DQ2_3/DDR1_DQ2_3

AE48

DDRC_DQ2_4/DDR1_DQ2_4

AB47

DDRC_DQ2_5/DDR1_DQ2_5

AB45

DDRC_DQ2_6/DDR1_DQ2_6

AE45

DDRC_DQ2_7/DDR1_DQ2_7

AD38

DDRC_DQ3_0/DDR1_DQ3_0

AD39

DDRC_DQ3_1/DDR1_DQ3_1

AE39

DDRC_DQ3_2/DDR1_DQ3_2

AE43

DDRC_DQ3_3/DDR1_DQ3_3

AE38

DDRC_DQ3_4/DDR1_DQ3_4

AD43

DDRC_DQ3_5/DDR1_DQ3_5

AD42

DDRC_DQ3_6/DDR1_DQ3_6

AE42

DDRC_DQ3_7/DDR1_DQ3_7

J48

DDRD_DQ0_0/DDR1_DQ4_0

J45

DDRD_DQ0_1/DDR1_DQ4_1

J49

DDRD_DQ0_2/DDR1_DQ4_2

G47

DDRD_DQ0_3/DDR1_DQ4_3

J47

DDRD_DQ0_4/DDR1_DQ4_4

G45

DDRD_DQ0_5/DDR1_DQ4_5

G48

DDRD_DQ0_6/DDR1_DQ4_6

E48

DDRD_DQ0_7/DDR1_DQ4_7

J38

DDRD_DQ1_0/DDR1_DQ5_0

G39

DDRD_DQ1_1/DDR1_DQ5_1

G38

DDRD_DQ1_2/DDR1_DQ5_2

G42

DDRD_DQ1_3/DDR1_DQ5_3

J39

DDRD_DQ1_4/DDR1_DQ5_4

J42

DDRD_DQ1_5/DDR1_DQ5_5

G43

DDRD_DQ1_6/DDR1_DQ5_6

J43

DDRD_DQ1_7/DDR1_DQ5_7

B43

DDRD_DQ2_0/DDR1_DQ6_0

D43

DDRD_DQ2_1/DDR1_DQ6_1

A43

DDRD_DQ2_2/DDR1_DQ6_2

C40

DDRD_DQ2_3/DDR1_DQ6_3

C43

DDRD_DQ2_4/DDR1_DQ6_4

D40

DDRD_DQ2_5/DDR1_DQ6_5

B40

DDRD_DQ2_6/DDR1_DQ6_6

A40

DDRD_DQ2_7/DDR1_DQ6_7

B35

DDRD_DQ3_0/DDR1_DQ7_0

D35

DDRD_DQ3_1/DDR1_DQ7_1

A35

DDRD_DQ3_2/DDR1_DQ7_2

D38

DDRD_DQ3_3/DDR1_DQ7_3

C35

DDRD_DQ3_4/DDR1_DQ7_4

C38

DDRD_DQ3_5/DDR1_DQ7_5

B38

DDRD_DQ3_6/DDR1_DQ7_6

A38

DDRD_DQ3_7/DDR1_DQ7_7

ICL-U_BGA1526

@

3 of 19

LP4(NIL) / DDR4(NIL)

DDRC_CLK_N/DDR1_CLK_N_0

DDRC_CLK_P/DDR1_CLK_P_0

DDRD_CLK_N/DDR1_CLK_N_1

DDRD_CLK_P/DDR1_CLK_P_1

DDRC_CKE0/DDR1_CKE0

DDRC_CKE1/NC DDRD_CKE0/NC

DDRD_CKE1/DDR1_CKE1

DDRC_CS_0/DDR1_CS#0

DDRC_CS_1/NC DDRD_CS_0/NC

DDRD_CS_1/DDR1_CS#1

DDRD_CA4/DDR1_BA0

NC/DDR1_BA1

DDRC_CA5/DDR1_BG0

NC/DDR1_BG1

NC/DDR1_MA0 NC/DDR1_MA1

DDRD_CA5/DDR1_MA2

NC/DDR1_MA3

NC/DDR1_MA4 DDRC_CA0/DDR1_MA5 DDRC_CA2/DDR1_MA6 DDRC_CA4/DDR1_MA7 DDRC_CA3/DDR1_MA8 DDRC_CA1/DDR1_MA9

NC/DDR1_MA10 NC/DDR1_MA11 NC/DDR1_MA12

DDRD_CA0/DDR1_MA13

DDRD_CA2/DDR1_MA14WE# DDRD_CA1/DDR1_MA15CAS# DDRD_CA3/DDR1_MA16RAS#

NC/DDR1_ODT_0 NC/DDR1_ODT_1

DDRC_DQSN_0/DDR1_DQSN_0 DDRC_DQSP_0/DDR1_DQSP_0 DDRC_DQSN_1/DDR1_DQSN_1 DDRC_DQSP_1/DDR1_DQSP_1 DDRC_DQSN_2/DDR1_DQSN_2 DDRC_DQSP_2/DDR1_DQSP_2 DDRC_DQSN_3/DDR1_DQSN_3 DDRC_DQSP_3/DDR1_DQSP_3 DDRD_DQSN_0/DDR1_DQSN_4 DDRD_DQSP_0/DDR1_DQSP_4 DDRD_DQSN_1/DDR1_DQSN_5 DDRD_DQSP_1/DDR1_DQSP_5 DDRD_DQSN_2/DDR1_DQSN_6

DDRD_DQSP_2/DDR1_DQSP_6 DDRD_DQSN_3/DDR1_DQSN_7 DDRD_DQSP_3/DDR1_DQSP_7

NC/DDR1_PAR

NC/DDR1_ACT#

NC/DDR1_ALERT#

Y48 Y47 M43 M42

U45 V46 M41 P43

V42 V39 Y39 T39

T38 T42

R45 N47

P42 Y49 U48 Y45 U47 R49 U49 M47 M45 R47 P39 N46 R48 Y41 V41 Y42 V47

V43 V38

AH46 AH47 AJ41 AL41 AC47 AC46 AE41 AD41 H47 H46 G41 J41 C42 D42 D36 C36

P38 M48 M49

P38,M48 SSD CRB NC

M_1_ALERT_N

RH13 0_0201_5%@

DDR_C_CLK# <24> DDR_C_CLK <24> DDR_D_CLK# <24> DDR_D_CLK <24>

DDR_C_CKE0 <24> DDR_C_CKE1 <24> DDR_D_CKE0 <24> DDR_D_CKE1 <24>

DDR_C_CS#0 <24> DDR_C_CS#1 <24> DDR_D_CS#0 <24> DDR_D_CS#1 <24>

DDR_D_CA4 <24>

DDR_C_CA5 <24>

DDR_D_CA5 <24>

DDR_C_CA0 <24> DDR_C_CA2 <24> DDR_C_CA4 <24> DDR_C_CA3 <24> DDR_C_CA1 <24>

DDR_D_CA0 <24> DDR_D_CA2 <24> DDR_D_CA1 <24> DDR_D_CA3 <24>

DDR_C_DQS#0 <24> DDR_C_DQS0 <24> DDR_C_DQS#1 <24> DDR_C_DQS1 <24> DDR_C_DQS#2 <24> DDR_C_DQS2 <24> DDR_C_DQS#3 <24> DDR_C_DQS3 <24> DDR_D_DQS#0 <24> DDR_D_DQS0 <24> DDR_D_DQS#1 <24> DDR_D_DQS1 <24> DDR_D_DQS#2 <24> DDR_D_DQS2 <24> DDR_D_DQS#3 <24> DDR_D_DQS3 <24>

12

A A

Security Classification

2020/10/ 01 2018/10/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2020/10/ 01 2018/10/ 01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

P008 - ICL-U(3/13)LPDDR4/x

LA-H811P

8 100Tuesday, December 24, 2019

1

0.1 (X00)

5

BOOT HALT

SPI0_MOSI(NO INTERNAL PU/PD)

0 = Enable

1 = Disable

RH643 100K_0201_5%

1 2

RH641 4.7K_0201_5%@

D D

1 2

CONSENT STRAP

SPI0_IO2(NO INTERNAL P U/PD)

0 = Enable

1 = Disable

RH141 100K_0201_5%

1 2

RH142 4.7K_0201_5%@

1 2

+V3.3A_1.8A_PCH_SPI +V3.3A_1.8A_PCH_SPI+V3.3A_1.8A_PCH_SPI

4

A0 PERSONALITY STRAP

SPI0_I O3

0 = Enable

1 = Disable

RH635 100K_0201_5%

1 2

RH636 100K_0201_5%@

1 2

3

TLS CONFIDENTIALITY

GPP_C2/SMBALERT#(INTERNAL PD 20K)

0 = TLS CONFIDENTIALITY DISABLE

1 = TLS CONFIDENTIALITY ENABLE

GPP_C2

RH692 4.7K_0201_5%

1 2

2

ESPI OR EC LESS

GPP_C5 (Internal 20 K internal Pull Down): SML0ALERT#

0 = Enable eSPI. (Default)

1 = Disable eSPI.

RH666 4.7K_0201_5%@

GPP_C5SOC_SPI_0_D2 SOC_SPI_0_D3SOC_SPI_0_D0

RH98 20K_0 201_5%@

1 2

+3V_PRIM+3V_PRIM

1

SOC_SPI_0_CLK SOC_SPI_0_D0 SOC_SPI_0_D1 SOC_SPI_0_D2 SOC_SPI_0_D3 SOC_SPI_0_CS#0 SOC_SPI_0_CS#1 SOC_SPI_0_CS#2

SECURE_BIOS_BIO

RH687 100K_0201_5%

MIPI60_SPI0_MOSI<7 9>

MIPI60_SPI0_IO2<79>

1 2

MIPI60@

1 2

MIPI60@

RH6401K_0201_5%

RH6341K_0201_5%

SOC_SPI_0_CLK

SOC_SPI_0_D0

SOC_SPI_0_D2

SOC_SPI_0_CLK_R

RH719 4.99_0201_1%

SOC_SPI_0_CLK_R<66> SOC_SPI_0_D0_R<66> SOC_SPI_0_D1_R<66>

SOC_SPI_0_D0_R SOC_SPI_0_D1_R SOC_SPI_0_D2_R SOC_SPI_0_D3_R SOC_SPI_0_CS#0_R SOC_SPI_0_CS#1_R

1 2

RH720 4.99_0201_1%

1 2

RH721 4.99_0201_1%

1 2

RH722 4.99_0201_1%

1 2

RH723 4.99_0201_1%

1 2

RH736 0_0201_5%@

1 2

RH735 0_0201_5%@

1 2

SOC_SPI_0_CS#2<66>

DVT2_04

RH750 0_0201_5%

S_BIO<39>

1 2

NO support C-Link

C C

SPI_0_D0_ROM SPI_0_CLK_ROM SPI_0_D1_ROM SPI_0_D2_ROM SPI_0_D3_ROM

Closed to ROM

RH23 49.9_02 01_1%

1 2

RH24 49.9_02 01_1%

1 2

RH25 49.9_02 01_1%

1 2

RH26 49.9_02 01_1%

1 2

RH27 49.9_02 01_1%

1 2

SOC_SPI_0_D0_R SOC_SPI_0_CLK_R SOC_SPI_0_D1_R SOC_SPI_0_D2_R SOC_SPI_0_D3_R

Serial Peripheral Interface (SPI) Topology Guidelines

PCH SPI

NPI pop D20 MP pop RC745

DVT1_23

PVT_05

D20

SPI ROM ( 32MByte ) ROM is Quad SPI

SOC_SPI_0_CS#0_R SPI_0_D1_ROM SPI_0_D3_ROM SPI_0_D2_ROM SPI_0_CLK_ROM

UH8

1

CS#

2

DO

3

IO2

4

GND

ThemalPad

W25Q256JVEIQ_WSON8_8X6

8

VCC

7

IO3

6

CLK

SPI_0_D0_ROM

5

DI

9

+3V_SPI

PVT_04

B B

A A

RB751S40T1G_SOD523-2

1

CH35

0.1U_0201_10V6K

2

@

21

@

12

RC7450_040 2_5%

WLAN--->

SSD-->

Card Reader--->

+3V_PRIM

CLK_PCIE_N0<52> CLK_PCIE_P0<52>

RH40 10K_0 201_5%DAR@

1 2

+3VS

CLKREQ_PCIE#0<52>

CLK_PCIE_N1<67> CLK_PCIE_P1<67>

RH727 10K_0201_5%

1 2

+3VS

CLKREQ_PCIE#1<67>

CLK_PCIE_N4<70> CLK_PCIE_P4<70>

RH39 10K_0 201_5%

1 2

+3VS

CLKREQ_PCIE#4<70>

UC1E

DB42

SPI0_CLK

DD43

Strap Pin

SPI0_MOSI

DF43

SPI0_MISO

DF42

Strap Pin

SPI0_IO2

DD41

Strap Pin

SPI0_IO3

DB43

SPI0_CS0#

DF41

SPI0_CS1#

DB41

SPI0_CS2#

DV16

GPP_E11/SPI1_CLK/BK1/SBK1

DT16

GPP_E13/SPI1_MOSI/BK3/SBK3

DU18

GPP_E12/SPI1_MISO/BK2/SBK2

DT18

GPP_E1/SPI1_IO2

DW18

GPP_E2/SPI1_IO3

DW16

GPP_E10/SPI1_CS_N/BK0/SBK0

DU16

GPP_E8/SATALED#/SPI1_CS1#

DV19

CL_CLK

DW19

CL_DATA

DT19

CL_RST#

ICL-U_BGA1526

@

TPM

JSPI

SOC_SPI_0_CS#1_R SOC_SPI_0_D0_R SOC_SPI_0_D1_R SOC_SPI_0_CLK_R SOC_SPI_0_CS#0_R

PROM_BIOS_R<78>

SOC_SPI_0_D3_R

+3V_SPI

ACES_50521-01041-P01_10P

Follow Pebble Creek MLK

DK33

DN34

DP34

DP36

DN40

JSPI1

1

2

3

4

5

6

7

8

9

10

CONN@

UC1J

CJ3

CLKOUT_PCIE_N0

CJ5

CLKOUT_PCIE_P0 GPP_D5/SRCCLKREQ0#

CL2

CLKOUT_PCIE_N1

CL1

CLKOUT_PCIE_P1 GPP_D6/SRCCLKREQ1#

CL3

CLKOUT_PCIE_N2

CL5

CLKOUT_PCIE_P2 GPP_D7/SRCCLKREQ2#

CK3

CLKOUT_PCIE_N3

CK4

CLKOUT_PCIE_P3 GPP_D8/SRCCLKREQ3#

CJ2

CLKOUT_PCIE_N4

CJ1

CLKOUT_PCIE_P4 GPP_H10/SRCCLKREQ4#

ICL-U_BGA1526

@

SMBUS

SPI 0

SML 0

GPP_C6/SML1CLK/SUSWARN_N/SUSPWRDNACK

SML1

SPI 1

eSPI

MLINK

5 of 19

11

G1

12

G2

GPP_H11/SRCCLKREQ5#

RTC

XTAL

10 of 19

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C7/SML1DATA/SUSACK#

GPP_A5/ESPI_CLK GPP_A0/ESPI_IO0 GPP_A1/ESPI_IO1 GPP_A2/ESPI_IO2 GPP_A3/ESPI_IO3 GPP_A4/ESPI_CS#

GPP_A6/ESPI_RESET#

RTCX1 RTCX2

RTCRST#

SRTCRST#

GPD8/SUSCLK

XTAL_IN

XTAL_OUT

XCLK_BIASREF

CF5 CF3 DP40

DL48 DL49

DT47 DK46

DF49

DW8 DU8

DU6

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

DK27 DP24

GPP_C2

DL24

SML0_SMBCLK

DK24

SML0_SMBDATA

DJ24

GPP_C5

DP22

SML1_SMBCLK

DN22

SML1_SMBDATA

DL22

ESPI_CLK

CR47

ESPI_IO0_R

CN45

ESPI_IO1_R

CN48

ESPI_IO2_R

CN49

ESPI_IO3_R

CN47

ESPI_CS#

CT45

ESPI_RESET#

CR46

PCH_RTCX1 PCH_RTCX2

PCH_RTCRST#

SRTCRST#

SUSCLK

XTAL_38P4M_IN_CPU XTAL_38P4M_OUT_CPU

CLK_BIASREF

SMB_CLK <79> SMB_DATA <79>

SML0_SMBCLK <46,48> SML0_SMBDATA <46,48>

SML1_SMBCLK <42,44,46,48>

SML1_SMBDATA <42,44,46,48>

RC569 49.9_0201_1% RC336 10_0201_1%

1 2

RC367 10_0201_1%

1 2

RC368 10_0201_1%

1 2

RC369 10_0201_1%

1 2

XTAL_38P4M_IN

XTAL_38P4M_OUT

10P_0201_50V8J

PCH_RTCRST# <63,79>

SUSCLK <52,67>

RH14 0_0201 _5%

1 2

RH15 0_0201 _5%

1 2

RH475 60.4_0201_1%

1 2

MIPI60

BB_L&BB_R (For support Vpro)

BB_L&BB_R

12

CH10

PD_L&PD_R

ESPI_CLK_5105<58,79> ESPI_IO0 <58,79> ESPI_IO1 <58,79> ESPI_IO2 <58,79> ESPI_IO3 <58,79> ESPI_CS# <5 8,79>

ESPI_RESET# <58,79>

RH17 200K _0201_1%

1 2

YH1

123

2

38.4MHZ_10PF_8Y38420005

1

Intel SPEC : CL = Specified Crystal Capacitive Load = 10 pF Series Resistance < or = 30 Ω Frequency Tolerance < or 100 PPM Aging ± 3 PPM

SUSCLK

1

CH49

@EMI@

0.1U_0201_10V6K

2

XTAL_38P4M_IN XTAL_38P4M_OUT

4

EMI Request

SOC_SPI_0_CLK

12

RC734

33_0201_5%

1

CC659

33P_0201_50V8J

2

ESPI 1.8V

@EMI@

2

CH11

10P_0201_50V8J

1

SML0_SMBDATA SML0_SMBCLK

SML1_SMBCLK SML1_SMBDATA

ESPI_CS# ESPI_RESET#

SMB_CLK

CC655 33P_0201_50V8J

SML0_SMBCLK

CC656 33P_0201_50V8J

SML1_SMBCLK

CC657 33P_0201_50V8J

ESPI_CLK_5105

CC658 33P_0201_50V8J

PCH_RTCX2

PCH_RTCX1

15P_0201_50V8J

+RTCVCC_R

1U_0201_6.3V6K

1 2

RH573 20K_0201_5%

1 2

RH572 20K_0201_5%

1U_0201_6.3V6K

PDG_An RC delay circuit with a t i me delay i n t he range of 18– 25 ms should be provided. The circuit should be connected to VCCRTC.

1

CH12

2

1

CH47

2

1

CH46

2

RH16 10M_0201_1%

32.768KHZ_12.5PF_9H03200042

CRB XTAL ESR = 50K MAX

RF Request

@RF@ 1 2

1 2

YC1

1 2

PCH_RTCRST#

SRTCRST#

1 2 1 2

PCH_RTCX2_R

RH144499_0201_1% RH143499_0201_1%

RH6061K_0201_5% RH6071K_0201_5%

RC71275K_0201_1% @ RC71175K_0201_1%

+3V_PRIM

RH637 0_0201_5%

1 2

1

CH13

15P_0201_50V8J

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

2020/10/01 2018/10/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

P009 - ICL-U(4/13)SPI,SMB,ESPI

Size

Document Number Re v

LA-H811P

Date : Sheet of

1

9 100Tuesday, December 24, 2019

0.1 (X00)

5

4

3

2

1

NO REBOOT

+3V_PRIM

RC682 10K_0201_5%@

1 2

RH646 100K_0201_5%@

1 2

D D

+3VS

RC222 49.9K_0201_1%

12

RC223 49.9K_0201_1%

12

RC655 49.9K_0201_1%

12

RC656 49.9K_0201_1%

12

RH713 100K_0201_5%@

1 2

RC339 10K_0201_5%@

1 2

RC338 10K_0201_5%@

1 2

RC748 10K_0201_5%@

1 2

RC749 10K_0201_5%

1 2

check 1.8VS or 3.3VS

RC254 0_0201_5%@

TPM_PIRQ#_R<66>

1 2

RC255 0_0201_5%@

1 2

MEDIACARD_IRQ# PCH_TBT_PERST#

UART_2_CRXD_DTXD UART_2_CTXD_DRXD UART_2_CRTS_DCTS UART_2_CCTS_DRTS PCH_TBT_PERST#

TPM_GPP_B17_SMI#_NMI TPM_PIRQ#

P_SENSOR_PWR_SAVE# P_DET#

TPM_GPP_B17_SMI#_NMI TPM_PIRQ#

DVT2_14

For TS lid open reques t

RW53 10K_0201_5%@

1 2

RH300 10K_0201_5%

1 2

RH688 100K_0201_5%@

C C

1 2

WAKE_BT PCH_TBT_PERST# HDA_BIT_CLK

DVT1_05 : CAM_DET# pull high 100k ohm

+3VS

RH747 100K_0201_5%

1 2

B B

PVT_17

RH11475K_0201_5% CNV@

12

RH72810K_0201_5% @

12

SPCE p.30 PU or PD 100K-180K PDG define only JFP need to PD 10K.

HDA for AUDIO

HDA_BIT_CLK_R<56> HDA_SYNC_R<56> HDA_SDOUT_R<56>

A A

1

2

@RF@

GPP_B18/GSPI0_MOS (Internal 20 K Pull Down)

0 = REBOOT ENABLED

1 = NO REBOOT

NRB_BIT

RH621 4.7K_0201_5%@

1 2

Check follow CRB 573129

SSD_PWR_EN<67>

BT_RADIO_DIS#<52,58>

MEDIACARD_IRQ#_R<70>

P_SENSOR_PWR_SAVE#<39>

TS

TP

CAM_DET#

DVT1_36, DVT1_40,DVT1_69

CNV_RF_RESET# CLKREQ_CNV#

1

CH50

CH51

2

56P_0201_25V8J

@RF@

RH751 0_0201_5%@

RH645 0_0201_5%@

SPKR<56>

Remove 0 ohm

PCH_3.3V_TS_EN<71>

P_DET#<3 9>

PCH_TBT_PERST#<46,48>

SBIOS_TX<7 9>

PANEL_BKLEN<6,38>

UART_2_CRXD_DTXD< 79> UART_2_CTXD_DRXD< 79> UART_2_CRTS_DCTS<79> UART_2_CCTS_DRTS<79>

I2C_0_SDA<38> I2C_0_SCL<38>

I2C_1_SDA<63> I2C_1_SCL<63>

DVT1_69

RH113 33_0201_1%

RH111 33_0201_1%

RH112 33_0201_1%

1

CH40

2

@

22P_0201_50V8J

PVT_09

0_0201_5%

1 2 1 2 1 2

1 2

PCH_TBT_PERST#

RH732 0_0201_5%@

RH715 0_0201_5%@

CNV_RF_RESET#<52>

+3VS

TPM_GPP_B17_SMI#_NMI

TPM_PIRQ#

P_DET# GPP_B23

1 2

UART_2_CRXD_DTXD UART_2_CTXD_DRXD UART_2_CRTS_DCTS UART_2_CCTS_DRTS

@

12

HDA_SDIN0<56>

PCM_CLK<52>

1 2

PCM_SYNC<52>

PCM_IN<5 2>

PCM_OUT<52> CAM_DET#<39, 58>

TS_RST#<38> CLKREQ_CNV#<52>

HDA_BIT_CLK HDA_SYNC HDA_SDOUT

CPUNSSC CLOCK FREQ

GPP_B23 (Internal 20 K Pull Down)

0 = 38.4 MHz clock (direct from crystal) (default)

1 = 19.2 MHz clock (from internal divider)

GPP_B23

RH647 4.7K_0201_5%@

1 2

UC1F

CH48

NRB_BIT

MEDIACARD_IRQ#

ENBKL_TS

GPP_H8

RH714

GPP_H9

HDA_BIT_CLK HDA_SYNC HDA_SDOUT HDA_SDIN0

GPP_A23

CNV_RF_RESET#

GPP_S4

RH7160_0201_5% @

12

GPP_S5

Reserved for debug

GPP_B16/GSPI0_CLK

CF48

Strap Pin

GPP_B18/GSPI0_MOSI

CF47

GPP_B17/GSPI0_MISO

CH49

GPP_B15/GSPI0_CS0#

CH47

GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1#

CL47

GPP_B20/GSPI1_CLK

CK47

GPP_B22/GSPI1_MOSI

CK46

GPP_B21/GSPI1_MISO

CH45

GPP_B19/GSPI1_CS0#

CL48

Strap Pin

GPP_B23/SML1ALERT#/PCHHOT#/GSPI1_CS1#

DP21

GPP_C8/UART0_RXD

DK21

GPP_C9/UART0_TXD

DL21

GPP_C10/UART0_RTS#

DJ22

GPP_C11/UART0_CTS#

DT22

GPP_C20/UART2_RXD

DW22

GPP_C21/UART2_TXD

DV22

GPP_C22/UART2_RTS#

DU22

GPP_C23/UART2_CTS#

DT24

GPP_C16/I2C0_SDA

DT23

GPP_C17/I2C0_SCL

DW23

GPP_C18/I2C1_SDA

DU23

GPP_C19/I2C1_SCL

DU41

GPP_H4/I2C2_SDA

DV41

GPP_H5/I2C2_SCL

DW41

GPP_H6/I2C3_SDA

DT41

GPP_H7/I2C3_SCL

DT40

GPP_H8/I2C4_SDA/CNV_MFUART2_RXD

DW40

GPP_H9/I2C4_SCL/CNV_MFUART2_TXD

ICL-U_BGA1526

@

UC1G

CY46

GPP_R0/HDA_BCLK/I2S0_SCLK

CV49

GPP_R1/HDA_SYNC/I2S0_SFRM

CY47

GPP_R2/HDA_SDO/I2S0_TXD

CV45

GPP_R3/HDA_SDI0/I2S0_RXD

DA47

GPP_R4/HDA_RST#

DP33

GPP_D19/I2S_MCLK

DC45

GPP_A23/I2S1_SCLK

DA49

GPP_R5/HDA_SDI1/I2S1_SFRM

DA45

GPP_R6/I2S1_TXD

DA48

GPP_R7/I2S1_RXD

CT49

GPP_A7/I2S2_SCLK

CT48

GPP_A8/I2S2_SFRM/CNV_RF_RESET#

CV47

GPP_A10/I2S2_RXD

CT47

GPP_A9/I2S2_TXD/MODEM_CLKREQ

CY39

GPP_S0/SNDW1_CLK

CY38

GPP_S1/SNDW1_DATA

DB39

GPP_S2/SNDW2_CLK

DD38

GPP_S3/SNDW2_DATA

DF38

GPP_S4/SNDW3_CLK/DMIC_CLK1

DD39

GPP_S5/SNDW3_DATA/DMIC_DATA1

ICL-U_BGA1526

@

FLASH DESCRIPTOR SECURITY OVERRIDE

GPP_R2/HDA_SDO (Internal 20 K Pull Down)

0 = ENABLE (DEFAULT)

1 = DISABLE (ME can update)

ME_FWP<58>

TOP SWAP OVERRIDE

GPP_B14 / SPKR (Internal 20 K Pull Down)

0 = Disable " Top Swap" mode. (Default)

+3V_PRIM +3V_PRIM

@

1 2

RH218 0_0201_5%

1 = Enable "Top Swap" mode.

RH667 8.2K_0201_5%@

SPKR

GPP_D15/ISH_UART0_RTS_N/GSPI2_CS1_N/IMGCLKOUT5

GPP_D16/ISH_UART0_CTS_N/CNV_WCEN

UART

GSPI

UART

I2C

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

I2C / ISH

6 of 19

GPP_H1/SD_PWR_EN_N/CNV_BT_I2S_SDO

7 of 19

1 2

RH217 1K_0201_1%

GPP_B9/I2C5_SDA/ISH_I2C2_SDA

GPP_B10/I2C5_SCL/ISH_I2C2_SCL

ISH

GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G0/SD_CMD

SD3.0

GPP_H0/CNV_BT_I2S_SDO

GPP_S6/SNDW4_CLK/DMIC_CLK0

GPP_S7/SNDW4_DATA/DMIC_DATA0

AUDIO

1 2

GPP_D13/ISH_UART0_RXD GPP_D14/ISH_UART0_TXD

GPP_B5/ISH_I2C0_SDA GPP_B6/ISH_I2C0_SCL

GPP_B7/ISH_I2C1_SDA GPP_B8/ISH_I2C1_SCL

GPP_D0/ISH_GP0 GPP_D1/ISH_GP1 GPP_D2/ISH_GP2

GPP_D3/ISH_GP3 GPP_D17/ISH_GP4 GPP_D18/ISH_GP5

GPP_E15/ISH_GP6 GPP_E16/ISH_GP7

GPP_G7/SD_WP

SD3_RCOMP

SNDW_RCOMP

CE46 CC48 CC49 CC47 CF45 CC45 CF49 CE47

DK38 DG38

CJ43

DG36 DG34

CV38

GPP_G6/SD_CLK

GPP_G5/SD_CD#

RF Request. Place near CPU side

HDA_SDIN0

HDA_SDOUTME_FWP_PCH

SML0B_SMBDATA

DV33

SML0B_SMBCLK

DW33 DT33 DU33

SML0BALERT#

SIO_EXT_WAKE# SIO_EXT_WAKE#

DK22 DW24 DV24 DU24

CN43 CN42

ISH_I2C_1_SDA

CN41

ISH_I2C_1_SCL

CL43

CL41 CJ39 DU36 DV36

ACC1_INT2#

DW36 DT36

ISH_TABLE_MODE#

DU34

P_INT#

DW34 DT14 DU14

ISH_GP2 for 2nd Acc elerometer INT2# ISH_GP4 for ISH_TABLE_MODE# ISH_GP5 for P_INT# ISH_GP7 for A LS_ALERT#

DDR_CHA_EN DDR_CHB_EN CNVI_EN#_R

SD3_RCOMP

WOV_DMIC_CLK0 WOV_DMIC_DATA0

SNDW_RCOMP

RH729 0_0201_5%@

1 2

RC20 200_0201_1%

RH705 33_0201_5%@

1 2

RH706 33_0201_5%@

1 2

RC16 200_0201_1%

1 2

@RF@

CC727 2.2P_0201_50V8B

1 2

SML0B_SMBDATA< 58>

SML0B_SMBCLK <58>

RC727 0_0201_5%@

1 2

SIO_EXT_WAKE#<58>

DBC_EN <38> WAKE_BT <52>

DVT1_25 : reserve GPIO between WLAN and CPU

ISH_I2C_1_SDA <39,63>

ISH_I2C_1_SCL< 39,63>

ACC1_INT2# <63 >

ISH_TABLE_MODE# <58> P_INT# <39>

ALS_ALERT# <39>

AUD_PWR_EN <7 1>

SPK2_DET# <57>

SPK1_DET# <57>

HOST_SD_WP# <70>

1 2

EC

ALS/G-sensor/P-se nsor

DVT1_11,DVT1_79

CNVI_EN# <52,71>

Intel DMIC for WOV function

1

CC654

@

27P_0201_25V8

2

PCH_DMIC_CLK12 <39>

PCH_DMIC_DATA12 <39>

ISH_I2C_1_SDA ISH_I2C_1_SCL

HOST_SD_WP#

SML0B_SMBDATA SML0B_SMBCLK

ISH_TABLE_MODE#

0= table mode 1= exit table mode

P_INT# ACC1_INT2#

P_INT# ACC1_INT2# ALS_ALERT#

DDR_CHA_EN DDR_CHB_EN

SPK1_DET# SPK2_DET#

RC667 1K_0201_5% RC668 1K_0201_5%

RC717 10K_0201_5%

RC671 10K_0201_5% RC672 1K_0201_5% RC673 1K_0201_5%

RC750 10K_0201_5%@

RC751 10K_0201_5%

12 12

12

12 12 12

12

RC738 10K_0201_5%@

1 2

RC739 10K_0201_5%@

1 2

RC741 10K_0201_5%

1 2

RC742 10K_0201_5%

1 2

R6157 10K _0201_5%

1 2

RH738 100K_0201_5%@

1 2

RH739 100K_0201_5%@

1 2

RH740 100K_0201_5%@

1 2

RH741 100K_0201_5%@

1 2

RH745 100K_0201_5%

1 2

RH746 100K_0201_5%

1 2

+1.8VS

+3VS

+3V_PRIM

+1.8VS

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

2020/10/01 2018/10/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

P010 - ICL-U(5/13)HDA,I2C,ISH

Size

Document Number Re v

LA-H811P

Date : Sheet of

1

10 100Tuesday, December 24, 2019

0.1 (X00)

5

4

3

2

1

3V SELECT STRAP

INPUT3VSE L

0 = 3.3V +/-5%

1 =3.0V +/-5%

RH301 4.7K_0201_5%@

D D

INPUT3VSEL

RH298

1 2

Microchip suggest 100K on RH575

PCH_DPWROK

12

RH5751M_0201_1%

12

CH480.01U_0402_16V7K

@

PCH_DPWROK<58>

SYS_PWROK<58,79>

C C

VCCST_OVERRIDE_R<78>

PM_RSMRST_PWRGD_MIPI60<79>

+1.05V_VCCST

RH95 1K_02 01_1%

RH80 49.9_02 01_1%

RH588 1K_0201_5%

PLACE 'RA' CLOSE TO MCP - WITHIN 1.5 INCH CRB P.35

+1.05V_VCCSTG

RH96 1K_02 01_5%

VCCST_OVERRIDE_R

PLACE 1K SERIES RESISTOR NEAR RSMRST_N AND VCCST_PWRGD “ T” JUNCTION POINT, NOT NEA R MIPI60

H_THERMTRIP#

12

H_CATERR#

12

VCCST_PWRGD

12

H_PROCHOT#

12

MIPI60@

+3VS

RH631 10K_0201_5%

1 2

PCH_TOUCHPAD_INTR#

+3V_PRIM

RH709 100K_0201_5%

B B

1 2

SIO_SLP_S0#

+3VS

RH655

@

1 2

D468

@

RB751S40T1G_SOD523-2

RH743

@

12

0_0201_5%

100K_0201_5%

TOUCH_SCREEN_PD#

RH6540_0201_5% @

12

LID_CL_TS_FP# <58,77>

DVT1_23

TOUCH_SCREEN_PD#_R<38>

2 1

+3VALW

RC147 100K_0201_5%

1 2

3

6

D2

A A

D1

5

2

G2

PMDXB600UNE_DFN1010B-6

S2

4

QC2B

5

DISPOFF_R#

G1

QC2A

PMDXB600UNE_DFN1010B-6

S1

1

RH744 0_0201_5%@

1 2

DISPOFF# <38>

VCCST_OVERRIDE

RH5840_0201_5% @

12

VCCSTPWRGOOD_TCSS

RH5860_0201_5% @

12

VCCST_PWRGD

RC6471K_0201_5% @

12

PCH_RSMRST#_AND

RC2471K_0201_5%

12

H_THERMTRIP#<58>

PCH_TOUCHPAD_INTR#<63>

PCH GLITCH ISSUE MIT IGATION(PDG p.306)

RH683 100K_0201_5%

CH53 0.33U_02 01_6.3V6M@

RH684 100K_0201_5%

CH54 0.33U_02 01_6.3V6M@

RH685 100K_0201_5%

CH55 0.33U_02 01_6.3V6M@

RH682 100K_0201_5%

CH52 0.33U_02 01_6.3V6M@

RH686 100K_0201_5%

CH56 0.33U_02 01_6.3V6M@

RH689 100K_0201_5%@

RH690 100K_0201_5%@

RH691 100K_0201_5%@

CH57 0.33U_02 01_6.3V6M@

+3VALW_DSW

100K_0201_5%

SYS_PWROK SYS_PWROK_R

PECI_EC<58>

H_PROCHOT#<16,58,86 ,91>

DBG_PMODE<79>

UART_WAKE_HOST<52>

1 2

STRAP FOR SPI 1.8V/3.3V SEL

INTRUDER #

0 = SPI voltage is 3.3V

1 = SPI voltage is 1.8V

+RTCVCC

RH5940_0201_5% @

12

SIO_SLP_SUS# SIO_SLP_S5# SIO_SLP_S4# SIO_SLP_S3# SIO_SLP_A# SIO_SLP_S0#

SIO_SLP_WLAN#

PCH_RSMRST#_AND SYS_RESET# PCH_PLTRST#

PCH_DPWROK PCH_PWROK

INPUT3VSEL INTRUDER#

SIO_SLP_SUS#<16,47,49,58>

SIO_SLP_S5#<79> SIO_SLP_S4#<58,78,79> SIO_SLP_S3#<58,78,79>

SIO_SLP_A#<7 9>

SIO_SLP_S0#<66,79> CPU_C10_GATE#<78 >

SIO_SLP_WLAN#<71>

PCH_RSMRST#_AND<63,78> SYS_RESET#<7 9>

MIPI60_DBRESET#_R< 79>

+3VS

RC433 8.2K_0201_5%@

1 2

RC434 8.2K_0201_5%@

1 2

H_PROCHOT# H_PROCHOT#_R

RC614 499_0201_1%

1 2

RH4 49.9_0201_1%

12

RH5 49.9_0201_1%

12

RH6 49.9_0201_1%@

12

RH7 49.9_0201_1%@

12

SIO_SLP_S3#

SIO_SLP_S4#

SIO_SLP_A#

SIO_SLP_WLAN#

SIO_SLP_SUS#

SIO_SLP_S0#

PCH_PLTRST#

SIO_SLP_S5#

4

RH641M_0201_1% @

12

INTRUDER#

RH67110K_0201 _1%

12

CC6530.1U_0201_10V6K

12

@

UC1K

DM49

SLP_SUS#

DF45

GPD10/SLP_S5#

DC48

GPD5/SLP_S4#

DF47

GPD4/SLP_S3#

DH47

GPD6/SLP_A#

CL45

GPP_B12/SLP_S0#

DE49 DN48

DG49

DK19

CM49

DR48 DN47 DP19

DN49 DR47

Strap Pin

if pop UC29, RC244 also need pop

ME_RESET#

H_CATERR# PECI_EC

H_THERMTRIP#

CPU_POPI_RCOMP PCH_OPI_RCOMP EDRAM_OPIO_RCOMP CPU_EOPIO_RCOMP

MEM_INTERLEAVED TOUCH_SCREEN_PD# PCH_TOUCHPAD_INTR#

GPP_E6 GPP_H2

GPP_H3/SX_EXIT_HOLDOFF_N/CNV_BT_I2S_SDO GPD9/SPL_WLAN# SLP_LAN#

RSMRST# SYS_RESET# GPP_B13/PLTRST#

DSW_PWROK PCH_PWROK SYS_PWROK

INPUT3VSEL INTRUDER#

ICL-U_BGA1526

@

RC430

@

1 2

0_0201_5%

+3VS

CC77

@

12

@

UC29

5

0.1U_0201_10V6K

1

P

B

SYS_RESET#_R SYS_RESET#

4

O

2

A

G

MC74VHC1G08DFT2G_SC70-5

3

UC1D

J4

CD5

C3 E3

CJ41

DU3

A14 B14

DL15

Strap Pin

DV11

DT11

CR38

CR39

DT12

Strap Pin

DJ38

Strap Pin

DL38

ICL-U_BGA1526

@

GPD11/LANPHYPC/DSWLDO_MON

11 of 19

RC432 1K_0201_5%

CATERR# PECI PROCHOT# THRMTRIP#

PROC_POPIRCOMP PCH_OPIRCOMP RSVD_25 RSVD_26

DBG_PMODE

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

GPP_E6 GPP_H2/CNV_BT_I2S_SDO GPP_H19/TIME_SYNC0

EMI request,Place near CPU side.

MIPI60_PCH_JTAG_TDO

MIPI60_PCH_JTAG_TDI

MIPI60_PCH_JTAGX

H_THERMTRIP#

H_PROCHOT#_R

@EMI@

CC735 0.1U_0201_25V6K

1 2

@EMI@

CC736 0.1U_0201_25V6K

1 2

@EMI@

CC737 0.1U_0201_25V6K

1 2

@EMI@

CC738 0.1U_0201_25V6K

1 2

@EMI@

CC739 0.1U_0201_25V6K

1 2

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_B11/PMCALERT#

GPP_H18/CPU_C10_GATE#

WAKE#

GPD2/LAN_WAKE#

VCCST_OVERRIDE

VCCST_PWRGD

VCCSTPWRGOOD_TCSS

PROCPWRGD

GPD7

+3VS

1 2

12

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_TRST#

JTAG

PCH_TCK

PCH_TDI PCH_TDO PCH_TMS

PCH_JTAGX

PROC_PRDY# PROC_PREQ#

4 of 19

3

SIO_PWRBTN#_R

CY42

AC_PRESENT_R AC_PRESENT

DE46

PCH_BATLOW#

DH48

CL39

CPU_C10_GATE#_R

DU40 DG40

DL45

WAKE#

LAN_WAKE#_R LAN_WAKE#

DE47 DF48

VCCST_OVERRIDE

CE4

VCCST_PWRGD_CPU V CCST_PWRGD

CF2

VCCSTPWRGOOD_TCSS

CE3 CF1

CPUPWRGD

DC47

GPD7

RC244

@

10K_0201_5%

RH57 0_0201_5%@ RH312 0_0201_5%@

RH280 0_0201_5%@

RH207 0_0201_5%@

RH600 0_0201_5%@

RH587 60.4_0201_1%

VCCST_PWRGD

CPUPWRGD

SYS_RESET#

1 2 1 2

1 2

1

TP101

EMI@

CC649 100P_0201_50V8J

1 2

EMI@

CC650 100P_0201_50V8J

1 2

@EMI@

CC651 0.1U_0201_10V6K

1 2

ESD Request:p lace near CPU side

MIPI60_CPU_JTAG_TCLK

P3 K5 K3 P4 N1

N5 R5 K1 K2 N3 N2

P6 M6

MIPI60_CPU_JTAG_TDI MIPI60_CPU_JTAG_TDO MIPI60_CPU_JTAG_TMS

MIPI60_PCH_JTAG_TRST# MIPI60_PCH_JTAG_TCLK MIPI60_PCH_JTAG_TDI MIPI60_PCH_JTAG_TDO MIPI60_PCH_JTAG_TMS MIPI60_PCH_JTAGX

MIPI60_CPU_JTAG_TCLK <79> MIPI60_CPU_JTAG_TDI <79> MIPI60_CPU_JTAG_TDO <79> MIPI60_CPU_JTAG_TMS <79> MIPI60_CPU_JTAG_TRST# <79>

MIPI60_PCH_JTAG_TRST# <79> MIPI60_PCH_JTAG_TCLK <79> MIPI60_PCH_JTAG_TDI <79> MIPI60_PCH_JTAG_TDO <79> MIPI60_PCH_JTAG_TMS <79> MIPI60_PCH_JTAGX <79>

MIPI60_PRDY# <79> MIPI60_PREQ# <79>

JTAG ODT DISABLE

GPP_E6

0 = JTAG ODT DISABLED

1 = JTAG ODT ENABLED

RH660

GPP_E6

RH661 4.7K_0201_5%@

1 2

+3V_PRIM

100K_0201_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

TBT_I2C_INT#

PAD~D TP@

MAF/SAF STRAP(eSPI Flash Sharing Mode)

GPP_H2/CNV_BT_I2S_SDI(INTERNAL PD 20K)

0 = MAF (Master Attached Flash)

1 = SAF (Slave Attached Flash)

GPP_H2

2020/10/01 2018/10/01

SIO_PWRBTN# <58,79>

AC_PRESENT <58>

TBT_I2C_INT# <42,44,46,48>

PCH_PCIE_WAKE#<58 >

LAN_WAKE# <58>

VCCST_PWRGD < 78>

PCH_PWROK_P<91>

IMVP_VR_ON_P<78>

RH618 2.2K_0201_5%@

1 2

RH617 20K_0201_5%@

1 2

Compal Secret Data

Deciphered Date

2

+3VS

RH733

100K_0201_5%

1 2

RH625 0_0201_5%@

DVT1_12

PCH_PLTRST#

MC74VHC1G08DFT2G_SC70-5

MIPI60_PCH_JTAG_TDI MIPI60_PCH_JTAG_TMS MIPI60_PCH_JTAG_TDO

MIPI60_CPU_JTAG_TDI MIPI60_CPU_JTAG_TMS MIPI60_CPU_JTAG_TDO

MIPI60_CPU_JTAG_TCLK MIPI60_PCH_JTAG_TCLK MIPI60_PCH_JTAG_TRST# MIPI60_PCH_JTAGX

+3V_PRIM

PCH_RSMRST#_AND TBT_I2C_INT#

PCH_RSMRST#_AND

LAN_WAKE# PCH_BATLOW# AC_PRESENT PCH_PCIE_WAKE#

1 2

+3VS

UH6

5

1

P

B

O

2

A

G

3

+3VS

5

UH1

1

P

B

O

2

A

G

3

MEM_INTERLEAVED

+3V_PRIM

RH592 10K_0201_5%@

1 2

RC687 10K_0201_5%

1 2

RH591 100K_0201_5%

1 2

+3VALW_DSW

RH601 10K_0201_5%

1 2

RH460 100K_0201_5%

1 2

RH297 10K_0201_5%

1 2

RH653 1K_0201_5%

1 2

@

PCH_PWROK

4

MC74VHC1G08DFT2G_SC70-5

+3VS

2

CC652

0.1U_0201_10V6K

1

4

12

RH46

100K_0201_5%

PCH_PLTRST#_EC< 46,48,52,66,67,70,79>

+1.05V_VCCSTG

PLACE WITHIN 1 .1INCH OF MCP

RC151 51_0201_5%MIPI60@

1 2

RC203 51_0201_5%MIPI60@

1 2

RC202 100_0201_5%

1 2

TDI&TMS KEEP S TUB TO MINIMUM

RC146 51_0201_5%@

1 2

RC181 51_0201_5%@

1 2

RC150 100_0201_5%

1 2

TDO PLACE WITHIN 1.1INCH OF S OC

PLACE WITHIN 1 .1INCH OF SOC

RC145 51_0201_5%

1 2

RC180 51_0201_5%@

1 2

RC201 51_0201_5%@

1 2

RC344 51_0201_5%@

1 2

RH629 10K_0201_5%@

1 2

RH630 10K_0201_5%@

1 2

+3V_PRIM

DIMM TYPE

HIGH

Interleave

LOW

Non-Interleave

Compal Electronics, Inc.

Title

P011 - ICL-U(6/13)GPIO

Size

Document Number Re v

LA-H811P

Date : Sheet of

1

0.1 (X00)

11 100Tuesday, December 24, 2019

5

4

3

2

1

D D

PCIE_CRX_DTX_N9<67> PCIE_CRX_DTX_P9<67> PCIE_CTX_DRX_N9<67> PCIE_CTX_DRX_P9<67>

PCIE_CRX_DTX_N10<67> PCIE_CRX_DTX_P10<67> PCIE_CTX_DRX_N10<67>

PCIe SSDX4 PCIe Gen3

C C

CardreaderX1 PCIe Gen2

+3V_PRIM

B B

DVT1_ 57

RH60410K_0201_5%

12

RH60510K_0201_5%

12

USB_OC0# USB_OC3#

PCIE_CTX_DRX_P10<67>

PCIE_CRX_DTX_N11<67> PCIE_CRX_DTX_P11<67> PCIE_CTX_DRX_N11<67> PCIE_CTX_DRX_P11<67> PCIE_CRX_DTX_N12<67>

PCIE_CRX_DTX_P12<67> PCIE_CTX_DRX_N12<67>

PCIE_CTX_DRX_P12<67>

PCIE_CRX_DTX_N16<70> PCIE_CRX_DTX_P16<70> PCIE_CTX_DRX_N16<70> PCIE_CTX_DRX_P16<70>

SSD_IFDET<67>

USB_OC0# USB_OC3#

SSD_DEVSLP<67>

SD_PWR_EN<71>

PCIE_RCOMPN

RH1100_0201_1%

12

PCIE_RCOMPP

UC1H

CV7

PCIE7_RXN

CV6

PCIE7_RXP

DD3

PCIE7_TXN

DD5

PCIE7_TXP

CT6

PCIE8_RXN

CT7

PCIE8_RXP

DA3

PCIE8_TXN

DA5

PCIE8_TXP

CP7

PCIE9_RXN

CP6

PCIE9_RXP

DA2

PCIE9_TXN

DA1

PCIE9_TXP

CM7

PCIE10_RXN

CM6

PCIE10_RXP

CY3

PCIE10_TXN

CY4

PCIE10_TXP

CK7

PCIE11_RXN/SATA0_RXN

CK6

PCIE11_RXP/SATA0_RXP

CW2

PCIE11_TXN/SATA0_TXN

CW1

PCIE11_TXP/SATA0_TXP

CJ6

PCIE12_RXN/SATA1A_RXN

CJ7

PCIE12_RXP/SATA1A_RXP

CW5

PCIE12_TXN/SATA1A_TXN

CW3

PCIE12_TXP/SATA1A_TXP

CG7

PCIE13_RXN

CG6

PCIE13_RXP

CT3

PCIE13_TXN

CT5

PCIE13_TXP

CE6

PCIE14_RXN

CE7

PCIE14_RXP

CT2

PCIE14_TXN

CT1

PCIE14_TXP

CC5

PCIE15_RXN/SATA1B_RXN

CC6

PCIE15_RXP/SATA1B_RXP

CR3

PCIE15_TXN/SATA1B_TXN

CR4

PCIE15_TXP/SATA1B_TXP

CA6

PCIE16_RXN/SATA2_RXN

CA5

PCIE16_RXP/SATA2_RXP

CP1

PCIE16_TXN/SATA2_TXN

CP2

PCIE16_TXP/SATA2_TXP

DW12

GPP_E0/SATAXPCIE0/SATAGP0

CR42

GPP_A12/SATAXPCIE1/SATAGP1

CR43

GPP_A13/SATAXPCIE2/SATAGP2

DW14

GPP_E9/USB_OC0#

CT43

GPP_A16/USB_OC3#

DU12

GPP_E4/DEVSLP0

DU11

GPP_E5/DEVSLP1

CV48

GPP_A11/SATA_DEVSLP2

DT38

GPP_H12/M2_SKT2_CFG0

DW38

GPP_H13/M2_SKT2_CFG1

DV38

GPP_H14/M2_SKT2_CFG2

DU38

GPP_H15/M2_SKT2_CFG3

DN1

PCIE_RCOMPN

DN3

PCIE_RCOMPP

ICL-U_BGA1526

@

PCIe

PCIe / SATA

PCIe / USB3.1

PCIe / SATA

8 of 19

PCIE1_RXN/USB31_1_RXN PCIE1_RXP/USB31_1_RXP

PCIE1_TXN/USB31_1_TXN

PCIE1_TXP/USB31_1_TXP

PCIE2_RXN/USB31_2_RXN PCIE2_RXP/USB31_2_RXP

PCIE2_TXN/USB31_2_TXN

PCIE2_TXP/USB31_2_TXP

PCIE3_RXN/USB31_3_RXN PCIE3_RXP/USB31_3_RXP

PCIE3_TXN/USB31_3_TXN

PCIE3_TXP/USB31_3_TXP

PCIE4_RXN/USB31_4_RXN PCIE4_RXP/USB31_4_RXP

PCIE4_TXN/USB31_4_TXN

PCIE4_TXP/USB31_4_TXP

PCIE5_RXN/USB31_5_RXN PCIE5_RXP/USB31_5_RXP

PCIE5_TXN/USB31_5_TXN

PCIE5_TXP/USB31_5_TXP

PCIE6_RXN/USB31_6_RXN PCIE6_RXP/USB31_6_RXP

PCIE6_TXN/USB31_6_TXN

PCIE6_TXP/USB31_6_TXP

USB2.0

USB_VBUSSENSE

USB2_COMP

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9

USB2N_10

USB2P_10

USB_ID

RSVD_81

DJ8 DJ6 DJ2 DJ1

DG9 DG7 DJ3 DJ5

DE7 DE9

PCIE_CTX_DRX_N3

DF3

PCIE_CTX_DRX_P3

DF5

DC7 DC9 DF2 DF1

DA6 DA7 DE4 DE3

CY7 CY6 DD1 DD2

DN8 DP8

DK11 DJ11

DP13 DN13

DK10 DJ10

DL5 DL3

DP11 DN11

DK13 DJ13

DN6 DP6

DL2 DL1

DP10 DN10

USB2_ID

DL6

USB2_VBUSSENSE

DL11

USB2_COMP

DN5

CD3

USB3_CRX_DTX_N2 <79>

USB3_CRX_DTX_P2<79>

USB3_CTX_DRX_N2 <79>

USB3_CTX_DRX_P2<79>

PCIE_CRX_DTX_N3 <52>

PCIE_CRX_DTX_P3 <52>

1 2

CH3 0.1U_0402_10V7K~D

1 2

DAR@

CH4 0.1U_0402_10V7K~D

DAR@

DVT1_ 69

USB20_N1 <79> USB20_P1 <79>

USB20_N4 <50> USB20_P4 <50>

USB20_N5 <77> USB20_P5 <77>

USB20_N8 <50> USB20_P8 <50>

USB20_N9 <39> USB20_P9 <39>

USB20_N10 <52> USB20_P10 <52>

RH8 10K_0201_5%

1 2

RH9 10K_0201_5%

1 2

RH10 113_0201_1%

1 2

USB debug

Type-C_R

FPR

Type-C_L UF Camera

BT

USB debug

PCIE_CTX_C_DRX_N3<52> PCIE_CTX_C_DRX_P3<52>

WLAN

A A

Security Classification

2020/10/ 01 2018/10/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2020/10/ 01 2018/10/ 01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

P012 - ICL-U(7/13)PCIE,USB

LA-H811P

12 100Tuesday, December 24, 2019

1

0.1 (X00)

5

4

3

2

1

UC1I

D12

CSI_E_CLK_N

C12

CSI_E_CLK_P

B12

CSI_E_DN_0

A12

CSI_E_DP_0

G13

CSI_E_DN_1

F13

CSI_E_DP_1

K10

CSI_F_CLK_N

L10

CSI_F_CLK_P

L8

CSI_F_DN_0

M8

CSI_F_DP_0

M11

CSI_F_DN_1

L11

DT34 DP38 DK36

DL36 DN38

X76_M8GB_R3@

UD3

SA0000BX51L

X76_M16GB_R3@

UD3

SA0000BX61L

X76_M32GB_R3@

UD3

SA0000BX71L

X76_H4GB_R3@

UD3

SA0000AD11L

X76_H8GB_R3@

UD3

SA0000BYX1L

X76_H16GB_R3@

UD3

SA0000BYW1L

X76_H32GB_R3@

UD3

SA0000C7V1L

CSI_F_DP_1

D9

CSI_D_CLK_N

C9

CSI_D_CLK_P

A7

CSI_D_DN_0

B7

CSI_D_DP_0

B9

CSI_D_DN_1

A9

CSI_D_DP_1

D7

CSI_D_DN_2/CSI_C_DN_0

C7

CSI_D_DP_2/CSI_C_DP_0

D8

CSI_D_DN_3/CSI_C_CLK_N

C8

CSI_D_DP_3/CSI_C_CLK_P

G11

CSI_H_CLK_N

J11

CSI_H_CLK_P

F6

CSI_H_DN_0

G6

CSI_H_DP_0

G10

CSI_H_DN_1

F10

CSI_H_DP_1

G8

CSI_H_DN_2/CSI_G_DN_0

J8

CSI_H_DP_2/CSI_G_DP_0

K6

CSI_H_DN_3/CSI_G_CLK_N

L6

CSI_H_DP_3/CSI_G_CLK_P

B4

CSI_RCOMP

GPP_D4/IMGCLKOUT0 GPP_H20/IMGCLKOUT1 GPP_H21/IMGCLKOUT2 GPP_H22/IMGCLKOUT3 GPP_H23/IMGCLKOUT4

ICL-U_BGA1526

@

MT53E512M32D2NP-046 WT

MT53E1G32D4NQ-046 WT

MT53E2G32D8QD-046 WT

H9HCNNN8KUMLHR-NME

H9HCNNNBKMALHR-NEE

H9HCNNNCPMALHR-NEE

H9HCNNNFAMALTR-NME

X76_M8GB_R3@

UD4

SA0000BX51L

X76_M16GB_R3@

UD4

SA0000BX61L

X76_M32GB_R3@

UD4

SA0000BX71L

X76_H4GB_R3@

UD4

SA0000AD11L

X76_H8GB_R3@

UD4

SA0000BYX1L

X76_H16GB_R3@

UD4

SA0000BYW1L

X76_H32GB_R3@

UD4

SA0000C7V1L

CSI2

9 of 19

DRAM Config Option

MEM_CONFIG 4 MEM_CONFIG 2M EM_CONFIG3

D D

CSI_RCOMP

RC8100_0201_1 %

12

RT_FORCE_PWR<42,4 4,46,48>

C C

X76

X7682 731L01

B B

X7682 731L02

X7682 731L03

X7682 731L10

X7682 731L04

X7682 731L05

X7682 731L06

DRAM Option R3

Micron 8GB/4266

X76_M8GB_R3@

UD1

MT53E512M32D2NP-046 WT

SA0000BX51L

Micron 16GB/4266

X76_M16GB_R3@

UD1

MT53E1G32D4NQ-046 WT

SA0000BX61L

Micron 32GB/4266

X76_M32GB_R3@

UD1

MT53E2G32D8QD-046 WT

SA0000BX71L

Hynix 4GB/3733

X76_H4GB_R3@

UD1

H9HCNNN8KUMLHR-NME

SA0000AD11L

Hynix 8GB/4266

X76_H8GB_R3@

UD1

H9HCNNNBKMALHR-NEE

SA0000BYX1L

Hynix 16GB/4266

X76_H16GB_R3@

UD1

H9HCNNNCPMALHR-NEE

SA0000BYW1L

Hynix 32GB/3733

X76_H32GB_R3@

UD1

H9HCNNNFAMALTR-NME

SA0000C7V1L

X76_M8GB_R3@

UD2

MT53E512M32D2NP-046 WT

SA0000BX51L

X76_M16GB_R3@

UD2

MT53E1G32D4NQ-046 WT

SA0000BX61L

X76_M32GB_R3@

UD2

MT53E2G32D8QD-046 WT

SA0000BX71L

X76_H4GB_R3@

UD2

H9HCNNN8KUMLHR-NME

SA0000AD11L

X76_H8GB_R3@

UD2

H9HCNNNBKMALHR-NEE

SA0000BYX1L

X76_H16GB_R3@

UD2

H9HCNNNCPMALHR-NEE

SA0000BYW1L

X76_H32GB_R3@

UD2

H9HCNNNFAMALTR-NME

SA0000C7V1L

MT53E512M32D2NP-046 WT

MT53E1G32D4NQ-046 WT

MT53E2G32D8QD-046 WT

H9HCNNN8KUMLHR-NME

H9HCNNNBKMALHR-NEE

H9HCNNNCPMALHR-NEE

H9HCNNNFAMALTR-NME

GPP_F8/EMMC_DATA0

GPP_F9/EMMC_DATA1 GPP_F10/EMMC_DATA2 GPP_F11/EMMC_DATA3 GPP_F12/EMMC_DATA4 GPP_F13/EMMC_DATA5 GPP_F14/EMMC_DATA6

eMMC

GPP_F15/EMMC_DATA7

GPP_F7/EMMC_CMD

GPP_F16/EMMC_RCLK

GPP_F17/EMMC_CLK

GPP_F18/EMMC_RESET#

EMMC_RCOMP

CNV_WT_D0N

CNV_WT_D0P

CNV_WT_D1N

CNV_WT_D1P CNV_WT_CLKN CNV_WT_CLKP

CNV_WR_D0N CNV_WR_D0P CNV_WR_D1N CNV_WR_D1P

CNVi

GPP_F1/CNV_BRI_RSP/UART0_RXD

GPP_F0/CNV_BRI_DT/UART0_RTS#

GPP_F3/CNV_RGI_RSP/UART0_CTS#

X76_M8GB@

RH665

10K_0201_5%

SD043100280

X76_M16GB@

RH665

10K_0201_5%

SD043100280

X76_M32GB@

RH665

10K_0201_5%

SD043100280

X76_H4GB@

RH665

10K_0201_5%

SD043100280

X76_H8GB@

RH665

10K_0201_5%

SD043100280

X76_H16GB@

RH665

10K_0201_5%

SD043100280

X76_H32GB@

RH665

10K_0201_5%

SD043100280

CNV_WR_CLKN CNV_WR_CLKP

CNV_WT_RCOMP

GPP_F2/CNV_RGI_DT/UART0_TXD

GPP_F4/CNV_RF_RESET#

GPP_F6/CNV_PA_BLANKING

GPP_F19/A4WP_PRESENT GPP_F5/MODEM_CLKREQ

X76_M8GB@

RH185

10K_0201_5%

SD043100280

X76_M16GB@

RH185

10K_0201_5%

SD043100280

X76_M32GB@

RH185

10K_0201_5%

SD043100280

X76_H4GB@

RH615

10K_0201_5%

SD043100280

X76_H8GB@

RH185

10K_0201_5%

SD043100280

X76_H16GB@

RH615

10K_0201_5%

SD043100280

X76_H32GB@

RH185

10K_0201_5%

SD043100280

X76_M8GB@

RH145

10K_0201_5%

SD043100280

X76_M16GB@

RH145

10K_0201_5%

SD043100280

X76_M32GB@

RH145

10K_0201_5%

SD043100280

X76_H4GB@

RH614

10K_0201_5%

SD043100280

X76_H8GB@

RH145

10K_0201_5%

SD043100280

X76_H16GB@

RH145

10K_0201_5%

SD043100280

X76_H32GB@

RH614

10K_0201_5%

SD043100280

DP27 DU30 DT30 DT29 DV30 DU29 DW30 DW29 DV28 DW28 DN27 DT28 DU28

DV45 DU45 DU44 DT44 DL42 DK42

DP44 DN44 DG42 DG44 DK44 DJ44

DT45

DL29 DP31

Strap Pin

DL31

Strap Pin

DN29

DJ29 DP29 DL27 DK29

(Resistor pop locati on)

MEM_CONFIG 1

X76_M8GB@

RH139

10K_0201_5%

SD043100280

X76_M16GB@

RH139

10K_0201_5%

SD043100280

X76_M32GB@

RH613

10K_0201_5%

SD043100280

X76_H4GB@

RH139

10K_0201_5%

SD043100280

X76_H8GB@

RH613

10K_0201_5%

SD043100280

X76_H16GB@

RH613

10K_0201_5%

SD043100280

X76_H32GB@

RH139

10K_0201_5%

SD043100280

MEM_CONFIG0 MEM_CONFIG1 MEM_CONFIG2 MEM_CONFIG3 MEM_CONFIG4

EMMC_RCOMP

CNV_WT_RCOMP

CNV_BRI_CRX_DTX CNV_RGI_CTX_DRX CNV_BRI_CTX_DRX CNV_RGI_CRX_DTX

GPP_F4

1 2

RC746 0_0201_5%

GPP_F19 GPP_F5

MEM_CONFIG 0

X76_M8GB@

RH129

10K_0201_5%

SD043100280

X76_M16GB@

RH612

10K_0201_5%

SD043100280

X76_M32GB@

RH129

10K_0201_5%

SD043100280

X76_H4GB@

RH612

10K_0201_5%

SD043100280

X76_H8GB@

RH612

10K_0201_5%

SD043100280

X76_H16GB@

RH129

10K_0201_5%

SD043100280

X76_H32GB@

RH612

10K_0201_5%

SD043100280

RC17 200_0201_1%

1 2

RC15 150_02 01_1%

1 2

RC503 22_0201_1%

1 2

RC504 22_0201_1%

1 2

@

Pin Name

MEM_CONF IG0

MEM_CONF IG1

MEM_CONF IG2

X7682 731L08

X7682 731L12

X7682 731L13

X7682 731L14

X7682 731L09

CNV_CTX_DRX_N0 <52> CNV_CTX_DRX_P0< 52> CNV_CTX_DRX_N1 <52> CNV_CTX_DRX_P1< 52> CLK_CNV_CTX_DRX_N<52> CLK_CNV_CTX_DRX_P<52>

CNV_CRX_DTX_N0 <52> CNV_CRX_DTX_P0< 52> CNV_CRX_DTX_N1 <52> CNV_CRX_DTX_P1< 52> CLK_CNV_CRX_DTX_N<52> CLK_CNV_CRX_DTX_P<52>

DVT1_51

GPP_F19

Micron 8GB SA0000BX50L

X76

CNVi

CNV_BRI_CRX_DTX <52> CNV_RGI_CTX_R_DRX<52> CNV_BRI_CTX_R_DRX<52>

CNV_RGI_CRX_DTX <52>

RH749 75K_0201_5%

1 2

Micron 16GB

Micron 32GB

SA0000BX60L

SA0000BX70L

0 1

0

1

0

DRAM Option R3

Samsung 4GB/3733

X76_S4GB_R3@

UD1

K4F8E304HB-MGCJ

SA0000AV71L

Samsung 8GB/4266

X76_S8GB_R3@

UD1

K4U6E3S4AA-MGCL

SA0000C6K1L

Samsung 16GB/4266

X76_S16GB_R3@

UD1

K4UBE3D4AA-MGCL

SA0000C6L1L

Samsung 32GB/4266

X76_S32GB_R3@

UD1

K4UCE3Q4AA-MGCL

SA0000CGN1L

Nanya 4GB/3733 (new)

X76_N4GB_R1@

UD1

NT6AN256T32AV-J2

SA0000CRC0L

X76_S4GB_R3@

UD2

K4F8E304HB-MGCJ

SA0000AV71L

X76_S8GB_R3@

UD2

K4U6E3S4AA-MGCL

SA0000C6K1L

X76_S16GB_R3@

UD2

K4UBE3D4AA-MGCL

SA0000C6L1L

X76_S32GB_R3@

UD2

K4UCE3Q4AA-MGCL

SA0000CGN1L

X76_N4GB_R1@

UD2

NT6AN256T32AV-J2

SA0000CRC0L

Hynix 8GB SA0000BYX0L

1

0

CNV_BRI_CRX_DTX CNV_RGI_CRX_DTX

RH724 20K_0201_5%@

1 2

RH725 20K_0201_5%@

1 2

DVT1_40, DVT1_77

Memory Type Configuration Strap pin

+1.8V_PRIM

Micron 4GB SA0000B7G0L

0

1

0

X76_S4GB_R3@

UD3

K4F8E304HB-MGCJ

SA0000AV71L

X76_S8GB_R3@

UD3

K4U6E3S4AA-MGCL

SA0000C6K1L

X76_S16GB_R3@

UD3

K4UBE3D4AA-MGCL

SA0000C6L1L

X76_S32GB_R3@

UD3

K4UCE3Q4AA-MGCL

SA0000CGN1L

X76_N4GB_R1@

UD3

NT6AN256T32AV-J2

SA0000CRC0L

RH612 10K_0201_5%@

RH613 10K_0201_5%@

RH614 10K_0201_5%@

RH615 10K_0201_5%@

RH616 10K_0201_5%@

Hynix 32GB SA0000C7V0L

1

0

1 2

Samsung 8GB SA0000C6K0L

01

1

11

0 00000MEM _CONFIG3

0 0000M EM_CONFIG 4

X76_S4GB_R3@

UD4

K4F8E304HB-MGCJ

SA0000AV71L

X76_S8GB_R3@

UD4

K4U6E3S4AA-MGCL

SA0000C6K1L

X76_S16GB_R3@

UD4

K4UBE3D4AA-MGCL

SA0000C6L1L

X76_S32GB_R3@

UD4

K4UCE3Q4AA-MGCL

SA0000CGN1L

X76_N4GB_R1@

UD4

NT6AN256T32AV-J2

SA0000CRC0L

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

MEM_CONFIG3

MEM_CONFIG4

Samsung 32GB

Nanya 4GB

SA0000CGN0L

SA0000CRC0L

NEW

1

DRAM Config Option

MEM_CONFIG 4 MEM_CONFI G2MEM_CONFIG3

+1.8V_PRIM

0

1

0

X76_S4GB@

RH665

10K_0201_5%

SD043100280

X76_S8GB@

RH665

10K_0201_5%

SD043100280

X76_S16GB@

RH665

10K_0201_5%

SD043100280

X76_S32GB@

RH665

10K_0201_5%

SD043100280

X76_N4GB@

RH665

10K_0201_5%

SD043100280

RH129 10K_0201_5%@

RH139 10K_0201_5%@

RH145 10K_0201_5%@

RH185 10K_0201_5%@

RH665 10K_0201_5%@

Samsung 16GB SA0000C6L0L

1

0

1

0

X76_S4GB@

RH615

10K_0201_5%

SD043100280

X76_S8GB@

RH185

10K_0201_5%

SD043100280

X76_S16GB@

RH615

10K_0201_5%

SD043100280

X76_S32GB@

RH615

10K_0201_5%

SD043100280

X76_N4GB@

RH185

10K_0201_5%

SD043100280

1 2

Hynix 16GB SA0000BYW0L

0

1

0

1

0 0

Samsung 4GB SA0000AV70L

X76_S4GB@

RH145

10K_0201_5%

SD043100280

X76_S8GB@

RH614

10K_0201_5%

SD043100280

X76_S16GB@

RH145

10K_0201_5%

SD043100280

X76_S32GB@

RH145

10K_0201_5%

SD043100280

X76_N4GB@

RH614

10K_0201_5%

SD043100280

Micron 4GB SA0000BWF0L

EOL

1

0

1

0

1

0

(Resistor pop locati on)

MEM_CONFIG 1

X76_S4GB@

RH613

10K_0201_5%

SD043100280

X76_S8GB@

RH613

10K_0201_5%

SD043100280

X76_S16GB@

RH139

10K_0201_5%

SD043100280

X76_S32GB@

RH139

10K_0201_5%

SD043100280

X76_N4GB@

RH613

10K_0201_5%

SD043100280

Hynix 4GB SA0000AD10L

MEM_CONFIG 0

X76_S4GB@

RH612

10K_0201_5%

SD043100280

X76_S8GB@

RH129

10K_0201_5%

SD043100280

X76_S16GB@

RH612

10K_0201_5%

SD043100280

X76_S32GB@

RH129

10K_0201_5%

SD043100280

X76_N4GB@

RH612

10K_0201_5%

SD043100280

1

0

1

0

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

2020/10/01 2018/10/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

P013 - ICL-U(8/13)CSI,CNVi,EMMC

Size

Document Number Re v

LA-H811P

Date : Sheet of

1

13 100Tuesday, December 24, 2019

0.1 (X00)

5

D D

4

3

2

1

+VCCIN

Max2V/70A(Proce ssor EDS 572795 rev 1. 32)

UC1L

CPU POWER 1 OF 3

A19

VCCIN_1

AC12

VCCIN_2

V13

VCCIN_3

W12

VCCIN_4

Y13

VCCIN_5

K29

VCCIN_6

K31

VCCIN_7

B19

VCCIN_8

B23

VCCIN_9

B27

VCCIN_10

B29

VCCIN_11

BN10

C C

B B

SOC_SVID_ALERT# SOC_SVID_CLK SOC_SVID_DAT

BP11

BR10 BT11

BU10 BV36

BW10 BW36

BW9

BY10

CA36

CA9 CB10 CC11 CC36

CC9 CD10 CE11

CE34 CE35 CF10 CF33 CG11 CG34 CG35 CH10

CJ11

CJ34

BP9

A21 BT9

BV9

C19 C23 A23 C27 C29

A24

A27

J30

H1 H2 H3

VCCIN_12 VCCIN_13 VCCIN_14 VCCIN_15 VCCIN_16 VCCIN_17 VCCIN_18 VCCIN_19 VCCIN_20 VCCIN_21 VCCIN_22 VCCIN_23 VCCIN_24 VCCIN_25 VCCIN_26 VCCIN_27 VCCIN_28 VCCIN_29 VCCIN_30 VCCIN_31 VCCIN_32 VCCIN_33 VCCIN_34 VCCIN_35 VCCIN_36 VCCIN_37 VCCIN_38 VCCIN_39 VCCIN_40 VCCIN_41 VCCIN_42 VCCIN_43 VCCIN_44 VCCIN_45 VCCIN_46 VCCIN_47 VCCIN_48 VCCIN_49 VCCIN_50 VCCIN_51

VIDALERT# VIDSCK VIDSOUT

ICL-U_BGA1526

@

12 of 19

VCCIN_SENSE

VSSIN_SENSE

VCCIN_52 VCCIN_53 VCCIN_54 VCCIN_55 VCCIN_56 VCCIN_57 VCCIN_58 VCCIN_59 VCCIN_60 VCCIN_61 VCCIN_62 VCCIN_63 VCCIN_64 VCCIN_65 VCCIN_66 VCCIN_67 VCCIN_68 VCCIN_69 VCCIN_70 VCCIN_71 VCCIN_72 VCCIN_73 VCCIN_74 VCCIN_75 VCCIN_76 VCCIN_77 VCCIN_78 VCCIN_79 VCCIN_80 VCCIN_81 VCCIN_82 VCCIN_83 VCCIN_84 VCCIN_85 VCCIN_86 VCCIN_87 VCCIN_88 VCCIN_89 VCCIN_90 VCCIN_91 VCCIN_92 VCCIN_93 VCCIN_94 VCCIN_95 VCCIN_96 VCCIN_97 VCCIN_98

VCCIN_99 VCCIN_100 VCCIN_101 VCCIN_102 VCCIN_103 VCCIN_104

CJ35 CK10 J32 CL34 CL35 CN34 CN35 CP33 CR34 A29 CR35 CT33 CT34 CT35 CU33 D19 D21 D23 D24 D27 AA12 D29 F19 F21 F23 F24 F27 F29 G1 G19 G23 AB1 G27 G29 H19 H23 H27 H29 J18 J20 J22 J23 AB13 J26 J28 K17 K19 K21 K23 K24 K27 M1 U1

F17 G17

VCCIN_SENSE_R VSSIN_SENSE_R

RC683 0_0201_5%@

1 2

RC684 0_0201_5%@

1 2

Trace Length Match<25 mils Must be routed as differential pair to VR

VCCIN_SENSE <91> VSSIN_SENSE <91>

1.The total Length of Data and Clock (from CPU to each VR) must be equal (± 0. 1 i nch).

2.Route the Al ert signal between the Clock and the Data signals. CAD Note: Pl ace the PU resistors close to CPU

+1.05V_VCCST

12

SVID DATA

SOC_SVID_DAT

SVID ALERT#

SOC_SVID_ALERT#

SVID CLK

SOC_SVID_CLK

@

12

RC6030_0201_5%

@

12

RC6010_0201_5%

@

12

RC6050_0201_5%

RC604 100_0201_1%

+1.05V_VCCST

12

+1.05V_VCCST

12

100_0201_5%

1

2

RC602 56_0201_5%

RC606

@

C4195

@RF@

33P_0201_50V8J

SVID_DAT <91>

SVID_ALERT# <91>

SVID_CLK <91>

A A

Security Classification

2020/10/ 01 2018/10/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2020/10/ 01 2018/10/ 01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

P014 - ICL-U(9/13)CPU PWR,SVID

LA-H811P

14 100Tuesday, December 24, 2019

1

0.1 (X00)

5

4

3

2

1

+1.1V_MEM

EMC CAPS

+1.1V_MEM

PLACE <160mil FROM SOC VDDQ, WITH EACH PAIR <470mil APART

CC14010U_0402_10V6M

CC1311U_0201_6.3V6K

CC1301U_0201_6.3V6K

1

D D

2

CC1331U_0201_6.3V6K

CC1321U_0201_6.3V6K

1

2

CC1341U_0201_6.3V6K

1

2

CC13610U_0402_6.3V6M

CC1351U_0201_6.3V6K

1

2

CC13710U_0402_6.3V6M

CC13810U_0402_10V6M

1

2

1

2

@

CC14122U_0603_6.3V6M

CC13910U_0402_10V6M

1

2

@

CC14222U_0603_6.3V6M

1

2

@

2

CC64312P_0201_25V8JEMI@

CC64412P_0201_25V8JEMI@

CC6462.2P_0201_25V8CEMI@

1

2

CC6472.2P_0201_25V8CEMI@

1

2

CC6482.2P_0201_25V8CEMI@

CC64512P_0201_25V8JEMI@

1

2

CC66012P_0201_25V8J@EMI@

1

2

Primary side cap

Follow PDG rev1.1 P.545

+VCCST_CPU +VCCSTG_CPU

C C

1

CC154

@

1U_0201_6.3V6M

2

+VCCST_CPU +1.05V_VCCST

B B

1

CC153 1U_0201_6.3V6M

2

1 2

RC592 0_0603_5%

1 2

RC659 0_0603_5%

+VCCSTG_OUT

CC191

1U_0201_6.3V6M

@

1

CC155

@

1U_0201_6.3V6M

2

@

+1.05V_VCCSTG+VCCSTG_OUT_LGC

@

1

2

1

2

+VCCSTG_OUT_LGC

CC156 1U_0201_6.3V6M

+VCCSTG_CPU

+VCCSTG_OUT

+VCCST_CPU

+1.1V_MEM

1.05V /0. 8A

1.05V /0. 15A

1.1V/3.5A(Proce ssor EDS 572795 rev 1. 32)

UC1M

AA37 AG36

AJ36 AL36

AL49 AN36 AP37 AR36 AR37 AT36 AT49 AA49 AV36

AW37

AY36 BA37 BA49 BB36 BD36 BE37 BF36 BF37 AB36 BF49 BG36

BJ36

BL37

BM49

BN37 BP38

CB1

BY1

G33

F33

E5

CPU POWER 2 OF 3

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20 VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25 VDDQ_26 VDDQ_27 VDDQ_28 VDDQ_29 VDDQ_30

VCCST

VCCSTG

VCCSTG_OUT_1 VCCSTG_OUT_2

VCCSTG_OUT_LGC

ICL-U_BGA1526

@

13 of 19

VDDQ_31 VDDQ_32 VDDQ_33 VDDQ_34 VDDQ_35 VDDQ_36 VDDQ_37 VDDQ_38 VDDQ_39 VDDQ_40 VDDQ_41 VDDQ_42 VDDQ_43 VDDQ_44 VDDQ_45 VDDQ_46 VDDQ_47

RSVD_78

RSVD_2 RSVD_3

VCC1P8A_1 VCC1P8A_2 VCC1P8A_3 VCC1P8A_4 VCC1P8A_5

VCCSTG_OUT_3 VCCSTG_OUT_4 VCCSTG_OUT_5 VCCSTG_OUT_6 VCCSTG_OUT_7

RSVD_74 RSVD_75 RSVD_76

VCCPLL

VCCPLL_OC_1 VCCPLL_OC_2 VCCPLL_OC_3 VCCPLL_OC_4

VCCIO_OUT

BP39 BR37 BT38 AC35 BU37 BU49 CA39 CB49 L38 L49 N36 T49 AC37 AD35 AD36 AE36 AF49

C33

C33,A33,B33 is RSVD

A33

Intel recommend ed NC

B33

BG9 BJ9 BM9 BW1 BW2

R35 V34 T34 U35 AB34

RSVD_W35

W35

RSVD_AA35

AA35

RSVD_Y34

Y34

CD2

CG38 CG41 CG42 CG49

AD7

1.8V/ 0.7 A

+VCCSTG_OUT

1

TP72

1

TP71

1

TP73

1.05V /0. 09A

1.1V/ 0.1 6A

+VCCIO_OUT

TP@ TP@ TP@

PAD~D PAD~D PAD~D

+VCC1P05_OUTPUT_PLL

+VCC1P8A

+VCC_SFR_OC

VCC1P8A shape from VR to VCC1P8A pins should have : a. total length L of < 22mm between VR and BGA. b. Average width W of 1.8mm.

1

CC129 10U_0402_6.3V6M

2

1

CC144 1U_0201_6.3V6M

2

1

2

1

CC145 1U_0201_6.3V6M

2

CC308

@

22U_0603_6.3V6M

+VCC_SFR_OC

@

+VCC1P8A

1

2

1

CC189 1U_0201_6.3V6M

2

CC66212P_0201_25V8J@EMI@

CC6632.2P_0201_25V8C@EMI@

1

2

CC188

@

10U_0402_10V6M

@

CC6642.2P_0201_25V8C@EMI@

CC6652.2P_0201_25V8C@EMI@

CC66112P_0201_25V8J@EMI@

1

2

+VCC1P05_OUTPUT_PLL

1

CC147 1U_0201_6.3V6M

2

A A

Security Classification

2020/10/ 01 2018/10/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2020/10/ 01 2018/10/ 01

3

Compal Secret Data

Deciphered Date

2

1

@

CC148 1U_0201_6.3V6M

2

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet of

Compal Electronics, Inc.

P015 - ICL-U(10/13)CPU PWR

LA-H811P

15 100Tuesday, December 24, 2019

1

0.1 (X00)

5

4

3

2

1

+VCCPRIM_1P8

+VCCA_CLKLDO_1P8

PLACE NEAR DW15

RC663 RC664

1.8V_PRIM_PG<58,88,89>

+3V_PRIM

breakout with a 3.8mm width plane

1

CC170 1U_0201_6.3V6M

2

@

1

CC171

@

0.1U_0201_10V6K

2

PLACE NEAR DG26

breakout with a 5mm width plane

1

CC173 1U_0201_6.3V6M

2

1

@

2

CC174

@

1U_0201_6.3V6M

1

2

PDG p.545 use XFL4012-601ME

SDS p.23 use UHP252012 , now use

CRB p.62 use 0.6UH/5A

GND shield around the VCC trace routing

1 2

12

1

CC177 1U_0201_6.3V6M

2

+3VALW_DSW

RC120

RC589

0.1_0402_1%

@

1

CC176 47U_0603_6.3V6M

2

breakout with a 1.4mm width plane

1

CC180

@

1U_0201_6.3V6M

2

PLACE NEAR DE31

+3VALW

12

10K_0201_5 %

12

10K_0201_5 %

+VCCIN_AUX

B+

12

RC783 100K_0201_5%@

@

2

G

2N7002KDW_SOT363-6

34

@

D

5

G

QC5B

S

1 2

RC587

CC175

@

1U_0201_6.3V6M

LC10.68UH_UHP252012NF-R68M_3A_20% @

0_0603_5%

12

RC782 100_0402_1%@

2N7002KDW_SOT363-6

61

D

QC5A

S

+1.8V_PRIM

0_0603_5%

+1.8V_PRIM

1.8V/32A(Processor EDS 572795 rev 1.32)

+VCCIN_AUX

D D

Trace Length Match<25 mils Must be routed as differential pair to VR

VCCIN_AUX_VCCSENSE<89> VCCIN_AUX_VSSSENSE< 89>

C C

+V3.3A_1.8A_PCH_SPI

RC685 0_0201_5%@ RC686 0_0201_5%@

+VCCPRIM_1P8

1 2 1 2

+VCCPFUSE_3P3

+VNN_BYPASS

VCCIN_AUX_VCCSENSE_R VCCIN_AUX_VSSSENSE_R

+V1.05A_BYPASS

1.05 V/0. 2A

3.3V /0.0 03A

VCCDSW_EN_GPIO<78>

VCCDSW_EN<58>

ALW_PWRGD_3V_5V<58,78>

RC697 0_0201_5%@

1 2

UC1N

AH1

VCCIN_AUX_1

AW10

VCCIN_AUX_2

AY11

VCCIN_AUX_3

AY9

VCCIN_AUX_4

BA10

VCCIN_AUX_5

BB9

VCCIN_AUX_6

CH1

VCCIN_AUX_7

CK11

VCCIN_AUX_8

CL10

VCCIN_AUX_9

CM11

VCCIN_AUX_10

CN1

VCCIN_AUX_11

AJ1

VCCIN_AUX_12

CN10

VCCIN_AUX_13

CP11

VCCIN_AUX_14

CR10

VCCIN_AUX_15

CT11

VCCIN_AUX_16

CU10

VCCIN_AUX_17

CV1

VCCIN_AUX_18

CV11

VCCIN_AUX_19

CW10

VCCIN_AUX_20

CY11

VCCIN_AUX_21

DC1

VCCIN_AUX_22

AL1

VCCIN_AUX_23

P13

VCCIN_AUX_24

R12

VCCIN_AUX_25

T13

VCCIN_AUX_26

U12

VCCIN_AUX_27

DC11

VCCIN_AUX_28

DE12

VCCIN_AUX_29

DF12

VCCIN_AUX_30

AM1

VCCIN_AUX_31

AN1

VCCIN_AUX_32

AT11

VCCIN_AUX_33

AT9

VCCIN_AUX_34

AU10

VCCIN_AUX_35

AV9

VCCIN_AUX_36

BF9

VCCIN_AUX_VCCSENSE

BD9

VCCIN_AUX_VSSSENSE

DJ15

VCC_V1P05EXT_1P05

CY34

VCC_VNNEXT_1P05

DC33

VCCPRIM_3P3_1

DD35

VCCPRIM_1P8_1

DB34

VCCSPI

ICL-U_BGA1526

@

CPU POWER 3 OF 3

14 of 19

SIO_SLP_SUS#<11,47,49,58>

DC1

2 1

RB751S40T1G_SOD523-2

DC2

21

RB751S40T1G_SOD523-2

VCCPRIM_3P3_2 VCCPRIM_3P3_3 VCCPRIM_3P3_4

VCCPRIM_1P8_2 VCCPRIM_1P8_3 VCCPRIM_1P8_4 VCCPRIM_1P8_5 VCCPRIM_1P8_6 VCCPRIM_1P8_7 VCCPRIM_1P8_8 VCCPRIM_1P8_9

VCCLDOSTD_0P85

VCCA_CLKLDO_1P8

VCCDPHY_1P24

VCCDSW_1P05

VCC1P05_1 VCC1P05_2 VCC1P05_3

VCCPLL

VCCPRIM_1P05_1

VCCPRIM_1P05_2

VCCPRIM_1P05_3

VCCPRIM_1P05_4

VCCRTC

VCCDSW_3P3

VCCPGPPR

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

GPP_B2/VRALERT#

VCCDSW_EN_Q

DF23 DG26 DG28

DF15 DF17 DF18 DF20 DG17 DG18 DG20 DF34

DW37

DW15

DW32

DD34

BY2 CB2 CC1

CD1

DG31

DG29

DF29

DF31

DG33

DE31

DF26

CL38 CJ38 CN38

RC699 0_0201_5%@

1 2

RC698 0_0201_5%@

1 2

DVT1_23

B B

For volume segment platform this rail is disabled. Keep the pin floating (do not short this pin to ground).

RC595 100K_0201_5%@

1 2

RC648 100K_0201_5%@

1 2

+V1.05A_BYPASS

+VNN_BYPASS

+1.8V_PRIM

RC583

@

1 2

0_0402_5% RC582 0_0402_5%

@

1 2

+V3.3A_1.8A_PCH_SPI+3V_PRIM

1

CC30

@

0.1U_0201_10V6K

2

+3V_PRIM

3.3V /0.2 02A

+VCCPRIM_1P8

1.8V /1.3 A

+VCCLDOSTD_ OUT_0P85

0.85V_DeCap only

1.8V /0.1 65A

1.24V_DeCap only

1.05V_DeCap only

1.05 V_Lo opba ck

1.05 V/0. 09A

1

TP100

TP@

1.05 V_Lo opba ck

3.3V /0.0 02A

3.3V/0.004 A

3.3V ,1.8 V,1. 5V/0. 005A

CORE_VID0_R CORE_VID1_R

VRALERT#

20K_0201_5%

RC744

+3V_PRIM

1 2

RC690 0_0201_5%@ RC689 0_0201_5%@ RC688 0_0201_5%@

VRALERT#_R

PCH_PRIM_EN_R

+VCCA_CLKLDO_1 P8

+VCCDPHY_1P24

+VCC1P05_OUTPUT_PLL

PAD~D

+VCC1.05_OUT_PCH

1 2 1 2 1 2

1 2

0_0402_5%

RC505

DVT1_23

D21

RB751S40T1G_SOD523-2

+VCCPRTC_3P3

@

RC508

@

21

CORE_VID0 CORE_VID1 VRALERT#_R

+VCCDSW_ 1P05

+3VALW_DSW

+3V_1.8V_HDA

CORE_VID0 <78,89> CORE_VID1 <78,89> VRALERT#_R <83>

CC511

@

0.1U_0402_25V6

PCH_PRIM_EN <88,95>

12

1M_0201_5%

H_PROCHOT# <11,58,86,91>

+VCC1.05_OUT_FET

1U_0201_6.3V6K

PLACE NEAR DG33

0.1uF cap should place before the 1uF cap.

Power reserved

CORE_VID0

RC609

@

RC611

@

CORE_VID1

RC610

@

RC612

@

+VCCDSW_1P05

1

CC183 1U_0201_6.3V6M

2

PLACE NEAR DD34

+VCCDPHY_1P24

DVT1_34 : change size

1

CC184

4.7U_0402_6.3V6M

2

PLACE NEAR DW32 WITHIN 3MM FROM PACKAGE

+VCCLDOSTD_OUT_0P85

1

CC260

2.6mm width plane

1

2

12

10K_0201_5 %

12

10K_0201_5 %

12

10K_0201_5 %

12

10K_0201_5 %

CC185 1U_0201_6.3V6K

2

PLACE NEAR DW37 WITHIN 3MM FROM PACKAGE

RC696

@

1 2

0_0402_5%

1

CC181

0.1U_0201_10V6K

CC182 1U_0201_6.3V6M

2

1uF cap should place after the 0.1uF cap.

+1.8V_PRIM

PLACE NEAR DF23

PLACE NEAR DG20

0.8mm width plane

+RTCVCC+VCCPRTC_3P3

CORE_VID0 CORE_VID1

PVT_13,PVT_14,PVT_16,PVT_18

Follow #575759 p.32

+3V_PRIM

+1.8V_PRIM

RC168 0_0402_5%

@

1 2

RC165 0_0402_5%

@

1 2

+3V_1.8V_HDA_R

+3V_PRIM

Close to RC164

1

CC164

@

10P_0201_25V8

2

A A

LC2

BLM18EG221TN1D_2P~D

1 2

2

RF@

CC167

2.2P_0201_25V

1

2

RF@

CC168

2.2P_0201_25V

1

+3V_1.8V_HDA

1

2

CC23

0.1U_0201_10V6K

+VCCPFUSE_3P3+3V_PRIM

RC747 0_0402_5%

@

1 2

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2020/10/01 2018/10/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

Compal Electronics, Inc.

P016 - ICL-U(11/13)PCH Power

LA-H811P

1

16 100Tuesday, December 24, 2019

0.1 (X00)

5

4

3

2

1

UC1O

D D

BC37

BD38 BD39 BD41

BD42 BD43 BD45 BD49

C C

B B

BG41

BH37

BM11

BM45 BM47

BR45 BR49

AC45 AC49 AD10 AD11 AD34 AD37

A11

A46 BA45 BA47 BB11

BB3 BB7

BD3

A48

BD5 BD6 BD7 BE1 BE2 BF3

A49 BF45 BF47

BF7 BG3

BG7

BJ1

BJ2

BJ3 AA45 BJ41 BJ43 BJ45 BJ49

BJ7

BM3

BM5

AA47

BM6 BM7 BP1 BP2 BP3

BP43

BP7

AB11

AB3 AB38 AB39 AB41

A17 AB42 AB43

AB5 AB6

AE6

AF37

A3

GND 1 OF 3

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74

15 of 19

ICL-U_BGA1526

@

VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148

AF45 AF47 AG1 AG11 AG3 AG38 AG39 AG41 A31 AG42 AG43 AG5 AG9 AH2 AH37 AH45 AH49 AJ2 AJ3 A34 AK37 AL2 AL45 AL47 AL6 AM2 AM37 AN2 AN38 AN39 A36 AN41 AN42 AN43 AN45 AN49 AN6 AR1 AR11 AR2 AR3 A39 AR7 AR9 AT3 AT45 AT47 AT5 AT6 AT7 AU37 AV11 A42 AV3 AV38 AV39 AV41 AV42 AV43 AV45 AV49 AV7 AY3 A44 AY7 B17 B2 B21 B24 B3 B31 B48 BA1 BA2

BT39 BT41 BT42 BT43

BU45 BU47

BV1

BV11

BV2 BV3 BV7

BW3

BW37

BW5 BW6

BW7 BY37 BY45 BY49

CA3 CA38 CA41 CA42 CA43

CA7 CB37 CB45 CB47

CC3

CC7 CE37 CE45 CE49

CE9 CG37 CG39 CG43 CG45 CG47

CG9

CH3

CH5

CJ37 CJ42

CK45 CK49

CK9

CL37 CL42

CL49 CM45 CM47

CM9

CN3 CN37 CN39

CN5

CP9 CR32

BT3

BT7

C11 C13 C14 C17 C21 C24 C31 C34 C39 C48 C49

CJ9

C6

UC1P

GND 2 OF 3

VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222

16 of 19

ICL-U_BGA1526

@

VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296

CR37 CR45 CR49 CT37 CT39 CT42 CT9 CU45 CU47 CU49 CV3 CV34 CV35 CV5 CV9 CY41 CY45 CY49 CY9 D13 D17 D31 D44 D49 DA10 DA33 DA9 DB32 DB35 DB38 DB45 DB47 DB49 DC3 DC49 DC5 DC6 DD37 DD42 DE10 DE13 DE17 DE18 DE20 DE22 DE23 DE26 DE28 DE29 DE33 DE45 DE6 DF13 DF22 DF28 DF33 DF35 DF39 DG10 DG12 DG13 DG15 DG22 DG23 DG47 DG6 DH1 DH3 DH45 DH5 DJ19 DJ21 DJ27 DJ31

DJ33 DJ36 DJ42

DK3 DK4

DK49

DK6

DK8 DL10 DL13 DL44 DL47

DM47

DN15 DN19 DN24 DN31 DN36 DN42 DP45 DR49

DT1

DT10 DT15 DT20 DT27

DT3

DT32 DT37 DT42 DT49

DT6

DT7

DT8

DU1

DU10 DU15

DU2

DU20 DU27 DU32 DU37 DU48 DU49

DU7

DV2

DV44 DV48

DV8 DW1

DW10

DW2

DW20 DW27 DW44 DW46 DW48 DW49

DW7

E11 E34 E36 E39 E42

E6

UC1Q

GND 3 OF 3

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361

17 of 19

ICL-U_BGA1526

@

VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369 VSS_370 VSS_371 VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395 VSS_396 VSS_397 VSS_398 VSS_399 VSS_400 VSS_401 VSS_402 VSS_403 VSS_404 VSS_405 VSS_406 VSS_407 VSS_408 VSS_409 VSS_410 VSS_411 VSS_412 VSS_413 VSS_414 VSS_415 VSS_416 VSS_417 VSS_418 VSS_419 VSS_420 VSS_421 VSS_422 VSS_423 VSS_424 VSS_425 VSS_426 VSS_427

F11 F31 F45 F47 F8 G21 G24 G3 G31 G36 G49 G5 H17 H21 H24 H31 H33 H36 H45 H49 J10 J13 J16 J36 J6 K11 K33 K8 L36 L39 L41 L42 L43 L45 L47 M10 M3 M36 M5 N45 N49 P11 P41 P8 R3 R37 T11 T36 T41 T43 T45 T47 U3 U37 U5 V11 V36 V45 V49 V9 W37 Y36 Y38 Y43 Y9 DE15

A A

Security Classification

2020/10/ 01 2018/10/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2020/10/ 01 2018/10/ 01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

P017 - ICL-U(12/13)GND

LA-H811P

1

0.1 (X00)

17 100Tuesday, December 24, 2019

0.1 (X00)

5

MIPI60_CFG0#<79> MIPI60_CFG1#<79> MIPI60_CFG2#<79> MIPI60_CFG3#<79> MIPI60_CFG4#<79> MIPI60_CFG5#<79> MIPI60_CFG6#<79> MIPI60_CFG7#<79> MIPI60_CFG8#<79> MIPI60_CFG9#<79>

MBP2# MBP3#

MIPI60_CFG10#<79> MIPI60_CFG11#<79> MIPI60_CFG12#<79> MIPI60_CFG13#<79> MIPI60_CFG14#<79> MIPI60_CFG15#<79>

MIPI60_CFG_STB0_DN<79> MIPI60_CFG_STB0_DP<79>

MIPI60_CFG_STB1_DN<79> MIPI60_CFG_STB1_DP<79>

1 2

MIPI60_MBP0#<79> MIPI60_MBP1#<79>

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

D D

+VCCIO_OUT

RC723 10K_0201_5%@

1 2

RC724 10K_0201_5%@

1 2

C C

B B

A A

5

TP88 TP89

TP90 TP91 TP92

TP93 TP94 TP95

TP67

TP68

4

CFG_RCOM

RC249.9_0201_1%

MBP2# MBP3#

TP_N34

1

TP_AK10

1

TP_AH10

1

TP_BC10

1

TP_CH33

1

TP_AM10

1

TP_BH10

1

TP_J34

1

RSVD_L34

1

RSVD_M34

1

4

UC1S

AG6

CFG_0

AE7

CFG_1

AG7

CFG_2

AD9

CFG_3

AE9

CFG_4

AB9

CFG_5

AJ6

CFG_6

AB7

CFG_7

V10

CFG_8

AJ5

CFG_9

Y10

CFG_10

AJ7

CFG_11

AB10

CFG_12

AL7

CFG_13

AL9

CFG_14

AJ9

CFG_15

V6

CFG_16

V7

CFG_17

Y6

CFG_18

Y7

CFG_19

AD6

CFG_RCOMP

T9

BPM#0

T7

BPM#1

T10

BPM#2

T6

BPM#3

BJ11

RSVD_62

BL10

RSVD_63

AV1

RSVD_TP_17

AT2

RSVD_TP_18

AT1

RSVD_TP_20

AU1

RSVD_TP_19

AU2

RSVD_TP_21

AV2

RSVD_TP_22

DP3

RSVD_67

DT2

RSVD_68

AR10

RSVD_69

AP10

RSVD_71

BP36

RSVD_70

BM36

RSVD_72

J15

VSS_430

K15

VSS_431

C5

SKTOCC#

D4

RSVD_77

A5

RSVD_64

ICL-U_BGA1526

@

UC1R

N34

RSVD_TP_28

AK10

RSVD_TP_29

BT36

RSVD_7

AH10

RSVD_TP_30

BC10

RSVD_TP_31

CH33

RSVD_TP_32

CJ32

RSVD_12

AM10

RSVD_TP_33

BH10

RSVD_TP_34

J34

RSVD_TP_27

Y11

RSVD_9

L34

RSVD_10

AJ11

RSVD_17

CG32

RSVD_21

CK33

RSVD_22

BP41

RSVD_20

AL11

RSVD_23

BG11

RSVD_24

AN11

RSVD_16

M13

RSVD_18

M34

RSVD_19

DU42

RSVD_42

DW42

RSVD_43

D33

RSVD_44

L13

RSVD_45

K13

RSVD_47

ICL-U_BGA1526

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RESERVED SIGNALS

19 of 19

RESERVED SIGNALS

3

RSVD_57 RSVD_58

RSVD_79 RSVD_80

VSS_428 VSS_429

RSVD_55 RSVD_56

RSVD_65 RSVD_66

RSVD_59 RSVD_60

TP_3 TP_4

TP_1 TP_2

VSS_432

RSVD_32 RSVD_33 RSVD_34

IST_TP_0 IST_TP_1

RSVD_27 RSVD_28

RSVD_35 RSVD_46 RSVD_48 RSVD_49 RSVD_50 RSVD_51 RSVD_52 RSVD_53 RSVD_54 RSVD_36 RSVD_37 RSVD_38 RSVD_39 RSVD_40 RSVD_41

A47 B47

C1 E1

CT32 CV32

G15 F15

BW11 CA11

C16 A16

C2 A4

DP5 DR5

D14 E16

DV6 DW6

DP2 DP1

DW4 DV4

CM33 DB10

R1

DW3 DV3

DH49

DL8

DW47 DV47 DU47

P10

DA11 CL32 CN32 CY35 DB37 DF37

BF11 BD11 BE10 BF10

CW33 CY32

CY37 CV37

G34 H34 DJ34 DK31 DK15 CP3 CP5 AN9 AN7 AF10 AE11 H5 D1 DJ40 DK40

TP_C1 TP_E1

TP_G15 TP_F15

TP_BW11 TP_CA11

TP_CM33 TP_DB10

TP_R1

TP_DW3 TP_DV3

TP_DW47 TP_DV47

TP_DA11 TP_CL32 TP_CN32

IST_TP_0 IST_TP_1 IST_TRIG_0 IST_TRIG_1

PCH_IST_TP_0 PCH_IST_TP_1

Compal Secret Data

Deciphered Date

1

TP59 PAD~D

1

TP60 PAD~D

1

TP8 PAD~D

1

TP7 PAD~D

1

TP3 PAD~D

1

TP4 PAD~D

1

TP16

1

TP15

1

TP18

1

TP17 PAD~D

1

TP19 PAD~D

1

TP23

1

TP24

1

TP96

1

TP97

1

TP98

1

TP62

1

TP61

1

TP64

1

TP63

1

TP66

1

TP65

RSVD_TP_1 RSVD_TP_2

RSVD_TP_10 RSVD_TP_11

RSVD_TP_5 RSVD_TP_6

RSVD_TP_13 RSVD_TP_14

RSVD_TP_24 RSVD_TP_25

RSVD_TP_15 RSVD_TP_16

RSVD_TP_12

RSVD_TP_7 RSVD_TP_8

RSVD_TP_9

RSVD_TP_23

RSVD_TP_26

RSVD_TP_35 RSVD_TP_36 RSVD_TP_37

IST_TRIG_0 IST_TRIG_1

PCH_IST_TP_0 PCH_IST_TP_1

2020/10/ 01 2018/10/ 01

3

2

TP@ TP@

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@ TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

TP@

PAD~D

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

P018 - ICL-U(13/13)RSVD,MIPI60

LA-H811P

1

0.1 (X00)

18 100Tuesday, December 24, 2019

1

0.1 (X00)

5

D D

C C

4

3

2

1

B B

A A

Security Classification

2020/10/ 01 2018/10/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2020/10/ 01 2018/10/ 01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

P019 - Reserve

LA-H811P

0.1 (X00)

19 100Tuesday, December 24, 2019

1

0.1 (X00)

5

D D

C C

4

3

2

1

B B

A A

Security Classification

2020/10/ 01 2018/10/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2020/10/ 01 2018/10/ 01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

P020 - Reserve

LA-H811P

0.1 (X00)

20 100Tuesday, December 24, 2019

1

0.1 (X00)

5

D D

C C

4

3

2

1

B B

A A

Security Classification

2020/10/ 01 2018/10/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2020/10/ 01 2018/10/ 01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

P021 - Reserve

LA-H811P

0.1 (X00)

21 100Tuesday, December 24, 2019

1

0.1 (X00)

5

D D

C C

4

3

2

1

B B

A A

Security Classification

2020/10/ 01 2018/10/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2020/10/ 01 2018/10/ 01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

P022 - Reserve

LA-H811P

0.1 (X00)

22 100Tuesday, December 24, 2019

1

0.1 (X00)

5

4

3

2

1

Memory connection refer 573975 Rev1P1

D D

+1.1V_MEM

RD25

0_0201_5%@

1 2

DDR_A_ODTA

12

RD26

@

0_0201_5%

ODT PD reserved -- CRB P.83

+1.1V_MEM +1.1V_MEM

RD27

0_0201_5%@

1 2

DDR_A_ODTB DDR_B_ODTB

12

RD28

@

0_0201_5%

C C

B B

ODT PD reserved -- CRB P.83

+VDDQ_MEM

1 2

RD2 240_0201_1%

1 2

RD1 240_0201_1%

DDR_A_CA0

DDR_A_CA0<7>

DDR_A_CA1

DDR_A_CA1<7>

DDR_A_CA2

DDR_A_CA2<7>

DDR_A_CA3 DDR_B_CA3

DDR_A_CA3<7>

DDR_A_CA4

DDR_A_CA4<7>

DDR_A_CA5

DDR_A_CA5<7>

DDR_A_CA0 DDR_A_CA1 DDR_A_CA2 DDR_A_CA3 DDR_A_CA4 DDR_A_CA5

DDR_A_ODTA DDR_A_ODTB

DDR_A_D3_2

DDR_A_D3_2<7>

DDR_A_D3_0

DDR_A_D3_0<7>

DDR_A_D3_1

DDR_A_D3_1<7>

DDR_A_D3_4

DDR_A_D3_4<7>

DDR_A_D3_3

DDR_A_D3_3<7>

DDR_A_D3_5

DDR_A_D3_5<7>

DDR_A_D3_6

DDR_A_D3_6<7>

DDR_A_D3_7

DDR_A_D3_7<7>

DDR_A_D2_4

DDR_A_D2_4<7> DDR_A_D1_3 <7>

DDR_A_D2_1

DDR_A_D2_1<7>

DDR_A_D2_3

DDR_A_D2_3<7>

DDR_A_D2_6

DDR_A_D2_6<7>

DDR_A_D2_7

DDR_A_D2_7<7>

DDR_A_D2_5

DDR_A_D2_5<7>

DDR_A_D2_0

DDR_A_D2_0<7>

DDR_A_D2_2

DDR_A_D2_2<7>

DDR_A_DQS3

DDR_A_DQS3<7>

DDR_A_DQS#3

DDR_A_DQS#3<7>

DDR_A_DQS2

DDR_A_DQS2<7>

DDR_A_DQS#2

DDR_A_DQS#2<7>

95mA

422mA

+1.8V_MEM

+1.1V_MEM

UD1C

F1

VDD1_1

VDDQ_1

F12

VDD1_2

VDDQ_2

G4

VDD1_3

VDDQ_3

G9

VDD1_4

VDDQ_4

T4

VDD1_5

VDDQ_5

T9

VDD1_6

VDDQ_6

U1

VDD1_7

VDDQ_7

U12

VDD1_8

VDDQ_8 VDDQ_9

VDDQ_10

A4

VDD2_1

VDDQ_11

A9

VDD2_2

VDDQ_12

F5

VDD2_3

VDDQ_13

F8

VDD2_4

VDDQ_14

H1

VDD2_5

VDDQ_15

H5

VDD2_6

VDDQ_16

H8

VDD2_7

VDDQ_17

H12

VDD2_8

VDDQ_18

K1

VDD2_9

VDDQ_19

K3

VDD2_10

VDDQ_20

K10

VDD2_11

K12

VDD2_12

N1

VDD2_13

NC_1

N3

VDD2_14

N10 N12

R12

AB4 AB9

NC_2

VDD2_15

NC_3

VDD2_16

NC_4

R1

VDD2_17

NC_5

R5

VDD2_18

R8

VDD2_19 VDD2_20

U5

VDD2_21

U8

VDD2_22 VDD2_23 VDD2_24

H9HCNNNBUUMLHR-NLM_FBGA200

@

UD1 UD2

+1.8V_MEM

12

CD68

CD67

1U_0201_10V6M

+1.1V_MEM

12

CD69

1U_0201_10V6M

12

CD70

CD71

1U_0201_10V6M

12

CD72

CD73

1U_0201_10V6M

DDRA DDRB

UD1A

A5

ZQ0

A8

ZQ1

H2

CA0a

J2

CA1a

H9

CA2a

H10

CA3a

H11

CA4a

J11

CA5a

R2

CA0b

P2

CA1b

R9

CA2b

R10

CA3b

R11

CA4b

P11

CA5b

G2

ODTa

T2

ODTb

A1

DNU_1

A2

DNU_2

A11

DNU_3

A12

DNU_4

B1

DNU_5

B12

DNU_6

AA1

DNU_7

AA12

DNU_8

AB1

DNU_9

AB2

DNU_10

AB11

DNU_11

AB12

DNU_12

B2

DQ0a

C2

DQ1a

E2

DQ2a

F2

DQ3a

F4

DQ4a

E4

DQ5a

C4

DQ6a

B4

DQ7a

B11

DQ8a

C11

DQ9a

E11

DQ10a

F11

DQ11a

F9

DQ12a

E9

DQ13a

C9

DQ14a

B9

DQ15a

D3

DQS0_ta

E3

DQS0_ca

D10

DQS1_ta

E10

DQS1_ca

H9HCNNNBUUMLHR-NLM_FBGA200

@

+VDDQ_MEM

B3 B5 B8 B10 D1 D5 D8 D12 F3 F10 U3 U10 W1 W5 W8 W12 AA3 AA5 AA8 AA10

G11 K5 K8 N5 N8

12

CD74

CD75

1U_0201_10V6M

323mA

+VDDQ_MEM

12

CD77

CD76

1U_0201_10V6M

DDR_A_CLK

J8

DDR_A_CLK#

CK_ta

J9

CK_ca

DDR_A_CLK

P8

DDR_A_CLK#

CK_tb

P9

CK_cb

DDR_A_CKE0

J4

CKE0a

DDR_A_CKE1

J5

CKE1a

DDR_A_CKE0

P4

CKE0b

DDR_A_CKE1

P5

CKE1b

DDR_A_CS#0

H4

CS0a

DDR_A_CS#1

H3

CS1a

DDR_A_CS#0

R4

CS0b

DDR_A_CS#1

R3

CS1b

C3

DMI0a

C10

DMI1a

Y3

DMI0b

Y10

DMI1b

DDR_DRAMRST#_R

T11

RESET

AA2

DQ0b

Y2

DQ1b

V2

DQ2b

U2

DQ3b

U4

DQ4b

V4

DQ5b

Y4

DQ6b

AA4

DQ7b

AA11

DQ8b

Y11

DQ9b

V11

DQ10b

U11

DQ11b

U9

DQ12b

V9

DQ13b

Y9

DQ14b

AA9

DQ15b

W3

DQS0_tb

V3

DQS0_cb

W10

DQS1_tb

V10

DQS1_cb

UD1B

A3

VSS_1

VSS_30

A10

VSS_2

VSS_31

C1

VSS_3

VSS_32

C5

VSS_4

VSS_33

C8

VSS_5

VSS_34

C12

VSS_6

VSS_35

D2

VSS_7

VSS_36

D4

VSS_8

VSS_37

D9

VSS_9

VSS_38

D11

VSS_10

VSS_39

E1

VSS_11

VSS_40

E5

VSS_12

VSS_41

E8

VSS_13

VSS_42

E12

VSS_14

VSS_43

G1

VSS_15

VSS_44

G3

VSS_16

VSS_45

G5

VSS_17

VSS_46

G8

VSS_18

VSS_47

G10

VSS_19

VSS_48

G12

VSS_20

VSS_49

J1

VSS_21

VSS_50

J3

VSS_22

VSS_51

J10

VSS_23

VSS_52

J12

VSS_24

VSS_53

K2

VSS_25

VSS_54

K4

VSS_26

VSS_55

K9

VSS_27

VSS_56

K11

VSS_57

VSS_28

N2

VSS_58

VSS_29

H9HCNNNBUUMLHR-NLM_FBGA200

@

12

CD80

CD78

CD79

1U_0201_10V6M

DDR_A_CLK <7> DDR_A_CLK# <7>

DDR_A_CKE0 <7>

DDR_A_CKE1 <7>

DDR_A_CS#0 <7>

DDR_A_CS#1 <7>

SHORTEST PATH TO GND

DDR_DRAMRST#_R <7,24>

DDR_A_D0_6 DDR_A_D0_1 DDR_A_D0_5 DDR_A_D0_3 DDR_A_D0_7 DDR_A_D0_2 DDR_A_D0_0 DDR_A_D0_4 DDR_A_D1_3 DDR_A_D1_6 DDR_A_D1_2 DDR_A_D1_1 DDR_A_D1_4 DDR_A_D1_0 DDR_A_D1_5 DDR_A_D1_7

DDR_A_DQS0 DDR_A_DQS#0

DDR_A_DQS1 DDR_A_DQS#1

DDR_A_D0_6 <7> DDR_A_D0_1 <7> DDR_A_D0_5 <7> DDR_A_D0_3 <7> DDR_A_D0_7 <7> DDR_A_D0_2 <7> DDR_A_D0_0 <7> DDR_A_D0_4 <7>

DDR_A_D1_6 <7> DDR_A_D1_2 <7> DDR_A_D1_1 <7> DDR_A_D1_4 <7> DDR_A_D1_0 <7> DDR_A_D1_5 <7> DDR_A_D1_7 <7>

DDR_A_DQS0 <7> DDR_A_DQS#0 <7>

DDR_A_DQS1 <7> DDR_A_DQS#1 <7>

N4 N9 N11 P1 P3 P10 P12 T1 T3 T5 T8 T10 T12 V1 V5 V8 V12 W2 W4 W9 W11 Y1 Y5 Y8 Y12 AB3 AB5 AB8 AB10

ODT PD reserved -- CRB P.84

+VDDQ_MEM

CD45

1

12P_0201_50V8J

2

@EMI@

+VDDQ_MEM

1

CD27

2.2P_0201_50V8B

2

@EMI@

+1.1V_MEM

1 2

DDR_B_ODTA

12

1 2

12

CD46

CD47

CD48

1

12P_0201_50V8J

2

@EMI@

1

CD28

CD44

CD43

2.2P_0201_50V8B

2

@EMI@

+VDDQ_MEM

RD29

0_0201_5%@

RD30

@

0_0201_5%

ODT PD reserved -- CRB P.84

RD31

0_0201_5%@

DDR_B_D1_6<7>

RD32

@

DDR_B_D1_2<7>

0_0201_5%

DDR_B_D1_4<7> DDR_B_D1_1<7> DDR_B_D1_0<7> DDR_B_D1_3<7> DDR_B_D1_5<7> DDR_B_D0_4<7> DDR_B_D0_1<7> DDR_B_D0_6<7> DDR_B_D0_5<7> DDR_B_D0_7<7> DDR_B_D0_3<7> DDR_B_D0_2<7> DDR_B_D0_0<7>

DDR_B_DQS1<7> DDR_B_DQS#1<7>

DDR_B_DQS0<7> DDR_B_DQS#0<7>

CD50

CD49

CD91

1

12P_0201_50V8J

2

@EMI@

1

CD81

CD65

CD66

2.2P_0201_50V8B

2

@EMI@

RD21 240_0201_1%

1 2

RD22 240_0201_1%

1 2

DDR_B_CA0<7> DDR_B_CA1<7> DDR_B_CA2<7> DDR_B_CA3<7> DDR_B_CA4<7> DDR_B_CA5<7>

DDR_B_D1_7 DDR_B_D1_6 DDR_B_D1_2 DDR_B_D1_4 DDR_B_D1_1 DDR_B_D1_0 DDR_B_D1_3 DDR_B_D1_5 DDR_B_D0_4 DDR_B_D0_1 DDR_B_D0_6 DDR_B_D0_5 DDR_B_D0_7 DDR_B_D0_3 DDR_B_D0_2 DDR_B_D0_0

DDR_B_DQS1 DDR_B_DQS#1

DDR_B_DQS0 DDR_B_DQS#0

+1.8V_MEM

95mA

+1.1V_MEM

422mA

12P_0201_50V8J

2.2P_0201_50V8B

A5

A8

DDR_B_CA0

H2

DDR_B_CA1

J2

DDR_B_CA2

H9

H10

DDR_B_CA4

H11

DDR_B_CA5

J11

DDR_B_CA0

R2

DDR_B_CA1

P2

DDR_B_CA2

R9

DDR_B_CA3

R10

DDR_B_CA4

R11

DDR_B_CA5

P11

DDR_B_ODTA

G2

DDR_B_ODTB

T2

A1

A2 A11 A12

B1 B12

AA1

AA12

AB1

AB2 AB11 AB12

B2 C2 E2 F2 F4 E4 C4

B4 B11 C11 E11 F11

F9

E9

C9

B9

D3

E3

D10 E10

UD2C

F1

VDD1_1

F12

VDD1_2

G4

VDD1_3

G9

VDD1_4

T4

VDD1_5

T9

VDD1_6

U1

VDD1_7

U12

VDD1_8

A4

VDD2_1

A9

VDD2_2

F5

VDD2_3

F8

VDD2_4

H1

VDD2_5

H5

VDD2_6

H8

VDD2_7

H12

VDD2_8

K1

VDD2_9

K3

VDD2_10

K10

VDD2_11

K12

VDD2_12

N1

VDD2_13

N3

VDD2_14

N10

VDD2_15

N12

VDD2_16

R1

VDD2_17

R5

VDD2_18

R8

VDD2_19

R12

VDD2_20

U5

VDD2_21

U8

VDD2_22

AB4

VDD2_23

AB9

VDD2_24

H9HCNNNBUUMLHR-NLM_FBGA200

@

+1.8V_MEM

12

UD2A

ZQ0

ZQ1

CA0a CA1a CA2a CA3a CA4a CA5a

CA0b CA1b CA2b CA3b CA4b CA5b

ODTa ODTb

DNU_1 DNU_2 DNU_3 DNU_4 DNU_5 DNU_6 DNU_7 DNU_8 DNU_9 DNU_10 DNU_11 DNU_12

DQ0a DQ1a DQ2a DQ3a DQ4a DQ5a DQ6a DQ7a DQ8a DQ9a DQ10a DQ11a DQ12a DQ13a DQ14a DQ15a

DQS0_ta DQS0_ca

DQS1_ta DQS1_ca

H9HCNNNBUUMLHR-NLM_FBGA200

@

+VDDQ_MEM

B3

VDDQ_1

B5

VDDQ_2

B8

VDDQ_3

B10

VDDQ_4

D1

VDDQ_5

D5

VDDQ_6

D8

VDDQ_7

D12

VDDQ_8

F3

VDDQ_9

F10

VDDQ_10

U3

VDDQ_11

U10

VDDQ_12

W1

VDDQ_13

W5

VDDQ_14

W8

VDDQ_15

W12

VDDQ_16

AA3

VDDQ_17

AA5

VDDQ_18

AA8

VDDQ_19

AA10

VDDQ_20

G11

NC_1

K5

NC_2

K8

NC_3

N5

NC_4

N8

NC_5

12

CD51

CD53

CD52

1U_0201_10V6M

12

323mA

CD54

1U_0201_10V6M

DQS0_tb

DQS0_cb

DQS1_tb

DQS1_cb

CK_ta

CK_ca

CK_tb

CK_cb

CKE0a

CKE1a

CKE0b

CKE1b

CS0a

CS1a

CS0b

CS1b

DMI0a DMI1a

DMI0b DMI1b

RESET

DQ0b DQ1b DQ2b DQ3b DQ4b DQ5b DQ6b DQ7b DQ8b

DQ9b DQ10b DQ11b DQ12b DQ13b DQ14b DQ15b

+1.1V_MEM

J8 J9

P8 P9

J4

J5

P4

P5

H4

H3

R4

R3

C3 C10

Y3 Y10

T11

AA2 Y2 V2 U2 U4 V4 Y4 AA4 AA11 Y11 V11 U11 U9 V9 Y9 AA9

W3 V3

W10 V10

12

CD55

1U_0201_10V6M

DDR_B_CLK DDR_B_CLK#

DDR_B_CLK

DDR_B_CLK#

DDR_B_CKE0

DDR_B_CKE1

DDR_B_CKE0

DDR_B_CKE1

DDR_B_CS#0

DDR_B_CS#1

DDR_B_CS#0

DDR_B_CS#1

SHORTEST PATH TO GND

DDR_DRAMRST#_R

DDR_B_D3_6 DDR_B_D3_2 DDR_B_D3_0 DDR_B_D3_1 DDR_B_D3_3 DDR_B_D3_7 DDR_B_D3_5 DDR_B_D3_4 DDR_B_D2_5 DDR_B_D2_6 DDR_B_D2_2 DDR_B_D2_4 DDR_B_D2_1 DDR_B_D2_0 DDR_B_D2_3 DDR_B_D2_7

DDR_B_DQS3 DDR_B_DQS#3

DDR_B_DQS2 DDR_B_DQS#2

UD2B

A3

VSS_1

A10

VSS_2

C1

VSS_3

C5

VSS_4

C8

VSS_5

C12

VSS_6

D2

VSS_7

D4

VSS_8

D9

VSS_9

D11

VSS_10

E1

VSS_11

E5

VSS_12

E8

VSS_13

E12

VSS_14

G1

VSS_15

G3

VSS_16

G5

VSS_17

G8

VSS_18

G10

VSS_19

G12

VSS_20

J1

VSS_21

J3

VSS_22

J10

VSS_23

J12

VSS_24

K2

VSS_25

K4

VSS_26

K9

VSS_27

K11

VSS_28

N2

VSS_29

H9HCNNNBUUMLHR-NLM_FBGA200

@

12

CD57

CD56

1U_0201_10V6M

VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58

12

CD58

1U_0201_10V6M

DDR_B_CLK <7> DDR_B_CLK# <7>

DDR_B_CKE0 <7>

DDR_B_CKE1 <7>

DDR_B_CS#0 <7>

DDR_B_CS#1 <7>

DDR_B_D3_6 <7>DDR_B_D1_7<7> DDR_B_D3_2 <7> DDR_B_D3_0 <7> DDR_B_D3_1 <7> DDR_B_D3_3 <7> DDR_B_D3_7 <7> DDR_B_D3_5 <7> DDR_B_D3_4 <7> DDR_B_D2_5 <7> DDR_B_D2_6 <7> DDR_B_D2_2 <7> DDR_B_D2_4 <7> DDR_B_D2_1 <7> DDR_B_D2_0 <7> DDR_B_D2_3 <7> DDR_B_D2_7 <7>

DDR_B_DQS3 <7> DDR_B_DQS#3 <7>

DDR_B_DQS2 <7> DDR_B_DQS#2 <7>

N4 N9 N11 P1 P3 P10 P12 T1 T3 T5 T8 T10 T12 V1 V5 V8 V12 W2 W4 W9 W11 Y1 Y5 Y8 Y12 AB3 AB5 AB8 AB10

12

CD59

1U_0201_10V6M

+VDDQ_MEM

12

CD60

1U_0201_10V6M

12

CD64

CD62

CD61

CD63

1U_0201_10V6M

+1.8V_MEM

1

CD303

CD305

10U_0402_6.3V6M

2

A A

5

+1.1V_MEM

1

CD308

CD306

1

CD310

10U_0402_6.3V6M

RF@

100P_0201_50V8J

2

CD311

RF@

100P_0201_50V8J

10U_0402_6.3V6M

2

+VDDQ_MEM

1

CD89

10U_0402_6.3V6M

2

4

CD312

CD90

RF@

100P_0201_50V8J

10U_0402_6.3V6M

2

EMC CAPS

+1.8V_MEM

1

CD304

CD12

10U_0402_6.3V6M

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT O F COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT O F COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT O F COMPAL ELECTRONICS, INC.

+1.1V_MEM

1

CD313

RF@

100P_0201_50V8J

2

1

CD7

CD307

10U_0402_6.3V6M

2

Compal Secret Data

2020/10/01 2018/10/01

CD314

RF@

100P_0201_50V8J

Deciphered Date

+VDDQ_MEM

1

CD87

10U_0402_6.3V6M

2

CD315

CD88

RF@

100P_0201_50V8J

10U_0402_6.3V6M

2

Compal Electronics, Inc.

Title

P023 - LPDDR4/x Channel A/B

Size

Document N umber Rev

LA-H811P

Date: Sheet o f

1

0.1 (X00)

23 100Tuesday, December 24, 2019

5

4

3

2

1

Memory connection refer 573975 Rev1P1

D D

+1.1V_MEM

RD33

0_0201_5%@

1 2

DDR_C_ODTA

12

RD34

@

0_0201_5%

ODT PD reserved -- CRB P.85

+1.1V_MEM

RD35

0_0201_5%@

1 2

DDR_C_ODTB

12

RD36

C C

0_0201_5%

@

ODT PD reserved -- CRB P.85

B B

+VDDQ_MEM +VDDQ_MEM

1 2

RD4 240_0201_1%

1 2

RD3 240_0201_1%

DDR_C_CA0

DDR_C_CA0<8>

DDR_C_CA1

DDR_C_CA1<8>

DDR_C_CA2

DDR_C_CA2<8>

DDR_C_CA3

DDR_C_CA3<8>

DDR_C_CA4

DDR_C_CA4<8>

DDR_C_CA5

DDR_C_CA5<8>

DDR_C_CA0 DDR_C_CA1 DDR_C_CA2 DDR_C_CA3 DDR_C_CA4 DDR_C_CA5

DDR_C_ODTA

DDR_C_ODTB

DDR_C_D3_5

DDR_C_D3_5<8>

DDR_C_D3_6

DDR_C_D3_6<8>

DDR_C_D3_1

DDR_C_D3_1<8>

DDR_C_D3_0

DDR_C_D3_0<8>

DDR_C_D3_4

DDR_C_D3_4<8>

DDR_C_D3_2

DDR_C_D3_2<8>

DDR_C_D3_7

DDR_C_D3_7<8>

DDR_C_D3_3

DDR_C_D3_3<8>

DDR_C_D2_3

DDR_C_D2_3<8>

DDR_C_D2_7

DDR_C_D2_7<8>

DDR_C_D2_4

DDR_C_D2_4<8>

DDR_C_D2_2

DDR_C_D2_2<8>

DDR_C_D2_5

DDR_C_D2_5<8>

DDR_C_D2_1

DDR_C_D2_1<8>

DDR_C_D2_0

DDR_C_D2_0<8>

DDR_C_D2_6

DDR_C_D2_6<8>

DDR_C_DQS3

DDR_C_DQS3<8>

DDR_C_DQS#3

DDR_C_DQS#3<8>

DDR_C_DQS2

DDR_C_DQS2<8>

DDR_C_DQS#2

DDR_C_DQS#2<8>

+1.8V_MEM

95mA

+1.1V_MEM

422mA

+1.8V_MEM

12

CD30

CD31

CD29

1U_0201_10V6M

UD3A

A5

ZQ0

A8

ZQ1

H2

CA0a

J2

CA1a

H9

CA2a

H10

CA3a

H11

CA4a

J11

CA5a

R2

CA0b

P2

CA1b

R9

CA2b

R10

CA3b

R11

CA4b

P11

CA5b

G2

ODTa

T2

ODTb

A1

DNU_1

A2

DNU_2

A11

DNU_3

A12

DNU_4

B1

DNU_5

B12

DNU_6

AA1

DNU_7

AA12

DNU_8

AB1

DNU_9

AB2

DNU_10

AB11

DNU_11

AB12

DNU_12

B2

DQ0a

C2

DQ1a

E2

DQ2a

F2

DQ3a

F4

DQ4a

E4

DQ5a

C4

DQ6a

B4

DQ7a

B11

DQ8a

C11

DQ9a

E11

DQ10a

F11

DQ11a

F9

DQ12a

E9

DQ13a

C9

DQ14a

B9

DQ15a

D3

DQS0_ta

E3

DQS0_ca

D10

DQS1_ta

E10

DQS1_ca

H9HCNNNBUUMLHR-NLM_FBGA200

@

UD3C

F1

VDD1_1

F12

VDD1_2

G4

VDD1_3

G9

VDD1_4

T4

VDD1_5

T9

VDD1_6

U1

VDD1_7

U12

VDD1_8

A4

VDD2_1

A9

VDD2_2

F5

VDD2_3

F8

VDD2_4

H1

VDD2_5

H5

VDD2_6

H8

VDD2_7

H12

VDD2_8

K1

VDD2_9

K3

VDD2_10

K10

VDD2_11

K12

VDD2_12

N1

VDD2_13

N3

VDD2_14

N10

VDD2_15

N12

VDD2_16

R1

VDD2_17

R5

VDD2_18

R8

VDD2_19

R12

VDD2_20

U5

VDD2_21

U8

VDD2_22

AB4

VDD2_23

AB9

VDD2_24

H9HCNNNBUUMLHR-NLM_FBGA200

@

12

CD32

CD33

1U_0201_10V6M

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8

VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20

12

CD34

1U_0201_10V6M

DDR_C_CLK

J8

CK_ta

J9

CK_ca

P8

CK_tb

P9

CK_cb

J4

CKE0a

J5

CKE1a

P4

CKE0b

P5

CKE1b

H4

CS0a

H3

CS1a

R4

CS0b

R3

CS1b

C3

DMI0a

C10

DMI1a

Y3

DMI0b

Y10

DMI1b

DDR_DRAMRST#_R DDR_DRAMRST#_R

T11

RESET

AA2

DQ0b

Y2

DQ1b

V2

DQ2b

U2

DQ3b

U4

DQ4b

V4

DQ5b

Y4

DQ6b

AA4

DQ7b

AA11

DQ8b

Y11

DQ9b

V11

DQ10b

U11

DQ11b

U9

DQ12b

V9

DQ13b

Y9

DQ14b

AA9

DQ15b

W3

DQS0_tb

V3

DQS0_cb

W10

DQS1_tb

V10

DQS1_cb

+VDDQ_MEM

323mA

B3 B5 B8 B10 D1 D5 D8 D12 F3 F10 U3 U10 W1 W5 W8 W12 AA3 AA5 AA8 AA10

G11

NC_1

K5

NC_2

K8

NC_3

N5

NC_4

N8

NC_5

+VDDQ_MEM+1.1V_MEM

12

CD35

1U_0201_10V6M

12

CD37

CD36

CD38

1U_0201_10V6M

DDR_C_CLK#

DDR_C_CLK DDR_C_CLK#

DDR_C_CKE0

DDR_C_CKE1

DDR_C_CKE0

DDR_C_CKE1

DDR_C_CS#0

DDR_C_CS#1

DDR_C_CS#0

DDR_C_CS#1

DDR_C_D0_0 DDR_C_D0_2 DDR_C_D0_1 DDR_C_D0_4 DDR_C_D0_3 DDR_C_D0_7 DDR_C_D0_6 DDR_C_D0_5 DDR_C_D1_6 DDR_C_D1_3 DDR_C_D1_7 DDR_C_D1_2 DDR_C_D1_0 DDR_C_D1_5 DDR_C_D1_1 DDR_C_D1_4

DDR_C_DQS0 DDR_C_DQS#0

DDR_C_DQS1 DDR_C_DQS#1

UD3B

A3

VSS_1

A10

VSS_2

C1

VSS_3

C5

VSS_4

C8

VSS_5

C12

VSS_6

D2

VSS_7

D4

VSS_8

D9

VSS_9

D11

VSS_10

E1

VSS_11

E5

VSS_12

E8

VSS_13

E12

VSS_14

G1

VSS_15

G3

VSS_16

G5

VSS_17

G8

VSS_18

G10

VSS_19

G12

VSS_20

J1

VSS_21

J3

VSS_22

J10

VSS_23

J12

VSS_24

K2

VSS_25

K4

VSS_26

K9

VSS_27

K11

VSS_28

N2

VSS_29

H9HCNNNBUUMLHR-NLM_FBGA200

@

12

CD39

CD40

1U_0201_10V6M

DDR_C_CLK <8> DDR_C_CLK# <8>

DDR_C_CKE0 <8>

DDR_C_CKE1 <8>

DDR_C_CS#0 <8>

DDR_C_CS#1 <8>

DDR_DRAMRST#_R <7,23>

DDR_C_D0_0 <8> DDR_C_D0_2 <8> DDR_C_D0_1 <8> DDR_C_D0_4 <8> DDR_C_D0_3 <8> DDR_C_D0_7 <8> DDR_C_D0_6 <8> DDR_C_D0_5 <8> DDR_C_D1_6 <8> DDR_C_D1_3 <8> DDR_C_D1_7 <8> DDR_C_D1_2 <8> DDR_C_D1_0 <8> DDR_C_D1_5 <8> DDR_C_D1_1 <8> DDR_C_D1_4 <8>

DDR_C_DQS0 <8> DDR_C_DQS#0 <8>

DDR_C_DQS1 <8> DDR_C_DQS#1 <8>

VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58

12

CD41

1U_0201_10V6M

+1.1V_MEM

RD37

0_0201_5%@

1 2

DDR_D_ODTA

12

RD38

@

0_0201_5%

ODT PD reserved -- CRB P.86

+1.1V_MEM

RD39

0_0201_5%@

1 2

DDR_D_ODTB

12

RD40

@

0_0201_5%

ODT PD reserved -- CRB P.86

N4 N9 N11 P1 P3 P10 P12 T1 T3 T5 T8 T10 T12 V1 V5 V8 V12 W2 W4 W9 W11 Y1 Y5 Y8 Y12 AB3 AB5 AB8 AB10

12

CD42

1U_0201_10V6M

95mA

422mA

DDR_D_D3_0<8> DDR_D_D3_2<8> DDR_D_D3_4<8> DDR_D_D3_1<8> DDR_D_D3_3<8> DDR_D_D3_5<8> DDR_D_D3_6<8> DDR_D_D3_7<8> DDR_D_D2_2<8> DDR_D_D2_4<8> DDR_D_D2_1<8> DDR_D_D2_0<8> DDR_D_D2_5<8> DDR_D_D2_3<8> DDR_D_D2_7<8> DDR_D_D2_6<8>

DDR_D_DQS3<8> DDR_D_DQS#3<8>

DDR_D_DQS2<8> DDR_D_DQS#2<8>

+1.8V_MEM

+1.1V_MEM

RD23 240_0201_1%

1 2

RD24 240_0201_1%

1 2

DDR_D_CA0<8> DDR_D_CA1<8> DDR_D_CA2<8> DDR_D_CA3<8> DDR_D_CA4<8> DDR_D_CA5<8>

DDR_D_D3_0 DDR_D_D3_2 DDR_D_D3_4 DDR_D_D3_1 DDR_D_D3_3 DDR_D_D3_5 DDR_D_D3_6 DDR_D_D3_7 DDR_D_D2_2 DDR_D_D2_4 DDR_D_D2_1 DDR_D_D2_0 DDR_D_D2_5 DDR_D_D2_3 DDR_D_D2_7 DDR_D_D2_6

DDR_D_DQS3 DDR_D_DQS#3

DDR_D_DQS2 DDR_D_DQS#2

UD4C

F1

VDD1_1

F12

VDD1_2

G4

VDD1_3

G9

VDD1_4

T4

VDD1_5

T9

VDD1_6

U1

VDD1_7

U12

VDD1_8

A4

VDD2_1

A9

VDD2_2

F5

VDD2_3

F8

VDD2_4

H1

VDD2_5

H5

VDD2_6

H8

VDD2_7

H12

VDD2_8

K1

VDD2_9

K3

VDD2_10

K10

VDD2_11

K12

VDD2_12

N1

VDD2_13

N3

VDD2_14

N10

VDD2_15

N12

VDD2_16

R1

VDD2_17

R5

VDD2_18

R8

VDD2_19

R12

VDD2_20

U5

VDD2_21

U8

VDD2_22

AB4

VDD2_23

AB9

VDD2_24

H9HCNNNBUUMLHR-NLM_FBGA200

@

12

CD13

CD14

1U_0201_10V6M

DDR_D_CA0 DDR_D_CKE0 DDR_D_CA1 DDR_D_CA2 DDR_D_CA3 DDR_D_CA4 DDR_D_CA5

DDR_D_CA0 DDR_D_CA1 DDR_D_CA2 DDR_D_CA3 DDR_D_CA4 DDR_D_CA5

DDR_D_ODTA

DDR_D_ODTB

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8

VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20

12

A5

A8

H2

J2

H9 H10 H11 J11

R2

P2

R9 R10 R11 P11

G2

T2

A1

A2 A11 A12

B1 B12

AA1

AA12

AB1

AB2 AB11 AB12

B2 C2 E2

F2

F4 E4 C4 B4

B11 C11 E11 F11

F9 E9 C9 B9

D3 E3

D10 E10

B3 B5 B8 B10 D1 D5 D8 D12 F3 F10 U3 U10 W1 W5 W8 W12 AA3 AA5 AA8 AA10

G11

NC_1

K5

NC_2

K8

NC_3

N5

NC_4

N8

NC_5

12

CD15

CD16

1U_0201_10V6M

DDRDDDRC

UD4A

ZQ0

ZQ1

CA0a CA1a CA2a CA3a CA4a CA5a

CA0b CA1b CA2b CA3b CA4b CA5b

ODTa ODTb

DNU_1 DNU_2 DNU_3 DNU_4 DNU_5 DNU_6 DNU_7 DNU_8 DNU_9 DNU_10 DNU_11 DNU_12

DQ0a DQ1a DQ2a DQ3a DQ4a DQ5a DQ6a DQ7a DQ8a DQ9a DQ10a DQ11a DQ12a DQ13a DQ14a DQ15a

DQS0_ta DQS0_ca

DQS1_ta DQS1_ca

H9HCNNNBUUMLHR-NLM_FBGA200

@

+VDDQ_MEM

323mA

+1.1V_MEM+1.8V_MEM

12

CD17

CD18

1U_0201_10V6M

CK_ta

CK_ca

CK_tb

CK_cb

CKE0a

CKE1a

CKE0b

CKE1b

CS0a

CS1a

CS0b

CS1b

DMI0a DMI1a

DMI0b DMI1b

RESET

DQ0b DQ1b DQ2b DQ3b DQ4b DQ5b DQ6b DQ7b DQ8b

DQ9b DQ10b DQ11b DQ12b DQ13b DQ14b DQ15b

DQS0_tb

DQS0_cb

DQS1_tb

DQS1_cb

UD4B

A3

VSS_1

A10

VSS_2

C1

VSS_3

C5

VSS_4

C8

VSS_5

C12

VSS_6

D2

VSS_7

D4

VSS_8

D9

VSS_9

D11

VSS_10

E1

VSS_11

E5

VSS_12

E8

VSS_13

E12

VSS_14

G1

VSS_15

G3

VSS_16

G5

VSS_17

G8

VSS_18

G10

VSS_19

G12

VSS_20

J1

VSS_21

J3

VSS_22

J10

VSS_23

J12

VSS_24

K2

VSS_25

K4

VSS_26

K9

VSS_27

K11

VSS_28

N2

VSS_29

H9HCNNNBUUMLHR-NLM_FBGA200

@

UD4UD3

12

CD19

CD20

1U_0201_10V6M

DDR_D_CLK

J8 J9

P8 P9

J4

J5

P4

P5

H4

H3

R4

R3

C3 C10

Y3 Y10

T11

AA2 Y2 V2 U2 U4 V4 Y4 AA4 AA11 Y11 V11 U11 U9 V9 Y9 AA9

W3 V3

W10 V10

12

DDR_D_CLK#

DDR_D_CLK DDR_D_CLK#

DDR_D_CKE1

DDR_D_CKE0

DDR_D_CKE1

DDR_D_CS#0

DDR_D_CS#1

DDR_D_CS#0

DDR_D_CS#1

VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58

CD21

1U_0201_10V6M

DDR_D_D1_1 DDR_D_D1_6 DDR_D_D1_7 DDR_D_D1_4 DDR_D_D1_0 DDR_D_D1_5 DDR_D_D1_3 DDR_D_D1_2 DDR_D_D0_4 DDR_D_D0_2 DDR_D_D0_5 DDR_D_D0_6 DDR_D_D0_3 DDR_D_D0_7 DDR_D_D0_0 DDR_D_D0_1

DDR_D_DQS1 DDR_D_DQS#1

DDR_D_DQS0 DDR_D_DQS#0

12

CD22

1U_0201_10V6M

N4 N9 N11 P1 P3 P10 P12 T1 T3 T5 T8 T10 T12 V1 V5 V8 V12 W2 W4 W9 W11 Y1 Y5 Y8 Y12 AB3 AB5 AB8 AB10

+VDDQ_MEM

DDR_D_CLK <8> DDR_D_CLK# <8>

DDR_D_CKE0 <8>

DDR_D_CKE1 <8>

DDR_D_CS#0 <8>

DDR_D_CS#1 <8>

DDR_D_D1_1 <8> DDR_D_D1_6 <8> DDR_D_D1_7 <8> DDR_D_D1_4 <8> DDR_D_D1_0 <8> DDR_D_D1_5 <8> DDR_D_D1_3 <8> DDR_D_D1_2 <8> DDR_D_D0_4 <8> DDR_D_D0_2 <8> DDR_D_D0_5 <8> DDR_D_D0_6 <8> DDR_D_D0_3 <8> DDR_D_D0_7 <8> DDR_D_D0_0 <8> DDR_D_D0_1 <8>

DDR_D_DQS1 <8> DDR_D_DQS#1 <8>

DDR_D_DQS0 <8> DDR_D_DQS#0 <8>

12

CD23

1U_0201_10V6M

12

CD24

CD26

CD25

1U_0201_10V6M

+1.1V_MEM+1.8V_MEM

1

CD11

CD10

10U_0402_6.3V6M

2

A A

5

CD316

RF@

100P_0201_50V8J

10U_0402_6.3V6M

2

1

CD6

CD5

10U_0402_6.3V6M

2

CD317

RF@

100P_0201_50V8J

10U_0402_6.3V6M

2

4

+VDDQ_MEM

1

CD86

CD85

10U_0402_6.3V6M

2

CD318

RF@

100P_0201_50V8J

10U_0402_6.3V6M

2

3

+1.8V_MEM

1

CD9

CD8

10U_0402_6.3V6M

2

+1.1V_MEM

1

CD4

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT O F COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT O F COMPAL ELECTRONICS, INC.

CD3

CD319

10U_0402_6.3V6M

RF@

100P_0201_50V8J

2

CD320

RF@

100P_0201_50V8J

10U_0402_6.3V6M

2

Compal Secret Data

2020/10/01 2018/10/01

2

Deciphered Date

+VDDQ_MEM

1

CD84

CD83

10U_0402_6.3V6M

2

1

CD321

RF@

100P_0201_50V8J

2

Compal Electronics, Inc.

Title

P024 - LPDDR4/x Channel C/D

Size

Document N umber Rev

LA-H811P

Date: Sheet o f

1

0.1 (X00)

24 100Tuesday, December 24, 2019

A

B

C

D

E

DVT1_61

+3VALW

RD41 100K_0402_5%@

1 2

RD42 100K_0402_5%

1 2

1 1

DVT1_60

2 2

RD43 RD45 RD44 RD46 LPDDR4(1.1V) : @ @

RD43 0_0402_5%LPDDR4X@

1 2

0.6V_VDDQ_EN

RD44 0_0201_5%LPDDR4@

1 2

0.6V_VDDQ_PG <87>

1.1V_MEM_PG <25,58,86>

+0.6V_VDDQP:LPDDR 4X +1.1V_MEM:LPDDR4

+0.6V_VDDQ

+1.1V_MEM

0.6V_VDDQ_EN

LPDDR4X@

RD45

0_1206_5%

1 2

LPDDR4@

RD46

0_1206_5%

1 2

RD400

@

1 2

0_0402_5%

+VDDQ_MEM

12

0.6V_VDDQ_EN_P<87,95>

DVT1_62

SUS_ON_P<78>

RD48

200K_04 02_1%

2

G

+0.6V_VDDQ

B+

12

2N7002KDW_SOT363-6

61

D

QE26A

S

12

RD47

0.1_0402_1%

2N7002KDW_SOT363-6

34

D

5

G

QE26B

S

12

RD300

CD309

1M_0201_5%

@

0.1U_0402_25V6

LPDDR4X(1.1v&0.6V): @ @

3 3

4 4

Security Classification

2020/10/ 01 2018/10/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2020/10/ 01 2018/10/ 01

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

P025 - LPDDR4&4X BOM OPTION

LA-H811P

25 100Tuesday, December 24, 2019

E

0.1 (X00)

5

D D

C C

4

3

2

1

B B

A A

Security Classification

2020/10/ 01 2018/10/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2020/10/ 01 2018/10/ 01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

P026 - Reserve

LA-H811P

0.1 (X00)

26 100Tuesday, December 24, 2019

1

0.1 (X00)

5

D D

C C

4

3

2

1

B B

A A

Security Classification

2020/10/ 01 2018/10/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2020/10/ 01 2018/10/ 01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

P027 - Reserve

LA-H811P

0.1 (X00)

27 100Tuesday, December 24, 2019

1

0.1 (X00)

5

D D

C C

4

3

2

1

B B

A A

Security Classification

2020/10/ 01 2018/10/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2020/10/ 01 2018/10/ 01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

P028 - Reserve

LA-H811P

0.1 (X00)

28 100Tuesday, December 24, 2019

1

0.1 (X00)

5

D D

C C

4

3

2

1

B B

A A

Security Classification

2020/10/ 01 2018/10/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2020/10/ 01 2018/10/ 01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

P029 - Reserve

LA-H811P

0.1 (X00)

29 100Tuesday, December 24, 2019

1

0.1 (X00)

5

D D

C C

4

3

2

1

B B

A A

Security Classification

2020/10/ 01 2018/10/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2020/10/ 01 2018/10/ 01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Re v

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

P030 - Reserve

LA-H811P

0.1 (X00)

30 100Tuesday, December 24, 2019

1

0.1 (X00)

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