DELL LA5091P Schematics
A
hexainf@hotmail.com
B
C
D
E
MODEL AME :
PCB O :
BOM P/ :
1 1
LA-5091P (DA60000BR10)
43169831L02
KIU20
Compal Confidential
2 2
Intel Diamondville Processor with Calistoga(945GSE) + DDRII + ICH7M
Bear Schematics Document
2009-3-31
REV: 1.0
3 3
@ : Nopop Component
1@ : For N280 only
2@ : For N270 only
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/11/10 2009/11/10
2008/11/10 2009/11/10
2008/11/10 2009/11/10
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
LA-5091P
LA-5091P
LA-5091P
1 39Wednesday, April 22, 2009
1 39Wednesday, April 22, 2009
1 39Wednesday, April 22, 2009
E
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Compal Confidential
B
C
D
E
Model ame : KIU20
File ame : LA-5091P
1 1
CRT Conn
page 14
LCD Conn.
page 13
2 2
RGB
LVDS
Diamondville SC
FCBGA8
437Pins
22x22mm
H_A#(3..31) H_D#(0..63)
FSB
400/533MHz
page 4,5
Calistoga GSE
FCBGA998
27x27mm
page 6,7,8,9,10
DMI
X2 mode
Memory BUS(DDRII)
1.8V DDRII 400/533
USB
PCI-Express
MII Card
WLA
page 19
3 3
10/100 Ethernet
RTL8103EL
page 24
RJ45
page 24
Power O/OFF
DC I
BATT CO/OTP
page 26 page 30
page 30
page 36
CHARGER
4 4
LED CO
page 31
page 22
A
DC/DC Interface
3VALW/5VALW
page 32
1.5VS/0.9VS/
2.5VS
page 34
1.8V/VCCP
page 33
CPU CORE
page 35
Int.KBD
page 25
B
ICH7M
BGA652
31x31mm
page 15,16,17,18
LPC BUS
EE KBC
KB926
Touch Pad
page 25
page 26
SATA
HDA
Audio Codec
ALC272-VB-GR
SPI
page 20
SPI ROM
page 26
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/11/10 2009/11/10
2008/11/10 2009/11/10
2008/11/10 2009/11/10
Thermal Sensor
EMC1402
Clock Generator
CK505
DDRII-SO-DIMM
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
page 4
page 12
2.5" HDD
page 22
AMP & Speaker
page 21
HeadPhone &
MIC Jack
page 21
D
page 11
Port 4
Port 6
Port 0
WWA
page 19
WLA
page 19
USB Port X1
PWR
page 27
USB daughter board
Port 3
Port 7
USB Port X1
page 27
USB Port X1
page 27
Through BT cable
Port 5
BlueTooth
page 19
Through LVDS cable
Port 1
Port 2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
CMOS CAM
page 13
Card Reader
RTS5159
SD/MMC/MS
page 23
Block Diagrams
Block Diagrams
Block Diagrams
LA-5091P
LA-5091P
LA-5091P
E
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2 39Wednesday, April 22, 2009
2 39Wednesday, April 22, 2009
2 39Wednesday, April 22, 2009
1.0
1.0
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A
hexainf@hotmail.com
ZZZ
ZZZ
PCB
PCB
DA60000BR10
1 1
DA60000BR10
B
C
D
E
Voltage Rails
S5
Power Plane
VIN
B+
+CPU_CORE
+0.9VS
+VCCP
+1.5VS
+1.8V
+2.5VS
+3VALW
+3VS
+5VALW
2 2
+5VS
+VS
+RTCBATT RTC power
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
Description
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
0.9V switched power rail for DDR terminator
VCCP switched power rail
1.5V switched power rail
1.8V power rail for DDR
2.5V switched power rail
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
VS always on power rail
SIGNAL
SLP_S3#
SLP_S4#
HIGH HIGH HIGH
HIGH
LOW
LOW LOW
LOWLOW
SLP_S5#
HIGHHIGHHIGH
HIGH
HIGH
LOW
+VALW
ON
ON
ON
ON
ON
S3S1
N/A N/A N/A
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
N/AN/AN/A
OFF
OFF
OFF
OFF
OFFOFF
OFFOFF
ON
OFF
OFF
OFF
ON ON*
OFF
OFF
ON ON*
OFF
OFF
ON ON*
ON
ON
+V +VS Clock
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
ONON
LOW
OFF
OFF
OFF
External PCI Devices
No PCI Device
EC SM Bus1 address
Device
Smart Battery
EEPROM(24C16/02)
IDSEL #DEVICE REQ/GNT #
EC SM Bus2 address
Address
1010 000X b
Device
EMC1402
PIRQ
Address
1001 100X b0001 011X b
3 3
BOARD ID Table(Page 25)
ID
0
1
2
*
3
4 4
BRD ID
R01 (SSI)
R02 (ST)
R10 (X build)
R10A (MP)
A
Ra
NC
100K
100K
100K
Rb Vab
0
8.2K
18K
NC
0.25V
0.50V
3.3V
0V
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ICH7M SM Bus address
Device
Clock Generator
(SLG8SP556VTR)
DDR DIMMA
2008/11/10 2009/11/10
2008/11/10 2009/11/10
2008/11/10 2009/11/10
C
Address
1101 001Xb
1010 000Xb
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
Notes List
Notes List
Notes List
LA-5091P
LA-5091P
LA-5091P
3 39Wednesday, April 22, 2009
3 39Wednesday, April 22, 2009
3 39Wednesday, April 22, 2009
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5
H_A#[3..16]<6>
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
D D
H_ADSTB#0<6>
H_REQ#[0..4]<6>
H_A#[17..31]<6>
H_ADSTB#1<6>
C C
T7 PADT7 PAD
H_A20M#<16>
H_FERR#<16>
H_IGNNE#<16>
H_STPCLK#<16>
H_INTR<16>
H_NMI<16>
H_SMI#<16>
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_AP0
T5 PADT5 PAD
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_AP1
H_A20M#
H_FERR#
H_IGNNE# CLK_CPU_BCLK#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
CPU N270 P/N: SA00002O31L
U5A
U5A
P21
A[3]#
H20
A[4]#
N20
A[5]#
R20
A[6]#
J19
A[7]#
N19
A[8]#
G20
A[9]#
M19
A[10]#
H21
A[11]#
L20
A[12]#
M20
A[13]#
K19
A[14]#
J20
A[15]#
L21
A[16]#
K20
ADSTB[0]#
D17
AP0
N21
REQ[0]#
J21
REQ[1]#
G19
REQ[2]#
P20
REQ[3]#
R19
REQ[4]#
C19
A[17]#
F19
A[18]#
E21
A[19]#
A16
A[20]#
D19
A[21]#
C14
C18
C20
E20
D20
B18
C15
B16
B17
C16
A17
B14
B15
A14
B19
M18
U18
T16
J4
R16
T15
R15
U17
D6
G6
H6
K4
K5
M15
L16
ADDR GROUP 1
ADDR GROUP 1
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
AP1
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
NC1
NC2
NC3
NC4
NC5
NC6
NC7
AU80586GE025D_FCBGA437
AU80586GE025D_FCBGA437
ADDR
GROUP
0
ADDR
GROUP
0
DEFER#
CONTROL
CONTROL
RESET#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PROCHOT#
XDP/ITP SIGNALS
XDP/ITP SIGNALS
THRMDA
THRMDC
THERM
THERM
THERMTRIP#
H CLK
H CLK
NC
NC
ADS#
BNR#
BPRI#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
BR1#
BCLK[0]
BCLK[1]
RSVD3
RSVD2
RSVD1
V19
Y19
U21
T21
T19
Y18
T20
F16
V16
W20
D15
W18
Y17
U20
W19
AA17
V20
K17
J18
H15
J15
K18
J16
M17
N16
TDI
M16
L17
K16
V15
G17
E4
E5
H17
V11
V12
C21
C1
A3
.
.
CPU N280 P/N: SA000031F1L
H_A#32
H_A#33
H_A#34
H_A#35
H_A20M#
H_IGNNE#
H_DPRSTP#
H_DPSLP#
H_PWRGOOD
H_SMI#
H_NMI
H_INTR
1 2
R103 124_0402_1%~D@ R103 124_0402_1%~D@
CPU_ITP<12>
CPU_ITP#<12>
1 2
R105 22.6_0402_1%@ R105 22.6_0402_1%@
+VCCP
This shall place near CPU
R200 56_0402_5%
R200 56_0402_5%
1 2
R198 56_0402_5%
R198 56_0402_5%
1 2
R206 56_0402_5%R206 56_0402_5%
1 2
R199 56_0402_5%
R199 56_0402_5%
1 2
R213 56_0402_5%
R213 56_0402_5%
1 2
R218 56_0402_5%
R218 56_0402_5%
1 2
+VCCP
BR1#
BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#
H_RESET_R#H_RESET#
ITP_TCK
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
+VCCP
R34 1K_0402_5%R34 1K_0402_5%
1 2
R30 1K_0402_5%R30 1K_0402_5%
1 2
R31 1K_0402_5%R31 1K_0402_5%
1 2
R29 1K_0402_5%R29 1K_0402_5%
B B
A A
+VCCP
1 2
R28 1K_0402_5%R28 1K_0402_5%
1 2
R32 1K_0402_5%R32 1K_0402_5%
1 2
R113 1K_0402_5%@ R113 1K_0402_5%@
1 2
R124 1K_0402_5%@ R124 1K_0402_5%@
1 2
R135 1K_0402_5%@ R135 1K_0402_5%@
1 2
R286 1K_0402_5%@ R286 1K_0402_5%@
1 2
R287 1K_0402_5%@ R287 1K_0402_5%@
1 2
R288 1K_0402_5%@ R288 1K_0402_5%@
1 2
ITP_TDO
5
4
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_IERR#
H_INIT#_R
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
H_HIT#
H_HITM#
BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
BR1#
H_PROCHOT#_R
H_THERMDA
H_THERMDC
H_THERMTRIP#
CLK_CPU_BCLK
JITP3
JITP3
28
VTT1
27
VTT0
26
VTAP
25
DBR#
24
DBA#
23
BPM0#
22
GND5
21
BPM1#
20
GND4
19
BPM2#
18
GND3
17
BPM3#
16
GND2
15
BPM4#
14
GND1
13
BPM5#
12
RESET#
11
FBO
10
GND0
9
BCLKP
8
BCLKN
7
TDO
6
NC2
5
TCK
4
NC1
3
TRST#
2
TMS
1
TDI
4
H_ADS# <6>
H_BNR# <6>
H_BPRI# <6>
H_DEFER# <6>
H_DRDY# <6>
H_DBSY# <6>
H_BR0# <6>
R33 1K_0402_5%R33 1K_0402_5%
1 2
H_LOCK# <6>
H_RESET# <6>
H_TRDY# <6>
H_HIT# <6>
H_HITM# <6>
1 2
R202 22_0402_5%R202 22_0402_5%
Close to CPU
H_THERMTRIP# <6,16>
CLK_CPU_BCLK <12>
CLK_CPU_BCLK# <12>
ITP_TMS
ITP_TDI
PREQ#
ITP_TDO
ITP_TCK
ITP_TRST#
29
GND6
GND7
MOLEX_52435-2891_28P~D@
MOLEX_52435-2891_28P~D@
30
+VCCP +VCCP
12
R201
R201
56_0402_5%
56_0402_5%
Close to CPU
H_RS#[0..2] <6>
H_PROCHOT# <35>
+CPU_GTLREF
C62
C62
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Close to CPU pin
within 500mils.
Zo=55ohm
3
H_D#[0..15]<6>
12
R27
R27
330_0402_5%
330_0402_5%
H_INIT# <16>
H_DSTBN#0<6>
H_DSTBP#0<6>
H_DINV#0<6>
T10 PADT10 PAD
H_D#[16..31]<6>
H_DSTBN#1<6>
H_DSTBP#1<6>
T13
T13
PAD
PAD
CPU_BSEL0<12>
CPU_BSEL1<12>
CPU_BSEL2<12>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Close to CPU pin
within 500mils.
Zo=55ohm
Deciphered Date
Deciphered Date
Deciphered Date
+VCCP
1
2
12
R47
R47
1K_0402_1%
1K_0402_1%
12
R48
R48
2K_0402_1%
2K_0402_1%
+CPU_GTLREF
+CPU_EXTBGREF
+CPU_EXTBGREF
1U_0402_6.3V4Z~D
1U_0402_6.3V4Z~D
C342
C342
R240 1K_0402_5%@R240 1K_0402_5%@
R239 1K_0402_5%@R239 1K_0402_5%@
+VCCP
12
12
1
2
1 2
1 2
R234
R234
1K_0402_1%
1K_0402_1%
R238
R238
2K_0402_1%
2K_0402_1%
Close to CPU pin
within 500mils.
Zo=55ohm
+VCCP
12
@
@
R158
R158
1K_0402_1%
1K_0402_1%
H_DPWR#
12
@
@
R136
R136
2K_0402_1%
2K_0402_1%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/11/10 2009/11/10
2008/11/10 2009/11/10
2008/11/10 2009/11/10
Compal Secret Data
Compal Secret Data
Compal Secret Data
2
U5B
Y11
W10
Y12
AA14
AA11
W12
AA16
Y10
Y9
Y13
W15
AA13
Y16
W13
AA9
W9
Y14
Y15
W16
V9
AA5
Y8
W3
U1
W7
W6
Y7
AA6
Y3
W2
V3
U2
T3
AA8
V2
W4
Y4
Y5
Y6
R4
A7
U5
V5
T17
R6
M6
N15
N6
P17
T6
J6
H5
G5
+VCCP
12
R51
R51
1K_0402_1%
1K_0402_1%
12
1
R49
R49
2K_0402_1%
2K_0402_1%
2
+3VS
1
C352
C352
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
H_THERMDA
H_THERMDC
2200P_0402_50V7K
2200P_0402_50V7K
2
U5B
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DP#0
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
DP#1
GTLREF
ACLKPH
DCLKPH
BINIT#
EDM
EXTBGREF
FORCEPR#
HFPLL
MCERR#
RSP#
BSEL[0]
BSEL[1]
BSEL[2]
AU80586GE025D_FCBGA437
AU80586GE025D_FCBGA437
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_DP#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1 H_DSTBN#3
H_DSTBP#1
H_DINV#1
H_DP#1
ACLKPH
DCLKPH
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
+CPU_CMREF
C65
C65
C351
C351
1 2
1
D[32]#
D[33]#
D[34]#
DATA GRP 0 DATA GRP 1
DATA GRP 0 DATA GRP 1
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
DATA GRP 2
DATA GRP 2
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
DP#2
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
DATA GRP 3
DATA GRP 3
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
DP#3
COMP[0]
COMP[1]
COMP[2]
COMP[3]
MISC
MISC
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
CORE_DET
CMREF[1]
Layout note:
COMP0,2 connect with Zo=27.4ohm +/-15%, make
trace length shorter than 0.5"
COMP1,3 connect with Zo=55ohm +/-15%, make
trace length shorter than0.5"
H_D#33
R2
H_D#34
P1
H_D#35
N1
H_D#36
M2
H_D#37
P2
H_D#38
J3
H_D#39
N3
H_D#40
G3
H_D#41
H2
H_D#42
N2
H_D#43
L2
H_D#44
M3
H_D#45
J2
H_D#46
H1
H_D#47
J1
H_DSTBN#2
K2
H_DSTBP#2
K3
H_DINV#2
L1
H_DP#2
M4
H_D#48
C2
H_D#49
G2
H_D#50
F1
H_D#51
D3
H_D#52
B4
H_D#53
E1
H_D#54
A5
H_D#55
C3
H_D#56
A6
H_D#57
F2
H_D#58
C6
H_D#59
B6
H_D#60
B3
H_D#61
C4
H_D#62
C7
H_D#63
D2
E2
H_DSTBP#3
F3
H_DINV#3
C5
H_DP#3
D4
COMP0
T1
COMP1
T2
COMP2
F20
COMP3
F21
H_DPRSTP#
R18
H_DPSLP#
R17
H_DPWR#
U4
H_PWRGOOD
V17
H_CPUSLP#
N18
A13
B7
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
H_D#32
R3
H_D#[32..47] <6>
H_DSTBN#2 <6>
H_DSTBP#2 <6>
H_DINV#2 <6>
T15PAD T15PAD
H_D#[48..63] <6>
H_DSTBN#3 <6>
H_DSTBP#3 <6>
H_DINV#3 <6>H_DINV#1<6>
T12PAD T12PAD
R57 27.4_0402_1%
R57 27.4_0402_1%
1 2
R58 54.9_0402_1%
R58 54.9_0402_1%
1 2
R208 27.4_0402_1%
R208 27.4_0402_1%
12
R209 54.9_0402_1%
R209 54.9_0402_1%
12
H_DPRSTP# <16,35>
H_DPSLP# <16>
H_DPWR# <6>
H_PWRGOOD <16>
H_CPUSLP# <6>
+CPU_CMREF
CPU THERMAL SENSOR
U17
U17
1
VDD
2
DP
3
DN
4
THERM#
EMC1402-1-ACZL-TR_MSOP8
EMC1402-1-ACZL-TR_MSOP8
Address:100_1100
SMCLK
SMDATA
ALERT#
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
EC_SMB_CK2
8
EC_SMB_DA2
7
6
5
GND
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
R304
R304
12
10K_0402_5%
10K_0402_5%
Diamondville(1/2)
Diamondville(1/2)
Diamondville(1/2)
LA-5091P
LA-5091P
LA-5091P
1
EC_SMB_CK2 <25>
EC_SMB_DA2 <25>
+3VS
of
of
of
4 39Wednesday, April 22, 2009
4 39Wednesday, April 22, 2009
4 39Wednesday, April 22, 2009
1.0
1.0
1.0
5
hexainf@hotmail.com
4
3
2
1
U5D
U5D
A2
VSS1
A4
VSS2
A8
VSS4
A15
D D
C C
B B
A A
VSS5
A18
VSS6
A19
VSS7
A20
VSS8
B1
VSS9
B2
VSS10
B5
VSS11
B8
VSS12
B13
VSS13
B20
VSS14
B21
VSS15
C8
VSS16
C17
VSS17
D1
VSS18
D5
VSS19
D8
VSS20
D14
VSS21
D18
VSS22
D21
VSS23
E3
VSS24
E6
VSS25
E7
VSS26
E8
VSS27
E15
VSS28
E16
VSS29
E19
VSS30
F4
VSS31
F5
VSS32
F6
VSS33
F7
VSS34
F17
VSS35
F18
VSS36
G1
VSS37
G4
VSS38
G7
VSS39
G9
VSS41
G13
VSS42
G21
VSS45
H3
VSS46
H4
VSS48
H7
VSS49
H9
VSS51
H13
VSS52
H16
VSS53
H18
VSS54
H19
VSS55
J5
VSS56
J7
VSS57
J9
VSS58
J13
VSS59
J17
VSS60
K1
VSS61
K6
VSS62
K7
VSS63
K9
VSS64
K13
VSS65
K15
VSS66
K21
VSS67
L3
VSS68
L4
VSS69
L5
VSS70
L6
VSS71
L7
VSS72
L9
VSS73
L13
VSS74
L15
VSS75
L18
VSS76
L19
VSS77
M1
VSS78
M5
VSS79
M7
VSS80
M9
VSS81
M13
VSS82
M21
VSS83
N4
VSS84
AU80586GE025D_FCBGA437
AU80586GE025D_FCBGA437
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
N5
N7
N9
N13
N17
P3
P4
P5
P6
P7
P9
P13
P15
P16
P18
P19
R1
R5
R7
R9
R13
R21
T4
T5
T7
T9
T10
T11
T12
T13
T18
U3
U6
U7
U15
U16
U19
V1
V4
V6
V7
V8
V13
V14
V18
V21
W1
W5
W8
W11
W14
W17
W21
Y1
Y2
Y20
Y21
AA2
AA3
AA4
AA7
AA10
AA12
AA15
AA18
AA19
AA20
+CPU_CORE
+CPU_CORE
+VCCP
C308
C308
1U_0402_6.3V6K
1U_0402_6.3V6K
C298
C298
10U_0805_10V4Z~D
10U_0805_10V4Z~D
V10
A9
B9
A10
A11
A12
B10
B11
B12
C10
C11
C12
D10
D11
D12
E10
E11
E12
F10
F11
F12
G10
G11
G12
H10
H11
H12
J10
J11
J12
K10
K11
K12
L10
L11
L12
M10
M11
M12
N10
N11
N12
P10
P11
P12
R10
R11
R12
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C309
C309
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
1
C299
C299
2
U5C
U5C
VTT1
VTT2
VTT3
VTT4
VTT5
C310
C310
1
2
1
2
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VCCPC64
VCCPC63
VCCPC62
VCCPC61
VCCA
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
1U_0402_6.3V6K
1U_0402_6.3V6K
C311
C311
10U_0805_10V4Z~D
10U_0805_10V4Z~D
C301
C301
VCCF
VCCQ1
VCCQ2
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCP25
VCCP26
VCCP27
VCCP28
VCCP29
VCCP30
VCCP31
VCCP32
VCCP33
VCCP34
VCCP35
VCCP36
VCCP37
VCCP38
VCCP39
VCCP40
VCCP41
VCCP42
VCCP43
VCCP44
VCCP45
AU80586GE025D_FCBGA437
AU80586GE025D_FCBGA437
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C300
C300
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
C9
D9
E9
F8
F9
G8
G14
H8
H14
J8
J14
K8
K14
L8
L14
M8
M14
N8
N14
P8
P14
R8
R14
T8
T14
U8
U9
U10
U11
U12
U13
U14
F14
F13
E14
E13
D7
F15
D16
E18
G15
G16
E17
G18
C13
D13
PLACE IN CAVITY
1
1
C312
C312
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C302
C302
2
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
VCCSENSE
VSSSENSE
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C313
C313
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
1
C46
C46
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C295
C295
1
2
CPU_VID0 <35>
CPU_VID1 <35>
CPU_VID2 <35>
CPU_VID3 <35>
CPU_VID4 <35>
CPU_VID5 <35>
CPU_VID6 <35>
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C314
C314
C320
C320
2
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0805_10V4Z~D
10U_0805_10V4Z~D
1
C304
C304
C303
C303
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
C307
C307
1
2
1
2
1
2
PLACE IN CORRIDOR AND CLOSE TO CPU
1U_0402_6.3V6K
1U_0402_6.3V6K
C337
C337
1
2
PLACE IN CAVITY
130mA
1
C321
C321
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C335
C335
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
+VCCP
1U_0402_6.3V6K
1U_0402_6.3V6K
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
C341
C341
1
2
+1.5VS
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C323
C323
C322
C322
2
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0805_10V4Z~D
10U_0805_10V4Z~D
1
C328
C328
C47
C47
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
1
C57
C57
+
+
2
C338
C338
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
+CPU_CORE
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C324
C324
2
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
1
1
C334
C334
2
2
12
R221
R221
100_0402_1%
100_0402_1%
12
R220
R220
100_0402_1%
100_0402_1%
1
C326
C326
2
1U_0402_6.3V6K
1U_0402_6.3V6K
VCCSENSE <35>
VSSSENSE <35>
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C327
C327
2
1U_0402_6.3V6K
1U_0402_6.3V6K
Length match within 25 mils
The trace space 7 mils,
Zo=27.4ohm
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C325
C325
1
C315
C315
2
2
+CPU_CORE
2 x 330uF(9mohm/2)
1
+
+
C51
C51
330U 2.5V Y
330U 2.5V Y
2
1
+
+
C331
C331
330U 2.5V Y
330U 2.5V Y
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/11/10 2009/11/10
2008/11/10 2009/11/10
2008/11/10 2009/11/10
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Diamondville(2/2)
Diamondville(2/2)
Diamondville(2/2)
LA-5091P
LA-5091P
LA-5091P
5 39Wednesday, April 22, 2009
5 39Wednesday, April 22, 2009
5 39Wednesday, April 22, 2009
1
1.0
1.0
1.0
of
of
of
5
4
3
2
1
H_D#[0..63]<4>
D D
C C
+VCCP
12
12
R6
R6
R175
R175
54.9_0402_1%
54.9_0402_1%
54.9_0402_1%
54.9_0402_1%
B B
12
R7
R7
R182
R182
24.9_0402_1%
24.9_0402_1%
Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.
+VCCP
12
R176
A A
R176
100_0402_1%
100_0402_1%
+H_VREF
12
1
R174
R174
2
200_0402_1%
200_0402_1%
5
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
+H_SWNG0
H_YRCOMP
H_YSCOMP
+H_SWNG1
12
24.9_0402_1%
24.9_0402_1%
C50 be placed <100mils
from GMCH pin
C243
C243
0.1U_0402_16V4Z
0.1U_0402_16V4Z
M5
M4
M3
M1
W2
W1
W4
W7
W5
AB4
AB8
W8
AA9
AA8
AB1
AB7
AA2
AB5
A10
C15
C4
F6
H9
H6
F7
E3
C2
C3
K9
F5
J7
K7
H8
E5
K8
J8
J2
J3
N1
K5
J5
H3
J4
N3
N8
N6
K3
N9
V8
V9
R6
T8
R2
N5
N2
R5
U7
R8
T4
T7
R3
T5
V6
V3
V2
V5
A6
J1
K1
H1
U1A
U1A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_VREF0
H_BNR#
H_BPRI#
H_BREQ0#
H_CPURST#
H_VREF1
HOST
HOST
H_DBSY#
H_DEFER#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DPWR#
H_DRDY#
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_HITM#
H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_SLPCPU#
H_TRDY#
Calistoga-GSE_FCBGA998
Calistoga-GSE_FCBGA998
+VCCP
12
R167
R167
12
R166
R166
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
HCLKN
HCLKP
H_HIT#
221_0402_1%~D
221_0402_1%~D
100_0402_1%
100_0402_1%
F8
D12
C13
A8
E13
E12
J12
B13
A13
G13
A12
D14
F14
J13
E17
H15
G15
G14
A15
B18
B15
E14
H13
C14
A17
E15
H17
D17
G17
F10
C12
H16
E2
B9
C7
G8
B10
E1
AA6
AA5
C10
C6
H5
J6
T9
U6
G7
E6
F3
M8
T1
AA3
F4
M7
T2
AB3
C8
B4
C5
G9
E9
G12
B8
F12
A5
B6
G10
E8
E10
+H_SWNG0
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADS#
H_ADSTB#0
H_ADSTB#1
+H_VREF
H_BNR#
H_BPRI#
H_BR0#
H_RESET#
+H_VREF
CLK_MCH_BCLK#
CLK_MCH_BCLK
H_DBSY#
H_DEFER#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DPWR#
H_DRDY#
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_HIT#
H_HITM#
H_LOCK#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP#
H_TRDY#
C240
C240
+VCCP
R180
R180
R178
R178
12
12
H_A#[3..31] <4>
H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# <4>
H_BR0# <4>
H_RESET# <4>
CLK_MCH_BCLK# <12>
CLK_MCH_BCLK <12>
H_DBSY# <4>
H_DEFER# <4>
H_DINV#0 <4>
H_DINV#1 <4>
H_DINV#2 <4>
H_DINV#3 <4>
H_DPWR# <4>
H_DRDY# <4>
H_DSTBN#[0..3] <4>
H_DSTBP#[0..3] <4>
H_HIT# <4>
H_HITM# <4>
H_LOCK# <4>
H_REQ#[0..4] <4>
H_RS#[0..2] <4>
H_CPUSLP# <4>
H_TRDY# <4>
+H_SWNG1
221_0402_1%~D
221_0402_1%~D
1
2
100_0402_1%
100_0402_1%
U1B
DMI_ITX_MRX_N0<17>
DMI_ITX_MRX_N1<17>
DMI_ITX_MRX_P0<17>
DMI_ITX_MRX_P1<17>
DMI_MTX_IRX_N0<17>
DMI_MTX_IRX_N1<17>
DMI_MTX_IRX_P0<17>
DMI_MTX_IRX_P1<17>
M_CLK_DDR0<11>
M_CLK_DDR1<11>
M_CLK_DDR#0<11>
M_CLK_DDR#1<11>
DDR_CKE0<11>
DDR_CKE1<11>
DDR_CS0#<11>
DDR_CS1#<11>
+1.8V
R232 80.6_0402_1%
R232 80.6_0402_1%
R228 80.6_0402_1%
+DIMM_VREF
C251
C251
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
R228 80.6_0402_1%
C53
C53
R41
R41
1K_0402_1%
1K_0402_1%
R43
R43
1K_0402_1%
1K_0402_1%
Issued Date
Issued Date
Issued Date
3
M_ODT0<11>
M_ODT1<11>
1 2
1 2
10uA
1
Layout Note:
+DIMM_VREF trace
2
width and spacing
is 20/20.
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.8V
12
+DIMM_VREF
12
Share +DIMM_VREF for
1.DDRII VREF
2.GMCH SM_VREF_0
SM_VREF_1
2008/11/10 2009/11/10
2008/11/10 2009/11/10
2008/11/10 2009/11/10
DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR#0
M_CLK_DDR#1
DDR_CKE0
DDR_CKE1
DDR_CS0#
DDR_CS1#
M_ODT0
M_ODT1
SMRCOMPN
SMRCOMPP
Compal Secret Data
Compal Secret Data
Compal Secret Data
U1B
Y29
DMI_RXN_0
Y32
DMI_RXN_1
Y28
DMI_RXP_0
Y31
DMI_RXP_1
V28
DMI_TXN_0
V31
DMI_TXN_1
V29
DMI_TXP_0
V32
DMI_TXP_1
AF33
SM_CK_0
AG1
SM_CK_1
AJ1
SM_CK_2
AM30
SM_CK_3
AG33
SM_CK#_0
AF1
SM_CK#_1
AK1
SM_CK#_2
AN30
SM_CK#_3
AN21
SM_CKE_0
AN22
SM_CKE_1
AF26
SM_CKE_2
AF25
SM_CKE_3
AG14
SM_CS#_0
AF12
SM_CS#_1
AK14
SM_CS#_2
AH12
SM_CS#_3
AJ21
SM_OCDCOMP_0
AF11
SM_OCDCOMP_1
AE12
SM_ODT_0
AF14
SM_ODT_1
AJ14
SM_ODT_2
AJ12
SM_ODT_3
AN12
SM_RCOMPN
AN14
SM_RCOMPP
AA33
SM_VREF_0
AE1
SM_VREF_1
Deciphered Date
Deciphered Date
Deciphered Date
CFG_0
CFG_1
CFG_2
CFG_3
CFG_5
CFG_6
DMI
DMI
RESERVED1
RESERVED2
RESERVED7
RESERVED8
RESERVED9
CFG/RSVD
CFG/RSVD
DDR2 MUXING
DDR2 MUXING
PM_ICHSYNC#
PM_BMBUSY#
PM_EXTTS#_0
PM
PM
PM_EXTTS#_1
THRMTRIP#
PWROK
RSTIN#
D_REFCLKN
D_REFCLKP
CLK
CLK
D_REFSSCLKN
D_REFSSCLKP
CLKREQ#
Calistoga-GSE_FCBGA998
Calistoga-GSE_FCBGA998
2
MCH_CLKSEL0
C18
E18
G20
G18
J20
J18
K32
K31
C17
F18
A3
E31
G21
F26
H26
J15
AB29
W27
A27
A26
J33
H33
J22
MCH_CLKSEL1
MCH_CLKSEL2
CFG5
R181 2.2K_0402_5%R181 2.2K_0402_5%
PM_EXTTS#1
H_THERMTRIP#
ICH_POK_EC
PLTRST_R#
1 2
R203 0_0402_5%R203 0_0402_5%
1 2
R211 100_0402_5%
R211 100_0402_5%
MCH_CLKSEL0 <12>
MCH_CLKSEL1 <12>
MCH_CLKSEL2 <12>
MCH_ICH_SYNC# <15>
PM_BMBUSY# <17>
12
CLK_MCH_DREFCLK# <12>
CLK_MCH_DREFCLK <12>
MCH_SSCDREFCLK# <12>
MCH_SSCDREFCLK <12>
MCH_CLKREQ# <12>
PM_EXTTS#0 <11>
PM_DPRSLPVR <17,35>
H_THERMTRIP# <4,16>
ICH_POK_EC <17,25>
PLTRST# <15,17,19,24,25>
Strap Pin Table
CFG5
PM_EXTTS#0
PM_EXTTS#1
Low = DMI x 2
High = DMI x 4
1 2
R187 10K_0402_5%R187 10K_0402_5%
1 2
R188 10K_0402_5%@R188 10K_0402_5%@
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Calistoga(1/5)-GTL/DMI/DDR
Calistoga(1/5)-GTL/DMI/DDR
Calistoga(1/5)-GTL/DMI/DDR
*
+3VS
LA-5091P
LA-5091P
LA-5091P
1
1.0
1.0
1.0
of
of
of
6 39Wednesday, April 22, 2009
6 39Wednesday, April 22, 2009
6 39Wednesday, April 22, 2009
5
hexainf@hotmail.com
D D
C C
B B
DDR_A_BS0<11>
DDR_A_BS1<11>
DDR_A_BS2<11>
DDR_A_DM[0..7]<11>
DDR_A_DQS[0..7]<11>
DDR_A_DQS#[0..7]<11>
DDR_A_MA[0..13]<11>
DDR_A_CAS#<11>
DDR_A_RAS#<11>
DDR_A_WE#<11>
PADT9PAD
T9
T8 PADT8 PAD
4
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_CAS#
DDR_A_RAS#
SA_RCVENIN#
SA_RCVENOUT#
DDR_A_WE#
AK12
AH11
AG17
AB30
AL31
AF30
AK26
AC28
AJ30
AK33
AL25
AC29
AK30
AJ33
AM25
AJ15
AM17
AM15
AH15
AK15
AN15
AJ18
AF19
AN17
AL17
AG16
AL18
AG18
AL14
AJ17
AK18
AN28
AM28
AH17
AH21
AJ20
AE27
AN20
AL21
AK21
AK22
AL22
AH22
AG22
AF21
AM21
AE21
AL20
AE22
AE26
AE20
AG7
AK5
AH3
AN9
AH8
AM2
AE3
AN8
AM3
AE2
AL9
AJ8
U1C
U1C
SA_BS_0
SA_BS_1
SA_BS_2
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
SB_BS_0
SB_BS_1
SB_BS_2
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
DDR2 SYSTEM MEMORY
DDR2 SYSTEM MEMORY
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SB_CAS#
SB_RAS#
SB_WE#
Calistoga-GSE_FCBGA998
Calistoga-GSE_FCBGA998
AC31
AB28
AE33
AF32
AC33
AB32
AB31
AE31
AH31
AK31
AL28
AK27
AH30
AL32
AJ28
AJ27
AH32
AF31
AH27
AF28
AJ32
AG31
AG28
AG27
AN27
AM26
AJ26
AJ25
AL27
AN26
AH25
AG26
AM12
AL11
AH9
AK9
AM11
AK11
AM8
AK8
AG9
AF9
AF8
AK6
AF7
AG11
AJ6
AH6
AN6
AM6
AK3
AL2
AM5
AL5
AJ3
AJ2
AG2
AF3
AE7
AF6
AH5
AG3
AG5
AF5
AG19
AG21
AG20
3
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_D[0..63] <11>
2
1
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/11/10 2009/11/10
2008/11/10 2009/11/10
2008/11/10 2009/11/10
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Calistoga(2/5)-DDR2
Calistoga(2/5)-DDR2
Calistoga(2/5)-DDR2
LA-5091P
LA-5091P
LA-5091P
7 39Wednesday, April 22, 2009
7 39Wednesday, April 22, 2009
7 39Wednesday, April 22, 2009
1
1.0
1.0
1.0
of
of
of
5
D D
R10
R10
150_0402_1%
150_0402_1%
R8
R8
150_0402_1%
150_0402_1%
R9
R9
150_0402_1%
150_0402_1%
C C
+3VS
1 2
R192 10K_0402_5%R192 10K_0402_5%
1 2
R191 10K_0402_5%R191 10K_0402_5%
GMCH_CRT_R
12
GMCH_CRT_G
12
GMCH_CRT_B
12
Close to U1.H25
R183 255_0402_1%
R183 255_0402_1%
LCTLA_CLK
LCTLB_DATA
12
GMCH_CRT_VSYNC<14>
GMCH_CRT_HSYNC<14>
R171 100K_0402_5%R171 100K_0402_5%
GMCH_ENBKL<25>
12
R184 1.5K_0402_1%
R184 1.5K_0402_1%
4
U1F
U1F
H27
SDVO_CTRLDATA
J27
SDVO_CTRLCLK
CLK_MCH_3GPLL#<12>
CLK_MCH_3GPLL<12>
GMCH_CRT_CLK<14>
GMCH_CRT_DATA<14>
GMCH_CRT_B<14>
GMCH_CRT_G<14>
GMCH_CRT_R<14>
12
EDID_CLK_LCD<13>
EDID_DAT_LCD<13>
GMCH_LVDDEN<13>
LVDSAC-<13>
LVDSAC+<13>
LVDSA0-<13>
LVDSA1-<13>
LVDSA2-<13>
LVDSA0+<13>
LVDSA1+<13>
LVDSA2+<13>
GMCH_CRT_B
GMCH_CRT_G
GMCH_CRT_R
CRT_IREF
LCTLA_CLK
LCTLB_DATA
EDID_CLK_LCD
EDID_DAT_LCD
L_IBG
LVDSACLVDSAC+
LVDSA0LVDSA1LVDSA2-
LVDSA0+
LVDSA1+
LVDSA2+
AA26
Y26
H20
H22
A24
A23
E25
F25
C25
D25
F27
D27
H25
H30
G29
F28
E28
G28
H28
K30
K27
J29
J30
K29
D30
C30
A30
A29
G31
F32
D31
H31
G32
C31
F33
D33
F30
E33
D32
F29
G_CLKN
G_CLKP
CRT_DDC_CLK
CRT_DDC_DATA
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_VSYNC
CRT_HSYNC
CRT_IREF
L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CTLBDATA
L_DDC_CLK
L_DDC_DATA
L_VDDEN
L_IBG
L_VBG
L_VREFH
L_VREFL
LA_CLKN
LA_CLKP
LB_CLKN
LB_CLKP
LA_DATAN_0
LA_DATAN_1
LA_DATAN_2
LA_DATAP_0
LA_DATAP_1
LA_DATAP_2
LB_DATAN_0
LB_DATAN_1
LB_DATAN_2
LB_DATAP_0
LB_DATAP_1
LB_DATAP_2
MISC
MISC
LVDS VGA
LVDS VGA
Calistoga-GSE_FCBGA998
Calistoga-GSE_FCBGA998
3
EXP_A_COMPI
EXP_A_ICOMPO
SDVO_TVCLKIN#
SDVO_INT#
SDVO_FLDSTALL#
SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL
SDVO
SDVO
SDVO_RED#
SDVO_GREEN#
SDVO_BLUE#
SDVO_CLKN
SDVO_RED
SDVO_GREEN
SDVO_BLUE
SDVO_CLKP
TV_DACA
TV_DACB
TV_DACC
TV_IREF
TV_IRTNA
TV
TV
TV_IRTNB
TV_IRTNC
TV_DCONSEL0
TV_DCONSEL1
2
+1.5VS_PCIE
R190
R190
24.9_0402_1%
PEGCOMP
R28
M28
N30
R30
T29
M30
P30
T30
P28
N32
P32
T32
N28
M32
P33
R32
+1.5VS
A21
C20
E20
G23
B21
C21
D21
G26
J26
24.9_0402_1%
1 2
Disable TV
1
B B
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/11/10 2009/11/10
2008/11/10 2009/11/10
2008/11/10 2009/11/10
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Calistoga(3/5)-VGA/LVDS
Calistoga(3/5)-VGA/LVDS
Calistoga(3/5)-VGA/LVDS
LA-5091P
LA-5091P
LA-5091P
8 39Wednesday, April 22, 2009
8 39Wednesday, April 22, 2009
8 39Wednesday, April 22, 2009
1
1.0
1.0
1.0
of
of
of
5
hexainf@hotmail.com
+VCCP
D D
C C
+VCCP
B B
A A
AB10
AA10
M25
M24
W22
M22
W21
M21
W20
M20
M19
M18
M17
M16
M15
W14
M14
M10
T25
R25
P25
N25
P24
N24
Y22
V22
U22
T22
R22
P22
N22
Y21
V21
U21
T21
R21
P21
N21
Y20
V20
U20
T20
R20
P20
N20
Y19
P19
N19
Y18
P18
N18
Y17
P17
N17
Y16
P16
N16
Y15
P15
N15
Y14
V14
U14
T14
R14
P14
N14
T10
R10
P10
N10
L10
D1
A18
U1H
U1H
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6
RSVD_3
RSVD_4
RSVD_5
RSVD_6
NCTF
NCTF
Calistoga-GSE_FCBGA998
Calistoga-GSE_FCBGA998
4
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19
CFG_19
RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED14
RESERVED15
RESERVED16
RESERVED17
RESERVED18
RESERVED19
RESERVED20
RESERVED21
RESERVED22
RESERVED23
RESERVED24
RESERVED25
AD25
AC25
AB25
AD24
AC24
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
K14
AD13
Y13
W13
V13
U13
T13
R13
P13
N13
M13
AD12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
AD11
AD10
K10
AN33
AA25
V25
U25
AA22
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA13
A4
A33
B2
AN1
C1
K28
K25
K26
R24
T24
K21
K19
K20
K24
K22
J17
K23
K17
K12
K13
K16
K15
+1.5VS
3
U1E
U1E
AH33
VSS_1
AK32
AG32
AE32
AC32
AA32
AM31
AJ31
AA31
AL30
AG30
AE30
AC30
AA30
AA29
AK28
AH28
AE28
AA28
AM27
AF27
AB27
AA27
AL26
AH26
W26
AN25
AK25
AG25
AE25
AM22
AJ22
AF22
AM20
AK20
AH20
AF20
W19
AM18
AH18
AF18
AK17
AH16
Y33
VSS_2
V33
VSS_3
R33
VSS_4
G33
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
U32
VSS_11
H32
VSS_12
E32
VSS_13
C32
VSS_14
VSS_15
VSS_16
VSS_17
U31
VSS_18
T31
VSS_19
R31
VSS_20
P31
VSS_21
N31
VSS_22
M31
VSS_23
J31
VSS_24
F31
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
Y30
VSS_31
V30
VSS_32
U30
VSS_33
G30
VSS_34
E30
VSS_35
B30
VSS_36
VSS_37
U29
VSS_38
R29
VSS_39
P29
VSS_40
N29
VSS_41
M29
VSS_42
H29
VSS_43
E29
VSS_44
B29
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
U28
VSS_50
T28
VSS_51
J28
VSS_52
D28
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
Y27
VSS_58
U27
VSS_59
T27
VSS_60
R27
VSS_61
P27
VSS_62
N27
VSS_63
M27
VSS_64
G27
VSS_65
E27
VSS_66
C27
VSS_67
B27
VSS_68
VSS_69
VSS_70
VSS_71
U26
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
J25
VSS_77
G25
VSS_78
A25
VSS_79
H23
VSS_80
F23
VSS_81
B23
VSS_82
VSS_83
VSS_84
VSS_85
G22
VSS_86
E22
VSS_87
J21
VSS_88
H21
VSS_89
F21
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
D20
VSS_95
VSS_96
R19
VSS_97
VSS_98
VSS_99
VSS_100
U18
VSS_101
H18
VSS_102
D18
VSS_103
VSS_104
V17
VSS_105
T17
VSS_106
F17
VSS_107
B17
VSS_108
VSS_109
U16
VSS_110
VSS
VSS
Calistoga-GSE_FCBGA998
Calistoga-GSE_FCBGA998
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
J16
AL15
AG15
W15
R15
F15
D15
AM14
AH14
AE14
H14
B14
F13
D13
AL12
AG12
H12
B12
AN11
AJ11
AE11
AM9
AJ9
AB9
W9
R9
M9
J9
F9
C9
A9
AL8
AG8
AE8
U8
AA7
V7
R7
N7
H7
E7
B7
AL6
AG6
AE6
AB6
W6
T6
M6
K6
AN5
AJ5
B5
AA4
V4
R4
N4
K4
H4
E4
AL3
AD3
W3
T3
B3
AK2
AH2
AF2
AB2
M2
K2
H2
F2
V1
R1
2
U1G
U1G
W33
NC1
AM33
NC2
AL33
NC3
C33
NC4
B33
NC5
AN32
NC6
A32
NC7
AN31
NC8
W28
NC9
V27
NC10
W29
NC11
J24
NC12
H24
NC13
W32
NC14
G24
NC15
F24
NC16
E24
NC17
D24
NC18
K33
NC19
A31
NC20
E21
NC21
C23
NC22
AN19
NC23
AM19
NC24
AL19
NC25
AK19
NC26
AJ19
NC27
AH19
NC28
AN3
NC29
Y9
NC30
J19
NC31
H19
NC32
G19
NC33
F19
NC34
E19
NC35
D19
NC36
C19
NC37
B19
NC38
A19
NC39
Y8
NC40
G16
NC41
F16
NC42
E16
NC43
D16
NC44
C16
NC45
B16
NC46
AN2
NC47
A16
NC48
Y7
NC49
AM4
NC50
AF4
NC51
AD4
NC52
AL4
NC53
AK4
NC54
W31
NC55
AJ4
NC56
AH4
NC57
AG4
NC58
AE4
NC59
AM1
NC60
Calistoga-GSE_FCBGA998
Calistoga-GSE_FCBGA998
NC
NC
RESERVED26
RESERVED27
RESERVED28
RESERVED29
RESERVED30
RESERVED31
RESERVED32
RESERVED33
RESERVED34
RESERVED35
RESERVED36
RESERVED37
RESERVED38
RESERVED39
RESERVED40
RESERVED41
RESERVED42
1
W30
NC61
Y6
NC62
AL1
NC63
Y5
NC64
Y10
NC65
W10
NC66
W25
NC67
V24
NC68
U24
NC69
V10
NC70
U10
NC71
K18
NC72
Y25
Y24
AB22
AB21
AB19
AB16
AB14
AA12
W24
AA24
AB24
AB20
AB18
AB15
AB13
AB12
AB17
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/11/10 2009/11/10
2008/11/10 2009/11/10
2008/11/10 2009/11/10
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Calistoga(4/5)-PWR/GND
Calistoga(4/5)-PWR/GND
Calistoga(4/5)-PWR/GND
LA-5091P
LA-5091P
LA-5091P
9 39Wednesday, April 22, 2009
9 39Wednesday, April 22, 2009
9 39Wednesday, April 22, 2009
1
1.0
1.0
1.0
of
of
of
2940mA
1
+
+
C41
C41
2
10U_0805_10V4Z
10U_0805_10V4Z
+VCCP
D15
D15
RB751V-40_SOD323-2
RB751V-40_SOD323-2
1 2
12
1
2
C39
C39
+2.5VS
5
5
10U_0805_10V4Z
10U_0805_10V4Z
1
C261
C261
2
1
C265
C265
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.47U_0603_16V4Z
0.47U_0603_16V4Z
0.47U_0603_16V4Z
0.47U_0603_16V4Z
1
+
+
C40
C40
2
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
0.47U_0603_16V4Z
0.47U_0603_16V4Z
1
2
C281
C281
C266
C266
C25
C25
1 2
C22
C22
1 2
1
2
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
C283
C283
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1250mA
10mil
0.1U_0402_16V4Z
0.1U_0402_16V4Z
780mA
10mil
C276
C276
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
10mil
2
1
1
2
+1.5VS
C250
C250
+VCCP
1
2
10mil
2
C248
C248
0.47U_0402_10V4Z~D
0.47U_0402_10V4Z~D
1
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AC27
AD26
AC26
AB26
AE19
AE18
AF17
AE17
AF16
AE16
AF15
AE15
M26
W18
W17
W16
AE9
AD9
AD8
AD7
AD6
AA1
T26
R26
P26
N26
V19
U19
T19
V18
T18
R18
U17
R17
V16
T16
R16
V15
U15
T15
J14
J10
H10
U9
A14
D10
P9
L9
D9
P8
L8
D8
P7
L7
D7
A7
P6
L6
G6
D6
U5
P5
L5
G5
D5
Y4
U4
P4
L4
G4
D4
Y3
U3
P3
L3
G3
D3
Y2
U2
P2
L2
G2
D2
F1
+VCCP
C37
C37
220U_B2_2.5VM_R35
D D
C C
B B
A A
220U_B2_2.5VM_R35
R168
R168
10_0402_5%
10_0402_5%
Check power sequence
if OK then @
Vccp->1.5V->3.3V
U1D
U1D
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT36
VTT35
VTT37
VTT38
VTT39
VTT40
4
VCCATVDACA0
VCCATVDACA1
VCCATVDACB0
VCCATVDACB1
VCCATVDACC0
VCCATVDACC1
VCCATVBG
VSSATVBG
VCCDTVDAC
VCCDQTVDAC
VCCDLVDS0
VCCDLVDS1
VCCDLVDS2
VCCADPLLA
VCCADPLLB
POWER
POWER
VCCDHMPLL1
VCCDHMPLL2
VCCTXLVDS0
VCCTXLVDS1
VCCA3GPLL
VCCA3GBG
VSSA3GBG
VCCACRTDAC0
VCCACRTDAC1
VSSACRTDAC
VSSALVDS
Calistoga-GSE_FCBGA998
Calistoga-GSE_FCBGA998
4
VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCAMPLL
VCCAHPLL
VCC3G0
VCC3G1
VCCSYNC
VCCALVDS
VTT41
VTT42
VTT43
VTT44
VTT45
B20
A20
B22
A22
D22
C22
D23
E23
F20
F22
C28
B28
A28
E26
D26
C26
AB33
AM32
AN29
AM29
AL29
AK29
AJ29
AH29
AG29
AF29
AE29
AN24
AM24
AL24
AK24
AJ24
AH24
AG24
AF24
AE24
AN18
AN16
AM16
AL16
AK16
AJ16
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AN4
AM10
AL10
AK10
AH1
AH10
AG10
AF10
AE10
AN7
AM7
AL7
AK7
AJ7
AH7
AN10
AJ10
AD1
AD2
B26
J32
AE5
AD5
D29
C29
U33
T33
V26
N33
M33
J23
C24
B24
B25
B31
B32
P1
L1
G1
U1
Y1
+1.5VS
400mA
2mA
10mA
144mA
20mA
40mA
10mil
10mil
10mil
+1.5VS_MPLL
+1.5VS_HPLL
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS
+2.5VS
+1.5VS_3GPLL
+2.5VS
+2.5VS_CRTDAC
+2.5VS
3
2
Disable TV
+1.5VS
+3VS
1
1
C23
C23
C239
C239
2
2
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.8V
533 MTS=1720mA
1
1
C288
C288
2
1U_0603_10V6K~D
1U_0603_10V6K~D
1
C330
C330
C293
C293
2
2
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
10mil
C54
C54
150mA
60mA
10mil
1
1
C286
C286
C318
C318
1U_0603_10V6K~D
1U_0603_10V6K~D
2
2
1U_0603_10V6K~D
1U_0603_10V6K~D
1U_0603_10V6K~D
1U_0603_10V6K~D
1
C319
C319
1U_0402_6.3V4Z~D
1U_0402_6.3V4Z~D
2
1
C329
C329
2
1
1U_0603_10V6K~D
1U_0603_10V6K~D
2
45mA
45mA
50mA
50mA
Route +2.5VS from GMCH pinN33 to
decoupling cap <200mil to the edge.
400mA
70mA
70mA
+VCCP
1
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
1
C242
C242
2
2
C241
C241
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.022U_0402_16V7K
0.022U_0402_16V7K
Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.
3
R172
R172
12
10_0603_5%
10_0603_5%
C244
C244
10U_0805_10V4Z
10U_0805_10V4Z
2008/11/10 2009/11/10
2008/11/10 2009/11/10
2008/11/10 2009/11/10
+2.5VS
CRTDAC: Route FB
within 3" of Calistoga
1
1
C24
C24
C235
C235
2
2
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
330U_D2E_2.5VM
330U_D2E_2.5VM
1
C249
C249
1
+
+
C257
C257
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+2.5VS
1
C267
C267
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+2.5VS
1
C256
C256
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
1 2
L20
L20
FBMA-L10-160808-301LMT_2P
FBMA-L10-160808-301LMT_2P
1
C254
C254
1
2
2
10U_0805_10V4Z
10U_0805_10V4Z
C245
C245
10U_0805_10V4Z
10U_0805_10V4Z
2
PCI-E/MEM/PSB PLL decoupling
R210
R210
1
1
C277
C277
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5VS_MPLL
+1.5VS_PCIE
C253
C253
45mA Max.
R45
R45
0_0603_5%
0_0603_5%
1
1
C48
C48
C52
C52
2
2
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5VS +1.5VS
0_0805_5%
1
2
10U_0805_10V4Z
10U_0805_10V4Z
0_0805_5%
1
+
+
C259
C259
2
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
C278
C278
2
10U_0805_10V4Z
10U_0805_10V4Z
12
+1.5VS_DPLLA+1.5VS_DPLLB
C236
C236
40mA Max.40mA Max.
1 2
330U_D2E_2.5VM
330U_D2E_2.5VM
1
C27
C27
1
+
+
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R177
R177
12
+1.5VS
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
12
0_0603_5%
0_0603_5%
+1.5VS
L2
L2
FBMA-L10-160808-301LMT_2P
FBMA-L10-160808-301LMT_2P
+2.5VS
1
C260
C260
2
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
close pin C29/D29
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Calistoga(5/5)-PWR/GND
Calistoga(5/5)-PWR/GND
Calistoga(5/5)-PWR/GND
1
@
@
+1.5VS_HPLL
1
C43
C43
C44
C44
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C247
C247
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
LA-5091P
LA-5091P
LA-5091P
1
+1.5VS+1.5VS_3GPLL
1
C287
C287
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
45mA Max.
R38
R38
0_0603_5%
0_0603_5%
1
2
10U_0805_10V4Z
10U_0805_10V4Z
+2.5VS
1
C237
C237
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.01U_0402_25V7K
0.01U_0402_25V7K
close pin B31
10 39Wednesday, April 22, 2009
10 39Wednesday, April 22, 2009
10 39Wednesday, April 22, 2009
12
+1.5VS
1
C246
C246
2
1.0
1.0
1.0
of
of
of
5
hexainf@hotmail.com
DDR_A_DQS#[0..7]<7>
DDR_A_D[0..63]<7>
DDR_A_DM[0..7]<7>
DDR_A_DQS[0..7]<7>
DDR_A_MA[0..13]<7>
D D
+1.8V
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
2
+0.9VS
1
2
C88
C88
C102
C102
1
C70
C70
C71
C71
2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
C87
C87
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C83
C83
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
RP5
RP5
18
27
36
45
56_0804_8P4R_5%
56_0804_8P4R_5%
RP6
RP6
18
27
36
45
56_0804_8P4R_5%
56_0804_8P4R_5%
RP4
RP4
18
27
36
45
56_0804_8P4R_5%
56_0804_8P4R_5%
1
2
1
1
C91
C91
2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
+
+
@
@
C C
+0.9VS
1
C79
C79
B B
A A
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C61
C61
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
1
C84
C84
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_A_MA13
M_ODT0
DDR_CS0#
DDR_A_RAS#
DDR_A_BS0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3
M_ODT1
DDR_CS1#
DDR_A_CAS#
DDR_A_WE#
DDR_A_BS2
DDR_CKE0
C69
C69
2
1
C104
C104
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
5
C89
C89
C90
C90
2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
1
C68
C68
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
1
C81
C81
C103
C103
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
RP1
RP1
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
56_0804_8P4R_5%
RP2
RP2
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
56_0804_8P4R_5%
RP3
RP3
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
56_0804_8P4R_5%
R159
R159
1 2
56_0402_5%
56_0402_5%
R160
R160
1 2
56_0402_5%
56_0402_5%
1
2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
C82
C82
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_A_BS1
DDR_A_MA0
DDR_A_MA2
DDR_A_MA4
DDR_A_MA6
DDR_A_MA7
DDR_A_MA11
DDR_CKE1
DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12
C101
C101
Layout Note:
Place near JDIM1
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4
+DIMM_VREF
20mils
1
C86
C86
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
1
C78
C78
C99
C99
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4
1
1
C80
C80
C100
C100
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Layout Note:
Place these resistor
closely DIMMA,all
trace length<750 mil
Layout Note:
Place these resistor
closely DIMMA,all
trace length
Max=1.3"
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1
C92
C92
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2
+3VS
1
C360
@C360
@
2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
3
+1.8V +1.8V
+DIMM_VREF
DDR_CKE0<6>
DDR_A_BS2<7>
DDR_A_BS0<7>
DDR_A_WE#<7>
DDR_A_CAS#<7>
DDR_CS1#<6>
M_ODT1<6>
CLK_SMBDATA<12>
CLK_SMBCLK<12>
1
C361
C361
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2008/11/10 2009/11/10
2008/11/10 2009/11/10
2008/11/10 2009/11/10
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D9
DDR_A_D8
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1#
M_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
CLK_SMBDATA
CLK_SMBCLK
+3VS
2/10:Change from 5.2mm to 4mm height CPN:SP07000CK00
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
JDIM1
JDIM1
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
TYCO_292526-4
TYCO_292526-4
DIMMA
2
DQ12
DQ13
CK0#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
NC/CKE1
NC/A15
NC/A14
RAS#
ODT0
NC/A13
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
CK1#
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
CK0
VSS
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
CK1
VSS
DM6
VSS
VSS
VSS
VSS
VSS
1
2
VSS
NC
A11
A7
A6
A4
A2
A0
BA1
S0#
NC
SA0
SA1
DDR_A_D4
4
DDR_A_D5
6
8
DDR_A_DM0
10
12
DDR_A_D6
14
DDR_A_D7
16
18
DDR_A_D12
20
DDR_A_D13
22
24
DDR_A_DM1
26
28
M_CLK_DDR0
30
M_CLK_DDR#0
32
34
DDR_A_D14
36
DDR_A_D15
38
40
42
DDR_A_D20
44
DDR_A_D21
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
R54
R54
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS0#
M_ODT0
DDR_A_MA13
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R53 10K_0402_5%
R53 10K_0402_5%
1 2
R52 10K_0402_5% R52 10K_0402_5%
1 2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
M_CLK_DDR0 <6>
M_CLK_DDR#0 <6>
0_0402_5%
0_0402_5%
1 2
DDR_CKE1 <6>
DDR_CS0# <6>
M_ODT0 <6>
M_CLK_DDR1 <6>
M_CLK_DDR#1 <6>
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DDRII-SODIMM A
DDRII-SODIMM A
DDRII-SODIMM A
DDR_A_BS1 <7>
DDR_A_RAS# <7>
LA-5091P
LA-5091P
LA-5091P
1
PM_EXTTS#0 <6>
1.0
1.0
11 39Wednesday, April 22, 2009
11 39Wednesday, April 22, 2009
11 39Wednesday, April 22, 2009
1.0
of
of
of
5
PCI
SRC
CPU
CLKSEL1
0
FSA
CLKSEL0
MHz
266
MHz
1000
MHz
MHz
33.30
14.318 96.0 48.0
DOT_96
MHz
USB
MHz
FSC FSB REF
CLKSEL2
0 1000 133 33.31 14.318 96.0 48.0
0 1001 200 33.30 14.318 96.0 48.0
0 1001 166 33.31 14.318 96.0 48.0
D D
1 1000 333 33.30 14.318 96.0 48.0
1 1000 100 33.31 14.318 96.0 48.0
1 1001 400 33.30 14.318 96.0 48.0
1 1 1
Reserved
4
+3VM_CK505
1 2
+3VS
R78 0_0805_5%R78 0_0805_5%
*
+VCCP
1 2
R131 0_0805_5%R131 0_0805_5%
1
C151
C151
10U_0805_10V4Z
10U_0805_10V4Z
2
+1.05VM_CK505
1
C163
C163
10U_0805_10V4Z
10U_0805_10V4Z
2
1
2
C181
C181
47P_0402_50V8J
47P_0402_50V8J
1
C198
C198
47P_0402_50V8J
47P_0402_50V8J
2
3
1
C175
C175
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C152
C152
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C197
C197
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C153
C153
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C199
C199
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C167
C167
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C155
C155
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C189
C189
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
1
C154
C154
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C200
C200
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
ICH_SMBDATA<17>
ICH_SMBCLK<17>
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
6 1
+3VS
3
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
+3VS
R112
R112
2.2K_0402_5%
2.2K_0402_5%
Q10A
Q10A
2
5
4
Q10B
Q10B
1
R108
R108
2.2K_0402_5%
2.2K_0402_5%
CLK_SMBDATA
CLK_SMBCLK
SA000020K00 (Silego : SLG8SP556VTR )
SA000020H10 (ICS : ICS9LPRS387AKLFT)
+3VM_CK505
+VCCP
R140
R138
R138
2.2K_0402_5%
2.2K_0402_5%
C C
B B
A A
FSA
CPU_BSEL0<4>
CPU_BSEL1<4>
CPU_BSEL2<4>
1 2
R147
@R147
@
0_0402_5%
0_0402_5%
1 2
R91
R91
0_0402_5%
0_0402_5%
@
@
R100
R100
10K_0402_5%
10K_0402_5%
FSC
1 2
R95
@R95
@
0_0402_5%
0_0402_5%
R140
56_0402_5%
56_0402_5%
1 2
12
1 2
R142
R142
1K_0402_5%
FSB
1K_0402_5%
12
R141
@R141
@
1K_0402_5%
1K_0402_5%
+VCCP
R81
1@ R81
1@
1K_0402_5%
1K_0402_5%
1 2
1 2
R86
R86
1K_0402_5%
1K_0402_5%
12
R82
2@ R82
2@
0_0402_5%
0_0402_5%
+VCCP
R97
@R97
@
1K_0402_5%
1K_0402_5%
1 2
1 2
12
R99
R99
1K_0402_5%
1K_0402_5%
12
R98
R98
0_0402_5%
0_0402_5%
C169 22P_0402_50V8J
C169 22P_0402_50V8J
14.31818MHZ_16PF_DSX840GA
14.31818MHZ_16PF_DSX840GA
C162 22P_0402_50V8J
C162 22P_0402_50V8J
Routing the trace at least 10mil
5
MCH_CLKSEL0 <6>
MCH_CLKSEL1 <6>
MCH_CLKSEL2 <6>
12
Y2
Y2
CLK_XTAL_IN
CLK_XTAL_OUT
+1.05VM_CK505
1 2
C1244.7P_0402_50VNPO @C1244.7P_0402_50VNPO @
12
C8325P_0402_50V8C @ C8325P_0402_50V8C @
C3924.7P_0402_50VNPO @C3924.7P_0402_50VNPO @
1 2
R289
R289
33_0402_5%
33_0402_5%
R121
R121
1 2
33_0402_5%
33_0402_5%
1 2
1 2
1 2
R295 22_0402_5%R295 22_0402_5%
1 2
R137 22_0402_5%R137 22_0402_5%
1 2
R101 33_0402_5% R101 33_0402_5%
R109
R109
10K_0402_5%
10K_0402_5%
R110
R110
@
@
10K_0402_5%
10K_0402_5%
RTS5159_48M<23>
CLK_ICH_48M<17>
CLK_ICH_14M<17>
H_STP_CPU#<17>
H_STP_PCI#<17>
CLK_PCI_LPC<25>
CLK_PCI_ICH<15>
VGATE<17,25,35>
4.7P_0402_50VNPO
4.7P_0402_50VNPO
C120
@C120
@
1 2
4.7P_0402_50VNPO
4.7P_0402_50VNPO
C123
@C123
@
1 2
1 2
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96#
Pin28/29 : LCDCLK / LCDCLK#
For PCI2_TME:0=Overclocking of CPU and SRC allowed
(ICS only) 1=Overclocking of CPU and SRC NOT allowed
1 = Pin24/25 : SRC_0 / SRC_0#
Pin28/29 : 27M/27M_SS
+3VS+3VS +3VS
R119
R129
R129
10K_0402_5%
10K_0402_5%
1 2
ITP_EN PCI4_SEL PCI2_TME
R132
R132
@
@
10K_0402_5%
10K_0402_5%
1 2
4
R119
@
@
10K_0402_5%
10K_0402_5%
1 2
R117
R117
10K_0402_5%
10K_0402_5%
1 2
FSB
FSC
VGATE
H_STP_CPU#
H_STP_PCI#
CLK_XTAL_IN
CLK_XTAL_OUT
PCI_LPC
PCI2_TME
PCI4_SEL
ITP_EN
U11
U11
55
VDD_SRC
6
VDD_REF
12
VDD_PCI
72
VDD_CPU
19
VDD_48
27
VDD_PLL3
66
VDD_CPU_IO
31
VDD_PLL3_IO
62
VDD_SRC_IO
52
VDD_SRC_IO
23
VDD_IO
38
VDD_SRC_IO
FSA
20
USB_0/FS_A
2
FS_B/TEST_MODE
7
REF_0/FS_C/TEST_
8
REF_1
1
CKPWRGD/PD#
11
NC
53
CPU_STOP#
54
PCI_STOP#
5
XTAL_IN
4
XTAL_OUT
13
PCI_1
14
PCI_2
15
PCI_3
16
PCI_4/SEL_LCDCL
17
PCIF_5/ITP_EN
18
VSS_PCI
3
VSS_REF
22
VSS_48
26
VSS_IO
69
VSS_CPU
30
VSS_PLL3
34
VSS_SRC
59
VSS_SRC
42
VSS_SRC
73
VSS
SLG8SP556VTR_QFN72_10X10
SLG8SP556VTR_QFN72_10X10
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
SRC_0/DOT_96
SRC_0#/DOT_96#
LCDCLK/27M
LCDCLK#/27M_SS
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
SRC_10#
SRC_11#
CLKREQ_3#
CLKREQ_4#
CLKREQ_6#
CLKREQ_7#
CLKREQ_9#
SLKREQ_10#
CLKREQ_11#
USB_1/CLKREQ_A#
2008/11/10 2009/11/10
2008/11/10 2009/11/10
2008/11/10 2009/11/10
9
SDA
10
SCL
71
CPU_0
70
CPU_0#
68
CPU_1
67
CPU_1#
24
25
28
29
32
SRC_2
33
SRC_2#
35
SRC_3
36
SRC_3#
39
SRC_4
40
SRC_4#
57
SRC_6
56
SRC_6#
61
SRC_7
60
SRC_7#
64
63
44
SRC_9
45
SRC_9#
50
SRC_10
51
48
SRC_11
47
37
41
58
65
43
49
46
21
Compal Secret Data
Compal Secret Data
Compal Secret Data
CLK_SMBDATA
CLK_SMBCLK
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_WLAN
CLK_PCIE_WLAN#
CPU_ITP
CPU_ITP#
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_PCIE_ICH
CLK_PCIE_ICH#
MCH_CLKREQ#
WLAN_CLKREQ#
CLKREQ_LAN#
Deciphered Date
Deciphered Date
Deciphered Date
CLK_SMBDATA <11>
CLK_SMBCLK <11>
CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>
CLK_MCH_BCLK <6>
CLK_MCH_BCLK# <6>
CLK_MCH_DREFCLK <6>
CLK_MCH_DREFCLK# <6>
MCH_SSCDREFCLK <6>
MCH_SSCDREFCLK# <6>
CLK_PCIE_SATA <16>
CLK_PCIE_SATA# <16>
CLK_MCH_3GPLL <8>
CLK_MCH_3GPLL# <8>
CLK_PCIE_WLAN <19>
CLK_PCIE_WLAN# <19>
CPU_ITP <4>
CPU_ITP# <4>
CLK_PCIE_LAN <24>
CLK_PCIE_LAN# <24>
CLK_PCIE_ICH <17>
CLK_PCIE_ICH# <17>
SRC PORT LIST
PORT
SRC0
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11
MCH_CLKREQ#
CLKREQ_LAN#
WLAN_CLKREQ#
DEVICE
MCH_DREFCLK
PCIE_SATA
MCH_3GPLL
PCIE_WLAN
PCIE_LAN
PCIE_ICH
R139 10K_0402_5%R139 10K_0402_5%
R111 10K_0402_5%R111 10K_0402_5%
R84 10K_0402_5%R84 10K_0402_5%
+3VS
12
12
12
REQ PORT LIST
MCH_CLKREQ# <6>
WLAN_CLKREQ# <19>
CLKREQ_LAN# <24>
REQ_3#
REQ_4#
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11#
REQ_A#
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Clock Generator CK505
Clock Generator CK505
Clock Generator CK505
MCH_DREFCLK
PCIE_WLAN
PCIE_LAN
LA-5091P
LA-5091P
LA-5091P
1
DEVICEPORT
1.0
1.0
1.0
of
12 39Wednesday, April 22, 2009
of
12 39Wednesday, April 22, 2009
of
12 39Wednesday, April 22, 2009
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