Dell Inspiron 5379, Inspiron 5579, Inspiron 7773 Schematics
5
D D
4
3
2
1
Starlord KBL_Refresh Schematics
KabyLake-R
C C
2017-05-25
REV : A00
B B
DY : None Installed
A A
UMA: UMA only installed
OPS: DISCRTE OPTIMUS installed
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
W
W
W
i
i
i
stron Corporation
stron Corporation
stron Corporation
2
2
2
1
1
1
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
T
tle
Title
Title
i
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A
A
A
3
3
3
Monday, August 2 8, 2017
Monday, August 2 8, 2017
Monday, August 2 8, 2017
Date: Sheet
Date: Sheet
Date: Sheet
C
C
C
er Page
er Page
er Page
ov
ov
ov
S
S
S
t
t
t
arlord KBL-R
arlord KBL-R
arlord KBL-R
1 1
1 1
1 1
1
o
o
o
f
f
f
A
A
A
0
0
0
06
06
06
0
0
0
Project code: 4PD0CF010001(SL13_R)
WWW.AliSaler.Com
5
4PD0CG010001(SL15_R)
4PD0CH010001(SL17_B)
Star lord KBL Block Diagram
PCB P/N: 16888
Revision: A00
D D
RA
M(GDDR5) *4
V
2GB/4GB
G
DDR5
GPU
NVDIA
N17S-G1
18W
GPU BOARD
HDMI V1.4
HDMI
57
13.3"/15.6"/17.3"
(HD/FHD)
ouc
h panel
T
USB3.0 Port2
owe
C C
P
r share
5
5
USB PowerShare
34
USB3.0 Port3
ROR only
35
7mm HDD
Free fall
INT2
B B
Sensor BD
on Panel side
Gsensor
ST
LNG2DMTR
E-compass
ST
LIS3MDLTR
yr
o
G
ST
LSM6DS3USTR
70
eSPI debug port
Thermal
NUVOTON
NCT7718W
SMBUS
26
Fan Control
A A
PWM
FAN
Int.
KB
5
DM
H
TI
TPS2544RTER
68
KBC
SMSC
1416
EC
M
I Level Shifter
PS2
ouc
h PAD
T
Image sensor
57
USB2.0
USB3.0
USB2.0
USB3.0
USB2.0
eSPI
24
4
PCIE x 4
PCIE Lane1~Lane4
HDMI
eDP
U
SB2.0 LANE7
U
SB3.0 LANE1
USB2.0 LANE1
USB3.0 LANE3
USB2.0 LANE2
SATA
2C
I
(To CCG4
I2C
& USB2.0/I2C MUX)
TPM
NUVOTON
NPCT650JB2YX
4
SPI
Flash ROM
I2C
nt
el CPU
I
KBL/KBL-R
U22 / U42
10 USB 2.0/1.1 ports
SB 3.0 ports
U
6
ig
h Definition Audio
H
3 SATA ports
6 PCIE ports
LPC I/F
I 5.0
CP
A
SPI
16MB
Quad Read
3
Channel A
Channel B
DP
MUX and Redriver
TI
USB3.0
USB3.0 LANE4
USB2.0
USB2.0 LANE4
SATA/PCIex2/PCIEx4(Optane)
TUSB546-DCI
CCG4
CYPRESS
CYPD4125
3
8
37
USB2.0/I2C MUX
M.2 SSD
CardReader
USB2.0 LANE8
USB2.0
USB2.0 x 1
USB2.0 LANE5
HDA
USB2.0 x 1
PCIE LANE5
USB2.0 LANE6
USB2.0 LANE3
SD 3.0
Realtak
RTS5176E
PCIe
USB2.0
Camera (HD/IR)
D-MIC
HDA
NGFF WLAN
USB2.0 Port4
55
CODEC
Realtek
ALC3253
2526
3
27
MIC_IN/GND
HP_R/L
2
SENSOR IO MB
ROR
17A18-SA 17A17-SA 17810-1
BBY
DDR4
IMM A
OD
S
12
DDR4
OD
IMM B
S
13
DP/USB 3.0
I2C
TI
TS3DS10224
(To KBC)
USB2.0/I2C
3
8
63
SD Card Slot
IO Board
2CH SPEAKER
(2CH 2W/4ohm)
ni
U
2
USB3.0 type c
Port1
BBY only
versal Jack
1
C
HARGER
ISL88739
NPUTS
I
AD+
16888-117A16-SA17A18-SA
38
<Core Design>
<Core Design>
<Core Design>
T
T
T
le
le
le
it
it
it
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
BT+
S
YSTEM DC/DC
SY8288CRAC-GP
NPUTS
I
DCBATOUT
C
PU Core Power
NCP81208MNTXG-GP
NCP81382MNTXG-1-GP
NCP81382MNTXG-1-GP
NCP81253MNTBG-GP
NPUTS
I
DCBATOUT
DCBATOUT +VCCGT
D
DR4
SY8288RAC-GP
APL5338XAI-TRG-GP
NPUTS OUTPUTS
I
DCBATOUT
C
PU DCDC-V1D00A
AOZ1268QI-02-GP
NPUTS OUTPUTS
I
DCBATOUT
L
DO-V1D5V
S-1339D15-M5001-GP
3D3V_S5
L
DO-V1D8V
APL5930KAI-TRG-GP
NPUTS OUTPUTS
I
3D3V_S5
5
G5016KD1U
NPUTS
I
5V_S5
M5938ARD1U-GP-U
INPUTS
1D0V_S5
TPS22965DSGR-GP-U
INPUTS
1D0V_S5
S
YSTEM DC/DC
TPS51225RUKR-GP
NPUTS
I
DCBATOUT
W
W
W
2
2
2
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
B
B
B
k Diagram
k Diagram
k Diagram
loc
loc
loc
rlord KBL-R
rlord KBL-R
rlord KBL-R
ta
ta
ta
S
S
S
1
UTPUTS
O
DCBATOUT
UTPUTS
O
PWR_5V
5V_S5
5V_AUX_S5
UTPUTS
O
VCC_CORE
+VCCSA_VRDCBATOUT
1D2V_S3
0D675V_S0
1D0V_S5
UTPUTSINPUTS
O
1D5V_S0
1D8V_S5
V/3V S0
OUTPUTS
5V_S0
3D3V_S03D3V_S5
V
CCSTG
UTPUTS
O
+VCCSTG
V
CCST
UTPUTS
O
+V1.00U_CPU
UTPUTS
O
3D3V_AUX_S5
3D3V_S5
PWR_3D3V
tron Corporation
tron Corporation
tron Corporation
is
is
is
, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1F
1F
1F
2
2
2
44
45
46~50
3
3
51
52
54
54
40
40
40
45
00
00
00
A
A
A
o
o
o
f
10
f
10
f
10
6Monday, August 28, 2017
6Monday, August 28, 2017
6Monday, August 28, 2017
5
4
3
2
1
SSID = CPU
D D
C C
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
W
W
W
i
i
i
stron Corporation
stron Corporation
stron Corporation
2
2
2
1
1
1
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
T
tle
Title
Title
i
(
(
(
eserved)
eserved)
eserved)
R
R
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet
Date: Sheet
Date: Sheet
R
A
A
A
3
3
3
S
S
S
arlord KBL-R
arlord KBL-R
arlord KBL-R
t
t
t
3 1
3 1
3 1
1
o
o
o
f
f
f
0
0
0
0
0
0
A
A
A
06Monday, August 2 8, 2017
06Monday, August 2 8, 2017
06Monday, August 2 8, 2017
5
WWW.AliSaler.Com
SSID = CPU
+
CSTG
VC
D D
[PECI] and [PRO CHOT#]
Impedance contr ol: 50 ohm
Vince,20170106
H
_P
ECI_CPU[24]
H
ROCHOT#[24,44,46]
_P
Rb
Vince,20161107
3
D3
V_S5_PC H
R
4
40
1 2
Vince,20161031
C C
Vince,20161031
T
WAK E_KBC#
P_
DY
100KR2J -1-GP
1 2
R
0
41
0R0402-P AD
+VCCSTG = 1.0 V +VCCSTG = 1.0 V
12
R
1
40
1KR2J-1-G P
1 2
R
TPAD14-O P-GP
TPAD14-O P-GP
TPAD14-O P-GP
TPAD14-O P-GP
TPAD14-O P-GP
TPAD14-O P-GP
TPAD14-O P-GP
TPAD14-O P-GP
40
Ra
3499R2F-2 -GP
T
TPAD14-O P-GP
T
P4
T
P4
T
P4
T
P4
T
P4
T
P4
T
P4
T
P4
4
3
2
1
#544669 CRB Rev 0.52
+
CST_CPU
VC
12
R
41
9
1KR2J-1-G P
P
_THERMT RIP#
CH
C
1D
P4
01
H
1
ATERR#
_C
H
ROCHOT# _R
_P
P
_THERMT RIP#
CH
1
S
OCC#
KT
02
X
1
_BPM0
DP
05
X
1
_BPM1
DP
06
X
1
_BPM2
DP
07
X
1
DP
_BPM3
08
1
03
1
09
1
04
R
41
249D9R2F -GP
R
349D9R2F -GP
41
R
449D9R2F -GP
41
R
549D9R2F -GP
41
T
OU
CH_PAD_ INTR#
C
12
PU
P
12
CH
E
12
DR
E
12
OP
C
_EN#
AM
T
CH_PANE L_INTR#
OU
T
CH_PANE L_PD#
OU
_POPIRCOM P
_POPIRCOM P
AM_OPIO_R COMP
IO_RCOMP
D63
A54
C65
C63
A65
C55
D55
B54
C56
BA5
AY5
AT16
AU16
H66
H65
A6
A7
PU
C
AT
ERR#
P
I
EC
P
RO
CHOT#
T
HE
RMTRIP#
S
KT
OCC#
B
#[0]
PM
B
#[1]
PM
B
PM
#[2]
B
PM
#[3]
G
_E3/CPU_GP0
PP
G
PP
_E7/CPU_GP1
G
PP
_B3/CPU_GP2
G
_B4/CPU_GP3
PP
P
RO
C_POPIRCOMP
P
_OPIRCOMP
CH
O
E_RCOMP
PC
O
PC
_RCOMP
SKYLAKE-U-GP
SKYLAKE_ULT
CPU MISC
JTAG
P
RO
P
_JTAG_TCK
CH
P
CH
P
CH
_JTAG_TDO
P
_JTAG_TMS
CH
P
4
OF 20
P
RO
C_TCK
P
C_TDI
RO
P
C_TDO
RO
P
C_TMS
RO
C_TRST#
_JTAG_TDI
CH
_TRST#
J
TA
B61
D60
A61
C60
B59
B56
D59
A56
C59
C61
A59
GX
X
_TCLK
DP
X
DP
_TDI
X
_TDO_CP U
DP
X
_TMS
DP
X
_TRST#
DP
P
_JTAG_T CK
CH
P
_JTAG_T DI
CH
P
CH
_JTAG_T DO
P
_JTAG_T MS
CH
X
DP
_TRST#
X
_TCK_JT AGX
DP
12
01
D4
E
DY
E
MI DVT1 0210
AZ5725-01FDR7G-GP
X
DP
X
DP
X
DP
P
CH
P
CH
P
CH
X
DP
X
DP
X
DP
P
CH
_TMS
_TDI
_TDO_CP U
_JTAG_T DI
_JTAG_T DO
_JTAG_T MS
_TCK_JT AGX
_TRST#
_TCLK
_JTAG_T CK
1 2
DY
1 2
DY
1 2
DY
PH in P.99
1 2
1 2
1 2
1 2
DY
R
1 2
40
2 51R2J-2-G P
DY
1 2
R
6 51R2J-2-G P
40
1 2
R
7 51R2J-2-G P
40
DY
+
VC
CSTG
R
42
151R2J-2-G P
R
42
251R2J-2-G P
R
351R2J-2-G P
42
R
851R2J-2-G P
40
R
951R2J-2-G P
40
R
651R2J-2-G P
41
R
71 KR2J-1-GP
41
Add resistor by NON DS3 function
(#543016) PROCHOT# Routing Guidelines
B B
M1,2,3,4,5: <3 inches
M6: 1-11 inches
MCPU: 0.3-1.5 i nches
Mt <0.3 mils
Main route(M1+M 2+M3+M4+M5+M6+ MCPU): 1-12 i nches
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
W
W
W
is
is
is
tron Corporation
tron Corporation
tron Corporation
2
2
2
, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1F
1F
1F
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
T
le
Title
Title
it
C
C
C
PU
PU
PU
_(JTAG/CPU SIDE BAND)
_(JTAG/CPU SIDE BAND)
_(JTAG/CPU SIDE BAND)
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A
A
A
3
3
3
Date: Sheet
Date: Sheet
Date: Sheet
S
S
S
rlord KBL-R
rlord KBL-R
rlord KBL-R
ta
ta
ta
4 10
4 10
4 10
1
o
o
o
f
f
f
00
00
00
A
A
A
6Friday, December 08, 201 7
6Friday, December 08, 201 7
6Friday, December 08, 201 7
SSID = CPU
5
4
3
2
1
DDR4 ball type: Interleaved Type
D D
P
U1B
C
A_DQ0
_
AL71
M
A_DQ0[12]
_
M
_
A_DQ1[12]
M
A_DQ2[12]
_
M
_
A_DQ3[12]
M_A_DQ[0:7]
M_A_DQ[8:15]
M_B_DQ[0:7]
M_B_DQ[8:15]
C C
M_A_DQ[16:23]
M_A_DQ[24:31]
M_B_DQ[16:23]
M_B_DQ[24:31]
B B
M
_
A_DQ4[12]
M
A_DQ5[12]
_
M
_
A_DQ6[12]
M
A_DQ7[12]
_
M
_
A_DQ8[12]
M
A_DQ9[12]
_
M
_
A_DQ10[12]
M
_
A_DQ11[12]
M
A_DQ12[12]
_
M
_
A_DQ13[12]
M
A_DQ14[12]
_
M
_
A_DQ15[12]
M
B_DQ0[13]
_
M
_
B_DQ1[13]
M
_
B_DQ2[13]
M
B_DQ3[13]
_
M
_
B_DQ4[13]
M
B_DQ5[13]
_
M
_
B_DQ6[13]
M
_
B_DQ7[13]
M
B_DQ8[13]
_
M
_
B_DQ9[13]
M
B_DQ10[13]
_
M
_
B_DQ11[13]
M
_
B_DQ12[13]
M
B_DQ13[13]
_
M
_
B_DQ14[13]
M
B_DQ15[13]
_
M
_
A_DQ16[12]
M
_
A_DQ17[12]
M
A_DQ18[12]
_
M
_
A_DQ19[12]
M
A_DQ20[12]
_
M
_
A_DQ21[12]
M
A_DQ22[12]
_
M
A_DQ23[12]
_
M
_
A_DQ24[12]
M
A_DQ25[12]
_
M
_
A_DQ26[12]
M
A_DQ27[12]
_
M
_
A_DQ28[12]
M
_
A_DQ29[12]
M
A_DQ30[12]
_
M
_
A_DQ31[12]
M
B_DQ16[13]
_
M
_
B_DQ17[13]
M
B_DQ18[13]
_
M
_
B_DQ19[13]
M
_
B_DQ20[13]
M
B_DQ21[13]
_
M
_
B_DQ22[13]
M
B_DQ23[13]
_
M
_
B_DQ24[13]
M
B_DQ25[13]
_
M
B_DQ26[13]
_
M
_
B_DQ27[13]
M
B_DQ28[13]
_
M
_
B_DQ29[13]
M
B_DQ30[13]
_
M
_
B_DQ31[13]
M
DQ Bit Swapping is allowed w ithin the same byte, and Byte Swapping is allowed within t he same channel.
Clock (CLK and CLK#) and Str obe (DQS and DQS#) differentia l signal swapping within a p air is not allowed. Also dif ferential
clock pair to clock pair swa pping within a channel is not allowed.
_
A_DQ1
M
_
A_DQ2
M
A_DQ3
_
M
_
A_DQ4
M
A_DQ5
_
M
_
A_DQ6
M
A_DQ7
_
M
A_DQ8
_
M
_
A_DQ9
M
A_DQ10
_
M
_
A_DQ11
M
A_DQ12
_
M
_
A_DQ13
M
_
A_DQ14
M
A_DQ15
_
M
_
B_DQ0
M
B_DQ1
_
M
_
B_DQ2
M
_
B_DQ3
M
B_DQ4
_
M
_
B_DQ5
M
B_DQ6
_
M
_
B_DQ7
M
B_DQ8
_
M
_
B_DQ9
M
_
B_DQ10
M
B_DQ11
_
M
_
B_DQ12
M
B_DQ13
_
M
_
B_DQ14
M
_
B_DQ15
M
A_DQ16
_
M
_
A_DQ17
M
A_DQ18
_
M
_
A_DQ19
M
_
A_DQ20
M
A_DQ21
_
M
_
A_DQ22
M
A_DQ23
_
M
_
A_DQ24
M
A_DQ25
_
M
_
A_DQ26
M
_
A_DQ27
M
A_DQ28
_
M
_
A_DQ29
M
A_DQ30
_
M
_
A_DQ31
M
_
B_DQ16
M
B_DQ17
_
M
_
B_DQ18
M
B_DQ19
_
M
_
B_DQ20
M
_
B_DQ21
M
B_DQ22
_
M
_
B_DQ23
M
B_DQ24
_
M
_
B_DQ25
M
B_DQ26
_
M
_
B_DQ27
M
_
B_DQ28
M
B_DQ29
_
M
_
B_DQ30
M
B_DQ31
_
M
AN68
AN69
AL70
AL69
AN70
AN71
AR70
AR68
AU71
AU68
AR71
AR69
AU70
AU69
AF65
AF64
AK65
AK64
AF66
AF67
AK67
AK66
AF70
AF68
AH71
AH68
AF71
AF69
AH70
AH69
BB65
AW65
AW63
AY63
BA65
AY65
BA63
BB63
BA61
AW61
BB59
AW59
BB61
AY61
BA59
AY59
AT66
AU66
AP65
AN65
AN66
AP66
AT65
AU65
AT61
AU61
AP60
AN60
AN61
AP61
AT60
AU60
AL68
SKYLAKE-U-GP
D
R0_DQ[0]
D
R0_DQ[1]
D
D
D
R0_DQ[2]
D
D
R0_DQ[3]
D
R0_DQ[4]
D
D
D
R0_DQ[5]
D
R0_DQ[6]
D
D
D
R0_DQ[7]
D
D
R0_DQ[8]
D
R0_DQ[9]
D
D
D
R0_DQ[10]
D
R0_DQ[11]
D
D
D
R0_DQ[12]
D
D
R0_DQ[13]
D
R0_DQ[14]
D
D
D
R0_DQ[15]
D
R1_DQ[0]/DDR0_DQ[8]
D
D
D
R1_DQ[1]/DDR0_DQ[9]
D
R1_DQ[2]/DDR0_DQ[10]
D
D
D
R1_DQ[3]/DDR0_DQ[11]
D
D
R1_DQ[4]/DDR0_DQ[12]
D
R1_DQ[5]/DDR0_DQ[13]
D
D
D
R1_DQ[6]/DDR0_DQ[14]
D
R1_DQ[7]/DDR0_DQ[15]
D
D
D
R1_DQ[8]/DDR0_DQ[24]
D
D
R1_DQ[9]/DDR0_DQ[25]
D
R1_DQ[10]/DDR0_DQ[26]
D
D
D
R1_DQ[11]/DDR0_DQ[27]
D
R1_DQ[12]/DDR0_DQ[28]
D
D
D
R1_DQ[13]/DDR0_DQ[29]
D
R1_DQ[14]/DDR0_DQ[30]
D
D
R1_DQ[15]/DDR0_DQ[31]
D
D
D
R0_DQ[16]/DDR0_DQ[32]
D
R0_DQ[17]/DDR0_DQ[33]
D
D
D
R0_DQ[18]/DDR0_DQ[34]
D
R0_DQ[19]/DDR0_DQ[35]
D
D
D
R0_DQ[20]/DDR0_DQ[36]
D
D
R0_DQ[21]/DDR0_DQ[37]
D
R0_DQ[22]/DDR0_DQ[38]
D
D
D
R0_DQ[23]/DDR0_DQ[39]
D
R0_DQ[24]/DDR0_DQ[40]
D
D
D
R0_DQ[25]/DDR0_DQ[41]
D
D
R0_DQ[26]/DDR0_DQ[42]
D
R0_DQ[27]/DDR0_DQ[43]
D
D
D
R0_DQ[28]/DDR0_DQ[44]
D
R0_DQ[29]/DDR0_DQ[45]
D
D
D
R0_DQ[30]/DDR0_DQ[46]
D
R0_DQ[31]/DDR0_DQ[47]
D
D
D
R1_DQ[16]/DDR0_DQ[48]
D
D
R1_DQ[17]/DDR0_DQ[49]
D
R1_DQ[18]/DDR0_DQ[50]
D
D
D
R1_DQ[19]/DDR0_DQ[51]
D
R1_DQ[20]/DDR0_DQ[52]
D
D
D
R1_DQ[21]/DDR0_DQ[53]
D
D
R1_DQ[22]/DDR0_DQ[54]
D
R1_DQ[23]/DDR0_DQ[55]
D
D
D
R1_DQ[24]/DDR0_DQ[56]
D
R1_DQ[25]/DDR0_DQ[57]
D
D
D
R1_DQ[26]/DDR0_DQ[58]
D
D
R1_DQ[27]/DDR0_DQ[59]
D
R1_DQ[28]/DDR0_DQ[60]
D
D
D
R1_DQ[29]/DDR0_DQ[61]
D
R1_DQ[30]/DDR0_DQ[62]
D
D
D
R1_DQ[31]/DDR0_DQ[63]
D
SKYLAKE_ULT
D
DR0_DQ[16]
D
D
DDR0_DQ[17]
D
DDR0_DQ[18]
D
DDR0_DQ[19]
D
DDR0_DQ[20]
D
DDR0_DQ[21]
R0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
D
D
DDR0_DQ[22]
D
R0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
D
DDR0_DQ[23]
D
D
D
D
R0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
D
D
D
D
D
D
D
D
D
D
R0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
D
D
D
D
DDR CH - A
D
R0_MA[5]/DDR0_CAA[0]/DDR0_MA[ 5]
R0_MA[9]/DDR0_CAA[1]/DDR0_MA[ 9]
D
D
R0_MA[6]/DDR0_CAA[2]/DDR0_MA[ 6]
R0_MA[8]/DDR0_CAA[3]/DDR0_MA[ 8]
D
D
R0_MA[7]/DDR0_CAA[4]/DDR0_MA[ 7]
D
R0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
R0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
R0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
R0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
R0_WE#/DDR0_CAB[2]/DD R0_MA[14]
D
R0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
R0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
D
R0_MA[2]/DDR0_CAB[5]/DDR0_MA[ 2]
D
D
R0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
D
R0_MA[1]/DDR0_CAB[8]/DDR0_MA[ 1]
R0_MA[0]/DDR0_CAB[9]/DDR0_MA[ 0]
D
D
D
D
D
D
D
D
D
R0_DQSN[2]/DDR0_DQSN[4]
D
D
D
R0_DQSP[2]/DDR0_DQSP[4]
D
D
R0_DQSN[3]/DDR0_DQSN[5]
D
R0_DQSP[3]/DDR0_DQSP[5]
D
D
D
R1_DQSN[2]/DDR0_DQSN[6]
D
R1_DQSP[2]/DDR0_DQSP[6]
D
D
D
R1_DQSN[3]/DDR0_DQSN[7]
D
D
R1_DQSP[3]/DDR0_DQSP[7]
D
PDG: DDR/ODT
OF 20
2
D
R0_CKN[0]
D
R0_CKP[0]
D
D
D
R0_CKN[1]
D
D
R0_CKP[1]
D
D
R0_CKE[0]
D
R0_CKE[1]
D
D
D
R0_CKE[2]
D
D
R0_CKE[3]
D
D
R0_CS#[0]
D
R0_CS#[1]
D
D
D
R0_ODT[0]
D
D
R0_ODT[1]
D
D
R0_MA[3]
D
D
R0_MA[4]
D
D
R0_DQSN[0]
D
R0_DQSP[0]
D
D
D
R0_DQSN[1]
D
D
R0_DQSP[1]
D
R1_DQSN[0]/DDR0_DQ[2]
R1_DQSP[0]/DDR0_DQ[2]
R1_DQSN[1]/DDR0_DQ[3]
R1_DQSP[1]/DDR0_DQ[3]
D
R0_ALERT#
D
R0_PAR
D
D
D
R_VREF_CA
D
R0_VREF_DQ
D
D
D
R1_VREF_DQ
D
D
R_VTT_CNTL
D
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
AM69
AT69
AT70
AH66
AH65
AG69
AG70
BA64
AY64
AY60
BA60
AR66
AR65
AR61
AR60
AW50
AT52
AY67
AY68
BA67
AW67
A_A5
_
M
_
A_A9
M
A_A6
_
M
_
A_A8
M
_
A_A7
M
_
A_A12
M
A_A11
_
M
_
A_A13
M
A_A15
_
M
_
A_A14
M
A_A16
_
M
_
A_A2
M
_
A_A10
M
A_A1
_
M
_
A_A0
M
_
A_A3
M
A_A4
_
M
A_DQS_DN0
_
M
_
A_DQS_DP0
M
A_DQS_DN1
_
M
_
A_DQS_DP1
M
_
B_DQS_DN0
M
B_DQS_DP0
_
M
_
B_DQS_DN1
M
B_DQS_DP1
_
M
_
A_DQS_DN2
M
_
A_DQS_DP2
M
A_DQS_DN3
_
M
_
A_DQS_DP3
M
B_DQS_DN2
_
M
_
B_DQS_DP2
M
_
B_DQS_DN3
M
B_DQS_DP3
_
M
S
_PGCNTL
M
_
A_CLK#0 [12]
M
A_CLK0 [12]
_
M
_
A_CLK#1 [12]
M
_
A_CLK1 [12]
M
_
A_CKE0 [12]
M
A_CKE1 [12]
_
M
_
A_CS#0 [12]
M
A_CS#1 [12]
_
M
_
A_DIMA_ODT0 [12]
M
A_DIMA_ODT1 [12]
_
M
M
M
M
M
M
_
M
_
M
_
M
A_ACT_N [12]
_
M
_
A_BG1 [12]
M
_
M
_
M
_
M
_
M
_
M
M
_
M
_
M
M
M
M
M
M_A_DQS0
M_A_DQS1
M_B_DQS0
M_B_DQS1
M_A_DQS2
M_A_DQS3
M_B_DQS2
M_B_DQS3
M
M
V
V
_
A_A5 [12]
A_A9 [12]
_
_
A_A6 [12]
_
A_A8 [12]
A_A7 [12]
_
A_BG0 [12]
A_A12 [12]
A_A11 [12]
A_A13 [12]
A_A15 [12]
A_A14 [12]
A_A16 [12]
A_BA0 [12]
A_A2 [12]
_
A_BA1 [12]
A_A10 [12]
_A_A1 [12]
_
A_A0 [12]
A_A3 [12]
_
_
A_A4 [12]
A_ALERT_N [12]
_
_
A_PARITY [12]
SM_VREF_CNTA [ 12]
_
SM_VREF_CNTB [ 13]
_
M_A_DQ[32:39]
M_A_DQ[40:47]
M_B_DQ[32:39]
M_B_DQ[40:47]
M_A_DQ[48:55]
M_A_DQ[56:63]
M_B_DQ[48:55]
M_B_DQ[56:63]
M
A_DQ33[12]
_
M
_
A_DQ34[12]
M
A_DQ35[12]
_
M
_
A_DQ36[12]
M
_
A_DQ37[12]
M
A_DQ38[12]
_
M
_
A_DQ39[12]
M
A_DQ40[12]
_
M
_
A_DQ41[12]
M
A_DQ42[12]
_
M
_
A_DQ43[12]
M
_
A_DQ44[12]
M
A_DQ45[12]
_
M
_
A_DQ46[12]
M
A_DQ47[12]
_
M
_
B_DQ32[13]
M
B_DQ33[13]
_
M
_
B_DQ34[13]
M
_
B_DQ35[13]
M
B_DQ36[13]
_
M
_
B_DQ37[13]
M
B_DQ38[13]
_
M
_
B_DQ39[13]
M
_
B_DQ40[13]
M
B_DQ41[13]
_
M
_
B_DQ42[13]
M
B_DQ43[13]
_
M
_
B_DQ44[13]
M
_
B_DQ45[13]
M
B_DQ46[13]
_
M
_
B_DQ47[13]
M
A_DQ48[12]
_
M
_
A_DQ49[12]
M
_
A_DQ50[12]
M
A_DQ51[12]
_
M
_
A_DQ52[12]
M
A_DQ53[12]
_
M
_
A_DQ54[12]
M
A_DQ55[12]
_
M
A_DQ56[12]
_
M
_
A_DQ57[12]
M
A_DQ58[12]
_
M
_
A_DQ59[12]
M
A_DQ60[12]
_
M
_
A_DQ61[12]
M
_
A_DQ62[12]
M
A_DQ63[12]
_
M
_
B_DQ48[13]
M
B_DQ49[13]
_
M
_
B_DQ50[13]
M
B_DQ51[13]
_
M
_
B_DQ52[13]
M
_
B_DQ53[13]
M
B_DQ54[13]
_
M
_
B_DQ55[13]
M
B_DQ56[13]
_
M
_
B_DQ57[13]
M
B_DQ58[13]
_
M
B_DQ59[13]
_
M
_
B_DQ60[13]
M
B_DQ61[13]
_
M
_
B_DQ62[13]
M
B_DQ63[13]
_
M
D
2V_S3
1
_PGCNTL
M
S
G
S
PJA138KA-GP
A_DQ33
_
M
_
A_DQ34
M
_
A_DQ35
M
A_DQ36
_
M
_
A_DQ37
M
A_DQ38
_
M
_
A_DQ39
M
A_DQ40
_
M
A_DQ41
_
M
_
A_DQ42
M
A_DQ43
_
M
_
A_DQ44
M
A_DQ45
_
M
_
A_DQ46
M
_
A_DQ47
M
B_DQ32
_
M
_
B_DQ33
M
B_DQ34
_
M
_
B_DQ35
M
_
B_DQ36
M
B_DQ37
_
M
_
B_DQ38
M
B_DQ39
_
M
_
B_DQ40
M
B_DQ41
_
M
_
B_DQ42
M
_
B_DQ43
M
B_DQ44
_
M
_
B_DQ45
M
B_DQ46
_
M
_
B_DQ47
M
_
A_DQ48
M
A_DQ49
_
M
_
A_DQ50
M
A_DQ51
_
M
_
A_DQ52
M
_
A_DQ53
M
A_DQ54
_
M
_
A_DQ55
M
A_DQ56
_
M
_
A_DQ57
M
A_DQ58
_
M
_
A_DQ59
M
_
A_DQ60
M
A_DQ61
_
M
_
A_DQ62
M
A_DQ63
_
M
_
B_DQ48
M
_
B_DQ49
M
B_DQ50
_
M
_
B_DQ51
M
B_DQ52
_
M
_
B_DQ53
M
_
B_DQ54
M
B_DQ55
_
M
_
B_DQ56
M
B_DQ57
_
M
_
B_DQ58
M
B_DQ59
_
M
_
B_DQ60
M
_
B_DQ61
M
B_DQ62
_
M
_
B_DQ63
M
01
5
Q
D
_
A_DQ32
M
_
A_DQ32[12]
AY39
AW39
AY37
AW37
BB39
BA39
BA37
BB37
AY35
AW35
AY33
AW33
BB35
BA35
BA33
BB33
AU40
AT40
AT37
AU37
AR40
AP40
AP37
AR37
AT33
AU33
AU30
AT30
AR33
AP33
AR30
AP30
AY31
AW31
AY29
AW29
BB31
BA31
BA29
BB29
AY27
AW27
AY25
AW25
BB27
BA27
BA25
BB25
AU27
AT27
AT25
AU25
AP27
AN27
AN25
AP25
AT22
AU22
AU21
AT21
AN22
AP22
AP21
AN21
D
3V_S0
3
12
P
U1C
C
R0_DQ[32]/DDR1_DQ[0]
D
D
D
R0_DQ[33]/DDR1_DQ[1]
D
R0_DQ[34]/DDR1_DQ[2]
D
D
D
R0_DQ[35]/DDR1_DQ[3]
D
D
R0_DQ[36]/DDR1_DQ[4]
D
R0_DQ[37]/DDR1_DQ[5]
D
D
D
R0_DQ[38]/DDR1_DQ[6]
D
R0_DQ[39]/DDR1_DQ[7]
D
D
D
R0_DQ[40]/DDR1_DQ[8]
D
D
R0_DQ[41]/DDR1_DQ[9]
D
R0_DQ[42]/DDR1_DQ[10]
D
D
D
R0_DQ[43]/DDR1_DQ[11]
D
R0_DQ[44]/DDR1_DQ[12]
D
D
D
R0_DQ[45]/DDR1_DQ[13]
D
D
R0_DQ[46]/DDR1_DQ[14]
D
R0_DQ[47]/DDR1_DQ[15]
D
D
D
R1_DQ[32]/DDR1_DQ[16]
D
R1_DQ[33]/DDR1_DQ[17]
D
D
D
R1_DQ[34]/DDR1_DQ[18]
D
R1_DQ[35]/DDR1_DQ[19]
D
D
D
R1_DQ[36]/DDR1_DQ[20]
D
D
R1_DQ[37]/DDR1_DQ[21]
D
R1_DQ[38]/DDR1_DQ[22]
D
D
D
R1_DQ[39]/DDR1_DQ[23]
D
R1_DQ[40]/DDR1_DQ[24]
D
D
D
R1_DQ[41]/DDR1_DQ[25]
D
D
R1_DQ[42]/DDR1_DQ[26]
D
R1_DQ[43]/DDR1_DQ[27]
D
D
D
R1_DQ[44]/DDR1_DQ[28]
D
R1_DQ[45]/DDR1_DQ[29]
D
D
D
R1_DQ[46]/DDR1_DQ[30]
D
R1_DQ[47]/DDR1_DQ[31]
D
D
R0_DQ[48]/DDR1_DQ[32]
D
D
D
R0_DQ[49]/DDR1_DQ[33]
D
R0_DQ[50]/DDR1_DQ[34]
D
D
D
R0_DQ[51]/DDR1_DQ[35]
D
R0_DQ[52]/DDR1_DQ[36]
D
D
D
R0_DQ[53]/DDR1_DQ[37]
D
D
R0_DQ[54]/DDR1_DQ[38]
D
R0_DQ[55]/DDR1_DQ[39]
D
D
D
R0_DQ[56]/DDR1_DQ[40]
D
R0_DQ[57]/DDR1_DQ[41]
D
D
D
R0_DQ[58]/DDR1_DQ[42]
D
D
R0_DQ[59]/DDR1_DQ[43]
D
R0_DQ[60]/DDR1_DQ[44]
D
D
D
R0_DQ[61]/DDR1_DQ[45]
D
R0_DQ[62]/DDR1_DQ[46]
D
D
D
R0_DQ[63]/DDR1_DQ[47]
D
R1_DQ[48]
D
D
D
R1_DQ[49]
D
D
R1_DQ[50]
D
R1_DQ[51]
D
D
D
R1_DQ[52]
D
R1_DQ[53]
D
D
D
R1_DQ[54]
D
D
R1_DQ[55]
D
R1_DQ[56]
D
D
D
R1_DQ[57]
D
R1_DQ[58]
D
D
D
R1_DQ[59]
D
D
R1_DQ[60]
D
R1_DQ[61]
D
D
D
R1_DQ[62]
D
R1_DQ[63]
D
D
SKYLAKE-U-GP
06
5
R
220KR2F-GP
_PGCNTL_R [51]
M
S
SKYLAKE_ULT
R1_MA[5]/DDR1_CAA[0]/DDR1_MA[ 5]
D
D
D
R1_MA[9]/DDR1_CAA[1]/DDR1_MA[ 9]
D
R1_MA[6]/DDR1_CAA[2]/DDR1_MA[ 6]
D
D
D
R1_MA[8]/DDR1_CAA[3]/DDR1_MA[ 8]
D
R1_MA[7]/DDR1_CAA[4]/DDR1_MA[ 7]
D
D
D
R1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
D
D
R1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
D
R1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
D
D
D
R1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
D
R1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
D
D
D
R1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
D
R1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
D
D
D
R1_WE#/DDR1_CAB[2]/DD R1_MA[14]
D
R1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
D
D
D
R1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
D
R1_MA[2]/DDR1_CAB[5]/DDR1_MA[ 2]
D
D
R1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
D
D
D
R1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
D
R1_MA[1]/DDR1_CAB[8]/DDR1_MA[ 1]
D
D
D
R1_MA[0]/DDR1_CAB[9]/DDR1_MA[ 0]
D
R0_DQSN[4]/DDR1_DQSN[0]
D
D
D
R0_DQSP[4]/DDR1_DQSP[0]
D
R0_DQSN[5]/DDR1_DQSN[1]
D
D
D
R0_DQSP[5]/DDR1_DQSP[1]
D
D
R1_DQSN[4]/DDR1_DQSN[2]
D
R1_DQSP[4]/DDR1_DQSP[2]
D
D
D
R1_DQSN[5]/DDR1_DQSN[3]
D
R1_DQSP[5]/DDR1_DQSP[3]
D
D
D
R0_DQSN[6]/DDR1_DQSN[4]
D
R0_DQSP[6]/DDR1_DQSP[4]
D
D
D
R0_DQSN[7]/DDR1_DQSN[5]
D
D
R0_DQSP[7]/DDR1_DQSP[5]
D
DDR CH - B
Design Guideline:
SM_RCOMP keep routing length less than 500 mils.
D
D
D
D
D
D
D
D
D
D
D
D
D
R1_CKN[0]
D
D
R1_CKN[1]
R1_CKP[0]
D
D
D
R1_CKP[1]
D
R1_CKE[0]
D
D
D
R1_CKE[1]
D
R1_CKE[2]
D
D
D
R1_CKE[3]
D
R1_CS#[0]
D
D
D
R1_CS#[1]
D
R1_ODT[0]
D
D
R1_ODT[1]
D
D
D
D
R1_DQSN[6]
D
D
R1_DQSP[6]
R1_DQSN[7]
D
D
R1_DQSP[7]
R1_ALERT#
D
D
AM_RESET#
R
D
R_RCOMP[0]
D
R_RCOMP[1]
R_RCOMP[2]
D
OF 20
3
R1_MA[3]
R1_MA[4]
D
R1_PAR
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
BA38
AY38
AY34
BA34
AT38
AR38
AT32
AR32
BA30
AY30
AY26
BA26
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
_
M
M
S
M
S
M
S
M
S
#543016
B_A5
B_A9
B_A6
B_A8
B_A7
B_A12
B_A11
B_ACT_N
B_A13
B_A15
B_A14
B_A16
B_A2
B_A10
B_A1
B_A0
B_A3
B_A4
A_DQS_DN4
A_DQS_DP4
A_DQS_DN5
A_DQS_DP5
B_DQS_DN4
B_DQS_DP4
B_DQS_DN5
B_DQS_DP5
A_DQS_DN6
A_DQS_DP6
A_DQS_DN7
A_DQS_DP7
B_DQS_DN6
B_DQS_DP6
B_DQS_DN7
B_DQS_DP7
_DRAMRST#
_RCOMP_0
_RCOMP_1
_RCOMP_2
B_CLK#0 [13]
_
M
_
B_CLK#1 [13]
M
B_CLK0 [13]
_
M
_
B_CLK1 [13]
M
B_CKE0 [13]
_
M
_
B_CKE1 [13]
M
_B_CS#0 [13]
M
_
B_CS#1 [13]
M
B_DIMB_ODT0 [13]
_
M
_
B_DIMB_ODT1 [13]
M
B_A5 [13]
_
M
_
B_A9 [13]
M
B_A6 [13]
_
M
_
B_A8 [13]
M
_
B_A7 [13]
M
_
B_BG0 [13]
M
_
B_A12 [13]
M
B_A11 [13]
_
M
_
B_ACT_N [13]
M
B_BG1 [13]
_
M
_
B_A13 [13]
M
B_A15 [13]
_
M
_
B_A14 [13]
M
_
B_A16 [13]
M
_
B_BA0 [13]
M
_
B_A2 [13]
M
_
B_BA1 [13]
M
_
B_A10 [13]
M
B_A1 [13]
_
M
_B_A0 [13]
M
_
B_A3 [13]
M
B_A4 [13]
_
M
M_A_DQS4
M_A_DQS5
M_B_DQS4
M_B_DQS5
M_A_DQS6
M_A_DQS7
M_B_DQS6
M_B_DQS7
_
M
_
M
1 2
01 121R2F -GP
5
R
1 2
5
02 80D6R2 F-L-GP
R
1 2
5
03 100R2F -L1-GP-U
R
Layout Note:
1
B_ALERT_N [13]
B_PARITY [13]
2V_S3
D
12
5
05
R
470R2F-GP
1 2
close to CPU
1 2
5
04
R
0R0402-PAD
D
501
E
AZ5725-01FDR7G-GP
D
R4_DRAMRST# [12,13]
D
2015/11/18 Modify
A_DQS_DN[7:0] [12]
_
A_DQS_DN0
_
M
_
A_DQS_DN1
M
A_DQS_DN2
_
M
_
A_DQS_DN3
M
A_DQS_DN4
_
M
_
A_DQS_DN5
M
_
A_DQS_DN6
M
A_DQS_DN7
_
M
_
A_DQS_DP0
M
_
A_DQS_DP1
M
A_DQS_DP2
_
M
_
A_DQS_DP3
A A
5
4
M
A_DQS_DP4
_
M
_
A_DQS_DP5
M
_
A_DQS_DP6
M
_
A_DQS_DP7
M
3
M
_
A_DQS_DP[7:0] [12]
M
2
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
_
B_DQS_DN0
B_DQS_DN1
_
_
B_DQS_DN2
B_DQS_DN3
_
_
B_DQS_DN4
B_DQS_DN5
_
_
B_DQS_DN6
_
B_DQS_DN7
B_DQS_DP0
_
_
B_DQS_DP1
B_DQS_DP2
_
_
B_DQS_DP3
_
B_DQS_DP4
B_DQS_DP5
_
_
B_DQS_DP6
B_DQS_DP7
_
B_DQS_DN[7:0] [13]
_
M
_
B_DQS_DP[7:0] [13]
M
<Core Design>
<Core Design>
<Core Design>
stron Corporation
stron Corporation
stron Corporation
i
i
i
W
W
W
1
1
1
F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2
2
2
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
i
tle
Title
Title
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
2
2
2
A
A
A
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
U_(DDR)
U_(DDR)
U_(DDR)
P
P
P
C
C
C
arlord KBL-R
arlord KBL-R
arlord KBL-R
t
t
t
S
S
S
1
5 1
5 1
5 1
f
f
f
o
o
o
0
0
0
A
A
A
06Friday, December 08, 2017
06Friday, December 08, 2017
06Friday, December 08, 2017
0
0
0
5
WWW.AliSaler.Com
4
3
2
1
Main Func = CPU
PU
1S
C
D D
C C
PCH strap pin:
FG
3
C
C
B B
12
60
R
1KR2J-1-GP
DY
4
FG
12
60
R
1KR2J-1-GP
P6
T
P6
T
P6
T
P6
T
P6
T
P6
T
P6
T
P6
T
P6
T
P6
T
P6
T
P6
T
P6
T
P6
T
P6
T
P6
T
P6
T
P6
T
P6
T
P6
T
P6
T
01TPAD14-OP-GP
P6
T
P6
02TPAD14-OP-GP
T
P6
12TPAD14-OP-GP
T
P6
13TPAD14-OP-GP
T
[BDW Only]PHYSICAL_DEBUG_ENA BLED (DFX PRIVACY)
4
CFG[3]
(#543016)
DISPLAY PORT PRESENCE STRAP
5
CFG[4]
0
FG
18TPAD14-OP-GP
1
C
FG
1
19TPAD14-OP-GP
1
C
2
FG
20TPAD14-OP-GP
1
C
FG
3
21TPAD14-OP-GP
1
C
FG
4
22TPAD14-OP-GP
1
C
5
FG
23TPAD14-OP-GP
1
C
FG
6
24TPAD14-OP-GP
1
C
7
FG
25TPAD14-OP-GP
1
C
FG
8
26TPAD14-OP-GP
1
C
9
FG
27TPAD14-OP-GP
1
C
FG
10
28TPAD14-OP-GP
1
C
FG
11
29TPAD14-OP-GP
1
C
12
FG
30TPAD14-OP-GP
1
C
FG
13
31TPAD14-OP-GP
1
C
14
FG
32TPAD14-OP-GP
1
C
FG
15
33TPAD14-OP-GP
1
C
16
FG
34TPAD14-OP-GP
1
C
FG
17
35TPAD14-OP-GP
1
C
FG
18
36TPAD14-OP-GP
1
C
19
FG
37TPAD14-OP-GP
1
C
FG
C
149D9R2F-GP
60
12
R
TP
_PMODE
I
38TPAD14-OP-GP
1
SV
R
1
SV
R
1
SV
R
1
SV
R
1
0 : ENABLED
SET DFX ENABLED BIT IN DEBU G INTERFACE MSR
1 : DISABLED
0 : ENABLED
An external Display Port dev ice is connected to the Embedd ed Display Port.
1 : DISABLED (Default)
No Physical Display Port att ached to Embedded DisplayPort* . No connect for disable.
_RCOMP
D_TP_BA70
D_TP_BA68
D_F65
D_G65
E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
E8
AY2
AY1
D1
D3
K46
K45
AL25
AL27
C71
B70
F60
A52
BA70
BA68
J71
J68
F65
G65
F61
E61
[0]
FG
C
FG
[1]
C
FG
[2]
C
[3]
FG
C
FG
[4]
C
[5]
FG
C
FG
[6]
C
[7]
FG
C
FG
[8]
C
FG
[9]
C
[10]
FG
C
FG
[11]
C
[12]
FG
C
FG
[13]
C
FG
[14]
C
[15]
FG
C
[16]
FG
C
FG
[17]
C
[18]
FG
C
FG
[19]
C
FG
_RCOMP
C
TP
_PMODE
I
D_AY2
SV
R
SV
D_AY1
R
SV
D_D1
R
SV
D_D3
R
SV
D_K46
R
D_K45
SV
R
D_AL25
SV
R
D_AL27
SV
R
D_C71
SV
R
SV
D_B70
R
SV
D_F60
R
D_A52
SV
R
D_TP_BA70
SV
R
SV
D_TP_BA68
R
D_J71
SV
R
SV
D_J68
R
SS
_F65
V
_G65
SS
V
SV
D_F61
R
D_E61
SV
R
SKYLAKE-U-GP
RESERVED SIGNALS-1
SKYLAKE_ULT
SVD_TP_AW71
R
RSVD_TP_AW70
R
R
R
R
P
SV
SV
SV
SV
R
R
R
R
R
R
R
R
R
R
R
R
C_SELECT#
RO
9 OF 20
1
D_TP_BB68
D_TP_BB69
D_TP_AK13
D_TP_AK12
SV
D_BB2
D_BA3
SV
SV
D_D5
R
D_D4
SV
R
SV
D_B2
R
D_C2
SV
R
SV
D_B3
R
D_A3
SV
R
D_AW1
SV
D_E1
SV
R
SV
D_E2
R
D_BA4
SV
SV
D_BB4
SV
D_A4
R
SV
D_C4
R
SV
D_A69
R
D_B69
SV
R
SV
D_AY3
SV
D_D71
D_C70
SV
SV
D_C54
D_D54
SV
_AY71
SS
V
Z
SV
D_AW71
D_AW70
SV
M
SV
D_TP_BB68
BB68
R
D_TP_BB69
SV
BB69
R
AK13
AK12
BB2
BA3
P5
_AU5
U5
A
T
P5
T
T
T
T
T
VM
SM
_AT5
P6
A
T5
T
P6
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
_BB5
P4
T
B
B5
P4
A69
B69
AY3
D71
C70
C54
D54
P1
_AY4
T
Y4
A
P1
_BB3
P2
T
B
B3
P2
SS
_AY71
V
AY71
AR56
VM
#
Z
#
D_TP_AW71
SV
R
AW71
SV
D_TP_AW70
R
AW70
AP56
SM
M
#
C64
RO
P
1 2
#
C_SELECT#
60
2
R
0R0402-PAD
1
1
1
1
1
1
1
1
1
1
1
1 2
60
3
R
100KR2J-1-GP
03 TPAD14-OP-GP
P6
T
P6
04 TPAD14-OP-GP
T
07 TPAD14-OP-GP
P6
T
P6
08 TPAD14-OP-GP
T
P6
09 TPAD14-OP-GP
T
10 TPAD14-OP-GP
P6
T
P6
11 TPAD14-OP-GP
T
P6
T
P6
14 TPAD14-OP-GP
T
P6
15 TPAD14-OP-GP
T
P6
17 TPAD14-OP-GP
T
DY
16 TPAD14-OP-GP
#54469 CRB.
Vince,20161027
VC
CST_CPU
+
2016/01/11 modify
SKL(#543016):
Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*
A A
<Core Design>
<Core Design>
<Core Design>
tron Corporation
tron Corporation
tron Corporation
is
is
is
W
W
W
1F
1F
1F
, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
2
2
2
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
_(RESERVED)
_(RESERVED)
_(RESERVED)
PU
PU
PU
C
C
C
rlord KBL-R
rlord KBL-R
rlord KBL-R
ta
ta
ta
S
S
S
1
6 10
6 10
6 10
f
f
f
o
o
o
A
A
A
5
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
2
2
2
A
A
A
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
00
00
00
6Friday, December 08, 2017
6Friday, December 08, 2017
6Friday, December 08, 2017
SSID = CPU
5
4
3
2
1
CCGT
V
+
CCSTG
V
+
CGT_SENSE[46]
C
V
S
SGT_SENSE[46]
V
For U22 & U42
T
_CORE
G
V
CCGT
+
T
_CORE
G
V
CCGT
+
T
_CORE
G
7
12
R
22_POWER_K52
U
12
DY
V
CCGT
+
0R2J-2-GP
22 only
U
C
U1M
P
CPU POWER 2 OF 4
A48
CCGT
A53
C
CGT
V
A58
CGT
C
V
A62
C
CGT
V
A66
CGT
C
V
AA63
C
CGT
V
AA64
CGT
C
V
AA66
C
CGT
V
AA67
CGT
C
V
AA69
C
CGT
V
AA70
CGT
C
V
AA71
CCGT
V
AC64
C
CGT
V
AC65
CGT
C
V
AC66
CGT
C
V
AC67
CCGT
V
AC68
C
CGT
V
AC69
CGT
C
V
AC70
C
CGT
V
AC71
CGT
C
V
J43
C
CGT
V
J45
CGT
C
V
J46
CCGT
V
J48
CGT
C
V
J50
C
CGT
V
J52
CGT
C
V
J53
CCGT
V
J55
C
CGT
V
J56
CGT
C
V
J58
C
CGT
V
J60
CGT
C
V
K48
C
CGT
V
K50
CGT
C
V
K52
C
CGT
V
K53
CGT
C
V
K55
C
CGT
V
K56
CGT
C
V
K58
CCGT
V
K60
C
CGT
V
L62
CGT
C
V
L63
C
CGT
V
L64
CCGT
V
L65
C
CGT
V
L66
CGT
C
V
L67
C
CGT
V
L68
CGT
C
V
L69
C
CGT
V
L70
CGT
C
V
L71
CCGT
V
M62
CGT
C
V
N63
C
CGT
V
N64
CGT
C
V
N66
CCGT
V
N67
C
CGT
V
N69
V
CGT
C
V
J70
CGT_SE NSE
C
J69
V
S
SGT_SE NSE
V
SKYLAKE-U-GP
D
2V_S3
1
SKYLAKE_ULT
C
S
V
V
V
CSTG_G 20
C
V
C
CC_G33
V
C
V
C
V
C
V
C
V
C
V
C
V
C
V
C
V
C
V
C
V
CC_K35
V
C
V
C
V
C
V
CC_K42
V
C
V
V
C_SENSE
S_SENSE
DALERT #
I
DSOUT
I
V
1
C_G32
C_G35
C_G37
C_G38
C_G40
C_G42
C_K33
C_K37
C_K38
C_K40
C_K43
IDSCK
V
2 OF 20
C_J30
C_J33
C_J37
C_J40
C
C_CORE
V
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
_
CPU_SVIDALRT#
H
_
CPU_SVIDCLK
H
CPU_SVIDDAT
_
H
V
CCFUSEPRG
+
C_SENSE [46]
C
V
S
S_SENSE [46]
V
1 2
0R0603-PAD
7
03
R
C
C
C_CORE
V
D D
701TPAD14-OP-GP
CCCOREG0
P
V
1
T
+
707TPAD14-OP-GP
CCCOREG1
P
V
1
T
+
Vince,20161012
Vince,20161012
C C
A30
A34
A39
A44
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AM32
AM33
AM35
AM37
AM38
G30
K32
AK32
AB62
P62
V62
H63
G61
AC63
AE63
AE62
AG62
AL63
AJ62
U1L
P
C_A30
C
CC_A34
V
C
C_A39
V
C_A44
C
V
C
C_AK33
V
C_AK35
C
V
C
C_AK37
V
C_AK38
C
V
C
C_AK40
V
C_AL33
C
V
C
C_AL37
V
C_AL40
C
V
CC_AM32
V
C
C_AM33
V
C_AM35
C
V
C_AM37
C
V
CC_AM38
V
C
C_G30
V
V
C
CG0
SVD_K32
R
V
C
CG1
RSVD_AK32
V
CCOPC_ AB62
COPC_P 62
C
V
C
COPC_V 62
V
V
CC_OPC _1P8_H6 3
V
C_OPC_ 1P8_G6 1
C
V
COPC_S ENSE
C
S
SOPC_S ENSE
V
V
C
CEOPIO
CEOPIO
C
V
V
CEOPIO _SENSE
C
SSEOPI O_SENSE
V
V
SKYLAKE-U-GP
CPU POWER 1 OF 4
2016/02/16 modify
SKYLAKE_ULT
#544669 CRB.
7
05
R
1 2
0R0805-PAD
CCGTX_ AK42
C
CGTX_A K43
V
CGTX_A K45
C
V
C
CGTX_A K46
V
CGTX_A K48
C
V
C
CGTX_A K50
V
CGTX_A K52
C
V
C
CGTX_A K53
V
CGTX_A K55
C
V
C
CGTX_A K56
V
CGTX_A K58
C
V
CCGTX_ AK60
V
C
CGTX_A K70
V
CGTX_A L43
C
V
C
CGTX_A L46
V
CCGTX_ AL50
V
C
CGTX_A L53
V
CGTX_A L56
C
V
C
CGTX_A L60
V
CGTX_A M48
C
V
C
CGTX_A M50
V
CGTX_A M52
C
V
CCGTX_ AM53
V
CGTX_A M56
C
V
C
CGTX_A M58
V
CGTX_A U58
C
V
CCGTX_ AU63
V
C
CGTX_B B57
V
V
CGTX_B B66
C
V
CGTX_S ENSE
C
V
S
SGTX_S ENSE
V
V
+
3 OF 20
1
CGT
C
CCGT
V
C
CGT
V
CGT
C
V
C
CGT
V
CGT
C
V
C
CGT
V
CGT
C
V
C
CGT
V
CGT
C
V
C
CGT
V
CGT
C
V
CCGT
V
C
CGT
V
CGT
C
V
CGT
C
V
CCGT
V
C
CGT
V
CGT
C
V
C
CGT
V
CGT
C
V
C
CGT
V
CGT
C
V
CCGT
V
CGT
C
V
V
DDQ_CPU_CLK
V
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
CCGT
+
Vince,20170202
T
X_CORE
G
Follow Kyloren 13" SCH
T
X_CORE
G
T
X_CORE
G
For U42 only
C_CORE
C
V
7
07
R
1 2
U42
D0002R5J-GP-U
C
C_CORE
V
08
7
R
1 2
U42
D0002R5J-GP-U
T
_CORE
G
T
X_CORE
G
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
Vince,20170622
CCGT
V
+
7
06
R
1 2
U22
D0002R5J-GP-U
D
2V_S3
1
12
19
7
C
SC1U10V2KX-1GP
DDQ_CPU_CLK
V
+
15SC10U6D3V3MX-GP
7
12
C
V
CCST_CPU
+
16SC1U10V2KX-1GP
7
12
C
V
CCSTG
+
17SC1U10V2KX-1GP
7
12
C
DY
2V_S3
D
1
7
18
12
C
V
CCSFR
+
12
7
20
C
C
C_CORE
V
12
7
19
R
100R2F-L1-GP-U
12
7
20
R
100R2F-L1-GP-U
CCGT
V
+
12
21
7
R
100R2F-L1-GP-U
12
22
7
R
100R2F-L1-GP-U
C
P
U1N
AU23
DQ_AU23
D
AU28
DQ_AU28
D
V
AU35
DDQ_AU3 5
V
AU42
D
DQ_AU42
V
BB23
DQ_BB2 3
D
V
BB32
D
DQ_BB3 2
V
BB41
DQ_BB4 1
D
V
BB47
D
DQ_BB4 7
V
BB51
DQ_BB5 1
D
V
V
AM40
D
DQC
V
A18
CCST
0.04 A
V
A22
CSTG_A 22
C
V
AL23
CPLL_O C
C
V
K20
CPLL_K 20
C
K21
C
CPLL_K 21
V
V
0.12 A
12
7
21
C
S
C
D1U16V2KX-3DLGP
SKYLAKE-U-GP
C_SENSE [46]
C
V
S
S_SENSE [46]
V
Layout Note:
1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE
impedance=50 ohm
3. Length match<25mil
CGT_SENSE [46]
C
V
S
SGT_SENSE [46]
V
CPU POWER 3 OF 4
SKYLAKE_ULT
CIO_SE NSE
C
SSIO_S ENSE
V
V
SSA_SE NSE
S
C
CSA_SE NSE
V
V
V
CCIO
+
4 OF 20
1
CIO
C
CIO
C
V
CCIO
V
C
CIO
V
CIO
C
V
C
CIO
V
CIO
C
V
V
CSA
C
CCSA
V
CSA
C
V
C
CSA
V
CSA
C
V
CCSA
V
C
CSA
V
CSA
C
V
C
CSA
V
CSA
C
V
C
CSA
V
CSA
C
V
C
CSA
V
CSA
C
V
V
CSA_SENSE
C
V
S
SSA_SENSE
V
VCCIO(ICCMAX.=2.73A
+
AK28
AK30
AL30
AL42
AM28
AM30
AM42
V
CCSA
+
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
CCSA
V
+
12
35
7
R
100R2F-L1-GP-U
12
7
34
R
100R2F-L1-GP-U
SSA_SENSE [46]
S
V
C
CSA_SENSE [46]
V
Layout Note:
SVID DATA
CCST_CPU
V
+
12
CLOSE TO CPU
B B
_
CPU_SVIDDAT
H
SVID CLOCK
CPU_SVIDCLK
_
H
_
CPU_SVIDALRT#
H
A A
5
220R2J-L2-GP
The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch).
Route the Alert signal betwee n the Clock and the Data si gnals.
#544669
7
26
R
100R2F-L1-GP-U
7
09
1 2
R
0R0402-PAD
V
CCST_CPU
+
12
7
R
54D9R2F-L1-GP
DY
32
7
1 2
R
0R0402-PAD
V
CCST_CPU
+
#544669
12
CLOSE TO CPU
7
27
R
56R2J-4-GP
28
7
R
12
4
23
R
_SVID_ALERT# [46]
V
#544669
CLOSE TO VR
_SVID_DATA [46]
R
V
_SVID_CLK [46]
R
V
SVID_543016:
3
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
1
1
1
A
A
A
Friday, December 08, 2017
Friday, December 08, 2017
Friday, December 08, 2017
Date: Sheetof
Date: Sheetof
2
Date: Sheetof
1
W
W
W
1
1
1
F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2
2
2
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
P
P
P
U(VCC_CORE)
U(VCC_CORE)
U(VCC_CORE)
C
C
C
arlord KBL-R
arlord KBL-R
arlord KBL-R
t
t
t
S
S
S
i
i
i
stron Corporation
stron Corporation
stron Corporation
7 1
7 1
7 1
A
A
A
06
06
06
0
0
0
0
0
0
5
WWW.AliSaler.Com
4
3
2
1
SSID = CPU
D D
C
1A
PU
H
I_DATA2#[57]
DM
H
DM
I_DATA2[57]
H
DM
I_DATA1#[57]
H
DM
I_DATA1[57]
H
DM
HDMI
Dummy, Vendor suggest
20141117
3
D3
V_S0
D3
V_S0
SRN2K2J -1-GP
1
DY
2 3
R
N8
R
N8
1
2 3
SRN2K2J -1-GP
C
4
_DP1_CT RL_DATA
PU
C
_DP1_CT RL_CLK
PU
01
03
C
4
PU
_DP2_CT RL_DATA
C
_DP2_CT RL_CLK
PU
C C
3
DP and DP to VGA
HDMI
+
VC
Check
CIO
R
80
1 2
24D9R2F -L-GP
C
1
I_DATA0#[57]
H
DM
I_DATA0[57]
H
I_CLK#[57]
DM
H
DM
I_CLK[57]
P
CH
_DPC_N0[38]
P
_DPC_P0[38]
CH
P
CH
_DPC_N1[38]
P
CH
_DPC_P1[38]
P
CH
_DPC_N2[38]
P
_DPC_P2[38]
CH
P
CH
_DPC_N3[38]
P
_DPC_P3[38]
CH
C
PU_DP1_ CTRL_CLK[57]
_DP1_CT RL_DATA[57]
PU
C
PU
_DP2_CT RL_CLK
C
PU
_DP2_CT RL_DATA
E
DP
_COMP
E55
D
DI
1_TXN[0]
F55
D
DI
1_TXP[0]
E58
D
1_TXN[1]
DI
F58
D
1_TXP[1]
DI
F53
D
1_TXN[2]
DI
G53
D
DI
1_TXP[2]
F56
D
DI
1_TXN[3]
G56
D
1_TXP[3]
DI
C50
D
DI
2_TXN[0]
D50
D
DI
2_TXP[0]
C52
D
2_TXN[1]
DI
D52
D
DI
2_TXP[1]
A50
D
DI
2_TXN[2]
B50
D
2_TXP[2]
DI
D51
D
2_TXN[3]
DI
C51
D
DI
2_TXP[3]
L13
G
_E18/DDPB_CTRLCLK
PP
L12
G
_E19/DDPB_CTRLDATA
PP
N7
G
PP
_E20/DDPC_CTRLCLK
N8
G
PP
_E21/DDPC_CTRLDATA
N11
G
_E22/DDPD_CTRLCLK
PP
N12
G
_E23/DDPD_CTRLDATA
PP
E52
E
DP
_RCOMP
SKYLAKE-U-GP
(#543016) The S kylake U/Y pro cessor supports only two DDI ports - Port 1 and Port 2.
SKYLAKE_ULT
DDI
DISPLAY SIDEBANDS
EDP
G
G
G
G
(#543016) eDP_RCOMP Guideline
Signal Trace
Width
eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1%
B B
(#543016) DDI Disabling and Termination Guidelines
Port Strap Enable Port Disable Port
Port 1
DDPB_CTRLDATA
Port 2
DDPC_CTRLDATA
Isolation
Spacing
PU to 3.3 V wit h 2.2-k
±5% resistor
PU to 3.3 V wit h 2.2-k
±5% resistor
Resistor
Value
Length
Max = 100 mils
NC
NC
S
IO
_EXT_SM I#
1 2
R
80
2 1 0KR2J-3-GP
3
D3
V_S0
E
DP
E
DP
E
DP
E
DP
E
DP
E
DP
E
DP
E
DP
E
DP
E
DP
E
DP
_DISP_UTIL
D
DI
D
DI
D
DI
D
DI
D
DI
D
DI
_E13/DDPB_HPD0
PP
PP
_E14/DDPC_HPD1
PP
_E15/DDPD_HPD2
PP
_E16/DDPE_HPD3
G
PP
_E17/EDP_HPD
E
_BKLTEN
DP
E
DP
_BKLTCTL
E
DP
1
OF 20
_TXN[0]
_TXP[0]
_TXN[1]
_TXP[1]
_TXN[2]
_TXP[2]
_TXN[3]
_TXP[3]
_AUXN
_AUXP
1_AUXN
1_AUXP
2_AUXN
2_AUXP
3_AUXN
3_AUXP
_VDDEN
C
PU
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
_DP2_HP D
TypeC
E
DP
_DISP_UTIL
C
_DP2_HP D
PU
S
IO
_EXT_SM I#
1 2
R
80
4 0R2J-2-GP
TypeC
R
80
3
100KR2J -1-GP
1 2
E
DP
_TX0_DN [55 ]
E
_TX0_DP [55]
DP
E
_TX1_DN [55 ]
DP
E
DP
_TX1_DP [55]
E
DP
_TX2_DN [55 ]
E
_TX2_DP [55]
DP
E
DP
_TX3_DN [55 ]
E
_TX3_DP [55]
DP
E
_AUX_DN [55]
DP
E
_AUX_DP [55]
DP
1
T
01 TPAD1 4-OP-GP
P8
D
PB_AUXN [38]
D
PB
C
_DP1_HP D [57]
PU
Vince,20161018
E
_HPD [55]
DP
L
L
_B
KLT_CTR L [55]
E
_VDD_EN [55]
DP
_AUXP [38]
_B
KLT_EN [24,55]
C
PU
_DP_HPD _R [37,38 ,57]
A A
Design Guidelin e:
Skylake process or signal eDP_ RCOMP should be connected to the VCCIO rai l via a single 24.9 ±1% Ω res istor.
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
W
W
W
is
is
is
tron Corporation
tron Corporation
tron Corporation
2
2
2
1F
1F
1F
, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A
A
A
3
3
3
Date: Sheet
Date: Sheet
Date: Sheet
C
C
C
PU
PU
PU
_(DISPLAY)
_(DISPLAY)
_(DISPLAY)
S
S
S
ta
ta
ta
rlord KBL-R
rlord KBL-R
rlord KBL-R
8 10
8 10
8 10
1
o
o
o
f
f
f
00
00
00
A
A
A
6Friday, December 08, 2017
6Friday, December 08, 2017
6Friday, December 08, 2017
5
4
3
2
1
Main Func = CPU
D D
C C
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
W
W
W
i
i
i
stron Corporation
stron Corporation
stron Corporation
2
2
2
1
1
1
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
T
tle
Title
Title
i
(
(
(
eserved)
eserved)
eserved)
R
R
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet
Date: Sheet
Date: Sheet
R
A
A
A
3
3
3
S
S
S
t
t
t
arlord KBL-R
arlord KBL-R
arlord KBL-R
9 1
9 1
9 1
1
o
o
o
f
f
f
0
0
0
0
0
0
A
A
A
06Monday, August 2 8, 2017
06Monday, August 2 8, 2017
06Monday, August 2 8, 2017
SSID = CPU
WWW.AliSaler.Com
5
4
3
2
1
D D
CORE
U-line 23e 28W
IccMax current-10ms max = 34 A
22U 0603 x 35(5 DY)
CC
_CORE
V
002
C1
P
12
C1
011
P
12
022
C1
P
C C
12
005
004
003
C1
C1
C1
P
P
P
12
12
12
S
C2
2U6D3V3MX-1-GP
S
C2
2U6D3V3MX-1-GP
S
C2
2U6D3V3MX-1-GP
S
S
S
C2
C2
C2
2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
C1
C1
C1
014
012
013
P
P
P
12
12
12
S
S
S
C2
C2
C2
2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
024
023
025
C1
C1
C1
P
P
P
12
12
12
S
S
S
C2
C2
C2
2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
SLICED GT
U-line 23e 28W
IccMax current-10ms max[A] = 67 A
22U 0603 x35 (5 DY)
CGT
VC
+
039
038
037
C1
C1
C1
P
P
P
12
12
12
S
S
S
C2
C2
C2
2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
C1
C1
C1
045
044
046
P
P
P
12
12
12
S
S
S
C2
C2
C2
2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
B B
058
060
059
C1
C1
C1
P
P
P
12
12
12
S
S
S
C2
C2
C2
2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
20140814 DAVID
EMI reserve , 20141118
009
006
007
C1
C1
P
P
12
12
S
C2
2U6D3V3MX-1-GP
C1
C1
016
015
P
P
12
12
S
C2
2U6D3V3MX-1-GP
026
027
C1
C1
P
P
12
12
S
C2
2U6D3V3MX-1-GP
041
040
C1
C1
P
P
12
12
S
C2
2U6D3V3MX-1-GP
C1
C1
048
047
P
P
12
12
S
C2
2U6D3V3MX-1-GP
061
062
C1
C1
P
P
12
12
S
C2
2U6D3V3MX-1-GP
010
008
C1
C1
P
P
12
12
S
S
C2
C2
2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
C1
C1
017
P
P
12
12
S
S
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12
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12
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C22U6D3V3MX-1-GP
2U6D3V3MX-1-GP
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12
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12
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057
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12
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12
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082
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12
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12
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C2
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2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
VCCSA
22U 0603 x13 (5 DY)
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071
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12
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074
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12
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075
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C1
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12
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2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
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077
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C1
P
P
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12
12
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S
S
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C2
C2
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2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
2U6D3V3MX-1-GP
2015/10/16 modify (Power team request)
A A
5
4
007
001
C1
C1
E
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12
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S
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CD
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1U25V2KX-L-GP
1U25V2KX-L-GP
<Core Design>
<Core Design>
<Core Design>
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Title
Title
it
T
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C
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
1
1
1
A
A
A
Date: Sheet
Date: Sheet
3
2
Date: Sheet
1
1F,
1F,
1F,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
PU
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88, Sec.1, Hsin Tai Wu Rd., Hsichih,
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06Friday, December 08, 2017
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Main Func = CPU
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SC22U6D3V3MX-1-GP
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1
112
12
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3.3A_SIP
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1
113
12
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CCMPHYGTAO N_1P0_LS_SIP
SC1U10V2KX-1GP
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114
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1U 0402 x 6
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1U10V2KX-1GP
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12
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1
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C
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Layout Note:
1uF:
SC1U10V2KX-1GP
C1174 near N15
C1180 near K15
C1173 near AF20
C1172 near N18
C1175 near AB19
22uF :
C1182 C1184 near N15
10uF:
C1176 near N15
+VCCIO(ICCMAX.= 2.73A)
1104
1103SC22U6D3V3MX-1-GP
1102SC22U6D3V3MX-1-GP
12
C
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B B
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A A
12
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20141117
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126
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SC22U6D3V3MX-1-GP
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12
1
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12
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1107SC10U6D3V3MX-GP
12
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1114
1101
12
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22U6D3V3MX-1-GP
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C
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12
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SCD1U25V2KX-GP
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2D2U10V2KX-GP
RF request 2016/01/12 modify
3
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1112
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SCD1U25V2KX-GP
SCD1U25V2KX-GP
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E
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<Core Design>
<Core Design>
<Core Design>
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W
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2
2
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F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
1
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Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
T
tle
Title
Title
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Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A
A
A
3
3
3
Date: Sheet
Date: Sheet
2
Date: Sheet
C
C
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P
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1 106Friday, December 08, 2 017
1 106Friday, December 08, 2 017
1 106Friday, December 08, 2 017
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WWW.AliSaler.Com
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_A1[5]
M
_A2[5]
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M
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_A3[5]
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_A4[5]
_A
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_A5[5]
M
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_A6[5]
M
_A7[5]
_A
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_A8[5]
M
_A9[5]
_A
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_A10[5]
M
_A11[5]
_A
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_A12[5]
M
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_A13[5]
M
_A14[5]
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_A15[5]
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_BA0[5]
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M
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B1
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C
101
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B2
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105
B3
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C
88
B4
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C
87
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B6
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B7
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137
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62
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79
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Q3
1
174
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173
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187
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186
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Q4
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207
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224
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225
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249
Q5
8
250
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Q5
232
Q6
0
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Q6
1
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Q6
246
Q6
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Layout note: closed to Dimm
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_DQ1 [5]
_DQ2 [5]
_DQ3 [5]
_DQ4 [5]
_DQ5 [5]
_DQ6 [5]
_DQ7 [5]
_DQ8 [5]
_DQ9 [5]
_DQ10 [5]
_DQ11 [5]
_DQ12 [5]
_DQ13 [5]
_DQ14 [5]
_DQ15 [5]
_DQ16 [5]
_DQ17 [5]
_DQ18 [5]
_DQ19 [5]
_DQ20 [5]
_DQ21 [5]
_DQ22 [5]
_DQ23 [5]
_DQ24 [5]
_DQ25 [5]
_DQ26 [5]
_DQ27 [5]
_DQ28 [5]
_DQ29 [5]
_DQ30 [5]
_DQ31 [5]
_DQ32 [5]
_DQ33 [5]
_DQ34 [5]
_DQ35 [5]
_DQ36 [5]
_DQ37 [5]
_DQ38 [5]
_DQ39 [5]
_DQ40 [5]
_DQ41 [5]
_DQ42 [5]
_DQ43 [5]
_DQ44 [5]
_DQ45 [5]
_DQ46 [5]
_DQ47 [5]
_DQ48 [5]
_DQ49 [5]
_DQ50 [5]
_DQ51 [5]
_DQ52 [5]
_DQ53 [5]
_DQ54 [5]
_DQ55 [5]
_DQ56 [5]
_DQ57 [5]
_DQ58 [5]
_DQ59 [5]
_DQ60 [5]
_DQ61 [5]
_DQ62 [5]
_DQ63 [5]
跟sw確
12
04 10KR2F-L1-GP
12
DY
12
05
12
12
08 10KR2F-L1-GP
R
DY
12
10
R
12
11 10KR2F-L1-GP
12
R
DY
12
12
R
3
M1
D
4 OF 4
D
M1
B
2 OF 4
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
M0
D
M1
D
M2
D
M3
D
M4
D
M5
D
M6
D
M7
D
#/DBI#/NC
M8
D
DR
4-260P-65-GP
D
D2
V_S3
1
#/DBI0#
#/DBI2#
#/DBI3#
#/DBI4#
#/DBI5#
#/DBI6#
#/DBI7#
1
11
12
1
1
17
18
1
1
23
24
1
1
29
1
30
35
1
1
36
41
1
1
42
1
47
48
1
1
53
54
1
1
59
60
1
63
1
QS
QS
QS
QS
QS
QS
QS
QS
QS
QS
QS
QS
QS
QS
QS
QS
QS
QS
#/DBI#
0_C
0_T
1_C
1_T
2_C
2_T
3_C
3_T
4_C
4_T
5_C
5_T
6_C
6_T
7_C
7_T
8_C
8_T
D
D
M1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DR
11
13
32
34
53
55
74
76
177
179
198
200
219
221
240
242
95
97
12
33
54
75
178
199
220
241
96
C
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
4-260P-65-GP
_A
_DQS_DN0
M
_A
_DQS_DP0
M
_DQS_DN1
_A
M
_A
_DQS_DP1
M
_DQS_DN2
_A
M
_A
_DQS_DP2
M
_A
_DQS_DN3
M
_DQS_DP3
_A
M
_A
_DQS_DN4
M
_DQS_DP4
_A
M
_A_DQS_DN5
M
_A
_DQS_DP5
M
_DQS_DN6
_A
M
_A
_DQS_DP6
M
_DQS_DN7
_A
M
_A
_DQS_DP7
M
DD
V
3 OF 4
V_S3
D2
1
V_S0
D3
3
255
SPD
57
2
PP
V
2
59
PP
V
2
58
TT
V
2
61
61
2
62
2
62
2
N
P1
P1
N
P2
N
P2
N
V_S3
D5
2
D6
0
12
28
C
S
CD
12
12
DY
V_S0
16
12
R
S
C2
1U16V2KX-L-GP
D2U10V3KX-L-GP
DY
20170307 DTC Dummy
D2
V_S3
1
認
A0
_CHA_DIM0
S
A1
_CHA_DIM0
S
_CHA_DIM0
A2
S
12
12
12
12
12
12
12
12
08
09
03
02
C
C
C
C
S
S
S
S
DY
C1
C1
C1
C1
0U6D3V3MX-GP
0U6D3V3MX-GP
0U6D3V3MX-GP
0U6D3V3MX-GP
12
14
12
C
S
DY
C1
U10V2KX-1GP
12
12
12
12
C
S
C1
U10V2KX-1GP
17
16
15
12
12
C
C
S
S
DY
C1
C1
U10V2KX-1GP
U10V2KX-1GP
_A
_DQS_DN0
M
_DQS_DN1
_A
M
_A
_DQS_DN2
M
_A
_DQS_DN3
M
_DQS_DN4
_A
M
_A
_DQS_DN5
M
_DQS_DN6
_A
M
_A
_DQS_DN7
M
_A
_DQS_DP0
M
_DQS_DP1
_A
M
_A
_DQS_DP2
M
_A
_DQS_DP3
M
_DQS_DP4
_A
M
_A
_DQS_DP5
M
_DQS_DP6
_A
M
_A
_DQS_DP7
M
12
12
12
12
12
12
12
06
04
05
C
C
C
C
S
S
S
S
DY
C1
C1
C1
C1
0U6D3V3MX-GP
0U6D3V3MX-GP
0U6D3V3MX-GP
0U6D3V3MX-GP
12
12
12
18
12
C
S
DY
C1
U10V2KX-1GP
12
20
19
12
12
C
C
C
S
S
S
DY
DY
C1
C1
C1
U10V2KX-1GP
U10V2KX-1GP
U10V2KX-1GP
RF request 2016/01/12 modify
_A
_DQS_DN[7:0] [5]
M
_DQS_DP[7:0] [5]
_A
M
12
DY
12
1
SS
V
2
SS
V
5
SS
V
6
SS
V
9
SS
V
0
1
SS
V
1
4
SS
V
5
1
SS
V
1
8
SS
V
1
9
SS
V
2
2
SS
V
2
3
SS
V
6
2
SS
V
2
7
SS
V
3
0
SS
V
1
3
SS
V
3
5
SS
V
6
3
SS
V
3
9
SS
V
4
0
SS
V
4
3
SS
V
4
4
SS
V
7
4
SS
V
4
8
SS
V
1
5
SS
V
5
2
SS
V
5
6
SS
V
7
5
SS
V
6
0
SS
V
1
6
SS
V
6
4
SS
V
6
5
SS
V
8
6
SS
V
6
9
SS
V
2
7
SS
V
7
3
SS
V
7
7
SS
V
8
7
SS
V
8
1
SS
V
2
8
SS
V
8
5
SS
V
6
8
SS
V
8
9
SS
V
9
0
SS
V
3
9
SS
V
9
4
SS
V
8
9
SS
V
4-260P-65-GP
DR
D
D6
V_S0
0
12
12
12
26
12
25
C
C
S
S
C1
C1
U10V2KX-1GP
U10V2KX-1GP
10
202
21
C1
E
S
C2
12
DY
D2U10V2KX-GP
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
UN 0225
2
9
9
1
02
1
03
06
1
1
07
67
1
1
68
71
1
1
72
1
75
76
1
1
80
81
1
1
84
1
85
88
1
1
89
92
1
1
93
1
96
1
97
2
01
02
2
2
05
06
2
2
09
2
10
13
2
2
14
17
2
2
18
2
22
23
2
2
26
27
2
2
30
2
31
34
2
2
35
38
2
2
39
43
2
2
44
2
47
48
2
2
51
52
2
V_S0
D6
0
12
12
12
23
C
S
C1
U10V2KX-1DLGP
D5
V_S3
12
12
12
11
C
S
C1
U10V2KX-1DLGP
2
1
20170104
V_S0
D6
0
12
12
12
12
30
C
S
C1
U10V2KX-1DLGP
12
12
31
12
32
C
C
S
S
C1
C1
U10V2KX-1DLGP
U10V2KX-1DLGP
27
12
24
C
C
S
S
C1
C1
U10V2KX-1DLGP
U10V2KX-1DLGP
12
12
12
12
07
12
12
C
S
C1
U10V2KX-1DLGP
13
12
C
C
S
S
C1
C1
U10V2KX-1DLGP
U10V2KX-1DLGP
A A
<Core Design>
<Core Design>
<Core Design>
tron Corporation
tron Corporation
tron Corporation
is
is
is
W
W
W
1F
1F
1F
, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
2
2
2
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
3-SODIMM1
3-SODIMM1
3-SODIMM1
ta
ta
ta
rlord KBL-R
rlord KBL-R
rlord KBL-R
S
S
S
1
12 1
12 1
12 1
f
f
f
o
o
o
A
A
A
06
06
06
5
it
le
Title
Title
T
A
A
A
4
3
2
DR
DR
DR
D
D
D
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
2
2
2
Friday, December 08, 2017
Friday, December 08, 2017
Friday, December 08, 2017
Date: Sheet
Date: Sheet
Date: Sheet
00
00
00
5
M
2A
D
44
A
0_CHB_DIM0
S
A
1_CHB_DIM0
S
2_CHB_DIM0
A
S
S
#_DIMM1_1
T
301
SCD1U16V2KX-3DLGP
1
0
A
1
33
1
A
1
32
2
A
31
1
3
A
1
28
4
A
26
1
5
A
1
27
6
A
22
1
7
A
1
25
8
A
1
21
9
A
146
0/AP
1
A
120
1
1
A
119
2
1
A
158
1
3
A
151
E
#/A14
W
156
S#/A15
A
C
152
A
S#/A16
R
150
A
0
B
145
A
1
B
115
0
G
B
113
G
1
B
92
B
0/NC
C
91
1/NC
B
C
101
B
2/NC
C
105
B
3/NC
C
88
4/NC
B
C
87
B
5/NC
C
100
6/NC
B
C
104
B
7/NC
C
137
0_T
K
C
139
K
0_C
C
138
1_T/NF
K
C
140
K
1_C/NF
C
109
E0
K
C
110
K
E1
C
149
S
0#
C
157
1#
S
C
162
0
/CS2#/NC
C
165
1
/CS3#/NC
C
155
D
T0
O
161
T1
D
O
256
A
0
S
260
1
A
S
166
A
2
S
254
D
A
S
253
L
C
S
108
SET#
E
R
114
C
T#
A
116
ERT#
L
A
134
V
ENT#/NF
E
143
RITY
A
P
164
EFCA
R
V
D
R4-260P-64- GP
D
_
B_A0[5]
M
B_A1[5]
_
M
_
B_A2[5]
M
B_A3[5]
_
M
_
B_A4[5]
M
_
B_A5[5]
M
B_A6[5]
_
M
_
B_A7[5]
M
B_A8[5]
_
M
_
B_A9[5]
M
B_A10[5]
_
M
_
B_A11[5]
M
_
B_A12[5]
M
B_A13[5]
_
M
_
B_A14[5]
M
B_A15[5]
_
M
_
H_SMBCLK[12,18]
DY
D
D
_
M
_
M
240R2F-1-GP
B_A16[5]
M
_
B_BA0[5]
M
B_BA1[5]
_
M
_
B_BG0[5]
M
B_BG1[5]
_
M
_
B_CLK0[5]
M
B_CLK#0[5]
_
M
_
B_CLK1[5]
M
_
B_CLK#1[5]
M
_
B_CKE0[5]
M
B_CKE1[5]
_
M
B_CS#0[5]
_
M
_
B_CS#1[5]
M
_
B_DIMB_ODT0[5]
M
B_DIMB_ODT1[5]
_
M
R4_DRAMRST#[5,12]
B_ACT_N[5]
B_ALERT_N[5]
B_PARITY[5]
_
M
_
VREF_CA_DIMMB
M
12
1
C
D D
H_SMBDATA[12,18]
C
P
C
P
2V_S3
D
1
C C
1 2
D
R4_DRAMRST#
D
12
1302
D
E
AZ5725-01FDR7G-GP
1
312
R
Layout note: closed to Dimm
2V_S3
D
1
1301
N
R
1
4
VREF_CA_DIMMB
_
B B
2 3
SRN1KJ-7-GP
M
R
1 2
2R2F-GP
1
305
12
1
323
C
SCD022U16V2KX-3GP
V
_VREF_PATH2
+
12
309
1
R
24D9R2F-L-GP
SM_VREF_CNTB [ 5]
_
V
1 OF 4
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
8
0
Q
7
Q
1
20
Q
2
21
3
Q
4
Q
4
3
5
Q
16
Q
6
17
7
Q
28
Q
8
29
Q
9
41
10
Q
42
Q
11
24
12
Q
25
Q
13
38
Q
14
37
15
Q
50
Q
16
49
17
Q
62
Q
18
63
Q
19
46
20
Q
45
Q
21
58
22
Q
59
Q
23
70
24
Q
71
Q
25
83
Q
26
84
27
Q
66
Q
28
67
29
Q
79
Q
30
80
Q
31
174
32
Q
173
Q
33
187
34
Q
186
Q
35
170
Q
36
169
37
Q
183
Q
38
182
39
Q
195
Q
40
194
41
Q
207
Q
42
208
Q
43
191
44
Q
190
Q
45
203
46
Q
204
Q
47
216
Q
48
215
49
Q
228
Q
50
229
51
Q
211
Q
52
212
53
Q
224
54
Q
225
Q
55
237
56
Q
236
Q
57
249
58
Q
250
Q
59
232
Q
60
233
61
Q
245
Q
62
246
63
Q
3V_S0
D
3
3V_S0
D
3
3V_S0
D
3
4
_
B_DQ8 [5]
M
B_DQ9 [5]
_
M
_
B_DQ10 [5]
M
B_DQ11 [5]
_
M
_
B_DQ12 [5]
M
_
B_DQ13 [5]
M
B_DQ14 [5]
_
M
_
B_DQ15 [5]
M
B_DQ0 [5]
_
M
_
B_DQ1 [5]
M
B_DQ2 [5]
_
M
_
B_DQ3 [5]
M
_
B_DQ4 [5]
M
B_DQ5 [5]
_
M
_
B_DQ6 [5]
M
B_DQ7 [5]
_
M
_
B_DQ16 [5]
M
_
B_DQ17 [5]
M
B_DQ18 [5]
_
M
_
B_DQ19 [5]
M
B_DQ20 [5]
_
M
_
B_DQ21 [5]
M
B_DQ22 [5]
_
M
B_DQ23 [5]
_
M
_
B_DQ24 [5]
M
B_DQ25 [5]
_
M
_
B_DQ26 [5]
M
B_DQ27 [5]
_
M
_
B_DQ28 [5]
M
_
B_DQ29 [5]
M
B_DQ30 [5]
_
M
_
B_DQ31 [5]
M
B_DQ32 [5]
_
M
_
B_DQ33 [5]
M
_
B_DQ34 [5]
M
B_DQ35 [5]
_
M
_
B_DQ36 [5]
M
B_DQ37 [5]
_
M
_
B_DQ38 [5]
M
B_DQ39 [5]
_
M
_
B_DQ40 [5]
M
_
B_DQ41 [5]
M
B_DQ42 [5]
_
M
_
B_DQ43 [5]
M
B_DQ44 [5]
_
M
_
B_DQ45 [5]
M
_
B_DQ46 [5]
M
B_DQ47 [5]
_
M
_
B_DQ48 [5]
M
B_DQ49 [5]
_
M
_
B_DQ50 [5]
M
_
B_DQ51 [5]
M
B_DQ52 [5]
_
M
_
B_DQ53 [5]
M
B_DQ54 [5]
_
M
_
B_DQ55 [5]
M
B_DQ56 [5]
_
M
_B_DQ57 [5]
M
_
B_DQ58 [5]
M
B_DQ59 [5]
_
M
_
B_DQ60 [5]
M
B_DQ61 [5]
_
M
_
B_DQ62 [5]
M
_
B_DQ63 [5]
M
DDR4 SWAP 0212
跟sw確
DY
302 10KR2F-L1-GP
1
12
R
1
303
1 2
R
0R0402-PAD
12
306 10KR2F-2-GP
1
R
12
307 0R2J-L-GP
1
R
DY
DY
12
310 10KR2F-L1-GP
1
R
1 2
311
1
R
0R0402-PAD
By layou modify 20150916
D
2V_S3
1
D
0_CHB_DIM0
A
S
1_CHB_DIM0
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2_CHB_DIM0
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1
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111
D
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112
D
D
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117
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118
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123
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D
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124
D
D
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129
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D
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130
D
D
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135
D
D
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136
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141
D
D
V
142
D
D
V
147
D
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148
D
D
V
153
D
D
V
154
D
D
V
159
D
D
V
160
D
D
V
163
D
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R4-260P-64-G P
D
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2 OF 4
D
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0#/DBI0#
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1#/DBI#
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2#/DBI2#
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D
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3#/DBI3#
D
4#/DBI4#
M
D
M
5#/DBI5#
D
6#/DBI6#
M
D
M
7#/DBI7#
D
M
8#/DBI#/NC
D
R4-260P-64- GP
D
D
2V_S3
20170307 DTC Dummy
12
12
12
304
303
1
1
C
C
C
S
S
DY
C
C
10U6D3V3MX-GP
10U6D3V3MX-GP
12
12
12
1
1
315
316
C
C
C
S
S
DY
DY
C
C
1U10V2KX-1GP
1U10V2KX-1GP
3 OF 4
255
DSPD
D
V
257
P
P
V
259
P
P
V
258
T
T
V
261
1
6
2
262
6
2
2
NP1
P
1
N
NP2
2
P
N
By layou modify 20150916
B_DQS_DN1
_
11
M
_
B_DQS_DP1
13
M
B_DQS_DN0
_
32
M
_
B_DQS_DP0
34
M
_
B_DQS_DN2
53
M
B_DQS_DP2
_
55
M
_
B_DQS_DN3
74
M
B_DQS_DP3
_
76
M
_
B_DQS_DN4
177
M
_
B_DQS_DP4
179
M
B_DQS_DN5
_
198
M
_
B_DQS_DP5
200
M
B_DQS_DN6
_
219
M
_
B_DQS_DP6
221
M
B_DQS_DN7
_
240
M
_
B_DQS_DP7
242
M
95
97
12
33
54
75
178
199
220
241
96
12
12
306
305
1
1
C
C
S
S
S
DY
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C
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10U6D3V3MX-GP
10U6D3V3MX-GP
10U6D3V3MX-GP
12
12
1
1
318
317
C
C
S
S
S
DY
C
C
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1U10V2KX-1GP
1U10V2KX-1GP
1U10V2KX-1GP
3V_S5
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3
1302
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12
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2D2U10V2KX-GP
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307
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319
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3
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5V_S3
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M
M
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M
M
M
M
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12
308
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S
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10U6D3V3MX-GP
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1
320
C
S
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1U10V2KX-1GP
6V_S0
_
B_DQS_DN1 [5]
_
B_DQS_DP1 [5]
B_DQS_DN0 [5]
_
_
B_DQS_DP0 [5]
B_DQS_DN2 [5]
_
_
B_DQS_DP2 [5]
B_DQS_DN3 [5]
_
_
B_DQS_DP3 [5]
_
B_DQS_DN4 [5]
B_DQS_DP4 [5]
_
_
B_DQS_DN5 [5]
B_DQS_DP5 [5]
_
_
B_DQS_DN6 [5]
_
B_DQS_DP6 [5]
B_DQS_DN7 [5]
_
_
B_DQS_DP7 [5]
1
12
309
1
C
S
DY
C
10U6D3V3MX-GP
12
1
321
C
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1U10V2KX-1GP
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329
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310
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E
12
1
322
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2D2U10V2KX-GP
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C1U10V2KX-1GP
12
DY
RF request 2016/01/12 modify
D
3
UN 0225
6V_S0
12
1
C
S
C
10U6D3V3MX-GP
3V_S0
2D
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4 OF 4
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325
324
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12
326
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10U6D3V3MX-GP
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1U10V2KX-1GP
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V
9
S
S
V
10
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S
V
14
S
S
V
15
S
S
V
18
S
S
V
19
S
S
V
22
S
S
V
23
S
S
V
26
S
S
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27
S
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30
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31
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35
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36
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39
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40
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43
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44
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47
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48
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51
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57
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60
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64
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12
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1U10V2KX-1GP
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B_DQS_DN0
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B_DQS_DN1
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B_DQS_DN2
_
M
_
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M
B_DQS_DN4
_
M
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B_DQS_DN5
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B_DQS_DN6
_
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B_DQS_DN7
_
M
_
B_DQS_DP0
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B_DQS_DP1
_
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B_DQS_DP2
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B_DQS_DP4
_
M
_
B_DQS_DP5
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B_DQS_DP6
_
M
_
B_DQS_DP7
M
99
S
S
V
102
S
S
V
103
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S
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106
S
S
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107
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167
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V
168
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171
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172
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175
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176
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180
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181
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184
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185
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188
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189
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192
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V
193
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V
196
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197
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V
201
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202
S
S
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205
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S
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206
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S
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209
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210
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213
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214
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217
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V
218
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V
222
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223
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226
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S
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227
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S
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230
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S
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231
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234
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235
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238
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239
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243
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244
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247
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248
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251
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5V_S3
D
2
12
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311
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1
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C
C
S
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1U10V2KX-1DLGP
12
331
1
C
S
C
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_
B_DQS_DN[7:0] [5]
M
B_DQS_DP[7:0] [5]
_
M
2
1
20170104
12
12
12
314
312
313
1
1
1
C
C
C
S
S
S
C
C
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1U10V2KX-1DLGP
1U10V2KX-1DLGP
1U10V2KX-1DLGP
RF request 2016/01/12 modify
A A
<Core Design>
<Core Design>
<Core Design>
stron Corporation
stron Corporation
stron Corporation
i
i
i
W
W
W
1
1
1
F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2
2
2
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
i
tle
Title
Title
T
A
A
A
5
4
3
2
D
D
D
D
D
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
2
2
2
Friday, December 08, 2017
Friday, December 08, 2017
Friday, December 08, 2017
Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
R3-SODIMM1
R3-SODIMM1
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WWW.AliSaler.Com
D D
4
3
2
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C C
(Blanking)
B B
<Core Design>
<Core Design>
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W
W
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tron Corporation
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A A
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Title
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4
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Date: Sheet
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4
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88, Sec.1, Hsin Tai Wu Rd., Hsichih,
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Taipei Hsien 221, Taiwan, R.O.C.
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rlord KBL-R
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14 1
14 1
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06Monday, August 28, 2017
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D38
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A38
B38
C31
D31
C33
D33
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B31
A33
B33
A29
B29
C28
D28
A27
B27
C27
D27
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I2_DN1
C
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S
C
S
I2_DN2
C
S
I2_DP2
C
I2_DN3
S
C
I2_DP3
S
C
I2_DN4
S
C
S
I2_DP4
C
S
I2_DN5
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C
I2_DN6
S
C
I2_DP6
S
C
I2_DN7
S
C
S
I2_DP7
C
I2_DN8
S
C
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S
C
S
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C
S
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I2_DN10
S
C
S
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C
S
I2_DN11
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SKYLAKE-U-GP
SKYLAKE_ULT
EMMC
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S
C
S
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S
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S
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S
C
I2_COMP
S
G
P
P_D4/FLASHTRIG
P_F13/EMMC_DATA0
P_F14/EMMC_DATA1
P_F15/EMMC_DATA2
P_F16/EMMC_DATA3
P_F17/EMMC_DATA4
P_F18/EMMC_DATA5
P_F19/EMMC_DATA6
P_F20/EMMC_DATA7
P
P_F21/EMMC_RCLK
G
P
P_F22/EMMC_CLK
P_F12/EMMC_CMD
P
E
M
MC_RCOMP
C37
D37
C32
D32
C29
DC resistance < 0.5ohm.
D29
B26
A26
C
E13
I2_COMP
S
B7
AP2
AP1
AP3
AN3
GPP_F: VCCPGPPF = 1.8V Only
AN1
AN2
AM4
AM1
AM2
AM3
AP4
E
AT1
M
MC_RCOM P
1 2
W
I
FI_RF_EN [66]
1 2
R
1
501 10 0R2F-L1-GP-U
R
502
1
200R2F-L -GP
W
FI_RF_EN
I
503
12
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10KR2J-3 -GP
C
hange to Dummy 20150402
[#545659 Rev0.7 ]
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
W
W
W
i
i
i
stron Corporation
stron Corporation
stron Corporation
2
2
2
1
1
1
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A
A
A
3
3
3
Date: Sheet
Date: Sheet
Date: Sheet
C
C
C
P
P
P
U_(CS-2/EMMC)
U_(CS-2/EMMC)
U_(CS-2/EMMC)
S
S
S
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1
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1
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5 106Friday, December 08, 2 017
5 106Friday, December 08, 2 017
5 106Friday, December 08, 2 017
f
f
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0
0
0
0
0
0
A
A
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SSID = PCH
WWW.AliSaler.Com
#543016:
220 nF nominal capacitors are recommended for Gen 3.
100 nF nominal capacitors are recommended for Gen 2.
GPU
D D
Vince,20170105
WLAN
HDD1
Vince,20160922
SSD
Layout Note:
C C
Vince,20161014
V1
.8A
+
07 10KR2J-3-GP
16
1 2
R
5
_RXN_C_dGPU_TXN0[66]
PU
C
PU
_RXP_C_dGPU_TXP0[66]
C
GP
U_RXN_C_CPU_TXN0[66]
d
U_RXP_C_CPU_TXP0[66]
GP
d
PU
_RXN_C_dGPU_TXN1[66]
C
PU
_RXP_C_dGPU_TXP1[66]
C
GP
U_RXN_C_CPU_TXN1[66]
d
U_RXP_C_CPU_TXP1[66]
GP
d
PU_RXN_C_dGPU_TXN2[66]
C
_RXP_C_dGPU_TXP2[66]
PU
C
GP
U_RXN_C_CPU_TXN2[66]
d
GPU_RXP_C_CPU_TXP2[66]
d
PU
_RXN_C_dGPU_TXN3[66]
C
_RXP_C_dGPU_TXP3[66]
PU
C
U_RXN_C_CPU_TXN3[66]
GP
d
GP
U_RXP_C_CPU_TXP3[66]
d
E_RX_CPU_N6[66]
CI
P
CI
E_RX_CPU_P6[66]
P
E_TX_WLAN_N6[66]
CI
P
CI
E_TX_WLAN_P6[66]
P
A_RX_CPU_N0[60]
AT
S
AT
A_RX_CPU_P0[60]
S
AT
A_TX_CPU_N0[60]
S
A_TX_CPU_P0[60]
AT
S
CI
E_RX_CPU_N9[63]
P
E_RX_CPU_P9[63]
CI
P
CI
E_TX_CPU_N9[63]
P
CI
E_TX_CPU_P9[63]
P
CI
E_RX_CPU_N10[63]
P
E_RX_CPU_P10[63]
CI
P
CI
E_TX_CPU_N10[63]
P
CI
E_TX_CPU_P10[63]
P
605TPAD14-OP-GP
P1
T
P1
606TPAD14-OP-GP
T
E_RX_CPU_N11[63]
CI
P
E_RX_CPU_P11[63]
CI
P
CI
E_TX_CPU_N11[63]
P
E_TX_CPU_P11[63]
CI
P
AT
A_RX_CPU_N12[63]
S
AT
A_RX_CPU_P12[63]
S
A_TX_CPU_N12[63]
AT
S
AT
A_TX_CPU_P12[63]
S
1. Trace Width: 4 mils min (b reakout) 12-15 mils (trace)
Note: Must maintain low DC re sistance routing (<0.1 ohm) .
2. Isolation Spacing: At leas t 12 mils to any adjacent
high speed I/O.
QA#
IR
P
16
06
C
05
16
C
16
08
C
1607
C
10
16
C
16
09
C
12
16
C
16
11
C
16
01 SCD1U16V2KX-3DLGP
C
02 SCD1U16V2KX-3DLGP
16
C
16
04
1 2
R
100R2F-L1-GP-U
1
1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
DP
X
DP
X
_PRDY#
_PREQ#
OPS
OPS
OPS
OPS
OPS
OPS
OPS
OPS
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
EG
P
EG
P
EG
P
EG
P
EG
P
EG
P
EG
P
EG
P
CI
P
CI
P
IR
P
E_RCOMPN
E_RCOMPP
QA#
_TX_CPU_N0
_TX_CPU_P0
_TX_CPU_N1
_TX_CPU_P1
_TX_CPU_N2
_TX_CPU_P2
_TX_CPU_N3
_TX_CPU_P3
CI
E_TX_CPU_N6
P
E_TX_CPU_P6
CI
P
C
PU
1H
PCIE/USB3/SATA
H13
CI
E1_RXN/US B3_5_R XN
G13
E1_RXP /USB3_5_ RXP
CI
P
B17
CIE1_T XN/USB3_5 _TXN
P
A17
CI
E1_TXP /USB3_5_ TXP
P
P
G11
CI
E2_RXN/US B3_6_R XN
F11
E2_RXP /USB3_6_ RXP
CI
P
D16
CI
E2_TXN/US B3_6_T XN
P
C16
E2_TXP /USB3_6_ TXP
CI
P
P
H16
E3_RXN
CI
G16
CI
E3_RXP
P
D17
E3_TXN
CI
P
C17
CIE3_T XP
P
P
G15
E4_RXN
CI
F15
E4_RXP
CI
P
B19
CIE4_T XN
P
A19
CI
E4_TXP
P
P
F16
CI
E5_RXN
E16
E5_RXP
CI
P
C19
CI
E5_TXN
P
D19
E5_TXP
CI
P
P
G18
E6_RXN
CI
F18
CI
E6_RXP
P
D20
E6_TXN
CI
P
C20
CIE6_T XP
P
P
F20
E7_RXN/S ATA0_R XN
CI
E20
CI
E7_RXP /SATA0_ RXP
P
B21
E7_TXN/S ATA0_T XN
CI
P
A21
CI
E7_TXP /SATA0 _TXP
P
P
G21
CI
E8_RXN/S ATA1A_ RXN
F21
E8_RXP /SATA1A _RXP
CI
P
D21
CI
E8_TXN/S ATA1A_ TXN
P
C21
E8_TXP /SATA1 A_TXP
CI
P
P
E22
CI
E9_RXN
E23
E9_RXP
CI
P
B23
CI
E9_TXN
P
A23
CIE9_T XP
P
P
F25
E10_RX N
CI
E25
CI
E10_RX P
P
D23
E10_TX N
CI
P
C23
CI
E10_TX P
P
P
F5
CIE_RC OMPN
E5
E_RCOMP P
CI
P
P
D56
C_PRDY#
RO
D61
ROC_PR EQ#
P
BB11
PP
_A7/PIR QA#
P
G
E28
CI
E11_RX N/SATA1B _RXN
E27
P
E11_RX P/SATA1 B_RXP
CI
D24
P
CI
E11_TX N/SATA1B _TXN
C24
P
E11_TX P/SATA 1B_TXP
CI
E30
P
CI
E12_RX N/SATA2_ RXN
F30
P
E12_RX P/SATA2 _RXP
CI
A25
P
CI
E12_TX N/SATA2_ TXN
B25
P
E12_TX P/SATA 2_TXP
CI
P
SKYLAKE-U-GP
USB 2.0 Table
Pair
Device
USB3.0 port1
0
1
USB3.0 Port2 (Debug Port/IOBD)
2
USB3.0 Port3 (IOBD)
3
Sensor HUB
CAMERA
4
WLAN
5
Touch Panel
6
Card Reader
7
SKYLAKE_ULT
SSIC / USB3
SB
3_2_RX N/SSIC_1 _RXN
3_2_RX P/SSIC_ 1_RXP
SB
U
SB
3_2_TX N/SSIC_1 _TXN
U
3_2_TX P/SSIC_ 1_TXP
SB
U
U
3_3_RX N/SSIC_2 _RXN
SB
SB
3_3_RX P/SSIC_ 2_RXP
U
3_3_TX N/SSIC_2 _TXN
SB
U
SB
3_3_TX P/SSIC_ 2_TXP
U
U
USB2
PP
_E0/SAT AXPCIE 0/SATA GP0
G
_E1/SAT AXPCIE 1/SATA GP1
PP
G
PP
_E2/SAT AXPCIE 2/SATA GP2
G
4
OF 20
8
H8
SB
3_1_RX N
G8
3_1_RX P
SB
C13
U
SB
3_1_TX N
U
D13
3_1_TX P
SB
U
U
J6
H6
B13
A13
J10
H10
B15
A15
E10
SB3_4_ RXN
F10
SB
3_4_RX P
U
C15
3_4_TX N
SB
U
D15
3_4_TX P
SB
U
U
AB9
SB
2N_1
AB10
2P_1
SB
U
U
AD6
2N_2
SB
AD7
SB
2P_2
U
U
AH3
SB2N_3
AJ3
2P_3
SB
U
U
AD9
2N_4
SB
AD10
SB2P_4
U
U
AJ1
2N_5
SB
AJ2
SB
2P_5
U
U
AF6
SB
2N_6
AF7
2P_6
SB
U
U
AH1
2N_7
SB
AH2
SB
2P_7
U
U
AF8
SB2N_8
AF9
SB
2P_8
U
U
AG1
SB
2N_9
AG2
SB2P_9
U
U
AH7
2N_10
SB
AH8
SB
2P_10
U
DC resistance < 0.5ohm.
U
AB6
SB
2_COMP
SB
COMP
AG3
U
2_ID
SB
2_ID
SB
U
SB2_VB USSENSE
U
PP
_E9/USB2 _OC0#
_E10/USB 2_OC1#
PP
G
PP_E11 /USB2_OC 2#
G
PP
_E12/USB 2_OC3#
G
G
PP
_E4/DEV SLP0
G
_E5/DEV SLP1
PP
G
PP
_E6/DEV SLP2
G
PP_E8/S ATALED #
G
U
AG4
SB
2_VBUSSENSE
U
U
A9
C9
D9
SB
_OC2#
U
B9
_OC3#
SB
U
J1
J2
_EXT_SCI#
IO
S
J3
H2
PP
_E0/SATAXPCIE0/SATAGP0
G
H3
PP
_E1/SATAXPCIE1/SATAGP1
G
G4
H1
(#543016) Unused SATAGP[2:0]/ GPP_E[2:0] pins must be ter minated to either 3.3 V rail or GND
using 8.2 KΩ to 10 KΩ on the motherboard.
Do not use both pull-up and p ull-down. Either pull-up or pull-down is acceptable.
SB
30_RX_CPU_N1 [36]
U
SB
30_RX_CPU_P1 [36]
U
30_TX_CPU_N1 [36]
SB
U
SB
30_TX_CPU_P1 [36]
U
30_RX_CPU_N2 [36]
SB
U
SB
30_RX_CPU_P2 [36]
U
SB
30_TX_CPU_N2 [36]
U
SB
30_TX_CPU_P2 [36]
U
Cutomer remove IO board USB3.0
SB
30_RX_CPU_N4 [38]
U
30_RX_CPU_P4 [38]
SB
U
SB
30_TX_CPU_N4 [38]
U
30_TX_CPU_P4 [38]
SB
U
SB
_CPU_PN0 [34]
U
_CPU_PP0 [34]
SB
USB3.0 port1
U
SB
_CPU_PN1 [36]
U
_CPU_PP1 [36]
SB
USB3.0 port2
U
SB
_CPU_PN2 [66]
U
_CPU_PP2 [66]
SB
USB3.0 port3
U
_CPU_PN3 [38]
SB
U
SB
_CPU_PP3 [38]
Type C
U
_CPU_PN4 [55]
SB
U
SB
_CPU_PP4 [55]
CAMERA
U
_CPU_PN5 [66]
SB
U
SB
_CPU_PP5 [66]
Card Reader
U
SB
_CPU_PN6 [66]
U
SB
_CPU_PP6 [66]
WLAN
U
SB
_CPU_PN7 [55]
U
SB
_CPU_PP7 [55]
Touch Panel
U
16
03 113R2F-GP
1 2
R
_OC0# [34,35]
SB
U
SB
_OC1# [66]
U
(#543016) When used as DEVSLP , no external pull-up or pu ll-down
_DEVSLP [60]
DD
H
termination required from SAT A Host DEVSLP.
_EXT_SCI#
IO
S
SD
_DEVSLP [63]
S
602 TPAD14-OP-GP
P1
1
T
P1
603 TPAD14-OP-GP
1
T
SSD_PEDET [63]
2_
M
A_LED# [64]
AT
S
SB
2_ID
U
2_VBUSSENSE
SB
U
Follow SKL PDG design guide
Vince,20161201
Vince,20160922
N1
602
R
1
2 3
SRN0J-6-GP
3
(#545659) The xHCI controller supports USB Debug port on all USB3.0 capable ports.
ROR only
V_S0
D3
3
_EXT_SCI#
IO
S
SB
_OC2#
U
_OC3#
SB
U
SB
_OC0#
U
SB
_OC1#
U
4
16
08 10KR2J-3-GP
R
N1
R
8
7
SRN10KJ-6-GP
12
D3
V_S5_PCH
3
601
1
2
3456
AT
A_LED#
S
(#543611)
The SATALED# signal is open-c ollector and requires a wea k external pull-up (8.2 kΩ to 10 kΩ) to Vcc3_3.
TBD
V_S0
D3
3
16
06
R
12
10KR2J-3-GP
2
1
#545659 (SKL_PCH_U_Y_EDS Rev0 .7)
B B
Dell_CY17_CSB_HSIO_Port_Assig nment_Rev0.7_2016-10-18_Rel ease (Wistron)_DELL
A A
<Core Design>
<Core Design>
5
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
1
1
1
A
A
A
Date: Sheetof
Date: Sheetof
4
3
2
Date: Sheetof
1
is
is
is
tron Corporation
tron Corporation
tron Corporation
W
W
W
1F,
1F,
1F,
88, Sec.1, Hsin Tai Wu Rd., Hsichih,
88, Sec.1, Hsin Tai Wu Rd., Hsichih,
88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2
2
2
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
PU
PU
PU
_(PCIE/SATA/USB)
_(PCIE/SATA/USB)
_(PCIE/SATA/USB)
C
C
C
rlord KBL-R
rlord KBL-R
rlord KBL-R
ta
ta
ta
S
S
S
16 1
16 1
16 1
06Friday, December 08, 2017
06Friday, December 08, 2017
06Friday, December 08, 2017
00
00
00
A
A
A
Main Func = PCH
5
4
Remove Power rail +V3.3A_SIP and R1712(DY), 20141118
3
2
1
D
3
D D
R
C C
B B
Vince,20170307
A A
R1709,R1723,R1 703,R1724 merge to RN1704
3V_S5
C_AUX_S5
T
V
3.3A_SIP
+
R
AOZ Power switch, P/N: 074.01334.0093
Low Rds(on)= 5m Ohm
Turn on rise time = 10us
N
1704
R
1
2
3
4 5
SRN10KJ-6-GP
1
730
R
330KR2J-L1-GP
1 2
731
1
R
X
E
1 2
20KR2J-L2-GP
N
1703
R
1
2 3
SRN10KJ-5-GP
717
1
12
DY
100KR2J-1-GP
Vince,20161107 Vince,20161121
V
1.8A
+
R
_PRESENT
C
A
8
C
H_WAKE#
P
7
H_BATLOW#
C
P
6
D11/LANPHYPC
P
G
GPD11 pull high by Intel PDG 1.3 request
#544669 (CRB): 330k.
M
_INTRUDER#
S
#543016 Rev0.7]
[
EXT_PWR_GATE#: Due to a bug on A0, a temporary pullpull-down that is active during the early portion of the power up sequence
T_PWR_GATE#
M
_RSMRST#
P
4
1
M
_PCH_PWROK
P
S_PWROK
Y
S
739 10KR2J-3-GP
1 2
DY
#544669 Rev0.52 CRB:
No PL resistor on THERMTRIP# .
_
CPUPWRGD
H
10KR2J-3-GP
_SUS_PWR_ACK_R
E
M
up resistor will be required to overcome the internal 20k
12
DY
1
714
R
EMI DVT1 0210
A
NWAKE#[24]
L
D
3V_S5
3
R
1 2
Layout note: 3 PAD SHARING
12
1701
D
E
DY
AZ5725-01FDR7G-GP
1
711
0R0603-PAD
R
1 2
DY
732
1
+
TPAD14-OP-GP
S_PWROK[24]
Y
S
R
0R2J-2-GP
V
CCPDSW_3P3
E
SET_OUT#[24,26]
+
Vince,20161121
+VCCMPHYGTAON_1P0
SKL: 1.0V
+VCCMPHYGTAON_1P0(ICCMAX.=2.12A)
V
CCMPHYGTAON_1P0_LS_SIP
+
H_DPWROK
710
1
C
SCD47U10V2KX-GP
1718 0R2J-2-GP
R
12
1711
D
DY
E
AZ5725-01FDR7G-GP
Change location to net PCH_DPWROK
12
DY
Dummy C1710 by it's useless
4
12
1 2
DY
3V_AUX_S5
D
3
1 2
E
_SUS_PWR_ACK_R
M
726
1
R
10KR2J-3-GP
_5V_POK#
V
3
RF request 2016/01/12 modify
1 2
1708
R
0R0402-PAD
1
727
R
100KR2J-1-GP
1 2
701
1
Q
4 3
S2
D2
25
1
G
G
2
1
6
1
D1
S
PJT138KA-GP
5
C
E
DS3 BOM Option
U
SACK#_R
S
1KR2J-1-GP
1
702
R
_RSMRST#
M
P
1 2
_5V_POK_C
V
3
1 2
728
1
R
0R0402-PAD
Vince,20161031
D
0V_S5
1
724
1
R
1710
S
C
2D2U10V2KX-GP
1 2
12
0R6J-L-GP
DY
Vince,20161017
C
P
EC1711 modify to 100k and 0.01uF at DVT1 20150203
3.3A_SIP
V
+
12
701
1
R
10KR2J-3-GP
1
1709
P
T
P
1705
T
TPAD14-OP-GP
1
706 0R0402-PAD
1 2
_RSMRST#
M
P
V
CCPDSW_3P3
(PDG#543016)
WAKE#: Ensure that WAKE# sig nal Trise (Maximum) is <100 ns .
P
D2/LAN_WAKE#
G
R
704 0R0402-PAD
1
1 2
R
1
707 10KR2J-3-GP
1 2
R
D
3V_S5
3
C
1713
E
S
C
12
2D2U10V2KX-GP
DY
U
NPWROK[24,40]
R
EMI DVT1 0210
RF request 2016/01/12 modify
704
1
C
SC10U6D3V3MX-GP
_5V_POK [40,45,52,54]
V
Change dummy property from DS3 to DY
V
_5V_POK [40,45,52,54]
3
3
H_RSMRST# [24]
C
P
C
1712
E
12
DY
D1U16V2KX-3GP
C
S
C
E
1
E
M
12
DY
1706
1KP50V2KX-1GP
C
S
C
H_PLTRST#
P
P_DBRESET#
D
X
_RSMRST#
M
P
CPUPWRGD
_
H
_
VCCST_PWRGD
H
Y
S_PWROK
S
M
_PCH_PWROK
P
H_DPWROK
C
P
_SUS_PWR_ACK_R
U
SACK#_R
S
H_WAKE#
C
P
P
D2/LAN_WAKE#
G
P
D11/LANPHYPC
G
12
1709
D
DY
E
AZ5725-01FDR7G-GP
12
1702
D
E
AZ5725-01FDR7G-GP
3
P
U1K
C
AN10
P_B13/PLTRST#
P
G
B5
Y
S_RESET#
S
AY17
S
MRST#
R
A68
R
OCPWRGD
P
B65
CST_PWRGD
C
V
B6
Y
S_PWROK
S
BA20
H_PWROK
C
P
BB20
S
W_PWROK
D
AR13
P
P_A13/SUSWARN#/SUSPWRDNACK
G
AP11
P_A15/SUSACK#
P
G
BB15
A
KE#
W
AM15
D2/LAN_WAKE#
P
G
AW17
P
D11/LANPHYPC
G
AT15
D7/USB2_WAKEOUT#
P
G
SKYLAKE-U-GP
SYSTEM POWER MANAGEMENT
SKYLAKE_ULT
P
G
1 OF 20
1
P_B12/SLP_S0#
P
G
P
D4/SLP_S3#
G
D5/SLP_S4#
P
G
P
D10/SLP_S5#
G
P_SUS#
L
S
L
P_LAN#
S
D9/SLP_WLAN#
P
G
P
D6/SLP_A#
G
D3/PWRBTN#
P
G
P
D1/ACPRESENT
G
D0/BATLOW#
P
G
P
P_A11/PME#
G
N
TRUDER#
I
P_B11/EXT_PWR_GATE#
P_B2/VRALERT#
P
G
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
AM10
AM11
O_SLP_S5#
I
S
L
P_SUS#
S
P_LAN#
L
S
U
X_EN_WOWL
A
O_SLP_A#
I
S
_PRESENT
C
A
C
H_BATLOW#
P
M
E#
P
_INTRUDER#
M
S
T_PWR_GATE#
X
E
ALERT#
R
V
1
Vince,20161031
1
1
1
1
1
1
IO_SLP_S0# [24,40,60,91]
S
I
O_SLP_S3# [27,40,51,54]
S
O_SLP_S4# [40,54]
I
S
P
1703 TPAD14-OP-GP
T
P
1711 TPAD14-OP-GP
T
1704 TPAD14-OP-GP
P
T
P
1710 TPAD14-OP-GP
T
P
1706 TPAD14-OP-GP
T
S
1707 TPAD14-OP-GP
P
T
1708 TPAD14-OP-GP
P
T
I
O_PWRBTN# [ 24]
BATLOW#:
Pull-up required even if not implemented.
C
_PRESENT
A
C
1707
E
12
DY
D1U16V2KX-3GP
C
S
Vince,20161017
C
_
VCCST_PWRGD
H
12
DY
1 2
716
1
R
100KR2F-L1-GP
12
1
719
R
47KR2F-GP
D
P_DBRESET#
X
S_PWROK
Y
S
L
T_RST#
P
E
SET_OUT#
R
_5V_POK
V
3
12
12
12
1703
D
E
AZ5725-01FDR7G-GP
1705
1704
D
D
DY
DY
E
E
AZ5725-01FDR7G-GP
MI DVT1 0210
E
AZ5725-01FDR7G-GP
711
1
C
SCD01U50V2KX-1GP
12
1708
D
E
R1722 & EC1708 modify to 100 k and 0.01uF at DVT1
AZ5725-01FDR7G-GP
EMI DVT1 0210
D
3
3V_AUX_S5
#543016 Rev0.7
1. VCCST_PWRGD is only 1.0 V tolerant.
2. VCCST_PWRGD must go low d uring Sx pwr states, regardles s of the voltage level of VC CST
737
1
R
1 2
100KR2J-1-GP
M
P
_RSMRST#_M
T_RST#[63,66,91]
L
P
Q
6
N
2N7002KDW-1-GP
1
ote:ZZ.27002.F7C01
R
100KR2J-1-GP
702
2345
1
P
1
715
M
_RSMRST#_R
12
DY
1 2
12
C
DY
1
701
D
RB751V-40H-GP
1 2
R
0R0402-PAD
Reserve by NON DS3 function 20150413
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
C
C
C
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
2
2
2
A
A
A
Date: Sheet
Date: Sheet
2
Date: Sheet
H_PLTRST#
P
1
713
R
0R0402-PAD
1
701
SC220P50V2KX-3GP
KA
C
OK_IN_M [43,44]
A
C
_PRESENT
A
M
_RSMRST#
1
P
P
P
P
720
stron Corporation
stron Corporation
stron Corporation
i
i
i
W
W
W
1
1
1
F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2
2
2
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
U_(POWER MANAGEMENT)
U_(POWER MANAGEMENT)
U_(POWER MANAGEMENT)
arlord KBL-R
arlord KBL-R
arlord KBL-R
t
t
t
S
S
S
1
1
7 106Friday, December 08, 2017
1
7 106Friday, December 08, 2017
1
7 106Friday, December 08, 2017
0
0
0
A
A
A
f
f
f
o
o
o
0
0
0
SSID = PCH
WWW.AliSaler.Com
D D
3
C C
R1835 and R1834 merge to RN1 802
2015/10/06 modify
V_S5_PCH
D3
1
2 3
V1
.8A
+
18
20
R
1 2
10KR2J-3-GP
18
21
R
1 2
10KR2J-3-GP
SERIRQ PH:
PDG: 8.2k
CRB: 10k
5
802
N1
R
PI
_HOLD_ROM
S
4
_WP_ROM
PI
S
SRN1KJ-7-GP
Vince,20161013
IO
_RCIN#
S
I_ALERT#
SP
E
Vince DVT2,20170511
PCH strap pin:
Sampled at rising edge of RSMRST#
eSPI or LPC
SML0ALERT# /
GPP_C5
This signal has a weak internal pull-down.
S
S
PI
S
PI
S
PI
S
This signal has a weak internal pull-down.
0 = LPC Is selected for EC.
1 = eSPI Is selected for EC.
PI
_CLK_ROM[25,91]
_SO_ROM[25,91]
PI
S
PI
_SI_ROM[25,91]
_WP_ROM[25]
PI
_HOLD_ROM[25]
S
_CS_ROM_N0[25]
_CS2#_R[91]
PI
_IRQ#_TPM2[91]
S
FS
_INT1[70]
F
_EN_PCH[60]
DD
H
R1806,R1807,R1808,R1809 merg e to RN1803
2015/10/06 modify
N1
R
1
2
3
4 5
SRN10J-1-GP
1 2
1 2
1 2
TPM
803
8
7
6
18
R
18
R
18
R
Vince,20161017
IO
_RCIN#
RCIN#:
Frequency to Avoid: 33 MHz
I_ALERT#[24, 68]
SP
E
Vince,20161017
S
E
1110R2F-L-GP
120R0402-PAD
260R2J-2-GP
P1
T
P1
T
P1
T
SP
PI
S
PI
S
PI
S
PI
S
S
S
P
R
804TPAD14-OP-GP
805TPAD14-OP-GP
806TPAD14-OP-GP
I_ALERT#
ML
0_ALERT#
S
_CLK_CPU
_SO_CPU
_SI_CPU
_WP_CPU
PI
_HOLD_CPU
_CS_CPU_N0
PI
_SPI_CS2#
CH
08
18
DY
T
12
0R2J-2-GP
C
1
C
1
H
1
4
PM
PU
PU
DD
_SPI_IRQ#
_D4_TP
_D5_TP
_DET#
PCH Prim
V_S5_PCH
D3
3
12
12
DY
C
AV2
AW3
AV3
AW2
AU4
AU3
AU2
AU1
M2
M3
J4
V1
V2
M1
G3
G2
G1
AW13
AY11
PU
S
S
S
S
S
S
S
S
G
G
G
G
G
G
C
C
C
G
G
SKYLAKE-U-GP
18
22
R
1KR2J-1-GP
Vince,20161013
18
23
R
1KR2J-1-GP
1E
SPI - FLASH
PI
0_CLK
0_MISO
PI
Strap
PI
0_MOSI
PI
0_IO2
0_IO3
PI
PI
0_CS0#
0_CS1#
PI
PI
0_CS2#
SPI - TOUCH
_D1/SPI1_CLK
PP
PP
_D2/SPI1_MISO
_D3/SPI1_MOSI
PP
_D21/SPI1_IO2
PP
PP
_D22/SPI1_IO3
_D0/SPI1_CS#
PP
C LINK
L_
CLK
DATA
L_
L_
RST#
PP
_A0/RCIN#
PP
_A6/SERIRQ
PCH strap pin:
BOOT HALT
SPI0_MOSI
This signal has a weak internal pull-up.
0 = ENABLED
1 = DISABLED
WEAK INTERNAL PU
SKYLAKE_ULT
LPC
SMBUS, SMLINK
G
3
PP
_C0/SMBCLK
G
_C1/SMBDATA
PP
G
PP
_C2/SMBALERT#
G
_C3/SML0CLK
PP
G
PP
_C4/SML0DATA
G
_C5/SML0ALERT#
PP
Strap
G
PP
_C6/SML1CLK
G
_C7/SML1DATA
PP
G
PP
_B23/SML1ALERT#/PCHHOT#
G
_A1/LAD0/ESPI_IO0
PP
G
PP
_A2/LAD1/ESPI_IO1
G
_A3/LAD2/ESPI_IO2
PP
G
PP
_A4/LAD3/ESPI_IO3
G
PP
_A5/LFRAME#/ESPI_CS#
G
_A14/SUS_STAT#/ESPI_RESET#
PP
PP
_A9/CLKOUT_LPC0/ESPI_CLK
G
PP
_A10/CLKOUT_LPC1
G
_A8/CLKRUN#
PP
G
2
1
PCH Prim
D3
V_S5_PCH
3
12
24
18
R
DY
1KR2J-1-GP
_SI_CPU
PI
S
I_IO[3..0][24,68]
SP
E
OF 20
5
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
EM
M
EM
M
MB
S
ML
S
ML
S
ML
S
ML
S
ML
S
ML
S
P
P
P
P
P
G
C
E
_SMBCLK
_SMBDATA
_ALERT#
0_SMBCLK
0_SMBDATA
0_ALERT#
1_SMBCLK
1_SMBDATA
1ALERT#
CH
_ESPI_IO0
_ESPI_IO1
CH
CH
_ESPI_IO2
CH
_ESPI_IO3
_ESPI_CLK
CH
PP
_A10/CLKOUT_LPC1
LK
RUN#
DY
SP
12
I_IO[3..0]
18
R
1KR2J-1-GP
S
S
25
E
I_IO0
SP
E
SP
I_IO1
E
I_IO2
SP
E
SP
I_IO3
E
ML
1_SMBCLK [24,26,66]
1_SMBDATA [24,26,66]
ML
Vince,20170106
I_RESET# [24,68]
SP
P1
808 TPAD14-OP-GP
1
T
LK
RUN# [24]
C
806
N1
R
1
8
2
7
3
6
45
SRN15J-GP
I_CS# [24,68]
SP
E
Vince,20161027
_ESPI_IO0
CH
P
CH
_ESPI_IO1
P
_ESPI_IO2
CH
P
CH
_ESPI_IO3
P
Vince,20170106
.8A
V1
+
Vince,20161017
18
18
R
RUN#
8K2R2F-1-GP
1 2
DY
EM
_SMBDATA
M
EM
_SMBCLK
M
LK
C
ML
1_SMBDATA
S
ML
1_SMBCLK
S
0_SMBDATA
ML
S
ML
0_SMBCLK
S
VT1 0210, Reserve by Intel MOW
D
ML
1ALERT#
S
MB
_ALERT#
S
EM
_SMBCLK
M
_SMBDATA
EM
M
D3
V_S0
3
01
18
Q
ote:ZZ.27002.F7C01
N
1
6
2345
2N7002KDW-1-GP
N1
807
R
8
7
6
SRN2K2J-4-GP
18
36
R
2K2R2J-2-GP
N1
R
4
SRN2K2J-1-GP
4
SRN10KJ-5-GP
12
12
811
D3
V_S5_PCH
3
1
2
3
45
18
37150KR2J-GP
R
1
23
N1
810
R
1
V_S0
D3
3
23
CH
_SMBDATA [12,13]
P
CH
_SMBCLK [ 12,13]
P
Vince,20161013
06
18
R
CH
_ESPI_CLK
P
Vince,20161017
1 2
15R2F-2-GP
SC10P50V2JN-4GP
E
C1
12
804
DY
SP
E
I_CLK [24,68]
Vince,20170110
B B
V_S0
D3
3
1 2
27
18
R
R
1
2 3
SRN10KJ-5-GP
R
1
2 3
SRN10KJ-5-GP
1 2
18
28
R
A A
DY
N1
812
N1
813
DY
Vince,20170117
_PCIE_SD_REQ#
LK
C
10KR2J-3-GP
LK
_PCIE_PEG_REQ#
C
4
_PCIE_NVME_REQ#
LK
C
LK
_PCIE_TBT_REQ#
C
4
_PCIE_LAN_REQ#
LK
C
LK
_PCIE_WLAN_REQ#
C
10KR2J-3-GP
WLAN
Vince,20161026
Vince,20161026
SSD
PU
1J
C
LK
_PCIE_VGA#[66]
C
LK
_PCIE_VGA[66]
C
_PCIE_PEG_REQ#[66]
LK
C
_CLK1_CPU#[66]
EG
P
EG
_CLK1_CPU[66]
P
_PCIE_WLAN_REQ#[66]
LK
C
LK
_PCIE_LAN_REQ#
C
LK
_PCIE_SD_REQ#
TA_CLK_CPU#[63]
SA
M
SA
TA_CLK_CPU[6 3]
M
_PCIE_NVME_REQ#[63]
LK
C
C
_PCIE_NVME_REQ#
LK
C
LK
_PCIE_TBT_REQ#
C
AR10
AT10
D42
C42
B42
A42
AT7
D41
C41
AT8
D40
C40
B40
A40
AU8
E40
E38
AU7
OUT_PCIE_N0
LK
C
LK
OUT_PCIE_P0
C
_B5/SRCCLKREQ0#
PP
G
LK
OUT_PCIE_N1
C
OUT_PCIE_P1
LK
C
PP
_B6/SRCCLKREQ1#
G
LK
OUT_PCIE_N2
C
LK
OUT_PCIE_P2
C
_B7/SRCCLKREQ2#
PP
G
OUT_PCIE_N3
LK
C
LK
OUT_PCIE_P3
C
_B8/SRCCLKREQ3#
PP
G
LK
OUT_PCIE_N4
C
LK
OUT_PCIE_P4
C
PP
_B9/SRCCLKREQ4#
G
LK
OUT_PCIE_N5
C
OUT_PCIE_P5
LK
C
PP
_B10/SRCCLKREQ5#
G
SKYLAKE-U-GP
CLOCK SIGNALS
SKYLAKE_ULT
Vince,20170120 common part request
1 2
15 10MR2J-L-GP
18
R
X
1 2
12
1804
C
SC9P50V2DN-GP
0 OF 20
1
CI
E_CLK_XDP_N
LK
C
LK
OUT_ITPXDP_P
C
G
X
OUT_ITPXDP#
PD
8/SUSCLK
L24_IN
TA
X
TA
L24_OUT
X
CL
K_BIASREF
TC
R
TC
R
RT
CRST#
S
RST#
TC
R
F43
E43
BA17
E37
E35
E42
AM18
X1
AM20
X2
AN18
AM16
S
X
X
X
R
R
S
R
US
CLK
TA
L24_IN
L24_OUT
TA
K_BIASREF
CL
_X1
TC
TC
_X2
C_RST#
RT
TC
_RST#
P
E_CLK_XDP_P
CI
P
12
07
18
R
DY
1 2
18
R
2K7R2F-GP
ntel recommend: 2.71k ohm 1%
I
_RST#[25]
TC
R
0R2J-2-GP
03
Vince,20161027
18
02
XTAL-32D768KHZ-91-GP
.00A_SIP
V1
+
TC
_X1
R
TC
_X2
R
12
1803
C
SC9P50V2DN-GP
Vince,20170328
1
P1
802 TPAD14-OP-GP
T
1
803 TPAD14-OP-GP
P1
T
US
_CLK [24]
S
V1.05S_AXCK_LCPLL
+
Vince,20170203
SRN20KJ-1-GP
12
06
18
C
SC1U10V2KX-1GP
#514849)
(
TA
L24_IN
X
TA
L24_OUT
X
Vince,20161223
_AUX_S5
TC
R
1
23
N1
801
R
4
21
18
01
G
12
C
G
AP
SC1U10V2KX-1GP
-OPEN
04
18
R
TA
L24_IN_R
X
12
0R2J-2-GP
U22
05
18
R
TA
L24_OUT_R
X
12
0R2J-2-GP
U22
S
R
05
18
SCD1U16V2KX-3GP
12
E
C1
DY
806
Layout: Place at the open do or area.
5
4
3
2
Metal cover XTAL
C
U22
12
U22
S
RT
C_RST#
TC
_RST#
SCD1U16V2KX-3GP
12
E
C1
DY
807
23
1802
R
1MR2J-1-GP
CLK
US
<Core Design>
<Core Design>
<Core Design>
it
le
Title
Title
T
PU
PU
PU
C
C
C
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
2
2
2
A
A
A
Date: Sheet
Date: Sheet
Date: Sheet
18
01
X
XTAL-24MHZ-87-GP
U22
4 1
C
U22
C1
803
E
DY
1 2
D7P50V2BN-GP
C4
S
W
W
W
2
2
2
_(LPC/SPI/SMBUS/CL/CLK)
_(LPC/SPI/SMBUS/CL/CLK)
_(LPC/SPI/SMBUS/CL/CLK)
rlord KBL-R
rlord KBL-R
rlord KBL-R
ta
ta
ta
S
S
S
1
01
18
12
SC15P50V2JN-2-GP
02
18
12
SC15P50V2JN-2-GP
tron Corporation
tron Corporation
tron Corporation
is
is
is
1F
1F
1F
, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
18 1
18 1
18 1
f
f
f
o
o
o
A
A
A
06Friday, December 08, 2017
06Friday, December 08, 2017
06Friday, December 08, 2017
00
00
00
5
SSID = PCH
D D
Strap pin:
Port B /
Port C Detected
DDPB_CTRLDATA
DDPC_CTRLDATA
Sampled at rising edge of PCH_PWROK
*
*
These two signals have weak in ternal pull-down.
Vince,20161107
fTPM: SW TPM
TPM:HW TPM
C C
PCH strap pin:
Flash Descriptor Security Overide/
Intel ME Debug Mode
HDA_SDOUT
The internal pull-down is disabled after
PLTRST# deasserts
Low = Default
High = Enable
3
D
3V_S5
fTPM
TPM
12
R
913
1
10KR2J-3 -GP
T
12
R
10KR2J-3 -GP
M_ID
P
912
1
Vince,20161102
TPAD14-O P-GP
PCH strap pin:
NO REBOOT
*
HDA_SPKR
The internal pull-down is disabled after
PLTRST# deasserts
Low = Enable (Default)
*
High = Disable
4
0 = Port B is not dete cted.
1 = Port B is detected.
0 = Port C is not detecte d.
1 = Port C is detected.
H
A_SDIN0[27]
D
1
T
1906
P
D
G
PU_PW ROK[24,66]
S
KR[27]
P
H
A_SYNC
D
H
A_BITCLK
D
H
A_SDOUT
D
H
D
A_RST#
D
IC_PCH_CL K
M
P
OJECT_ID1
R
P
OJECT_ID0
R
P
OJECT_ID2
R
P
R
OJECT_ID3
T
3
P
D
M_ID
3V_S0
BA22
AY22
BB22
BA21
AY21
AW22
J5
AY20
AW20
AK7
AK6
AK9
AK10
H5
D7
D8
C8
AW5
1KR2J-1-G P
R
006
2
1 2
DY
C
U1G
P
AUDIO
H
D
A_SYNC/I2S0_SFRM
H
A_BLK/I2S0_SCLK
D
H
D
A_SDO/I2S0_TXD
H
D
A_SDI0/I2S0_RXD
H
D
A_SDI1/I2S1_RXD
H
A_RST#/I2S1_SCLK
D
G
P_D23/I2S_MCLK
P
I
S1_SFRM
2
I
2
S1_TXD
G
P_F1/I2S2_SFRM
P
G
P_F0/I2S2_SCLK
P
G
P
P_F2/I2S2_TXD
G
P
P_F3/I2S2_RXD
G
P
P_D19/DMIC_CLK0
G
P_D20/DMIC_DATA0
P
G
P
P_D17/DMIC_CLK1
G
P
P_D18/DMIC_DATA1
G
P_B14/SPKR
P
SKYLAKE-U-GP
S
KR
P
3
7
SKYLAKE_ULT
SDIO/SDXC
G
P
P_G0/SD_CMD
G
P_G1/SD_DATA0
P
G
P_G2/SD_DATA1
P
G
P_G3/SD_DATA2
P
G
P
P_G4/SD_DATA3
G
P
P_G5/SD_CD#
G
P_G6/SD_CLK
P
G
P_G7/SD_WP
G
P
P_A17/SD_PWR_EN#/ISH_GP7
P
G
P_A16/SD_1P8_SEL
P
S
D
_RCOMP
G
P
Vince,20170721
+
V
1.8A
R
915
1
RORL
10KR2J-3 -GP
1 2
P
OJECT_ID0
R
OF 20
P_F23
+
V
RORL
1 2
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
1.8A
R
916
1
10KR2J-3 -GP
P
OJECT_ID1
R
2
G
C
6_THM_D IS#
C
S
U_A16_T P
P
_RCOMP
D
+
DY
V
1.8A
1 2
1
1 2
R
1
200R2F-L -GP
R
918
1
10KR2J-3 -GP
P
OJECT_ID2
R
G
C
6_THM_D IS# [24]
K
_LED_BL _DET [65]
B
T
1902
P
901
TPAD14-O P-GP
Vince,20170106
+
V
1.8A
R
DY
10KR2J-3 -GP
1 2
P
R
Vince,20161026
920
1
OJECT_ID3
1
R
914
1
10KR2J-3 -GP
1 2
R
1
H
A_CODEC _SYNC[27]
D
E
C
1901
H
B B
1 2
SC10P50 V2JN-4GP
12
DY
A A
D
C
1902
A_CODEC _BITCLK
H
D
A_RST#
DY
E
SCD1U16 V2KX-3GP
H
D
A_CODEC _BITCLK[27]
H
A_CODEC _SDOUT[27]
D
R
909 1KR2J-1-G P
M
E
_FW P_EC[24]
R1907,R1912 merge to RN1902
2015/10/06 modify
5
1
4
0R0402-P AD
1 2
908
SRN33J-5 -GP-U
2 3
1
R
N
1902
H
D
A_SYNC
Vince,20170106
H
D
A_BITCLK
H
4
D
A_SDOUT
3
DY
1 2
DY
1 2
R
917
1
10KR2J-3 -GP
2
R
919
1
10KR2J-3 -GP
DY
1 2
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A
A
A
3
3
3
Date: Sheet
Date: Sheet
Date: Sheet
R
921
1
10KR2J-3 -GP
DY
1 2
W
W
W
i
i
i
stron Corporation
stron Corporation
stron Corporation
2
2
2
1
1
1
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
C
C
C
P
P
P
U_(AUDIO/SDIO/SDXC)
U_(AUDIO/SDIO/SDXC)
U_(AUDIO/SDIO/SDXC)
S
S
S
t
t
t
arlord KBL-R
arlord KBL-R
arlord KBL-R
1
0
0
0
0
0
0
A
A
o
o
o
1
1
1
9 106Friday, December 08, 2 017
9 106Friday, December 08, 2 017
9 106Friday, December 08, 2 017
A
f
f
f
SSID = PCH
WWW.AliSaler.Com
5
C2
002
12
E
SC1KP50V2KX-1GP
009
N2
R
1
2 3
OPS
SRN10KJ-5-GP
D3
V_S0
3
D D
DEBUG
1 2
1 2
DEBUG
1 2
1 2
1 2
1 2
1 2
1 2
DY
Vince,20161012
20
4851KR2J-1-GP
R
4951KR2J-1-GP
20
R
20
4210KR2J-3-GP
R
4310KR2J-3-GP
20
R
20
4410KR2J-3-GP
R
4510KR2J-3-GP
20
R
20
4610KR2J-3-GP
R
4710KR2J-3-GP
20
R
PCH strap pin:
No Reboot
GSPI0_MOSI /
GPP_B18
The signal has a weak internal pull-down.
C C
V_S5_PCH
D3
3
R
R
Sampled at rising edge of PCH_PWROK
0 = Disable “No Reboot” mode.
1 = Enable “No Reboot” mode (PCH will disable the TCO
Timer system reboot feature). This function is useful
when running ITP/XDP.
20
40 10KR2J-3-GP
1 2
20
41 10KR2J-3-GP
1 2
D
4
D
AR
T_2_CTXD_DRXD
U
T_2_CRXD_DTXD
AR
U
LU
ETOOTH_EN
B
_PANEL_EN
BC
D
FS
_INT2
F
DET#
B_
K
R_
CAM_DET#
I
_ID
PK
S
TC
_DET#
R
IO
_EXT_WAKE#
S
GP
D
GP
U_HOLD_RST#
GP
U_PWR_EN
U_HOLD_RST# [66]
hange to Dummy 20150402
C
PU_EVENT#[66]
G
C6
_FB_EN[66]
G
D
#570213 Intel CRB
20
R
20
R
BC
_PANEL_EN[55]
Vince,20161012
PTP
PCH Prim
V_S5_PCH
D3
3
12
20
07
R
DY
1KR2J-1-GP
RB
_BIT
N
12
19
20
R
DY
1KR2J-1-GP
D3
V_S0
3
12
20
55
R
DY
150KR2J-GP
READ_MODE
D_
S
12
20
56
R
DY
20KR2J-L2-GP
03 0R2J-2-GP
1 2
GC6_20
04 0R2J-2-GP
1 2
GC6_20
B
AR
U
AR
T_2_CTXD_DRXD[68]
U
IO
S
0_SDA_TCH_PAD[65]
2C
I
2C
0_SCL_TCH_PAD[65]
I
P2
027 TPAD14-OP-GP
T
028 TPAD14-OP-GP
P2
T
P2
020 TPAD14-OP-GP
T
V1
+
Vince,20161026
4
PK
_ID[29]
S
ETOOTH_EN[66]
LU
T_2_CRXD_DTXD[68]
_EXT_WAKE#[24]
B_
DET#[65]
K
1
1
.8A_SIP
1
Vince,20161123
PU
G
C6
G
RAM_ID1
V
RB
_BIT
N
D_
S
B
2C
I
2C
I
_EVENT_MCP#
_FB_EN_MCP
READ_MODE
RD_ID2
OA
0_SDA_TCH_PNL
0_SCL_TCH_PNL
EM
_CONFIG0
M
AH10
AH11
AH12
AF11
AF12
AN8
AP7
AP8
AR7
AM5
AN7
AP5
AN5
AB1
AB2
W4
AB3
AD1
AD2
AD3
AD4
AH9
PU
1F
C
LPSS ISH
_B15/GSPI0_CS#
PP
G
PP
_B16/GSPI0_CLK
G
_B17/GSPI0_MISO
PP
G
PP
_B18/GSPI0_MOSI
G
_B19/GSPI1_CS#
PP
G
PP
_B20/GSPI1_CLK
G
_B21/GSPI1_MISO
PP
G
PP
_B22/GSPI1_MOSI
G
_C8/UART0_RXD
PP
G
PP
_C9/UART0_TXD
G
_C10/UART0_RTS#
PP
G
PP
_C11/UART0_CTS#
G
PP
_C20/UART2_RXD
G
PP
_C21/UART2_TXD
G
_C22/UART2_RTS#
PP
G
PP
_C23/UART2_CTS#
G
U7
PP
_C16/I2C0_SDA
G
U6
_C17/I2C0_SCL
PP
G
U8
_C18/I2C1_SDA
PP
G
U9
PP
_C19/I2C1_SCL
G
_F4/I2C2_SDA
PP
G
PP
_F5/I2C2_SCL
G
PP
_F6/I2C3_SDA
G
_F7/I2C3_SCL
PP
G
PP
_F8/I2C4_SDA
G
_F9/I2C4_SCL
PP
G
SKYLAKE-U-GP
RA
M_ID1
V
Strap
3
DY
D3
12
DY
12
SKYLAKE_ULT
V_S0
20
R
10KR2J-3-GP
R
10KR2J-3-GP
3
OF 20
6
D_
CAM_DET#
P2
_D9/ISH_SPI_CS#
PP
G
PP
_D10/ISH_SPI_CLK
G
_D11/ISH_SPI_MISO
PP
G
PP
_D12/ISH_SPI_MOSI
G
_D5/ISH_I2C0_SDA
PP
G
PP
_D6/ISH_I2C0_SCL
G
PP
_D7/ISH_I2C1_SDA
1.8V Only
G
G
PP
_D8/ISH_I2C1_SCL
G
PP
_F10/I2C5_SDA/ISH_I2C2_SDA
G
_F11/I2C5_SCL/ISH_I2C2_SCL
PP
G
PP
_D13/ISH_UART0_RXD/SML0BDATA
G
PP
_D14/ISH_UART0_TXD/SML0BCLK
G
_D15/ISH_UART0_RTS#
PP
G
PP
_D16/ISH_UART0_CTS#/SML0BALERT#
PP
_C12/UART1_RXD/ISH_UART1_RXD
G
PP
_C13/UART1_TXD/ISH_UART1_TXD
G
_C14/UART1_RTS#/ISH_UART1_RTS#
PP
G
PP
_C15/UART1_CTS#/ISH_UART1_CTS#
G
PP
G
PP
G
PP
G
PP
G
PP
G
PP
G
_A12/BM_BUSY#/ISH_GP6
PP
G
_A18/ISH_GP0
_A19/ISH_GP1
_A20/ISH_GP2
_A21/ISH_GP3
_A22/ISH_GP4
_A23/ISH_GP5
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
I
I
G
3
D
R
SH
_I2C0_SDA
_I2C0_SCL
SH
I
I
EM
M
V
U
U
B
U
U
I
G
G
G
G
G
G
G
N2_INT1_ISH
SE
U_HOLD_RST#
GP
TC
_DET#
1_SDA
2C
2C
1_SCL
_CHB_EN
M_ID2
RA
AR
T0_RTS#
T0_CTS#
AR
RD_ID1
OA
AR
T1_RTS#
T1_CTS#
AR
_KB_DISABLE
SH
SE
N_INT1_ISH
SE
N_INT2_ISH
N2_INT1_ISH
SE
SE
N2_INT2_ISH
O_INT_ISH
YR
YR
O_DRDY_ISH
N_INT1_ISH
SE
Vince,20161014
YR
O_DRDY_ISH
G
D3
V_S0
3
12
10
20
R
29
20
30
BBY
10KR2J-3-GP
RD_ID1
OA
B
ROR
12
R
09
20
10KR2J-3-GP
B
D3
V_S0
3
12
OPS
RD_ID2
OA
12
UMA
P2
1
T
20
21 0R2J-2-GP
1 2
R
ISH
20 0R2J-2-GP
20
1 2
R
ISH
007 TPAD14-OP-GP
P2
1
T
Vince,20161026
U_PWR_EN [66]
GP
D
1
012 TPAD14-OP-GP
P2
T
1
P2013 TPAD14-OP-GP
T
1
P2
014 TPAD14-OP-GP
T
FS
F
1
016 TPAD14-OP-GP
P2
T
1
P2
017 TPAD14-OP-GP
T
20
23 0R2J-2-GP
R
20
24 0R2J-2-GP
R
25 0R2J-2-GP
20
R
20
26 0R2J-2-GP
R
27 0R2J-2-GP
20
R
20
28 0R2J-2-GP
R
20
31
R
1 2
DY
100KR2J-1-GP
20
35
R
1 2
DY
100KR2J-1-GP
20
34
R
1 2
DY
100KR2J-1-GP
BIOS strap pin:
05
20
R
10KR2J-3-GP
BIOS UMA/DIS Strap pin
08
20
R
10KR2J-3-GP
_INT2 [70]
1 2
1 2
1 2
1 2
1 2
1 2
006 TPAD14-OP-GP
CAM_DET# [55]
R_
I
DY
DY
UMA
DIS
2
G
G
G
R
EN
S
EN
S
N_INT2_ISH
SE
N2_INT2_ISH
SE
YR
O_INT_ISH
TC
_DET# [25]
SOR_I2C_SDA [55,70]
SOR_I2C_SCL [55,70]
1 2
100KR2J-1-GP
1 2
100KR2J-1-GP
1 2
100KR2J-1-GP
GPP_C11
BOARD_ID2
0
1
1
D3
V_S0
3
007
N2
R
SRN1KJ-7-GP
_I2C0_SCL
SH
I
1
2 3
N2
R
1
DY
2 3
SRN2K2J-1-GP
4
008
4
SH
_I2C0_SDA
I
1_SCL
2C
I
2C
1_SDA
I
(PDG#543016) Ensure that all I2C interface on-board termin ations are pulled up
to the same voltage rail as the device/end point.
Vince,20161102
SE
N_INT1 [55]
G
N_INT2 [55]
SE
G
SE
N2_INT1_C [70]
G
SE
G
YR
G
YR
G
20
R
DY
20
R
DY
20
R
DY
N2_INT2_C [70]
O_INT_C [70]
O_DRDY [55]
32
33
36
(PDG#543016) If the UART/GPI O functionality is also not us ed,
the signals can be left as no-connect.
Vince,20170111
V_S5
D3
3
12
01
20
R
10KR2J-3-GP
SH
I
_KB_DISABLE_R
Vth(max)=1.1V
20
01
Q
6
S1
D1
1
G2
D2
4 3
S2
PJT138KA-GP
1
_KB_DISABLE
SH
I
25
G
MODE#
B_
N
D3V_S5
3
1 2
B_
N
R
10KR2J-3-GP
MODE# [24]
20
50
B B
A A
<Core Design>
<Core Design>
<Core Design>
tron Corporation
tron Corporation
tron Corporation
is
is
is
W
W
W
1F
1F
1F
, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
2
2
2
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
_(LPSS/ISH)
_(LPSS/ISH)
_(LPSS/ISH)
PU
PU
PU
rlord KBL-R
rlord KBL-R
rlord KBL-R
ta
ta
ta
S
S
S
1
Taipei Hsien 221, Taiwan, R.O.C.
20 1
20 1
20 1
o
o
o
A
A
A
06Friday, December 08, 2017
06Friday, December 08, 2017
06Friday, December 08, 2017
f
f
f
5
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A
A
A
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
C
C
C
2
2
2
00
00
00
Main Func = PCH
5
4
3
2
1
SKYLAKE_ULT
1.8V Only
Vince,20161013
5 OF 20
1
AK15
CPGPPA
C
V
AG15
C
CPGPPB
V
Y16
CPGPPC
C
V
Y15
C
CPGPPD
V
T16
C
CPGPPE
V
AF16
CPGPPF
C
V
AD15
C
CPGPPG
V
CPRIM_3P3_V19
CPRIM_1P0_T1
C
CATS_1P8
C
V
CRTCPRIM_3P3
C
CRTC_AK19
V
CRTC_BB14
C
V
PRTC
C
D
C
CCLK1
V
C
CCLK2
V
C
CCLK3
V
CCLK4
C
V
CCLK5
C
V
CCLK6
C
V
V
1.8A_SIP
+
12
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
C
2
SC1U10V2KX-1GP
108
C
V
V
C
V
P
P_B0/CORE_VID0
G
P_B1/CORE_VID1
P
G
+
V
V
V
V
CCPRIM_CORE
+
DY
V
1.8A_SIP
CRTCEXT
C
.85A_VID0
0
0
.85A_VID1
12
C
2
102
V1.8A_SIP
+
+
V
+
V
+
V
+
V
+
V
+
V
+
V
+
V
+
V
+
SC1U10V2KX-1GP
V
3.3A_SIP
1.00A_SIP
1.8A_SIP
3.3A_SIP
C
1.00A_SIP
CCCLK2
1.00A_SIP
CCCLK4
CCCLK5
1.00A_SIP
+
V
3.3A_SIP
+
2
112
1 2
1
1
V
CCDSW_1P0
V
CCPRTC_3P3
+
SCD1U16V2KX-3DLGP
P
T
P
T
C
2
SC1U10V2KX-1GP
103
12
2101 TPAD14-OP-GP
2102 TPAD14-OP-GP
+
V
1.00A_SIP
CCPRTC_3P3
V
+
C
2
118
12
T
C_AUX_S5
R
CCMPHYGTAON_1P0_LS_SIP
V
+
1.00A_SIP
V
+
1.00A_SIP
V
+
V
1.00A_SIP
+
V
1.00A_SIP
+
Layout Note:
SC1U10V2KX-1GP
12
1uF:
C
2
C2101 near AB19
SC1U10V2KX-1GP
121
C2104 near K17
C2116 near A10
C2121 near AL1
C
C
2
2
SC1U10V2KX-1GP
101
104
12
12
SCD1U16V2KX-3DLGP
12
SC1U10V2KX-1GP
C
2
117
1 2
1 2
1 2
1 2
1 2
1 2
Layout Note:
0.1uF:
C2118 near AK19
1uF:
C2117 near Ak19
V
CCPRTC_3P3
+
2
106
R
0R0603-PAD
CCAMPHYPLL_1P0
V
+
107
2
R
0R0603-PAD
CCAPLL_1P0
V
+
108
2
R
0R0603-PAD
CCCLK2
V
+
109
2
R
0R0603-PAD
V
CCCLK4
+
2
110
R
0R0603-PAD
V
CCCLK5
+
2
111
R
0R0603-PAD
D D
120
2
C
S
C
12
12
1U10V2KX-1GP
2101
C
E
DY
S
C
D1U25V2KX-GP
D
5V_S0
1
V
3.3A_SIP
+
C C
B B
102
2
R
0R2J-2-GP
V
CCMPHYGTAON_1P0_LS_SIP
+
1 2
DY
2
101
1 2
R
0R0402-PAD
V
CCMPHYGTAON_1P0_LS_SIP
+
V
CCMPHYGTAON_1P0_LS_SIP
+
CCPRIM_CORE
V
+
V
CCDSW_1P0
+
+
CCAMPHYPLL_1P0
V
+
V
CCAPLL_1P0
+
+
V
CCPDSW_3P3
+
+
+
V
3.3A_SIP
+
V
1.00A_SIP
+
V
3.3A_SIP
+
C
2
105
12
V
1.00A_SIP
1.00A_SIP
V
CCPAZIO
V
3.3A_SIP
V
SC1U10V2KX-1GP
12
+
V
1.00A_SIP
C
2
SC1U10V2KX-1GP
106
PU1O
C
C
CPRIM_1P0
V
CPRIM_1P0
C
V
C
CPRIM_1P0
V
C
CPRIM_CORE
V
C
CPRIM_CORE
V
CPRIM_CORE
C
V
C
CPRIM_CORE
V
C
PDSW_1P0
D
CMPHYAON_1P0
C
V
L1
C
CMPHYAON_1P0
V
C
CMPHYGT_1P0_N15
V
C
CMPHYGT_1P0_N16
V
CMPHYGT_1P0_N17
C
V
C
CMPHYGT_1P0_P15
V
CMPHYGT_1P0_P16
C
V
CAMPHYPLL_1P0
C
V
C
CAMPHYPLL_1P0
V
CAPLL_1P0
C
V
CPRIM_1P0_AB17
C
V
C
CPRIM_1P0_Y18
V
CDSW_3P3_AD17
C
V
C
CDSW_3P3_AD18
V
CDSW_3P3_AJ17
C
V
CHDA
C
V
C
CSPI
V
C
CSRAM_1P0
V
CSRAM_1P0
C
V
C
CSRAM_1P0
V
C
CSRAM_1P0
V
C
CPRIM_3P3_AJ21
V
C
CPRIM_1P0_AK20
V
CAPLLEBB
C
V
SKYLAKE-U-GP
Layout Note:
1uF:
SCD1U16V2KX-3DLGP
C2105 near V19
C2106 near AK17
C2107 near AG15
C2109 near Y16
C2110 near T16
C2111 near AJ19
CPU POWER 4 OF 4
AB19
AB20
P18
AF18
2.57A
AF19
V20
V21
AL1
K17
N15
N16
N17
P15
P16
K15
L15
V15
AB17
Y18
AD17
AD18
AJ17
AJ19
AJ16
AF20
AF21
T19
T20
AJ21
AK20
N18
C
C
C
C
2
2
2
2
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SCD1U16V2KX-3DLGP
109
107
110
12
12
111
12
12
12
SC22U6D3V3MX-1-GP
C
2
122
Layout Note:
1uF:
C2116 near A10
22uF:
C2115 near K19
C2119 near N20
C2122 near L19
3
<Core Design>
<Core Design>
<Core Design>
stron Corporation
stron Corporation
stron Corporation
i
i
i
W
W
W
1
1
1
F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2
2
2
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
2
2
2
A
A
A
Date: Sheet
Date: Sheet
2
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
U_(POWER1)
U_(POWER1)
U_(POWER1)
P
P
P
C
C
C
arlord KBL-R
arlord KBL-R
arlord KBL-R
t
t
t
S
S
S
1
0
0
0
A
A
2
1 106Friday, December 08, 2017
2
1 106Friday, December 08, 2017
2
1 106Friday, December 08, 2017
A
f
f
f
o
o
o
CCAMPHYPLL_1P0
V
+
12
DY
A A
5
C
2
113
SC22U6D3V3MX-1-GP
Layout Note:
22uF:
C2113 near K15
CCAPLL_1P0
V
+
12
DY
4
SC22U6D3V3MX-1-GP
C
2
114
Layout Note:
22uF:
C2113 near K15
+
1.00A_SIP
V
12
CCCLK2
CCCLK4
V
+
SC1U10V2KX-1GP
SC22U6D3V3MX-1-GP
C
C
2
2
116
115
12
DY
CCCLK5
V
V
+
+
SC22U6D3V3MX-1-GP
C
2
119
12
DY
DY
0
0
0
5
WWW.AliSaler.Com
4
3
2
1
Main Func = PCH
D D
C
PU
1T
AW69
AW68
TAL
24_OUT_U42
X
C C
AW48
AU56
C7
U12
U11
H11
SV
R
SV
R
SV
R
SV
R
SV
R
SV
R
SV
R
SV
R
SKYLAKE-U-GP
D_AW69
D_AW68
D_AU56
D_AW48
D_C7
D_U12
D_U11
D_H11
SKYLAKE_ULT
SPARE
R
R
SV
R
SV
R
SV
R
SV
R
SV
R
SV
R
0 OF 20
2
SV
D_F6
D_E3
SV
D_C11
D_B11
D_A11
D_D12
D_C12
D_F52
F6
E3
C11
B11
A11
D12
C12
F52
TAL
X
24_IN_U42
Vince,20170110
Metal cover XTAL
For U42
02
22
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24_IN_U42
X
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24_OUT_U42
B B
X
R
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22
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U42
0R2J-2-GP
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24_IN_U42_R
X
12
23
01
22
12
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03
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X
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01
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02
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Vince,20161223
<Core Design>
<Core Design>
<Core Design>
W
W
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tron Corporation
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is
A A
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Title
Title
it
T
C
C
C
PU
PU
PU
S
S
S
ta
ta
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5
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
4
4
4
A
A
A
Date: Sheet
Date: Sheet
4
3
Date: Sheet
2
is
88, Sec.1, Hsin Tai Wu Rd., Hsichih,
88, Sec.1, Hsin Tai Wu Rd., Hsichih,
88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1F,
1F,
1F,
2
2
2
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
_(RSVD)
_(RSVD)
_(RSVD)
rlord KBL-R
rlord KBL-R
rlord KBL-R
22 1
22 1
22 1
00
00
00
A
A
A
f
f
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06Friday, December 08, 2017
06Friday, December 08, 2017
06Friday, December 08, 2017
5
Main Func = PCH
4
3
2
1
C
U1Q
P
C
U1P
P
AA2
AA4
AA65
AA68
AB15
AB16
AB18
AB21
AB8
AD13
AD16
AD19
AD20
AD21
AD62
AD8
AE64
AE65
AE66
AE67
AE68
AE69
AF10
AF15
AF17
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH6
AH63
AH64
AH67
AJ15
AJ18
AJ20
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AK8
AL28
AL32
AL35
AL38
AL45
AL48
AL52
AL55
AL58
AL64
A67
A70
AF1
AF2
AF4
AJ4
AL2
AL4
A5
GND 1 OF 3
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
SKYLAKE-U-GP
SKYLAKE_ULT
D D
T
P
2309T PAD14-OP-GP
T
P
2311T PAD14-OP-GP
T
P
2310T PAD14-OP-GP
C C
B B
A
1
_TP
5
A
1
7_TP
6
A
1
0_TP
7
1
6 OF 20
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
AL65
S
S
AL66
S
S
AM13
S
S
AM21
S
S
AM25
S
S
AM27
S
S
AM43
S
S
AM45
S
S
AM46
S
S
AM55
S
S
AM60
S
S
AM61
S
S
AM68
S
S
AM71
S
S
AM8
S
S
AN20
S
S
AN23
S
S
AN28
S
S
AN30
S
S
AN32
S
S
AN33
S
S
AN35
S
S
AN37
S
S
AN38
S
S
AN40
S
S
AN42
S
S
AN58
S
S
AN63
S
S
AP10
S
S
AP18
S
S
AP20
S
S
AP23
S
S
AP28
S
S
AP32
S
S
AP35
S
S
AP38
S
S
AP42
S
S
AP58
S
S
AP63
S
S
AP68
S
S
AP70
S
S
AR11
S
S
AR15
S
S
AR16
S
S
AR20
S
S
AR23
S
S
AR28
S
S
AR35
S
S
AR42
S
S
AR43
S
S
AR45
S
S
AR46
S
S
AR48
S
S
AR5
S
S
AR50
S
S
AR52
S
S
AR53
S
S
AR55
S
S
AR58
S
S
AR63
S
S
AR8
S
S
AT2
S
S
AT20
S
S
AT23
S
S
AT28
S
S
AT35
S
S
AT4
S
S
AT42
S
S
AT56
S
S
AT58
S
S
T
P
2307T PAD14-OP-GP
T
P
2304T PAD14-OP-GP
T
P
2312T PAD14-OP-GP
T
2305T PAD14-OP-GP
P
T
2306T PAD14-OP-GP
P
A
1
1_TP
V
A
1
V
71_TP
B
1
1_TP
7
B
1
A
1_TP
B
1
A
2_TP
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV1
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA10
BA14
BA18
BA2
BA23
BA28
BA32
BA36
BA45
F68
GND 2 OF 3
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
SKYLAKE-U-GP
SKYLAKE_ULT
1
7 OF 20
C
P
U1R
BA49
V
S
S
BA53
V
S
S
BA57
V
S
S
BA6
V
S
S
BA62
V
S
S
BA66
V
S
S
BA71
V
S
S
BB18
V
S
S
BB26
V
S
S
BB30
V
S
S
BB34
V
S
S
BB38
V
S
S
BB43
V
S
S
BB55
V
S
S
BB6
V
S
S
BB60
V
S
S
BB64
V
S
S
BB67
V
S
S
BB70
V
S
S
C1
V
S
S
C25
V
S
S
C5
V
S
S
D10
V
S
S
D11
V
S
S
D14
V
S
S
D18
V
S
S
D22
V
S
S
D25
V
S
S
D26
V
S
S
D30
V
S
S
D34
V
S
S
D39
V
S
S
D44
V
S
S
D45
V
S
S
D47
V
S
S
D48
V
S
S
D53
V
S
S
D58
V
S
S
D6
V
S
S
D62
V
S
S
D66
V
S
S
D69
V
S
S
E11
V
S
S
E15
V
S
S
E18
V
S
S
E21
V
S
S
E46
V
S
S
E50
V
S
S
E53
V
S
S
E56
V
S
S
E6
V
S
S
E65
V
S
S
E71
V
S
S
F1
V
S
S
F13
V
S
S
F2
V
S
S
F22
V
S
S
F23
V
S
S
F27
V
S
S
F28
V
S
S
F32
V
S
S
F33
V
S
S
F35
V
S
S
F37
V
S
S
F38
V
S
S
F4
V
S
S
F40
V
S
S
F42
V
S
S
BA41
V
S
S
B
1
A
71_TP
B
67_TP
B
B
70_TP
B
C
_TP
1
E
7
1_TP
1
1
1
1
T
2303 TPA D14-OP-GP
P
T
P
2302 TPA D14-OP-GP
T
P
2301 TPA D14-OP-GP
T
P
2308 TPA D14-OP-GP
T
2313 TPA D14-OP-GP
P
G10
G22
G43
G45
G48
G52
G55
G58
G60
G63
G66
H15
H18
H71
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
F8
G5
G6
J11
J13
J25
J28
J32
J35
J38
J42
J8
L11
L16
L17
GND 3 OF 3
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
SKYLAKE-U-GP
SKYLAKE_ULT
1
8 OF 20
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
L18
S
S
L2
S
S
L20
S
S
L4
S
S
L8
S
S
N10
S
S
N13
S
S
N19
S
S
N21
S
S
N6
S
S
N65
S
S
N68
S
S
P17
S
S
P19
S
S
P20
S
S
P21
S
S
R13
S
S
R6
S
S
T15
S
S
T17
S
S
T18
S
S
T2
S
S
T21
S
S
T4
S
S
U10
S
S
U63
S
S
U64
S
S
U66
S
S
U67
S
S
U69
S
S
U70
S
S
V16
S
S
V17
S
S
V18
S
S
W13
S
S
W6
S
S
W9
S
S
Y17
S
S
Y19
S
S
Y20
S
S
Y21
S
S
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
W
W
W
i
i
i
stron Corporation
stron Corporation
stron Corporation
2
2
2
1
1
1
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
T
tle
Title
Title
i
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A
A
A
3
3
3
Date: Sheet
Date: Sheet
Date: Sheet
C
C
C
P
P
P
U_(VSS)
U_(VSS)
U_(VSS)
S
S
S
t
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arlord KBL-R
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o
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2
2
2
3 106Friday, December 08, 2 017
3 106Friday, December 08, 2 017
3 106Friday, December 08, 2 017
f
f
1
f
0
0
0
0
0
0
A
A
A
5
WWW.AliSaler.Com
Main Func = KBC
D0
V_S5
1
24
02
R
1 2
412
8
7
6
409
8
7
6
410
8
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6
411
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76
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12
24
17
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DY
0R0402-PAD
Layout Note:
Need very close to EC
SO
0
K
SO
1
K
2
SO
K
SO
3
K
SO
4
K
SO
5
K
6
SO
K
SO
7
K
3V
ALW_EC
+
8
SO
K
SO
10
K
11
SO
K
SO
12
K
13
SO
K
SO
14
K
15
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K
16
SO
K
AS
K_SATA_LED#[64]
M
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1 2
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GPIO123 (BSS_STRAP)GPIO102 (CR_STRAP)
Already pull low
on CPU side
CH
P
P2
406
1
T
TPAD14-OP-GP
2418
R
0R2J-2-GP
1 2
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24
08
Q
G
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2N7002K-2-GP
non-PreDrive
non-PreDrive
Vince,20161018
_RSMRST#
Just for Starload placement
2015/09/23 modify
D D
3V
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+
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R
1
2
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3
4 5
SRN100KJ-5-GP
N2
R
1
2
non-PreDrive
3
4 5
SRN100KJ-5-GP
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R
1
2
non-PreDrive
3
4 5
SRN100KJ-5-GP
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R
1
2
non-PreDrive
3
4 5
SRN100KJ-5-GP
C C
LK
RUN#[18]
C
U_PWROK[19,66]
GP
D
ALL_SYS_PWRGD assert,
Vince,20161101
delay 10ms; PCH_PWROK assert.
For eSPI
3VALW_EC
+
24
50
R
100KR2J-1-GP
1 2
SO
9
K
49
24
R
100KR2J-1-GP
DY
B B
1 2
100KR2J-1-GP
12
N2
403
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1
2
3
4 5
SRN10KJ-6-GP
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404
R
1
2
3
4 5
SRN10KJ-6-GP
O
D
V_S5
D3
3
RE
F_CPU
V
C
24
SCD1U16V2KX-3DLGP
06
20SCD1U16V2KX-3DLGP
16SCD1U16V2KX-3DLGP
21SCD1U16V2KX-3DLGP
C
C
C
24
24
24
12
12
0
SI
8
K
SI
1
7
K
2
SI
6
K
SI
3
K
7
SI
8
K
SI
6
7
K
5
SI
6
K
4
SI
K
Vince,20161011
Vince,20161013
AS
K_SATA_LED#
M
VE
R_CURRENT_P8#[66]
Vince,20161018
NT
#_Typec[37]
I
YS
_PWROK[17]
S
BA
T_PRES#[43]
P
D8
V_S5_PWROK[40,54]
1
TC
RST_ON[25]
R
_RSMRST#[17]
CH
P
KLT_EN_EC
_B
L
C_
A
SB
_POWERSHARE_VBUS_EN[34]
U
P_
WAKE_KBC#[4,65]
T
PWROK[17,40]
UN
R
ES
ET_OUT#[17,26]
R
US
_CLK[18]
Vince,20170203
S
Vince,2017328 common part re quest
SC18P50V2JN-1DLGP
2015/09/22 modify
401
D2
E
AZ5725-01FDR7G-GP
12SCD1U16V2KX-3DLGP
11SCD1U16V2KX-3DLGP
C
C
24
24
12
12
12
Just for Starload placement
2015/09/23 modify
[0..16][65]
SO
K
SI
[0..7][65]
K
_TP_SIO[65]
LK
C
_TP_SIO[65]
AT
D
IO
_PWRBTN#[17]
S
_SLP_S0#[17,40,60,91]
IO
S
SP
I_IO[3..0][18,68]
E
Vince,20160926
I_CS#[18,68]
SP
E
I_CLK[18,68]
SP
E
SP
I_ALERT#[18,68]
E
24
74
1 2
R
0R0402-PAD
SPI_RESET#[18,68]
E
_CL_SIO#[70]
ID
L
22
24
1 2
R
25
1 2
MI DVT1 0210
E
0R0402-PAD
402
P2
1
T
TPAD14-OP-GP
25
24
1 2
R
01
24
X
1 2
XTAL-32D768KHZ-91-GP
Microchip: Use CL=9p Xtal
_P
ROCHOT# [4,44,46]
H
DIS[43]
24
C
12
1 2
0R0603-PAD
10SCD1U16V2KX-3DLGP
C
24
12
DY
24
R
0R2J-2-GP
24
R
46
14SCD1U16V2KX-3DLGP
C
24
23
，
12
1 2
PI
G
= 10p
C
0R0402-PAD
O052/SPI_IO2
1 2
13SCD1U16V2KX-3DLGP
C
24
12
SO
0
K
SO
1
K
2
SO
K
SO
3
K
SO
4
K
SO
5
K
SO
6
K
7
SO
K
SO
8
K
SO
9
K
10
SO
K
SO
11
K
SO
12
K
13
SO
K
SO
14
K
SO
15
K
16
SO
K
AP
_LED#
C
SI
0
K
SI
1
K
2
SI
K
SI
3
K
SI
4
K
5
SI
K
SI
6
K
7
SI
K
C_
SLP_S0IX#
E
SP
I_IO0
E
I_IO1
SP
E
SP
I_IO2
E
SP
I_IO3
E
RUN#_EC
LK
C
PU
_PWR_LEVEL
G
EN#
P_
T
T_EN_EC
KL
B
SB
_EN#
U
_XTAL2
EC
M
EC
_XTAL1_R
M
24
24
C
SC18P50V2JN-1DLGP
24
C
ALW_EC
3V
+
f don't need RTC alarm wake up,
I
can change to 3D3V_AUX_S5
0R0402-PAD
CV
E
12
28
24
BC
K
2
1U16V2KX-3DLGP
PI
O027/KS O00/PVT _IO1
14
S
CD
O015/KS O01/PVT _CS#
PI
G
15
PIO016 /KSO02/P VT_SC LK
G
16
PI
O017/KS O03/PVT _IO0
G
37
O045/BC M_INT1#/K SO04
PI
G
38
PI
O046/BC M_DAT1/K SO05
G
39
PIO047 /BCM_CLK 1/KSO0 6
G
50
PI
O025/KS O07/PVT _IO2
G
46
O055/PW M2/KSO0 8/PVT_ IO3
PI
G
68
PI
O102/KS O09/CR_ STRAP
G
72
O106/KS O10
PI
G
74
PI
O110/KS O11
G
75
O111/KS O12
PI
G
76
PIO112 /PS2_CL K1A/KS O13
G
77
O113/PS 2_DAT1 A/KSO1 4
PI
G
86
PI
O125/KS O15
G
92
O132/KS O16
PI
G
93
PIO140 /KSO17
G
G
98
O143/KS I0/DTR#
PI
99
G
PI
O144/KS I1/DCD#
6
G
O005/SMB 00_DAT A/SMB00 _DATA1 8/KSI2
PI
7
G
PI
O006/SMB 00_CLK /SMB00_ CLK18/K SI3
104
G
O147/KS I4/DSR#
PI
105
G
PI
O150/KS I5/RI#
107
G
O151/KS I6/RTS#
PI
108
G
PI
O152/KS I7/CTS#
G
78
PIO114 /PS2_CL K0
79
G
PI
O115/PS 2_DAT0
52
G
O026/PS 2_CLK1 B
PI
88
G
PI
O127/PS 2_DAT1 B
G
59
PI
O040/LA D0/ESPI _IO0
60
G
O041/LA D1/ESPI _IO1
PI
61
G
PI
O042/LA D2/ESPI _IO2
62
G
O043/LA D3/ESPI _IO3
PI
58
G
PI
O044/LF RAME#/ES PI_CS #
56
G
O064/LR ESET#
PI
57
G
PIO034 /PCI_CL K/ESPI _CLK
63
G
PI
O067/CL KRUN#
55
G
PI
O063/SE R_IRQ/E SPI_A LERT#
10
G
O011/SMI #/EMI_INT #
PI
49
G
PIO060 /KBRST
53
G
PI
O061/LP CPD#/ES PI_RE SET#
66
G
O100/EC _SCI#
PI
G
32
O126/SHD _SCLK
PI
28
G
PI
O133/SHD _IO0
29
G
O134/SHD _IO1
PI
30
G
PI
O135/SHD _IO2
31
G
O136/SHD _IO3
PI
27
G
PI
O123/SHD _CS#
G
67
PIO101 /SPI_C LK
69
G
PI
O103/SP I_IO0
71
G
O105/SP I_IO1
PI
42
G
PI
O052/SP I_IO2
33
G
O062/SP I_IO3
PI
3
G
PI
O001/SP I_CS#/3 2KHZ_O UT
G
13
ES
ET_IN#/G PIO014
48
R
O057/VC C_PWR GD
PI
73
G
PI
O107/RE SET_OUT #
G
125
TAL2
123
X
TA
L1
X
MEC1416-NU-D0-GP
4
Vince,20161013
Vince,20170525
1.
V1
8VALW_EC
.8A
+
+
62
24
R
12
0R0402-PAD
23SCD1U16V2KX-3DLGP
C
24
TR
V
O050/TA CH0
PI
PI
O051/TA CH1
G
G
PIO053 /PWM0
O054/PW M1
PI
G
G
O056/PW M3
PI
G
PI
O002/PW M7
G
O156/LE D1
PI
G
PI
O104/LE D2
G
PI
O035/SB -TSI_CL K
G
REF_CP U
V
O145/IC SP_CLO CK
PI
O146/IC SP_DAT A
G
P_MCLR
CS
I
O/GPIO0 04
GP
B
CI
_OUT/GPI O036
V
CI
_IN1#/GP IO162
V
_IN0#/GP IO163
CI
V
O160/DA C_0
PI
G
PI
O161/DA C_1
G
AC
D
O124/CMP _VOUT0
PI
G
PI
O020/CMP _VIN0
G
O165/CMP _VREF0
PI
G
O120/CMP _VOUT1
PI
G
PIO021 /CMP_VIN1
G
PI
O024/AD C7
G
O023/AD C6/A20M
PI
G
PI
O022/AD C5
G
O153/AD C4
PI
G
PI
O154/AD C3
G
O155/AD C2
PI
G
PI
O122/AD C1
G
O121/AD C0
PI
G
DC_VRE F
A
Layout Note:
DY
12
54
_33_18
8
T_CHG_SMBDAT
BA
P
9
T_CHG_SMBCLK
BA
P
11
PU
_THM_SMBDAT
G
12
_THM_SMBCLK
PU
G
89
ype
C_SMBDA
T
91
ypeC_SMBCLK
T
96
MODE#
B_
N
97
ID
_CL_SIO_TAB#
L
40
1_TACH
AN
F
41
44
45
47
34
35
36
4
1
AT
2_LED#
B
106
1_LED#
AT
B
70
80
81
90
94
_P
ECI
H
95
RE
F_CPU
V
101
P_CLOCK
CS
I
102
CS
P_DATA
I
87
CS
P_CLR
I
119
120
YS
PWR_PRES
S
121
ON
LW
A
126
DM
I_EC_DET#
H
127
OW
ER_SW_IN#
P
128
23
_THM_DIS#_EC
C6
G
24
W_
ACAVIN_NB
H
22
_VREF
85
MP
_VOUT0
C
20
MP
_VIN0
C
25
EF0
CR
V
83
ROCHOT
P
21
_VIN1
MP
C
26
CD
_TST
L
118
117
116
109
OD
EL_ID
M
110
_A
DP_R
I
111
RD_ID
OA
B
113
CD
_VCC_TEST_EN
L
114
ATT
_B
I
115
3V
ALW_EC
+
12
24
22
C
C_
AGND
E
1U16V2KX-3DLGP
S
CD
12
GP
U_PWROK [19,66]
D
_AUX_S5
TC
R
72
24
R
1 2
BAT
3
122
5
19
43
65
82
10
T
V
V
V
V
V
V
TR
TR
TR
TR
TR
TR
V
BA
O007/SMB 01_DAT A/SMB01 _DATA1 8
PI
PIO010 /SMB01_C LK/SMB0 1_CLK1 8
G
PI
O012/SMB 02_DAT A/SMB02 _DATA1 8
G
O013/SMB 02_CLK /SMB02_ CLK18
PI
G
PI
O130/SMB 03_DAT A/SMB03 _DATA1 8
G
PIO131 /SMB03_C LK/SMB0 3_CLK1 8
G
PI
O141/SMB 04_DAT A/SMB04 _DATA1 8
G
O142/SMB 04_CLK /SMB04_ CLK18
PI
G
G
PIO030 /BCM_INT0 #/PWM4
PI
O031/BC M_DAT0/P WM5
G
G
O032/BC M_CLK0/P WM6
PI
G
PI
O157/LE D0/TST_ CLK_O UT
G
PI
O116/TF DP_DAT A/UART_ RX
G
O117/TF DP_CLK /UART_T X
PI
G
O033/PE CI_DAT /SB_TS I_DAT
PI
G
PI
G
YSPWR_ PRES/GP IO003
S
CI_OVR D_IN/GPI O164
V
PI
O166/CMP _VREF1 /UART_C LK
G
S
CAP
V
V
V
A
V
V
V
V
R_
SS
SS
VS
SS_VBAT
SS
SS
SS
7
1
4
4
1
5
6
8
18
00
1
112
124
AGND
CAP
E
V
C_
R_
12
24
18
C
S
C1
U10V2KX-1GP
45
24
R
1 2
0R0402-PAD
C_
AGND
E
Connect GND and AGND planes via either
0R resistor or connect directly.
C6
_THM_DIS#_EC
G
24
71 0R2J-2-GP
R
2431
R
10KR2J-3-GP
DY
1 2
RD_ID
OA
B
08
24
C
S
Vince,20161013
For Typec SMBUS
E_WAKE#
CI
P
RE
ATH_LED#
B
1 2
24
37
R
SC100P50V2JN-3GP
C
43R2J-GP
12
24
05
DY
Need very close to EC, PDG: <0.5 inches.
24
20
1 2
R
0R0402-PAD
29SCD1U16V2KX-3DLGP
24
1 2
C
2470
12
R
0R0402-PAD
Vince,20161018
CD
_TST [55]
L
Vince,20161107
ALW_EC
3V
+
A00
12
CD
1U16V2KX-3DLGP
AGND
C_
E
Vince,20161018
1
1
3V
ALW_EC
+
Vince,20160929
3
12
43
24
R
49K9R2F-L-GP
PCB_REV
12
44
24
R
100KR2F-L1-GP
BA
T_CHG_SMBDAT [43,44]
P
BA
T_CHG_SMBCLK [43,44]
P
MODE# [20]
B_
N
OL
_DOWN# [66]
V
B_
LED_PWM [65]
K
EE
P [27]
B
AN
1_PWM [26]
F
_UP# [66]
OL
V
WAKE# [17]
AN
L
S_
ID [43]
P
407TPAD14-OP-GP
P2
T
Vince,20161018
405
P2
T
TPAD14-OP-GP
FWP_EC [19]
E_
M
OS
T_DEBUG_TX [68]
H
_DIS#_R [65]
TP
P
ECI_CPU [4]
_P
H
B_
MUTE# [27]
N
LW
ON [40]
A
w_
ACAV_IN [44]
h
Vince,20161018
_THM_DIS# [19]
C6
G
MP
_VOUT0 [26]
C
MP
_VIN0_R [26]
C
SB
_PWR_SHR_EN_L# [34]
U
AN
EL_BKEN_EC [55]
P
_EXT_WAKE# [20]
IO
S
ATT
_B
I
12
41
24
C
AGND
C_
E
ouch Panel PH internally.
T
CH_REPORT_SW
OU
T
R2498,R2499 merge to RN2407
2015/10/06 modify
_UP#
OL
V
OL
_DOWN#
V
24
30
R
10KR2J-3-GP
Vince,20161114
Vince,20161114
Vince,20161012
TC
_AUX_S5
R
12
DY
1KR2J-1-GP
3V
ALW_EC
+
24
24
R
20KR2F-L-GP
1 2
12
24
09
C
12
S
CD
01U50V2KX-1GP
Vince,20160929
Vince,20160929
24
26
R
12
330R2J-3-GP
Need very close to EC
Need very close to EC
SC2200P50V2KX-2GP
29 10KR2J-3-GP
24
1 2
R
DY
407
N2
R
SRN10KJ-5-GP
ID
_CL_SIO#
L
D3
V_S0
3
1 2
D3
V_AUX_S5
3
64
24
R
DY
ref = 1.117
V
temp around 85
24
48
R
1
0K
R2F-2-GP
DM
H
Vince,20170105
oo
st_mon [44]
b
Layout Note:
1234
24
02
D
RB751V-40H-GP
K A
Change symbol part number, be cause origin symbol is DELL OBS part
03
24
D
RB751V-40H-GP
KA
AN
_TACH1 [26]
F
eDP backlight Control from PCH
_B
KLT_EN_EC
Vince,20170206
12
63
24
R
1KR2J-1-GP
12
24
54
R
100KR2J-1-GP
I_EC_DET# [57]
24
Q
1
G
DY
S
2
2N7002K-2-GP
Vince,20161018
ACAVIN_NB
W_
H
24
R
For Typec charge detect modfy 2016/01/04
V_S0
D3
3
V_S5
D3
3
Just for Starload placement
2015/09/23 modify
L
D3
V_AUX_S5
3
12
15
24
C
17
DY
S
_VCC_TEST_EN
CD
CD
L
3
1U16V2KX-3DLGP
D
SB
_EN#
U
75
12
0R0402-PAD
DP_R
_A
I
330R2J-3-GP
12
35
24
C
C_
AGND
E
SC2200P50V2KX-2GP
Move schematic, 20141118
MP
_VIN1
C
12
DY
36
24
C
SC2200P50V2KX-2GP
12
24
21
R
20150116 2040Change symbol part number, be cause origin symbol is DELL OBS part
Vince,20161107
OU
CH_REPORT_SW [55]
T
IN_OK [43]
C_
D
455
R2
P
56
24
R
DY
DY
12
24
R
100KR2J-1-GP
12
150KR2F-L-GP
12
115KR2F-GP
2
35
24
R
1 2
0R0402-PAD
36
D3
V_S5
3
12
34
24
R
100KR2J-1-GP
D_
IA [44]
A
Vince,20170203
OD
EL_ID
M
_B
KLT_EN [8,55]
L
Vince,20161018
CD
_VCC_TEST_EN [55]
L
SB
_EN# [35,66]
U
Vince,20170721
D3
V_S5
3
24
42
R
200KR2F-L-GP
MODEL_ID
C
12
24
07
SCD1U16V2KX-3DLGP
AGND
C_
E
B_
CLOSE#_2[70]
K
3V
HG
C
Q2412 and Q2413 merge
Vince,20161031
PU
G
PU
G
12
12
24
41
R
100KR2F-L1-GP
ALW_EC
+
AT
2_LED#
B
D3
V_S5
3
_AMBER_LED#[64]
24014/12/23 mo dify
D3
V_S0
3
100KR2J-1-GP
1 2
AP
_LED#
C
V_S0
D3
3
_THM_SMBDAT
_THM_SMBCLK
CG
4_I2C_SDA[37]
C
4_I2C_SCL[37]
CG
C
StarlordR-L[KBL-U]
StarlordR-L[KBL-R]
StarlordR-L[SKL-U]
61
24
1 2
R
0R0402-PAD
15
24
Q
S
D
DY
G
24
16
Q
1
2
3 4
2N7002KDW-1-GP
89
24
R
S
D
G
24
14
Q
47
24
1 2
R
0R0402-PAD
59
24
1 2
R
0R0402-PAD
2N7002KDW-1-GP
2N7002K-2-GP
N
6
5
ote:ZZ.27002.F7C01
2N7002K-2-GP
3V
ALW_EC
+
_CL_SIO_TAB#
ID
L
05
26
Q
1
2
TypeC
3 4
ML
ML
D3
1_SMBDATA
S
1_SMBCLK
S
N
6
ote:ZZ.27002.F7C01
5
1
V_S5
D3
3
24
96
R
100KR2J-1-GP
DY
1 2
T_WHITE_LED# [64]
AT
B
V_S5
3
AT
P_
1_LED#
B
AP
_LED#_R [65]
C
ML
1_SMBDATA [18,26,66]
S
ML
1_SMBCLK [18,26,66]
S
Reserve by NON DS3 function 20150413
SRN2K2J-1-GP
ype
C_SMBDA
T
C_SMBCLK
ype
T
D3
V_S5
3
405
N2
R
1
8
2
ID
_CL_SIO#
L
EN#[65]
T
604
N2
R
7
3
6
4 5
SRN100KJ-5-GP
3V
ALW_EC
+
1
23
4
ype
C_SMBDA [38]
T
Vince,20161123
ype
C_SMBCLK [38]
T
IO
_EXT_SCI# [16]
S
3V
ALW_EC
+
3V
ALW_EC
+
3V
ALW_EC
+
24
80
R
100KR2J-1-GP
14
CS
P_CLOCK
I
DY
24
CS
P_DATA
I
R
1 2
1 2
OS
T_DEBUG_TX
H
4K7R2J-2-GP
CS
P_CLR
I
4
B3
D
7
1
2
3
4
5
6
8
A
CES-CON6-58-GP
EC Debug
Power Switch Logic(PSL)
_PWRBTN#[66]
BC
K
3
24
32
R
1 2
1KR2J-1-GP
Vince,20170516
_AUX_S5
TC
R
51
24
R
100KR2J-1-GP
1 2
OW
P
12
SC2D2U10V3KX-1DLGP-U
ER_SW_IN#
24
26
C
<Core Design>
<Core Design>
<Core Design>
it
le
Title
Title
T
BC
BC
BC
K
K
K
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
1
1
1
A
A
A
ta
ta
ta
S
S
S
Friday, December 08, 2017
Friday, December 08, 2017
Friday, December 08, 2017
Date: Sheetof
Date: Sheetof
2
Date: Sheetof
1
is
is
is
tron Corporation
tron Corporation
tron Corporation
W
W
W
1F,
1F,
1F,
88, Sec.1, Hsin Tai Wu Rd., Hsichih,
88, Sec.1, Hsin Tai Wu Rd., Hsichih,
88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2
2
2
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Nuvoton NPCE285PA0DX
Nuvoton NPCE285PA0DX
Nuvoton NPCE285PA0DX
rlord KBL-R
rlord KBL-R
rlord KBL-R
24 1
24 1
24 1
06
06
06
A A
Vince,20161013
Vince,20161031
BA
T_CHG_SMBCLK
P
T_CHG_SMBDAT
BA
P
_PWR_SHR_EN_L#
SB
U
BA
T_PRES#
P
IO
_EXT_SCI#
S
Vince,20161018
5
R
1234
SRN4K7J-8-GP
1 2
73 10KR2J-3-GP
24
R
1 2
24
15 10KR2J-3-GP
R
Just for Starload placement
2015/09/23 modify
3V
ALW_EC
+
3V
ALW_EC
+
N2
402
00
00
00
A
A
A
5
Main Func = SPI Flash
R
2
501
4K7R2J-2 -GP
3
3V_S5_P CH
D
1 2
SPI Flash ROM(8M) for PCH
D D
4
3
3V_SPIVCC 1
D
12
C
2
SC10U10 V5KX-2GP
501
DY
3
D
3V_S5_P CH
3
12
R
2
515
0R0402-P AD
12
C
502
2
DY
SCD1U16 V2KX-3GP
2
72.25128.0B1
QUAD/DUAL fast read DUAL fast readSource
O
O
O O
1
SFDP
O
O
O
O
O
Change to Dummy 20150402
S
I25
P
S
P
I_CS_ROM_ N0[18]
E
SC4D7P5 0V2BN-GP
1 2
R
2
S
P
I_SO_ROM[18,91]
S
I_WP_R OM[1 8]
P
C C
507
1 2
R
10R2F-L-G P
2
508 10R 2F-L-GP
2502
C
S
I_SO_ROM_ R
P
S
P
I_WP_R OM_R
S
S
12
DY
I_SO_ROM_ R
P
P
I_WP_R OM_R
1
C
#
S
2
S
O
/SIO1
3
S
I
O2
4
G
D
N
MX25L12 873FM2I-10G-GP
8
V
C
C
S
I
O3
S
C
S
/SIO0
I
S
7
I_HOLD_RO M_R
P
S
6
P
LK
I_CLK_ROM _R
S
5
I_SI_ROM_R
P
3
D
3V_SPIVCC 1
1 2
R
503
2
10R2F-L-G P
12
12
2501
DY
C
E
SC4D7P50V2BN-GP
E
DY
SC10P50 V2JN-4GP
2503
C
Vince,20161018
S
I_CLK_ROM _R
P
S
I_SI_ROM_R
P
S
I_HOLD_RO M [18]
P
1 2
1 2
R
505
2
10R2F-L-G P
R
506 10R2 F-L-GP
2
S
P
I_CLK_ROM [18,9 1]
S
P
I_SI_ROM [18,91]
Vince,20161018
Delivery Voltage 3.19V
B B
Main Func = RTC
+
TC_VCC
R
(when R2510 1K6 ohm)
3
D
3V_AUX_ S5
12
R
2
510
0R2J-2-GP
3
D
3V_RTC_ SYS
12
R
2
517
47KR2F-G P
DY
D
501
2
1
2
BAS40C-2 -GP
R
C_AUX_S 5
T
3
12
C
503
2
SCD47U2 5V3KX-1-DL-GP
Q
503
2
N
ote:ZZ.27002.F7C01
1
6
2
A A
12
R
504
2
10MR2J-L -GP
R
C_RST#[1 8]
T
5
3 4
2N7002K DW-1-GP
Vince,20161027
5
4
R
T
C_DET# [2 0]
12
R
SCD1U16V2KX-3GP
12
E
C
2504
DY
3
509
2
100KR2J -1-GP
R
CRST_ON [24]
T
<Core Design>
<Core Design>
<Core Design>
W
W
W
i
i
i
stron Corporation
stron Corporation
stron Corporation
2
2
2
1
1
1
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A
A
A
3
3
3
Friday, December 08, 20 17
Friday, December 08, 20 17
Friday, December 08, 20 17
Date: Sheet
Date: Sheet
2
Date: Sheet
F
F
F
ash/RTC
ash/RTC
ash/RTC
l
l
l
S
S
S
t
t
t
arlord KBL-R
arlord KBL-R
arlord KBL-R
2
2
2
5 106
5 106
5 106
1
0
0
0
0
0
0
A
A
o
o
o
A
f
f
f
5
WWW.AliSaler.Com
4
3
2
1
Main Func = Thermal Sensor
D3
3
D3
V_S0
3
01
26
12
12
1
1 2
1 2
7718
7718
C
DY
SC10U6D3V3MX-GP
7718_DXP
CT
N
12
26
06
C
SC470P50V3JN-2GP
DY
7718_DXN
CT
N
Layout Note:
C2607 close THM2601
7718
T
26
02
C
SCD1U16V2KX-3DLGP
12
26
C
7718
SC2200P50V2KX-2GP
RT#
LE
A
RIT#
_C
D D
3
26
03
Q
PMBS3904-1-GP
2
7718
.System Sensor, Put on palm rest
2
Layout Note:
Both DXN and DXP routing 10 mil trace width and 10 mil spa cing.
V_S0
D3
3
C C
03 7K5R2F-1-GP
26
R
04 7K5R2F-1-GP
26
R
ML
1_SMBDATA[ 18,24,66]
S
1_SMBCLK[18,24,66]
ML
S
HM
261
T
1
DD
CL
V
S
T
0R2J-2-GP
26
01
R
2
7718
+
DA
D
S
3
-
LE
RT#
D
4
ES
R
HE
RM_SYS_SHDN#
T
RIT#
_C
T
NCT7718W-GP
ET_OUT#[17, 24]
A
ND
G
_C
RIT#
07
12
DY
ote:ZZ.27002.F7C01
Q
N
6
7718
2N7002KDW-1-GP
8
7
6
LE
RT#
A
5
V_S0
26
01
Q
G
S
2N7002K-2-GP
D3
V_S0
3
1
23
602
N2
R
SRN2K2J-1-GP
7718
4
1
2345
12
08
26
DY
C
02
26
D
DY
HM_SML1_DATA
T
HM
_SML1_CLK
T
_SML1_CLK
HM
T
HM
_SML1_DATA
T
12
09
26
DY
C
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
E_HW_SHUTDOWN# [40]
UR
12
10
26
C
SCD1U16V2KX-3GP
1 2
DY
26
15 0R2J-2-GP
R
KBC T8
_VOUT0
MP
C
D3
3
DY
P
DVT1 0210, for T8 function
3V
V_S0
+
12
09
26
R
10R2F-L-GP
26
10
R
NTC-100K-8-GP
D3
V_S5
3
07 10KR2J-3-GP
26
1 2
R
26
02
R
1 2
0R0402-PAD
ALW_EC
12
08
26
R
27KR2F-L-GP
VT1 0210, for T8 function
D
12
12
C
SCD1U16V2KX-3DLGP
26
12
D_
IN1_C
V
Close to KBC
VD_IN1 for system thermal sensorClose to Thermal sensor
12
F
F
C
26
13
C
SC100P50V2JN-3GP
V_
5
_TACH1[24]
AN
AN
1_PWM[24]
_VOUT0 [24]
MP
C
26
R
1 2
S0
_VIN0_R [24]
MP
11
0R0402-PAD
26
12
R
1 2
0R0402-PAD
PWM FAN1
_VCC_1
AN
F
SC4D7U6D3V3KX-GP
SCD1U16V2KX-3DLGP
C
C
26
26
04
05
12
12
DY
13
26
1 2
R
26
0R0402-PAD
14
1 2
R
0R0402-PAD
26
01
D
C
26
KA
03
12
DY
51V30-GP
B5
R
_VCC_1
AN
F
_TACH1_C
AN
F
AN
_PWM1_C
F
P2604
FT
1
A
AN
_TACH1_C
F
_PWM1_C
AN
F
_VCC_1
AN
F
Layout Note:
Signal Routing Guideline:
Trace width = 15mil
SC2200P50V2KX-2GP
1
AN
F
5
1
2
3
4
6
ACES-CON4-29-GP
FT
P2601
1
A
P2602
FT
1
A
P2603
FT
1
A
B B
A A
<Core Design>
<Core Design>
<Core Design>
tron Corporation
tron Corporation
tron Corporation
is
is
is
W
W
W
1F
1F
1F
, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
, 88, Sec.1, Hsin Tai Wu R d., Hsichih,
2
2
2
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1
26 1
26 1
26 1
f
f
f
o
o
o
A
A
A
06
06
06
5
Title
Title
Title
RMAL NCT7718W/Fan
RMAL NCT7718W/Fan
RMAL NCT7718W/Fan
HE
HE
HE
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
2
2
2
A
A
A
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
rlord KBL-R
rlord KBL-R
rlord KBL-R
ta
ta
ta
S
S
S
Friday, December 08, 2017
Friday, December 08, 2017
Friday, December 08, 2017
00
00
00
5
4
3
2
1
Main Func = Audio
moat
V
703
0R0603-PAD
5
A
A
H
K
_S0
D_AGND
U
D_AGND
U
D
A_SPKR_R
C_BEEP_R
B
C
E
C
E
C
E
C
E
C
E
R
moat
2707 SC1KP50V2KX-1GP
1 2
DY
2706 SC1KP50V2KX-1GP
1 2
DY
2705 SCD1U25V2KX-GP
1 2
DY
2704 SC1KP50V2KX-1GP
1 2
DY
2703 SCD1U25V2KX-GP
1 2
DY
2
706
1 2
0R0805-PAD
Layout Note:
2
701
D
1
2
BAT54C-11-GP
U
D_PC_BEEP_C
A
3
12
C
1 2
2
717
R
2K2R2J-2-GP
2
720
U
D_PC_BEEP_R
A
SCD1U16V2KX-3DLGP
5
V_AVDD
+
2
12
12
2
711
C
Layout Note:
Place close to Pin 40
4D7U6D3V3KX-GP
C
U
D_AGND
A
S
704
2
C
SC1U50V3KX-GP
1 2
U
D_AGND
U
D_AGND
A
U
D_AGND
A
N
2701
R
2 3
1
SRN1KJ-7-GP
R
1 2
4
D
3V_S0
3
D D
D
8V_S0
1
724
2
R
1 2
0R0402-PAD
2
R
1 2
0R0805-PAD
12
731
701
2
C
SCD1U16V2KX-3DLGP
+
3
V_AVDD
P
VDD
C
12
724
2
C
SC4D7U6D3V3KX-GP
Close pin 21
1.5A
V
_S0
5
C C
D
3V_S0
3
1
D
8V_S0
1
D
5V_S0
moat
713
2
1 2
R
0R0402-PAD
2
705
1 2
R
DY
710 0R2J-2-GP
2
1 2
R
DY
0R2J-2-GP
2
702
R
1 2
0R0805-PAD
704
2
R
1 2
0R0805-PAD
5
V_PVDD
+
3
V_1D8V_AVDD
+
12
U
D_AGND
A
2
2
706
C
12
12
10U6D3V3MX-GP
C
S
Layout Note:
Close pin41
C
2
707
708
C
S
C
12
D1U16V2KX-3DLGP
10U6D3V3MX-GP
C
S
Layout Note:
Close pin46
2
709
C
S
C
12
D1U16V2KX-3DLGP
Speaker trace width >40mil @ 2W4ohm speaker power
Vince,20161004
2
715
C
SC4D7U6D3V3KX-GP
Close pin16
U
A
D_SENSE_A
A
D_AGND
U
A
A
Layout Note:
2
722
R
100KR2J-1-GP
Azalia I/F EMI
D
A_CODEC_SDOUT
H
A_CODEC_BITCLK
D
C
33P50V2JN-3GP
EMI suggest change to 33p
B B
2015/12/02
12
12
DY
DY
SC33P50V2JN-3GP
M
D
H
2709
2708
C
C
E
E
S
IC_DATA_R
S
C
33P50V2JN-3GP
V_AVDD
3
+
2
728
R
12
DY
100KR2J-1-GP
_MUTE#[24]
B
N
C
2701
E
12
DY
2
708
R
1 2
0R0402-PAD
Width>40mil, t o improve Headp ohone Crosstal k noise
Change it to s harp will be be tter.
Add 2 vias (>0 .5A) when trace layer change.
Layout Note:
D_AGND
U
A
2
R
1 2
0R0402-PAD
2
705
C
U
D_VREF
A
1 2
D
O1_CAP
L
V_AVDD
5
+
V_PVDD
5
+
D_SPK_L+
U
A
U
D_SPK_L-
A
U
D_SPK_R-
A
U
D_SPK_R+
A
V_PVDD
5
+
U
D_SENSE[29]
T
3
V_AVDD
+
12
2
716
C
M
IC_DATA[55]
D
U
D_AGND
D_AGND
U
12
SC2D2U10V3KX-1GP
2
702
1 2
C
SC10U6D3V3MX-GP
2
711 100KR2J-1-GP
1 2
R
T
C_AUX_S5
R
V_AVDD
3
+
PD#
A
E
IC_CLK[55]
M
D
SC33P50V2JN-3GP
Close pin6
U
D_PC_BEEP_R
A
U
D_SPK_L+[29]
A
U
D_SPK_L-[29]
A
D_SPK_R-[29]
U
A
D_SPK_R+[29]
U
A
2
725
R
1 2
0R0402-PAD
Layout Note:
Place close to Pin 1
A
SC4D7U6D3V3KX-GP
723
2
C
DY
1 2
NG2[29]
I
R
L
EEVE[29]
723
5
P
2702
12
S
U
D_PC_BEEP
A
NE1_R[29]
I
L
NE1_L[29]
I
L
_STB
V
2
R
200KR2F-L-GP
O
1
C
2
717
C
SCD1U16V2KX-3DLGP
D
A27
H
37
V
SS1
A
38
EF
R
V
39
O1-CAP
D
L
40
DD1
V
A
41
V
DD1
P
42
P
K-OUT-L+
S
43
P
K-OUT-L-
S
44
K-OUT-R-
P
S
45
K-OUT-R+
P
S
46
V
DD2
P
47
V
STB/AUXMODE
5
48
P
2/LINE2-JD/JD2
H
49
N
D
G
ALC3253-VA3-CG-GP
709
A
12
MBO-GPI
2
714
R
716
2
R
D_SENSE_A
U
12
C
A
PD#
E
12
100R2F-L1-GP-U
12
100R2F-L1-GP-U
2017/03/27 mod ify by EMI sugg est
2
713SC10U6D3V3MX-GP
36
1
D
D
NE2-L/PORT-E-L
I
L
/LINE1-JD/JD1
P
H
35
NE2-R/PORT-E-R
I
L
DIF-OUT/GPIO2/DMIC-DATA34
P
S
2
M
IC_DATA_R
M
IC_CLK_R
710
2
C
C
S
D1U16V2KX-3DLGP
I
C_CAP
M
25
26
27
28
29
30
31
32
33
34
BEEP
C
C2-CAP
I
P
M
NE1-L/PORT-C-L
I
NE1-R/PORT-C-R
I
L
L
DD
V
D
P
D
3
4
5
M
C2-L/PORT-F-L/RING2
I
C2-R/PORT-F-R/SLEEVE
I
M
M
L
-DET/EAPD
IO0/DMIC-DATA12
IO1/DMIC-CLK
LK
P
P
C
C
G
G
D
B
S
6
7
8
9
SS
V
D
12
0R2J-2-GP
732
DY
2
R
C2-VREFO-L
C
C2-VREFO-R
I
I
OUT-L/PORT-I-L
M
OUT-R/PORT-I-R
P
P
H
H
C
P
OUT2-R/PORT-B-R
H
P
OUT2-L/PORT-B-L
H
A
O2-CAP
D
L
A
I
NE1-VREFO-R-E/MONO
I
NE1-VREFO-L-E
L
D
O3-CAP
L
ATA-IN
ATA-OUT
DD-IO
NC
V
Y
D
D
S
S
D
10
11
12
2
C
12
DEC_SDOUT_R
O
C
A_CODEC_SDIN0
D
H
A_CODEC_SYNC
D
H
DEC_BITCLK_R
O
C
P
VEE
N
B
C
P
B
C
VDD
P
V
SS2
DD2
V
V_AVDD
3
+
719
S
C
D1U16V2KX-3DLGP
M
M
A
A
24
P
VEE
C
23
B
N
C
C
22
P
B
C
21
20
19
18
D
O2_CAP
L
17
16
15
14
13
O3_CAP
D
L
C
12
10U6D3V3MX-GP
C
S
719
2
R
0R0402-PAD
718
2
R
0R0402-PAD
720
2
R
0R0402-PAD
I
C2_VREFO_R [29]
I
C2_VREFO_L [29]
U
D_HP1_JACK_L [29]
U
D_HP1_JACK_R [29]
2
703 SC1U50V3KX-GP
12
VDD
P
C
2
712 SC10U6D3V3MX-GP
12
C
V_1D8V_AVDD
3
+
moat
2
718
12
12
12
NE1_VREFO_R [29]
I
L
I
NE1_VREFO_L [29]
L
P
KR[19]
S
EP[24]
E
B
A_CODEC_SDOUT [19]
D
H
D
A_SDIN0 [19]
H
A_CODEC_SYNC [19]
D
H
D
A_CODEC_BITCLK [19]
H
A
V
1.8A
+
150mA
722
2
C
S
12
12
C
D1U16V2KX-3DLGP
R
10KR2J-3-GP
2
701
Q
O_SLP_S3#[17,40,51,54]
I
S
A A
G
S
2N7002K-2-GP
5
8V_EN#
D
D
1
2
726
1 2
2
727
R
20KR2J-L2-GP
12
C
SC1U10V2KX-1GP
D
8V_EN_R#
1
714
2
702
2
Q
DMG3415U-GP
DS
G
DY
D
8V_S0
1
12
2
721
C
S
C
D1U16V2KX-3GP
<Core Design>
<Core Design>
<Core Design>
stron Corporation
stron Corporation
stron Corporation
i
i
i
W
W
W
F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1
1
1
2
2
2
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
A
A
A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
2
2
2
A
A
A
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
S
S
S
Taipei Hsien 221, Taiwan, R.O.C.
u
u
u
dio Codec ALC3246
dio Codec ALC3246
dio Codec ALC3246
arlord KBL-R
arlord KBL-R
arlord KBL-R
t
t
t
1
0
0
0
0
0
0
A
A
7 106Friday, December 08, 2017
7 106Friday, December 08, 2017
7 106Friday, December 08, 2017
2
2
2
A
f
f
f
o
o
o
5
WWW.AliSaler.Com
D D
C C
4
3
2
1
B B
A A
<Core Design>
<Core Design>
5
<Core Design>
it
le
Title
Title
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
1
1
1
A
A
A
Date: Sheetof
Date: Sheetof
4
3
2
Date: Sheetof
1
ta
ta
ta
rlord KBL-R
rlord KBL-R
rlord KBL-R
S
S
S
is
is
is
tron Corporation
tron Corporation
tron Corporation
W
W
W
1F,
1F,
1F,
88, Sec.1, Hsin Tai Wu Rd., Hsichih,
88, Sec.1, Hsin Tai Wu Rd., Hsichih,
88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2
2
2
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Re
Re
Re
served)
served)
served)
(
(
(
28 1
28 1
28 1
06Monday, August 28, 2017
06Monday, August 28, 2017
06Monday, August 28, 2017
00
00
00
A
A
A
5
SSID = Audio
4
3
2
1
D_SPK_L -_C
D_SPK_R -_C
12
2910
C
E
Speaker
12
2912
C
E
SC1KP50V2KX-1DLGP
S
K1
P
7
1
2
3
4
S
P
K_ID[20]
12
12
2909
2911
C
C
E
E
SC1KP50V2KX-1DLGP
SC1KP50V2KX-1DLGP
SC1KP50V2KX-1DLGP
5
6
8
HR-CON6-1 -GP-U
CONN Pin
Pin1
Net name
SPK_L+
Pin2 SPK_L-
Pin3
Pin4
Pin5
SPK_R-
SPK_R+
SPK_DET#
Pin6 GND
Layout Note:
Speaker trace width >40mil @ 2W4ohm speaker power
1 2
E
L
A
U
D D
D_SPK_L +[27]
A
D_SPK_L -[27]
U
A
U
D_SPK_R -[27]
A
D_SPK_R +[27 ]
U
DY
12
12
DY
2903
2904
C
C
E
E
SC100P50V2JN-3GP
SC100P50V2JN-3GP
12
DY
2901
2902
C
C
E
E
SC100P50V2JN-3GP
SC100P50V2JN-3GP
2902 HCB1005KF-121T 20-GP
1 2
E
2901 HCB1005KF-121T 20-GP
L
1 2
E
2903 HCB1005KF-121T 20-GP
L
1 2
E
L
2904 HCB1005KF-121T 20-GP
main: 68.00358.031
2nd: 068.00006.0041
12
DY
A
D_SPK_L -_C
U
A
D_SPK_L +_C
U
A
U
D_SPK_R -_C
A
D_SPK_R +_C
U
1
A
F
A
A
A
TP2901
TP2902
F
TP2903
F
TP2904
F
1
1
1
A
A
D_SPK_R +_C
U
U
D_SPK_L +_C
A
U
A
U
2017/03/27 modify by EMI suggest
C C
R
2901
N
NE1-L_C
NE1-L_R
1
2 3
SRN2K2J -1-GP
M
I
C2_VREF O_R[27]
M
C2_VREF O_L[27]
I
R
NG2[27]
I
A
D_HP1_J ACK_L[27]
U
L
I
NE1_L[27]
L
I
NE1_VRE FO_L[27]
A
U
D_HP1_J ACK_R[27]
L
I
NE1_R[27]
L
NE1_VRE FO_R[27]
I
S
EEVE[27]
L
C
907
2
C
908
2
L
1 2
SC10U6D 3V3MX-GP
L
1 2
SC10U6D 3V3MX-GP
I
I
4
1 2
R
907 0R 0603-PAD
2
1 2
R
922 0R 0402-PAD
2
1 2
R
912 2K2R2J-2-GP
2
DY
1 2
R
909 0R 0603-PAD
2
1 2
R
921 0R 0402-PAD
2
1 2
R
913 2K2R2J-2-GP
2
DY
A
D_HP1_J ACK_L1
U
A
U
D_HP1_J ACK_R1
12
10KR2J-3-GP
R
2
920
DY
SC100P50V2JN-3GP
SC100P50V2JN-3GP
E
C
2908
12
DY
Universal Jack (Moved to I/O Board)
1 2
1 2
1 2
SC100P50V2JN-3GP
E
C
2907
DY
SC100P50V2JN-3GP
12
12
919
2
R
DY
10KR2J-3-GP
DY
E
E
C
C
2905
2906
12
12
DY
1 2
R
906 0R 0603-PAD
2
R
90810R2F-L-GP
2
R
91010R2F-L-GP
2
R
911 0R 0603-PAD
2
R
I
NG2_R
A
D_PORTA _L_R_B
U
A
U
D_PORTA _R_R_B
S
L
EEVE_R
S
L
EEVE_R
A
U
D_PORTA _L_R_B
J
A
CK_PLUG
J
CK_PLUG _DET
A
A
U
D_PORTA _R_R_B
R
I
NG2_R
A
U
D_AGND
H
3
1
5
6
2
4
M
S
Audio(IP/NK comb)
AUDIO-JK52 2-GP
P
MIC1
Delay circuit
B B
(JACK_PLUG_DET: on IO Board)
A
U
D_AGND
J
CK_PLUG _DET
A
1
0 mils
A A
A
U
12
D_AGND
R
905
2
0R0402-P AD
5
E
D2901
DF2B6D8 E-1-GP
CLOSS TO HPMIC1
AZ5725-01FDR7G-GP
K A
4
AZ5725-01FDR7G-GP
AZ5725-01FDR7G-GP
AZ5725-01FDR7G-GP
E
D
2902
12
E
E
D
D
2904
2903
12
12
R
I
NG2_R
A
U
D_PORTA _L_R_B
J
A
CK_PLUG
J
A
CK_PLUG _DET
A
D_PORTA _R_R_B
U
S
E
D
2905
12
E
D2906
DF2B6D8 E-1-GP
K A
L
EEVE_R
A
U
D_AGND
3
J
CK_PLUG
A
1 2
R
2
923 0R 0603-PAD
12
DY
A
D_AGND
U
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A
A
A
3
3
3
Date: Sheet
Date: Sheet
2
Date: Sheet
Audio IO
Audio IO
Audio IO
S
S
S
t
t
t
arlord KBL-R
arlord KBL-R
arlord KBL-R
Friday, December 08, 20 17
Friday, December 08, 20 17
Friday, December 08, 20 17
1
0 mils10 mils
C
902
2
SC10U6D 3V3MX-GP
W
W
W
i
i
i
stron Corporation
stron Corporation
stron Corporation
2
2
2
1
1
1
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
F, 88, Sec.1, Hsin T ai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
Taipei Hsien 221, Taiwan, R.O.C .
1
A
D_SENSE [2 7]
U
o
o
o
2
2
2
9 106
9 106
9 106
f
f
f
A
A
A
0
0
0
0
0
0
5
WWW.AliSaler.Com
4
3
2
1
Main Func = Audio
D D
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
W
W
W
tron Corporation
tron Corporation
tron Corporation
is
is
A A
le
Title
Title
it
T
(
(
(
Reserved)
Reserved)
Reserved)
S
S
S
ta
ta
ta
rlord KBL-R
rlord KBL-R
rlord KBL-R
5
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
4
4
4
A
A
A
Monday, August 28, 2017
Monday, August 28, 2017
Monday, August 28, 2017
Date: Sheet
Date: Sheet
4
3
Date: Sheet
2
is
88, Sec.1, Hsin Tai Wu Rd., Hsichih,
88, Sec.1, Hsin Tai Wu Rd., Hsichih,
88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1F,
1F,
1F,
2
2
2
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
f
f
30 1
30 1
30 1
f
o
o
o
1
00
00
00
A
A
A
06
06
06
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