Dell Inspiron 3490, Inspiron 3590, Inspiron 3790, Inspiron 5494, Inspiron 5594 Schematics

A

B

C

D

E

COMPAL CONFIDENTIAL

MODEL NAME :

FDI40 N3-14", FDI4A V3-14", FDI43 N5-14",

1 1

FDI50 N3-15", FDI5A V3-15", FDI53 N5-15", FDI70 N3-17"

PCB NO :

DA8001K6000 (SBDR) DA8001K6100 (NBDR)

BOM P/N :

SBDR-DIS

431AJ431L51 431AJ431L52 431AJ431L53

NBDR-DIS

431AJ431L01 431AJ431L02

X4E X4EAJ431L51(N3)

X4EAJ431L52(V3) X4EAJ431L01(N5)

431AJ431L54

2 2

CML-U+MEC1418

2019-06-20

REV : 1.0 (A00)

@ : Un-pop Component DIS@ : GPU Support INSPIRON@/VOSTRO@ : Inspiron/Vostro CML@/CNL@ : CML/CNL BASE@/PREM@ : Pentium,Celeron / i3,i5,i7 EXO@/TOPAZ@ : R17M-M1-30/R17M-M2-50 EC@ : EC Support

PCB R1

ZZZ

DAZ2QM00100

PCB_SBD R_R1@

PCB FDI40 LA -G716P LS-F1 12P/F114P /G711P

PCB R3

ZZZ

DAZ2QM00101

PCB_SBD R_R3_GCE@

PCB FDI40 LA -G716P LS-F1 12P GOLD A31 !

ZZZ

DAZ2QM00102

PCB_SBD R_R3_TRI@

PCB FDI40 LA -G716P LS-F1 12P TRIPOD A 31 !

ZZZ

DAZ2QM00103

PCB_SBD R_R3_HAN@

PCB FDI40 LA -G716P LS-F1 12P HANNS A 31 !,

ZZZ

DAZ2QM00104

PCB_SBD R_R3_TMT@

PCB FDI40 LA -G716P LS-F1 12P T-MAC A31 !

ZZZ

DAZ2RF00300

PCB_NBR D_R1@

PCB FDI43 LA -G716P LS-G 718P

ZZZ

DAZ2RF00301

PCB_NBR D_R3_GCE@

PCB FDI43 LA -G716P LS-G 718P GOLD A31 !

ZZZ

DAZ2RF00302

PCB_NBR D_R3_TRI@

PCB FDI43 LA -G716P LS-G 718P TRIPOD A 31 !

ZZZ

DAZ2RF00303

PCB_NBR D_R3_HAN@

PCB FDI43 LA -G716P LS-G 718P HANNS A31 !

ZZZ

DAZ2RF00304

PCB_NBR D_R3_TMT@

PCB FDI43 LA -G716P LS-G 718P T-MAC A3 1 !

JP@/PJP@ : JUMP 100@/1000@: Lan

CPU R1 CPU R3

UC1

S IC FJ80701 04307606 SRGL0 V0 2.1G BGA

i3-10110U

SA0000CU31L

CML_2.1G _R1@

UC1

S IC FJ80701 04307606 SRGL0 V0 2.1G A31!

i3-10110U

SA0000CU32L

CML_2.1G _R3@

EMI@/ESD@/RF@ : EMI, ESD and RF Component @EMI@/@ESD@/@RF@ : EMI, ESD and RF Un-POP Component CMC@ : XDP Component

CONN@ : Connector Component KBBL@ : KB Backlight TPM@/FTPM@ : HW TPM/SW TPM

UC1

3 3

S IC FJ80701 04307504 SRGKY V0 1. 6G BGA

i5-10210U

SA0000CST2L

CML_1.6G _R1@

UC1

S IC FJ80701 04307504 SRGKY V0 1. 6G A31!

i5-10210U

SA0000CST3L

CML_1.6G _R3@

750_CTPM@:750 and china TPM ST_CTPM@:ST and china TPM CTPM@:China TPM FFS@ : Free Fall Sensor TYPEC@ : TypeC

UC1

S IC FJ80701 04303905 SRGKW V0 1.8G FCB GA

i7-10510U

SA0000CU22L

CML_1.8G _R1@

UC1

S IC FJ80701 04303905 SRGKW V0 1.8G A 31!

i7-10510U

SA0000CU21L

CML_1.8G _R3@

TYPEC@EMI@/TYPEC@ESD@: EMI, ESD ,TypeC Component M1_30@/M2_50@ : R17M-M1-30/R17M-M2-50 2G_G5@/2G_H@/2G_S@/2G_M@ : VRAM type PCB@/PCB_R1@/PCB_R3_G@/PCB_R3_T@/PCB_R3_H@/PCB_R3_TM@: PCB MB

PCB_NBDR_R1@: PCB MB DAZ for NBDR TS_NON@/TS_USB@/TS_I2C@: Touch Screen Interface Select

Layout Dell logo

4 4

A

B

SBDR@/NBDR@: SBDR/ NBDR Select

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/ 20 2020/06/ 30

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet o f

D

Date : Sheet o f

Compal Electronics, Inc.

Cover Page

LA-G716P

1 1 01Thursday, June 20 , 2019

E

1.0

A

B

C

D

E

Block Diagram

DDR4

1 1

VRAM(GDDR5)* 2 2GB

P35~3 6

GPU

AMD R520/R530

R17M-M1-30/R17M-M 2-50 (15"/17" ) 18W

P27~3 1

PCIe x 4GDDR 5

Intel CPU

Comet Lake/ Whiskey Lake-U/ Cannon Lake-U

15W

VGA

Connector

# VGA converter

RTD2166

DP x 2

eDP connector

HDMI connector , 1.4a

# DP re-driver PS8330B

P38

P40

eDP 1.2

DDI x 4

DDI x 2

P40

DDR4 2400MHz Channel A

DDR4 2400MHz Channel B

USB2.0 x 1

USB3.0 x 1 Gen1

USB2.0 x 1

USB3.0 x 1 Gen1

USB2.0 x 1

Port 1 (USB3.0 Type-A)

Port 3 (USB3.0 Type-A)

Port 2 (USB2.0 Type-A)

BGA 1528 balls

Type-C MUX TUSB542

Reser ved

*Pentium/Celeron Only

Touch screen

LAN 10/100 # LAN 10/1 00/1000

M.2 SSD (NVMe)

ODD

2.5" HDD/SSD

# FFS

P42

P38

P51P51P51

P68

P67

P43

CC

TPS25810

USB3.0 x 1

P42

P50

USB Type-C

Connector

Reser ved

Transformer

2 2

5V@3A

Reser ved Reser ved

RJ45

Connector

3 3

USB3.0 x 1 Gen1

USB2.0 x 1 (Port4)

I2C

USB2.0 x 1 (Port8)

PCIe x 1

PCIe x 4

SATA x 1 Gen1

SATA x 1

SMBu s

46 x 24 mm

PCH-LP

USB2.0 x 1 SD 3.0

USB2.0 x 1

PCIe x 1 / CNVi

USB2.0 x 1

SPI

Card reader RTS5144

BT with WLAN

Camera

Finger print

#dTPM NPCT750

SPI ROM 16 MB

4GB/8GB

SODIMM A

P23

DDR4 4GB/8GB

SODIMM B

P24

P71

P73

P52

P38

P66

P8

SD Card slot

2CH SPEAKER (2CH 2W/4ohm)

HDA CODEC Realtek ALC3204-CG

P56

Universal Ja ck

RING2/SLEEVE

HP_R/L

P56

# ----> V3 only

4 4

Battery

Charger

A

RTC

Daughter board

B

Keyboard

HDA

P6~1 7

eSPI

SMSC KBC 1418 MEC1418-NU

PWM FAN

C

Thermal sensor NCT771 8W

I2C

P66P77P62

RTC

Precision Touchpa d Click Pad

PS/2

P62

P58

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2019/06/20 2020/06/30

Deciphered Date

Compal Electronics, Inc.

Title

Block Diagram

Size Document Number Rev

LA-G716P

Date: Sheet

E

of

2 101Thursday, June 20, 2019

of

2 101Thursday, June 20, 2019

of

2 101Thursday, June 20, 2019

1.0

POWER STATES

Signal

State

S0 (Full ON) / M0

S3 (Suspend to RAM) / M3

D D

S4 (Suspend to DISK) / M3

S5 (SOFT OFF) / M3

G3

DS3

5

SLP

S5#

S4#

HIGH HIGH

LOW

ALWAY S PLANE

ON

ONLOW HIGH

ONLOW LOW

S3#

HIGH

LOW HIGH HIGH ON

OFF OFF OFF OFF OFF OFF OFF

RUN

SUS

PLAN E

PLANE

ON

ON ON

ON

OFF

OFF OFF

OFF

CLOCKS

USB 2.0

1

2

OFF

3

4*

5

6

7

------------------ ---

8*

9

10

Voltage Rails

+19V_ADPIN +17.4V_BATT++ +19VB +RTC_CE LL RTC power ONONON +3VALW_DSW +3VALW power for PCH DS W rails ON*ONON +5VALW System +5V always on power rail ON*ONON +3VALW System +3V always on power rail ON*ONON +1.8V_PRIM System +1.8V always on power rail

C C

+1.0V_PRIM System +1.0V always on power rail ON*

+2.5V_MEM

+0.6V_DDR_VTT DDR +0.6VS power rail for DDR terminator +VCCST +VCCSTG +1.05 VCCSTG power rail ON +VCCIO +1.05 VCCIO power rail ON +VCC_COR E Core voltage for CPU +VCC_GT Sliced graphics power rail +VCC_SA System Agent power rail +3VLP +19VB to +3VLP power rail for suspend power ONONON +3VALW_PCH +3VALW power for PCH suspend rails

+5VS +3VS +1.35V_MEM_GFX +3VGS

+1.8VGS +1.8V power rail for GPU +0.95VSDGPU +0.95V power rail for GPU

B B

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OF F

A A

Adapter power supply

Bat t ery po wer s uppl y AC or bat t ery po wer rail f or Syst e m

DDR4 +1.2V power rail+1.2V_DDR DDR4 +2.5V power rail ON

+1.05 VCCST power rail

System +5VS power rail System +3VS power rail +1.35V power rail for GPU +3V power rail for GPU

5

S0 S 3 S4/S5Power Plane Des cript i on

N/A N/A N/A

ON ON ON ON ON

ON ON ON

ON ON ON ON ON ON ON

N/A N/A N/A

ON ON ON

ONON

OFF OF F OFF OF F OFF

OFF

ON

OFF OFF

N/A N/A N/A

ON*

OFF OFF OFFOFF OFF

OFF OFFOFF OFF

ON*

OFF OFF OFFOFF OFF OFF OFFOFF

4

DESTINATION

USB2.0 port1

USB2.0 Port2

USB2.0 Port, IO/B

Touch screen

Finger printer

Camera

Card reader , IO/B

Reserved

NA

BT

Board ID & Model ID Table

Pull-down#Pull-up

10.0

100

1

2

3

4

5

6

7

8

9

10

USB3.0

USB3.0-1

USB3.0-2

USB3.0-3

USB3.0-4

USB3.0-5

USB3.0-6

100

PCIE-1

PCIE-2

PCIE-3

PCIE-4

PCIE-5

PCIE-6

PCIE-7

PCIE-8

PCIE-9

PCIE-10

PCIE-11

PCIE-12

PCIE-13

PCIE-14

PCIE-15

PCIE-16

4

17.8

27.0

37.4

49.9

64.9

82.5

107.0

154.0

200.0

PCIE

SATA

SATA-0

SATA-1A

SATA-1B

SATA-2

Voltage

3.000

2.801

2.598

2.402

2.201

2.001

1.808

1.594

1.299

1.100

Board ID

EVT

DVT1

DVT2

Pilot

DESTINATION

USB3.0 port1

NA

USB3.0 port2

TypeC

GPU

LOM

WLAN

SATA HDD

SATA ODD

NVME SSD

Model ID

SBDR-UMA

NBDR-UMA

SBDR-DSC

NBDR-DSC

3

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2019/06/20 2020/06/30

Deciphered Date

1

Compal Electronics, Inc.

Title

Notes List

Size Document Number Rev

LA-G716P

Date: Sheet

1

of

3 101Thursday, June 20, 2019

of

3 101Thursday, June 20, 2019

of

3 101Thursday, June 20, 2019

1.0

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET A ND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

5

4

3

2

1

https://shop62935598.taobao.com

SIO_SLP _S4#

SIO_SLP _S3#

CPU_C10_GATE#

JP10

DGPU_PWR _EN

SY6288D20AAC

(UU1)

SY6288D20AAC

(UU2)

EM5209VF

(UZ3)

SY6861A1AAC

(UT3)

LCD_VCC_TEST_ EN

EDP_VDD_ EN

DGPU_PWR _EN

+VCCST

+VCCSTG

+VCCIO

+0.95VSDGPU

or

JP9

USB_EN#

SIO_SLP _S3#

OVP_TR IP_P1

+LCDVD D

+3VGS

0ohm 0603

(RM2)

EM5209VF

(UZ6)

USB30_VCC A

USB30_VCC B

+5VS

+CCG_VBUS

DGPU_PWR _EN

JP11

+1.8V_EMMC

+1.8VGS

0ohm 0603

(R23)

0ohm 0805

(RA1)

JP6

JP7

FUSE 1.5A_6V

(FI1)

FUSE 0.5A_13.2V (F3)

+TPAN_VDD

+5V_PVD D

+5V_HDD

+5V_ODD

+5V_HDMI

+5V_KB_B L

FUSE 1.5A_24V

D D

CPU PWR

GPU PWR

Peripheral Device PWR

ADAPTER

+PWR_S RC

C C

CHARGER ISL88739HRZ-T (PUB01)

(+19VB)

PJPH01

PJPW01

PJP501

PJP301

(F1)

RT6228AGQU F (PUH01)

RT6226AGQU F (PUW01)

SY8180CRAC (PU501)

SY8286BRAC (PU301)

EN_3V

+3VALWP

PJP302

+3VALW

BATTERY

NCP302045MNTXG

B B

(PUI01)

NCP302045MNTXG

(PUI02)

NCP302045MNTXG

(PUG01)

NCP81253M NTBG (PUA01)

+DCBAT_LCD

PJPH02PRIM_PWR GD

PJP502 PJP503

PJPW02

+1.05V_PRIM

+1.35V_MEM_GFX

+5VALW

BAS40C (D1)

DGPU_PWRO K

EN_5V

+1.05VALWP

+1.35VGPUP

+5VALWP

+3VLP

+RTC_VCC

0.6V_DDR_VTT_ ON

+VCC_CORE

+VCC_GT

+VCC_S A

SIO_SLP _S3#

+3VS

PCH_PWR _EN

+3VALW_PCH

+3V_EMMC

PCH_PRIM_ EN

+1.8VALWP

+2.5VP +2.5V_MEM

+1.2VP +1.2V_DDR

+0.6VSP

RSHUNT

EM5209VF

(UZ3)

TPS22967DSGR

(UZ4)

0ohm 0603

(RM1)

PJP180 1

RT8061AZQW (PU1801)

PJP250 1 SIO_SLP_ S4# PJP250 2

RT9059GSP (PU2501)

PJPM01

RT8207PGQW (PUM01)

DRVON PWM1_2ph_CP U

DRVON PWM_1a_CPU

DRVON PWM_1b_CPU

+2.5V_PG

+RTC_CELL

PJPM02

PJPM03

EM5209VF

(UZ1)

TPS22961

(UZ2)

EM5209VF

(UZ6)

SY6288C20AAC

(U1)

TPS22967DSGR

(UZ5)

PJP180 2

+0.6V_DDR_ VTT

+VCC_CORE_GT

+1.8V_PRIM

ISL62771HRTZ-T (PUV01)

A A

5

4

DGPU_PWR _EN

+VGA_CORE

Security C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2019/06/20 2020/06/30

Deciphered Date

Compal Electronics, Inc.

Title

Power MAP

Size

Document Number Rev

LA-G716P

Date: Shee t

1

of

4 101Thursday, June 20 , 2019

of

4 101Thursday, June 20 , 2019

of

4 101Thursday, June 20 , 2019

1.0

5

4

3

2

1

Timing Diagram for S5 to S0 mode

10b

IMVP_VR_ON

D D

ADAPTER

a

ISL88739

BATTERY

BAT-->1

C C

HW_ACAV_IN

b

SIO_PWRBTN #

6

PRIM_PWRGD

5

PCH_RSM RST#

5a

RUNPWRO K ALL_SYS_PWRG D

10a

RESET_OU T#

B B

11

12

SYS_PWROK

AC-->2

POWER_SW_ IN#

EC 1416

ACOK

+19VB

HW_ACAV_IN

2b

EN_5V

2a

EN_3V

VCCDSW_E N

b

+19VB

AND

POK

PCH_PRIM_ EN

4

VL +5VALW

+3VLP +3VALW

c

+3VALW

5

+3VALW

3

PRIM_PWRGD

+1.8V_PRIMRT8061

+19VB

+3VALW_PCHTPS22967

SY8180

+19VB

SY8286

+19VB

NCP81218

+VCC_S A +VCC_COR E +VCC_GT

+3VALW_PCH

+RTC_SOC

c

+3VALW_DSW

DDR_VTT_ CNTL

+3V_HDA

+3.3V_SPI

+1.8V_PRIM

+1.05V_PRIM

+1.0V_MPHYGT

+1.05V_PRIM +1.05V_MPH YPLL

+1.05V_MPHY

+1.05V_X TAL

+1.05V_PRIMRT6228

VCCST_PWRGD

10b

RESET_OU T#

11

SYS_PWROK

12

PCH_P LTRST#

13

CPU

DDR_VTT_ CTL

PCH

VCCRTC

VCCDSW_3 P3

VCCHDA

VCCSPI

VCCPRIM_3P3

VCCPRIM_1P8

VCCAPLL_1P 05 VCCDUSB _1P05 VCCA_BCLK_ 1P05 VCCA_SRC_ 1P05 VCCPRIM_1P0 5 VCCPRIM_CORE

VCCMPHYGT_1P0 VCCSRAM_1P0 VCCAMPHYPLL_1P0 VCCAPLLEBB

VCCAMPHYPLL_1P0 5

VCCPRIM_MPHY_1P0 5

VCCA_XTAL_1P05

VCCST_PWRGOO D

PCH_PWR OK

SYS_PWROK

PLTRST#

VDDQ VCCPLL_OC

VCC_OPC_1 P8

VCCEOPIO

CFL-U 43e only

RSMRST#

DSW_PWROK

PWRBTN#

CPU_C1 0_GATE#

VCCIO

VCCGT

VCCGTX

VCCST VCCPLL VCCSTG

VCCSA

VCCOPC

SLP_S5 #

SLP_S4 #

SLP_S3 #

VCC

+VCC_COR E

+VCCIO

+VCC_GT

+1.2V_DDR

+VCCST

+VCC_S A

PCH_RSMR ST#_Q

PCH_DPW ROK

SIO_PWRBTN #

SIO_SLP_S 5#

SIO_SLP_S 4#

0.6V_DDR_V TT_ON

SIO_SLP_S 3#

8b

+2.5V_PG

AND

5b

6

7

8a

VCCSTG

9a

9b

+1.05V_PRIM

EM5209

+3VALW

PGOOD

+19VB

RT8207

PGOOD

1.2V_VTT_PWRGD

+5VALW

EM5209

+3VALW

+1.05V_PRIM

EM5209

+1.05V_PRIM

+VCCST

+2.5V_MEMRT90 59

+1.2V_DDR

+0.6V_DDR_ VTT

8c

+5VS

+3VS

+VCCSTG

VPP

DDR4

VDDQ

VTT

TPS22961 +VCCIO

9C

A A

Security C lassification

5

https://shop62935598.taobao.com

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Security C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2019/06/20 2020/06/30

Deciphered Date

Compal Electronics, Inc.

Title

Platform Power Sequence

Size

Document Number Rev

LA-G716P

Date: Shee t

1

of

5 101Thursday, June 20 , 2019

of

5 101Thursday, June 20 , 2019

of

5 101Thursday, June 20 , 2019

1.0

5

+VCCSTG

H_PROCHOT#

1 2

RC1 1K_0402_5%

+VCCST

D D

RC2 1K_0402_5%

RC3 49.9_0402_1%

COMPENSATION FOR EDP_COMP

+VCCIO

RC4 24.9_0402_1 %

CAD note: Trace width=5 mils, Spacing=25mils Max length=600mils

+3VS

RC5 10K_0402_5%

C C

RC6 10K_0402_5%

RC203 10K_0402_5 %

1 2

@

1 2

CML@

1 2

@

1 2

H_THERMT RIP#

CATERR#

RC4 100_0402_1%

SD0341000 80

EDP_COMP

TOUCH_PAD_INT #

TOUCH_PANEL_ PD#

TOUCH_SCR EEN_INT#

CNL@

TOUCH_SCR EEN_INT# [38 ]

4

UC1A

CPU_DP1_N0[40] CPU_DP1_P0[40] CPU_DP1_N1[40] CPU_DP1_P1[40] CPU_DP1_N2[40] CPU_DP1_P2[40] CPU_DP1_N3[40] CPU_DP1_P3[40]

CPU_DP2_N0[40] CPU_DP2_P0[40] CPU_DP2_N1[40] CPU_DP2_P1[40]

EDP_COMP

CPU_DP1_CTRL_CLK[40]

CPU_DP1_C TRL_DATA[40]

TOUCH_SCREEN_RST[38]

CPU_DP1_C TRL_CLK CPU_DP1_C TRL_DATA

CPU_DP2_C TRL_DATA

AL5

DDI1_TXN_0

AL6

DDI1_TXP_0

AJ5

DDI1_TXN_1

AJ6

DDI1_TXP_1

AF6

DDI1_TXN_2

AF5

DDI1_TXP_2

AE5

DDI1_TXN_3

AE6

DDI1_TXP_3

AC4

DDI2_TXN_0

AC3

DDI2_TXP_0

AC1

DDI2_TXN_1

AC2

DDI2_TXP_1

AE4

DDI2_TXN_2

AE3

DDI2_TXP_2

AE1

DDI2_TXN_3

AE2

DDI2_TXP_3

AM6

DISP_RCOMP

CC8

GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#

CC9

GPP_E19/DPPB_CTRLDATA

CH4

GPP_E20/DPPC_CTRLCLK

CH3

GPP_E21/DPPC_CTRLDATA

CP4

GPP_E22/DPPD_CTRLCLK

CN4

GPP_E23/DPPD_CTRLDATA

CR26

GPP_H16/DDPF_CTRLCLK

CP26

GPP_H17/DDPF_CTRLDATA

WHL-U42 _BGA1528

DDI

DISPLAY SIDEBANDS

3

EDP

GPP_E13/DDPB_HPD0/DISP_MISC0 GPP_E14/DDPC_HPD1/DISP_MISC1 GPP_E15/DPPD_HPD2/DISP_MISC2 GPP_E16/DPPE_HPD3/DISP_MISC3

GPP_E17/EDP_HPD/DISP_MISC4

1 of 20

EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1 EDP_TXN_2 EDP_TXP_2 EDP_TXN_3 EDP_TXP_3

EDP_AUX_N EDP_AUX_P

DISP_UTILS

DDI1_AUX_N DDI1_AUX_P DDI2_AUX_N DDI2_AUX_P DDI3_AUX_N DDI3_AUX_P

EDP_BKLTEN

EDP_VDDEN

EDP_BKLTCTL

2

AG4 AG3 AG2 AG1 AJ4 AJ3 AJ2 AJ1

AH4 AH3

AM7

AC7 AC6 AD4 AD3 AG7 AG6

CN6 CM6 CP7 CP6 CM7

CK11 CG11 CH11

CPU_DP2_H PD

BKLT_IN_EC

EDP_TXN0 [38] EDP_TXP0 [38] EDP_TXN1 [38] EDP_TXP1 [38]

EDP_AUXN [38] EDP_AUXP [38]

TP1

CPU_DP2_AUXN [40] CPU_DP2_AUXP [40]

CPU_DP1_H PD [40] CPU_DP2_H PD [40]

EDP_HPD [38]

BKLT_IN_EC [58] EDP_VDD_EN [38] EDP_BKLT_CTRL [38]

CPU_DP1_C TRL_CLK

CPU_DP1_C TRL_DATA

CPU_DP2_C TRL_DATA

RC7 2.2K_0402_5%

RC8 2.2K_0402_5%

RC9 2.2K_0402_5%

1

+3VS

12

CPU_DP2_H PD

BKLT_IN_EC

UC1D

CB34 CC35

BP27

BW25

AA4 AR1

Y4

BJ1

U1 U2 U3 U4

CE9 CN3

L5 N5

CATERR# PECI PROCHOT# THRMTRIP#

BPM#_0 BPM#_1 BPM#_2 BPM#_3

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP

RSVD70 RSVD71

WHL-U42 _BGA1528

CPU MISC

4 of 20

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_TCK

PCH_TDI PCH_TDO PCH_TMS

PCH_TRST#

PCH_JTAGX

PROC_PREQ# PROC_PRDY#

49.9_0402_1%

TP2 TP3 TP4 TP5

TP6

12

TOUCH_PANEL_ PD#

RC16

49.9_0402_1%

CATERR#

H_PROCHOT# _R H_THERMT RIP#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3

CAM_EN# TOUCH_SCR EEN_INT# TOUCH_PAD_INT #

CPU_POPIRCOMP PCH_POPIRCOMP

H_PROCHOT#[58,82,84,88]

B B

TP_WAKE_KBC#[58,63]

TOUCH_SCREEN_PD#[38]

1 2

RC160 499_0402_ 1%

DZ1 RB751S40T 1G_SOD523-2

1 2

TOUCH_SCR EEN_PD#

PECI_EC[58]

1 2

@

RC14 0_0 201_5%

12

RC15

T6 U6 Y5 T5 AB6

W6 U5 W5 P5 Y6 P6

W2 W1

CPU_XDP_TCK 0 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST #

SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST# CPU_XDP_TCK 0

XDP_PREQ# XDP_PRDY#

CPU_XDP_TCK0 [80] SOC_XDP_TDI [80] SOC_XDP_TDO [80] SOC_XDP_TMS [80] SOC_XDP_TRST# [80]

PCH_JTAG_TCK1 [80]

TP7 TP8

RC12 100K_0402_ 5%

RC13 100K_0402_ 5%

12

L5,N5 are required for CFL U43e only.

COMPENSATION FOR OPIRCOMP

CAD Note: Min trace width=10 mi ls, Max trace length=500 mils

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Only for Dell

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2019/06/20 2020/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

CPU(1/12))DDI,MSIC,XDP,EDP

LA-G716P

1

6 101Thursday, June 20, 20 19

1.0

5

4

3

2

1

DDR4 Interleaved Memory

D D

C C

B B

DDR_A_D[0..15][23]

DDR_A_D[16..31][23]

DDR_A_D[32..47][23]

DDR_A_D[48..63][23]

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

UC1B

Interleave / Non-Interleaved

A26

DDR0_DQ_0/DDR0_DQ_0

D26

DDR0_DQ_1/DDR0_DQ_1

D28

DDR0_DQ_2/DDR0_DQ_2

C28

DDR0_DQ_3/DDR0_DQ_3

B26

DDR0_DQ_4/DDR0_DQ_4

C26

DDR0_DQ_5/DDR0_DQ_5

B28

DDR0_DQ_6/DDR0_DQ_6

A28

DDR0_DQ_7/DDR0_DQ_7

B30

DDR0_DQ_8/DDR0_DQ_8

D30

DDR0_DQ_9/DDR0_DQ_9

B33

DDR0_DQ_10/DDR0_DQ_10

D32

DDR0_DQ_11/DDR0_DQ_11

A30

DDR0_DQ_12/DDR0_DQ_12

C30

DDR0_DQ_13/DDR0_DQ_13

B32

DDR0_DQ_14/DDR0_DQ_14

C32

DDR0_DQ_15/DDR0_DQ_15

H37

DDR0_DQ_16/DDR0_DQ_32

H34

DDR0_DQ_17/DDR0_DQ_33

K34

DDR0_DQ_18/DDR0_DQ_34

K35

DDR0_DQ_19/DDR0_DQ_35

H36

DDR0_DQ_20/DDR0_DQ_36

H35

DDR0_DQ_21/DDR0_DQ_37

K36

DDR0_DQ_22/DDR0_DQ_38

K37

DDR0_DQ_23/DDR0_DQ_39

N36

DDR0_DQ_24/DDR0_DQ_40

N34

DDR0_DQ_25/DDR0_DQ_41

R37

DDR0_DQ_26/DDR0_DQ_42

R34

DDR0_DQ_27/DDR0_DQ_43

N37

DDR0_DQ_28/DDR0_DQ_44

N35

DDR0_DQ_29/DDR0_DQ_45

R36

DDR0_DQ_30/DDR0_DQ_46

R35

DDR0_DQ_31/DDR0_DQ_47

AN35

DDR0_DQ_32/DDR1_DQ_0

AN34

DDR0_DQ_33/DDR1_DQ_1

AR35

DDR0_DQ_34/DDR1_DQ_2

AR34

DDR0_DQ_35/DDR1_DQ_3

AN37

DDR0_DQ_36/DDR1_DQ_4

AN36

DDR0_DQ_37/DDR1_DQ_5

AR36

DDR0_DQ_38/DDR1_DQ_6

AR37

DDR0_DQ_39/DDR1_DQ_7

AU35

DDR0_DQ_40/DDR1_DQ_8

AU34

DDR0_DQ_41/DDR1_DQ_9

AW35

DDR0_DQ_42/DDR1_DQ_10

AW34

DDR0_DQ_43/DDR1_DQ_11

AU37

DDR0_DQ_44/DDR1_DQ_12

AU36

DDR0_DQ_45/DDR1_DQ_13

AW36

DDR0_DQ_46/DDR1_DQ_14

AW37

DDR0_DQ_47/DDR1_DQ_15

BA35

DDR0_DQ_48/DDR1_DQ_32

BA34

DDR0_DQ_49/DDR1_DQ_33

BC35

DDR0_DQ_50/DDR1_DQ_34

BC34

DDR0_DQ_51/DDR1_DQ_35

BA37

DDR0_DQ_52/DDR1_DQ_36

BA36

DDR0_DQ_53/DDR1_DQ_37

BC36

DDR0_DQ_54/DDR1_DQ_38

BC37

DDR0_DQ_55/DDR1_DQ_39

BE35

DDR0_DQ_56/DDR1_DQ_40

BE34

DDR0_DQ_57/DDR1_DQ_41

BG35

DDR0_DQ_58/DDR1_DQ_42

BG34

DDR0_DQ_59/DDR1_DQ_43

BE37

DDR0_DQ_60/DDR1_DQ_44

BE36

DDR0_DQ_61/DDR1_DQ_45

BG36

DDR0_DQ_62/DDR1_DQ_46

BG37

DDR0_DQ_63/DDR1_DQ_47

WHL-U42 _BGA1528

2 of 20

Buf f er wit h Open Dr ai n Out put F or VTT po wer control

0.1U_0402_1 6V7K

UC2

DDR_VTT_CNTL

NC1VCC

2

A

3

GND

74AUP1G07GW _TSSOP5

LPDDR3 / DDR4

DDR0_CKN_0/DDR0_CKN_0 DDR0_CKP_0/DDR0_CKP_0 DDR0_CKN_1/DDR0_CKN_1 DDR0_CKP_1/DDR0_CKP_1

DDR0_CKE_0/DDR0_CKE_0 DDR0_CKE_1/DDR0_CKE_1

DDR0_CKE_2/NC DDR0_CKE_3/NC

DDR0_CS#_0/DDR0_CS#_0 DDR0_CS#_1/DDR0_CS#_1

DDR0_ODT_0/DDR0_ODT_0

NC/DDR0_ODT_1

DDR0_CAB_9/DDR0_MA_0 DDR0_CAB_8/DDR0_MA_1 DDR0_CAB_5/DDR0_MA_2

NC/DDR0_MA_3

NC/DDR0_MA_4 DDR0_CAA_0/DDR0_MA_5 DDR0_CAA_2/DDR0_MA_6 DDR0_CAA_4/DDR0_MA_7 DDR0_CAA_3/DDR0_MA_8 DDR0_CAA_1/DDR0_MA_9

DDR0_CAB_7/DDR0_MA_10 DDR0_CAA_7/DDR0_MA_11 DDR0_CAA_6/DDR0_MA_12 DDR0_CAB_0/DDR0_MA_13

DDR0_CAB_2/DDR0_MA_14 DDR0_CAB_1/DDR0_MA_15 DDR0_CAB_3/DDR0_MA_16

DDR0_CAB_4/DDR0_BA_0 DDR0_CAB_6/DDR0_BA_1 DDR0_CAA_5/DDR0_BG_0

DDR0_CAA_8/DDR0_ACT# DDR0_CAA_9/DDR0_BG_1

Interleave / Non-Interleaved

DDR0_DQSN_0/DDR0_DQSN_0 DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQSN_1/DDR0_DQSN_1 DDR0_DQSP_1/DDR0_DQSP_1 DDR0_DQSN_2/DDR0_DQSN_4 DDR0_DQSP_2/DDR0_DQSP_4 DDR0_DQSN_3/DDR0_DQSN_5 DDR0_DQSP_3/DDR0_DQSP_5 DDR0_DQSN_4/DDR1_DQSN_0 DDR0_DQSP_4/DDR1_DQSP_0 DDR0_DQSN_5/DDR1_DQSN_1 DDR0_DQSP_5/DDR1_DQSP_1 DDR0_DQSN_6/DDR1_DQSN_4 DDR0_DQSP_6/DDR1_DQSP_4 DDR0_DQSN_7/DDR1_DQSN_5 DDR0_DQSP_7/DDR1_DQSP_5

CC1

12

Y

NC/DDR0_ALERT#

NC/DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ_0 DDR0_VREF_DQ_1

DDR1_VREF_DQ

DDR_VTT_CTL

+1.2V_DDR +3VS

5

4

LPDDR3 / DDR4

12

1

2

V32 V31 T32 T31

U36 U37 U34 U35

AE32 AF32 AE31 AF31

AC37 AC36 AC34 AC35 AA35 AB35 AA37 AA36 AB34 W36 Y31 W34 AA34 AC32

AC31 AB32 Y32

W32 AB31 V34

V35 W35

C27 D27 D31 C31 J35 J34 P34 P35 AP35 AP34 AV34 AV35 BB35 BB34 BF34 BF35

W37 W31

F36 D35 D37 E36 C35

RC19 200K_0402_ 1%

0.6V_DDR_VTT_ON [86]

@

CC2 100P_0402_ 50V8J

DDR_A_CLK#0 DDR_A_CLK0 DDR_A_CLK#1 DDR_A_CLK1

DDR_A_CKE0 DDR_A_CKE1 DDR_A_CKE2 DDR_A_CKE3

DDR_A_CS#0 DDR_A_CS#1

DDR_A_ODT0 DDR_A_ODT1

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13

DDR_A_WE# DDR_A_CAS# DDR_A_RAS#

DDR_A_BA0 DDR_A_BA1 DDR_A_BG0

DDR_A_BG1

DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7

DDR_A_ALE RT# DDR_A_PAR

+V_DDR_REFA_R

+V_DDR_REFB_R

DDR_VTT_CNTL

UC1C

DDR_A_CLK#0 [23] DDR_A_CLK0 [23] DDR_A_CLK#1 [23] DDR_A_CLK1 [23]

DDR_A_CKE0 [23] DDR_A_CKE1 [23]

TP9 TP11

DDR_A_CS#0 [23] DDR_A_CS#1 [23] DDR_A_ODT0 [23] DDR_A_ODT1 [23]

DDR_A_MA0 [23] DDR_A_MA1 [23] DDR_A_MA2 [23] DDR_A_MA3 [23] DDR_A_MA4 [23] DDR_A_MA5 [23] DDR_A_MA6 [23] DDR_A_MA7 [23] DDR_A_MA8 [23] DDR_A_MA9 [23] DDR_A_MA10 [23] DDR_A_MA11 [23] DDR_A_MA12 [23] DDR_A_MA13 [23]

DDR_A_WE# [23]

DDR_A_RAS# [23]

DDR_A_BA1 [23] DDR_A_BG0 [23]

DDR_A_BG1 [23]

DDR_A_DQS#0 [23] DDR_A_DQS0 [ 23] DDR_A_DQS#1 [23] DDR_A_DQS1 [ 23] DDR_A_DQS#2 [23] DDR_A_DQS2 [ 23] DDR_A_DQS#3 [23] DDR_A_DQS3 [ 23] DDR_A_DQS#4 [23] DDR_A_DQS4 [ 23] DDR_A_DQS#5 [23] DDR_A_DQS5 [ 23] DDR_A_DQS#6 [23] DDR_A_DQS6 [ 23] DDR_A_DQS#7 [23] DDR_A_DQS7 [ 23]

DDR_A_ALERT# [23] DDR_A_PAR [23] DDR_DRAMRST# [23]

CAD Note: Min trace width=20 mils, spacing of adjacent signal=20 mils

DDR_B_D[0..15][24]

DDR_B_D[16..31][24]

DDR_B_D[32..47][24]

DDR_B_D[48..63][24]

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

lnterleave / Non-lnterle ave d

J22

DDR1_DQ_0/DDR0_DQ_16

H25

DDR1_DQ_1/DDR0_DQ_17

G22

DDR1_DQ_2/DDR0_DQ_18

H22

DDR1_DQ_3/DDR0_DQ_19

F25

DDR1_DQ_4/DDR0_DQ_20

J25

DDR1_DQ_5/DDR0_DQ_21

G25

DDR1_DQ_6/DDR0_DQ_22

F22

DDR1_DQ_7/DDR0_DQ_23

D22

DDR1_DQ_8/DDR0_DQ_24

C22

DDR1_DQ_9/DDR0_DQ_25

C24

DDR1_DQ_10/DDR0_DQ_26

D24

DDR1_DQ_11/DDR0_DQ_27

A22

DDR1_DQ_12/DDR0_DQ_28

B22

DDR1_DQ_13/DDR0_DQ_29

A24

DDR1_DQ_14/DDR0_DQ_30

B24

DDR1_DQ_15/DDR0_DQ_31

G31

DDR1_DQ_16/DDR0_DQ_48

G32

DDR1_DQ_17/DDR0_DQ_49

H29

DDR1_DQ_18/DDR0_DQ_50

H28

DDR1_DQ_19/DDR0_DQ_51

G28

DDR1_DQ_20/DDR0_DQ_52

G29

DDR1_DQ_21/DDR0_DQ_53

H31

DDR1_DQ_22/DDR0_DQ_54

H32

DDR1_DQ_23/DDR0_DQ_55

L31

DDR1_DQ_24/DDR0_DQ_56

L32

DDR1_DQ_25/DDR0_DQ_57

N29

DDR1_DQ_26/DDR0_DQ_58

N28

DDR1_DQ_27/DDR0_DQ_59

L28

DDR1_DQ_28/DDR0_DQ_60

L29

DDR1_DQ_29/DDR0_DQ_61

N31

DDR1_DQ_30/DDR0_DQ_62

N32

DDR1_DQ_31/DDR0_DQ_63

AJ29

DDR1_DQ_32/DDR1_DQ_16

AJ30

DDR1_DQ_33/DDR1_DQ_17

AM32

DDR1_DQ_34/DDR1_DQ_18

AM31

DDR1_DQ_35/DDR1_DQ_19

AM30

DDR1_DQ_36/DDR1_DQ_20

AM29

DDR1_DQ_37/DDR1_DQ_21

AJ31

DDR1_DQ_38/DDR1_DQ_22

AJ32

DDR1_DQ_39/DDR1_DQ_23

AR31

DDR1_DQ_40/DDR1_DQ_24

AR32

DDR1_DQ_41/DDR1_DQ_25

AV30

DDR1_DQ_42/DDR1_DQ_26

AV29

DDR1_DQ_43/DDR1_DQ_27

AR30

DDR1_DQ_44/DDR1_DQ_28

AR29

DDR1_DQ_45/DDR1_DQ_29

AV32

DDR1_DQ_46/DDR1_DQ_30

AV31

DDR1_DQ_47/DDR1_DQ_31

BA32

DDR1_DQ_48/DDR1_DQ_48

BA31

DDR1_DQ_49/DDR1_DQ_49

BD31

DDR1_DQ_50/DDR1_DQ_50

BD32

DDR1_DQ_51/DDR1_DQ_51

BA30

DDR1_DQ_52/DDR1_DQ_52

BA29

DDR1_DQ_53/DDR1_DQ_53

BD29

DDR1_DQ_54/DDR1_DQ_54

BD30

DDR1_DQ_55/DDR1_DQ_55

BG31

DDR1_DQ_56/DDR1_DQ_56

BG32

DDR1_DQ_57/DDR1_DQ_57

BK32

DDR1_DQ_58/DDR1_DQ_58

BK31

DDR1_DQ_59/DDR1_DQ_59

BG29

DDR1_DQ_60/DDR1_DQ_60

BG30

DDR1_DQ_61/DDR1_DQ_61

BK30

DDR1_DQ_62/DDR1_DQ_62

BK29

DDR1_DQ_63/DDR1_DQ_63

WHL-U42 _BGA1528

DDR1_DQSN_0/DDR0_DQSN_2 DDR1_DQSP_0/DDR0_DQSP_2 DDR1_DQSN_1/DDR0_DQSN_3 DDR1_DQSP_1/DDR0_DQSP_3 DDR1_DQSN_2/DDR0_DQSN_6 DDR1_DQSP_2/DDR0_DQSP_6 DDR1_DQSN_3/DDR0_DQSN_7 DDR1_DQSP_3/DDR0_DQSP_7 DDR1_DQSN_4/DDR1_DQSN_2 DDR1_DQSP_4/DDR1_DQSP_2 DDR1_DQSN_5/DDR1_DQSN_3 DDR1_DQSP_5/DDR1_DQSP_3 DDR1_DQSN_6/DDR1_DQSN_6 DDR1_DQSP_6/DDR1_DQSP_6 DDR1_DQSN_7/DDR1_DQSN_7 DDR1_DQSP_7/DDR1_DQSP_7

3 of 20

DDR4 COMPENSATION SIGNALS

SM_RCOMP0

RC17 121_0 402_1%CML@

SM_RCOMP1

RC18 80.6_0 402_1%CML@

SM_RCOMP2

RC20 100_0 402_1%

CAD Note: Trace width=15 mils, Spacing=25 mils(Within Group 20mils) Max trace length= 500 mils

LPDDR3 / DDR4

DDR1_CKN_0/DDR1_CKN_0

DDR1_CKP_0/DDR1_CKP_0

DDR1_CKN_1/DDR1_CKN_1

DDR1_CKP_1/DDR1_CKP_1

DDR1_CKE_0/DDR1_CKE_0 DDR1_CKE_1/DDR1_CKE_1

DDR1_CKE_2/NC DDR1_CKE_3/NC

DDR1_CS#_0/DDR1_CS#_0 DDR1_CS#_1/DDR1_CS#_1

DDR1_ODT_0/DDR1_ODT_0

NC/DDR1_ODT_1 DDR1_CAB_9/DDR1_MA_0 DDR1_CAB_8/DDR1_MA_1 DDR1_CAB_5/DDR1_MA_2

NC/DDR1_MA_3

NC/DDR1_MA_4 DDR1_CAA_0/DDR1_MA_5 DDR1_CAA_2/DDR1_MA_6 DDR1_CAA_4/DDR1_MA_7 DDR1_CAA_3/DDR1_MA_8 DDR1_CAA_1/DDR1_MA_9

DDR1_CAB_7/DDR1_MA_10 DDR1_CAA_7/DDR1_MA_11 DDR1_CAA_6/DDR1_MA_12 DDR1_CAB_0/DDR1_MA_13

DDR1_CAB_2/DDR1_MA_14 DDR1_CAB_1/DDR1_MA_15 DDR1_CAB_3/DDR1_MA_16

DDR1_CAB_4/DDR1_BA_0 DDR1_CAB_6/DDR1_BA_1 DDR1_CAA_5/DDR1_BG_0

DDR1_CAA_9/DDR1_BG_1 DDR1_CAA_8/DDR1_ACT#

lnterleave / Non-lnterleaved

NC/DDR1_ALERT#

NC/DDR1_PAR

DRAM_RESET#

DDR_RCOMP_0 DDR_RCOMP_1 DDR_RCOMP_2

1 2

AF28 AF29 AE28 AE29

T28 T29 V28 V29

AL37 AL35 AL36 AL34 AG36 AG35 AF34 AG37 AE35 AF35 AE37 AC29 AE36 AB29 AG34 AC28 AB28 AK35

AJ35 AK34 AJ34

AJ37 AJ36 W29

Y28 W28

H24 G24 C23 D23 G30 H30 L30 N30 AL31 AL30 AU31 AU30 BC31 BC30 BH31 BH30

Y29 AE34 BU31

BN28 BN27 BN29

DDR_B_CLK#0 DDR_B_CLK0 DDR_B_CLK#1 DDR_B_CLK1

DDR_B_CKE0 DDR_B_CKE1 DDR_B_CKE2 DDR_B_CKE3

DDR_B_CS#0 DDR_B_CS#1

DDR_B_ODT0 DDR_B_ODT1

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13

DDR_B_WE# DDR_B_CAS# DDR_B_RAS#

DDR_B_BA0 DDR_B_BA1 DDR_B_BG0

DDR_B_BG1 DDR_B_ACT#DDR_A_ACT#

DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7

DDR_B_ALE RT# DDR_B_PAR DDR_DRAMRS T#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

RC17

100_0402_1%

SD03410008 0

RC18

100_0402_1%

SD03410008 0

DDR_B_CLK#0 [24] DDR_B_CLK0 [24] DDR_B_CLK#1 [24] DDR_B_CLK1 [24]

DDR_B_CKE0 [24] DDR_B_CKE1 [24]

DDR_B_CS#0 [24] DDR_B_CS#1 [24] DDR_B_ODT0 [24] DDR_B_ODT1 [24] DDR_B_MA0 [24] DDR_B_MA1 [24] DDR_B_MA2 [24] DDR_B_MA3 [24] DDR_B_MA4 [24] DDR_B_MA5 [24] DDR_B_MA6 [24] DDR_B_MA7 [24] DDR_B_MA8 [24] DDR_B_MA9 [24] DDR_B_MA10 [24] DDR_B_MA11 [24] DDR_B_MA12 [24] DDR_B_MA13 [24]

DDR_B_WE# [24] DDR_B_CAS# [24] DDR_B_RAS# [24]DDR_A_CAS# [23]

DDR_B_BA0 [24] DDR_B_BA1 [24]DDR_A_BA0 [23] DDR_B_BG0 [24]

DDR_B_BG1 [24] DDR_B_ACT# [24]DDR_A_ACT# [23]

DDR_B_DQS#0 [24] DDR_B_DQS0 [24] DDR_B_DQS#1 [24] DDR_B_DQS1 [24] DDR_B_DQS#2 [24] DDR_B_DQS2 [24] DDR_B_DQS#3 [24] DDR_B_DQS3 [24] DDR_B_DQS#4 [24] DDR_B_DQS4 [24] DDR_B_DQS#5 [24] DDR_B_DQS5 [24] DDR_B_DQS#6 [24] DDR_B_DQS6 [24] DDR_B_DQS#7 [24] DDR_B_DQS7 [24]

DDR_B_ALERT# [24] DDR_B_PAR [24]

CNL@

TP10 TP12

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

5

Only for Dell

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

2019/06/20 2020/06/30

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU(2/12)DDR4

Size

Custom

Date : Sheet o f

CPU(2/12)DDR4

Document Number Re v

LA-G716P

1

7 101Thursday, June 20, 2019

1.0

5

4

3

2

1

RC21~RC25 place colse to Device

CPU_SPI_0_CLK CPU_SPI_0_D1 CPU_SPI_0_D0 CPU_SPI_0_D2 CPU_SPI_0_D3 CPU_SPI_0_CS#0 CPU_SPI_0_CS#1

FFS_INT1

HDD_DET#

UC3

1

CS#

3

WP#

7

HOLD#

4

GND

W25Q64JVSSIQ_SO8

RC24

TPM@

10_0402_1%

SD034100A80

RC25

TPM@

10_0402_1%

SD034100A80

FFS_INT1

HDD_DET#

CPU_SPI_0_CS#0

CPU_SPI_0_D0

CPU_SPI_0_D2

CPU_SPI_0_D3

CPU_SPI_0_CLK

RC39 49.9_0402_1%FTPM@ RC41 49.9_0402_1%FTPM@

CPU_SPI_CLK CPU_SPI_D1 CPU_SPI_D0 CPU_SPI_D2 CPU_SPI_D3

1 2 1 2

CPU_SPI_CLK[66]

CPU_SPI_D1[66]

D D

C C

RC21 10_0402_1%

SD034100A80

RC22 10_0402_1%

SD034100A80

RC23 10_0402_1%

SD034100A80

+3VS

+3VALW_PCH +3.3V_SPI

+3.3V_SPI

Reserve For EC Auto Load Code

+3.3V_SPI

B B

CPU_SPI_D0[66]

TPM@

1 2

RC27 10K_0402_5%

1 2

RC206 10K_0402_5%

@

1 2

RC30 0_0603_5%

1 2

@

RC31 4.7K_0402_5%

1 2

RC35 100K_0402_5%

1 2

RC36 100K_0402_5%

1 2

RC37 100K_0402_5%

Follow 566439

1 2

RC187 100 K_0402_5%

CPU_SPI_D3

1 2

RC21 0_0402_5%

@

RC22 0_0402_5%

@

1 2 1 2

RC23 0_0402_5%

@

RC24 0_0402_5%

@

1 2

RC25 0_0402_5%

@

1 2

CPU_SPI_0_CS#2[66]

TPM_SPI_IRQ#[66]

FFS_INT1[67]

HDD_DET#[67]

RC21

FTPM@

S RES 1/16W 5.6 +-5% 0402

SD028560B80

RC22

FTPM@

S RES 1/16W 5.6 +-5% 0402

SD028560B80

RC23

FTPM@

S RES 1/16W 5.6 +-5% 0402

SD028560B80

RC24

FTPM@

S RES 1/16W 5.6 +-5% 0402

SD028560B80

RC25

FTPM@

S RES 1/16W 5.6 +-5% 0402

SD028560B80

CPU_SPI_0_CS#0 SPI_D2_ROMCPU_SPI_D2 SPI_D3_ROM

64Mb Flash ROM

+3.3V_SPI

CPU_SPI_0_CS#1

1 2

RC207 4.7K_0402_5%

CPU_SPI_0_CS#1

RC177 49.9_0402_1%FTPM@

A A

CPU_SPI_D3

1 2

RC181 49.9_0402_1%FTPM@

1 2

SPI_D2_ROM2CPU_SPI_D2 SPI_D3_ROM2

UC3 place colse to UX1

UC11

1

CS#

3

WP#

7

HOLD#

4

GND

W25Q128JVSIQ_SO8

UC1E

CH37

SPI0_CLK

CF37

SPI0_MISO

CF36

SPI0_MOSI

CF34

SPI0_IO2

CG34

SPI0_IO3

CG36

SPI0_CS0#

CG35

SPI0_CS1#

CH34

SPI0_CS2#

CF20

GPP_D1/SPI1_CLK/BK1/SBK1

CG22

GPP_D2/SPI1_MISO_IO1/BK2/SBK2

CF22

GPP_D3/SPI1_MOSI_IO0/BK3/SBK3

CG23

GPP_D21/SPI1_IO2

CH23

GPP_D22/SPI1_IO3

CG20

GPP_D0/SPI1_CS0#/BK0/SBK0

CH7

CL_CLK

CH8

CL_DATA

CH9

CL_RST#

BV29

GPP_A0/RCIN#/TIME_SYNC1

BV28

GPP_A6/SERIRQ

WHL-U42_BGA1528

XDP_HOOK3[80]

+3.3V_SPI

8

VCC

6

SCLK

5

SI/SIO0

2

SO/SIO1

+3.3V_SPI

8

VCC

6

SCLK

5

SI/SIO0

2

SO/SIO1

SPI - FLASH

SPI - TOUCH

C LINK

5 of 20

RC32 1K_0402_1%CMC@

1 2

RC40 place to within 1100 mil of SPIO_MOSI/SPI0_IO2 pin for XDP

1 2

CC4 0.1U_04 02_10V7K

SPI_CLK_ROM SPI_D0_ROM SPI_D1_ROM

CC74 0.1U_0402_10V7K

SPI_CLK_ROM2 SPI_D0_ROM2 SPI_D1_ROM2

RC40 49.9_0402_1%FTPM@ RC42 49.9_0402_1%FTPM@ RC43 49.9_0402_1%FTPM@

1 2

RC178 49.9_0402_1%FTPM@ RC180 49.9_0402_1%FTPM@ RC179 49.9_0402_1%FTPM@

1 2 1 2 1 2

CPU_SPI_D0

CPU_SPI_CLK CPU_SPI_D0 CPU_SPI_D1

SMBUS , SMLINK

GPP_B23/SML1ALERT#/PCHHOT#

LPC , ESPI

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

RC39

TPM@

33_0402_1%

SD034330A80

RC40

TPM@

33_0402_1%

SD034330A80

RC41

TPM@

33_0402_1%

SD034330A80

RC42

TPM@

33_0402_1%

SD034330A80

RC43

TPM@

33_0402_1%

SD034330A80

CK14 CH15 CJ15

CH14 CF15 CG15

CN15 CM15 CC34

CA29 BY29 BY27 BV27 CA28 CA27

BV32 BV30 BY30

RC177 33_0402_1%

SD034330A80

RC178 33_0402_1%

SD034330A80

RC179 33_0402_1%

SD034330A80

RC180 33_0402_1%

SD034330A80

RC181 33_0402_1%

SD034330A80

MEM_SMBCLK MEM_SMBDATA GPP_C2

SML0_SMBCLK SML0_SMBDATA GPP_C5

SML1_SMBCLK SML1_SMBDATA GPP_B23

ESPI_IO0 ESPI_IO1 ESPI_IO2 ESPI_IO3

ESPI_RST#

ESPI_CLK

TPM@

SML1_SMBCLK [28,58,66]

SML1_SMBDATA [28,58,66]

ESPI_CS# [58] ESPI_RST# [58]

EMI@

1 2

RC26 33_ 0402_5%

1

CC3 10P_0402_50V8J

2

ESPI_RST#

RC205 100K_0402_5%

SPI_CLK_ROM

33_0402_5%

RC45

1 2

33P_0402_50V8J

1 2

place colse to UC3

MEM_SMBCLK

MEM_SMBDATA

SML1 -> EC, THM, GPU

ESPI_CLK_R [58]

@RF@

12

@EMI@

CC5

@EMI@

+3VS

5

3 4

ESPI_IO0 ESPI_IO1 ESPI_IO2 ESPI_IO3

SML0_SMBCLK

SML0_SMBDATA

QC1A

2

L2N7002DW1T1G_ SC88-6

1

6

QC1B L2N7002DW1T1G_ SC88-6

1 2 1 2

RC192 15_0402_5% RC193 15_0402_5%

1 2 1 2

RC194 15_0402_5% RC195 15_0402_5%

PCH_SMBDATA

PCH_SMBCLK

SML1_SMBCLK

SML1_SMBDATA

MEM_SMBCLK

MEM_SMBDATA

RC196 1K_0402_5%

RC197 1K_0402_5%

RC198 1K_0402_5%

RC199 1K_0402_5%

RC33 1K_0 402_5%

RC34 1K_0 402_5%

Weak Int. PD.

GPP_C2

TLS CONFIDENTIALITY

LOW(DEFAULT) HIGH

Weak Int. PD.

GPP_C5

EC interface

LOW(DEFAULT) HIGH

GPP_B23

Intel DCI-OOB

LOW(DEFAULT) HIGH

SMB -> DDR4, FFS, VGA

PCH_SMBCLK [23,24,40,67]

PCH_SMBDATA [23,24,40,67]

12

RC282.2 K_0402_5%

12

RC292.2 K_0402_5%

+3VALW_PCH

12

+3VALW_PCH

12

RC38 4.7K_0402_5%

DISABLE

ENABLE

+3VALW_PCH

12

RC44 4.7K_0402_5%

LPC eSPI

+3VALW_PCH

CMC@

12

RC46 4.7K_0402_5%

DISABLE

ENABLE

ESPI_IO0_R [58] ESPI_IO1_R [58] ESPI_IO2_R [58] ESPI_IO3_R [58]

+3VS

128Mb Flash ROM

UC11 place colse to UX1

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D DEPARTMENT E XCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT E XCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT E XCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2019/06/20 2020/06/30

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

Compal Electronics, Inc.

CPU(3/12)SPI,ESPI,SMB,LPC

LA-G716P

1

8 101Thursday, June 20, 2019

1.0

Only for Dell

5

ME_FWP

LOW = ENABLE -- >ME lock, can't update ME HIGH = DISABLE -->ME un-lock, can upd ate ME

1 2

HDA_SYNC_R[56]

HDA_BIT_CLK_R[56]

HDA_SDOUT_R[56]

ME_FWP[58]

D D

Weak Int. PD.

HDA_SDOUT

1 2

@

RC51 4.7K_0402 _5%

Flash Descriptor Security override

LOW(DEFAULT) HIGH

+3VALW_PCH

RC57 4.7K_0402 _5%

1 2

@

ENABLE DISA BLE

Weak Int. PD.

SPKR

RC47 33_040 2_5%

1 2

RC48 33_040 2_5%

1 2

RC49 33_040 2_5%

1 2

RC50 1K_040 2_5%

HDA_BIT_CLK

1

@RF@

CC6

2.2P_0201_2 5V8C

2

CNV_RF_RESET#[52]

CLKREQ_CNV#[52]

DGPU_PWROK[27,92,94]

SPKR[56]

Top Swap Override

TPM_ID

1 2

@

1 2

@

1 2

CNV@

1 2

@

DISABLE

ENABLE

BLUETOOTH_ EN

WIFI_RF_EN

DGPU_PWR OK

CNV_RF_RESET #

CLKREQ_CNV#

COMPENSATION FOR CNV_WT_RCOMP

CAD Note: Min trace width=10 mils, Spacing=15 mils Max trace length=500 mils

BOARD_ID1[11]

LOW(DEFAULT) HIGH

C C

+3VALW_PCH

12

FTPM@

RC59 10K_0402_5 %

12

TPM@

RC63 10K_0402_5 %

B B

+3VALW

RC174 10K_0402_5 %

RC175 10K_0402_5 %

+3VS

RC68 10K_0 402_5%

RC74 75K_0 402_1%

RC73 71.5K_0 402_1%

CPU ID

A A

CML-U WHL-U(Reserved) Pentium/Celeron

i3/i5/i7

Only for Dell

5

4

HDA_SYNC HDA_BIT_CLK HDA_SDOUT

HDA_SDIN0[56]

CNV_RF_RESET #

CLKREQ_CNV#

TPM_ID

DGPU_PWR OK

SPKR

CNV_CRX_DTX_N0[52] CNV_CRX_DTX_P0[52]

CNV_CRX_DTX_N1[52]

CNV_CRX_DTX_P1[52] CNV_CTX_DRX_N0[52] CNV_CTX_DRX_P0[52]

CNV_CTX_DRX_N1[52] CNV_CTX_DRX_P1[52]

CLK_CNV_CRX_DTX_N[52] CLK_CNV_CRX_DTX_P[52] CLK_CNV_CTX_DRX_N[52] CLK_CNV_CTX_DRX_P[52]

1 2

RC60 150_0201_ 1%

Follow RVP

BLUETOOTH_EN[52] LCD_CBL_DET#[38]

1 2

RC61 10K_0402_5 %

+3VALW_PCH

BOARD_ID2

BOARD_ID2 (GPP_C 11)

4

@

12

---

RC69 RC71

UC1G

BN34

HDA_SYNC/I2S0_SFRM

BN37

HDA_BCLK/I2S0_SCLK

BN36

HDA_SDO/I2S0_TXD

BN35

HDA_SDI0/I2S0_RXD

BL36

HDA_SDI1/I2S1_RXD/SNDW1_DATA

BL35

HDA_RST#/I2S1_SCLK/SNDW1_CLK

CK23

GPP_D23/I2S_MCLK

BL37

I2S1_SFRM/SNDW2_CLK

BL34

I2S1_TXD/SNDW2_DATA

CJ32

GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#

CH32

GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK

CH29

GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ

CH30

GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO

CP24

GPP_D19/DMIC_CLK0/SNDW4_CLK

CN24

GPP_D20/DMIC_DATA0/SNDW4_DATA

CK25

GPP_D17/DMIC_CLK1/SNDW3_CLK

CJ25

GPP_D18/DMIC_DATA1/SNDW3_DATA

CF35

GPP_B14/SPKR

WHL-U42 _BGA1528

UC1I

CR30

CNV_WR_D0N

CP30

CNV_WR_D0P

CM30

CNV_WR_D1N

CN30

CNV_WR_D1P

CN32

CNV_WT_D0N

CM32

CNV_WT_D0P

CP33

CNV_WT_D1N

CN33

CNV_WT_D1P

CN31

CNV_WR_CLKN

CP31

CNV_WR_CLKP

CP34

CNV_WT_CLKN

CN34

CNV_WT_R COMP

PROJECT_ID1 PROJECT_ID2

BLUETOOTH_ EN

BOARD_ID2

A4WP_PRESEN T

BASE@

RC69 10K_0402_5 %

PREM@

RC71 10K_0402_5 %

BOARD_ID1 (GPP_C12 )

CP32 CR32 CP20

CK19 CG17

CR14 CP14 CN14 CM14

CJ17

CH17

CF17

12

RC70 10K_0402_5 %

12

@

RC72 10K_0402_5 %

CNV_WT_CLKP

CNV_WT_RCOMP_0 CNV_WT_RCOMP_1 GPP_F0/CNV_PA_BLANKING

GPP_F1 GPP_F2

GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_F8/CNV_MFUART2_RXD GPP_F9/CNV_MFUART2_TXD

GPP_F23/A4WP_PRESENT

WHL-U42 _BGA1528

RC70 RC72

---

3

AUDIO SDIO / SDXC

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

7 of 20

CNVio

GPP_H18/CPU_C10_GATE#

GPP_H19/TIMESYNC_0

GPP_H21/XTAL_FREQ_SELECT

GPP_D4/IMGCLKOUT0/BK4/SBK4

GPP_H20/IMGCLKOUT_1

GPP_F12/EMMC_DATA0 GPP_F13/EMMC_DATA1 GPP_F14/EMMC_DATA2

EMMC

GPP_F15/EMMC_DATA3 GPP_F16/EMMC_DATA4 GPP_F17/EMMC_DATA5 GPP_F18/EMMC_DATA6 GPP_F19/EMMC_DATA7

GPP_F20/EMMC_RCLK

GPP_F21/EMMC_CLK

GPP_F11/EMMC_CMD

GPP_F22/EMMC_RESET#

9 of 20

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

GPP_A16/SD_1P8_SEL

GPP_H22 GPP_H23 GPP_F10

GPD7

GPP_F3

EMMC_RCOMP

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

SD_1P8_RCOMP SD_3P3_RCOMP

CH36 CL35 CL36 CM35 CN35 CH35 CK36 CK34

BW36 BY31

CK33

SD_RCOMP

CM34

CN27

CM27

GPP_H21

CF25 CN26

GPP_H23

CM26 CK17

BV35

GPD7 PROJECT_ID3

CN20

WIFI_RF_EN

CG25 CH25

CR20 CM20 CN19 CM19 CN18 CR18 CP18 CM18

CM16 CP16 CR16 CN16

EMMC_RCOMP

CK15

RC64 200_0 402_1%

COMPENSATION FOR EMMC_RCOMP

CAD Note: Min trace width=10 mils, Spacing=12 mils Max trace length=500 mils

2019/06/20 2020/06/30

RC54 200_0402_ 1%

COMPENSATION FOR SD_RCOMP

CAD Note: Min trace width=10 mils, Spacing=12 mils Max trace length=500 mils

CPU_C10_GATE# [78]

WIFI_RF_EN [52]

1 2

Compal Secret Data

Deciphered Date

2

KB_LED_BL_DET [63]

12

2

1

+1.8V_PRIM+3V_HDA

12

PROJECT_ID1 PROJECT_ID3

12

INSPIRON@

RC52 10K_0402_5 %

12

VOSTRO@

RC55 10K_0402_5 %

RC53,RC 56 eMMC SKU Opt i onal

LOW HIGH

GPD PU to DSW PWR rail

GPD7

RC58 100K_040 2_5%

12

Weak Int. PD.

GPP_H21

12

RC62 4.7K_ 0402_5%

XTAL Frequency Select

LOW(DEFAULT) HIGH

38.4MHz 24MHz

Weak Int. PD.

GPP_H23

eSPI Flash Sharing Mode

LOW(DEFAULT) HIGH

+1.8V_PRIM

12

RC200

PROJECT_ID2

10K_0402_5 %

12

@

RC201 10K_0402_5 %

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

Compal Electronics, Inc.

CPU(4/12)HDA,EMMC,SD

12

@

RC65 4.7K_ 0402_5%

MAF EABLE SAF EABLE

RC200,R C201 DIS/UMA SKU Opt i onal

LOW(DEFAULT) HIGH

LA-G716P

1

@

RC53 10K_0402_5 %

RC56 10K_0402_5 %

Stand ard Narrow Border

+3VALW_DSW

+3VALW_PCH

UMA DIS

9 101Thursday, June 20, 20 19

1.0

5

4

3

2

1

12

1 2

+3VALW_DSW

12

+RTC_SOC

CC9

15P_0201_2 5V8J

CC10

15P_0201_2 5V8J

WHL need PD

+3VALW_DSW

RC78,RC81,RC85,RC88 close to Device

CLK_PEG_N0[27]

GPU--->

WLAN--->

D D

LAN--->

SSD--->

CLK_PEG_P0[27]

CLKREQ_PEG#0[28]

CLKREQ_PCIE#1[52]

CLKREQ_PCIE#2[51]

CLKREQ_PCIE#4[68]

+3VS

CLK_PCIE_N1[52] CLK_PCIE_P1[52]

+3VS

CLK_PCIE_N2[51] CLK_PCIE_P2[51]

+3VS

CLK_PCIE_N4[68] CLK_PCIE_P4[68]

+3VS

1 2

RC78 10K_04 02_5%

1 2

RC81 10K_04 02_5%

1 2

RC85 10K_04 02_5%

1 2

RC88 10K_04 02_5%

PCH_PLTRST#

+3VS

UC4 change CPN & Description only

5

PCH_PLTRS T#

C C

1 2

CC79 0.1U_0402_10 V7K

@ESD@

+3VALW_PCH

1 2

RC100 10K_0402_ 5%

B B

+3VALW_DSW

1 2

RC92 4.7K_0402 _5%

1 2

RC93 10K_0402 _5%

UC4

MC74VHC1G08E DFT2G_SC70

SYS_PWROK

07/4 ESD require

SYS_RESET#

PCH_PCIE_W AKE#

LANWAKE#

1

2

P

IN1

IN2

G

3

Jason 2019-04-26

4

O

100K_0402_5%

12

TP20

RC94

H_VCCST_PW RGD[78]

PCIE_WAKE#[51 ,52,58,68]

0.1U_0402_10V7K

1

CC75

ESD@

2

PCH_RSMRST#_Q[80]

1 2

RC75 10K_04 02_5%

RC76 1K_0402_5%@ RC99 62_0402_1 %

PCH_RSMRST #_Q

1 2

RC101 0_0201_5%

1 2

RC102 0_0201_5%

PLTRST# [27 ,51,52,58,66,68]

07/4 ESD require

1 2 1 2

SYS_PWROK[58] RESET_OUT#[58]

@

LANWAKE#[58]

PCH_PLTRS T# SYS_RESET# PCH_RSMRST#_Q

H_CPUPW RGDH_CPUPW RGD_R VCCST_PWR GD

PCH_DPWROK

PCH_PCIE_W AKE#

UC1J

AW2

CLKOUT_PCIE_N_0

AY3

CLKOUT_PCIE_P_0

CF32

GPP_B5/SRCCLKREQ0#

BC1

CLKOUT_PCIE_N_1

BC2

CLKOUT_PCIE_P_1

CE32

GPP_B6/SRCCLKREQ1#

BD3

CLKOUT_PCIE_N_2

BC3

CLKOUT_PCIE_P_2

CF30

GPP_B7/SRCCLKREQ2#

BH3

CLKOUT_PCIE_N_3

BH4

CLKOUT_PCIE_P_3

CE31

GPP_B8/SRCCLKREQ3#

BA1

CLKOUT_PCIE_N_4

BA2

CLKOUT_PCIE_P_4

CE30

GPP_B9/SRCCLKREQ4#

BE1

CLKOUT_PCIE_N_5

BE2

CLKOUT_PCIE_P_5

CF31

GPP_B10/SRCCLKREQ5#

WHL-U42 _BGA1528

UC1K

BJ35

GPP_B13/PLTRST#

CN10

SYS_RESET#

BR36

RSMRST#

AR2

PROCPWRGD

BJ2

VCCST_PWRGOOD

CR10

SYS_PWROK

BP31

PCH_PWROK

BP30

DSW_PWROK

BV34

GPP_A13/SUSWARN#/SUSPW RDACK

BY32

GPP_A15/SUSACK#

BU30

WAKE#

BU32

GPD2/LAN_WAKE#

BU34

GPD11/LANPHYPC

WHL-U42 _BGA1528

CLOCK SINGNALS

10 of 20

SYSTEM POW ER MANAGEMENT

11 of 20

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

AU1 AU2

XTAL_IN

XTAL_OUT

CLKIN_XTAL

RTCX1 RTCX2

SRTCRST#

RTCRST#

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD9/SPL_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_B2/VRALERT#

BT32

CK3 CK2

CJ1 CM3

BN31 BN32

BR37 BR34

SLP_SUS# SLP_LAN#

INTRUDER#

INPUT3VSEL

GPD8/SUSCLK

XCLK_BIASREF

GPP_B11/EXT_PWR_GATE#

CLK_ITPXDP_N CLK_ITPXDP_P

SUSCLK

XTAL24_IN XTAL24_OUT

XCLK_BIASREF REFCLK_CNV_R

PCH_RTCX1 PCH_RTCX2

PCH_SRTCR ST# PCH_RTCR ST#

BJ37 BU36 BU27 BT29

BU29 BT31 BT30 BU37

BU28 BU35 BV36

BR35

CC37 CC36

BT27

TP14 TP15

RC79 0_0201_5%

RC80 0_0201_5%

1 2

RC83 60.4_0402_1 %

1 2

RC84 0_0201_5 %

CNV@

12

RC86 10K_0402_5 %

COMPENSATION FOR XCLK_BIASREF

CAD Note: Min trace width=10 mils, Spacing=15 mils Max trace l ength=1000 mils

SIO_SLP_S3# SIO_SLP_S4#

SIO_SLP_S0# SIO_SLP_S3# SIO_SLP_S4# SIO_SLP_S5#

SIO_SLP_SUS# SIO_SLP_LAN# SIO_SLP_WLAN# SIO_SLP_A#

SIO_PWRBTN# AC_PRESENT PCH_BATLOW #

INTRUDER#

EXT_PWR_GAT E#

INPUT3VSEL

TP17 TP18

TP16

SIO_SLP_S3# [78] SIO_SLP_S4# [78,86] SIO_SLP_S5# [84]

TP19

TP21

TP22

TP23

SIO_PWRBTN# [58]

TP24

1 2

CNV@

1 2

@

SUSCLK_WLAN [52]

SUSCLK_EC [58]

REFCLK_CNV [52]

CLRP1, CLRP2 Always Open

XTAL24_IN XTAL24_OUT

PCH_RTCX1 PCH_RTCX2

PCH_SRTCR ST#

PCH_RTCR ST#

INTRUDER#

1 2

RC89 33 _0402_5%EMI@

12

1 2

EMI@

RC91 33 _0402_5%

RC95 10M_0402_ 5%

1 2

PCH_BATLOW #

AC_PRESENT

SIO_PWRBTN#

AC_PRESENT

SIO_SLP_S3#

SIO_SLP_S4#

07/4 ESD require

INPUT3VSEL

RC77 20K_0 402_5%

1 2

CC7 1U_0201_6.3V6M

1 2

CLRP1 SHORT PADS@

CLR all register bits

RC82 20K_0 402_5%

1 2

CC8 1U_0201_6.3V6M

1 2

CLRP2 SHORT PADS@

CLR CMOS

RC87 1M_0402_5 %

XTAL24_IN_R

200K_0402_1%

RC90

3

4

YC1 24MHZ_12PF_X3G0 24000DC1H

1

2

XTAL24_OUT_R

CC11

1 2

6.8P_0402_5 0V8C

12

YC2

32.768KHZ_9P F_X1A000141000200

20ppm / 9pF ESR <5 0kohm (MAX)

CC12

1 2

6.8P_0402_5 0V8C

12

RC96 10K_0 402_5%

12

@

RC97 10K_0 402_5%

12

@

RC98 100K_ 0402_5%

12

RC66 10K_0 402_5%

12

RC10 100K_ 0402_5%

12

RC11 100K_ 0402_5%

1 2

CC76 0.1U_0402_ 10V7K

@ESD@

@

RC103 4.7K_0402_5%

1 2

RC104 4.7K_0402_5%

3.0V Select

LOW

0: 3.3V supply is 3.3V +- 5%

HIGH

1: 3.3V supply is 3.0V +- 5%

POK

1U_0201_6.3V6M

1M_0402_5%

12

1

RC105

A A

CC14

2

5

RSMRST circuit

PCH_RSMRST#[58]

POK[78,82,85]

UC5 change CPN & Description only

Jason 2019-04-26

Only for Dell

+3VALW

CC13

@

1 2

0.1U_0402_ 10V7K

5

1

P

IN1

2

POK

IN2

3

PCH_RSMRST #_Q

4

O

G

UC5

MC74VHC1G08E DFT2G_SC70

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2019/06/20 2020/06/30

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

Compal Electronics, Inc.

CPU(5/12)CLK,GPIO

LA-G716P

1

10 101Thursday, June 2 0, 2019

1.0

5

4

3

2

1

+1.8V_PRIM

1 2

RC121 20K_0402_5 %

1 2

RC122 20K_0402_5 %

1 2

RC202 20K_0402_5 %

D D

+3VS

1 2

RC106 10K_0402_5 %

+1.8V_PRIM

1 2

RC162 20K_0402_ 5%

1 2

RC108 4.7K_0402_5%

M.2 CNV Mode Select

LOW HIGH

+3VALW_PCH

C C

1 2

RC112 4.7K_0402_5%

NO REBOOT Mode

LOW(DEFAULT) HIGH

+3VALW_PCH

1 2

RC115 4.7K_0402_5%

Boot BIOS Strap

LOW(DEFAULT) HIGH

+3VALW_PCH

1 2

RC182 4.7K_0402_ 5%

B B

1 2

RC183 4.7K_0402_ 5%

CNV@

@

CNV@

@

CNV_BRI_CRX_DTX

CNV_RGI_CRX_DTX

CNV_BRI_CTX_DRX

DBC_PANEL_EN

CNV_RGI_CTX_DRX

CNVi ENABLE CNVi DISABLE

Weak Int. PD.

NRB_BIT

DISABLE

ENABLE

Weak Int. PD.

SD_READ_MODE

SPI

LPC

I2C_3_SDA

I2C_3_SCL

I2C_3_SDA [79]

I2C_3_SCL [79]

UC1F

CC27

GPP_B15/GSPI0_CS0#

CC32

GPP_A7/PIRQA#/GSPI0_CS1#

CE28

VRAM_ID1 NRB_BIT

TP25

CNV_BRI_CRX_DTX

CNV_RGI_CTX_DRX CNV_BRI_CTX_DRX

CNV_RGI_CRX_DTX

SIO_EXT_WAKE# KB_DET#

DBC_PANEL_EN GPP_A11 TOUCH_I2C_D ET#

SD_READ_MODE

I2C_3_SDA I2C_3_SCL

DBC_PANEL_EN[38]

PCH_3.3V_TS_EN[38] SD_READ_MODE[73 ]

CNV_BRI_CRX_DTX[52] CNV_RGI_CTX_DRX[52] CNV_BRI_CTX_DRX[52]

CNV_RGI_CRX_DTX[52]

SIO_EXT_WAKE#[58]

KB_DET#[63]

I2C_0_SDA[63]

I2C_0_SCL[63]

I2C_1_SDA[38]

I2C_1_SCL[38]

PWR MONITOR

GPP_B16/GSPI0_CLK

CE27

GPP_B17/GSPI0_MISO

CE29

GPP_B18/GSPI0_MOSI

CA31

GPP_B19/GSPI1_CS0#

CA32

GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN#

CC29

GPP_B20/GSPI1_CLK

CC30

GPP_B21/GSPI1_MISO

CA30

GPP_B22/GSPI1_MOSI

CK20

GPP_F5/CNV_BRI_RSP

CG19

GPP_F6/CNV_RGI_DT

CJ20

GPP_F4/CNV_BRI_DT

CH19

GPP_F7/CNV_RGI_RSP

CR12

GPP_C20/UART2_RXD

CP12

GPP_C21/UART2_TXD

CN12

GPP_C22/UART2_RTS#

CM12

GPP_C23/UART2_CTS#

CM11

GPP_C16/I2C0_SDA

CN11

GPP_C17/I2C0_SCL

CK12

GPP_C18/I2C1_SDA

CJ12

GPP_C19/I2C1_SCL

CF27

GPP_H4/I2C2_SDA

CF29

GPP_H5/I2C2_SCL

CH27

GPP_H6/I2C3_SDA

CH28

GPP_H7/I2C3_SCL

CJ30

GPP_H8/I2C4_SDA

CJ31

GPP_H9/I2C4_SCL

WHL-U42 _BGA1528

+3VALW_PCH

12

TS_NON@

RC208

TOUCH_I2C_D ET#

10K_0402_5 %

12

TS_I2C@

RC209 10K_0402_5 %

I2C , UART

Change Touch screen detect strap pin define

Jason 2019-06-18

ISH

GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#

6 of 20

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

GPP_D10/ISH_SPI_CLK/GSPI2_CLK GPP_D11/ISH_SPI_MISO/GSPI2_MISO GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_H10/I2C5_SDA/ISH_I2C2_SDA

GPP_H11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD

GPP_D14/ISH_UART0_TXD

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

+3VALW_PCH

VRAM_ID2 VRAM_ID1

12

@

RC117 10K_0402_5 %

12

2G_G5@

RC119 10K_0402_5 %

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

12

@

RC118 10K_0402_5 %

12

2G_G5@

RC120 10K_0402_5 %

CN22 CR22 CM22 CP22

CK22 CH20

CH22 CJ22

CJ27 CJ29

CM24 CN23 CM23 CR24

CG12 CH12 CF12 CG14

BW35 BW34 CA37 CA36 CA35 CA34 BW37

CAM_DET# RTC_DET#

DGPU_PWR _EN VRAM_ID2

FFS_INT2 UART1_RTS# UART1_CTS#

DGPU_HOLD_RST# [27] CAM_DET# [38] RTC_DET# [66]

DGPU_PWR_EN [37,92]

IO_CBL_DET# [73] VGA_CBL_DET# [40]

BOARD_ID1 [9]

FFS_INT2 [67]

TP26 TP27

DGPU_HOLD_R ST#DGPU_HOLD_R ST#

CAM_DET#

FFS_INT2

KB_DET#

RTC_DET#

SIO_EXT_WAKE#

DGPU_PWR _EN

1 2

DIS@

RC107 10K_0402_5%

12

RC204 10K_0402_5%

12

RC109 10K_0402_5%

+3VALW_PCH

12

RC110 10K_0402_5%

12

RC111 100K_0402_5%

12

RC113 10K_0402_5%

+3VS

12

RC114

DIS@

36K_0402_5 %

RC116

DIS@

150K_0402_ 5%

1 2

+3VS

RC208,R C209 Touch panel interface

LOW HIGH

I2C

USB

VRAM ID

(PCBA VRAM Size Config.)

2G GDDR5 Reserved Reserved Reserved

VBIOS_ID2 (GPP_CN23)

0 0 1 1

VBIOS_ID1

(GPP_CE27)

0 1 0 1

*Combine in X76

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Only for Dell

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2019/06/20 2020/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

CPU(6/12)GPIO

LA-G716P

1

11 101Thursday, June 2 0, 2019

1.0

5

PEG_CRX_GTX_N[5..8][27]

PEG_CRX_GTX_P[5..8][27]

PEG_CTX_GRX_N[5..8][27]

PEG_CTX_GRX_P[5..8][27]

D D

GPU --->

LOM --->

WLAN --->

C C

SATA HDD --->

SATA ODD --->

PCIE SSD --->

B B

PEG_CRX _GTX_N[5..8]

PEG_CRX _GTX_P[5..8]

PEG_CTX _GRX_N[5..8]

PEG_CTX _GRX_P[5..8]

PCIE_CRX_DTX_N9[51] PCIE_CRX_DTX_P9[51] PCIE_CTX_DRX_N9[51] PCIE_CTX_DRX_P9[51]

PCIE_CRX_DTX_N10[52] PCIE_CRX_DTX_P10[52] PCIE_CTX_DRX_N10[52] PCIE_CTX_DRX_P10[52]

SATA_CR X_DTX_N0[67]

SATA_CR X_DTX_P0[67] SATA_CT X_DRX_N0[67] SATA_CT X_DRX_P0[67]

SATA_CR X_DTX_N1[67] SATA_CR X_DTX_P1[67]

SATA_CT X_DRX_N1[67] SATA_CT X_DRX_P1[67]

PCIE_CRX_ DTX_N13[68] PCIE_CRX_ DTX_P13[68]

PCIE_CTX_ DRX_N13[68] PCIE_CTX_ DRX_P13[68]

PCIE_CRX_ DTX_N14[68] PCIE_CRX_ DTX_P14[68]

PCIE_CTX_ DRX_N14[68] PCIE_CTX_ DRX_P14[68]

PCIE_CRX_ DTX_N15[68] PCIE_CRX_ DTX_P15[68]

PCIE_CTX_ DRX_N15[68] PCIE_CTX_ DRX_P15[68]

PCIE_CRX_ DTX_N16[68] PCIE_CRX_ DTX_P16[68]

PCIE_CTX_ DRX_N16[68] PCIE_CTX_ DRX_P16[68]

1 2

RC126 100_040 2_1%

PEG_CRX _GTX_N5 PEG_CRX _GTX_P5 PEG_CTX _GRX_N5 PEG_CTX _GRX_P5

PEG_CRX _GTX_N6 PEG_CRX _GTX_P6 PEG_CTX _GRX_N6 PEG_CTX _GRX_P6

PEG_CRX _GTX_N7 PEG_CRX _GTX_P7 PEG_CTX _GRX_N7 PEG_CTX _GRX_P7

PEG_CRX _GTX_N8 PEG_CRX _GTX_P8 PEG_CTX _GRX_N8 PEG_CTX _GRX_P8

PCIE_RCOM PN PCIE_RCOM PP

COMPENSATION FOR PCIE_RCOMP

CAD Note: Min trace width=10 mils Max trace mismatch=5 mils

A A

4

UC1H

BW9

PCIE5_RXN/USB31_5_RXN

BW8

PCIE5_RXP/USB31_5_RXP

BW4

PCIE5_TXN/USB31_5_TXN

BW3

PCIE5_TXP/USB31_5_TXP

BU6

PCIE6_RXN/USB31_6_RXN

BU5

PCIE6_RXP/USB31_6_RXP

BU4

PCIE6_TXN/USB31_6_TXN

BU3

PCIE6_TXP/USB31_6_TXP

BT7

PCIE7_RXN

BT6

PCIE7_RXP

BU2

PCIE7_TXN

BU1

PCIE7_TXP

BU9

PCIE8_RXN

BU8

PCIE8_RXP

BT4

PCIE8_TXN

BT3

PCIE8_TXP

BP5

PCIE9_RXN

BP6

PCIE9_RXP

BR2

PCIE9_TXN

BR1

PCIE9_TXP

BN6

PCIE10_RXN

BN5

PCIE10_RXP

BR4

PCIE10_TXN

BR3

PCIE10_TXP

BN10

PCIE11_RXN/SATA0_RXN

BN8

PCIE11_RXP/SATA0_RXP

BN4

PCIE11_TXN/SATA0_TXN

BN3

PCIE11_TXP/SATA0_TXP

BL6

PCIE12_RXN/SATA1A_RXN

BL5

PCIE12_RXP/SATA1A_RXP

BN2

PCIE12_TXN/SATA1A_TXN

BN1

PCIE12_TXP/SATA1A_TXP

BK6

PCIE13_RXN

BK5

PCIE13_RXP

BM4

PCIE13_TXN

BM3

PCIE13_TXP

BJ6

PCIE14_RXN

BJ5

PCIE14_RXP

BL2

PCIE14_TXN

BL1

PCIE14_TXP

BG5

PCIE15_RXN/SATA1B_RXN

BG6

PCIE15_RXP/SATA1B_RXP

BL4

PCIE15_TXN/SATA1B_TXN

BL3

PCIE15_TXP/SATA1B_TXP

BE5

PCIE16_RXN/SATA2_RXN

BE6

PCIE16_RXP/SATA2_RXP

BJ4

PCIE16_TXN/SATA2_TXN

BJ3

PCIE16_TXP/SATA2_TXP

CE6

PCIE_RCOMP_N

CE5

PCIE_RCOMP_P

CR28

GPP_H12/M2_SKT2_CFG_0

CP28

GPP_H13/M2_SKT2_CFG_1

CN28

GPP_H14/M2_SKT2_CFG_2

CM28

GPP_H15/M2_SKT2_CFG_3

WHL -U42_BGA1528

PCIE / USB3.1 / SATA

3

PCIE1_RXN/USB31_1_RXN PCIE1_RXP/USB31_1_RXP PCIE1_TXN/USB31_1_TXN

PCIE1_TXP/USB31_1_TXP

PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN

PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP

PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN

PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP

PCIE3_RXN/USB31_3_RXN PCIE3_RXP/USB31_3_RXP PCIE3_TXN/USB31_3_TXN

PCIE3_TXP/USB31_3_TXP

PCIE4_RXN/USB31_4_RXN PCIE4_RXP/USB31_4_RXP PCIE4_TXN/USB31_4_TXN

PCIE4_TXP/USB31_4_TXP

USB2.0

USB2_VBUSSENSE

GPP_E9/USB2_OC0#/GP_BSSB_CLK

GPP_E10/USB2_OC1#/GP_BSSB_DI

GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#/SPI1_CS1#

8 of 20

GPI O

USB_ OC0 #

USB_ OC1 #

USB_ OC2 #

USB_ OC3 #

DEVS LP0

DEVS LP1

DEVS LP2

CB5 CB6 CA4 CA3

BY8 BY9 CA2 CA1

BY7 BY6 BY4 BY3

BW6 BW5 BW2 BW1

CE3

USB2_1N

CE4

USB2_1P

CE1

USB2_2N

CE2

USB2_2P

CG3

USB2_3N

CG4

USB2_3P

CD3

USB2_4N

CD4

USB2_4P

CG5

USB2_5N

CG6

USB2_5P

CC1

USB2_6N

CC2

USB2_6P

CG8

USB2_7N

CG9

USB2_7P

CB8

USB2_8N

CB9

USB2_8P

CH5

USB2_9N

CH6

USB2_9P

CC3

USB2_10N

CC4

USB2_10P

USB2_ID

RSVD_69

CC5 CE8 CC6

CK6 CK5 CK8 CK9

CP8 CR8 CM8

CN8 CM10 CP10

CN7

AR3

USB2_COMP

DEVICE CONTROL

USB Port (MB)

USB Port (DB)

NA

USB Port (Type-C)

HDD

NA

M.2 SSD

USB2_CO MP USB2_ID USB2_VB USSENSE

USB_OC0 # USB_OC1 # USB_OC2 # USB_OC3 #

SATA_LE D#

2

USB3_CRX_DTX_N1 [71] USB3_CRX_DTX_P1 [71] USB3_CTX_DRX_N1 [71] USB3_CTX_DRX_P1 [71]

USB3_CRX_DTX_N2 [71] USB3_CRX_DTX_P2 [71] USB3_CTX_DRX_N2 [71] USB3_CTX_DRX_P2 [71]

USB3_CRX_MTX_N4 [42] USB3_CRX_MTX_P4 [42] USB3_CTX_MRX_N4 [42 ] USB3_CTX_MRX_P4 [42]

USB20_N 1 [71 ] USB20_P 1 [71]

USB20_N 2 [71 ] USB20_P 2 [71]

USB20_N 3 [73 ] USB20_P 3 [73]

USB20_N 4 [43 ] USB20_P 4 [43]

USB20_N 5 [66 ] USB20_P 5 [66]

USB20_N 6 [38 ] USB20_P 6 [38]

USB20_N 7 [73 ] USB20_P 7 [73]

USB20_N 8 [43 ] USB20_P 8 [43]

USB20_N 10 [5 2] USB20_P 10 [52]

1 2

RC123 113_04 02_1%

1 2

RC124 0_0402 _5%@

1 2

RC125 0_0402 _5%@

USB_OC0# [71] USB_OC1# [73]

USB_OC3# [50]

HDD_DEVSLP [67]

SSD_DEVSLP [68]

SATA_OD D_PRSNT# [67] M2_SSD_ PEDET [68]

SATA_LED# [63,68]

SATA_LE D#

USB_OC3 # USB_OC0 # USB_OC1 # USB_OC2 #

1 2

RC127 10K_0402_5%

1 2 1 2

RC188 10K_040 2_5%

1 2

RC189 10K_040 2_5%

1 2

RC190 10K_040 2_5% RC191 10K_040 2_5%

---> USB3.0 (MB)

---> TYPE C

-----> USB2.0 (MB)

-----> USB2.0 (M/B)

-----> USB2.0 (IO/B)

-----> Touch Screen

-----> Finger Printer

-----> CCD

-----> Card Reader (IO/B)

(Reserved)

-----> BT

COMPENSATION FOR USB2_COMP

CAD Note: Min trace width=50 Ohm, Spacing=15 mils Max trace length=500 mils

+3VS

+3VALW_P CH

1

Port 4, 8 Colay Opt i onal

Security Classification

2019/06/ 20 2020/06/ 30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Only for Dell

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/ 20 2020/06/ 30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

CPU(7/12)PCIE,USB,SATA

LA-G716P

12 101Thursday, June 20 , 2019

1

1.0

5

4

3

2

1

1 2

+VCCIO

4.06 6A

+VCC_SA

6A

VCCIO_SENSE VSSIO_SENSE

TP30 TP31

12

VSA_SEN- [88] VSA_SEN+ [88]

Trace Length Match< 25 mils

RC165 100_0402_1%

+VCCST

0.1U_0201_6.3V6K

1U_0201_6.3V6M

1

2

+VCCIO

10U_0402_6.3V6M

1

2

+VCCIO : 10UF/6.3V/0402 *6 1UF/6.3V/0402 * 8

+1.2V_DDR

22U_0603_6.3V6M

1

2

CC16

CC15

2

10U_0402_6.3V6M

1

CC20

2

1

CC34

2

10U_0402_6.3V6M

1

CC21

CC22

2

10U_0402_6.3V6M

1

CC35

CC36

2

+VCCPLL_OC +VCCST

PSC Side, BL27,BM26

1U_0201_6.3V6M

1

CC17

2

10U_0402_6.3V6M

1

CC23

2

10U_0402_6.3V6M

1

CC37

2

1

CC24

2

10U_0402_6.3V6M

1

CC38

2

1

CC25

2

10U_0402_6.3V6M

1

CC39

2

1

2

1U_0201_6.3V6M

1

CC26

2

10U_0402_6.3V6M

1

CC40

2

+VCCSTG

PSC Side, BP11,BP2PSC Side, BR11,BT11

1U_0201_6.3V6M

22U_0603_6.3V6M

@

1

CC18

CC72

2

PSC Side, BG1,BG2

1U_0201_6.3V6M

1

CC19

2

PSC SideBSC Side

1U_0201_6.3V6M

1

CC27

2

1U_0201_6.3V6M

1

CC28

CC29

2

1U_0201_6.3V6M

@

1

2

@

1

CC30

CC31

2

1U_0201_6.3V6M

@

1

CC33

CC32

2

BSC SidePSC Side

1U_0201_6.3V6M

1

CC42

CC41

2

1U_0201_6.3V6M

1

CC43

2

10U_0402_6.3V6M

1

CC44

1

CC45

2

10U_0402_6.3V6M

1

CC46

CC47

2

+1.2V_DDR

UC1N

AD36

3.3 A

D D

+VCCST

+VCCSTG

+VCCPLL_OC

+VCCST

C C

B B

60

20

12 0

13 0

AH32

AH36 AM36 AN32

AW32

AY36

BE32 BH36

R32 Y36

BC28

BP11

BP2

BG1 BG2

BL27 BM26

BR11

BT11

WHL-U42_BGA1528

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11

RSVD1

VCCST1 VCCST2

VCCSTG1 VCCSTG2

VCCPLL_OC1 VCCPLL_OC2

VCCPLL1 VCCPLL2

CPU POWER 3 OF 4

14 of 20

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

+VCC_SA

AK24

VCCIO1

AK26

VCCIO2

AL24

VCCIO3

AL25

VCCIO4

AL26

VCCIO5

AL27

VCCIO6

AM25

VCCIO7

AM27

VCCIO8

BH24

VCCIO9

BH25

VCCIO10

BH26

VCCIO11

BH27

VCCIO12

BJ24

VCCIO13

BJ26

VCCIO14

BP16

VCCIO15

BP18

VCCIO16

BG8

VCCSA2

BG10

VCCSA1

BH9

VCCSA3

BJ8

VCCSA5

BJ9

VCCSA6

BJ10

VCCSA4

BK8

VCCSA9

BK25

VCCSA7

BK27

VCCSA8

BL8

VCCSA13

BL9

VCCSA14

BL10

VCCSA10

BL24

VCCSA11

BL26

VCCSA12

BM24

VCCSA15

BN25

VCCSA16

BP28 BP29

BE7 BG7

RC164 100_0402_1%

+1.2V_VDDQ : 22UF/6.3V/0603 *1 10UF/6.3V/0603 *9 1UF/6.3V/0402 * 4

A A

Security Classification

2019/06/20 2020/06/30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2019/06/20 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

B

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

CPU(8/12)POWER

Document Number Re v

CPU(8/12)POWER

LA-G716P

1

13 101Thursday, June 20, 2019

1.0

Only for Dell

5

+1.05V_PRIM

1 2

@

RC128 0_0603_5%

1U_0402_6.3V6K

1

CC53

2

1U_0402_6.3V6K

1

CC56

2

Close to CP17

1U_0201_6.3V6M

1

CC64

2

1

2

12

1

2

1

2

D D

+1.05V_PRIM

1 2

RC129 0_0603_5%

+1.05V_PRIM

C C

+3VALW_PCH

B B

+3VALW_PCH

A A

1 2

RC130 0_0603_5%

1 2

@

RC131 0_0402_5%

1 2

@

RC132 0_0402_5%

+1.8V_PRIM

5

22U_0603_6.3V6M

CC49

47U_0603_6.3V6M

CC54

47U_0603_6.3V6M

CC57

1U_0201_6.3V6M

CC60

1U_0201_6.3V6M

Close to BR24

@

CC63

+1.05V_MPHY

Close to BV12

+1.05V_MPHYPLL

Close to BV2

+1.05V_XTAL

Close to CP5

+3V_HDA

Close to BT20

+3VALW_DSW

+3VALW_PCH

Close to CP29

1U_0201_6.3V6M

1

2

0.1U_0201_6.3V6K

1

@

CC65

2

4

+1.05V_PRIM

Close to BP20

+1.05V_PRIM

Close to BV18

1U_0201_6.3V6M

1

CC55

2

+1.05V_VCCDSW

Close to BT24

1U_0201_6.3V6M

1

CC59

2

+1.05V_PRIM

1U_0201_6.3V6M

1

CC62

2

@

CC66

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

1U_0402_6.3V6K

1

2

+1.8V_PRIM

+3VALW_PCH

@

+1.05V_PRIM

+1.05V_MPHY

+1.05V_MPHYPLL

+1.05V_PRIM

+3VALW_DSW

+3V_HDA

+3.3V_SPI

+1.05V_MPHY

CC48

69 6

4.26 A

Intenal VRM

24

2.87 8A

15 2

1

6

2

3

1.62 5A

28 0

2019/06/20 2020/06/30

UC1P

BP20

VCCPRIM_1P05_1

BW16

VCCPRIM_1P05_9

BW18

VCCPRIM_1P05_10

BW19

VCCPRIM_1P05_11

BY16

VCCPRIM_1P05_12

CA14

VCCPRIM_1P05_14

CC15

VCCPRIM_1P8_1

CD15

VCCPRIM_1P8_4

CD16

VCCPRIM_1P8_5

CP17

VCCPRIM_1P8_8

CB22

VCCPRIM_3P3_4

CB23

VCCPRIM_3P3_5

CC22

VCCPRIM_3P3_6

CC23

VCCPRIM_3P3_7

CD22

VCCPRIM_3P3_8

CD23

VCCPRIM_3P3_9

CP29

VCCPRIM_3P3_10

BU15

VCCPRIM_CORE1

BU22

VCCPRIM_CORE2

BV15

VCCPRIM_CORE3

BV16

VCCPRIM_CORE4

BV18

VCCPRIM_CORE5

BV19

VCCPRIM_CORE6

BV20

VCCPRIM_CORE7

BV22

VCCPRIM_CORE8

BW20

VCCPRIM_CORE9

BW22

VCCPRIM_CORE10

CA12

VCCPRIM_CORE11

CA16

VCCPRIM_CORE12

CA18

VCCPRIM_CORE13

CA19

VCCPRIM_CORE14

CA20

VCCPRIM_CORE15

CB12

VCCPRIM_CORE16

CB14

VCCPRIM_CORE17

CB15

VCCPRIM_CORE18

BT24

VCCDSW_1P05

BU14

VCCAPLL_1P05_4

BV12

VCCPRIM_MPHY_1P05_1

BW12

VCCPRIM_MPHY_1P05_3

BW14

VCCPRIM_MPHY_1P05_4

BY12

VCCPRIM_MPHY_1P05_5

BY14

VCCPRIM_MPHY_1P05_6

BV2

VCCAMPHYPLL_1P05

BR15

VCCAPLL_1P05_2

CC12

VCCDUSB_1P05

BR24

VCCDSW_3P3_1

BT20

VCCHDA

BV23

VCCSPI

BT18

VCCPRIM_1P05_4

BT19

VCCPRIM_1P05_5

BU18

VCCPRIM_1P05_7

BU19

VCCPRIM_1P05_8

BT22

VCCPRIM_1P05_6

BP22

VCCPRIM_1P05_2

BV14

VCCPRIM_MPHY_1P05_2

WHL-U42_BGA1528

3

CPU POWER 4 OF 4

16 of 20

Compal Secret Data

Deciphered Date

VCCPRIM_3P3_3

VCCRTC

VCCPRIM_1P05_13

DCPRTC

VCCPRIM_1P05_3

VCCAPLL_1P05_3

VCCA_BCLK_1P05

VCCAPLL_1P05_1

VCCA_SRC_1P05

VCCA_XTAL_1P05

VCCDPHY_1P24_2 VCCDPHY_1P24_4

VCCDPHY_1P24_1 VCCDPHY_1P24_3 VCCDPHY_1P24_5

VCCDSW_3P3_2

VCCA_19P2_1P05

VCCPRIM_1P8_2 VCCPRIM_1P8_3 VCCPRIM_1P8_6 VCCPRIM_1P8_7 VCCPRIM_1P8_9

VCCPRIM_3P3_2

VCCPRIM_3P3_1

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

2

CB16

BR23

BY20 BP24

Intenal VRM

BR20

BT12

BP14

BR14

BU12

CP5

BY24 CA24

BY23 CA23 CP25

BT23

BR12

CC18 CC19 CD18 CD19 CP23

BW23

BP23

CB36 CB35

2

1 2

CC50 1U_0201_6.3V6M@

+3VALW_PCH

+1.05V_PRIM

Close to BP24

+1.05V_PRIM

+RTC_SOC

Close BR23

1

2

9

10 2

42

2

+1.05V_XTAL

61 0

+VCCLDOSRAM_1P24

VCCDPHY_1P24

Intenal VRM

27

19 9

PRIMCORE_VID0 PRIMCORE_VID1

+VCCLDOSRAM_1P24 VCCDPHY_1P24

Title

Size

B

Date : Sheet o f

Close to CP25

1 2

CNV@

LA-G716P

1

2

+3VALW_DSW

+1.05V_PRIM

+1.8V_PRIM

+3VALW_PCH

TP28 TP29

RC133 0_0402_5%

Compal Electronics, Inc.

CPU(9/12)Power

Document Number Re v

1

1U_0201_6.3V6M

0.1U_0402_10V7K CC51

1

CC52

2

CC58

4.7U_0402_6.3V6M

+1.8V_PRIM

Close to CP23

1U_0201_6.3V6M

1

CC61

@

2

1.0

14 101Thursday, June 20, 2019

1

Only for Dell

5

+VCC_CO RE

UC1L

AN9

VCCCORE5

AN10

VCCCORE1

AN24

VCCCORE2

AN26

VCCCORE3

AN27

VCCCORE4

AP2

VCCCORE6

AP9

VCCCORE9

AP24

VCCCORE7

D D

C C

AP26

AR5 AR6 AR7

AR8 AR10 AR25 AR27

AT9

AT24 AT26

AU5

AU6

AU7

AU8

AU9 AU24 AU25 AU26 AU27

AV2

AV5

AV7 AV10 AV27

AW5 AW6 AW7 AW8 AW9

AW10

BB9 BC24

AY9 BB24

WHL -U42_BGA1528

VCCCORE8 VCCCORE13 VCCCORE14 VCCCORE15 VCCCORE16 VCCCORE10 VCCCORE11 VCCCORE12 VCCCORE19 VCCCORE17 VCCCORE18 VCCCORE24 VCCCORE25 VCCCORE26 VCCCORE27 VCCCORE28 VCCCORE20 VCCCORE21 VCCCORE22 VCCCORE23 VCCCORE30 VCCCORE32 VCCCORE33 VCCCORE29 VCCCORE31 VCCCORE39 VCCCORE40 VCCCORE41 VCCCORE42 VCCCORE43 VCCCORE34

RSVD3 RSVD4 RSVD1 RSVD2

SVID ALERT

B B

VIDALERT#

SVID DATA

CPU POWER 1 OF 4

12 of 20

1 2

RC135 220_0402_5%

VCCCORE35 VCCCORE36 VCCCORE37 VCCCORE38 VCCCORE44 VCCCORE45 VCCCORE48 VCCCORE49 VCCCORE50 VCCCORE46 VCCCORE47 VCCCORE51 VCCCORE52 VCCCORE56 VCCCORE57 VCCCORE58 VCCCORE59 VCCCORE53 VCCCORE54 VCCCORE55 VCCCORE63 VCCCORE64 VCCCORE60 VCCCORE61 VCCCORE62 VCCCORE69 VCCCORE65 VCCCORE66 VCCCORE67 VCCCORE68 VCCCORE70 VCCCORE73 VCCCORE71 VCCCORE72 VCCCORE74

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

RSVD5

VCCSTG1

+VCCST

12

RC134 56_0402 _5%

+VCCST

12

RC136 100_040 2_1%

AW24 AW25 AW26 AW27 AY24 AY26 BA5 BA7 BA8 BA25 BA27 BB2 BB26 BC5 BC6 BC7 BC9 BC10 BC26 BC27 BD5 BD8 BD10 BD25 BD27 BE9 BE24 BE25 BE26 BE27 BF2 BF9 BF24 BF26 BG27

AN6 AN5

AA3

AA1

AA2

Y3

BG3

4

+VCC_CO RE

VIDALERT#

VIDSOUT

+VCCSTG

VIDALERT_N [88]

+VCC_CORE

12

RC167 100_040 2_1%

VCCSENSE [88 ]

12

VIDSCLK [88]

CAD Note: Place the PU resistors close to CPU close to CPU 3000mils

VSSSENSE [88]

Trace Len gth Match< 25 mils

RC168 100_040 2_1%

(To VR)

CAD Note: Place the PU resistors close to CPU close to CPU 3000mils

3

Jason 2019-04-24

+VCC_CO RE

+VCC_GT

RSV for +VCC_OPC

UC1M

A5

VCCGT8

A6

VCCGT9

A8

VCCGT10

A11

VCCGT1

A12

VCCGT2

A14

VCCGT3

A15

VCCGT4

A17

VCCGT5

A18

VCCGT6

A20

VCCGT7

ES1/ES 2

AA9

VCCGT11/VCCCORE75

AB2

VCCGT13/VCCCORE76

AB8

VCCGT14/VCCCORE77

AB9

VCCGT15/VCCCORE78

AB10

VCCGT12/VCCCORE79

AC8

VCCGT16/VCCCORE80

AD9

VCCGT17/VCCCORE81

AE8

VCCGT19/VCCCORE82

AE9

VCCGT20/VCCCORE83

AE10

VCCGT18/VCCCORE84

AF2

VCCGT22/VCCCORE85

AF8

VCCGT23/VCCCORE86

AF10

VCCGT21/VCCCORE87

AG8

VCCGT24/VCCCORE88

AG9

VCCGT25/VCCCORE89

AH9

VCCGT26/VCCCORE90

AJ8

VCCGT28/VCCCORE91

AJ10

VCCGT27/VCCCORE92

AK2

VCCGT29//VCCCORE93

AK9

VCCGT30/VCCCORE94

AL8

VCCGT32/VCCCORE95

AL9

VCCGT33/VCCCORE96

AL10

VCCGT31/VCCCORE97

AM8

VCCGT34/VCCCORE98

V2

VCCGT115/VCCCORE99

Y10

VCCGT119/VCCCORE100

Y8

VCCGT120/VCCCORE101

B3

VCCGT39

B4

VCCGT40

B6

VCCGT41

B8

VCCGT42

B11

VCCGT35

B14

VCCGT36

B17

VCCGT37

B20

VCCGT38

C2

VCCGT49

C3

VCCGT51

C6

VCCGT52

C7

VCCGT53

C8

VCCGT54

C11

VCCGT43

C12

VCCGT44

C14

VCCGT45

C15

VCCGT46

C17

VCCGT47

C18

VCCGT48

C20

VCCGT50

D4

VCCGT62

D7

VCCGT63

D11

VCCGT55

D12

VCCGT56

D14

VCCGT57

WHL -U42_BGA1528

UC1O

K12

RSVD48

K14

RSVD49

K15

RSVD50

K17

RSVD51

K18

RSVD52

K20

RSVD53

L25

RSVD54

M24

RSVD55

M26

RSVD56

P24

RSVD57

P26

RSVD58

R24

RSVD59

R25

RSVD60

R26

RSVD61

2

31A70A

CPU POWER 2 OF 4

13 of 20

RESERVED SIGNALS

VCCGT_SENSE VSSGT_SENSE

RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 RSVD46 RSVD47

VCCGT58 VCCGT59 VCCGT60 VCCGT61 VCCGT64 VCCGT69 VCCGT70 VCCGT71 VCCGT72 VCCGT65 VCCGT66 VCCGT67 VCCGT68 VCCGT73 VCCGT74 VCCGT75 VCCGT76 VCCGT77 VCCGT78 VCCGT79 VCCGT87 VCCGT88 VCCGT89 VCCGT90 VCCGT80 VCCGT81 VCCGT82 VCCGT83 VCCGT84 VCCGT85 VCCGT86 VCCGT95 VCCGT96 VCCGT91 VCCGT92 VCCGT93 VCCGT94 VCCGT98

VCCGT97 VCCGT100 VCCGT101

VCCGT99 VCCGT102 VCCGT104 VCCGT105 VCCGT106 VCCGT103 VCCGT107 VCCGT108 VCCGT109 VCCGT111 VCCGT112 VCCGT110 VCCGT114 VCCGT113

VCCGT116 VCCGT117 VCCGT118

AA24 AA26 AB25 AC24 AC25 AC26 AD24 AD26 V25 T25

+VCC_GT

D15 D17 D18 D20 E4 F5 F6 F7 F8 F11 F14 F17 F20 G11 G12 G14 G15 G17 G18 G20 H5 H6 H7 H8 H11 H12 H14 H15 H17 H18 H20 J7 J8 J11 J14 J17 J20 K2 K11 L7 L8 L10 M9 N7 N8 N9 N10 P2 P8 R9 T8 T9 T10 U8 U10

V9 W8 W9

E3 D2

12

RC170 100_040 2_1%

+VCC_GT

RSV for +VCC_EDRAM_EOPIO

1

12

RC169 100_040 2_1%

VCC_GT_SENSE [88] VSS_GT_SENSE [88]

Trace Len gth Match< 25 mils

VIDSOUT

A A

VIDSOUT [88]

Only for Dell

5

4

(To VR)

Security Classification

2019/06/ 20 2020/06/ 30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/ 20 2020/06/ 30

3

Compal Secret Data

Deciphered Date

W25

RSVD62

V24

RSVD63

Y25

RSVD64

Y24

RSVD65

WHL -U42_BGA1528

2

15 of 20

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet o f

Compal Electronics, Inc.

CPU(10/12)POWER,SVID

LA-G716P

15 101Thursday, June 20 , 2019

1

1.0

5

UC1R

CR34

BT5 BY5

CP35

CM37

CK37

AW1

D D

C C

B B

CM1 BD6

AY4 B34 E35

AE24 AE26

AF25 AG24 AG26 AH24 AH25

B36 C36

C37 CN1 CN2

CN37

CP2

A32

F33

BJ7

CJ36

A36

BK10

CJ4

AB27

BK2 CK1

AB3

BK28 AB30

BK3 CK4

AB33 BK33

CK7

AB36

BK4

CL2

AB4

BK7

CM13

AB7

BL25

CM17

AC10

BL28

CM21

AC27

BL29

CM25

AC30

BL30

CM29

BL31

CM31

AD33

BL32

CM33

AD35

A4

B2

D1

A3

GND 1 OF 3

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72

WHL-U42_BGA1528

17 of 20

VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144

BL7 AE25 BM33 CM5 AE27 BM35 CM9 AE30 BM36 CN13 AE7 BM9 CN17 AF27 BN30 CN21 AF3 BN7 CN25 AF30 CN29 AF33 BP15 AF36 AF4 CN5 AF7 BP25 CN9 AG10 BP3 CP1 BP32 CP11 AH27 BP33 CP13 AH28 BP4 CP15 AH29 BP7 CP19 AH30 CP21 AH31 BR19 CP27 AH33 BR25 AH35 CP37 AJ25 BT15 AJ28 BT16 CP9 AJ7 CR2 AK3 CR36 AK33 D21 AK36 BT25 D25 AK4 BT28 AL28 BT33 D5 AL29

4

UC1S

BT35

D6 AL32 BT36

D8

AL7

D9

AM10 BU11

E23

AM28

E27 AM33 BU23

E29 AM35 BU24

E31 BU25

E33 AN25

BU7

E9

AN28

BV11

F12

AN29

F15

AN30

F18

AN31

BV3

F2

AN7

BV31

F21

AN8

BV33

F24

BV4

F3

AP3

BW11

F4

AP33

BW15

G21

AP36

G27

AP4

G33 AR28

G35

G36

AT33

BW24

G9

AT35

H21

AT36

BW7

H27

AT4

BY11

AU10

BY15

H9

AU28

BY22

J12

AU29

J15

WHL-U42_BGA1528

VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216

GND 2 OF 3

18 of 20

VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289

BY25 J18 AU32 BY28 J21 AV25 BY33 J24 AV28 BY35 J33 AV3 BY36 J36 AV33 J6 AV36 C1 K21 AV4 C21 K22 AV6 C25 K24 AV8 C29 K25 AW28 C33 K27 AW29 C4 K28 AW3 C9 K29 AW30 CA11 K3 AW31 CA15 K30 AY33 CA22 K31 AY35 K32 B12 K4 B15 CA25 K9 B18 CB11 L27 B21 L33 B23 L35 B25 CB18 L36 B27 CB19 L6 B29 CB2 N25 B31 CB20 N27 CB25

3

N6

B37

CB3

P10

B5

CB33

P3 B7

CB4

P33

B9

CB7

P36 BA10 CC11

P4

BA28

P7

BA3 CC20

R27

BB3 CC25

R28 BB33 CC28

R29 BB36 CC31

R30

BB4

CC7

R31 BC25 CD11

T27

CD12

T30 BC29 CD14

T33

T35 BC32 CD24

T36 CD25

T7

BC8

CE33

U26 BD28 CE35

U7 BD33 CE36

V26

BD35

CE7

V27 BD36 CF11

V3 BE10 CF14

V30 BE28 CF19

V33 BE29

CF2

V36

BE3

2

UC1T

GND 3 OF 3

VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361

WHL-U42_BGA1528

19 of 20

VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369 VSS_370 VSS_371 VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395 VSS_396 VSS_397 VSS_398 VSS_399 VSS_400 VSS_401 VSS_402 VSS_403 VSS_404 VSS_405 VSS_406 VSS_407 VSS_408 VSS_409 VSS_410 VSS_411 VSS_412 VSS_413 VSS_414 VSS_415 VSS_416 VSS_417 VSS_418 VSS_419 VSS_420 VSS_421 VSS_422 VSS_423 VSS_424 VSS_425 VSS_426 VSS_427 VSS_428 VSS_429 VSS_430 VSS_431 VSS_432 VSS_433

CF23 V4 BE30 CF28 W10 BE31 CF3 W27 CF4 W30 BF3 CG33 W7 BF33 CG7 BF36 Y26 BF4 CH31 Y27 BG25 Y30 BG28 CJ11 Y33 CJ14 Y35 BH28 CJ19 Y7 BH29 CJ23 BH32 CJ28 BH33 CJ33 BH35 CJ35 BP19 BR16 BY18 BY19 CC16 BU16 CC14 BR22 BU20 CD20 BT14 BP12 CB24 CC24 J5 U24 BD7 AR4 AU4 AW4 BA6 BC4 BE4 BE8 BA4 BD4 BG4 CJ2 CJ3 AM5 CM4 AC5 AG5 CR6

1

A A

Security Classification

2019/06/20 2020/06/30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2019/06/20 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Document Number Re v

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

CPU(11/12)GND

LA-G716P

16 101Thursday, June 20, 2019

1

1.0

Only for Dell

5

4

3

2

1

Ref 575418

1 2

RC137 1K_0402_1%

D D

Reset sequence af t er PC U PLL i s l ocked

1 : (DEFAULT) Normal Operat i on; No St all

CFG0

0 : Stall

1 2

RC138 1K_0402_1%

PCI Express Stat i c Lane Revers al For All PE G Ports

1 : (DEFAULT) Normal Operat i on

CFG2

0 : Lane Reversal

1 2

C C

RC140

@

CFG0

CFG2

CFG4

1K_0402_1%

TPC11

CFG3[80]

TPC12

TPC13 TPC14 TPC15 TPC16 TPC17 TPC18 TPC19 TPC20

TPC21 TPC22 TPC23 TPC24

RC139 49.9_0402_1%

XDP_ITP_PMODE[80]

12

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCOMP

Display Port Presence Strap

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG4

1 : Disabled; No Physical Display Port at t ached t o E mbedded Di spl ay Port

1 2

RC141 1K_0402_1%

1 2

RC142 1K_0402_1%

B B

PCI Express Bifurcat i on

— 00 = 1 x 8, 2 x4 PCI Expr ess*

CFG[6:5]

— 01 = r es erv ed

— 10 = 2 x8 PCI Expr ess * — 11 = 1 x16 PCI Expr ess *

1 2

RC143 1K_0402_1%

CFG6

@

CFG5

@

CFG7

@

RC171

0_0201_5%

12

PEG Training

1 : (default) PEG Train immediately following RESET# de-assert i on.

CFG7

0 : PEG Wait for BIOS for training.

UC1Q

T4

CFG_0

R4

CFG_1

T3

CFG_2

R3

CFG_3

J4

CFG_4

M4

CFG_5

J3

CFG_6

M3

CFG_7

R2

CFG_8

N2

CFG_9

R1

CFG_10

N1

CFG_11

J2

CFG_12

L2

CFG_13

J1

CFG_14

L1

CFG_15

L3

CFG_16

N3

CFG_18

L4

CFG_17

N4

CFG_19

AB5

CFG_RCOMP

W4

ITP_PMODE

CG2

RSVD25

CG1

RSVD24

H4

RSVD34

H3

RSVD33

BV24

RSVD22

BV25

RSVD23

G3

RSVD66

G4

RSVD67

BK36

RSVD17

BK35

RSVD16

W3

RSVD35

AM4

RSVD7

AM3

RSVD6

A35

RSVD1

D34

RSVD30

G2

RSVD32

G1

RSVD31

WHL-U42_BGA1528

RESERVED SIGNALS

20 of 20

RSVD_TP5 RSVD_TP4

IST_TRIG

RSVD_TP3

RSVD15 RSVD14

TP_1 TP_2

RSVD21 RSVD20

RSVD18 RSVD19

RSVD29

RSVD26 RSVD27

VSS_434

RSVD12 RSVD13

RSVD8 RSVD9

RSVD11 RSVD10

RSVD72 RSVD73

RSVD74 RSVD75

TP_4 TP_3

RSVD68

RSVD_TP1 RSVD_TP2

RSVD28

RSVD36 RSVD37

SKTOCC#

F37 F34

IST_TRIG

CP36 CN36

BJ36 BJ34

BK34 BR18

BT9 BT8

BP8 BP9

CR4

CP3 CR3

BP36

AT3 AU3

AN1 AN2

AN4 AN3

AL2 AL1

AL4 AL3

BP34 BP35

C34

RC172 0_0201_5%

A34 B35

CR35

AH26 AJ27

E1

SKTOCC#

RC173 0_0201_5%

TP32

1 2

@

TP34

1 2

@

A A

Security Classification

2019/06/20 2020/06/30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2019/06/20 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

CPU(12/12)RSVD

Document Number Re v

CPU(12/12)RSVD

LA-G716P

1

17 101Thursday, June 20, 2019

1.0

Only for Dell

5

4

3

2

1

Main Function:

D D

C C

Reserve

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2019/06/20 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

B

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

RSVD

Document Number Re v

RSVD

LA-G716P

18 101Thursday, June 20, 2019

1

1.0

Only for Dell

5

4

3

2

1

Main Function:

D D

C C

Reserve

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2019/06/20 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

B

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

(RSVD)

Document Number Re v

(RSVD)

LA-G716P

19 101Thursday, June 20, 2019

1

1.0

Only for Dell

5

4

3

2

1

Main Function:

D D

C C

Reserve

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2019/06/20 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

(RSVD)

Document Number Re v

LA-G716P

20 101Thursday, June 20, 2019

1

1.0

Only for Dell

5

4

3

2

1

Main Function:

D D

C C

Reserve

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2019/06/20 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

(RSVD)

Document Number Re v

LA-G716P

21 101Thursday, June 20, 2019

1

1.0

Only for Dell

5

4

3

2

1

Main Function:

D D

C C

Reserve

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2019/06/20 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

(RSVD)

Document Number Re v

LA-G716P

22 101Thursday, June 20, 2019

1

1.0

Only for Dell

Main Func = DDR

5

Layout Note: Place near JDIMM1.257,259

+2.5V_MEM

D D

Layout Note: Place near JDIMM1

10U_0402_6.3V6M

1U_0201_6.3V6M

1

CD2

CD1

2

+1.2V_DDR

1U_0201_6.3V6M

1

CD8

2

C C

1U_0201_6.3V6M

1

2

1

CD10

CD9

2

+1.2V_DDR

10U_0402_6.3V6M

12

1

CD17

2

RD2 0_0201_5%

RD3 0_0201_5%

10U_0402_6.3V6M

1

CD18

2

1

CD16

2

B B

+3VS +3VS +3VS

@

+V_DDR_REFA_R

20mil

1 2

RD11 2_0402_1%

A A

1

CD27

0.022U_0402_25V7K

2

12

RD13

24.9_0402_1%

1U_0201_6.3V6M

1

CD11

CD12

2

10U_0402_6.3V6M

1

CD20

CD19

2

12

RD4

@

0_0201_5%

12

RD5

@

0_0201_5%

+1.2V_DDR

Layout Note: Place near JDIMM1.258

+0.6V_DDR_VTT

1

2

1U_0201_6.3V6M

1

CD13

2

10U_0402_6.3V6M

1

CD21

2

12

RD10

1K_0402_1%~D

12

RD12

1K_0402_1%~D

1U_0201_6.3V6M

CD3

+V_DDR_REFA

10U_0402_6.3V6M

1U_0201_6.3V6M

1

CD4

2

1U_0201_6.3V6M

1

CD14

CD15

2

10U_0402_6.3V6M

1

CD22

CD23

2

12

RD6

@

0_0201_5%

12

RD7

@

0_0201_5%

CD5

Only for Dell

5

1

@

+

CD24 330U_D2_2V_Y

2

4

Layout Note: Place near JDIMM1.255

DDR_DRAMRST#_RDIMM_CHA_SA0 DIMM_CHA_SA1 DIMM_CHA_SA2

4

DDR_A_D[0..63][7] DDR_A_MA[0..13][7] DDR_A_DQS#[0..7][7] DDR_A_DQS[0..7][7]

+3VS

0.1U_0402_16V7K~D

CD6

1

2

1 2

@

RD9 0_0201_5%

1

ESD@

CD26 S CER CAP 10P 50V J NPO 0201

2

2.2U_0402_6.3V6M

CD7

+1.2V_DDR

12

RD8 470_0402_1%

+3VS

3

DDR_A_CKE0[7]

DDR_A_BG1[7] DDR_A_BG0[7]

DDR_A_CLK0[7] DDR_A_CLK#0[7]

DDR_A_PAR[7] DDR_A_BA1[7]

DDR_A_CS#0[7]

DDR_A_WE#[7]

DDR_A_ODT0[7]

DDR_A_CS#1[7]

DDR_A_ODT1[7]

DDR_DRAMRST# [ 7]

3

2

+1.2V_DDR

DDR_A_D10

DDR_A_D13

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D15

DDR_A_D14

DDR_A_D3

DDR_A_D7

DDR_A_D5

DDR_A_D1

DDR_A_D16

DDR_A_D21

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D22

DDR_A_D19

DDR_A_D24

DDR_A_D28

DDR_A_D26

DDR_A_D30

DDR_A_CKE0

DDR_A_BG1 DDR_A_BG0

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA6

DDR_A_MA3 DDR_A_MA1

DDR_A_CLK0 DDR_A_CLK#0

DDR_A_PAR DDR_A_BA1

DDR_A_CS#0 DDR_A_WE#

DDR_A_ODT0 DDR_A_CS#1

DDR_A_ODT1

TP47

DDR_A_D36

DDR_A_D37

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D38

DDR_A_D39

DDR_A_D45

DDR_A_D41

+1.2V_DDR

PCH_SMBCLK[8,24,40,67] PCH_SMBDATA [8,24,40,67]

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

DDR_A_D44

DDR_A_D42

DDR_A_D48

DDR_A_D52

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D55

DDR_A_D50

DDR_A_D57

DDR_A_D60

DDR_A_D62

DDR_A_D63

PCH_SMBCLK

JDIMM1

CONN@

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5

11

DQS0_c

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI _n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25

53

DQS2_c

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DBI 3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45

95

DQS8_c

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/ A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n ,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI 5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI 7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LOTES_ADDR0206-P001A02~D

DEREN_40-42271-26001RHF

SP07001CY0L

2019/06/20 2020/06/30

DM0_n/DBI 0_n

DM2_n/DBI 2_n

DM8_n/DBI _n/NC

RESET_n

ALERT_n

EVENT_n/NF

CK1_t/NF

CK1_c/NF

RAS_n/A1 6

CAS_n/A1 5

C0/CS2_n /NC

DM4_n/DBI 4_n

DM6_n/DBI 6_n

Compal Secret Data

Deciphered Date

VSS2

VSS4

VSS6

VSS7

VSS9

VSS11

DQ12

VSS13

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

CKE1 VDD2

ACT_n

VDD4

VDD6

VDD8

VDD10

VDD12

A10/AP

VDD14

VDD16

VDD18

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

+1.2V_DDR

2

DDR_A_D8

4

DQ4

6

DDR_A_D12

8

DQ0

10 12 14

DDR_A_D9

16

DQ6

18

DDR_A_D11

20

DQ2

22

DDR_A_D6

24 26

DDR_A_D2

28

DQ8

30

DDR_A_DQS#0

32

DDR_A_DQS0

34 36

DDR_A_D0

38 40

DDR_A_D4

42 44

DDR_A_D17

46 48

DDR_A_D20

50 52 54 56

DDR_A_D18

58 60

DDR_A_D23

62 64

DDR_A_D29

66 68

DDR_A_D25

70 72

DDR_A_DQS#3

74

DDR_A_DQS3

76 78

DDR_A_D31

80 82

DDR_A_D27

84 86 88 90 92 94 96 98 100 102 104 106

DDR_DRAMRST#_R

108

DDR_A_CKE1

110 112 114

DDR_A_ALERT#

116 118

DDR_A_MA11

120

A11

A7

A5 A4

A2

A0

BA0

A13

SA2

SDA SA0

VTT

SA1

2

DDR_A_MA7

122 124

DDR_A_MA5

126

DDR_A_MA4

128 130

DDR_A_MA2

132 134 136

DDR_A_CLK1

138

DDR_A_CLK#1

140 142

DDR_A_MA0

144

DDR_A_MA10

146 148

DDR_A_BA0

150

DDR_A_RAS#

152 154

DDR_A_CAS#

156

DDR_A_MA13

158 160 162 164

DIMM_CHA_SA2

166 168

DDR_A_D33

170 172

DDR_A_D32

174 176 178 180

DDR_A_D34

182 184

DDR_A_D35

186 188

DDR_A_D43

190 192

DDR_A_D40

194 196

DDR_A_DQS#5

198

DDR_A_DQS5

200 202

DDR_A_D47

204 206

DDR_A_D46

208 210

DDR_A_D53

212 214

DDR_A_D49

216 218 220 222

DDR_A_D54

224 226

DDR_A_D51

228 230

DDR_A_D56

232 234

DDR_A_D61

236 238

DDR_A_DQS#7

240

DDR_A_DQS7

242 244

DDR_A_D59

246 248

DDR_A_D58

250 252

PCH_SMBDATA

254

DIMM_CHA_SA0

256 258

DIMM_CHA_SA1

260 262

DDR_DRAMRST#_R [24] DDR_A_CKE1 [7]

DDR_A_ACT# [7] DDR_A_ALERT# [7]

12

RD1

240_0402_1%

TP46

+1.2V_DDR

DDR_A_CLK1 [7] DDR_A_CLK#1 [7]

DDR_A_BA0 [7] DDR_A_RAS# [7]

DDR_A_CAS# [7]

+V_DDR_REFA

0.1U_0402_16V7K~D

CD25

1

2

+1.2V_DDR

Compal Electronics, Inc.

Title

DDR4 DIMMA_RVS

Size Document Number Re v

LA-G716P

Date: Sheet o f

1

All VREF traces should have 10 mil trace width

+0.6V_DDR_VTT+2.5V_MEM

1

1.0

23 101Thursday, June 20, 2019

1.0

5

4

3

2

1

Main Func = DDR

DDR_B_D[0..63][7] DDR_B_MA[0..13][7]

Layout Note: Place near JDIMM2.257,259

+2.5V_MEM

D D

Layout Note: Place near JDIMM2

10U_0402_6.3V6M

1U_0201_6.3V6M

1

CD29

CD28

2

Layout Note: Place near JDIMM2.258

+0.6V_DDR_VTT

1U_0201_6.3V6M

1

CD30

2

10U_0402_6.3V6M

1

CD31

2

CD32

DDR_B_DQS#[0..7][7] DDR_B_DQS[0..7][7]

Layout Note: Place near JDIMM2.255

+3VS

2.2U_0402_6.3V6M

0.1U_0402_16V7K~D

CD34

CD33

1

2

+1.2V_DDR

1U_0201_6.3V6M

1

CD35

2

C C

+1.2V_DDR

10U_0402_6.3V6M

1

CD43

2

B B

DIMM_CHB_SA0 DIMM_CHB_SA1 DIMM_CHB_SA2

1U_0201_6.3V6M

1

CD36

CD37

2

10U_0402_6.3V6M

1

CD44

CD45

2

+3VS +3VS +3VS

12

RD15

@

0_0201_5%

12

RD16

@

0_0201_5%

1U_0201_6.3V6M

1

CD38

2

10U_0402_6.3V6M

1

CD46

2

1U_0201_6.3V6M

1

CD39

2

10U_0402_6.3V6M

1

CD47

2

12

RD17

@

0_0201_5%

12

RD18

@

0_0201_5%

1U_0201_6.3V6M

1

CD40

CD41

2

10U_0402_6.3V6M

1

2

1

CD48

CD49

2

1U_0201_6.3V6M

CD42

DDR_B_CKE0[7]

DDR_B_BG1[7] DDR_B_BG0[7]

10U_0402_6.3V6M

CD50

12

RD19

@

0_0201_5%

12

RD20

@

0_0201_5%

DDR_B_CLK0[7] DDR_B_CLK#0[7]

DDR_B_PAR[7] DDR_B_BA1[7]

DDR_B_CS#0[7]

DDR_B_WE#[7]

DDR_B_ODT0[7]

DDR_B_CS#1[7]

DDR_B_ODT1[7]

DDR_B_CLK0 DDR_B_CLK#0

DDR_B_PAR DDR_B_BA1

DDR_B_CS#0 DDR_B_WE#

DDR_B_ODT0 DDR_B_CS#1

DDR_B_ODT1

TP49

+1.2V_DDR

+V_DDR_REFB_R

A A

20mil

1 2

RD22 2_0402_1%

1

CD52

0.022U_0402_25V7K

2

12

RD24

24.9_0402_1%

+1.2V_DDR

12

RD21

1K_0402_1%~D

+V_DDR_REFB

RD23

1K_0402_1%~D

+2.5V_MEM

+3VS

PCH_SMBCLK[8,23,40,67]

Only for Dell

5

4

3

+1.2V_DDR

DDR_B_D12

DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D15

DDR_B_D10

DDR_B_D7

DDR_B_D2

DDR_B_D1

DDR_B_D6

DDR_B_D16

DDR_B_D21

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D23

DDR_B_D22

DDR_B_D29

DDR_B_D24

DDR_B_D26

DDR_B_D30

DDR_B_CKE0

DDR_B_BG1 DDR_B_BG0

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA6

DDR_B_MA3 DDR_B_MA1

DDR_B_D38

DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34

DDR_B_D35

DDR_B_D40

DDR_B_D44

DDR_B_D47

DDR_B_D46

DDR_B_D49

DDR_B_D52

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50

DDR_B_D51

DDR_B_D56

DDR_B_D61

DDR_B_D59

PCH_SMBCLK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

JDIMM2

CONN@

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5

11

DQS0_c

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI _n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25

53

DQS2_c

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DBI 3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45

95

DQS8_c

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/ A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n ,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI 5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI 7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LOTES_ADDR0205-P001A02~D

DEREN_40-42261-26001RHF

SP07001HW0L

2019/06/20 2020/06/30

DM0_n/DBI 0_n

DM2_n/DBI 2_n

DM8_n/DBI _n/NC

EVENT_n/NF

RAS_n/A1 6

CAS_n/A1 5

C0/CS2_n /NC

DM4_n/DBI 4_n

DM6_n/DBI 6_n

Compal Secret Data

VSS2

DQ4

VSS4

DQ0

VSS6

VSS7

DQ6

VSS9

DQ2

VSS11

DQ12

VSS13

DQ8

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

A11

A7

VDD6

A5 A4

VDD8

A2

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A0

A10/AP

VDD14

BA0

VDD16

A13

VDD18

VREFCA

SA2

VSS54

DQ36

VSS56

DQ32

VSS58

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

SDA SA0 VTT SA1

GND2

Deciphered Date

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262

2

+1.2V_DDR

DDR_B_D13

DDR_B_D8

DDR_B_D14

DDR_B_D11

DDR_B_D3

DDR_B_D0

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D5

DDR_B_D4

DDR_B_D17

DDR_B_D20

DDR_B_D19

DDR_B_D18

DDR_B_D25

DDR_B_D28

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D31

DDR_B_D27

DDR_DRAMRST#_R DDR_B_CKE1

DDR_B_ALERT#

DDR_B_MA11 DDR_B_MA7

DDR_B_MA5 DDR_B_MA4

DDR_B_MA2

DDR_B_CLK1 DDR_B_CLK#1

DDR_B_MA0 DDR_B_MA10

DDR_B_BA0 DDR_B_RAS#

DDR_B_CAS# DDR_B_MA13

DIMM_CHB_SA2

DDR_B_D32

DDR_B_D39

DDR_B_D37

DDR_B_D36

DDR_B_D41

DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D42

DDR_B_D43

DDR_B_D48

DDR_B_D53

DDR_B_D55

DDR_B_D54

DDR_B_D57

DDR_B_D60

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D63

DDR_B_D62DDR_B_D58

PCH_SMBDATA

DIMM_CHB_SA0

DIMM_CHB_SA1

RD14

240_0402_1%

+1.2V_DDR

DDR_DRAMRST#_R [23] DDR_B_CKE1 [7]

DDR_B_ACT# [7] DDR_B_ALERT# [7]

12

+1.2V_DDR

DDR_B_CLK1 [7] DDR_B_CLK#1 [7]

DDR_B_BA0 [7] DDR_B_RAS# [7]

DDR_B_CAS# [7]

TP48

+V_DDR_REFB

0.1U_0402_16V7K~D

CD51

1

2

PCH_SMBDATA [8,23,40,67]

+0.6V_DDR_VTT

Compal Electronics, Inc.

Title

DDR4 DIMMB_STD

Size Document Number Re v

LA-G716P

Date: Sheet o f

All VREF traces should have 10 mil trace width

1

1.0

24 101Thursday, June 20, 2019

1.0

5

4

3

2

1

Main Function:

D D

C C

Reserve

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2019/06/20 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

(RSVD)

Document Number Re v

LA-G716P

25 101Thursday, June 20, 2019

1

1.0

Only for Dell

5

4

3

2

1

Main Function:

D D

C C

Reserve

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2019/06/20 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

(RSVD)

Document Number Re v

LA-G716P

26 101Thursday, June 20, 2019

1

1.0

Only for Dell

1

Main Func = GPU

A A

PEG_CTX_GRX_P5 PEG_CTX_GRX_N5

PEG_CTX_GRX_P6 PEG_CTX_GRX_N6

PEG_CTX_GRX_P7 PEG_CTX_GRX_N7

PEG_CTX_GRX_P8 PEG_CTX_GRX_N8

DIS@ DIS@

12

CV9 0.22U_0201_6.3V6M

12

CV10 0.22U_0201_6.3V6M

12

CV11 0.22U_0201_6.3V6M

12

CV12 0.22U_0201_6.3V6M

12

CV13 0.22U_0201_6.3V6M

12

CV14 0.22U_0201_6.3V6M

12

CV15 0.22U_0201_6.3V6M

12

CV16 0.22U_0201_6.3V6M

PEG_CTX_C_GRX_P5 PEG_CTX_C_GRX_N5

PEG_CTX_C_GRX_P6 PEG_CTX_C_GRX_N6

PEG_CTX_C_GRX_P7 PEG_CTX_C_GRX_N7

PEG_CTX_C_GRX_P8 PEG_CTX_C_GRX_N8

GPU R1/R3

UV1

B B

S IC 216-0889004 A0 R17M-M2-50 FCBGA 0FD

UV1

S IC 216-0889004 A0 R17M-M2-50 WESTON XT BGA 631P GPU A31 !

UV1

S IC 216-0890010 A0 R17M-M1-30 631P R610

UV1

S IC 216-0890010 A0 R17M-M1-30 R610 A31!

C C

SA0000B1W0L

M2_50@

SA0000B1W1L

M2_50_R3@

R610 R1

SA000087T5L

M1_30_R1@

R610 R3

SA000087T6L

M1_30_R3@

1 2

DIS@

CLK_PEG_P0 CLK_PEG_N0

CLK_PEG_P0[10] CLK_PEG_N0[10]

RV2 1K_0402_1%

PEG_CRX_GTX_N[5..8][12]

PEG_CRX_GTX_P[5..8][12]

PEG_CTX_GRX_N[5..8][12]

PEG_CTX_GRX_P[5..8][12]

PLT_RST_VGA#

2

AF30

AE31

AE29 AD28

AD30 AC31

AC29 AB28

AB30 AA31

AA29

Y28

Y30

W31

W29

V28

V30 U31

U29 T28

T30 R31

R29 P28

P30 N31

N29 M28

M30 L31

L29 K30

AK30 AK32

N10

AL27

PEG_CRX_GTX_N[5..8]

PEG_CRX_GTX_P[5..8]

PEG_CTX_GRX_N[5..8]

PEG_CTX_GRX_P[5..8]

@

UV1A

PCIE_RX0P PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P PCIE_RX6N

PCIE_RX7P PCIE_RX7N

NC#V30 NC#U31

NC#U29 NC#T28

NC#T30 NC#R31

NC#R29 NC#P28

NC#P30 NC#N31

NC#N29 NC#M28

NC#M30 NC#L31

NC#L29 NC#K30

CLOCK

PCIE_REFCLKP PCIE_REFCLKN

TEST_PG

PERSTB

2160856030-A0_FCBGA631

PCI EXPRESS INTERFACE

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

NC#W24 NC#W23

CALIBRATIO N

PCIE_CALR_TX

PCIE_CALR_RX

NC#V27 NC#U26

NC#U24 NC#U23

NC#T26 NC#T27

NC#T24 NC#T23

NC#P27 NC#P26

NC#P24 NC#P23

NC#M27

NC#N26

PEG_CRX_C_GTX_P5

AH30

PEG_CRX_C_GTX_N5

AG31

PEG_CRX_C_GTX_P6

AG29

PEG_CRX_C_GTX_N6

AF28

PEG_CRX_C_GTX_P7

AF27

PEG_CRX_C_GTX_N7

AF26

PEG_CRX_C_GTX_P8

AD27

PEG_CRX_C_GTX_N8

AD26

AC25 AB25

Y23 Y24

AB27 AB26

Y27 Y26

W24 W23

V27 U26

U24 U23

T26 T27

T24 T23

P27 P26

P24 P23

M27 N26

Y22

AA22

1 2

RV1 1.69K_0402_1%

DIS@

1 2

RV3 1K_0402_1%

DIS@

3

4

5

No Use GPU Display Port outpud

@

DIS@ DIS@

12

CV1 0.22U_0201_6.3V6M

12

CV2 0.22U_0201_6.3V6M

12

CV3 0.22U_0201_6.3V6M

12

CV4 0.22U_0201_6.3V6M

12

CV5 0.22U_0201_6.3V6M

12

CV6 0.22U_0201_6.3V6M

12

CV7 0.22U_0201_6.3V6M

12

CV8 0.22U_0201_6.3V6M

+0.95VSDGPU

PEG_CRX_GTX_P5 PEG_CRX_GTX_N5

PEG_CRX_GTX_P6 PEG_CRX_GTX_N6

PEG_CRX_GTX_P7 PEG_CRX_GTX_N7

PEG_CRX_GTX_P8 PEG_CRX_GTX_N8

UV1F

TXCAP_DPA3P TXCAM_DPA3N

TX0P_DPA2P TX0M_DPA2N

TX1P_DPA1P TX1M_DPA1N

TX2P_DPA0P TX2M_DPA0N

NC_TXOUT_L3P NC_TXOUT_L3N

TMDP

TXCBP_DPB3P TXCBM_DPB3N

TX3P_DPB2P TX3M_DPB2N

TX4P_DPB1P TX4M_DPB1N

TX5P_DPB0P TX5M_DPB0N

NC_TXOUT_U3P NC_TXOUT_U3N

216-0842024-A11-MAR_FCBGA631

?

VARY_BL

DIGON

AB11 AB12

AL15 AK14

AH16 AJ15

AL17 AK16

AH18 AJ17

AL19 AK18

AH20 AJ19

AL21 AK20

AH22 AJ21

AL23 AK22

AK24 AJ23

+VGA_CORE_TOPAZ

+3VGS

UV2 change CPN & Description only

PLT_RST#

PLTRST#[10,51,52,58,66,68]

DGPU_HOLD_RST#[11]

DGPU_HOLD_ RST#(GPP_D10 )

D D

Only for Dell

1

Jason 2019-04-26

MC74VHC1G08EDFT2G_SC70

UV2

DIS@

5

1

P

IN1

4

O

2

IN2

G

12

3

RV4 100K_0402_5%

DIS@

2

PLT_RST_VGA# [58]

DGPU_PWROK[9,92,94]

@

1 2

CV32 0.1U_0402_10V6K

PLT_RST_VGA#

UV3 change CPN & Description only

Jason 2019-04-26

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+3VGS

UV3 MC74VHC1G08EDFT2G_SC70

5

1

P

IN1

O

2

IN2

G

3

@

4

1 2

@

RV166 8.2K_0402_5%

Compal Secret Data

2019/06/20 2020/06/30

Compal Secret Data

VGA_POK [92]

12

RV165 10K_0402_1%

@

Deciphered Date

4

Compal Electronics, Inc.

Title

Size Document Number Re v

Date: Sheet o f

Compal Electronics, Inc.

MESO_(1/5)_PCIE/DP

LA-G716P

5

27 101Thursday, June 20, 2019

1.0

Main Func = GPU

A A

+VGA_CORE +VGA_CORE_TOPAZ

B B

1

SML1_SMBDATA[8,58,66]

SML1_SMBCLK[8,58,66]

RV24 0_0603_5%

TOPAZ@

1 2

L2N7002DW1T1G_SC88-6

QV1B

DIS@

5

G

3 4

D

+3VGS

4.7K_0402_5%

S

2

G

QV1A

DIS@

6 1

S

D

L2N7002DW1T1G_SC88-6

12

RV5

RV6

4.7K_0402_5%

DIS@

Reduce 3.3V TO 1.8V level shif t f or EX O.

JTAG

+3VGS

RV17 5.1K_0402 _1%@

1 2

RV18 1K_0402 _1%

DIS@1 2

+3VGS

@ 1 8 2 7 3 6 4 5

RP34 10K_0804_8P4R_5%

@

C C

D D

RV19 10K_040 2_5%

CV18

8.2P 50V D NPO 0402

DIS@

1

2

JTAG_TDO_GPU JTAG_TDI_GPU JTAG_TMS_GPU JTAG_TRSTB

JTAG_TCK

12

RV20

DIS@

1M_0402_5%

YV1

DIS@

27MHZ_10PF_7V2700005 0

3

GND

4

GND

TESTEN

2

XTALINXTALOUT

1

10P change to 8.2P 7/4

1

CV17

8.2P 50V D NPO 0402

DIS@

2

+3VGS

Disable MLPS

RV22 10K_040 2_5%@

1 2

RV21 10K_040 2_5%EXO@

1 2

Enable MLPS

2

TP56

VGA_SMB_DA3

VGA_SMB_CK3

+1.8VGS

RV82 4.7K_0402 _5%TOPAZ@

FB_VDDCI

TP73

TP74

RV80 4.7K_0402_5%DIS@

+3VGS

GPU_PWR_LEVEL[58]

SVI2_SVD

1 2

RV44 0_0402_5%EXO@

SVI2_SVC

1 2

RV45 0_0402_5%EXO@

CLKREQ_PEG#0[10]

GPIO28

+1.8VGS

RV81 4.7K_0402 _5%TOPAZ@

PLL_Analog_in

12

RV151 10K_0 402_5%

RV152 10K_0 402_5%

1 2

RV153 0_0402_ 5%

LV2

DIS@

1 2

BLM15BD121SN1D_0402

DIS@

CV20 1U_0201_6.3V6M

12

TP57 TP58 TP59 TP60 TP61 TP62 TP63 TP64 TP65 TP66 TP67 TP68 TP69 TP70 TP71 TP72

12

TP75 TP76

+VGA_CORE_TOPAZ

TP77

VGA_SMB_DA3 VGA_SMB_CK3

+VGA_CORE_TOPAZ

GPU_VID3

GPIO19_CTF

TOPAZ@12

GPU_VID1

@1 2

CLKREQ_PEG#0_R

@

JTAG_TRSTB JTAG_TDI_GPU JTAG_TCK JTAG_TMS_GPU JTAG_TDO_GPU

TESTEN

+VGA_CORE_TOPAZ

TP78

PX_EN

TP79

XTALIN XTALOUT

RV29 10K_040 2_5%

DIS@

1 2

RV59 10K_040 2_5%

DIS@1 2

GPIO28

13mA

+TSVDD

AE9 Y11 AE8 AD9

AC10

AD7 AC8 AC7 AB9 AB8 AB7 AB4 AB2

AC6 AC5

AA5 AA6

BP_0

BP_1

AA1

U10 T10

P10

W10

AK10 AM10

AF24

AB13

AD10

AJ9 AL9

AC14 AB16

AC16

AM28 AK28

AC22 AB22

AD17 AC17

3

@

UV1B

N9

DBG_DATA16

L9

DBG_DATA15 DBG_DATA14 DBG_DATA13 DBG_DATA12 DBG_DATA11 DBG_DATA10 DBG_DATA9

DVO

DBG_DATA8 DBG_DATA7 DBG_DATA6 DBG_DATA5 DBG_DATA4 DBG_DATA3 DBG_DATA2

Y8

DBG_DATA1

Y7

DBG_DATA0

W6

NC#W6

V6

NC#V6

NC#AC5 NC#AC6

NC#AA5 NC#AA6

U1

NC#U1

W1

NC#W1

U3

NC#U3

Y6

NC#Y6 NC#AA1

I2C

R1

SCL

R3

SDA

GENERAL PURPOSE I/O

U6

GPIO_0 GPIO_1 GPIO_2

U8

SMBDATA

U7

SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6

T7

GPIO_7_BLON GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

GPIO_11

N5

GPIO_12

N3

GPIO_13

Y9

GPIO_14_HPD2

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16

R6

GPIO_17_THERMAL_INT GPIO_18

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21

N8

GPIO_22_ROMCSB GPIO_29 GPIO_30

N7

CLKREQB

L6

JTAG_TRSTB

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

K7

TESTEN NC#AF24

GENERICA

W8

GENERICB

W9

GENERICC

W7

GENERICD GENERICE NC#AJ9 NC#AL9

HPD1 PX_EN

DBG_VREFG

PLL/CLOCK

XTALIN XTALOUT

XO_IN XO_IN2

SEYMOUR/FutureASIC

T4

DPLUS

THERMAL

T2

DMINUS

R5

GPIO28_FDO TSVDD TSVSS

216-0842024-A11-MAR_FCBGA631

TOPAZ Thermal Address-->0x82

U?

DPA

DPB

DPC

AVSSN#AK26

AVSSN#AJ25

AVSSN#AG25

DAC1

FutureASIC/SEYMOUR/PARK

GENLK_VSYNC

SWAPLOCKA SWAPLOCKB

DDC/AUX

DDCVGACLK

DDCVGADATA

?

NC#AF2 NC#AF4

NC#AG3 NC#AG5

NC#AH3 NC#AH1

NC#AK3 NC#AK1

NC#AK5 NC#AM3

NC#AK6 NC#AM5

NC#AJ7

NC#AH6

NC#AK8

NC#AL7

NC#V4 NC#U5

NC#W3 NC#V2

NC#Y4 NC#W5

NC#AA3

NC#Y2

NC#J8

HSYNC VSYNC

RSET

AVDD

AVSSQ

VDD1DI

VSS1DI

CEC_1

RSVD#AK12 RSVD#AL11

RSVD#AJ11

GENLK_CLK

DDC1CLK

DDC1DATA

AUX1P AUX1N

DDC2CLK

DDC2DATA

AUX2P AUX2N

NC#AD20 NC#AC20

NC#AE16 NC#AD16

4

Resistor Divider Lookup Lable

0402 1% resistors are equired

R_pd (ohm)R_pu (ohm)

AF2 AF4

AG3 AG5

AH3 AH1

AK3 AK1

AK5 AM3

AK6 AM5

AJ7 AH6

AK8 AL7

V4 U5

W3 V2

Y4 W5

PLL_Analog_out

AA3 Y2

J8

AM26

R

AK26

AL25

G

AJ25

AH24

B

AG25

AH26 AJ27

WAKEB

AD22

AG24 AE22

AE23 AD23

AM12

AK12

RV155 0_040 2_5%TO PAZ@

AL11

RV156 0_040 2_5%TO PAZ@

AJ11

RV157 0_040 2_5%TO PAZ@

AL13 AJ13

AG13 AH12

AC19

PS_0

AD19

PS_1

AE17

PS_2

AE20

PS_3

AE19

TS_A

AE6 AE5

AD2 AD4

AC11 AC13

AD13 AD11

FB_GND

AD20

FB_VDDC

AC20

AE16 AD16

AC1 AC3

PS_0

PS_1

PS_2

PS_3

1 2 1 2 1 2

12

RV83

16.2K_0402_1%

TOPAZ@

+3VGS

12

RV162

4.7K_0402_5%

@

12

RV163

4.7K_0402_5%

DIS@

RV158 0_040 2_5%TO PAZ@ RV159 0_040 2_5%TO PAZ@

VCCSENSE_VGA VSSSENSE_VGA

NC

8.45k

4.53k

6.98k

4.53k

3.24k

3.4k

4.75k

Capacitor Divider Lookup Lable

Cap (nF) Bitd [5:4]

680nF

82nF

10nF 10

NC

SVI2_SVD SVI2_SVT SVI2_SVC

+VGA_CORE_TOPAZ

1 2 1 2

RV42 10_040 2_5% RV43 10_040 2_5%

4.75k

2k

4.99k

5.62k

10k

NC

00

01

11

EXO@

1 2

EXO@

1 2

Bitd [3:1]

000

001

010

011

100

101

110

111

SVI2_SVD [92] SVI2_SVT [92] SVI2_SVC [92]

VSSSENSE_VGA VCCSENSE_VGA

+VGA_CORE

PS_0[3:1]=001

PS_0[5:4]=11

PS_1[3:1]=001

PS_1[5:4]=11

PS_2[3:1]=000

PS_2[5:4]=11

PS_3[3:1]=000

PS_3[5:4]=11

VSSSENSE_VGA [92] VCCSENSE_VGA [92]

PS_0

CV28

PS_1

CV29

PS_2

CV30

@

PS_3

CV31

+1.8VGS

12

1

@

2

0.68U_0402_10V

+1.8VGS

12

1

@

2

0.68U_0402_10V

+1.8VGS

12

1

2

0.082U_0402_16V

+1.8VGS

12

1

@

2

0.68U_0402_10V

TOPAZ@

1 2

RV25 0_0402_5%

DIS@

RV84

10K_0402_5%

SVI2_SVD SVI2_SVC

@

RV89

10K_0402_5%

DIS@

RV8

8.45K_0402_1%

DIS@

RV9 2K_0402_1%

DIS@

RV11

8.45K_0402_1%

DIS@

RV12 2K_0402_1%

@

RV13

8.45K_0402_1%

DIS@

RV14

4.75K_0402_1%

@

RV15

8.45K_0402_1%

@

RV16

4.75K_0402_1%

SD034475180

1 2

Strap Name :

PS_0[1] ROM_CONFIG[0]

PS_0[2] ROM_CONFIG[1]

PS_0[3] ROM_CONFIG[2]

PS_0[4] N/A

PS_0[5] AUD_PO RT_CONN_PINSTRAP[0]

Strap Name :

PS_1[1] STRAP_BIF_ GEN3_EN_A

PS_1[2] TRAP_BIF_CLK_PM_EN

PS_1[3] N/A

PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING

PS_1[5] STRAP_TX_DEE MPH_EN

Strap Name :

PS_2[1] N/A

PS_2[2] N/A

PS_2[3] STRAP_BIOS_ROM_EN

PS_2[4] STRAP_BIF_VGA_DIS

PS_2[5] N/A

Strap Name :

PS_3[1] BOARD_CONFIG[0] (Memory ID )

PS_3[2] BOARD_CONFIG[1] (Memory ID )

PS_3[3] BOARD_CONFIG[2] (Memory ID )

PS_3[4] AUD_PO RT_CONN_PINSTRAP[1]

PS_3[5] AUD_PO RT_CONN_PINSTRAP[2]

+3VGS+1.8VGS

EXO@

1 2

RV26 0_0402_5%

@

RV87 10K_0402_5%

DIS@

RV88 10K_0402_5%

5

M2-50 use +1.8v

Boot-VID Code

SVC

0 0 1 1

Voltage

SVD

Selected (V)

0 1 1.0 0 1 0.8

1.1

0.9

VRAM Type Need reference

X76 Schemat i c

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

Only for Dell

2

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/20 2020/06/30

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

MESO_(2/5)_MSIC

Size

Document Number Re v

Size

Document Number Re v

Size

Document Number Re v

Date: Sheet o f

LA-G716P

5

28 101Thursday, June 20, 2019

1.0

Main Func = GPU

370mA (HDMI)

+1.8VGS

188mA (Display Port)

1 2

RV27 0_0603_5%@

Crystal Pad Analog Supply (40mA)

A A

+0.95VSDGPU

1 2

RV30 0_0603_5%@

B B

C C

D D

1

No Use GPU Display Port output

AG15 AG16

AF16 AG17 AG18 AG19

AF14

AG20 AG21

AF22 AG22 AD14

AG14 AH14 AM14 AM16 AM18

AF23 AG23 AM20 AM22 AM24

AF19

AF20 AE14

AF17

U?

GND

?

@

UV1G

DP POWER

DP_VDDR#AG15 DP_VDDR#AG16 DP_VDDR#AF16 DP_VDDR#AG17 DP_VDDR#AG18 DP_VDDR#AG19 DP_VDDR#AF14

DP_VDDC#AG20 DP_VDDC#AG21 DP_VDDC#AF22 DP_VDDC#AG22 DP_VDDC#AD14

DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR

DPAB_CALR

216-0842024-A11-MAR_FCBGA631

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

VSS_MECH VSS_MECH VSS_MECH

U?

NC/DP POWER

AE11

NC#AE11

AF11

NC#AF11

AE13

NC#AE13

AF13

NC#AF13

NC#AG8

NC#AG10

NC#AF6 NC#AF7 NC#AF8 NC#AF9

NC#AE1 NC#AE3 NC#AG1 NC#AG6 NC#AH5

NC#AF10

NC#AG9 NC#AH8 NC#AM6 NC#AM8 NC#AG7

NC#AG11

NC#AE10

?

VDDC

AG8 AG10

VDDCI

AF6 AF7 AF8 AF9

AE1 AE3 AG1 AG6 AH5 AF10 AG9 AH8

PCIE_VDDC

AM6 AM8 AG7 AG11

BIF_VDDC

SPLL_VDDC

AE10

+1.35V_MEM_GFX

A3 A30 AA13 AA16 AB10 AB15 AB6 AC9 AD6 AD8 AE7 AG12 AH10 AH28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B6 B8 C1 C32 E28 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6

A32 AM1 AM32

VDDR1

VDDR3

PCIE_PVDD

MPLL_PVDD

SPLL_PVDD

VDDR4

VDD_CT

+TSVDD 1 00

+DP_VDDR

1

CV261U_0 201_6.3V6M

CV2710 U_0402_6.3V6M

DIS@

2

280mA

+DP_VDDC

1

CV340.1U_0201_6.3V6K

CV331U_0201 _6.3V6M

DIS@

2

@

UV1E

AA27

GND

AB24

GND

AB32

GND

AC24

GND

AC26

GND

AC27

GND

AD25

GND

AD32

GND

AE27

GND

AF32

GND

AG27

GND

AH32

GND

K28

GND

K32

GND

L27

GND

M32

GND

N25

GND

N27

GND

P25

GND

P32

GND

R27

GND

T25

GND

T32

GND

U25

GND

U27

GND

V32

GND

W25

GND

W26

GND

W27

GND

Y25

GND

Y32

GND

M6

GND

N13

GND

N16

GND

N18

GND

N21

GND

P6

GND

P9

GND

R12

GND

R15

GND

R17

GND

R20

GND

T13

GND

T16

GND

T18

GND

T21

GND

T6

GND

U15

GND

U17

GND

U20

GND

U9

GND

V13

GND

V16

GND

V18

GND

Y10

GND

Y15

GND

Y17

GND

Y20

GND

R11

GND

T11

GND

AA11

GND

M12

GND

N11

GND

V11

GND

216-0842024-A11-MAR_FCBGA631

2

2.2uF

10uF+VGA_CORE

1uF

6 16 0

2 3 2

10uF 1uF 0.1uF+0.95VSDGPU

1 6 0

1 0

2

11 1

0+DP_VDDC

10uF 0.1uF

1 5 1

0 1 0

10uF+1.8VGS 0.1uF1uF

(NC)

0 1 0

0.1uF

11

1 01

00 0

11 0

3

+1.35V_MEM_GFX

1

CV4010 U_0402_6.3V6M

DIS@

2

+1.8VGS

1 2

RV7 0_0603_ 5%@

1

CV641U_0201 _6.3V6M

DIS@

0.01uF2.2uF

2

1

CV452.2U_0402_6.3V6M

CV432.2U_0402_6.3V6M

CV412.2U_0402_6.3V6M

CV442.2U_0402_6.3V6M

CV422.2U_0402_6.3V6M

DIS@

2

+3VGS

DIS@

2

1 2

RV10 0_0603_5%@

DIS@

2

1

2A

1

CV470.01 U_0402_16V7K

CV460.1U_0201_6.3V6K

DIS@

2

13mA

+VDD_CT

25mA

+VDDR3

1

CV651U_0201 _6.3V6M

DIS@

2

0.1uF1uF10uF+3VGS

+1.8VGS

LV6

DIS@

1 2

BLM15BD221SN1D_2P

012

1

CV8110U_04 02_6.3V6M

CV8210U_04 02_6.3V6M

CV831U_0201 _6.3V6M

DIS@

2

+1.8VGS

LV7

DIS@

1 2

BLM15BD121SN1D_04 02

1

CV8410 U_0402_6.3V6M

CV851U_0 201_6.3V6M

DIS@

+0.95VSDGPU +VGA_CORE

2

LV8

DIS@

1 2

BLM15BD121SN1D_04 02

90mA

+MPLL_PVDD

75mA

+SPLL_PVDD

100mA

+SPLL_VDDC

1

CV921U_0201 _6.3V6M

CV9110U_04 02_6.3V6M

CV930.1U_0201_6.3V6K

DIS@

2

H13 H16 H19 J10 J23 J24

K10 K23 K24

K9 L11 L12 L13 L20 L21 L22

AA20 AA21 AB20 AB21

AA17 AA18 AB17 AB18

V12 Y12 U12

H7

H8

+BIF_VDDC

J9

L8

J7

4

@

UV1D

MEM I/O

VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1

LEVEL TRANSL ATION

VDD_CT VDD_CT VDD_CT VDD_CT

I/O

VDDR3 VDDR3 VDDR3 VDDR3

VDDR4 VDDR4 VDDR4

PLL

MPLL_PVDD

SPLL_PVDD

SPLL_VDDC

SPLL_PVSS

216-0842024-A11-MAR_FCBGA631

1

CV6110U_04 02_6.3V6M

DIS@

2

U?

?

RV31 0_0 603_5%

1

CV631U_0201 _6.3V6M

CV621U_0201 _6.3V6M

DIS@

2

PCIE

CORE

ISOLATE D CORE I/O

@

PCIE_PVDD

PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC

POWER

BIF_VDDC BIF_VDDC

+0.95VSDGPU

12

NC#AB23 NC#AC23 NC#AD24 NC#AE24 NC#AE25 NC#AE26 NC#AF25 NC#AG26

VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC

VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI

5

+1.8VGS

100mA

AM30

AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26

L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22

AA15 N15 N17 R13 R16 R18 Y21 T12 T15 T17 T20 U13 U16 U18 V21 V15 V17 V20 Y13 Y16 Y18 AA12 M11 N12 U11

R21 U21

M13 M15 M16 M17 M18 M20 M21 N20

1A

800mA

+BIF_VDDC

1

CV4910U_04 02_6.3V6M

DIS@

2

+PCIE_VDDC

1

CV5410 U_0402_6.3V6M

DIS@

2

DIS@

1

CV8610U_04 02_6.3V6M

DIS@

2

1

CV501U_0201 _6.3V6M

DIS@

2

+0.95VSDGPU

@

12

RV23 0_060 3_5%

1

CV551U_0 201_6.3V6M

DIS@

2

1

CV6710U_04 02_6.3V6M

CV6810U_04 02_6.3V6M

DIS@

2

1

CV8710U_04 02_6.3V6M

DIS@

2

1

CV581U_0 201_6.3V6M

CV601U_0 201_6.3V6M

CV571U_0 201_6.3V6M

CV561U_0 201_6.3V6M

CV591U_0 201_6.3V6M

DIS@

2

+VGA_CORE

1

CV7110U_04 02_6.3V6M

CV6910U_04 02_6.3V6M

CV7010U_04 02_6.3V6M

DIS@

2

1

CV1002.2U_0402_6.3V6M

CV1012.2U_0402_6.3V6M

DIS@

2

1

CV901U_0201 _6.3V6M

CV881U_0201 _6.3V6M

CV891U_0201 _6.3V6M

DIS@

2

1

CV752.2U_0402_6.3V6M

CV732.2U_0402_6.3V6M

CV7210U_04 02_6.3V6M

CV742.2U_0402_6.3V6M

CV762.2U_0402_6.3V6M

CV772.2U_0402_6.3V6M

DIS@

2

1

CV1022.2U_0402_6.3V6M

CV1032.2U_0402_6.3V6M

CV1042.2U_0402_6.3V6M

CV1052.2U_0402_6.3V6M

DIS@

2

1

CV1200.1U_0201_6.3V6K

CV1210.1U_0201_6.3V6K

DIS@

2

CV782.2U_0402_6.3V6M

DIS@

2

1

CV1062.2U_0402_6.3V6M

CV1092.2U_0402_6.3V6M

CV1082.2U_0402_6.3V6M

CV1072.2U_0402_6.3V6M

DIS@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/20 2020/06/30

4

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

MESO_(4/5)_Power

Size Document Number Re v

Custom

Date: Sheet of

LA-G716P

5

29 101Thursday, June 20, 2019

1.0

Only for Dell

5

4

3

2

1

Power-Up/Down Sequence

D D

VDDR3(3.3V)

+3VGS

(DGPU_PWR_EN )

PCIE_VDDC(0.95V)

+0.95VSDGPU (DGPU_PWR_EN with RC delay)

1.8V_IO(1.8V)

+1.8VGS (DGPU_PWR_EN with RC delay)

VDDC/VDDCI(0.8~1. 15V)

+VGA_CORE (DGPU_PWR_EN )

VMEMIO(1.35V or 1.5V)

+1.35V _MEM_GFX (DGPU_PWROK with RC delay)

PWRGOOD

DGPU_PW ROK

C C

PERS Tb

PLT_RST_VGA#

REFCLK

CLK_PEG_VGA/CLK_ PEG_VGA#

DEVICE

1. All the ASIC supplies must reach their respective nominal voltages within 20 ms of the start o f the ramp-up sequence, though a sho rter ramp-up duration is preferred. The maximum slew rate on all rails is 50 mV/μ s.

2. It is recommended that the 3.3-V rail ramp up first.

3. It is recommended that the 0.95-V rail reach at least 90% of its no minal value no later than 2 ms from the start of VDDC ramping up.

4. The pow er rails that are shared with other c omponents on the system should be gated for the dGPU so that when the dGPU is powered down (for example AMD Powe rXpress? idle state), all the power rails are removed from the dGPU. The gate c ircuits must meet the slew rate requirement (such as ? 50 mV/μ s).

5. VDDC and VDD_CT sh ould not ramp u p simultaneously. For example, VDDC should reach 90% before VDD_CT starts to ramp up (or v ice versa).

6. For power down, reversing the ramp-up sequen ce is recommended.

< 20mS

>10uS

> 100mS > 100mS (SW)

> 100uS

Asserted Before PERSTb

Device in

Device Hardware Reset Device CFG Accessible

Reset

or Working

< 20mS

Device Powering down

No requirements

Device Po wered down

Samsung 2G

UV13

SA00009TA2L

S8_R1@

S IC D5 256M32 K4G80325FC-HC25 FBGA 170P

UV13

SA00009TA3L

S8_R3@

S IC D5 256M32 K4G80325FC-HC25 FBGA 170P A31 !

UV15

SA00009TA2L

S8_R1@

S IC D5 256M32 K4G80325FC-HC25 FBGA 170P

UV15

SA00009TA3L

S8_R3@

S IC D5 256M32 K4G80325FC-HC25 FBGA 170P A31 !

Hynix 2G

UV13

SA0000C170L

H8_R1@

S IC D5 256M32 H5GC8H24AJR-R2C BGA 170P

UV13

SA0000C171L

H8_R3@

S IC D5 256M32 H5GC8H24AJR-R2C BGA A31!

UV15

SA0000C170L

H8_R1@

S IC D5 256M32 H5GC8H24AJR-R2C BGA 170P

UV15

SA0000C171L

H8_R3@

S IC D5 256M32 H5GC8H24AJR-R2C BGA A31!

Micron 2G

UV13

SA00009TI2L

M8_R1@

S IC D5 256M32 MT51J256M32HF-80:B FBGA

UV13

SA00009TI3L

M8_R3@

S IC D5 256M32 MT51J256M32HF-80:B A31!

Samsung 2G Hynix 2G Micron 2G

RV16

2G_S@

UV15

SA00009TI2L

M8_R1@

S IC D5 256M32 MT51J256M32HF-80:B FBGA

UV15

SA00009TI3L

M8_R3@

S IC D5 256M32 MT51J256M32HF-80:B A31!

RV15

2G_H@

RV16

2G_H@

RV15

2G_M@

4.75K_0402_1%

SD03447518 0

B B

MCP

GPP_B13

GPP_D10

GPP_D13

GPP_D18

PCH_P LTRST#

DGPU_H OLD_RS T#

DGPU_P WR_E N

DGPU_ PWRO K

AND GATE

PLTRST#

AND GATE

PLT_RST_VGA#

GPU

PERSTB

3.4K_0402_1%

SD03434018 0

10K_0402_1%

SD03410028 0

For AMD R17M-M1-30 VRAM

4.75K_0402_1%

SD03447518 0

8Gb R3 P/N Conf i g ur at i on SizeMemory ID Vendor

Deciphered Date

SAMSUNG

Hynix

Micron

Compal Electronics, Inc.

Title

MESO_Note

Size

Document Number Re v

LA-G716P

Date : Sheet o f

1

SA00009TA3L S IC D5 256M32 K4G80325FC-HC25 FBGA 170P A31 !

000

SA0000C171L S IC D5 256M32 H5GC8H24AJR-R2C BGA A31!

+3VS

+1.05V_PRIM

B+

LDO

PWM

DGPU_P WR_E N

A A

DGPU_P WR_E N D GPU_P WROK

5

Only for Dell

1

2

3

+3VGS

+0.95VSDGPU

+VGA_CORE

+1.8V_PRIM

DGPU_P WR_E N

2

3

+1.8VGS

+1.35V_MEM_GFX

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

LDO

B+

PWM

4

110

SA00009TI3L S IC D5 256M32 MT51J256M32HF-80:B A31!111

Compal Secret Data

2019/06/20 2020/06/30

Compal Secret Data

2

2GB

1.0

30 101Thursday, June 20, 2019

1.0

Dell Inspiron 3490, Inspiron 3590, Inspiron 3790, Inspiron 5494, Inspiron 5594 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual