Dell Inspiron 3459, Inspiron 3559 Schematics

5

D D

4

3

2

1

Iris2 Schematics

Skylake-U

C C

2015/05/20 REV : A00

B B

DY : None Installed

A A

UMA: UMA only installed OPS: DISCRTE OPTIMUS installed

5

4

3

2

Iris SKL UMA

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Tuesday, September 08, 2 015

Date: Sheet of

Cover Page

Iris2 SKL-U

Taipei Hsien 221, Taiwan, R.O.C.

1 105

1

X02

Project code:

5

Iris-2 14 --> 4PD02V010001 PCB P/N: 14236-SF Revision:A00

IO Board: 14927

D D

Thermal

NUVOTON NCT7718W

SMBUS

79

GPU

VRAM(DDR3L) *4

2GB (Single Rank)

4GB (Dual Rank)

81,82,83,84

DDR3L

DIS only

DP/VGA Converter

VGA Conn.

Co-lay

HDMI V1.4a

C C

14.0"/15.6" (HD)

2CH SPEAKER (2CH 2W/4ohm)

B B

29

Universal Jack

IO Board (14927-SB)

A A

5

VGA

56

HDMI

57

Camera (HD)

MIC_IN/GND

HP_R/L

USB2(USB2.0)

USB3(USB2.0)

Left side

USB1(USB3.0)

AMD MESO-LE (14"/15") (23x23) 25W

76,77,78,79,80

REALTEK RTD2168-CGT

D-MIC

52

HDA CODEC

Realtek ALC3246-CG

27

USB2.0 x 1

USB3.0 x 1

4

3

Iris2 SKL-U Block Diagram

DDR3L 1333/1600 MHz Channel A

PCIe x 4

56

eDP

USB2.0 x 1

HDA

USB2.0 x 1

4

Intel CPU

Skylake U

28W (UMA only) 15W (UMA&DIS)

SKL PCH-LP

10 USB 2.0/1.1 ports

6 USB 3.0 ports

High Definition Audio

3 SATA ports

6 PCIE ports

LPC I/F

ACPI 5.0

DDR3L 1333/1600 MHz Channel B

PCIe x 1

USB2.0 x 1

LAN 10/100

RealTek RTL8106E

NGFF WLAN

802.11b/g/n

802.11ac BT 4.0 1x1

LPC BUS

MEC1404-NU-GP

SPI

Flash ROM

8MB

Flash ROM

4MB

I2C

SATA(Gen3) x 1

25

NON Precision Touchpad

9.5 mm HDD

SATA(Gen1) x 1

CardReader

USB2.0 x 1

3

SD 3.0

Realtek RTS5170

LPC debug port

KBC

SMSC

ODD

33

PS2

60

30

61

65

Int. KB

65

60

SD Card Slot

2

DDR3L 1600

SODIMM A

12

DDR3L 1600

SODIMM B

13

RJ45 Conn.

PCB LAYER

L1:Top L2:VCC L3:Signal L4:Signal L5:VCC L6:Signal

L7:GND L8:bottom

1

CHARGER

BQ24770RUYR

INPUTS

AD+

BT+

SYSTEM DC/DC

RT6576DGQW-GP

INPUTS

DCBATOUT

CPU Core Power

NCP81208MNTXG NCP81382MNTXG x 2 NCP81382MNTXG ( 23e) NCP81253MNTBG

INPUTS

DCBATOUT

DCBATOUT +VCCGT

DCBATOUT

DDR3L SUS

TPS51716RUKR

INPUTS OUTPUTS

DCBATOUT 1D35V_S3

CPU VCCIO 1V

TPS22961DNYT

3D3V_S5

OUTPUTS

DCBATOUT

OUTPUTS

3D3V_AUX_S5 5V_PWR_2 5V_S5 3D3V_S5

OUTPUTS

VCC_CORE

+VCCGT (23e)

+VCCSADCBATOUT

0D65V_S0

OUTPUTSINPUTS

+VCCIO_VR

46~50

33

CPU VCCPRIM_CORE

44

45

51

52

1V

OUTPUTS

5V_S0

3D3V_S03D3V_S5

OUTPUTS

+V_EDRAM_VR +V_EOPIO_VR

OUTPUTS

3D3V_VGA_S0

40

A00

52

53

54

41

86

SMBUS

24

Thermal

NUVOTON NCT7718W

Fan Control

BCD AP2113MTR

FAN

26

HSIO PWR

INPUTS

+VCCMPHYGTAON_1P0_LS_SIP

1D0V_S5

VCCSTG

M5938ARD1U

INPUTS

1D0V_S5

VCCST

M5938ARD1U

INPUTS

1D0V_S5

26

OUTPUTS

+V1.00DX

OUTPUTS

+V1.00U_CPU

1D0V_PWR

CPU DCDC-V1D00A

SY8208DQNC

INPUTS OUTPUTS

DCBATOUT

LDO-V1D5V

S-1339D15-M5001

3D3V_S5

LDO-V1D8V

17

APL5930KAI-TRG

INPUTS OUTPUTS

3D3V_S5

40

G5016KD1U

INPUTS

5V_S5

EOPIO/EDRAM (23e)

40

TPS22961DNYT

INPUTS

1D0V_S5 1D0V_S5

AO3419L

INPUTS

3D3V_S0

Iris SKL UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

C

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

Iris2 SKL-U

1

OUTPUTSINPUTS

VCCPRIM_CORE

1D0V_S5

OUTPUTSINPUTS

1D5V_S0

1D8V_S5

5V/3V S0

3D3V VGA

2 105Tuesday, May 26, 2015

5

4

3

2

1

Main Func = CPU

D D

C C

(Blanking)

B B

A A

5

4

3

2

Iris SKL UMA

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

A3

(Reserved)

Iris2 SKL-U

Taipei Hsien 221, Taiwan, R.O.C.

3 105Tuesday, May 26, 2015

1

A00

5

4

3

2

1

Main Func = CPU

+VCCST_ CPU

12

+VCCSTG

D D

[PECI] and [PRO CHOT#] Impedance contr ol: 50 ohm

H_PECI[24]

H_PROCH OT#[2 4,44,46]

XDP_BPM [3:0][99]

#543016 Rev0.7: Ra = 500 ohm / Rb = 1k ohm #544669 Rev0.52 : Ra = 56 ohm (TO BE CHANGED TO 100 OHMS) / Rb = 62 ohm and 150 ohm

TOUCH_P ANEL_INTR#[24,55]

C C

INT_TP#[24,65]

Rb

+VCCSTG = 1.0 V +VCCSTG = 1.0 V

12

R401

R401 1KR2J-1-G P

1KR2J-1-G P

R403499R2F-2 -GP R403499R2F-2 -GP

1 2

Ra

Do Not Stuff

R404 Do N ot StuffR404 Do N ot Stuff

1 2

Do Not Stuff

TP403

TP404

TP401

Do Not Stuff

TP402

GPP_E3/C PU_GP0

1

GPP_B4/C PU_GP3

1

R41249D9R2F -GP R41249D9R2F -GP R41349D9R2F -GP R41349D9R2F -GP R41449D9R2F -GP R41449D9R2F -GP R41549D9R2F -GP R41549D9R2F -GP

H_CATER R#

1

H_PROCH OT#_R PCH_THE RMTRIP SKTOCC#

1

XDP_BPM 0 XDP_BPM 1 XDP_BPM 2 XDP_BPM 3

TOUCHPA D_INTR#

CPU_POP IRCOMP

12

PCH_POP IRCOMP

12

EDRAM_O PIO_RCOMP

12

EOPIO_RCO MP

12

PCH_THE RMTRIP

CPU1D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKYLAKE-GP

071.SKYLA.000U

SKYLAKE_ULT

CPU MISC

(#543016) PROCHOT# Routing Guidelines

#544669 CRB Rev 0.52

R419

R419 1KR2J-1-G P

1KR2J-1-G P

R420

1 2

DY

Do Not Stuff

JTAG

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

4 OF 20

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PCH_TRST#

JTAGX

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

H_THERM TRIP# [40]

XDP_TCL K [99]

XDP_TDI [99] XDP_TDO _CPU [99] XDP_TMS [99] XDP_TRS T# [99]

PCH_JTA G_TCK [99] PCH_JTA G_TDI [99 ] PCH_JTA G_TDO [99] PCH_JTA G_TMS [99] XDP_TRS T# [99] XDP_TCK _JTAGX [99]

XDP_TMS XDP_TDI

XDP_TDO _CPU

PCH_JTA G_TDI

PCH_JTA G_TDO

PCH_JTA G_TMS

XDP_TCK _JTAGX

XDP_TRS T# XDP_TCL K

PCH_JTA G_TCK

1 2

DY

R421D o Not Stuff

DY

R421D o Not Stuff R422D o Not Stuff

R422D o Not Stuff

R423D o Not Stuff

R4085 1R2J-2-GP R4085 1R2J-2-GP

R4095 1R2J-2-GP R4095 1R2J-2-GP

R4165 1R2J-2-GP R4165 1R2J-2-GP

R417Do Not Stu ff

1 2

PH in P.99

1 2

R402 Do Not Stuff

1 2

R406 51R2J-2-G PR406 51R2J-2-G P

1 2

R407 Do Not Stuff

1 2

+VCCSTG

B B

M1,2,3,4,5: <3 inches M6: 1-11 inches MCPU: 0.3-1.5 i nches Mt <0.3 mils Main route(M1+M 2+M3+M4+M5+M6+ MCPU): 1-12 inc hes

A A

5

4

3

2

Iris SKL UMA

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(JTAG/CPU SIDE BAND)

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Iris2 SKL-U

4 105Wednesd ay, September 09, 20 15

1

X02

Main Func = CPU

M_A_DQ[63:0][12]

5

4

3

2

1

DDR3L ball type: Interleaved Type

M_B_DQ[63:0][13]

D D

CPU1B

M_A_DQ0

AL71

M_A_DQ1 M_A_DQ2 M_A_DQ3

M_A_DQ[0:7]

M_A_DQ[8:15]

M_B_DQ[0:7]

M_B_DQ[8:15]

C C

M_A_DQ[16:23]

M_A_DQ[24:31]

M_B_DQ[16:23]

M_B_DQ[24:31]

DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel.

B B

Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential clock pair to clock pair swapping within a channel is not allowed.

M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

AF65

DDR1_DQ[0]/DDR0_DQ[8]

AF64

DDR1_DQ[1]/DDR0_DQ[9]

AK65

DDR1_DQ[2]/DDR0_DQ[10]

AK64

DDR1_DQ[3]/DDR0_DQ[11]

AF66

DDR1_DQ[4]/DDR0_DQ[12]

AF67

DDR1_DQ[5]/DDR0_DQ[13]

AK67

DDR1_DQ[6]/DDR0_DQ[14]

AK66

DDR1_DQ[7]/DDR0_DQ[15]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

SKYLAKE-GP

SKYLAKE_ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[ 5]

DDR0_DQ[16]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[ 9]

DDR0_DQ[17]

DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[ 6]

DDR0_DQ[18]

DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[ 8]

DDR0_DQ[19]

DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[ 7]

DDR0_DQ[20]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_DQ[21]

DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[ 12]

DDR0_DQ[22]

DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[ 11]

DDR0_DQ[23]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT # DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[ 13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[ 2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[ 10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[ 1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[ 0]

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7]

DDR CH - A

071.SKYLA.000U

DDR1_DQSN[0]/DDR0_DQ[2] DDR1_DQSP[0]/DDR0_DQ[2] DDR1_DQSN[1]/DDR0_DQ[3] DDR1_DQSP[1]/DDR0_DQ[3]

PDG: DDR/ODT

A A

5

2 OF 20

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

M_A_DQ32

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

M_A_A5

BA51

M_A_A9

BB54

M_A_A6

BA52

M_A_A8

AY52

M_A_A7

AW52 AY55

M_A_A12

AW54

M_A_A11

BA54

M_A_A15

BA55

M_A_A14

AY54

M_A_A13

AU46 AU48 AT46 AU50 AU52

M_A_A2

AY51 AT48

M_A_A10

AT50

M_A_A1

BB50

M_A_A0

AY50

M_A_A3

BA50

M_A_A4

BB52

M_A_DQS_DN0

AM70

M_A_DQS_DP0

AM69

M_A_DQS_DN1

AT69

M_A_DQS_DP1

AT70

M_B_DQS_DN0

AH66

M_B_DQS_DP0

AH65

M_B_DQS_DN1

AG69

M_B_DQS_DP1

AG70

M_A_DQS_DN2

BA64

M_A_DQS_DP2

AY64

M_A_DQS_DN3

AY60

M_A_DQS_DP3

BA60

M_B_DQS_DN2

AR66

M_B_DQS_DP2

AR65

M_B_DQS_DN3

AR61

M_B_DQS_DP3

AR60

AW50

DDR0_PAR

AT52

AY67 AY68 BA67

AW67

4

M_A_CLK#0 [12] M_A_CLK0 [12] M_A_CLK#1 [12] M_A_CLK1 [12]

M_A_CKE0 [12] M_A_CKE1 [12]

M_A_CS#0 [12] M_A_CS#1 [12] M_A_DIMA_ODT0 [12] M_A_DIMA_ODT1 [12]

M_A_BS2 [12]

M_A_CAS# [12]

M_A_WE# [12]

M_A_RAS# [12]

M_A_BS0 [12]

M_A_BS1 [12]

M_A_DQS0

M_A_DQS1

M_B_DQS0

M_B_DQS1 M_A_DQS2

M_A_DQS3

M_B_DQS2

M_B_DQS3

TP501 Do Not StuffTP501 Do Not Stuff

1

V_SM_VREF_CN T [42]

M_VREF_DQ_D IM0 [42] M_VREF_DQ_D IM1 [42]

SM_PGCNTL [51]

M_A_DQ[32:39]

M_A_DQ[40:47]

M_B_DQ[32:39]

M_B_DQ[40:47]

M_A_DQ[48:55]

M_A_DQ[56:63]

M_B_DQ[48:55]

M_B_DQ[56:63]

M_A_DQ33

M_A_DQ34

M_A_DQ35

M_A_DQ36

M_A_DQ37

M_A_DQ38

M_A_DQ39

M_A_DQ40

M_A_DQ41

M_A_DQ42

M_A_DQ43

M_A_DQ44

M_A_DQ45

M_A_DQ46

M_A_DQ47

M_B_DQ32

M_B_DQ33

M_B_DQ34

M_B_DQ35

M_B_DQ36

M_B_DQ37

M_B_DQ38

M_B_DQ39

M_B_DQ40

M_B_DQ41

M_B_DQ42

M_B_DQ43

M_B_DQ44

M_B_DQ45

M_B_DQ46

M_B_DQ47

M_A_DQ48

M_A_DQ49

M_A_DQ50

M_A_DQ51

M_A_DQ52

M_A_DQ53

M_A_DQ54

M_A_DQ55

M_A_DQ56

M_A_DQ57

M_A_DQ58

M_A_DQ59

M_A_DQ60

M_A_DQ61

M_A_DQ62

M_A_DQ63

M_B_DQ48

M_B_DQ49

M_B_DQ50

M_B_DQ51

M_B_DQ52

M_B_DQ53

M_B_DQ54

M_B_DQ55

M_B_DQ56

M_B_DQ57

M_B_DQ58

M_B_DQ59

M_B_DQ60

M_B_DQ61

M_B_DQ62

M_B_DQ63

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQS_DN0

M_A_DQS_DN1

M_A_DQS_DN2

M_A_DQS_DN3

M_A_DQS_DN4

M_A_DQS_DN5

M_A_DQS_DN6

M_A_DQS_DN7

M_A_DQS_DP0

M_A_DQS_DP1

M_A_DQS_DP2

M_A_DQS_DP3

M_A_DQS_DP4

M_A_DQS_DP5

M_A_DQS_DP6

M_A_DQS_DP7

3

CPU1C

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKYLAKE-GP

071.SKYLA.000U

M_A_A[15:0] [12]

M_A_DQS_DN[7: 0] [12]

M_A_DQS_DP[7:0] [12]

SKYLAKE_ULT

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[ 5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[ 9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[ 6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[ 8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[ 7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[ 12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[ 11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT # DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[ 13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[ 2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[ 10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[ 1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[ 0]

DDR CH - B

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

Design Guideline: SM_RCOMP keep routing length less than 500 mils.

2

3 OF 20

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

BA38 AY38 AY34 BA34 AT38 AR38 AT32 AR32 BA30 AY30 AY26 BA26 AR25 AR27 AR22 AR21

AN43 AP43 AT13 AR18 AT18 AU18

M_B_A5 M_B_A9 M_B_A6 M_B_A8 M_B_A7

M_B_A12 M_B_A11 M_B_A15 M_B_A14

M_B_A13

M_B_A2

M_B_A10 M_B_A1 M_B_A0 M_B_A3 M_B_A4

M_A_DQS_DN4 M_A_DQS_DP4 M_A_DQS_DN5 M_A_DQS_DP5 M_B_DQS_DN4 M_B_DQS_DP4 M_B_DQS_DN5 M_B_DQS_DP5 M_A_DQS_DN6 M_A_DQS_DP6 M_A_DQS_DN7 M_A_DQS_DP7 M_B_DQS_DN6 M_B_DQS_DP6 M_B_DQS_DN7 M_B_DQS_DP7

DDR1_PAR SM_DRAMRST # SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

#543016

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQS_DN0 M_B_DQS_DN1 M_B_DQS_DN2 M_B_DQS_DN3 M_B_DQS_DN4 M_B_DQS_DN5 M_B_DQS_DN6 M_B_DQS_DN7

M_B_DQS_DP0 M_B_DQS_DP1 M_B_DQS_DP2 M_B_DQS_DP3 M_B_DQS_DP4 M_B_DQS_DP5 M_B_DQS_DP6 M_B_DQS_DP7

M_B_CLK#0 [13] M_B_CLK#1 [13] M_B_CLK0 [13] M_B_CLK1 [13]

M_B_CKE0 [13] M_B_CKE1 [13]

M_B_CS#0 [13] M_B_CS#1 [13] M_B_DIMB_ODT0 [13] M_B_DIMB_ODT1 [13]

M_B_BS2 [13]

M_B_CAS# [13]

M_B_WE# [13]

M_B_RAS# [13]

M_B_BS0 [13]

M_B_BS1 [13]

M_A_DQS4

M_A_DQS5

M_B_DQS4

M_B_DQS5

M_A_DQS6

M_A_DQS7

M_B_DQS6

M_B_DQS7

TP502 Do Not StuffTP502 Do Not Stuff

1

R501 121R2F-GPR501 121R2F-GP

1 2

R502 80D6R2F-L-G PR502 80D6R2F-L-G P

1 2

R503 100R2F-L1-GP- UR503 100R2F-L1-GP- U

1 2

Layout Note:

M_B_A[15:0] [13]

M_B_DQS_DN[7: 0] [13]

M_B_DQS_DP[7:0] [13]

1D35V_S3

12

R505

R505 470R2F-GP

470R2F-GP

R504

DY

1 2

Do Not Stuff

D502

Do Not Stuff

DDR3_DR AMRST# [12,13]

close to CPU

Iris SKL UMA

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

CPU_(DDR)

Iris2 SKL-U

1

5 105Wednesd ay, September 09, 2015

A00

Main Func = CPU

D D

C C

PCH strap pin:

CFG3

CFG4

5

CPU1S

RESERVED SIGNALS-1

CFG[19:0][99]

ITP_PMODE[99]

TP601Do Not Stuff TP601Do Not Stuff TP602Do Not Stuff TP602Do Not Stuff

TP612Do Not Stuff TP612Do Not S tuff TP613Do Not Stuff TP613Do Not S tuff

12

DY

[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

R604

R604 Do Not Stuff

Do Not Stuff

CFG[3]

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG17

CFG18 CFG19

CFG_RCOM P

R60149D 9R2F-GP R60149D 9R2F-GP

12

RSVD_TP_BA70

1

RSVD_TP_BA68

1

RSVD_F65

1

RSVD_G65

1

0 : ENABLED SET DFX ENABLED BIT IN DEBUG INTERFACE MSR

1 : DISABLED

E68 B67 D65 D67 E70 C68 D68 C67 F71 G69 F70 G68 H70 G71 H69 G70

E63 F63

E66 F66

E60

E8

AY2 AY1

D1 D3

K46 K45

AL25 AL27

C71 B70

F60

A52

BA70 BA68

J71 J68

F65 G65

F61 E61

RESERVED SIGNALS-1

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2 RSVD_AY1

RSVD_D1 RSVD_D3

RSVD_K46 RSVD_K45

RSVD_AL25 RSVD_AL27

RSVD_C71 RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70 RSVD_TP_BA68

RSVD_J71 RSVD_J68

VSS_F65 VSS_G65

RSVD_F61 RSVD_E61

SKYLAKE-GP

071.SKYLA.000U

SKYLAKE_ULT

(#543016)

12

DISPLAY PORT PRESENCE STRAP

R605

R605 1KR2J-1-GP

1KR2J-1-GP

CFG[4]

0 : ENABLED An external Display Port device is connected to the Embedded Display Port.

1 : DISABLED (Default) No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.

4

RSVD_TP_AW71 RSVD_TP_AW70

19 OF 20

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4 RSVD_C4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

VSS_AY71

ZVM#

RSVD_AW71 RSVD_AW70

MSM#

PROC_SELECT#

3

RSVD_TP_BB68

BB68

RSVD_TP_BB69

BB69

RSVD_TP_AK13

AK13

RSVD_TP_AK12

AK12

BB2 BA3

TP5_AU5

AU5

TP5

TP6_AT5

AT5

TP6

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

TP4_BB5

BB5

TP4

A69 B69

AY3

D71 C70

C54 D54

TP1_AY4

AY4

TP1

TP2_BB3

BB3

TP2

VSS_AY71

AY71

ZVM#

AR56

RSVD_TP_AW 71

AW71

RSVD_TP_AW 70

AW70

MSM#

AP56 C64

PROC_SELEC T#

R602

1 2

Do Not Stuff

1 1

1

1 1

1

1 1

1

1 2

R603

100KR2J-1-GP

TP603 Do Not StuffTP603 Do Not Stuff TP604 Do Not StuffTP604 Do Not Stuff

TP605 Do Not StuffTP605 Do Not Stuff TP606 Do Not StuffTP606 Do Not Stuff

TP607 Do Not StuffTP607 Do Not Stuff TP608 Do Not StuffTP608 Do Not Stuff

TP609 Do Not StuffTP609 Do Not Stuff

TP610 Do Not StuffTP610 Do Not Stuff TP611 Do Not StuffTP611 Do Not Stuff

TP616 Do Not StuffTP616 Do Not Stuff

TP614 Do Not StuffTP614 Do Not Stuff TP615 Do Not StuffTP615 Do Not Stuff

TP617 Do Not StuffTP617 Do Not Stuff

#54469 CRB.

+VCCST_CP U

CFG TERMINATIONS

20140807 david

2

1

#544669 Rev0.52 (CRB)

SKL(#543016): Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*

B B

A A

Iris SKL UMA

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

CPU_(RESERVED)

Iris2 SKL-U

1

6 105Wednesd ay, September 09, 2015

A00

R702

3A

Do Not Stuff

3A

TP701Do Not Stuff TP701Do Not Stuff

TP702Do Not Stuff TP702Do Not Stuff

1 2

23e

+V_EDRAM_VR

+V_EOPIO_VR

5

1

+V_EDRAM_VR

VCC_EDRAM_FUSEPRG

VCCSENSE_EDRAM_VR VSSSENSE_EDRAM_VR

+V_EOPIO_VR

VCCSENSE_EOPIO_VR VSSSENSE_EOPIO_VR

12

R724

R724 Do Not Stuff

Do Not Stuff

23e

12

R725

R725 Do Not Stuff

Do Not Stuff

23e

12

R729

R729 Do Not Stuff

Do Not Stuff

23e

12

R731

R731 Do Not Stuff

Do Not Stuff

23e

VCC_CORE

+VCCCOREG0

+VCCCOREG1

VCCSENSE_EDRAM_VR VSSSENSE_EDRAM_VR

VCCSENSE_EOPIO_VR VSSSENSE_EOPIO_VR

CPU1L

A30

VCC_A3 0

A34

VCC_A3 4

A39

VCC_A3 9

A44

VCC_A4 4

AK33

VCC_AK 33

AK35

VCC_AK 35

AK37

VCC_AK 37

AK38

VCC_AK 38

AK40

VCC_AK 40

AL33

VCC_AL 33

AL37

VCC_AL 37

AL40

VCC_AL 40

AM32

VCC_AM3 2

AM33

VCC_AM3 3

AM35

VCC_AM3 5

AM37

VCC_AM3 7

AM38

VCC_AM3 8

G30

VCC_G3 0

K32

VCCG0

AK32

VCCG1

AB62

VCCOPC _AB62

P62

VCCOPC _P62

V62

VCCOPC _V62

H63

VCC_OP C_1P8_ H63

G61

VCC_OP C_1P8_ G61

AC63

VCCOPC _SENSE

AE63

VSSOPC _SENSE

AE62

VCCEOP IO

AG62

VCCEOP IO

AL63

VCCEOP IO_SENS E

AJ62

VSSEOP IO_SENS E

SKYLAKE-GP

071.SKYLA.000U

RSVD_K32

RSVD_AK32

CPU POWER 1 OF 4

SKYLAKE_ULT

12 OF 20

G32

VCC_G3 2

G33

VCC_G3 3

G35

VCC_G3 5

G37

VCC_G3 7

G38

VCC_G3 8

G40

VCC_G4 0

G42

VCC_G4 2

J30

VCC_J3 0

J33

VCC_J3 3

J37

VCC_J3 7

J40

VCC_J4 0

K33

VCC_K3 3

K35

VCC_K3 5

K37

VCC_K3 7

K38

VCC_K3 8

K40

VCC_K4 0

K42

VCC_K4 2

K43

VCC_K4 3

E32

VCC_SE NSE

E33

VSS_SE NSE

B63

VIDALE RT#

A63

VIDSCK

D64

VIDSOUT

G20

VCCSTG _G20

SVID DATA

VCC_CORE

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

+VCCFUSEPRG

Main Func = CPU

D D

+V1.8S_EDRAM

140mA

+V_EDRAM_VR

12

C702Do Not Stuff

C701Do Not Stuff

23e

+V_EOPIO_VR

12

C704Do Not Stuff

C703Do Not Stuff

23e

C C

CLOSE TO CPU

H_CPU_SVIDDAT

VCC_SENSE [46] VSS_SENSE [46]

R703

1 2

Do Not Stuff

+VCCST_CPU

12

4

CPU1M

+VCCGT

+VCCSTG

VCCGT_SENSE[46] VSSGT_SENSE[46]

Layout Note: The total Length of Data and Clock (from CPU to each VR) m ust be equal (±0.1 inch). Route the Alert signal betwee n the Clock and the Data sign als.

R726

#544669

100R2F-L1-GP-U

R709

1 2

Do Not Stuff

A48

VCCGT

A53

VCCGT

A58

VCCGT

A62

VCCGT

A66

VCCGT

AA63

VCCGT

AA64

VCCGT

AA66

VCCGT

AA67

VCCGT

AA69

VCCGT

AA70

VCCGT

AA71

VCCGT

AC64

VCCGT

AC65

VCCGT

AC66

VCCGT

AC67

VCCGT

AC68

VCCGT

AC69

VCCGT

AC70

VCCGT

AC71

VCCGT

J43

VCCGT

J45

VCCGT

J46

VCCGT

J48

VCCGT

J50

VCCGT

J52

VCCGT

J53

VCCGT

J55

VCCGT

J56

VCCGT

J58

VCCGT

J60

VCCGT

K48

VCCGT

K50

VCCGT

K52

VCCGT

K53

VCCGT

K55

VCCGT

K56

VCCGT

K58

VCCGT

K60

VCCGT

L62

VCCGT

L63

VCCGT

L64

VCCGT

L65

VCCGT

L66

VCCGT

L67

VCCGT

L68

VCCGT

L69

VCCGT

L70

VCCGT

L71

VCCGT

M62

VCCGT

N63

VCCGT

N64

VCCGT

N66

VCCGT

N67

VCCGT

N69

VCCGT

J70

VCCGT_ SENSE

J69

VSSGT_ SENSE

SKYLAKE-GP

071.SKYLA.000U

VR_SVID_DATA [46]

CPU POWER 2 OF 4

SKYLAKE_ULT

13 OF 20

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX _AK42 VCCGTX _AK43 VCCGTX _AK45 VCCGTX _AK46 VCCGTX _AK48 VCCGTX _AK50 VCCGTX _AK52 VCCGTX _AK53 VCCGTX _AK55 VCCGTX _AK56 VCCGTX _AK58 VCCGTX _AK60 VCCGTX _AK70 VCCGTX _AL43 VCCGTX _AL46 VCCGTX _AL50 VCCGTX _AL53 VCCGTX _AL56

VCCGTX _AL60 VCCGTX _AM48 VCCGTX _AM50 VCCGTX _AM52 VCCGTX _AM53 VCCGTX _AM56 VCCGTX _AM58 VCCGTX _AU58 VCCGTX _AU63 VCCGTX _BB57 VCCGTX _BB66

VCCGTX _SENSE VSSGTX _SENSE

3

+VCCGT

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

+VCCGT

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

#544669 CRB.

R705

1 2

Do Not Stuff

+VDDQ_CPU_CLK1D35V_S3

DY

1D35V_S3+VDDQ_CPU_CLK

12

C722

C722 Do Not Stuff

Do Not Stuff

12

C719

C719 SC1U10V2KX-1GP

VCC_CORE

+VCCGT

DY

12

SC1U10V2KX-1GP

+VDDQ_CPU_CLK

C715SC10U6D3V3MX-GP C715SC10U6D3V3MX-GP

12

+VCCST_CPU

C716SC1U10V2KX-1GP C716SC1U10V2KX-1GP

12

C717Do Not StuffDYC717Do Not Stuff

12

C718SCD1U16V2KX-3GP C718SCD1U16V2KX-3GP

12

R719

R719 100R2F-L1-GP-U

100R2F-L1-GP-U

R720

R720 100R2F-L1-GP-U

100R2F-L1-GP-U

R721

R721 100R2F-L1-GP-U

100R2F-L1-GP-U

R722

R722 100R2F-L1-GP-U

100R2F-L1-GP-U

+VCCSTG

1D35V_S3

+V1.00U_CPU

12

0.04 A

12

C720

SCD1U16V2KX-3GP

AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51

AM40

A18

A22

AL23

K20 K21

0.12 A

C721

SCD1U16V2KX-3GP

VCC_SENSE [46]

VSS_SENSE [46]

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Length match<25mil

VCCGT_SENSE [46]

VSSGT_SENSE [46]

CPU1N

CPU POWER 3 OF 4

VDDQ_A U23 VDDQ_A U28 VDDQ_A U35 VDDQ_A U42 VDDQ_B B23 VDDQ_B B32 VDDQ_B B41 VDDQ_B B47 VDDQ_B B51

VDDQC

VCCST

VCCSTG _A22

VCCPLL _OC

VCCPLL _K20 VCCPLL _K21

SKYLAKE-GP

071.SKYLA.000U

SKYLAKE_ULT

2

VCCIO_ SENSE VSSIO_ SENSE

VSSSA_ SENSE VCCSA_ SENSE

14 OF 20

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

VCCIO_VR_FB

VSSIO_VR_FB

VCCSA_SENSE VSSSA_SENSE

VCCIO_VR_FB VSSIO_VR_FB

+VCCIO

+VCCIO(ICCMAX.=2.73A

+VCCSA

+VCCIO

12

+VCCSA

12

R733

R733 100R2F-L1-GP-U

100R2F-L1-GP-U

R730

R730 100R2F-L1-GP-U

100R2F-L1-GP-U

R735

R735 100R2F-L1-GP-U

100R2F-L1-GP-U

R734

R734 100R2F-L1-GP-U

100R2F-L1-GP-U

VSSSA_SENSE [46] VCCSA_SENSE [46]

(#543016 SKL U/Y PDG rev1.0)

1

12

R732

1 2

Do Not Stuff

+VCCST_CPU

4

12

R727

R727 56R2J-4-GP

56R2J-4-GP

+VCCST_CPU

DY

#544669 CLOSE TO CPU

12

R723

R723 Do Not Stuff

Do Not Stuff

#544669 CLOSE TO VR

VR_SVID_ALERT# [46]

VR_SVID_CLK [46]

SVID_543016:

Iris SKL UMA

Title

Size Document Number Rev

Size Document Number Rev A1

A1

Wednesday, September 09, 2015

Date: Sheet of

3

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU(VCC_CORE)

Iris2 SKL-U

7 105

A00

SVID CLOCK

B B

A A

5

H_CPU_SVIDCLK

H_CPU_SVIDALRT#

R728

220R2J-L2-GP

5

4

3

2

1

Main Func = CPU

Strap pin:

Port B / Port C Detected

D D

DDPB_CTRLDATA

DDPC_CTRLDATA

These two signals have weak inte rnal pull-down.

C C

Sampled at rising edge of PCH_PWROK

0 = Port B is not detected . 1 = Port B is detected.

*

0 = Port C is not detected. 1 = Port C is detected.

*

3D3V_S0

RN801

3D3V_S0

RN801

2 3 1

SRN2K2J -1-GP

RN803

2 3 1

DY

Do Not Stuff

CPU_DP1 _CTRL_CLK CPU_DP1 _CTRL_DATA

4

CPU_DP2 _CTRL_DATA CPU_DP2 _CTRL_CLK

4

HDMI/CRT

HDMI

+VCCIO

Check

CPU_DP1 _CTRL_CLK[57]

CPU_DP1 _CTRL_DATA[57]

R801

1 2

24D9R2F -L-GP

HDMI_CRT_ N0[56,57]

HDMI_CRT_ P0[56,57]

HDMI_CRT_ N1[56,57]

HDMI_CRT_ P1[56,57]

HDMI_DATA 0#[5 7]

HDMI_DATA 0[57]

HDMI_CLK#[57]

HDMI_CLK[57]

Do Not Stuff

TP802

1 OF 20

CPU1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

CPU_DP2 _CTRL_CLK SIO_EXT_S MI#_R CPU_DP2 _CTRL_DATA

DDPD_CT RLDATA

1

EDP_COM P

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKYLAKE-GP

071.SKYLA.000U

SKYLAKE_ULT

DDI

DISPLAY SIDEBANDS

Strap

EDP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

1 OF 20

EDP_TXN[0]

EDP_TXP[0]

EDP_TXN[1]

EDP_TXP[1]

EDP_TXN[2]

EDP_TXP[2]

EDP_TXN[3]

EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48 F48 G46 F46

CPU_HDM I_HPD

L9 L7 L6

CPU_CRT _HPD

N9 L10

R12 R11 U13

EDP_DISP_ UTIL

(#543016) The S kylake U/Y pro cessor supports only two DDI ports - Port 1 and Port 2.

eDP_TX_C PU_N0 [55] eDP_TX_C PU_P0 [55] eDP_TX_C PU_N1 [55] eDP_TX_C PU_P1 [55]

1

TP801 Do Not StuffTP801 Do Not Stuff

R804

1 2

Do Not Stuff

1 2

CRT

R803 Do Not S tuff

eDP_AUX_ CPU_N [55] eDP_AUX_ CPU_P [55 ]

PCH_DPB _AUXN [5 6] PCH_DPB _AUXP [56]

L_BKLT_ EN [24 ] L_BKLT_ CTRL [55] EDP_VDD _EN [55 ]

CPU_DP1 _HPD [56,57]

SIO_EXT_S MI#_R [24]

EDP_HPD [55]

(#543016) eDP_RCOMP Guideline

Signal Trace

Width

eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1%

B B

Isolation Spacing

Resistor Value

Length

Max = 100 mils

SIO_EXT_S MI#_R

1 2

3D3V_S0

R802 10KR2J-3-GPR80 2 10KR2J-3 -GP

(#543016) DDI Disabling and Termination Guidelines

Port Strap Enable Port D isable Port

Port 1

DDPB_CTRLDATA

Port 2

DDPC_CTRLDATA

A A

Design Guidelin e: Skylake process or signal eDP_ RCOMP should be connected to the VCCIO rail via a single 24 .9 ±1% Ω resis tor.

5

PU to 3.3 V wit h 2.2-k ±5% resistor

NC

Iris SKL UMA

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(DISPLAY)

Iris2 SKL-U

8 105Wednesd ay, September 09, 20 15

1

A00

5

4

3

2

1

Main Func = CPU

D D

C C

(Blanking)

B B

A A

5

4

3

2

Iris SKL UMA

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

A3

(Reserved)

Taipei Hsien 221, Taiwan, R.O.C.

Iris2 SKL-U

9 105Tuesday, May 26, 2015

1

A00

5

4

3

2

1

Main Func = CPU

(#543016 PDG)

CORE

U-line 23e 28W IccMax current-10ms max = 34 A

D D

VCC_CORE

PC1006

PC1007

PC1002

PC1003

PC1004

12

PC1011

12

PC1022

12

PC1004

12

SC22U6D3V3MX-1-GP

PC1012

PC1013

12

SC22U6D3V3MX-1-GP

PC1023

PC1024

12

SC22U6D3V3MX-1-GP

PC1001

12

SC22U6D3V3MX-1-GP

PC1010

12

SC22U6D3V3MX-1-GP

PC1021

C C

12

SC22U6D3V3MX-1-GP

PC1005

12

PC1014

12

PC1025

12

PC1007

PC1008

PC1009

12

PC1016

12

PC1027

12

PC1009

12

SC22U6D3V3MX-1-GP

PC1020

PC1018

12

PC1029

12

PC1020

PC1019

12

SC22U6D3V3MX-1-GP

22U 0603 x 22

PC1030

12

SC22U6D3V3MX-1-GP

PC1017

12

SC22U6D3V3MX-1-GP

PC1028

12

SC22U6D3V3MX-1-GP

12

SC22U6D3V3MX-1-GP

PC1015

12

SC22U6D3V3MX-1-GP

PC1026

12

SC22U6D3V3MX-1-GP

1D35V_S3

PC1055SC10U6D3V3MX-GP PC1055SC10U6D3V3MX-GP

PC1062Do Not StuffDYPC1062Do Not Stuff

DY

10U 0603 x 4

12

PC1057SC10U6D3V3MX-GP PC1057SC10U6D3V3MX-GP

PC1056SC10U6D3V3MX-GP PC1056SC10U6D3V3MX-GP

PC1058SC10U6D3V3MX-GP PC1058SC10U6D3V3MX-GP

PC1064

12

PC1063Do Not StuffDYPC1063Do Not Stuff

DY

Do Not Stuff

12

PC1059Do Not StuffDYPC1059Do Not Stuff

12

PC1060Do Not StuffDYPC1060Do Not Stuff

PC1061Do Not StuffDYPC1061Do Not Stuff

DY

+VCCIO

+VCCPRIM_COR E

+VCCIO(ICCMAX.=2.73A)

12

PC1036SC22U6D3V3MX-1-GP PC1036SC22U6D3V3M X-1-GP

PC1037Do Not StuffDYPC1037Do Not Stuff

PC1035SC22U6D3V3MX-1-GP PC1035SC22U6D3V3M X-1-GP

B B

SLICED GT

U-line 23e 28W IccMax current-10ms max[A] = 67 A

+VCCGT

PC1031

12

SC22U6D3V3MX-1-GP

PC1044

12

SC22U6D3V3MX-1-GP

DY

PC1032

12

PC1069

12

PC1038

PC1039

12

SC22U6D3V5MX-2GP

PC1033

PC1041

PC1042

PC1034

12

SC22U6D3V3MX-1-GP

PC1070

12

SC22U6D3V3MX-1-GP

PC1071

PC1072

PC1073

12

SC22U6D3V3MX-1-GP

PC1043

12

PC1074

12

SC22U6D3V3MX-1-GP

VCCSA

+VCCSA

PC1045

12

PC1076

PC1075

12

SC22U6D3V3MX-1-GP

PC1077

12

PC1046

12

SC22U6D3V3MX-1-GP

PC1078

12

PC1066

PC1065

PC1050

SC22U6D3V3MX-1-GP

PC1081

12

PC1049

12

SC22U6D3V3MX-1-GP

PC1050

PC1051

12

SC22U6D3V3MX-1-GP

PC1053

PC1052

12

SC22U6D3V3MX-1-GP

DY

PC1047

PC1048

12

SC22U6D3V3MX-1-GP

PC1080

PC1079

12

SC22U6D3V3MX-1-GP

PC1065

PC1054

12

Do Not Stuff

DY

12

Do Not Stuff

DY

PC1068

PC1067

12

Do Not Stuff

DY

PC1098

PC1097

12

Do Not Stuff

DY

22U 0603 x 8

22U 0603 x28

A A

PC1094

PC1093

PC1082

12

PC1089

PC1087

12

PC1089

PC1088

PC1090

12

Do Not Stuff

SC22U6D3V3MX-1-GP

DY

SC22U6D3V3MX-1-GP

5

PC1086

PC1084

PC1083

PC1085

12

SC22U6D3V3MX-1-GP

PC1091

12

DY

PC1093

PC1092

12

SC22U6D3V3MX-1-GP

Do Not Stuff

DY

PC1096

PC1095

12

Do Not Stuff

SC22U6D3V3MX-1-GP

Do Not Stuff

DY

4

3

2

Iris SKL UMA

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

CPU_(Power CAP1)

Iris2 SKL-U

1

10 105Tuesday, May 26, 2015

A00

5

4

3

2

1

Main Func = CPU

+VCCGT

12

C1136

C1138

DY

SC1U10V2KX-1GP

Do Not Stuff

D D

C1138,C1148,C1150 DY ( Based on OPI )

12

C1148

12

C1150

C1149

1U 0402 x 6

DY

Do Not Stuff

SC1U10V2KX-1GP

Do Not Stuff

12

C1147

DY

SC1U10V2KX-1GP

UNSLICED GT

+VCCIO

+VCCIO(ICCMAX.=2.73A)

12

C1152

C1151

SC1U10V2KX-1GP

VCCIO

12

C1154

C1153

DY

SC1U10V2KX-1GP

Do Not Stuff

PCH DERIVED RAILS

1D0V_S5 +V1.00A_SIP

R1117

1 2

Do Not Stuff

C C

VCCPRIM_COR E

B B

short pad

R1125 Do Not StuffR1125 Do Not Stuff

1 2

R1122 Do Not StuffR1122 Do Not Stuff

1 2

R1112 Do Not StuffR1112 Do Not Stuff

1 2

R1114 Do Not StuffR1114 Do Not Stuff

1 2

R1121 Do Not StuffR1121 Do Not Stuff

1 2

R1133 Do Not StuffR1133 Do Not Stuff

1 2

R1134 Do Not StuffR1134 Do Not Stuff

1 2

R1130 Do Not StuffR1130 Do Not Stuff

1 2

R1131 Do Not StuffR1131 Do Not Stuff

1 2

R1132 Do Not StuffR1132 Do Not Stuff

1 2

+VCCSA

3 PAD SHARING

R1104

1 2

DY

Do Not Stuff

+V1.00A_SIP

Do Not Stuff

R1105

1 2

DY

Do Not Stuff

R1103

1 2

Do Not Stuff

+VCCF24NS_ 1P0_L

+VCC24TBT_1 P0

+VCCPRIM_1P0

+VCCF100_1P0_L

+VCCF135_1P0

+VCCFHV

+VCCMPHYAON _1P0

+VCCDTS_1P 0

+VCC19P2_1P0

+VCCF100OC _1P0_L

+VCCPRIM_COR E

2014/12/09 modify

3D3V_S5_PCH

Current? TBD

+VCCPGPPA(ICCMAX.=0.05A)

+V1.8A_SIP +VCCPGPPA

+V3.3A_SIP

R1110

1 2

Do Not Stuff

+V1.8A_SIP

Do Not Stuff

+VCCPRIM_COR E +VCCIO

R1107

1 2

DY

R1111

1 2

DY

Do Not Stuff

R1109

1 2

Do Not Stuff

R1115

1 2

Do Not Stuff

R1116

1 2

Do Not Stuff

R1123

1 2

Do Not Stuff

R1124

1 2

Do Not Stuff

R1127

1 2

Do Not Stuff

R1126

1 2

Do Not Stuff

R1128

1 2

Do Not Stuff

R1136

1 2

DY

Do Not Stuff

+VCCPRTC PRIM_3P3

+VCCPGPPB

+VCCPGPPC

+VCCPGPPE

+VCCPRIM_3P3

+VCCPSPI

+VCCPGPPG

GTUS

+VCCGT

+VCCMPHYGTA ON_1P0_LS_SIP

C1174

SC1U10V2KX-1GP

12

+V_VCCGTUS_VR can merge to +VC CGT

PC1105

PC1104

12

PC1107

PC1106

12

C1182

12

DY

12

SC22U6D3V3MX-1-GP

Do Not Stuff

SC22U6D3V3MX-1-GP

+VCCMPHYGTA ON_1P0_LS_SIP

R1101

1 2

0R3J-0-U-G P

C1180

12

+VCCAPLLEBB_1 P0

12

SC1U10V2KX-1GP

20141114 Alden

+VCCMPHYGTAON_1P0(ICCMAX.=3.5A )

C1173

DY

Do Not Stuff

+VCCMPHYGTA ON_1P0_LS_SIP

R1102

1 2

0R3J-0-U-G P

+VCCAMPHYPLL_1P 0_L

Do Not Stuff

C1181

12

DY

C1172

SC1U10V2KX-1GP

12

+VCCMPHYGTA ON_1P0_LS_SIP

R1106

1 2

0R5J-5-GP

+VCCSRAM_1P 0

12

C1176

DY

12

C1175

Do Not Stuff

SC1U10V2KX-1GP

R1135

1 2

Do Not Stuff

R1118

1 2

DY

+VCCPAZIO

+V3.3A_SIP

+V1.8A_SIP

1 2

Do Not Stuff

1 2

Do Not Stuff

3

R1108

R1129

DY

+VCCPGPPD _TCH

1 2

0R3J-0-U-G P

+VCCPGPPD _TCH

12

C1183

DY

Do Not Stuff

R1113

+VCCPGPPD

+VCCAMPHYPLL_1P 0_L +VCCAMPHYPLL_1P 0 +V1.00A_SIP +VCCAPLL_1P0

R1119

+V1.8A +V 1.8A_SIP

R1139

12

Do Not Stuff

+V1.8A_SIP

R1138

0R3J-0-U-G P

+VCCPGPPF

12

2

R1119

1 2

0R3J-0-U-G P

12

C1184

DY

Do Not Stuff

R1120

1 2

0R3J-0-U-G P

Iris SKL UMA

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

CPU_(Power CAP2)

Iris2 SKL-U

1

11 105Tuesday, May 26, 2015

A00

CAP TBD

+V3.3A_SIP

+V1.8A_SIP

Do Not Stuff

VCC_CORE

12

C1103

C1101

C1102

SC1U10V2KX-1GP

A A

U-line 23e 28W IccMax current-10ms max = 34 A

SC1U10V2KX-1GP

5

12

C1116

C1117

SC1U10V2KX-1GP

1U 0402 x 5

SC1U10V2KX-1GP

4

5

4

3

2

1

Main Func = DDR SODIMM

SA0_DIMA SA1_DIMA

12

R1202

Do Not Stuff

DM1

M_A_A[15:0][5]

D D

M_A_BS2[5]

M_A_BS0[5] M_A_BS1[5]

M_A_DQ[63:0][5]

M_A_DQ[0:7]

M_A_DQ[8:15]

12

C1201

Layout Note:

Place these caps close to VREF_CA

M_VREF_CA_D IMMA

12

C1218

C1202

M_A_DQ[16:23]

SCD1U16V2KX-3GP

C C

12

C1204

DY

SCD1U16V2KX-3GP

Layout Note:

Place these caps close to VTT1 and VTT2.

SCD1U16V2KX-3GP

Layout Note:

Place these caps close to VREF_DQ

M_VREF_DQ_D IMMA

12

C1206

C1205

Do Not Stuff

SCD1U16V2KX-3GP

M_A_DQ[24:31]

M_A_DQ[32:39]

M_A_DQ[40:47]

M_A_DQ[48:55]

M_A_DQ[56:63]

M_A_DQS_DN[7: 0][5]

B B

M_A_DQS_DP[7:0][5]

M_A_DIMA_ODT0[5] M_A_DIMA_ODT1[5]

M_VREF_CA_D IMMA

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

DDR3_DR AMRST#[5,13]

M_VREF_DQ_D IMMA

M_A_DIMA_ODT0 M_A_DIMA_ODT1

12

DY

0D675V_S0

ED1217

ED1217 Do Not Stuff

Do Not Stuff

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ3 M_A_DQ1 M_A_DQ4 M_A_DQ7 M_A_DQ2 M_A_DQ6 M_A_DQ0 M_A_DQ5 M_A_DQ9 M_A_DQ13 M_A_DQ14 M_A_DQ10 M_A_DQ8 M_A_DQ12 M_A_DQ15 M_A_DQ11 M_A_DQ20 M_A_DQ16 M_A_DQ23 M_A_DQ19 M_A_DQ21 M_A_DQ17 M_A_DQ22 M_A_DQ18 M_A_DQ25 M_A_DQ28 M_A_DQ26 M_A_DQ30 M_A_DQ24 M_A_DQ29 M_A_DQ31 M_A_DQ27 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ46 M_A_DQ47 M_A_DQ44 M_A_DQ45 M_A_DQ43 M_A_DQ42 M_A_DQ53 M_A_DQ49 M_A_DQ55 M_A_DQ54 M_A_DQ52 M_A_DQ48 M_A_DQ51 M_A_DQ50 M_A_DQ61 M_A_DQ56 M_A_DQ62 M_A_DQ63 M_A_DQ60 M_A_DQ57 M_A_DQ58 M_A_DQ59

M_A_DQS_DN0 M_A_DQS_DN1 M_A_DQS_DN2 M_A_DQS_DN3 M_A_DQS_DN4 M_A_DQS_DN5 M_A_DQS_DN6 M_A_DQS_DN7

M_A_DQS_DP0 M_A_DQS_DP1 M_A_DQS_DP2 M_A_DQS_DP3 M_A_DQS_DP4 M_A_DQS_DP5 M_A_DQS_DP6 M_A_DQS_DP7

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P- 108-GP-U

62.10017.X41

RAS#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NP1

NP2

110 113

WE#

115

114 121

73 74

101

CK0

103

102

CK1

104

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

199

SA0_DIMA

197

SA0

SA1_DIMA

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D35V_S3

M_A_RAS# [5] M_A_WE# [5] M_A_CAS# [5]

M_A_CS#0 [5] M_A_CS#1 [5]

M_A_CKE0 [5] M_A_CKE1 [5]

M_A_CLK0 [5] M_A_CLK#0 [5]

M_A_CLK1 [5] M_A_CLK#1 [5]

PCH_SMBDAT A [13,18,56,6 5,99] PCH_SMBCLK [13,18,56,65,99]

3D3V_S0

DY

12

C1203

Do Not Stuff

Layout Note:

Place these Caps near DIMM1.

0D675V_S0

Do Not Stuff

1D35V_S3

12

C1214

C1215

SC1U10V2KX-1GP

Note: SA0 DIM0 = 0, SA1_DIM0 = 0

12

SO-DIMMA SPD Address is 0xA0

R1201

Do Not Stuff

SO-DIMMA TS Address is 0x30

12

TC1201

Do Not Stuff

C1212

SC1U10V2KX-1GP

12

C1213

SC1U10V2KX-1GP

C1220

SCD1U16V2KX-3GP

1U 0402 x 3

12

C1207

C1208

SC10U6D3V3MX-GP

12

C1221

SCD1U16V2KX-3GP

12

DY

12

C1216

SC1U10V2KX-1GP

Place these Caps near DIMM1.

10U 0603 x 3

12

C1209

SC10U6D3V3MX-GP

12

C1222

SCD1U16V2KX-3GP

1U 0402 x 2

0.1U 0402 x 5

12

C1211

C1210

SCD1U16V2KX-3GP

close to dimm

A A

Iris SKL UMA

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Wednesd ay, September 09, 2015

Wednesd ay, September 09, 2015 Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

DDR3-SODIMM1

Iris2 SKL-U

1

12 105

A00

5

4

3

2

1

Main Func = DDR SODIMM

DM2

M_B_A[15:0][5]

D D

M_B_BS2[5]

M_B_BS0[5] M_B_BS1[5]

M_B_DQ[63:0][5]

M_B_DQ[8:15]

M_B_DQ[0:7]

M_B_DQ[16:23]

M_B_DQ[24:31]

M_B_DQ[32:39]

M_B_DQ[40:47]

DM2

SCD1U16V2KX-3GP

Do Not Stuff

DM2

12

C1309

12

C1310

Layout Note:

Place these caps close to VREF_CA

SCD1U16V2KX-3GP

Layout Note:

Place these caps close to VREF_DQ

SCD1U16V2KX-3GP

M_VREF_CA_D IMMB

12

C1306

C1308

DM2

SCD1U16V2KX-3GP

M_VREF_DQ_D IMMB

C C

DM2

12

C1302

DY

C1305

SCD1U16V2KX-3GP

M_B_DQ[48:55]

M_B_DQ[56:63]

M_B_DQS_DN[7: 0][5]

B B

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

M_B_DQS_DP[7:0][5]

M_B_DIMB_ODT0[5] M_B_DIMB_ODT1[5]

M_VREF_CA_D IMMB M_VREF_DQ_D IMMB

DDR3_DR AMRST#[5,12]

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ10 M_B_DQ11 M_B_DQ13 M_B_DQ15 M_B_DQ9 M_B_DQ14 M_B_DQ12 M_B_DQ8 M_B_DQ4 M_B_DQ0 M_B_DQ2 M_B_DQ3 M_B_DQ1 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ31 M_B_DQ25 M_B_DQ29 M_B_DQ27 M_B_DQ24 M_B_DQ28 M_B_DQ26 M_B_DQ30 M_B_DQ33 M_B_DQ36 M_B_DQ34 M_B_DQ39 M_B_DQ37 M_B_DQ32 M_B_DQ35 M_B_DQ38 M_B_DQ45 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ40 M_B_DQ44 M_B_DQ46 M_B_DQ47 M_B_DQ51 M_B_DQ49 M_B_DQ55 M_B_DQ48 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ50 M_B_DQ58 M_B_DQ56 M_B_DQ60 M_B_DQ59 M_B_DQ57 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS_DN1 M_B_DQS_DN0 M_B_DQS_DN2 M_B_DQS_DN3 M_B_DQS_DN4 M_B_DQS_DN5 M_B_DQS_DN6 M_B_DQS_DN7

M_B_DQS_DP1 M_B_DQS_DP0 M_B_DQS_DP2 M_B_DQS_DP3 M_B_DQS_DP4 M_B_DQS_DP5 M_B_DQS_DP6 M_B_DQS_DP7

0D675V_S0

12

ED1301

DY

Do Not Stuff

close to dimm

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P- 259-GP

62.10024.S11

62.10024.S11 DM2

DM2

RAS#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NP1

NP2

110 113

WE#

115

114 121

73 74

101

CK0

103

102

CK1

104

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

199

SA0_DIMB

197

SA0

SA1_DIMB

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D35V_S3

M_B_RAS# [5] M_B_WE# [5] M_B_CAS# [5]

M_B_CS#0 [5] M_B_CS#1 [5]

M_B_CKE0 [5] M_B_CKE1 [5]

M_B_CLK0 [5] M_B_CLK#0 [5]

M_B_CLK1 [5] M_B_CLK#1 [5]

PCH_SMBDAT A [1 2,18,56,65,99] PCH_SMBCLK [12,18,56,65,99]

3D3V_S0

12

DY

C1311

C1311 Do Not Stuff

Do Not Stuff

Layout Note:

Place these Caps near DIMM2.

0D675V_S0

12

C1307

DM2

1D35V_S3

DM2

SC1U10V2KX-1GP

12

SA1_DIMB

SA0_DIMB

C1304

SC1U10V2KX-1GP

DM2

12

3D3V_S0

DM2

12

C1303

12

R1302

R1302 10KR2J-3-GP

10KR2J-3-GP

12

R1301

Do Not Stuff

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

12

DM2

C1317

C1318

DM2

SC10U6D3V3MX-GP

12

C1321

C1322

DM2

SC1U10V2KX-1GP

12

C1315

C1314

DM2

SCD1U16V2KX-3GP

1U 0402 x 3

SC1U10V2KX-1GP

DM2

SC10U6D3V3MX-GP

12

10U 0603 x 3

12

C1323

SC10U6D3V3MX-GP

C1316

DM2

SCD1U16V2KX-3GP

1U 0402 x 2

0.1U 0402 x 5

12

C1312

C1313

DM2

SCD1U16V2KX-3GP

Place these Caps near DIMM2.

A A

Iris SKL UMA

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

DDR3-SODIMM2

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Wednesd ay, September 09, 2015

Wednesd ay, September 09, 2015 Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

Iris2 SKL-U

1

13 105

A00

5

D D

4

3

2

1

C C

(Blanking)

B B

Iris SKL UMA

Wistron Corporation

A A

Title

(Reserved)_SODIMM _SODIMM4

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Iris2 SKL-U

14 105Tuesday, May 26, 2015

1

A00

5

Main Func = PCH

4

3

2

1

CPU1I

SKYLAKE_ULT

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

D D

C C

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKYLAKE-GP

071.SKYLA.000U

SKYLAKE_ULT

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

9 OF 20

CSI2_CLKN0

CSI2_CLKP0

CSI2_CLKN1

CSI2_CLKP1

CSI2_CLKN2

CSI2_CLKP2

CSI2_CLKN3

CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

C37 D37 C32 D32 C29

DC resistance < 0.5ohm.

D29 B26 A26

CSI2_COMP

E13

WIFI_RF_ EN

B7

AP2 AP1 AP3

GPP_F: VCCPGPPF = 1.8V Only

AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

EMMC_RC OMP

AT1

1 2

R1501

1 2

WIFI_RF_ EN [61]

100R2F-L 1-GP-U

R1502

200R2F-L -GP

WIFI_RF_ EN

R1503

1 2

10KR2J-3 -GP

3D3V_S0

[#545659 Rev0.7 ]

B B

A A

5

4

3

2

Iris SKL UMA

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(CS-2/EMMC)

Iris2 SKL-U

15 10 5Wednesd ay, September 09, 20 15

1

A00

Main Func = PCH

#543016: 220 nF nominal capacitors are recommended for Gen 3. 100 nF nominal capacitors are recommended for Gen 2.

GPU

D D

WLAN

LAN

HDD1

ODD

Layout Note:

3D3V_S0

C C

PCIE Table

Port

1

2

3

4

5(L0~L3)

6(L3)

6(L2)

6(L0~L1)

5

PEG_RX_CPU_N0[76] PEG_RX_CPU_P0[76] PEG_TX_GPU_N0[76] PEG_TX_GPU_P0[76]

PEG_RX_CPU_N1[76] PEG_RX_CPU_P1[76] PEG_TX_GPU_N1[76] PEG_TX_GPU_P1[76]

PEG_RX_CPU_N2[76] PEG_RX_CPU_P2[76] PEG_TX_GPU_N2[76] PEG_TX_GPU_P2[76]

PEG_RX_CPU_N3[76] PEG_RX_CPU_P3[76] PEG_TX_GPU_N3[76] PEG_TX_GPU_P3[76]

PCIE_RX_CPU_N5[61] PCIE_RX_CPU_P5[61] PCIE_TX_CON_N5[61] PCIE_TX_CON_P5[61]

PCIE_RX_CPU_N6[31] PCIE_RX_CPU_P6[31] PCIE_TX_CON_N6[31] PCIE_TX_CON_P6[31]

SATA_RX_CPU_N0[60] SATA_RX_CPU_P0[60] SATA_TX_CPU_N0[60] SATA_TX_CPU_P0[60]

SATA_RX_CPU_N1[60]

SATA_RX_CPU_P1[60]

SATA_TX_CPU_N1[60]

SATA_TX_CPU_P1[60]

1. Trace Width: 4 mils min (b reakout) 12-15 mils (trace) Note: Must maintain low DC re sistance routing (<0.1 ohm).

2. Isolation Spacing: At leas t 12 mils to any adjacent high speed I/O.

R1604

XDP_PRDY#[99] XDP_PREQ#[99]

PIRQA#

R160710KR2J-3-GP R160710KR2J-3-GP

12

Device

N/A

WLAN

LAN

GPU

HDD

ODD SATA1

N/A

C1606

C1606 C1605

C1605

C1608

C1608 C1607

C1607

C1610

C1610 C1609

C1609

C1612

C1612 C1611

C1611

C1601

C1601 C1602

C1602

C1603

C1603 C1604

C1604

1 2

100R2F-L1-GP-U

Share BUS

USB3.0_3

USB3.0_4

SATA0

1 2 1 2

Do Not Stuff

OPS

OPS OPS

OPS

Do Not Stuff

OPS

OPS OPS

OPS

Do Not Stuff

OPS

OPS OPS

OPS

Do Not Stuff

OPS

OPS OPS

OPS

Do Not Stuff

SCD1U16V2KX-3GP

PEG_TX_CPU_N0 PEG_TX_CPU_P0

PEG_TX_CPU_N1 PEG_TX_CPU_P1

PEG_TX_CPU_N2 PEG_TX_CPU_P2

PEG_TX_CPU_N3 PEG_TX_CPU_P3

PCIE_TX_CPU_N5 PCIE_TX_CPU_P5

PCIE_TX_CPU_N6 PCIE_TX_CPU_P6

PCIE_RCOMPN PCIE_RCOMPP

PIRQA#

USB 2.0 Table

Pair

Device

0

USB3.0 port1

1

USB2.0 Port2 (Debug Port/IOBD)

USB2.0 Port3 (IOBD)

2

3

4

CAMERA

5

Card Reader

6

Touch Panel

WLAN

7

CPU1H

PCIE/USB3/SATA

H13

PCIE1_ RXN/USB3_ 5_RXN

G13

PCIE1_ RXP/USB3 _5_RX P

B17

PCIE1_ TXN/USB3_ 5_TXN

A17

PCIE1_ TXP/USB3 _5_TX P

G11

PCIE2_ RXN/USB3_ 6_RXN

F11

PCIE2_ RXP/USB3 _6_RX P

D16

PCIE2_ TXN/USB3_ 6_TXN

C16

PCIE2_ TXP/USB3 _6_TX P

H16

PCIE3_ RXN

G16

PCIE3_ RXP

D17

PCIE3_ TXN

C17

PCIE3_ TXP

G15

PCIE4_ RXN

F15

PCIE4_ RXP

B19

PCIE4_ TXN

A19

PCIE4_ TXP

F16

PCIE5_ RXN

E16

PCIE5_ RXP

C19

PCIE5_ TXN

D19

PCIE5_ TXP

G18

PCIE6_ RXN

F18

PCIE6_ RXP

D20

PCIE6_ TXN

C20

PCIE6_ TXP

F20

PCIE7_ RXN/SATA 0_RXN

E20

PCIE7_ RXP/SAT A0_RX P

B21

PCIE7_ TXN/SATA 0_TXN

A21

PCIE7_ TXP/SAT A0_TX P

G21

PCIE8_ RXN/SATA 1A_RX N

F21

PCIE8_ RXP/SAT A1A_R XP

D21

PCIE8_ TXN/SATA 1A_TX N

C21

PCIE8_ TXP/SAT A1A_T XP

E22

PCIE9_ RXN

E23

PCIE9_ RXP

B23

PCIE9_ TXN

A23

PCIE9_ TXP

F25

PCIE10 _RXN

E25

PCIE10 _RXP

D23

PCIE10 _TXN

C23

PCIE10 _TXP

F5

PCIE_R COMPN

E5

PCIE_R COMPP

D56

PROC_P RDY#

D61

PROC_P REQ#

BB11

GPP_A7 /PIRQA#

E28

PCIE11 _RXN/SAT A1B_R XN

E27

PCIE11 _RXP/SA TA1B_ RXP

D24

PCIE11 _TXN/SAT A1B_T XN

C24

PCIE11 _TXP/SA TA1B_ TXP

E30

PCIE12 _RXN/SAT A2_RX N

F30

PCIE12 _RXP/SA TA2_R XP

A25

PCIE12 _TXN/SAT A2_TX N

B25

PCIE12 _TXP/SA TA2_T XP

SKYLAKE-GP

071.SKYLA.000U

SKYLAKE_ULT

X

4

SSIC / USB3

USB3_2_ RXN/SSIC _1_RX N USB3_2_ RXP/SSI C_1_R XP USB3_2_ TXN/SSIC _1_TX N USB3_2_ TXP/SSI C_1_T XP

USB3_3_ RXN/SSIC _2_RX N USB3_3_ RXP/SSI C_2_R XP USB3_3_ TXN/SSIC _2_TX N USB3_3_ TXP/SSI C_2_T XP

USB2

USB2_VB USSENSE

GPP_E9 /USB2_OC 0# GPP_E1 0/USB2_O C1# GPP_E1 1/USB2_O C2# GPP_E1 2/USB2_O C3#

GPP_E4 /DEVSLP 0 GPP_E5 /DEVSLP 1 GPP_E6 /DEVSLP 2

GPP_E0 /SATAXP CIE0/S ATAGP0 GPP_E1 /SATAXP CIE1/S ATAGP1 GPP_E2 /SATAXP CIE2/S ATAGP2

GPP_E8 /SATALE D#

8 OF 20

H8

USB3_1_ RXN

G8

USB3_1_ RXP

C13

USB3_1_ TXN

D13

USB3_1_ TXP

J6 H6 B13 A13

J10 H10 B15 A15

E10

USB3_4_ RXN

F10

USB3_4_ RXP

C15

USB3_4_ TXN

D15

USB3_4_ TXP

AB9

USB2N_1

AB10

USB2P_1

AD6

USB2N_2

AD7

USB2P_2

AH3

USB2N_3

AJ3

USB2P_3

USB_CPU_PN3

AD9

USB2N_4

USB_CPU_PP3

AD10

USB2P_4

AJ1

USB2N_5

AJ2

USB2P_5

AF6

USB2N_6

AF7

USB2P_6

AH1

USB2N_7

AH2

USB2P_7

AF8

USB2N_8

AF9

USB2P_8

AG1

USB2N_9

AG2

USB2P_9

DC resistance < 0.5ohm.

AH7

USB2N_10

AH8

USB2P_1 0

USBCOMP

AB6

USB2_CO MP

AG3

USB2_ID

AG4

A9

USB_OC1#

C9

USB_OC2#

D9

USB_OC3#

B9

J1 J2 J3

GPP_E0/SATAXPCIE0/SATAGP0

H2 H3

GPP_E2/SATAXPCIE2/SATAGP2

G4

H1

(#543016) Unused SATAGP[2:0]/ GPP_E[2:0] pins must be termi nated to either 3.3 V rail or GND using 8.2 KΩ to 10 KΩ on the motherboard. Do not use both pull-up and p ull-down. Either pull-up or p ull-down is acceptable.

USB_CPU_PN0 [36] USB_CPU_PP0 [36]

USB_CPU_PN1 [37] USB_CPU_PP1 [37]

USB_CPU_PN2 [37] USB_CPU_PP2 [37]

1

TP1601 Do Not StuffTP1601 Do Not Stuff

1

TP1602 Do Not StuffTP1602 Do Not Stuff

USB_CPU_PN4 [55] USB_CPU_PP4 [55]

USB_CPU_PN5 [33] USB_CPU_PP5 [33]

USB_CPU_PN6 [55] USB_CPU_PP6 [55]

USB_CPU_PN7 [61] USB_CPU_PP7 [61]

R1603 113R2F-GPR1603 113R2F-GP

1 2

USB_OC0# [35]

USB_OC3# [24]

HDD_DEVSLP [60]

SIO_EXT_SCI#_R [24]

SATA_ODD_DA# [60]

SATA_LED#_R [24,64]

GPP_E0/SATAXPCIE0/SATAGP0

GPP_E2/SATAXPCIE2/SATAGP2

USB30_RX_CPU_N1 [36] USB30_RX_CPU_P1 [36] USB30_TX_CPU_N1 [36] USB30_TX_CPU_P1 [36]

USB1 (USB3.0 Port1)

USB1 (USB2.0 port1)

USB2 (IO BD/ USB2.0 Port2)

USB3 (IO BD/USB2.0 Port3)

CAMERA (USB2.0 Port5)

Card Reader (USB2.0 Port6)

Touch Panel (USB2.0 Port7)

WLAN (USB2.0 Port8)

Unused SATA[3:0]GP pins must be terminated to either

3.3V rail or GND using 8.2K to 10K on the motherboard. Either pull-up or pull-down is acceptable.

SATA_ODD_PRSNT#

(#543016) When used as DEVSLP , no external pull-up or pull -down termination required from SAT A Host DEVSLP.

SATA_ODD_PRSNT# [60]

1 2

3D3V_S0

R1601

Do Not Stuff

DY

R1602

Do Not Stuff

DY

3

(#545659) The xHCI controller supports USB Debug port on a ll USB3.0 capable ports.

3D3V_S0

R1608

SATA_ODD_DA#

USB_OC2# USB_OC3# USB_OC0# USB_OC1#

ZPODD

Do Not Stuff

R1609 Do Not Stuff

1 2

ODD / ZPODD

RN802

8 7

SRN10KJ-6-GP

12

3D3V_S0

R1610

1 2 3456

3D3V_S5_PCH

SIO_EXT_SCI#_R

12

10KR2J-3-GP

SATA_LED#_R

(#543611) The SATALED# signal is open-c ollector and requires a weak external pull-up (8.2 kΩ to 10 kΩ) to Vcc3_3.

3D3V_S0

R1606

10KR2J-3-GP

2

3D3V_S0

12

1

#545659 (SKL_PCH_U_Y_EDS Rev0 .7)

B B

A A

Iris SKL UMA

Title

Size Document Number Rev

A1

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(PCIE/SATA/USB)

Iris2 SKL-U

16 105Wednesday, September 09, 2015

A00

5

4

3

2

1

Main Func = PCH

3D3V_S5

R1709

1 2

10KR2J-3-GP

+VCCPDSW _3P3

R1703

1 2

1KR2J-1-GP

R1723

D D

C C

B B

A A

1 2

10KR2J-3-GP

RTC_AUX_S5

R1730

330KR2J-L1-GP

1 2

R1733 10KR2J-3-GPR1733 10KR2J-3-GP R1732 10KR2J-3-GPR1732 10KR2J-3-GP

R1717 Do Not Stuff

SUSACK#[24]

ME_SUS_PW R_ACK[2 4]

3D3V_AUX_S5

1 2 1 2

AC_PRESENT

PCH_WA KE#

PCH_BATLOW #

#544669 (CRB): 330k.

SM_INTRUDER #

PM_RSMRST# PM_PCH_PW ROK

12

DY

SYS_PWROK

+VCCMPHYGTAON_1P0

SKL: 1.0V

+VCCMPHYGTAON_1P0(ICCMAX.=3.5A )

NON DS3

R1708

1 2

0R2J-2-GP

RN1702

2 3

DS3

1

Do Not Stuff

R1727

100KR2J-1-GP

1 2

NON DS3

6

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

5

+VCCMPHYGTA ON_1P0_LS_SIP1D0V_S5

4

Q1701

2N7002KDW -GP

1 2

R1726

R1726 10KR2J-3-GP

10KR2J-3-GP

3V_5V_POK#

R1724

Do Not Stuff

R1735

Do Not Stuff

12

C1704

C1704 SC10U10V5KX-2G P

SC10U10V5KX-2G P

SUSACK#_RME_SUS_PW R_ACK_R

SUSACK#_R ME_SUS_PW R_ACK_R

PM_RSMRST#

3V_5V_POK_C

2345

1

#544669 Rev0.52 CRB: No PL resistor on THERMTRIP#.

H_CPUPW RGD

DS3 BOM Option

PCH_DPW ROK

1KR2J-1-GP

1KR2J-1-GP R1702

R1702

1 2

R1728

1 2

NON DS3

0R2J-2-GP

DS3

R1729

1 2

Do Not Stuff

+V3.3A_SIP

3D3V_S5

Layout note: 3 PAD SHARING

12

R405

R405 Do Not Stuff

Do Not Stuff

DY

EC_WAKE#[24]

R1718 Do Not Stuff

1 2

DS3

EC1711

SIO_SLP_SUS#

DS3

1 2

Do Not Stuff

R1725

R1725 Do Not Stuff

Do Not Stuff

1 2

12

DY

Do Not Stuff

R1712

DY

R1711

R1710

+VCCPDSW _3P3

Do Not Stuff

XDP_DBRESE T#[99]

H_THERMT RIP_EN[40]

SYS_PWROK[24] RESET_OUT #[24,26,40]

ME_SUS_PW R_ACK_R[20]

+VCCPDSW _3P3

GPD2/LAN_W AKE#

1 2

Do Not Stuff

2015/04/20 modify

3V_5V_POK [40,45,53,54]

EC1712

12

DY

Do Not Stuff

4

+VCCPRIM_3P3

12

R1701

R1701 3KR2J-2-GP

3KR2J-2-GP

DY

R411Do Not StuffDYR411Do Not Stuff

H_VCCST_PW RGD_R

(PDG#543016) WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns.

SIO_SLP_S3#[24,27,40,51,52,54]

ALL_SYS_PWRG D[24,40]

PCH_RSMRS T# [24]

1 2

R1706 Do Not StuffR1706 Do Not Stuff

1 2

R1704 0R2J- 2-GP

1 2

NON DS3

DY for OBFF disable

R1707 10KR2J -3-GPR1707 10KR2J -3-GP

1 2

U1702

1

NC#1

2

A

GND3Y

74LVC1G07GW -GP

73.01G07.0HG

PCH strap pin:

DSWVRMEN

This signal has no integrated pull-up/pull-down.

PM_RSMRST#[99]

60D4R2F-GP

60D4R2F-GP R1734

R1734

5

VCC

4

DY

At which pinout for SKL?

On Die DSW VR Enable

Low = Disable High = Enable (default)

*

PLT_RST#[24,31,40,55,61,68,76]

R1715

Do Not Stuff

PCH_PLTRST # XDP_DBRESE T#

H_CPUPW RGD H_VCCST_PW RGD

SYS_PWROK PM_PCH_PW ROK PCH_DPW ROKPM_RSMRST#

ME_SUS_PWR_ACK_R SUSACK#_R

PCH_WA KE# GPD2/LAN_W AKE#

3D3V_S5

Do Not Stuff

C1703

12

DY

U1701

1

2

74LVC1G07GW -GP

73.01G07.0HG

1 2

R1716

R1716 Do Not Stuff

Do Not Stuff

12

EC1709

EC1709 Do Not Stuff

Do Not Stuff

3

R1713

1 2

12

Do Not Stuff

12

C1701

C1701 Do Not Stuff

Do Not Stuff

DY

CPU1K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/USB2_WAKEOUT#

SKYLAKE-GP

071.SKYLA.000U

3D3V_S5

SCD1U16V2KX-3GP

C1702

12

5

NC#1

VCC

A

4

GND3Y

DY

12

R1719

R1719 Do Not Stuff

Do Not Stuff

DY

12

DY

EC1702

EC1706

Do Not Stuff

PCH_PLTRST #

SYSTEM POWER MANAGEMENT

+VCCSTG

2015/02/10 modify

12

R1722

R1722 100KR2J-1-GP

100KR2J-1-GP

SKYLAKE_ULT

GPP_B12/SLP_S0#

GPD9/SLP_WLAN#

GPD1/ACPRESENT

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

Dis-wire with XDP_PM_RSMRST_PW RGD_XDP

H_VCCST_PW RGD_R

12

EC1708

EC1708 SCD01U50V2KX- 1GP

SCD01U50V2KX- 1GP

XDP_DBRESE T#

SYS_PWROK PLT_RST# RESET_OUT # 3V_5V_POK

12

DY

EC1703

12

DY

EC1704

Do Not Stuff

12

DY

EC1705

Do Not Stuff

11 OF 20

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

[#543016 Rev0.7] EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k pull-down that is active during the early portion of the power up sequence

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

SIO_SLP_S5#

SLP_LAN# GPD9/SLP_W LAN# SIO_SLP_A#

AC_PRESENT PCH_BATLOW #

PME# SM_INTRUDER #

EXT_PWR _GATE# GPP_B2/VRALER T#

3D3V_AUX_S5

1

1 1 1

R1737

1 2

NON DS3

100KR2J-1-GP

1

TP1703 Do Not S tuffTP1703 Do Not Stuff

TP1704 Do Not S tuffTP1704 Do Not Stuff TP1705 Do Not S tuffTP1705 Do Not Stuff TP1706 Do Not S tuffTP1706 Do Not Stuff

TP1707 Do Not StuffTP1707 Do Not Stuff

TP1708 Do Not StuffTP1708 Do Not Stuff

PM_RSMRST#_M

SIO_SLP_S0# [40] SIO_SLP_S3# [24,27,40,51,52,54]

SIO_SLP_S4# [24,40,51]

SIO_SLP_SUS# [24,40,53,54 ]

SIO_PWRBTN # [24,99]

Q1702

NON DS3

6

2N7002KDW -GP

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

EXT_PWR _GATE#

20KR2J-L2-GP

D1702

RB751V-40H-G P

R1720

1 2

NON DS3

0R2J-2-GP

20KR2J-L2-GP

KA

AC_PRESENT

BATLOW#: Pull-up required even if not implemented.

83.R2004.G8F

PM_RSMRST#_R PM_RSMRST#

2345

1

Modify on 20150204

VCCST_PWRGD / HWM201:

#543016 Rev0.7

1. VCCST_PWRGD is only 1.0 V tolerant.

2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST

Iris SKL UMA

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

CPU_(POWER MANAGEMENT)

Size Document Num ber Rev

A2

Date: Sheet of

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

Iris2 SKL-U

1

3D3V_S5_PCH

R1731

12

AC_PRESENT

EC1707

12

DY

Do Not Stuff

PWR_CH G_ACOK [24,44]

17 105Wednesday, Septemb er 09, 2015

A00

Main Func = PCH

D D

PCH Prim

3D3V_S5_PCH

12

R1834

R1834 1KR2J-1-GP

1KR2J-1-GP

SPI_WP_CPU

3D3V_S0

R2021

1 2

10KR2J-3-GP

R2032

1 2

10KR2J-3-GP

SERIRQ PH: PDG: 8.2k CRB: 10k

C C

RCIN#: Frequency to Avoid: 33 MHz

3D3V_S0

B B

A A

5

PCH Prim

3D3V_S5_PCH

12

R1835

R1835 1KR2J-1-GP

1KR2J-1-GP

12

R1836

R1836 Do Not Stuff

Do Not Stuff

DY

SIO_RCIN#

SERIRQ

SRN10KJ-6-G P

CLKREQ_PCIE#5

1

8

CLKREQ_PEG#0

2

7

CLKREQ_PCIE#1

3

6

4 5

RN1812

CLKREQ_PCIE#3

1

8

CLKREQ_PCIE#4

2

7

CLKREQ_PCIE#2

3

6

4 5

RN1813

SRN10KJ-6-G P

Swap on 2014/12/24

GPU

WLAN

LAN

5

PCH strap pin:

eSPI or LPC

SML0ALERT# / GPP_C5

This signal has a weak internal pull-down.

SPI0_MOSI_XDP[99]

XDP_SPI0_IO2[99]

SPI_HOLD_CPU

SPI_CLK_ROM[24,25]

SPI_SO_ROM[ 24,25]

SPI_SI_ROM[2 4,25] SPI_WP_ROM[2 5] SPI_HOLD_ROM[25]

SPI_CS_ROM_N0[24,25] SPI_CS_ROM_N1[25]

CL_CLK[61] CL_DATA[61]

CL_RST#[61]

SIO_RCIN#[24]

SERIRQ[24]

PEG_CLK_CPU #[76] PEG_CLK_CPU[76]

CLKREQ_PEG#0[79]

PEG_CLK1_CPU #[61] PEG_CLK1_CPU[61]

CLKREQ_PCIE#1[61]

PEG_CLK2_CPU #[31] PEG_CLK2_CPU[31]

CLKREQ_PCIE#2[31]

Sampled at rising edge of RSMRST#

This signal has a weak internal pull-down. 0 = LPC Is selected for EC. 1 = eSPI Is selected for EC.

PLACE WITHIN 1.1 INCH OF PCH

1 2

Resister value will check later

1 2 1 2 1 2 1 2 1 2 1 2 1 2

Do Not Stuff

12

EC1805

DY

R1826

XDP

R1827

XDP

Do Not Stuff

R180610R2F- L-GP R180610R2F-L-GP R180710R2F- L-GP R180710R2F-L-GP R180810R2F- L-GP R180810R2F-L-GP R180910R2F- L-GP R180910R2F-L-GP R181110R2F- L-GP R181110R2F-L-GP R1812Do Not S tuff R1812Do N ot Stuff R1816Do Not S tuff R1816Do N ot Stuff

4

PCH Prim

3D3V_S5_PCH

12

R1822

DY

Do Not Stuff

GPP_C5/SML0ALER T#

(#543016)Optional, can be left as OPEN/No-Connect.

SPI_SI_CPU

SPI_WP_CPU

SPI_CLK_CPU SPI_SO_CPU SPI_SI_CPU SPI_WP_CPU SPI_HOLD_CPU SPI_CS_CPU_N0 SPI_CS_CPU_N1

CPU_D1_TP

TP1801Do N ot Stuff TP1801Do Not Stuff

1

CPU_D2_TP

TP1802Do N ot Stuff TP1802Do Not Stuff

1

CPU_D3_TP

TP1803Do N ot Stuff TP1803Do Not Stuff

1

CPU_D4_TP

TP1804Do N ot Stuff TP1804Do Not Stuff

1

CPU_D5_TP

TP1805Do N ot Stuff TP1805Do Not Stuff

1

CPU_D6_TP

TP1806Do N ot Stuff TP1806Do Not Stuff

1

CLKREQ_PEG#0

CLKREQ_PCIE#1

CLKREQ_PCIE#3

CLKREQ_PCIE#4

CLKREQ_PCIE#5

4

AW13

DY

AV2

AW3

AV3

AW2

AU4 AU3 AU2 AU1

M2 M3

J4 V1 V2 M1

G3 G2 G1

AY11

12

CPU1E

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKYLAKE-GP

R1823

R1823 Do Not Stuff

Do Not Stuff

SPI - FLASH

Strap

SPI - TOUCH

C LINK

071.SKYLA.000U

CPU1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKYLAKE-GP

071.SKYLA.000U

PCH strap pin:

BOOT HALT

SKYLAKE_ULT

CLOCK SIGNALS

SKYLAKE_ULT

LPC

0 = ENABLED 1 = DISABLED WEAK INTERNAL PU

SMBUS, SMLINK

GPP_A14/SUS_STAT#/ESPI_RESET#

SPI0_MOSI

This signal has a weak internal pull-up.

3

LPC_LAD[3..0][24,68]

5 OF 20

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

Strap

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

20140820 DAIVD

SC5P50V2CN- 2GP

10 OF 20

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

F43 E43

BA17

E37 E35

E42

AM18 AM20

AN18 AM16

3

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

SPI_SI_CPU

MEM_SMBCLK

R7

MEM_SMBDATA

R8

GPP_C2/SMBALER T#

R10

SML0_SMBCLK

R9

SML0_SMBDATA

W2

GPP_C5/SML0ALER T#

W1

SML1_SMBCLK

W3

SML1_SMBDATA

V3

GPP_B23/SML1ALERT #

AM7

LPC_LAD0_R

AY13

LPC_LAD1_R

BA13

LPC_LAD2_R

BB13

LPC_LAD3_R

AY12

LPC_LFRAME#_R

BA12

SUS_STAT#/LPC PD#

BA11

PCI_CLK_LPC0

AW9

PCI_CLK_LPC1

AY9

CLKRUN#_R

AW11

PCI_CLK_LPC0

PCI_CLK_LPC0 PCI_CLK_LPC1

C1804

SUSCLK_R

R1813 Do Not StuffR1813 Do Not Stuff

XTAL24_IN XTAL24_OUT

XCLK_BIASREF

RTC_X1 RTC_X2

SRTC_RST # RTC_RST#

PCH Prim

3D3V_S5_PCH

12

R1824

DY

Do Not Stuff

12

R1825

DY

Do Not Stuff

LPC_LAD[3..0]

LPC_LAD2 LPC_LAD1 LPC_LAD3 LPC_LAD0

R1819 Do Not StuffR1819 Do Not Stuff

1 2

R1828 Do Not Stuff

R1804 Do Not Stuff

R1804 Do Not Stuff R1805 33R2J-2- GPR1805 33R2J-2- GP

1 2

R1815 10M R2J-L-GPR 1815 10MR2J- L-GP

X1802

12

2 3

XTAL-32D768KH Z-68-GP

82.30001.G01

2rd = 82.30001.G11

1 2

R1803

1 2

2K7R2F-GP

Intel recommend: 2.71k ohm 5%

RTCRST_O N[24]

RN1806

8 7 6

SRN0J-7-GP -U

SML1_SMBCLK [24,26,79] SML1_SMBDATA [24,26,79]

20140820 DAIVD

R1801

12

Do Not Stuff

CRT

1 2

LPC

1 2 1 2

DY

41

12

+VCCF24NS_ 1P0_L

12

R1902

10KR2J-3-GP

Do Not Stuff

12

EC1808

DY

2

LPC_LAD2_R

1

LPC_LAD1_R

2

LPC_LAD3_R

3

LPC_LAD0_R

45

LPC_LFRAME# [24,68]

CLKRUN# [24]

EC1801

Do Not StuffDYEC1801

Do Not Stuff

EC1802

12

DY

RTC_X1

RTC_X2

C1803

C1803 SC5P50V2CN- 2GP

SC5P50V2CN- 2GP

PCIE_CLK_XDP_N [99] PCIE_CLK_XDP_P [99]

SUS_CLK [24]

+V1.05S_AXCK_LCPLL

Q1901

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

SUS_STAT#/LPC PD#

CLKRUN#_R

Do Not StuffDYEC1802

Do Not Stuff

12

DY

D

(#514849)

EC1804

Do Not Stuff

CLK_DP2VGA [56]

CLK_PCI_LPC [68]

CLK_PCI_LPC_MEC [24]

Do Not StuffDYEC1804

Do Not Stuff

12

C1901

SC1U10V2KX-1GP

Layout: Place at the open door area.

2

SKL MOW 2014WW52 requirement

20140820 DAIVD

3D3V_S5_PCH

R1814

12

DY

3D3V_S0

R1818

8K2R2F-1-GP

1 2

MEM_SMBDATA

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

MEM_SMBCLK

R1810

1

23

RN1901

RN1901 SRN20KJ-1-G P

SRN20KJ-1-G P

4

12

C1902

C1902 SC1U10V2KX-1G P

SC1U10V2KX-1G P

12

R1810

1 2

Do Not Stuff

R1802

R1802 1MR2J-1-GP

1MR2J-1-GP

SUSCLK_R

XTAL24_IN XTAL24_IN_R

XTAL24_OUT

RTC_AUX_S5

21

G1901

Do Not Stuff

23

12

DY

1

RN1807

SML1_SMBDATA SML1_SMBCLK SML0_SMBDATA SML0_SMBCLK

GPP_B23/SML1ALERT #

GPP_C2/SMBALER T#

MEM_SMBCLK MEM_SMBDATA

3D3V_S0

2N7002KDW -GP

1

6

2345

Q1801

X1801

X1801 XTAL-24MHZ- 81-GP

XTAL-24MHZ- 81-GP

82.30004.841

4 1

DY

1 2

SRTC_RST # RTC_RST#

Iris SKL UMA

Do Not Stuff

12

EC1806

EC1807

DY

Title

Size Document Num ber Rev

Date: Sheet of

RN1807

1

8

2

7

3

6

45

SRN2K2J-4-G P

R1820

150KR2F-L-GP

12

R1817

12

2K2R2J-2-GP

SRN2K2J-1-G P

23 1

4

RN1811

RN1810

23 1

4

SRN10KJ-5-G P

PCH_SMBDAT A [12,13,56,6 5,99]

PCH_SMBCLK [12,13,56,65,99]

C1801

12

SC15P50V2JN-L- GP

C1802

12

SC15P50V2JN-L- GP

EC1803

Do Not Stuff

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

CPU_(LPC/SPI/SMBUS/CL/CLK)

A2

Iris2 SKL-U

1

3D3V_S5_PCH

3D3V_S0

18 105Wednesday, Septemb er 09, 2015

A00

5

Main Func = PCH

4

3

2

1

D D

HDA_SYNC HDA_BITCL K

HDA_SDIN0[27]

DGPU_PW ROK[24,79 ,85]

12

DY

EC2001

R2052

1 2

UMA

C C

PCH strap pin:

Flash Descriptor Security Overide/ Intel ME Debug Mode

HDA_SDOUT

The internal pull-down is disabled a fter PLTRST# deasserts

B B

Low = Default High = Enable

EC1901

1 2

DY

Do Not Stuff

DGPU_PW ROK

100KR2J -1-GP

*

HDA_COD EC_BITCLK

Do Not Stuff

PCH strap pin:

NO REBOOT

Low = Enable (Default)

HDA_SPKR

The internal pull-down is disabled a fter PLTRST# deasserts

*

HDA_COD EC_BITCLK[27]

HDA_COD EC_SYNC[27]

HDA_COD EC_RST#[2 7]

HDA_COD EC_SDOUT[27]

High = Disable

ME_FW P_EC[24]

HDA_SDO UT

HDA_RST #

DGPU_PW ROK

SPKR[27 ]

R1907 33R2J-2-G PR1907 33R2J-2-G P

R1908 Do Not StuffR1908 Do Not Stuff

R1911 Do Not StuffR1911 Do Not Stuff

R1912 33R2J-2-G PR1912 33R2J-2-G P

R1909 1KR2J-1-G PR1909 1 KR2J-1-GP

SPKR

3D3V_S0

1 2

BA22 AY22 BB22 BA21 AY21

AW22

J5

AY20

AW20

AK7 AK6 AK9

AK10

H5 D7

D8 C8

AW5

Do Not Stuff

Do Not Stuff R2006

R2006

1 2

DY

HDA_BITCL K

HDA_SYNC

HDA_RST #

HDA_SDO UT

CPU1G

AUDIO

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKYLAKE-GP

071.SKYLA.000U

SPKR

SKYLAKE_ULT

7 OF 20

SDIO/SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

KB_LED_ BL_DET

CPU_A16 _TP

SD_RCOM P

1

R1903

1 2

TP1902

R1901

1 2

200R2F-L -GP

Do Not Stuff

KB_LED_ BL_DET_R [65]

HDA_COD EC_RST#

12

EC1902

DY

Do Not Stuff

A A

5

4

3

2

Iris SKL UMA

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(AUDIO/SDIO/SDXC)

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Iris2 SKL-U

19 10 5Wednesd ay, September 09, 20 15

1

A00

Main Func = PCH

5

RN2009

DGPU_HOLD _RST#

1

4

DGPU_PW R_EN

2 3

DY

Do Not Stuff

DGPU_HOLD _RST#[76]

12

DY

3D3V_S0

D D

LPSS_UART2_R XD

R204851KR2J-1-GP R204851KR2J-1-GP

12

LPSS_UART2_T XD

R204951KR2J-1-GP R204951KR2J-1-GP

12

LPSS_UART2_C TS#

R204651KR2J-1-GP R204651KR2J-1-GP

3D3V_S0

12

R1910 10KR2J-3-GPR1910 10KR2J-3-GP

1 2

R1914 2K2R2J-2-GPR1914 2K2R2J-2-GP

1 2

2015/05/13 DVT2 modify

BLUETOOTH _EN

DBC_PANEL_E N

PCH strap pin:

No Reboot

GSPI0_MOSI / GPP_B18

The signal has a weak internal pull-down.

3D3V_S0

C C

3D3V_S5_PCH

R2039 Do Not Stuff

R2039 Do Not Stuff R2040 10KR2J-3-GPR2040 10KR2J-3-GP R2041 10KR2J-3-GPR2041 10KR2J-3-GP

Sampled at rising edge of PCH_PWROK

0 = Disable “No Reboot” mode. 1 = Enable “No Reboot” mode (PCH will disable the TCO Timer system reboot feature). This function is useful when running ITP/XDP.

RN2010

DY

Do Not Stuff

4

I2C0_SDA_TCH_ PAD I2C0_SCL_TCH_P AD

RTC_DET# SIO_EXT_WAKE #

1 2 3

2015/05/6 DVT2 modify

1 2

DY

1 2 1 2

ME_SUS_PW R_ACK_R [17]

PCH strap pin:

No Reboot

GSPI0_MOSI / GPP_B18

The signal has a weak internal pull-down.

B B

Sampled at rising edge of PCH_PWROK

0 = Disable “No Reboot” mode. 1 = Enable “No Reboot” mode (PCH will disable the TCO Timer system reboot feature). This function is useful when running ITP/XDP.

EC2002

Do Not Stuff

DY

PCH Prim

3D3V_S5_PCH

12

R2007

DY

Do Not Stuff

GPP_B18/GSPI0_MOSI

12

R2019

DY

Do Not Stuff

SIO_EXT_WAKE #[24]

PTP

DBC_PANEL_E N[55]

TP2008

BLUETOOTH _EN[61]

SATA_ODD_PW RGT[60]

I2C0_SDA_TCH_ PAD[65] I2C0_SCL_TCH_P AD[65]

4

VRAM_ID1 GPP_B18/GSPI0_MOSI

GPP_B22/GSPI1_MOSI

1

Do Not Stuff

BOARD_ID2

LPSS_UART2_R XD LPSS_UART2_T XD

LPSS_UART2_C TS#

For debug USB/UART:

TP2009

Do Not Stuff

AN8 AP7 AP8 AR7

AM5 AN7 AP5 AN5

AB1 AB2

W4

AB3

AD1 AD2 AD3 AD4

U7 U6

U8 U9

AH9

AH10

AH11 AH12

AF11 AF12

LPSS_UART2_C TS#

1

CPU1F

LPSS ISH

GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL

SKYLAKE-GP

071.SKYLA.000U

SKYLAKE_ULT

Strap

LPSS_UART2_T XD LPSS_UART2_R XD

Intel has removed EHCI controller from BDW and proposed to use UART interface for Win7 debug.

3

6 OF 20

GPP_D9/ISH_SPI_CS#

GPP_D10/ISH_SPI_CLK GPP_D11/ISH_SPI_MISO GPP_D12/ISH_SPI_MOSI

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA

GPP_D14/ISH_UART0_TXD/SML0BCLK

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

5V_S5

ACES-CON 4-37-GP

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

56

DB2

1

2 3

20.F1897.004

4

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

AC1 AC2 AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7 AP13

USB_UART_S EL_D9

DGPU_HOLD _RST#

RTC_DET#

I2C0_SDA I2C0_SCL

I2C1_SDA I2C1_SCL

1.8V Only

UART0_TXD UART0_RTS # UART0_CTS #

UART1_RXD UART1_TXD UART1_RTS # UART1_CTS #

PROJECT_ID1 PROJECT_ID2 KB_DET#

BOARD_ID3

VRAM_ID2

TP2006 Do Not StuffTP2006 Do Not Stuff

1

RTC_DET# [25]

TP2007 Do Not StuffTP2007 Do Not Stuff

1

TP2010 Do Not StuffTP2010 Do Not Stuff

1

TP2011 Do Not StuffTP2011 Do Not Stuff

1

TP2012 Do Not StuffTP2012 Do Not Stuff

1

TP2013 Do Not StuffTP2013 Do Not Stuff

1

TP2014 Do Not StuffTP2014 Do Not Stuff

1 1

TP2015Do Not StuffTP2015Do Not Stuff

KB_DET# [6 5]

PANEL_SIZE_ID [55]

3D3V_S0 3D3V_S0

12

R2015

Do Not Stuff

LOVE LAND

PROJECT_ID1

12

R2016

10KR2J-3-GP

Iris2

3D3V_S0

12

R2005

OPS

Do Not Stuff

BOARD_ID2

VRAM_ID2

UMA

VRAM_4G

VRAM_1G / 2G

12

R2008

R2008 10KR2J-3-GP

10KR2J-3-GP

12

R2053

R2053 Do Not Stuff

Do Not Stuff

12

R2054

R2054 Do Not Stuff

Do Not Stuff

2

DGPU_PW R_EN [85,86]

3D3V_S0

KB_DET#

Do Not Stuff

PROJECT_ID2

Do Not Stuff

BIOS strap pin:

BIOS UMA/DIS Strap pin

UMA

DIS

VRAM_2G

VRAM_ID1

VRAM_1G / 4G

1

3D3V_S0

Do Not Stuff

RN2007

I2C0_SCL I2C0_SDA

I2C1_SCL I2C1_SDA

(PDG#543016) Ensure that all I2C interface on-board terminations are pulled up to the same voltage rail as the device/end point.

(PDG#543016) If the UART/GPIO functionality is also not used, the signals can be left as no-connect.

12

R2027

R2027 10KR2J-3-GP

10KR2J-3-GP

BIOS strap pin:

PROJECT Strap pin

Iris2

LOVE LAND

Tulip

GPP_C11 GPP_A21

BOARD_ID2

0

1

R2023

R2023 Do Not Stuff

Do Not Stuff

R2024

BIOS strap pin:

R2017

R2018

12

DY

12

DY

3D3V_S03D3V_S0

12

RN2007

1 2 3

DY

RN2008

1 2 3

DY

Do Not Stuff

BOARD_ID3

3D3V_S0

EXO

MESO

EVT_0925

BIOS VRAM Size Strap pin

1G

2G

4G

4

PROJECT_ID2

12

R2025

R2025 Do Not Stuff

Do Not Stuff

12

R2026

R2026 Do Not Stuff

Do Not Stuff

X

VRAM_ID2

0

GPP_A18GPP_A19

PROJECT_ID1

0

1X

XX

BIOS strap pin:

BIOS UMA/DIS Strap pin

MESO

EXO

GPP_B17GPP_A23

VRAM_ID1

BOARD_ID3

0

1

0

10

01

A A

Iris SKL UMA

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

CPU_(LPSS/ISH)

Iris2 SKL-U

1

A00

20 105Wednesday, Septemb er 09, 2015

A00

Main Func = PCH

5

4

3

2

1

+VCCPRIM_1P0

+VCCPRIM_COR E

D D

C C

C2120

12

DY

Do Not Stuff

+VCCDSW _1P0

+VCCMPHYAON _1P0

+VCCMPHYGTA ON_1P0_LS_SIP

+VCCAMPHYPLL_1P 0

+VCCAPLL_1P0

+V1.00A_SIP

+VCCPDSW _3P3

+VCCPAZIO

+VCCPSPI

+VCCSRAM_1P 0

+VCCPRIM_3P3

+VCCFHV

+VCCAPLLEBB_1 P0

+VCCPRIM_1P0 +VCCPR IM_CORE

C2102

C2101

Do Not Stuff

12

DY

2.57A

Do Not Stuff

AB19 AB20

P18

AF18 AF19

V20 V21

AL1

K17

L1

N15 N16 N17 P15 P16

K15 L15

V15

AB17

Y18

AD17 AD18

AJ17

AJ19

AJ16

AF20 AF21

T19 T20

AJ21

AK20

N18

+VCCDSW _1P0

12

CPU1O

CPU POWER 4 OF 4

VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0

VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE

DCPDSW_1P0

VCCMPHYAON_1P0 VCCMPHYAON_1P0

VCCMPHYGT_1P0_N15 VCCMPHYGT_1P0_N16 VCCMPHYGT_1P0_N17 VCCMPHYGT_1P0_P15 VCCMPHYGT_1P0_P16

VCCAMPHYPLL_1P0 VCCAMPHYPLL_1P0

VCCAPLL_1P0

VCCPRIM_1P0_AB17 VCCPRIM_1P0_Y18

VCCDSW_3P3_AD17 VCCDSW_3P3_AD18 VCCDSW_3P3_AJ17

VCCHDA

VCCSPI

VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0

VCCPRIM_3P3_AJ21

VCCPRIM_1P0_AK20

VCCAPLLEBB

SKYLAKE-GP

+VCCMPHYAON _1P0

C2103

SC1U10V2KX-1GP

C2104

SC1U10V2KX-1GP

12

SKYLAKE_ULT

1.8V Only

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCRTCPRIM_3P3

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

071.SKYLA.000U

+VCCPRIM_3P3

C2105

SC1U10V2KX-1GP

12

15 OF 20

AK15

VCCPGPPA

AG15

VCCPGPPB

Y16

VCCPGPPC

Y15

VCCPGPPD

T16

VCCPGPPE

AF16

VCCPGPPF

AD15

VCCPGPPG

V19

T1

AA1

VCCATS_1P8

AK17

AK19

VCCRTC_AK19

BB14

VCCRTC_BB14

BB10

DCPRTC

A14

VCCCLK1

K19

VCCCLK2

L21

VCCCLK3

N20

VCCCLK4

L19

VCCCLK5

A10

VCCCLK6

AN11 AN13

+VCCPGPPC + VCCPGPPE

C2106

Do Not Stuff

12

DY

VCCRTCE XT

V0.85A_VID0 V0.85A_VID1

C2107

12

+VCCPGPPA +VCCPGPPB +VCCPGPPC +VCCPGPPD +VCCPGPPE +VCCPGPPF +VCCPGPPG

+VCCPRIM_3P3

+VCCDTS_1P 0

+V1.8A_SIP +VCCPRTC PRIM_3P3

+VCC19P2_1P0

+VCCF100_1P0_L

+VCCF135_1P0

+VCCF100OC _1P0_L

+VCCF24NS_ 1P0_L

+VCC24TBT_1 P0

SC1U10V2KX-1GP

+VCCPRTC _3P3

C2112 SC D1U16V2KX-3GPC2112 SCD1U16V2KX -3GP

1 2

TP2101 Do Not StuffTP2101 Do Not Stuff

1

TP2102 Do Not StuffTP2102 Do Not Stuff

1

+V1.8A_SIP

+VCCPRTC PRIM_3P3

C2108

C2109

SC1U10V2KX-1GP

12

SC1U10V2KX-1GP

12

RTC_AUX_S5

C2118

C2119

SCD1U16V2KX-3GP

Do Not Stuff

12

DY

C2117

12

SC1U10V2KX-1GP

CAP need close to VCCRTC

R2106

1 2

Do Not Stuff

+VCCPRTC _3P3

RTC_AUX_S5

+VCC24TBT_1 P0

C2116

SC1U10V2KX-1GP

12

C2110

Do Not Stuff

DY

C2111

SC1U10V2KX-1GP

12

Do Not Stuff

+VCCF100_1P0_L

B B

SC22U6D3V5MX- 2GP

A A

5

C2113

12

+VCCF24NS_ 1P0_L

Do Not Stuff

+VCCF100OC _1P0_L

Do Not Stuff

C2115

12

DY

C2114

12

DY

Iris SKL UMA

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

CPU_(POWER1)

Iris2 SKL-U

1

21 105Tuesday, May 26, 2015

A00

5

4

3

2

1

Main Func = PCH

D D

CPU1T

AW69

RSVD_AW69

AW68

RSVD_AW68

AU56

RSVD_AU56

AW48

RSVD_AW48

C7

RSVD_U12 RSVD_U11

C2202

12

DY

C C

C2201

Do Not Stuff

DY

Do Not Stuff

12

RSVD_C7

U12

RSVD_U12

U11

RSVD_U11

H11

RSVD_H11

SKYLAKE-GP

071.SKYLA.000U

SKYLAKE_ULT

SPARE

SKL MOW 2014WW52 requirement

20 OF 20

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12

RSVD_F52

F6 E3 C11 B11 A11 D12 C12 F52

B B

Iris SKL UMA

Wistron Corporation

A A

Title

CPU_(RSVD)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

CPU_(RSVD)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Iris2 SKL-U

22 105Tuesday, May 26, 2015

1

A00

5

4

3

2

1

Main Func = PCH

CPU1P

GND 1 OF 3

Do Not Stuff

TP2307

D D

TP2301

C C

B B

NCTF_A5

1

NCTF_A7 0

1

Do Not Stuff

GND 1 OF 3

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

VSS

AA65

VSS

AA68

VSS

AB15

VSS

AB16

VSS

AB18

VSS

AB21

VSS

AB8

VSS

AD13

VSS

AD16

VSS

AD19

VSS

AD20

VSS

AD21

VSS

AD62

VSS

AD8

VSS

AE64

VSS

AE65

VSS

AE66

VSS

AE67

VSS

AE68

VSS

AE69

VSS

AF1

VSS

AF10

VSS

AF15

VSS

AF17

VSS

AF2

VSS

AF4

VSS

AF63

VSS

AG16

VSS

AG17

VSS

AG18

VSS

AG19

VSS

AG20

VSS

AG21

VSS

AG71

VSS

AH13

VSS

AH6

VSS

AH63

VSS

AH64

VSS

AH67

VSS

AJ15

VSS

AJ18

VSS

AJ20

VSS

AJ4

VSS

AK11

VSS

AK16

VSS

AK18

VSS

AK21

VSS

AK22

VSS

AK27

VSS

AK63

VSS

AK68

VSS

AK69

VSS

AK8

VSS

AL2

VSS

AL28

VSS

AL32

VSS

AL35

VSS

AL38

VSS

AL4

VSS

AL45

VSS

AL48

VSS

AL52

VSS

AL55

VSS

AL58

VSS

AL64

VSS

SKYLAKE-GP

071.SKYLA.000U

SKYLAKE_ULT

16 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

TP2302

TP2302 TP2305

TP2305

TP2306

Do Not Stuff

NCTF_B7 1

1

NCTF_BA 1

1

Do Not Stuff

NCTF_BA 2

1

Do Not Stuff

CPU1Q

AT63

VSS

AT68

VSS

AT71

VSS

AU10

VSS

AU15

VSS

AU20

VSS

AU32

VSS

AU38

VSS

AV1

VSS

AV68

VSS

AV69

VSS

AV70

VSS

AV71

VSS

AW10

VSS

AW12

VSS

AW14

VSS

AW16

VSS

AW18

VSS

AW21

VSS

AW23

VSS

AW26

VSS

AW28

VSS

AW30

VSS

AW32

VSS

AW34

VSS

AW36

VSS

AW38

VSS

AW41

VSS

AW43

VSS

AW45

VSS

AW47

VSS

AW49

VSS

AW51

VSS

AW53

VSS

AW55

VSS

AW57

VSS

AW6

VSS

AW60

VSS

AW62

VSS

AW64

VSS

AW66

VSS

AW8

VSS

AY66

VSS

B10

VSS

B14

VSS

B18

VSS

B22

VSS

B30

VSS

B34

VSS

B39

VSS

B44

VSS

B48

VSS

B53

VSS

B58

VSS

B62

VSS

B66

VSS

B71

VSS

BA1

VSS

BA10

VSS

BA14

VSS

BA18

VSS

BA2

VSS

BA23

VSS

BA28

VSS

BA32

VSS

BA36

VSS

F68

VSS

BA45

VSS

SKYLAKE-GP

071.SKYLA.000U

GND 2 OF 3

SKYLAKE_ULT

17 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

NCTF_BA 71

Do Not Stuff

NCTF_BB 70 NCTF_C1

Do Not Stuff

TP2303

1

Do Not Stuff

TP2304

1

TP2308

1

[#543016 Rev0.9 ]

CPU1R

GND 3 OF 3

F8

VSS

G10

VSS

G22

VSS

G43

VSS

G45

VSS

G48

VSS

G5

VSS

G52

VSS

G55

VSS

G58

VSS

G6

VSS

G60

VSS

G63

VSS

G66

VSS

H15

VSS

H18

VSS

H71

VSS

J11

VSS

J13

VSS

J25

VSS

J28

VSS

J32

VSS

J35

VSS

J38

VSS

J42

VSS

J8

VSS

K16

VSS

K18

VSS

K22

VSS

K61

VSS

K63

VSS

K64

VSS

K65

VSS

K66

VSS

K67

VSS

K68

VSS

K70

VSS

K71

VSS

L11

VSS

L16

VSS

L17

VSS

SKYLAKE-GP

071.SKYLA.000U

SKYLAKE_ULT

18 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

A A

5

4

3

2

Iris SKL UMA

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(VSS)

Iris2 SKL-U

1

23 10 5Tuesday, May 26, 2015

A00

5

Main Func = KBC

1D0V_S5

R2402

20140814 DAVID

D D

3D3V_S5_KBC

RN2412

1 2 3 4 5

SRN10KJ-6-GP

RN2409

1 2 3 4 5

SRN10KJ-6-GP

1 2 3 4 5

SRN100KJ-5-GP

1 2 3 4 5

SRN100KJ-5-GP

C C

DGPU_PWROK

EC2401

12

DY

Do Not Stuff

EC LCD test

EC_BRIGHTNESS[55]

LCD_TST_R[55]

LCD_TST_EN[55]

B B

CMP_VOUT1 CMP_VOUT1_R

A A

1 2

Do Not Stuff

+VCCSTG

R2440

1 2

DY

Do Not Stuff

+V1.00U_CPU

R2492

1 2

DY

Do Not Stuff

Layout Note:

Need very close to EC

KSI7

8

KSI4

7

KSI2

6

KSI1

KSI0

8

KSI3

7

KSI5

6

KSI6

RN2410

8 7 6

RN2411

8 7 6

Layout Note:

Need very close to EC

3D3V_S5_KBC

KSO5 KSO7 KSO12 KSO16

KSO15 KSO13 KSO11 KSO10

PLT_RST#[17,31,40,55,61,68,76]

SATA_LED#[64]

SATA_LED#_R[16,64]

INT_TP#[4,65]

delay 10ms; RESET_OUT# assert.

R2456 Do Not StuffR2456 Do Not Stuff

1 2

R2419 Do Not StuffR2419 Do Not Stuff

1 2

R2461 Do Not StuffR2461 Do Not Stuff

1 2

EC_GPIO47 High Active

R2420

1 2

Do Not Stuff

12

C2419

R2417

Do Not Stuff

DY

Do Not Stuff

12

5

3D3V_S5 3D3V_S5_KBC

12

C2416

SCD1U16V2KX-3GP

H_PROCHOT#_EC

12

C2420

C2415

DY

Do Not Stuff

CLKRUN#[18]

R2510

SPI_CLK_ROM[18,25]

RTCRST_ON[18]

SPI_CS_ROM_N0[18,25]

SIO_SLP_S4#[17,40,51]

PCH_ALW_ON[41]

ME_SUS_PWR_ACK[17]

RESET_OUT#[17,26,40]

3D3V_S5

12

C2412

SCD1U16V2KX-3GP

12

Do Not Stuff

DY

SPI_SI_ROM[18,25]

SPI_SO_ROM[18,25]

AC_DIS[43]

R2491 Do Not StuffR2491 Do Not Stuff

R2481 Do Not StuffR2481 Do Not Stuff

SUS_CLK[18]

R2416

1 2

Do Not Stuff

DY

3D3V_S5_KBC

C2411

SCD1U16V2KX-3GP

KSO[0..16][65]

CLK_TP_SIO[65]

DAT_TP_SIO[65] SIO_PWRBTN#[17,99] PCH_RSMRST#[17] LPC_LAD[3..0][18,68]

CLK_PCI_LPC_MEC[18]

1 2

SC12P50V2JN-3GP

12

KSI[0..7][65]

LPC_LFRAME#[18,68]

Do Not Stuff

C2425

1 2

C2403

C2403 Do Not Stuff

Do Not Stuff

EC_VTT

12

C2406

SCD1U16V2KX-3GP

C2421

EC_AGND

3D3V_S5_KBC

R2450

R2450 100KR2J-1-GP

100KR2J-1-GP

1 2

KSO9

R2449

R2449 Do Not Stuff

Do Not Stuff

DY

1 2

RN2403

KSO14

1

8

KSO0

2

7

KSO2

3

6

KSO1

4 5

SRN100KJ-5-GP

RN2404

KSO3

1

8

KSO8

2

7

KSO6

3

6

KSO4

4 5

SRN100KJ-5-GP

R2410

12

C2402

Do Not Stuff

SATA_LED#

R2477

R2477 Do Not Stuff

Do Not Stuff

R2431 Do Not StuffR2431 Do Not Stuff

1 2

LCD_TST

EVT1 2014/10/20

R2418

R2418 Do Not Stuff

Do Not Stuff

1 2

DY

Q2408

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

12

SCD1U16V2KX-3GP

DY

1 2

SWHDLED

ALL_SYS_PWRGD[17,40]

D

PM_LAN_ENABLE[31]

R2446

1 2

Do Not Stuff

12

C2414

C2410

SCD1U16V2KX-3GP

CAP_LED#

PCH_PLTRST#_EC

SERIRQ[18]

SIO_RCIN#[18]

R248510R2F-L-GP R248510R2F-L-GP

1 2

R248610R2F-L-GP R248610R2F-L-GP

1 2

R248710R2F-L-GP R248710R2F-L-GP

1 2

R2490

1 2

Do Not Stuff

PTP_INT#_EC

LAN_EN

USB_EN# RUNPWROK

12

R2428

XTAL2

12

DY

XTAL1

X2401

1 2

XTAL-32D768KHZ-83-GP

082.30003.0131

2rd = 82.30001.C01

Microchip: Use CL=9p Xtal，C = 10p

H_PROCHOT# [4,44,46]

12

C2413

SCD1U16V2KX-3GP

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

SIO_EXT_SMI# TP_EN#

SIO_EXT_SCI#

EC_SPI_CLK EC_SPI_MOSI EC_SPI_MISO SATA_LED#

EC_SPI_CS0#

C2417

DY

C2428

1 2

XTAL_KBC_2

1 2

4

If don't need RTC alarm wake up, can change to 3D3V_AUX_S5

12

RTC_AUX_S53D3V_AUX_S5

Do Not Stuff

R2473

DY

Do Not Stuff

1 2

ECVBAT

12

KBC24

2

GPIO02 7/KSO00 /PVT_I O1

14

GPIO01 5/KSO01 /PVT_C S#

15

GPIO01 6/KSO02 /PVT_S CLK

16

GPIO01 7/KSO03 /PVT_I O0

37

GPIO04 5/BCM_INT 1#/KSO 04

38

GPIO04 6/BCM_DA T1/KSO 05

39

GPIO04 7/BCM_CL K1/KSO 06

50

GPIO02 5/KSO07 /PVT_I O2

46

GPIO05 5/PWM2/K SO08/P VT_IO3

68

GPIO10 2/KSO09 /CR_ST RAP

72

GPIO10 6/KSO10

74

GPIO11 0/KSO11

75

GPIO11 1/KSO12

76

GPIO11 2/PS2_C LK1A/K SO13

77

GPIO11 3/PS2_D AT1A/K SO14

86

GPIO12 5/KSO15

92

GPIO13 2/KSO16

93

GPIO14 0/KSO17

98

GPIO14 3/KSI0/D TR#

99

GPIO14 4/KSI1/D CD#

6

GPIO00 5/SMB00_ DATA/S MB00_DA TA18/K SI2

7

GPIO00 6/SMB00_ CLK/SMB0 0_CLK 18/KSI 3

104

GPIO14 7/KSI4/D SR#

105

GPIO15 0/KSI5/R I#

107

GPIO15 1/KSI6/R TS#

108

GPIO15 2/KSI7/C TS#

78

GPIO11 4/PS2_C LK0

79

GPIO11 5/PS2_D AT0

52

GPIO02 6/PS2_C LK1B

88

GPIO12 7/PS2_D AT1B

59

GPIO04 0/LAD0

60

GPIO04 1/LAD1

61

GPIO04 2/LAD2

62

GPIO04 3/LAD3

58

GPIO04 4/LFRAME #

56

GPIO06 4/LRESE T#

57

GPIO03 4/PCI_C LK

63

GPIO06 7/CLKRUN#

55

GPIO06 3/SER_I RQ

10

GPIO01 1/SMI#/EMI _INT#

49

GPIO06 0/KBRST

53

GPIO06 1/LPCPD #

66

GPIO10 0/EC_SC I#

32

GPIO12 6/SHD_SC LK

28

GPIO13 3/SHD_IO 0

29

GPIO13 4/SHD_IO 1

30

GPIO13 5/SHD_IO 2

31

GPIO13 6/SHD_IO 3

27

GPIO12 3/SHD_CS #

67

GPIO10 1/SPI_C LK

69

GPIO10 3/SPI_I O0

71

GPIO10 5/SPI_I O1

42

GPIO05 2/SPI_I O2

33

GPIO06 2/SPI_I O3

3

GPIO00 1/SPI_C S#/32K HZ_OUT

13

RESET_ IN#/GPIO 014

48

GPIO05 7/VCC_P WRGD

73

GPIO10 7/RESET _OUT#

125

XTAL2

123

XTAL1

MEC1404-NU-GP

071.01404.000E

R2458

R2458 Do Not Stuff

Do Not Stuff

C2424

SC12P50V2JN-3GP

USB_EN#

4

1 2

R2479

1 2

Do Not Stuff

R2472

Do Not Stuff

43

103

122

VBAT

GPIO00 7/SMB01_ DATA/S MB01_DA TA18

GPIO01 0/SMB01_ CLK/SMB0 1_CLK 18

GPIO01 2/SMB02_ DATA/S MB02_DA TA18

GPIO01 3/SMB02_ CLK/SMB0 2_CLK 18

GPIO13 0/SMB03_ DATA/S MB03_DA TA18

GPIO13 1/SMB03_ CLK/SMB0 3_CLK 18

GPIO14 1/SMB04_ DATA/S MB04_DA TA18

GPIO14 2/SMB04_ CLK/SMB0 4_CLK 18

MEC1404

VSS_VBAT

VSS

VSS64VSS

84

124

100

EC_AGND

R2445

1 2

Do Not Stuff

EC_AGND

3D3V_S5

3D3V_S5_KBC

12

C2423

SCD1U16V2KX-3GP

54

VTR_33 _18

VTR5VTR19VTR

VTR65VTR82VTR

GPIO03 0/BCM_INT 0#/PW M4 GPIO03 1/BCM_DA T0/PW M5 GPIO03 2/BCM_CL K0/PW M6

GPIO15 7/LED0/T ST_CL K_OUT

GPIO11 6/TFDP_ DATA/UA RT_RX

GPIO11 7/TFDP_ CLK/UAR T_TX

GPIO03 3/PECI_ DAT/SB _TSI_D AT

SYSPWR _PRES/G PIO00 3

GPIO16 6/CMP_VR EF1/UAR T_CLK

VR_CAP18VSS17VSS51AVSS

112

VR_CAP

12

C2418

SC1U10V2KX-1GP

R2434

R2434 100KR2J-1-GP

100KR2J-1-GP

1 2

8 9 11 12 89 91 96 97

40

GPIO05 0/TACH0

41

GPIO05 1/TACH1

44

GPIO05 3/PWM0

45

GPIO05 4/PWM1

47

GPIO05 6/PWM3

34 35 36 4

GPIO00 2/PWM7

1 106

GPIO15 6/LED1

70

GPIO10 4/LED2

80 81

90

GPIO03 5/SB-TSI _CLK

94

95

VREF_C PU

101

GPIO14 5/ICSP_ CLOCK

102

GPIO14 6/ICSP_ DATA

87

ICSP_MC LR

119

BGPO/GP IO004

120 121

VCI_OUT /GPIO03 6

126

VCI_IN1 #/GPIO1 62

127

VCI_IN0 #/GPIO1 63

128

VCI_OV RD_IN/GP IO164

23

GPIO16 0/DAC_0

24

GPIO16 1/DAC_1

22

DAC_VR EF

85

GPIO12 4/CMP_VO UT0

20

GPIO02 0/CMP_VI N0

25

GPIO16 5/CMP_VR EF0

83

GPIO12 0/CMP_VO UT1

21

GPIO02 1/CMP_VI N1

26

118

GPIO02 4/CMP_ST RAP0

117

GPIO02 3/ADC6/A 20M

116

GPIO02 2/ADC5

109

GPIO15 3/ADC4

110

GPIO15 4/ADC3

111

GPIO15 5/ADC2

113

GPIO12 2/ADC1

114

GPIO12 1/ADC0

115

ADC_VR EF

Layout Note:

Connect GND and AGND planes via either 0R resistor or connect directly.

USB_PWR_EN# [35]

X00_0805

R2462

Do Not Stuff

R2474

BOARD_ID_R

BOARD_ID

1 2

3D3V_AUX_KBC_33

SMBDA1 SMBCLK1

SMBDA2 SMBCLK2

L_BKLT_EN_EC

PBAT_PRES#

FAN1_TACH

DGPU_PWROK_KBC

BAT1_LED# BAT2_LED#

PTP_DIS# PECI_EC

EC_VTT

ICSP_CLOCK ICSP_DATA ICSP_CLR

EC_MUTE# +3VLP

ALWON VCI_IN1# POWER_SW_IN# ACAV_IN

CMP_VOUT0 CMP_VIN0 VCREF0

CMP_VOUT1

LCD_TST

CMP_STRAP0

MODEL_ID I_ADP BOARD_ID I_SYS I_BATT

3D3V_S5_KBC

C2422

SCD1U16V2KX-3GP

12

EC_AGND

3D3V_S5_KBC

DY

R2414

1 2

Do Not Stuff

12

Do Not Stuff

C2408

R2427

1 2

OPS

Do Not Stuff

1 2

Do Not Stuff

R2437

C2405

43R2J-GP

12

DY

R2469 Do Not StuffR2469 Do Not Stuff

12

C2429SCD1U16V2KX-3GP C2429SCD1U16V2KX-3GP

1 2

R2470 Do Not StuffR2470 Do Not Stuff

12

R2421

330R2J-3-GP

Need very close to ECALL_SYS_PWRGD assert,

12

C2435

EC_AGND

SC2200P50V2KX-2GP

3D3V_S5_KBC

R2493

R2493 10KR2F-2-GP

10KR2F-2-GP

CMP_STRAP0

1 2

3D3V_S5_KBC

R2478

R2478 Do Not Stuff

Do Not Stuff

EC debug

HOST_DEBUG_TX E51_TXD_R

ICSP_CLOCK ICSP_DATA

ICSP_CLR

EC debug

R2476 Do Not Stuff

R2463 Do Not Stuff

R2463 Do Not Stuff R2464 Do Not Stuff

R2464 Do Not Stuff

R2466 Do Not Stuff

R2466 Do Not Stuff R2465 Do Not Stuff

R2465 Do Not Stuff

3D3V_S5

12

R2443

R2443 64K9R2F-1-GP

64K9R2F-1-GP

PCB_REV

12

R2444

R2444 100KR2F-L1-GP

100KR2F-L1-GP

1 2

EC_AGND

SCD1U16V2KX-3GP

Need very close to EC

EC_MUTE# [27]

ALWON [40]

PWR_CHG_ACOK [17,44]

3D3V_S5_KBC

GPU_PWR_LEVEL [79]

12

BOARD_ID

X00_0811 Change pin define

12

EC debug

12 12

EC debug

EC debug EC debug

EC debug

12 12

EC debug

3

R2424

20KR2F-L-GP

R2448

10KR2F-2-GP

CMP_VIN0_R [26]

Layout Note:

DB3

EC debug

100.0K

100.0KReserved 174.0K

3D3V_S0

3D3V_AUX_S5

Vref = 1.117 temp around 85

1 2

12

P_SYS [44,46]

boost_mon [44]

L_BKLT_EN_EC

M00 (SA)

X00 (SB)

X01 (SC)

X02 (SD)

A00 (1)

Reserved

Reserved 1.65V

Reserved 1.358V100.0K 143.0K

Reserved

SMBDA1 [43,44] SMBCLK1 [43,44]

SYS_PWROK [17]

SIO_SLP_SUS# [17,40,53,54] PBAT_PRES# [43,44]

LID_CL_SIO# [64]

BKLGT_PWM [65]

BEEP [27]

DGPU_PWROK [19,79,85] SUSACK# [17]

EC_WAKE# [17] PS_ID [43] PCIE_WAKE# [31]

SIO_SLP_S3# [17,27,40,51,52,54]

ME_FWP_EC [19]

HOST_DEBUG_TX [61]

H_PECI [4]

ECVBAT

R2452

100KR2J-1-GP

1 2

FAN1_DAC_1 [26]

CMP_VOUT0 [26] CMP_VIN0_R [26]

PANEL_BKEN_EC [55] SIO_EXT_WAKE# [20]

AD_IA [44]

R2471

12

DY

Do Not Stuff

For T8 TEMP test

R2422

I_SYS

12

330R2J-3-GP

12

C2427

SC2200P50V2KX-2GP

EC_AGND

R2423

I_BATT

12

330R2J-3-GP

12

C2441

Need very close to EC

SC2200P50V2KX-2GP

EC_AGND

7

3D3V_AUX_KBC_R

1

ICSP_CLK_R

2

ICSP_DATA_R

3 4 5

ICSP_MCLR_R

6 8

Do Not Stuff

3

R2430

R2430 10KR2J-3-GP

10KR2J-3-GP

1 2

D2403

RB751V-40H-GP

83.R2004.G8F

C2409

C2409 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

10.0K

20.0K

33.0K

47.0K

64.9K

76.8

100.0K

KA

FAN_TACH1 [26]

2015/1/14 mofidy

R2435

12

Do Not Stuff

12

eDP backlight Control from PCH

R2436

R2436 100KR2J-1-GP

100KR2J-1-GP

+3VLP

VOLTAGEPULL-HIGH RESISTORPULL-LOW RESISTORPCB VERSION A/D(PIN98)

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.204V

1.048V215.0K100.0K

L_BKLT_EN [8]

3D3V_AUX_S5

12

R2453

R2453 1KR2J-1-GP

1KR2J-1-GP

R2455

100KR2J-1-GP

1 2

Modify on 2014/12/09

2

32K4R2F-1-GP

MODEL_ID

C2407

SCD1U16V2KX-3GP

TOUCH_PANEL_INTR#

Touch Panel PH internally.

3D3V_S5

R2442

MODEL_ID

1 2

EC_AGND

R2429 Do Not Stuff

1 2

MODEL_ID_DET(GPIO07) PULL-HIGH RESISTORPULL-LOW RESISTOR

12

R2441

R2441 100KR2F-L1-GP

100KR2F-L1-GP

3D3V_S0

DY

CHG_AMBER_LED#[64]

Q2412 and Q2413 merge

24014/12/23 mod ify

CAP_LED#

Power Switch Logic(PSL)

KBC_PWRBTN#[64]

SMBDA2

SMBCLK2

SMBDA2

SMBCLK2

SMBCLK1 SMBDA1

PCH_ALW_ON

PBAT_PRES#

SIO_EXT_SCI#

SIO_EXT_SMI#

BAT1_LED#

R2489

R2489 100KR2J-1-GP

100KR2J-1-GP

1 2

S

G

Q2414

K A

Do Not Stuff

K A

Do Not Stuff

3D3V_S5_KBC

23

RN2603

DS3

Do Not Stuff

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

100.0K

RN2402

SRN4K7J-8-GP

R2495 Do Not Stuff

1 2

DS3

R2415 10KR2J-3-GPR2415 10KR2J-3-GP

1 2

R2411 Do Not StuffR2411 Do Not Stuff

1 2

R2412 Do Not StuffR2412 Do Not Stuff

1 2

R2457 Do Not Stuff

1 2

DY

Q2412

1

6

2

5

3 4

2N7002KDW-GP

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

ECVBAT

R2451

R2451 100KR2J-1-GP

100KR2J-1-GP

1 2

2015/1/14 mofidy

D2402

DY

D2405

PTP

3D3V_S5_PCH

1

Do Not Stuff

4

6

DS3

Q2604

SML1_SMBDATA

R2438Do Not Stuff R2438Do Not Stuff

12

SML1_SMBCLK

R2439Do Not Stuff R2439Do Not Stuff

12

22.1K(64.22125 .6DL)

32.4K(64.32425 .6DL)

49.9K(64.49925 .6DL) 2.201V

64.9K(64.64925 .6DL)

120K(64.12035 .6DL) 200K(64.20035 .6DL)

1234

POWER_SW_IN#

C2426

12

SC1U10V2KX-1GP

TOUCH_PANEL_INTR# [4,55]

TP_LOCK# [65]

1

2345

TBD TBD

Iris2_SKL_UMA

TBD

Iris2_SKL_DIS

Love_land_DIS Love_land_UMA

TBD

3D3V_S5 3D3V_S5

3D3V_S0

R2432

1 2

1KR2J-1-GP

LID_CL_SIO#

PTP_DIS#

Do Not Stuff

NON DS3

1

VOLTAGE

3.0V10.0 K(64.10025.6DL)

2.702V

2.492V

2.001V

1.709V9 3.1K(64.93125. 6DL)

1.499V

1.099V100.0K

3D3V_S5_KBC

SIO_EXT_SCI#_R [16]

SIO_EXT_SMI#_R [8]

USB_OC3# [16]

RN2405

1

8

2

BATT_WHITE_LED# [64]

BAT2_LED#

CAP_LED#_S [65]

TP_EN#[65]

LID_CL_SIO#

3 4 5

SRN100KJ-5-GP

7 6

EVT1_1021

EVT1 2014/10/21

SML1_SMBDATA [18,26,79]

SML1_SMBCLK [18,26,79]

Iris SKL UMA

Title

KBC SMSC 1404

Size Document Number Rev

Size Document Number Rev A1

A1

Wednesday, September 09, 2015

Date: Sheet of

1

Iris2 SKL-U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

24 105

3D3V_S5

A00

5

Main Func = SPI Flash

SPI Flash ROM1(8M) for PCH

3D3V_S5 _PCH

4

8M:72.25Q64.K01 4M:72.25Q32.H01

3

3D3V_S5 _PCH

2

1

12

C2501

12

DY

C2505

SPI1_HOLD _ROM_RSPI1_SO_R OM_R

SPI1_CLK_ ROM_R SPI1_SI_ROM_ R

12

DY

C2501

DY

R2503 10R2F-L-GPR2503 10R2F-L-G P R2505 10 R2F-L-GPR2505 10 R2F-L-GP R2506 10 R2F-L-GPR2506 10 R2F-L-GP

EC2503

EC2503 Do Not Stuff

Do Not Stuff

12

DY

12

DY

D D

R2501

4K7R2J-2 -GP

SPI_CS_RO M_N0[18,24] SPI_SO_RO M[1 8,24]

SPI_WP _ROM[18]

C C

SPI_WP _ROM[18]

B B

SPI Flash ROM2(4M) for PCH

SPI_CS_RO M_N1[18] SPI_SO_RO M[1 8,24]

R2507 10 R2F-L-GPR2507 10 R2F-L-GP

1 2

R2508 10 R2F-L-GPR2508 10 R2F-L-GP

1 2

Do Not Stuff

R2513 10 R2F-L-GPR2513 10 R2F-L-GP

1 2

R2514 10 R2F-L-GPR2514 10 R2F-L-GP

1 2

EC2504

Do Not Stuff

EC2502

12

DY

R2515

4K7R2J-2 -GP

SPI1_W P_ROM_R

12

DY

SPI_WP _ROM_R

3D3V_S5 _PCH

4

RN2501

RN2501 Do Not Stuff

Do Not Stuff

DY

1 2

1

2 3

SPI25

1

CS#

2

DO/IO1

3

WP#/IO2

4

GND

W25 Q64FVSSIQ-GP

72.25Q64.K01

4

RN2502

RN2502 Do Not Stuff

Do Not Stuff

DY

1 2

1

2 3

SPI252

1

CS#

2

DO/IO1 WP#/IO2 GND

HOLD#/RESET#/IO3

3 4

W25 Q32FVSSIQ-GP

72.25Q32.H01

VCC

HOLD#/IO3

CLK

DI/IO0

Do Not Stuff

8 7 6 5

VCC

CLK

DI/IO0

Do Not Stuff

SPI 4MB

3D3V_S5 _PCH

SPI_HOLD_ ROM_RSPI_SO_RO M_R

SPI_CLK_R OM_R SPI_SI_ROM_R

EC2501

8 7 6 5

EC2506

Do Not Stuff

12

DY

Do Not Stuff

3D3V_S5 _PCH

12

C2502

C2502 SCD1U16 V2KX-3GP

SCD1U16 V2KX-3GP

1 2 1 2 1 2

3D3V_S5 _PCH

12

C2504

C2504 SCD1U16 V2KX-3GP

SCD1U16 V2KX-3GP

R2509 10 R2F-L-GPR2509 10 R2F-L-GP

1 2

R2511 10 R2F-L-GPR2511 10 R2F-L-GP

1 2

R2512 10 R2F-L-GPR2512 10 R2F-L-GP

1 2

EC2505

EC2505 Do Not Stuff

Do Not Stuff

SPI_HOLD_ ROM [18 ] SPI_CLK_R OM [18,24] SPI_SI_ROM [18,24]

Single SPI shared flash connection (SPI Quad I/O mode)

Refer to "NCPE985x/ NPCE995x board design reference guide"

72.25Q64.K01

72.25647.00A

QUAD/DUAL fast read DUAL fast readSource

O

O O072.25B64.0001

SFDP

O

Main Func = RTC

RTC_AUX _S5+RTC_VC C 3D3V_AU X_S5

1 2 NP1 NP2

+RTC_VC C

1

D2501

R2502

1KR2J-1-G P

AFTP250 1AFTP25 01

1

12

4

12

R2504

R2504 10MR2J-L -GP

10MR2J-L -GP

RTC_PW R

1

2

BAS40C-2 -GP

75.00040.07D

2nd = 75.00040.C7D

3rd = 75.00040.A7D

Q2505

G

S

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

3

12

C2503

DY

Do Not Stuff

Iris SKL UMA

D

3

RTC_DET # [20]

2

Iris SKL UMA

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Wednesd ay, September 09, 20 15

Date: Sheet of

Flash/RTC

Iris2 SKL-U

Taipei Hsien 221, Taiwan, R.O.C.

25 10 5

1

A00

AFTP250 2AFTP25 02

RTC1

PWR

GND

NP1 NP2

BAT-0600 03HA002M213Z L-GP-U1

62.70014.001

2nd = 62.70001.061

3rd = 20.F2316.002

A A

5

3rd = 20.F2316.002

Main Func = Thermal Sensor

5

4

3

2

1

Fan controller1

FAN261

FON#

12

DY

Do Not Stuff

FAN261

1

FSM#

GND

2

VIN

GND

3

VOUT

GND

VSET4GND

APL5606AKI-TRG-G P

74.05606.A71

2rd = 74.02113.0E1

3rd = 74.03940.A71

R2606

FAN_TACH 1_C

1 2

Do Not Stuff

FAN_VCC1

D2601

KA

12

C2603

DY

Do Not Stuff

AFTP2802A FTP2802 AFTP2801A FTP2801

8 7 6 5

2nd = 20.F1295.003

R2605

Do Not Stuff

1 2

DY

3D3V_S0 3D3V_S0

1

23

RN2602

D D

3D3V_S0

12

C2601

C2602

12

NCT7718_DXP

C2606

C2606 Do Not Stuff

Do Not Stuff

NCT7718_DXN

C2602

T8

Do Not Stuff

12

T8

Do Not Stuff

Q2603

C

T8

Do Not Stuff

E

DY

B

DY

2.System Sensor, Put on palm rest

Layout Note:

C C

3D3V_S0

R2603 Do Not Stuff

R2604 Do Not Stuff

B B

C2812 close U2801

Layout Note:

Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

1 2

T8

1 2

T8

NCT7718_ALER T#

T_CRIT#

C2607

C2607 Do Not Stuff

Do Not Stuff

DY

12

T_CRIT#

R2601

R2601 Do Not Stuff

Do Not Stuff

SML1_SMBDATA[18,24,79]

SML1_SMBCLK[18,24 ,79]

1 2 3

RESET_OUT #[17,24,40]

THERM_SYS_SHD N#

Do Not Stuff

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

THM26

VDD D+

T8

D-

ALERT#

T_CRIT_A#4GND

Do Not Stuff

1

6

2345

DY

Q2601

8

SCL

7

SDA

NCT7718_ALER T#

6 5

Q2602

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

2015/05/6 DVT2 modify

RN2602 Do Not Stuff

Do Not Stuff

T8

4

DY

D

THERM_SYS_SHD N#

THM_SML1_DAT A

THM_SML1_CLK

THM_SML1_CLK THM_SML1_DAT A

12

DY

C2609

C2608

Do Not Stuff

12

DY

1 2

DY

R2612 Do Not Stuff

C2610

Do Not Stuff

need to check with NTD team Barkley 1404 test result

3D3V_S5_KBC

R2607 10KR2J-3-GPR2607 10KR2J-3-GP

R2602

1 2

Do Not Stuff

Close to Thermal sensor

R2609

Do Not Stuff

R2610

NTC-100K-8- GP

3D3V_S5_KBC3D3V_AUX_S5

12

R2608

R2608 25K5R2F-GP

25K5R2F-GP

12

C2612

12

SCD1U16V2KX- 3GP

12

DY

PURE_HW _SHUTDOW N# [40]

CMP_VOUT0

1 2

CMP_VOUT0 [24]

Close to KBC VD_IN1 for system thermal sensor

CMP_VIN0_R [24]

12

C2613

SC100P50V2JN-3 GP

VD_IN1_C

SC100P50V2JN-3 GP

1 2

Do Not Stuff

Layout Note:

Signal Routing Guideline: Trace width = 15mil

R2611

Layout Note:

Need 10 mil trace width.

DY

FAN1_DAC_1[24]

12

5V_S0

FAN_TACH 1[24]

Do Not Stuff

EC2602

DY

FAN_VCC1

C2604

DY

FAN_TACH 1

FAN_VCC1

EC2601

12

DY

Do Not Stuff

3 2

1

ETY-CON3-8- GP

20.F1841.003

AFTP2803A FTP2803

FAN_TACH 1_C

1

FAN_VCC1

1

5V_S0

12

C2611

C2605

SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP

FAN1

5

4

1

GPU thermal sensor

3D3V_VGA_S0 3D3V_VGA_S0

R2613 Do Not Stuff

1 2

GPU T8

R2614 Do Not Stuff

1 2

GPU T8

GPU_T8

12

C2615

C2616

12

Do Not Stuff

C2616 Do Not Stuff

Do Not Stuff

GPU_T_CRIT#

THM262

GPU T8

1

VDD

2

D+

3

DT_CRIT#4GND

Do Not Stuff

R2615

1 2

GPU T8

Do Not Stuff

ALERT#

SCL SDA

DY

GPU_DPLUS[79]

C2614

GPU T8

A A

GPU_DMINUS[79]

Layout Note:

Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

5

GPU T8

8 7

GPU_ALERT#

6 5

GPU_T_CRIT_R #

GPU_ALERT#

GPU_T_CRIT#

SMB_CLK_VGA_R [79]

3D3V_VGA_S0

G

S

SMB_DATA_VGA_ R [79]

Q2605

D

DY

Do Not Stuff

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

PURE_HW _SHUTDOW N#

Iris SKL UMA

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

THERMAL NCT7718W/Fan

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Iris2 SKL-U

Wednesd ay, September 09, 2015

Wednesd ay, September 09, 2015 Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

1

26 105

A00

12

DY

C2617

C2618

Do Not Stuff

4

5

4

3

2

1

Main Func = Audio

R2731

1 2

Do Not Stuff

D D

3D3V_S0

1D8V_S0

C C

3D3V_S0

1D5V_S0

moat

1D8V_S0

R2713

1 2

3246

R2705 Do Not StuffR2705 Do Not Stuff

1 2

R2710 Do Not Stuff

1 2

DY

AVDD2: +1.8VD@3246 +1.5VD@3234

Do Not Stuff

25mA

R2701

1 2

Do Not Stuff

R2724

1 2

3246

Do Not Stuff

1.5A

5V_S0 +5V_PVDD

R2702

1 2

Do Not Stuff

R2704

1 2

Do Not Stuff

+3V_1D5V_AVDD

Do Not Stuff

12

AUD_AGND

Azalia I/F EMI

EC2708

12

DY

Do Not Stuff

B B

A A

5

+3V_AVDD

ALC3234 and ALC3246

C2701

12

SCD1U16V2KX-3GP

C2707

C2706

12

SC4D7U6D3V3KX-GP

Layout Note:

Close pin41

SCD1U16V2KX-3GP

C2709

C2708

12

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP

Layout Note:

Close pin46

CPVDD

12

C2724

SC4D7U6D3V 3KX-GP

Close pin36

Speaker trace width >40mil @ 2W4ohm speaker power

C2715

SC4D7U6D3V 3KX-GP

Close pin40

HDA_CODE C_SDOUT HDA_CODE C_BITCLK

EC2709

+3V_AVDD

AUD_AGND

Layout Note:

EC_MUTE#[24]

R2728

DY

Do Not Stuff

DMIC_CLK[55]

Do Not Stuff

Close pin3

12

DMIC_DATA_R

C2723

4

C2712 SC10U6D3V3MX-GPC2712 SC10U 6D3V3MX-GP

1 2

AUD_SPK_L+[29]

AUD_SPK_L-[29]

AUD_SPK_R-[29]

AUD_SPK_R+[29]

R2708

1 2

Do Not Stuff

EC2701

Do Not StuffDYEC2701

Do Not Stuff

12

DY

DMIC_DATA[55]

HDA_CODE C_SDOUT[19]

DY

HDA_CODE C_BITCLK[19]

1 2

HDA_SDIN0[19]

HDA_CODE C_SYNC[19]

HDA_CODE C_RST#[19]

+3V_1D5V_AVDD

TP2702TP2702

SIO_SLP_S3#[17,24,40,51,52,54]

+5V_PVDD

AUD_SPK_L+

AUD_SPK_L-

AUD_SPK_R-

AUD_SPK_R+

+5V_PVDD

1

SC4D7U6D3V 3KX-GP

LINE1_VREFO_R[29]

LINE1_VREFO_L[29]

AUD_HP1_JAC K_L[29]

AUD_HP1_JAC K_R[29]

LDO2_CAP

EAPD#

COMBO-GPI

1 2

SC1U10V2KX-1G P

12

C2703

C2703 SC1U10V2KX-1G P

SC1U10V2KX-1G P

CBP

37

38

39

40

41

42

43

44

45

46

47

48

49

ALC3234-CG-G P

+3V_AVDD

C2716

R2714Do Not Stuff R2714Do Not Stuff

R2716Do Not Stuff R2716Do Not Stuff

R2719Do Not Stuff R2719Do Not Stuff

1 2

R2720Do Not Stuff R2720Do Not Stuff

1 2

R2718Do Not Stuff R2718Do Not Stuff

1 2

HDA_CODE C_SYNC

Q2701

G

S

Do Not Stuff

C2704

1 2

CPVDD

CPVEE

CBN

33

34

35

36

HDA27

CBP

AVSS2

LDO2-CAP

AVDD2

PVDD1

SPK-OUT-L+

SPK-OUT-L-

SPK-OUT-R-

SPK-OUT-R+

PVDD2

PDB

SPDIF-OUT/GPIO2

GND

12

3246

CBN

CPVEE

CPVDD

71.03234.003

3246:071.03246.0003

DVDD1GPIO0/DMIC-DATA2GPIO1/DMIC-CLK3DVSS4SDATA-OUT5BCLK6LDO3-CAP7SDATA-IN8DVDD-IO9SYNC10RESET#11PCBEEP

C2717

12

SCD1U16V2KX-3GP

DMIC_DATA_R

DMIC_CLK_R

CODEC_SD OUT_R

CODEC_BITC LK_R

HDA_CODE C_SDIN0

HDA_CODE C_RST#

12

3246

R2726

C2722

3246

Do Not Stuff

1D8V_EN#

D

3

32

HPOUT-L/PORT-I-L

HPOUT-R/PORT-I-R

R2727

1 2

3246

Do Not Stuff

31

LINE1-VREFO-L

Reserved for ALC3234

12

C2705

12

C2702

C2702 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

SC4D7U6D3V3KX-GP

AUD_VREF

LDO1_CAP

25

26

27

28

29

30

VREF

AVDD1

LDO1-CAP LINE2_L/PORT-E-L

MIC2-VREFO

LINE2_R/PORT-E-R

LINE1-VREFO-R

LINE1_L/PORT-C-L

LINE1_R/PORT-C-R

MIC2_R/PORT-F-R/SLEEVE

MIC2_L/PORT-F-L/RING

+3V_AVDD

12

3246

1D8V_EN_R#

MIC2/LINE2_JD/JD2

HP/LINE1_JD/JD1

C2719SCD1U16V2KX-3GP C2719SCD1U16V2 KX-3GP

12

I2C_SDA@3246

HDA_CODEC_RST#_R

R2721

1 2

S

C2714

C2714 Do Not Stuff

Do Not Stuff

2nd = 84.00102.031

3rd = 84.03413.B31

MONO-OUT

12

I2C_SCL@3246

Do Not Stuff

SPDIFO/FRONT_JD/JD3/GPIO3

LDO3_CAP

C2718SC4D7U6D3V3KX-GP C2718SC4D7U6D3V3K X-GP

12

150mA

MIC2_VREFO [29]

R2711

R2711 100KR2J-1-GP

100KR2J-1-GP

+5V_AVDD

AUD_AGND

AVSS1

NC#20

MIC-CAP

AUD_PC_BEEP

Q2702

Do Not Stuff

3246

D

G

AUD_AGND

moat

R2703

1 2

Do Not Stuff

C2710

SCD1U16V2KX-3GP

24

23

22

21

V3D3_STB

20

MIC_CAP

19

18

17

AUD_PC_BEEP _3246 A UD_PC_BEEP_R

16

JDREF

15

14

AUD_SENSE_A

13

R2715

1 2

Do Not Stuff

1D8V_S01D8V_S5

D

12

C2721

Do Not Stuff

DY

SCD1U16V2KX-3GP

LINE1_L [29]

LINE1_R [29]

C2713 SC10U6D3V3MX-GPC2713 SC10U 6D3V3MX-GP

1 2

SLEEVE [29 ]

RING2 [29]

R2707 Do Not Stuff

1 2

DY

moat

1 2

R2709

R2709 200KR2F-L-GP

200KR2F-L-GP

AUD_PC_BEEP _R

SPKR[19]

BEEP[ 24]

2015/1/14 modify for Beep waveform

Do Not Stuff

12

C2711

Layout Note:

Place close to Pin 26

AUD_AGND

SC4D7U6D3V3KX-GP

R2712 Do Not StuffR2712 Do Not Stuff

AUD_SENSE

Layout Note:

Place close to Pin 13

2

moat

R2725 Do Not Stuff

1 2

3246

1 2

AUD_AGND

R2723

1 2

3246

Do Not Stuff

AUD_AGND

RN2701

2 3 1

SRN1KJ-7-G P

5V_S0+5V_AVD D

5V_S5

Layout Note:

AUD_SENSE [29]

4

moat

EC2707 Do Not Stuff

1 2

DY

EC2706 Do Not Stuff

1 2

DY

EC2705 Do Not Stuff

1 2

DY

EC2704 Do Not Stuff

1 2

DY

EC2703 Do Not Stuff

1 2

DY

AUD_AGND

R2706

1 2

Do Not Stuff

Layout Note:

AUD_AGND

Tied at point only under

3D3V_S5

Codec or near the Codec

Width>40mil, to improve Headpohone Crosstalk noise Change it to sharp will be better. Add 2 vias (>0.5A) when trace layer change.

moat

R2722

100KR2J-1-GP

C2720

AUD_PC_BEEP _R

1 2

SCD1U16V2KX- 3GP

12

R2717

R2717 2K2R2J-2-GP

2K2R2J-2-GP

Audio Codec ALC3246

Iris2 SKL-U

1

HDA_SPKR_R

2

KBC_BEEP_R

1

BAT54C-7-F- 3-GP

75.00054.E7D

2nd = 83.R2003.W81

3rd = 75.00054.A7D

4th = 83.R2003.V81

AUD_SENSE_A

+3.3VD@3234 follow Pin1 Power setting@3246

D2701

AUD_PC_BEEP _C

3

Iris SKL UMA

Title

Size Document Numb er Rev

A2

Date: Sheet of

+3V_AVDD

12

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

27 105Wednesday, Septem ber 09, 2015

A00

5

D D

C C

4

3

2

1

B B

A A

Iris SKL UMA

Title

Size Document Number Rev

A1

Date: Sheet of

5

4

3

2

Date: Sheet of

1

(Reserved)

Iris2 SKL-U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

28 105Tuesday, May 26, 2015

A00

5

Main Func = Audio

4

3

2

1

Layout Note:

Speaker trace width >40mil @ 2W4ohm speaker power

12

12 12 12

AUD_SPK _R+_C

AUD_SPK _R-_C AUD_SPK _L+_C AUD_SPK _L-_C

D D

AUD_SPK _R+[27]

AUD_SPK _R-[27 ] AUD_SPK _L+[27] AUD_SPK _L-[27]

SC1KP50V2KX-1GP

12

EC2901

EC2902

SC1KP50V2KX-1GP

EC2903

12

EC2904

R2904Do No t Stuff R2904Do Not S tuff

R2903Do No t Stuff R2903Do Not S tuff R2902Do No t Stuff R2902Do Not S tuff R2901Do No t Stuff R2901Do Not S tuff

Speaker

SPK1

1

2 3 4

ACES-CON 4-29-GP

20.F1639.004

2nd = 20.F1804.004

AUD_SPK _L-_C AUD_SPK _L+_C AUD_SPK _R-_C

AUD_SPK _R+_C

5

6

CONN Pin

Pin1

Pin2

Pin3

Pin4

AFTP290 1AFTP29 01

1

AFTP290 2AFTP29 02

1

AFTP290 3AFTP29 03

1

AFTP290 4AFTP29 04

1

Net name

SPK_R+

SPK_R-

SPK_L+

SPK_L-

2015/09/08 modify (EMI suggest)

C C

RN2901

1

MIC2_VREF O[27]

SRN2K2J -1-GP

RING2[27]

AUD_HP1 _JACK_L[27]

LINE1_L[27]

LINE1_VRE FO_L[27]

AUD_HP1 _JACK_R[27]

LINE1_R[27]

LINE1_VRE FO_R[27]

SLEEVE[27]

C2907

C2908

1 2

SC4D7U6 D3V3KX-GP

1 2

SC4D7U6 D3V3KX-GP

SRN2K2J -1-GP

LINE1-L_C

LINE1-L_R

4

2 3

R2908 10 R2F-L-GPR2908 10 R2F-L-GP

1 2

R2922 1K R2J-1-GPR2922 1K R2J-1-GP

1 2

R2912 4K 7R2J-2-GPR2912 4K 7R2J-2-GP

1 2

R2910 10 R2F-L-GPR2910 10 R2F-L-GP

1 2

R2921 1K R2J-1-GPR2921 1K R2J-1-GP

1 2

R2913 4K 7R2J-2-GPR2913 4K 7R2J-2-GP

1 2

AUD_HP1 _JACK_L1

AUD_HP1 _JACK_R1

EC2908

Do Not StuffDYEC2908

Do Not Stuff

12

R2920

Do Not StuffDYR2920

Do Not Stuff

DY

R2906Do No t Stuff R2906Do Not S tuff

12

R2907Do No t Stuff R2907Do Not S tuff

12

R2909Do No t Stuff R2909Do Not S tuff

12

R2911Do No t Stuff R2911Do Not S tuff

EC2906

Do Not StuffDYEC2906

EC2907

Do Not StuffDYEC2907

Do Not Stuff

12

DY

Do Not Stuff

12

R2919

DY

Do Not Stuff

DY

EC2905

Do Not StuffDYEC2905

Do Not Stuff

12

DY

12

RING2_R AUD_POR TA_L_R_B

JACK_PL UG

AUD_POR TA_R_R_B SLEEVE_ R

Universal Jack (Moved to I/O Board)

RING2_R [66]

AUD_POR TA_L_R_B [66]

JACK_PL UG [66]

AUD_POR TA_R_R_B [66]

SLEEVE_ R [6 6]

Delay circuit

B B

(JACK_PLUG_DET: on IO Board)

AUD_AGN D AUD_AG ND

JACK_PL UG

A A

5

4

3

R2923 Do Not StuffR2923 Do Not Stuff

2

1 2

12

DY

AUD_AGN D

Iris SKL UMA

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Date: Sheet of

Audio IO

Iris2 SKL-U

Wednesd ay, September 09, 20 15

10 mils10 mils

C2902

C2902 Do Not Stuff

Do Not Stuff

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

29 10 5

1

AUD_SEN SE [27]

A00

5

4

3

2

1

Main Func = Audio

D D

C C

(Blanking)

B B

Iris SKL UMA

Wistron Corporation

A A

Title

(Reserved)

Size Document Number Rev

Size Document Number Rev A4

A4

Date: Sheet of

5

4

3

Date: Sheet of

(Reserved)

Iris2 SKL-U

Tuesday, May 26, 2015

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

30 105

1

A00

Dell Inspiron 3459, Inspiron 3559 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual