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Inspiron 17 7737
Quick Start Manual
2 pgs140.05 Kb0
Schematics
102 pgs1.77 Mb0
Specifications
1 pgs2.43 Mb0

Dell Inspiron 17 7737 Schematics

5
D D
4
3
2
1
Hadley17" Schematics Document
Haswell ULT
C C
2013-06-24 REV :A00
B B
DY : None Installed
A A
5
4
3
2
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Cover Page
Cover Page
Cover Page
Hadley 17"
Hadley 17"
Hadley 17"
1
1 102Tuesday, June 25, 2013
1 102Tuesday, June 25, 2013
1 102Tuesday, June 25, 2013
A00
A00
A00
5
17" LCD
FHD(1920 x 1080)
D D
LVDS EDP
52
eDP to LVDS Conveter
Realtek
RTD
2136R
HDMI Level Shift
HDMI CONN
TMDS
54
Prade
PS8171
USB PowerShare
USB 2.0
USB 3.0 / Power share
34
TI
TPS2544RTER
USB 3.0 CONN
34
C C
USB 3.0 CONN
USB 3.0 CONN
USB 3.0
34
USB 3.0
34
USB3.0 Redriver
TI
SN65LVPE502RGER
USB3.0 Redriver
TI
SN65LVPE502RGER
Daughter board
B B
Internal Digital MIC
Combo jack
Audio Codec
Realtek ALC3223
2CH SPEAKER
4
3
Hadley17 Block Diagram
DDR3L Channel A
53
Intel CPU
Haswell ULT
DDR3L Channel B
15W
TMDS
54
35
34
34
USB 2.0
USB 3.0
USB 2.0
USB 3.0
USB 2.0
USB 3.0
USB 2.0
USB 3.0
HDA
Lynx Point-LP
8 USB 2.0/1.1 ports 2-4 USB 3.0 ports
High Definition Audio
4 SATA ports
8-12 PCIE ports
LPC I/F
ACPI 4.0a
SPI
Flash ROM
SPI
PCI-E x4
PCI-E
USB 2.0
SATA3
USB 2.0
USB 2.0
SATA3
SATA2
PCI-E
LPC
25
KBC
DDR3L 1600MHz
DDR3L 1600MHz
N14P-GT / N14E-GL
Mini-Card
802.11a/b/g/n BT
mSATA
Touch Screen
2M 720P Camera
SATA repeater
TI SN75LVCP601
ODD
(10/100/1000M)
Realtek
RTL8411B
LPC debug port
DC Fan Contrroller
Slot A
Slot B
GPU
35W/37W
65
ANPEC
APL5606AKI
73~77
58
60
52
52
56
56
30
26
12
13
SATA3
2
Project code : 91.48L01.001 PCB
P/N : 12309
Revision : -1
GDDR5 Ch A
GDDR5 Ch B
RJ45LAN+Card reader
MMI Card Connector (SD/SDHC/SDXC/ SD-UHS/MS/MS-Pro)
DC Fan Module
VRAM(GDDR5)
128M x 16 x4(1GB)
VRAM(GDDR5)
128M x 16 x 4(1GB)
HDD
26
1
CHARGER
BQ24717
AD+ BT+ DCBATOUT
OUTPUTSINPUTS
SYSTEM DC/DC
TPS51225
INPUTS OUTPUTS
DCBATOUT
INPUTS OUTPUTS
DCBATOUT
5V_AUX_S5 3D3V_AUX_S5 5V_CHARGER 3D3V_PWR
CPU DC/DC TPS51622
VCC_CORE
46~47
SYSTEM DC/DC
TPS51363
OUTPUTSINPUTS
DCBATOUT
1D05V_S0
SYSTEM DC/DC
TPS51216
INPUTS
DCBATOUT
OUTPUTS
1D35V_S3 0D675V_S0
SYSTEM DC/DC
NCP81172
INPUTS
DCBATOUT
5V_S5 3D3V_S5
3D3V_S0 1D05V_S0
1D35V_S3 1D35V_VGA_S0
OUTPUTS
VGA_CORE
Switches
OUTPUTSINPUTS
5V_S0 3D3V_S0
3D3V_VGA_S0 1D05V_VGA_S0
36, 83
LDO
TLV70215DBVR
3D3V_S5 1D8V_S0
OUTPUTSINPUTS
PCB LAYER
L1 : TOP
L2 : GND
L3 : Signal
L4 : Signal
L5 : VCC
L6 : Signal
L7 : GND
L8 : Bottom
44
45
48
49
82
51
Nuvoton
CE985PA0DX
PS2
NP
Touch Pad
Int. KB
3
A A
SMBus
5
4
SMBus
24
Thermal
63
Nuvoton
7718W
NCT
26
2
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Block Diagram
Block Diagram
Block Diagram
Hadley 17"
Hadley 17"
Hadley 17"
2 102Tuesday, June 25, 2013
2 102Tuesday, June 25, 2013
2 102Tuesday, June 25, 2013
1
A00
A00
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
(Reserved)
(Reserved)
(Reserved)
Hadley 17"
Hadley 17"
Hadley 17"
3 102Tuesday, June 25, 2013
3 102Tuesday, June 25, 2013
3 102Tuesday, June 25, 2013
1
A00
A00
A00
5
4
3
2
1
SSID = CPU
D D
1D05S_VCCST
12
R401
R401
62R2J-GP
62R2J-GP
H_PROCHOT#24,42,44,46
C C
R407 200R2F-L-GPR407 200R2F-L-GP
1 2
R408 120R2F-GPR408 120R2F-GP
1 2
R409 100R2F-L1-GP-UR409 100R2F-L1-GP-U
1 2
Layout Note:
Design Guideline: SM_RCOMP keep routing length less than 500 mils.
Layout Note:
Impedance control:50 ohm
SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2
TP401TP401 TP402TP402
H_PECI24
1 2
TP403TP403
DDR_PG_CTRL12
R403
R403 56R2J-4-GP
56R2J-4-GP
SKTOCC#
1
H_CATERR#
1
H_PROCHOT#_R
H_CPUPW RGD
1
R405
R405
12
10KR2J-3-GP
10KR2J-3-GP
SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 SM_DRAMRST# DDR_PG_CTRL
B B
D61 K61 N62
K63
C61
AU60 AV60 AU61 AV15 AV61
CPU1B
CPU1B
PROC_DETECT# CATERR# PECI
PROCHOT#
PROCPWRGD
SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST# SM_PG_CNTL1
HASWELL-6-GP
HASWELL-6-GP
SM_DRAMRST#
MISC
MISC
THERMAL
THERMAL
PWR
PWR
DDR3L
DDR3L
HSW_ULT_DDR3L
HSW_ULT_DDR3L
1D35V_S3
12
R410
R410 470R2J-2-GP
470R2J-2-GP
JTAG
JTAG
R404
R404
1 2
Do Not Stuff
Do Not Stuff
2 OF 19
2 OF 19
XDP_PRDY#
J62
PRDY#
PREQ# PROC_TCK PROC_TMS
PROC_TRST#
PROC_TDI
PROC_TDO
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
Layout Note:
Place close to DIMM
XDP_PREQ#
K62
XDP_TCLK
E60
XDP_TMS
E61
XDP_TRST#
E59
XDP_TDI
F63
XDP_TDO
F62
XDP_BPM0
J60
XDP_BPM1
H60
XDP_BPM2
H61
XDP_BPM3
H62
XDP_BPM4
K59
XDP_BPM5
H63
XDP_BPM6
K60
XDP_BPM7
J61
DDR3_DRAMRST# 12,13
XDP_PRDY# 96 XDP_PREQ# 96
XDP_BPM[7:0]
XDP_BPM[7:0] 96
1D05S_VCCST
RN401
XDP_TMS XDP_TDI
XDP_TDO
XDP_TRST# XDP_TCLK
RN401
1
8
2
7
3
6
XDP
XDP
4 5
Do Not Stuff
Do Not Stuff
XDP
XDP
R402 Do Not Stuff
R402 Do Not Stuff
1 2
R406 51R2J-2-GPR406 51R2J-2-GP
1 2
Check TCLK Pull down Res.
UMA
UMA
A A
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU (THERMAL/CLOCK)
CPU (THERMAL/CLOCK)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (THERMAL/CLOCK)
A3
A3
A3
Hadley 17"
Hadley 17"
Hadley 17"
4 102Tuesday, June 25, 2013
4 102Tuesday, June 25, 2013
4 102Tuesday, June 25, 2013
A00
A00
A00
5
4
3
2
1
SSID = CPU
HSW_ULT_DDR3L
CPU1C
AM63 AM62
AM61 AM60
AM57
AM54
AW58 AW56
AW54 AW52
AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60
AP63 AP62
AP61 AP60 AP58 AR58
AK57 AL58 AK58 AR57 AN57 AP55 AR55
AK54 AL55 AK55 AR54 AN54 AY58
AY56 AV58
AU58 AV56 AU56 AY54
AY52 AV54
AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51
CPU1C
SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
M_A_DQ[63:0]12
D D
C C
M_A_DQ[63:0]
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQS7 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
HSW_ULT_DDR3L
DDR CHANNEL A
DDR CHANNEL A
3 OF 19
3 OF 19
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1 SA_CKE0
SA_CKE1 SA_CKE2 SA_CKE3
SA_CS#0 SA_CS#1
SA_ODT0 SA_RAS#
SA_WE#
SA_CAS#
SA_BA0 SA_BA1 SA_BA2
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8
SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15
SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7
SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7
SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1
AU37 AV37 AW36 AY36
AU43 AW43 AY42 AY43
AP33 AR32
AP32 AY34
AW34 AU34
AU35 AV35 AY41
AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42
AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48
AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49
AP49 AR51 AP51
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6
+V_SM_VREF_C NT
M_A_DIMA_CLK_DD R#0 12 M_A_DIMA_CLK_DD R0 12 M_A_DIMA_CLK_DD R#1 12 M_A_DIMA_CLK_DD R1 12
M_A_DIMA_CKE0 12 M_A_DIMA_CKE1 12
M_A_DIMA_CS#0 12 M_A_DIMA_CS#1 12
TP_M_A_DIMA_ODT 0
M_A_RAS# 12
M_A_WE# 12
M_A_CAS# 12
M_A_BS0 12 M_A_BS1 12 M_A_BS2 12
M_A_A[15:0] 12
M_A_DQS#[7:0] 12
M_A_DQS[7:0] 12
+V_SM_VREF_C NT 37 DDR_W R_VREF01 12 DDR_W R_VREF02 13
CPU1D
M_B_DQ[63:0]13
TP501TP501
1
M_B_DQ[63:0]
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
AW31 AW29
AW27 AW25
AM29
AM26
AW23 AW21
AW19 AW17
AY31 AY29 AV31
AU31 AV29 AU29 AY27
AY25 AV27
AU27 AV25 AU25
AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26
AK25 AL25 AY23
AY21 AV23
AU23 AV21 AU21 AY19
AY17 AV19
AU19 AV17 AU17 AR21 AR22 AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20 AM20 AR18 AP18
CPU1D
SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
HSW_ULT_DDR3L
HSW_ULT_DDR3L
DDR CHANNEL B
DDR CHANNEL B
4 OF 19
4 OF 19
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3
SB_CS#0 SB_CS#1
SB_ODT0 SB_RAS#
SB_WE#
SB_CAS#
SB_BA0 SB_BA1 SB_BA2
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8
SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15
SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7
SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7
AM38 AN38 AK38 AL38
AY49 AU50 AW49 AV50
AM32 AK32
AL32 AM35
AK35 AM33
AL35 AM36 AU49
AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46
AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18
AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18
TP_M_B_DIMB_ODT 0
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7
M_B_DIMB_CLK_DD R#0 13 M_B_DIMB_CLK_DD R0 13 M_B_DIMB_CLK_DD R#1 13 M_B_DIMB_CLK_DD R1 13
M_B_DIMB_CKE0 13 M_B_DIMB_CKE1 13
M_B_DIMB_CS#0 13 M_B_DIMB_CS#1 13
1
M_B_RAS# 13
M_B_WE# 13
M_B_CAS# 13
M_B_BS0 13 M_B_BS1 13 M_B_BS2 13
M_B_A[15:0] 13
M_B_DQS#[7:0] 13
M_B_DQS[7:0] 13
TP503TP503
HASWELL- 6-GP
HASWELL- 6-GP
HASWELL- 6-GP
B B
A A
5
4
3
HASWELL- 6-GP
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O. C.
CPU (DDR)
CPU (DDR)
CPU (DDR)
Hadley 17"
Hadley 17"
Hadley 17"
1
A00
A00
5 102Tuesday, June 25, 2013
5 102Tuesday, June 25, 2013
5 102Tuesday, June 25, 2013
A00
5
4
3
2
1
SSID = CPU
HSW_ULT_DDR3L
CPU1S
CPU1S
D D
CFG[19:0]96
C C
CFG[19:0]
1 2
R601
R601 49D9R2F-GP
49D9R2F-GP
1 2
R603
R603 8K2R2F-1-GP
8K2R2F-1-GP
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15
CFG16 CFG18 CFG17 CFG19
CFG_RCOMP
TD_IREF
AC60 AC62 AC63 AA63 AA60
Y62 Y61 Y60 V62 V61 V60 U60 T63 T62 T61 T60
AA62
U63
AA61
U62 V63
H18 B12
A5 E1
D1
J20
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15
CFG16 CFG18 CFG17 CFG19
CFG_RCOMP RSVD#A5 RSVD#E1
RSVD#D1 RSVD#J20 RSVD#H18 TD_IREF
HSW_ULT_DDR3L
RESERVED
RESERVED
19 OF 19
19 OF 19
RSVD_TP#AV63 RSVD_TP#AU63
RSVD_TP#C63 RSVD_TP#C62
RSVD#B43
RSVD_TP#A51 RSVD_TP#B51
RSVD_TP#L60
RSVD#N60
RSVD#W23
RSVD#Y22
PROC_OPI_RCOMP
RSVD#AV62
RSVD#D58
VSS VSS
RSVD#P20 RSVD#R20
AV63 AU63
C63 C62
EDP_SPARE
B43 A51
B51 L60 N60 W23
PROC_OPI_COMP3
Y22
PROC_OPI_COMP
AY15 AV62
D58 P22
N21
HVM_CLK#
P20
HVM_CLK
R20
1
TP605
TP605 Do Not Stuff
Do Not Stuff
1127 add (follow EA40)
DY
DY
R606 Do Not Stuff
R606 Do Not Stuff
1 2
R602 49D9R2F-GPR602 49D9R2F-GP
1 2
1
TP619 Do Not StuffTP619 Do Not Stuff
1
TP620 Do Not StuffTP620 Do Not Stuff
Layout Note:
1.Referenced "continuous" VSS plane only.
2.Avoid routing next to clock pins or noisy signals.
3.Trace width: 12~15mil
4.Isolation Spacing: 12mil
5.Max length: 500mil
CFG3
DY
DY
12
R604
R604 Do Not Stuff
Do Not Stuff
PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)
0 : ENABLED
CFG[3]
SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
1 : DISABLED
CFG4
B B
A A
5
4
12
R605
R605 1KR2J-1-GP
1KR2J-1-GP
DISPLAY PORT PRESENCE STRAP
0 : ENABLED
CFG[4]
AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE EMBEDDED DISPLAY PORT
1 : DISABLED
NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT
3
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
CPU (RESERVED)
CPU (RESERVED)
CPU (RESERVED)
Hadley 17"
Hadley 17"
Hadley 17"
6 102Tuesday, June 25, 2013
6 102Tuesday, June 25, 2013
6 102Tuesday, June 25, 2013
1
A00
A00
A00
5
4
3
2
1
SSID = CPU
D D
HSW_ULT_DDR3L
CPU1L
CPU1L
L59
AH26
AJ31 AJ33
AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50
F59 N58
AC58
E63
AB23
A59
E20 AD23 AA23 AE59
L62
N63
L63
B59
F60
C59
D63
H59
P62
P60
P61
N59
N61
T59 AD60 AD59 AA59 AE60 AC59 AG58
U59
V59 AC22
AE22 AE23
AB57 AD57 AG57
C24
C28
C32
J58
RSVD#L59 RSVD#J58
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VCC RSVD#N58 RSVD#AC58
VCC_SENSE RSVD#AB23 VCCIO_OUT VCCIOA_OUT RSVD#AD23 RSVD#AA23 RSVD#AE59
VIDALERT# VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY
VSS PWR_DEBUG# VSS RSVD_TP#P60 RSVD_TP#P61 RSVD_TP#N59 RSVD_TP#N61 RSVD#T59 RSVD#AD60 RSVD#AD59 RSVD#AA59 RSVD#AE60 RSVD#AC59 RSVD#AG58 RSVD#U59 RSVD#V59
VCCST VCCST VCCST
VCC VCC VCC VCC VCC VCC
HASWELL-6-GP
HASWELL-6-GP
12
TP701TP701
R701
R701
43R2J-GP
43R2J-GP
1 2
1D35V_S3
VCC_CORE
TP_VCCIO_OUT
1
+VCCIOA_OUT
H_CPU_SVIDALRT#
H_CPU_SVIDCLK H_CPU_SVIDDAT H_VCCST_PWRGD
PWR_DEBUG
1D05S_VCCST
VCC_CORE
1D05S_VCCST
R703 75R2F-2-GPR703 75R2F-2-GP
1 2
R704 130R2F-1-GPR704 130R2F-1-GP
1 2
VR_SVID_ALERT#
H_CPU_SVIDDAT
1127 130R change to 110R 1203 110R change to 130R
C C
1109_modify for
power sequence
A00 0619
1D05V_VTT_PWRGD36,48
B B
1 2
R707
R707 100KR2F-L1-GP
100KR2F-L1-GP
1109 Change net name of R703.2 from H_CPU_SVIDALRT# to VR_SVID_ALERT#
Layout Note:
1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE impedance=50 ohm
3. Lwngth match<25mil
H_VCCST_PWRGD
12
R709
R709 51KR2J-1-GP
51KR2J-1-GP
A00 0619
VCC_SENSE46
VR_SVID_ALERT#46
H_CPU_SVIDCLK46 H_CPU_SVIDDAT46
H_VR_ENABLE46
IMVP_PWRGD_R
1D05S_VCCST
VCC_CORE
R702
R702
100R2F-L1-GP-U
100R2F-L1-GP-U
R705 150R2J-L1-GP-UR705 150R2J-L1-GP-U
1 2
HSW_ULT_DDR3L
HSW ULT POWER
HSW ULT POWER
12 OF 19
12 OF 19
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57
VCC_CORE
A00 0619
PR714
PR714
1 2
0R2J-2-GP
0R2J-2-GP
PD701
PD701
DY
DY
Do Not Stuff
Do Not Stuff
H_VR_ENABLE
KA
DY
DY
DY
DY
12
12
R710
R710 Do Not Stuff
Do Not Stuff
PC706
PC706 Do Not Stuff
Do Not Stuff
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
CPU (VCC_CORE)
CPU (VCC_CORE)
CPU (VCC_CORE)
Hadley 17"
Hadley 17"
Hadley 17"
7 102Tuesday, June 25, 2013
7 102Tuesday, June 25, 2013
7 102Tuesday, June 25, 2013
1
A00
A00
A00
R711
R711
1 2
Do Not Stuff
Do Not Stuff
A A
5
1D05S_VCCST1D05V_S0
12
DY
DY
12
C703
C703
C701
C701
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
4
IMVP_PWRGD24,46
1 2
R713
R713 100KR2F-L1-GP
100KR2F-L1-GP
IMVP_PWRGD_L IMVP_PWRGD_R
C704
C704
Do Not Stuff
Do Not Stuff
12
12
R712
R712
47KR2F-GP
47KR2F-GP
DY
DY
3
5
4
3
2
1
SSID = CPU
D D
HSW_ULT_DDR3L
CPU1A
CPU1A
HSW_ULT_DDR3L
1 OF 19
1 OF 19
HDMI_DATA2#54
HDMI_DATA254
HDMI
HDMI_DATA1#54
HDMI_DATA154
HDMI_DATA0#54
HDMI_DATA054
HDMI_CLK#54
HDMI_CLK54
C C
C54 C55
B58
C58
B55 A55 A57 B57
C51 C50 C53
B54
C49
B50 A53 B53
HASWELL-6-GP
HASWELL-6-GP
DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3
DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3
EDPDDI
EDPDDI
EDP_RCOMP
EDP_DISP_UTIL
EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1
EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3
EDP_AUXN EDP_AUXP
C45 B46 A47 B47
C47 C46 A49 B49
A45 B45
D20 A43
EDP_TX0_DN 53 EDP_TX0_DP 53 EDP_TX1_DN 53 EDP_TX1_DP 53
EDP_AUX_DN 53 EDP_AUX_DP 53
EDP_COMP EDP_BRIGHTNESS
R801
R801
24D9R2F-L-GP
24D9R2F-L-GP
1
TP801TP801
+VCCIOA_OUT
Design Guideline:
12
EDP_COMP keep routing length max 100 mils. Trace Width:20 mils.
B B
UMA
UMA
A A
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
e Document Number Rev
Size Document Number Rev
Size Document Number Rev
Siz
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (DDI/EDP)
CPU (DDI/EDP)
CPU (DDI/EDP)
Hadley 17"
Hadley 17"
Hadley 17"
8 102Tuesday, June 25, 2013
8 102Tuesday, June 25, 2013
8 102Tuesday, June 25, 2013
A00
A00
A00
5
4
3
2
1
SSID = CPU
HSW_ULT_DDR3L
CPU1P
CPU1P
D D
C C
B B
D33
VSS
D34
VSS
D35
VSS
D37
VSS
D38
VSS
D39
VSS
D41
VSS
D42
VSS
D43
VSS
D45
VSS
D46
VSS
D47
VSS
D49
VSS
D5
VSS
D50
VSS
D51
VSS
D53
VSS
D54
VSS
D55
VSS
D57
VSS
D59
VSS
D62
VSS
D8
VSS
E11
VSS
E17
VSS
F20
VSS
F26
VSS
F30
VSS
F34
VSS
F38
VSS
F42
VSS
F46
VSS
F50
VSS
F54
VSS
F58
VSS
F61
VSS
G18
VSS
G22
VSS
G3
VSS
G5
VSS
G6
VSS
G8
VSS
H13
VSS
HASWELL-6-GP
HASWELL-6-GP
HSW_ULT_DDR3L
16 OF 19
16 OF 19
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS
VSS_SENSE
VSS
H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63
V58 AH46 V23 E62 AH16
VSS_SENSE
12
VSS_SENSE 46
Layout Note:
R901
R901
100R2F-L1-GP-U
100R2F-L1-GP-U
1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE impedance=50 ohm
3. Lwngth match<25mil
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
CPU (VSS)
CPU (VSS)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
CPU (VSS)
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Hadley 17"
Hadley 17"
Hadley 17"
9 102Tuesday, June 25, 2013
9 102Tuesday, June 25, 2013
9 102Tuesday, June 25, 2013
1
A00
A00
A00
5
4
3
2
1
SSID = CPU
1D35V_S3
D D
C1001
SC10U6D3V3MX-GP
C1001
SC10U6D3V3MX-GP
12
12
12
12
C1017
C1017
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
C C
C1003
SC10U6D3V3MX-GP
C1003
SC10U6D3V3MX-GP
C1002
SC10U6D3V3MX-GP
C1002
SC10U6D3V3MX-GP
12
12
C1018
C1018
DY
DY
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
C1004
SC10U6D3V3MX-GP
C1004
SC10U6D3V3MX-GP
12
12
12
C1020
C1020
C1019
C1019
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
C1006
SC10U6D3V3MX-GP
C1006
C1005
C1005
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
12
Layout Note:
Direct tie to CPU VccIn/Vss balls
Layout Note:
As close to CPU as possible
B B
A A
5
4
3
2
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet
CPU(Power CAP1)
CPU(Power CAP1)
CPU(Power CAP1)
Hadley 17"
Hadley 17"
Hadley 17"
10 102Tuesday, June 25, 2013
10 102Tuesday, June 25, 2013
10 102Tuesday, June 25, 2013
1
of
A00
A00
A00
5
4
3
2
1
MAX: 1.92A
1D05V_HSIO +V1.05DX_MODPHY_PCH
D D
R1101
R1101
1 2
Do Not Stuff
Do Not Stuff
X01 0313
C1102
SC1U6D3V2KX-GP
C1102
SC1U6D3V2KX-GP
C1101
SC1U6D3V2KX-GP
C1101
12
SC1U6D3V2KX-GP
12
L1101 IND-2D2UH-196-GP
L1101 IND-2D2UH-196-GP
1 2
68.2R21D.10R
68.2R21D.10R
C1103
C1103
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
+V1.05S_AUSB3PLL1D05V_HSIO
+V1.05S_AUSB3PLL
C1104
SC10U6D3V3MX-GP
C1104
SC10U6D3V3MX-GP
12
C1123
12
Do Not StuffDYC1123
Do Not Stuff
1D05V_HSIO +V1.05S_ASATA3PLL
L1102 IND-2D2UH-196-GP
L1102 IND-2D2UH-196-GP
1 2
68.2R21D.10R
68.2R21D.10R
12
+V1.05S_ASATA3PLL
C1106
C1105
C1105
C1106
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C1107
Do Not StuffDYC1107
Do Not Stuff
12
DY
DY
CAP need close to pin K9 L10
+V1.05S_APLLOPI1D05V_S0
R1102
R1102
C C
1 2
Do Not Stuff
Do Not Stuff
X01 0313
CAP need close to pin AA21
IND-2D2UH-196-GP
IND-2D2UH-196-GP L1104
L1104
B B
1 2
68.2R21D.10R
68.2R21D.10R
+V1.05S_AXCK_LCPLL1D05V_S0
12
+V1.05S_APLLOPI
12
C1113
SC1U6D3V2KX-GP
C1113
SC1U6D3V2KX-GP
12
C1110
SC10U6D3V3MX-GP
C1110
C1109
SC1U6D3V2KX-GP
C1109
SC1U6D3V2KX-GP
SC10U6D3V3MX-GP
12
1205 Add
1D05V_S0 +1.05M_ASW +V1.05S_CORE_PCH1D05V_S0
C1114
Do Not StuffDYC1114
Do Not Stuff
CAP need close to pin B18 CAP need close to pin B11
3D3V_S5_PCH +V3.3A_PSUS
R1103 Do Not StuffR1103 Do Not Stuff
C1124
Do Not StuffDYC1124
Do Not Stuff
12
DSW 20121019
1 2
X02 0510
1205 Add
C1108
SC10U6D3V3MX-GP
C1108
SC10U6D3V3MX-GP
12
1D05V_S0 +V1.05S_AXCK_DCB
L1103 IND-2D2UH-196-GP
L1103 IND-2D2UH-196-GP
1 2
68.2R21D.10R
68.2R21D.10R
DY
CAP need close to pin AC9 CAP need close to pin J18
R1104
R1104
1 2
Do Not Stuff
Do Not Stuff
X01 0313 X01 0313
C1115
Do Not StuffDYC1115
Do Not Stuff
C1116
SC1U6D3V2KX-GP
C1116
12
SC1U6D3V2KX-GP
12
DY
R1105
R1105
1 2
Do Not Stuff
Do Not Stuff
C1118
SC1U6D3V2KX-GP
C1118
SC1U6D3V2KX-GP
C1117
SC1U6D3V2KX-GP
C1117
SC1U6D3V2KX-GP
12
12
C1119
SC10U6D3V3MX-GP
C1119
SC10U6D3V3MX-GP
12
DY
+V1.05S_AXCK_DCB
C1112
Do Not StuffDYC1112
DY
Do Not Stuff
12
C1125
Do Not StuffDYC1125
Do Not Stuff
12
DY
C1111
SC1U6D3V2KX-GP
C1111
SC1U6D3V2KX-GP
12
1205 Add
RTC_AUX_S5
C1122
SC1U6D3V2KX-GP
C1122
C1120
Do Not StuffDYC1120
Do Not Stuff
C1121
12
C1121
12
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
DY
CAP need close to pin A20 CAP need close to pin AE9
A A
5
4
CAP need close to pin AE8 J11
UMA
UMA
UMA
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
3
Date: Sheet of
2
CAP need close to pin AG10
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU(Power CAP2)
CPU(Power CAP2)
CPU(Power CAP2)
A00
A00
Hadley 17"
Hadley 17"
Hadley 17"
11 102Tuesday, June 25, 2013
11 102Tuesday, June 25, 2013
11 102Tuesday, June 25, 2013
1
A00
5
4
3
2
1
SSID = MEMORY
DM1
M_A_A[15 :0]5
D D
M_A_BS25
Layout Note:
Place these cap s close to VREF_C A
M_VREF_ CA_DIMMA
12
12
DY
DY
Layout Note:
Place these cap s close to VREF_D Q
M_VREF_ DQ_DIMMA
C C
12
0D675V _S0
12
DY
DY
Layout Note:
Place these cap s close to VTT1 a nd VTT2.
B B
Layout Note:
All VREF traces should have width=20mi l; spacing=20 mil
12
DY
DY
DY
DY
C1201
C1201
C1218
C1218
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
12
C1205
C1205
DY
DY
DY
DY
Do Not Stuff
Do Not Stuff
C1204
C1204
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
C1215
C1215
C1214
C1214
C1216
C1216
DY
DY
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
M_A_BS05 M_A_BS15
M_A_DQ[6 3:0]5
C1202
C1202
Do Not Stuff
Do Not Stuff
C1206
C1206
Do Not Stuff
Do Not Stuff
M_A_DQS #[7:0]5
M_A_DQS [7:0]5
M_VREF_ CA_DIMMA M_VREF_ DQ_DIMMA
DDR3_D RAMRST#4,13
C1217
Do Not StuffDYC1217
Do Not Stuff
M_A_DIMA _ODT0 M_A_DIMA _ODT1
12
DY
M_A_DQ1 3 M_A_DQ8 M_A_DQ1 4 M_A_DQ1 0 M_A_DQ9 M_A_DQ1 2 M_A_DQ1 5 M_A_DQ1 1 M_A_DQ2 9 M_A_DQ2 8 M_A_DQ3 0 M_A_DQ3 1 M_A_DQ2 5 M_A_DQ2 4 M_A_DQ2 7 M_A_DQ2 6 M_A_DQ4 4 M_A_DQ4 1 M_A_DQ4 3 M_A_DQ4 7 M_A_DQ4 5 M_A_DQ4 0 M_A_DQ4 2 M_A_DQ4 6 M_A_DQ5 1 M_A_DQ5 0 M_A_DQ4 9 M_A_DQ4 8 M_A_DQ5 2 M_A_DQ5 3 M_A_DQ5 4 M_A_DQ5 5 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ6 M_A_DQ5 M_A_DQ4 M_A_DQ3 M_A_DQ7 M_A_DQ2 1 M_A_DQ2 0 M_A_DQ1 7 M_A_DQ1 6 M_A_DQ1 8 M_A_DQ1 9 M_A_DQ2 2 M_A_DQ2 3 M_A_DQ3 6 M_A_DQ3 3 M_A_DQ3 4 M_A_DQ3 8 M_A_DQ3 7 M_A_DQ3 2 M_A_DQ3 5 M_A_DQ3 9 M_A_DQ6 2 M_A_DQ5 8 M_A_DQ6 0 M_A_DQ6 1 M_A_DQ6 3 M_A_DQ5 9 M_A_DQ5 6 M_A_DQ5 7
M_A_DQS #1 M_A_DQS #3 M_A_DQS #5 M_A_DQS #6 M_A_DQS #0 M_A_DQS #2 M_A_DQS #4 M_A_DQS #7
M_A_DQS 1 M_A_DQS 3 M_A_DQS 5 M_A_DQS 6 M_A_DQS 0 M_A_DQS 2 M_A_DQS 4 M_A_DQS 7
0D675V _S0
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
close to dimm
98 97 96 95 92 91 90 86 89 85
107
84 83
119
80 78 79
109 108
5
7 15 17
4
6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70
129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194
10 27 45 62
135 152 169 186
12 29 47 64
137 154 171 188
116 120
126
1 30
203 204
DM1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2
BA0 BA1
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
ODT0 ODT1
VREF_CA VREF_DQ
RESET#
VTT1 VTT2
DDR3-20 4P-119-G P-U
DDR3-20 4P-119-G P-U
62.10017.Z81
62.10017.Z81
EVENT# VDDSPD
NC#/TEST
VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18
NP1
NP1
NP2
NP2
110
RAS#
113
WE#
115
CAS#
114
CS0#
121
CS1#
73
CKE0
74
CKE1
101
CK0
103
CK0#
102
CK1
104
CK1#
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
200
SDA
202
SCL
198 199
SA0_DI MA
197
SA0
SA1_DI MA
201
SA1
77
NC#1
122
NC#2
125 75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100 105 106 111 112 117 118 123 124
2
VSS
3
VSS
8
VSS
9
VSS
13
VSS
14
VSS
19
VSS
20
VSS
25
VSS
26
VSS
31
VSS
32
VSS
37
VSS
38
VSS
43
VSS
44
VSS
48
VSS
49
VSS
54
VSS
55
VSS
60
VSS
61
VSS
65
VSS
66
VSS
71
VSS
72
VSS
127
VSS
128
VSS
133
VSS
134
VSS
138
VSS
139
VSS
144
VSS
145
VSS
150
VSS
151
VSS
155
VSS
156
VSS
161
VSS
162
VSS
167
VSS
168
VSS
172
VSS
173
VSS
178
VSS
179
VSS
184
VSS
185
VSS
189
VSS
190
VSS
195
VSS
196
VSS
205
VSS
206
VSS
1D35V_ S3
M_A_RAS # 5 M_A_WE # 5 M_A_CAS # 5
M_A_DIMA _CS#0 5 M_A_DIMA _CS#1 5
M_A_DIMA _CKE0 5 M_A_DIMA _CKE1 5
M_A_DIMA _CLK_D DR0 5 M_A_DIMA _CLK_D DR#0 5
M_A_DIMA _CLK_D DR1 5 M_A_DIMA _CLK_D DR#1 5
PCH_SMBD ATA 13,18,58 ,62,67 PCH_SMBC LK 13,18,58 ,62,67
3D3V_S 0
12
C1203
C1203
Do Not Stuff
Do Not Stuff
DY
DY
X02 0417 DY C1201 C1202 C1206 C1212 C1214 C1216 C1218 C1220 C1221 based on RMT test result.
1D35V_ S3
Remove
Layout Note:
Place these Cap s near SO-DIMM A.
X02 0510
DDR_PG _CTRL4
1 2
Do Not Stuff
Do Not Stuff
Q1201 Need check Vth=1V
SA0_DI MA SA1_DI MA
12
R1201
R1201
Do Not Stuff
Do Not Stuff
C1207
Do Not StuffDYC1207
Do Not Stuff
C1209
SC10U6D3V3MX-GP
C1209
SC10U6D3V3MX-GP
C1208
SC10U6D3V3MX-GP
C1208
SC10U6D3V3MX-GP
12
12
12
DY
12
12
12
12
C1210
C1210
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DDR_PG _CTRL_ R
R1205
R1205
C1213
C1213
C1212
C1212
C1211
C1211
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1D35V_ S3
G
Q1201
Q1201 DMN5L06K -7-GP
DMN5L06K -7-GP
84.05067.031
84.05067.031
Note: SA0 DIM0 = 0, SA1_DIM0 = 0
12
C1221
C1221
DY
DY
Do Not Stuff
Do Not Stuff
SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30
12
C1222
C1222
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
5V_S5
12
R1208
R1208 220KR2 J-L2-GP
220KR2 J-L2-GP
DDR_VT T_PG_C TRL
12
R1204
R1204 Do Not Stuff
Do Not Stuff
DY
DY
Layout Note:
Place Close SO- DIMMA.
DDR_W R_VREF 015
1D35V_ S3
D
Q1202
Q1202 2N7002K -2-GP
2N7002K -2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
S
G
M_A_B_D IMM_ODT
DDR_VT T_PG_C TRL 49
12
R1215
R1215
Do Not Stuff
Do Not Stuff
DY
DY
2R2F-GP
2R2F-GP R1210
R1210
1 2
12
C1219
C1219 SCD022 U16V2JX -GP
SCD022 U16V2JX -GP
+V_VREF _PATH1
12
R1212
R1212 24D9R2 F-L-GP
24D9R2 F-L-GP
R1206 66D5R2F-GPR1206 66D5R2F-GP
1 2
R1207 66D5R2F-GPR1207 66D5R2F-GP
1 2
R1203 66D5R2F-GPR1203 66D5R2F-GP
1 2
R1209 66D5R2F-GPR1209 66D5R2F-GP
1 2
1D35V_ S30D675V _VTTRE F
12
R1211
R1211 1K8R2F -GP
1K8R2F -GP
M_B_DIMB _ODT0 13 M_B_DIMB _ODT1 13
M_VREF_ DQ_DIMMA
12
R1213
R1213 1K8R2F -GP
1K8R2F -GP
M_A_DIMA _ODT0 M_A_DIMA _ODT1
12
R1202
R1202 Do Not Stuff
Do Not Stuff
12
C1220
C1220
DY
DY
Do Not Stuff
Do Not Stuff
DS
A A
UMA
UMA
UMA
Title
Title
Title
Size Document Numb er Re v
Size Document Numb er Re v
Size Document Numb er Re v Custom
Custom
Custom
Tuesday, June 2 5, 2013
Tuesday, June 2 5, 2013
Tuesday, June 2 5, 2013
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, S ec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, S ec.1, Hsin Tai W u Rd., Hsichih,
21F, 88, S ec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 22 1, Taiwan, R.O.C.
Taipei Hsien 22 1, Taiwan, R.O.C.
Taipei Hsien 22 1, Taiwan, R.O.C.
DDR3L-SODIMM1
DDR3L-SODIMM1
DDR3L-SODIMM1
Hadley 17"
Hadley 17"
Hadley 17"
12 102
12 102
12 102
A00
A00
A00
5
4
3
2
1
SSID = MEMORY
DM2
M_B_A[15:0]5
D D
Layout Note:
Place these caps close to VREF_CA
M_VREF_CA_D IMMB
12
C1301
C1301
X02 0417 DY C1302 C1304 C1306, POP C1305 based on RMT test result.
Layout Note:
Place these caps
C C
Layout Note:
Place these caps close to VTT1 and VTT2.
B B
close to VREF_DQ
M_VREF_DQ_D IMMB
12
C1305
C1305
0D675V_S0
12
C1316
C1316
DY
DY
Do Not Stuff
Do Not Stuff
Layout Note:
All VREF traces should have width=20mil; spacing=20 mil
12
12
DY
DY
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
DY
DY
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
12
C1302
C1302
EC1302
EC1302
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
DY
DY
C1304
C1304
C1306
C1306
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
C1318
C1318
C1317
C1317
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
M_B_BS25 M_B_BS05
M_B_BS15
M_B_DQ[63:0]5
M_B_DQS#[7:0]5
M_B_DQS[7:0]5
M_B_DIMB_ODT012 M_B_DIMB_ODT112
M_VREF_CA_D IMMB M_VREF_DQ_D IMMB
DDR3_DR AMRST#4,12
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
M_B_DQ8 M_B_DQ14 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ9 M_B_DQ13 M_B_DQ15 M_B_DQ28 M_B_DQ29 M_B_DQ26 M_B_DQ27 M_B_DQ25 M_B_DQ24 M_B_DQ30 M_B_DQ31 M_B_DQ40 M_B_DQ41 M_B_DQ46 M_B_DQ42 M_B_DQ45 M_B_DQ44 M_B_DQ47 M_B_DQ43 M_B_DQ56 M_B_DQ57 M_B_DQ59 M_B_DQ58 M_B_DQ61 M_B_DQ60 M_B_DQ63 M_B_DQ62 M_B_DQ4 M_B_DQ1 M_B_DQ3 M_B_DQ7 M_B_DQ5 M_B_DQ0 M_B_DQ2 M_B_DQ6 M_B_DQ32 M_B_DQ37 M_B_DQ38 M_B_DQ34 M_B_DQ33 M_B_DQ36 M_B_DQ39 M_B_DQ35 M_B_DQ17 M_B_DQ16 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ23 M_B_DQ22 M_B_DQ52 M_B_DQ49 M_B_DQ48 M_B_DQ53 M_B_DQ51 M_B_DQ55 M_B_DQ54 M_B_DQ50
M_B_DQS#1 M_B_DQS#3 M_B_DQS#5 M_B_DQS#7 M_B_DQS#0 M_B_DQS#4 M_B_DQS#2 M_B_DQS#6
M_B_DQS1 M_B_DQS3 M_B_DQS5 M_B_DQS7 M_B_DQS0 M_B_DQS4 M_B_DQS2 M_B_DQS6
C1319
Do Not StuffDYC1319
Do Not Stuff
0D675V_S0
12
DY
close to dimm
A A
98 97 96 95 92 91 90 86 89 85
107
84 83
119
80 78 79
109 108
5
7 15 17
4
6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70
129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194
10 27 45 62
135 152 169 186
12 29 47 64
137 154 171 188
116 120
126
1 30
203 204
DM2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2
BA0 BA1
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
ODT0 ODT1
VREF_CA VREF_DQ
RESET#
VTT1 VTT2
DDR3-204P- 90-GP
DDR3-204P- 90-GP
RAS# CAS# CS0#
CS1# CKE0
CKE1
CK0#
CK1#
EVENT#
VDDSPD
NC#1 NC#2
NC#/TEST
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8
VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18
NP1
NP1
NP2
NP2
110 113
WE#
115 114
121 73
74 101
CK0
103 102
CK1
104 11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
200
SDA
202
SCL
198 199
SA0_DIMB
197
SA0
SA1_DIMB
201
SA1
77 122 125
75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124
2
VSS
3
VSS
8
VSS
9
VSS
13
VSS
14
VSS
19
VSS
20
VSS
25
VSS
26
VSS
31
VSS
32
VSS
37
VSS
38
VSS
43
VSS
44
VSS
48
VSS
49
VSS
54
VSS
55
VSS
60
VSS
61
VSS
65
VSS
66
VSS
71
VSS
72
VSS
127
VSS
128
VSS
133
VSS
134
VSS
138
VSS
139
VSS
144
VSS
145
VSS
150
VSS
151
VSS
155
VSS
156
VSS
161
VSS
162
VSS
167
VSS
168
VSS
172
VSS
173
VSS
178
VSS
179
VSS
184
VSS
185
VSS
189
VSS
190
VSS
195
VSS
196
VSS
205
VSS
206
VSS
1D35V_S3
M_B_RAS# 5 M_B_WE# 5 M_B_CAS# 5
M_B_DIMB_CS#0 5 M_B_DIMB_CS#1 5
M_B_DIMB_CKE0 5 M_B_DIMB_CKE1 5
M_B_DIMB_CLK_DD R0 5 M_B_DIMB_CLK_DD R#0 5
M_B_DIMB_CLK_DD R1 5 M_B_DIMB_CLK_DD R#1 5
PCH_SMBDAT A 12,18,58,62,67 PCH_SMBCLK 12,18,58,62,67
12
DY
DY
C1303
C1303
Do Not Stuff
Do Not Stuff
1D35V_S3
Layout Note:
Place these Caps near SO-DIMMA.
Layout Note:
Place Close SO-DIMMA.
DDR_W R_VREF025
3D3V_S0
12
DY
12
Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34
C1311
Do Not StuffDYC1311
Do Not Stuff
12
DY
DY
12
C1314
C1314
Do Not Stuff
Do Not Stuff
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
0D675V_VTTRE F 1D35V_S3
R1308
R1308
Do Not Stuff
Do Not Stuff
2R2F-GP
2R2F-GP R1304
R1304
1 2
C1320
C1320 SCD022U16V2JX -GP
SCD022U16V2JX -GP
R1307
R1307 24D9R2F-L-G P
24D9R2F-L-G P
C1310
12
12
C1315
C1315
12
DY
DY
C1312
Do Not StuffDYC1312
Do Not Stuff
C1313
C1313
12
+V_VREF_PATH 2
12
3D3V_S0
12
R1301
R1301 10KR2J-3-GP
10KR2J-3-GP
SA1_DIMB SA0_DIMB
12
R1302
R1302 Do Not Stuff
Do Not Stuff
X01 0313
C1307
SC10U6D3V3MX-GP
C1307
Do Not StuffDYC1310
Do Not Stuff
C1309
Do Not StuffDYC1309
Do Not Stuff
12
SC10U6D3V3MX-GP
C1308
SC10U6D3V3MX-GP
C1308
SC10U6D3V3MX-GP
12
12
DY
12
EC1301
EC1301
Do Not Stuff
Do Not Stuff
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
R1306
R1306 1K8R2F-GP
1K8R2F-GP
12
R1303
R1303 1K8R2F-GP
1K8R2F-GP
M_VREF_DQ_D IMMB
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev A2
A2
A2
Tuesday, June 25, 2013
Tuesday, June 25, 2013
Tuesday, June 25, 2013
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O. C.
DDR3L-SODIMM2
DDR3L-SODIMM2
DDR3L-SODIMM2
Hadley 17"
Hadley 17"
Hadley 17"
1
13 102
13 102
13 102
A00
A00
A00
5
D D
C C
4
3
2
1
B B
A A
5
4
3
2
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
M1&M3
M1&M3
M1&M3
Hadley 17"
Hadley 17"
Hadley 17"
14 102Tuesday, June 25, 2013
14 102Tuesday, June 25, 2013
14 102Tuesday, June 25, 2013
1
A00
A00
A00
5
4
3
2
1
SSID = CPU
D D
1204: Change R1507 PL 100K
DY
DY
1 2
R1507
R1507 Do Not Stuff
Do Not Stuff
C C
0102 Remove
RN1504
RN1504
1 2 3
OPS
OPS
Do Not Stuff
Do Not Stuff
R1509
R1509
1 2
100KR2J-1-GP
100KR2J-1-GP
L_BKLT_CTRL
DGPU_PW R_EN
4
DGPU_HOLD_RST#
DGPU_PW ROK
HDD_FALL_INT67
L_BKLT_CTRL53
R1503
R1503
DGPU_PW R_EN82,83 DGPU_HOLD_RST#73
DGPU_PW ROK24,82,83
1210 Add TP
TP1503TP1503 TP1504TP1504
DY
DY
1 2
Do Not Stuff
Do Not Stuff
TP1501TP1501 TP1505TP1505
TP1502TP1502
eDP_BKLEN
1
eDP_VDDEN
1
PIRQA# PIRQB# PIRQC# PIRQD# PCI_PME#
1
MCP_GPIO55
1
DGPU_PW R_EN DGPU_HOLD_RST# DGPU_PW ROK
PCH_SD_CD#
1
AD4
B8 A9 C6
U6 P4 N4 N2
U7 L1 L3 R5 L4
CPU1I
CPU1I
EDP_BKLCTL EDP_BKLEN EDP_VDDEN
PIRQA#/GPIO77 PIRQB#/GPIO78 PIRQC#/GPIO79 PIRQD#/GPIO80 PME#
GPIO55 GPIO52 GPIO54 GPIO51 GPIO53
eDP SIDEBAND
eDP SIDEBAND
PCIE
PCIE
HSW_ULT_DDR3L
HSW_ULT_DDR3L
DISPLAY
DISPLAY
9 OF 19
9 OF 19
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP
DDPB_HPD DDPC_HPD
EDP_HPD
B9 C9 D9 D11
C5 B6 B5 A6
C8 A8 D6
3D3V_S0
1
23
4
RN1501
RN1501 SRN2K2J-1-GP
SRN2K2J-1-GP
PCH_HDMI_CLK 54 PCH_HDMI_DATA 54
HDMI_PCH_DET 54 EDP_HPD 53
3D3V_S0
B B
A A
5
RN1505
RN1505
8 7 6
SRN10KJ-6-GP
SRN10KJ-6-GP
PIRQA# PIRQC#
PIRQB#
1
FFS_INT2
2
CLK_PCIE_WLAN_REQ3#
3
PIRQD#
45
PIRQA# 18 PIRQC# 18
FFS_INT2 20,67
CLK_PCIE_WLAN_REQ3# 18,58
4
3
HASWELL-6-GP
HASWELL-6-GP
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU ( EDP SIDEBAND/GPIO/DDI )
CPU ( EDP SIDEBAND/GPIO/DDI )
CPU ( EDP SIDEBAND/GPIO/DDI )
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Hadley 17"
Hadley 17"
Hadley 17"
A00
A00
15 102Tuesday, June 25, 2013
15 102Tuesday, June 25, 2013
15 102Tuesday, June 25, 2013
1
A00
5
SSID = CPU
4
3
2
1
D D
CPU_RXN_C_dGPU_TXN073 CPU_RXP_C_dGPU_TXP073
dGPU_RXN_C_CPU_TXN073 dGPU_RXP_C_CPU_TXP073
CPU_RXN_C_dGPU_TXN173 CPU_RXP_C_dGPU_TXP173
dGPU_RXN_C_CPU_TXN173 dGPU_RXP_C_CPU_TXP173
CPU_RXN_C_dGPU_TXN273 CPU_RXP_C_dGPU_TXP273
dGPU_RXN_C_CPU_TXN273 dGPU_RXP_C_CPU_TXP273
CPU_RXN_C_dGPU_TXN373 CPU_RXP_C_dGPU_TXP373
dGPU_RXN_C_CPU_TXN373
C C
B B
1203 Add port4
dGPU_RXP_C_CPU_TXP373 PCIE_PRX_WLANTX_N358
PCIE_PRX_WLANTX_P358 PCIE_PTX_WLANRX_N3_C58
PCIE_PTX_WLANRX_P3_C58 PCIE_PRX_LANTX_N430
PCIE_PRX_LANTX_P430 PCIE_PTX_LANRX_N4_C30
PCIE_PTX_LANRX_P4_C30
+V1.05S_AUSB3PLL
Do Not Stuff
Do Not Stuff C1606
C1606
1 2
OPS
OPS
1 2
OPS
OPS
C1605
C1605 Do Not Stuff
Do Not Stuff Do Not Stuff
Do Not Stuff C1608
C1608
1 2
OPS
OPS
1 2
OPS
OPS
C1607
C1607 Do Not Stuff
Do Not Stuff Do Not Stuff
Do Not Stuff C1610
C1610
1 2
OPS
OPS
1 2
OPS
OPS
C1609
C1609 Do Not Stuff
Do Not Stuff Do Not Stuff
Do Not Stuff C1612
C1612
1 2
OPS
OPS
1 2
OPS
OPS
C1611
C1611 Do Not Stuff
Do Not Stuff
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1601
C1601
1 2 1 2
C1602
C1602 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1603
C1603
1 2 1 2
C1604
C1604 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
USB3_PRX_DTX_N263
USB3_PRX_DTX_P263
USB3_PTX_DRX_N263
USB3_PTX_DRX_P263
USB3_PRX_DTX_N363
USB3_PRX_DTX_P363
USB3_PTX_DRX_N363
USB3_PTX_DRX_P363
R1601
R1601
3KR2F-GP
3KR2F-GP
1 2
Layout Note:
1. PCIE_RCOMP/ PCIE_IREF trace width=12~15mil Isolation Spacing: 12mil
2.
3. Total trace length<500mil
dGPU_RXN_CPU_TXN0 dGPU_RXN_CPU_TXP0
dGPU_RXN_CPU_TXN1 dGPU_RXP_CPU_TXP1
dGPU_RXN_CPU_TXN2 dGPU_RXN_CPU_TXP2
dGPU_RXN_CPU_TXN3 dGPU_RXN_CPU_TXP3
PCIE_PTX_WLANRX_N3 PCIE_PTX_WLANRX_P3
PCIE_PTX_LANRX_N4 PCIE_PTX_LANRX_P4
PCIE_RCOMP
CPU1K
CPU1K
F10
PERN5_L0
E10
PERP5_L0
C23
PETN5_L0
C22
PETP5_L0
F8
PERN5_L1
E8
PERP5_L1
B23
PETN5_L1
A23
PETP5_L1
H10
PERN5_L2
G10
PERP5_L2
B21
PETN5_L2
C21
PETP5_L2
E6
PERN5_L3
F6
PERP5_L3
B22
PETN5_L3
A21
PETP5_L3
G11
PERN3
F11
PERP3
C29
PETN3
B30
PETP3
F13
PERN4
G13
PERP4
B29
PETN4
A29
PETP4
G17
PERN1/USB3RN3
F17
PERP1/USB3RP3
C30
PETN1/USB3TN3
C31
PETP1/USB3TP3
F15
PERN2/USB3RN4
G15
PERP2/USB3RP4
B31
PETN2/USB3TN4
A31
PETP2/USB3TP4
E15
RSVD#E15
E13
RSVD#E13
A27
PCIE_RCOMP
B27
PCIE_IREF
WL
AN
LAN + Card Reader
HASWELL-6-GP
HASWELL-6-GP
HSW_ULT_DDR3L
HSW_ULT_DDR3L
PCIE USB
PCIE USB
11 OF 19
11 OF 19
USB2N0 USB2P0
USB2N1 USB2P1
USB2N2 USB2P2
USB2N3 USB2P3
USB2N4 USB2P4
USB2N5 USB2P5
USB2N6 USB2P6
USB2N7 USB2P7
USB3RN1 USB3RP1
USB3TN1 USB3TP1
USB3RN2 USB3RP2
USB3TN2 USB3TP2
USBRBIAS#
USBRBIAS RSVD#AN10 RSVD#AM10
OC0/GPIO40# OC1/GPIO41# OC2/GPIO42# OC3/GPIO43#
AN8 AM8
AR7 AT7
AR8 AP8
AR10 AT10
AM15 AL15
AM13 AN13
AP11 AN11
AR13 AP13
G20 H20
C33 B34
E18 F18
B33 A33
AJ10 AJ11 AN10 AM10
AL3 AT1 AH2 AV3
USB_PN7 USB_PP7
USB_COMP
USB_OC#0_1 USB_OC#2_3 USB_OC#4_5 USB_OC#6_7
MCP_GPIO7318
USB_PN0 34 USB_PP0 34
USB_PN1 35 USB_PP1 35
USB_PN2 63 USB_PP2 63
USB_PN3 63 USB_PP3 63
USB_PN4 52 USB_PP4 52
USB_PN5 58 USB_PP5 58
USB_PN6 52 USB_PP6 52
TP1601TP1601
1
TP1602TP1602
1
1 2
R1602
R1602 22D6R2F-L1-GP
22D6R2F-L1-GP
USB3_PRX_CTX_N0 34 USB3_PRX_CTX_P0 34
USB3_PTX_CRX_N0 34 USB3_PTX_CRX_P0 34
USB3_PRX_CTX_N1 34 USB3_PRX_CTX_P1 34
USB3_PTX_CRX_N1 34 USB3_PTX_CRX_P1 34
USB_OC#0_1 18,35 USB_OC#2_3 35
MCP_GPIO73 USB_OC#6_7 USB_OC#2_3 USB_OC#4_5
USB 2.0 Table
Pair
Device
USB3.0 port1
0
USB3.0 Port2
1
(with Power Share) USB3.0 Port3
2
USB3.0 Port4
3
CAMERA
4
WLAN
5
Touch Panel
6
NC
7
Layout Note:
1. USB_COMP using 50 ohm single-ended impedance
2. Isolation Spacing :15mil
3. Total trace length<500mil
DSW 20121019
3D3V_S5_PCH
RN1601
RN1601
1
8
2
7
3
6
4 5
SRN10KJ-6-GP
SRN10KJ-6-GP
PCIE Table
Port
1
2
3
A A
4
5(4lane)
6(4lane)
5
Device
TBD
TBD
WLAN
LAN
TBD
TBD
Share BUS
USB3.0_3
USB3.0_4
SATA0~3
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
CPU (PCIE/USB)
CPU (PCIE/USB)
CPU (PCIE/USB)
Hadley 17"
Hadley 17"
Hadley 17"
16 102Tuesday, June 25, 2013
16 102Tuesday, June 25, 2013
16 102Tuesday, June 25, 2013
1
A00
A00
A00
5
SSID = CPU
4
3
2
1
0116: modify for OBFF & wake up
D D
RN1703
RN1703 SRN10KJ-5-GP
SRN10KJ-5-GP
1
4
2 3 1 2
DY
DY
R1717 Do Not Stuff
R1717 Do Not Stuff
PM_PCH_PWROK PM_RSMRST#
SYS_PWROK
X01 0311 Remove OBFF circuit.
0104:Reserve For EMI
XDP_DBRESET#
C C
B B
PCH_PW ROK24,26,36
PM_PWRBTN#24,96 AC_PRESENT24,76
BATLOW #20 PCH_SLP_S0#48 PM_SLP_SUS# 24,38
3D3V_S5
3D3V_S5_PCH
12
EC1702
EC1702
DY
DY
Do Not Stuff
Do Not Stuff
R1706 Do Not StuffR1706 Do Not Stuff
1 2
X02 0510
PLT_RST#24,30,58,65,73
1 2
R1730 10KR2J-3-GPR1730 10KR2J-3-GP
0110 Change
1 2
DY
DY
R1724 Do Not Stuff
R1724 Do Not Stuff
1 2
R1727 10KR2J-3-GPR1727 10KR2J-3-GP
R1715
R1715
Do Not Stuff
Do Not Stuff
AC_PRESENT
0109: ADD
PM_SUS_STAT# PM_SUSW ARN#
R1707
R1707
1 2
Do Not Stuff
Do Not Stuff
TP1705
TP1705 Do Not Stuff
Do Not Stuff
12
DY
DY
X02 0510
12
DY
DY
1
R1713
R1713
1 2
Do Not Stuff
Do Not Stuff C1701
C1701 Do Not Stuff
Do Not Stuff
PM_SUSACK#_R
XDP_DBRESET# SYS_PWROK
PM_PCH_PWROK
MPWROK PCI_PLTRST#
PM_RSMRST#
PM_SUSW ARN#_R
PM_PWRBTN# AC_PRESENT BATLOW # PCH_SLP_S0# PCH_SLP_WLAN#
PCI_PLTRST#
PM_SUSACK#24
PM_SUSW ARN#24
CPU1H
CPU1H
AK2
SUSACK#
AC3
SYS_RESET#
AG2
SYS_PWROK
AY7
PCH_PWROK
AB5
APWROK
AG7
PLTRST#
AW6
RSMRST#
AV4
SUSWARN#/SUSPWRDNACK#/GPIO30
AL7
PWRBTN#
AJ8
ACPRESENT/GPIO31
AN4
BATLOW#/GPIO72
AF3
SLP_S0#
AM5
SLP_WLAN#/GPIO29
HASWELL-6-GP
HASWELL-6-GP
X02 0513
RN1702
RN1702
1 2 3
DS3
DS3
SRN0J-6-GP
SRN0J-6-GP
4
HSW_ULT_DDR3L
HSW_ULT_DDR3L
SYSTEM POWER MANAGEMENT
SYSTEM POWER MANAGEMENT
PM_SUSACK#_R PM_SUSW ARN#_R
3D3V_AUX_S5
R1726
R1726 10KR2J-3-GP
10KR2J-3-GP
1 2
3V_5V_POK# 3V_5V_POK_C
NON DS3
NON DS3
1 2
R1708
R1708 Do Not Stuff
Do Not Stuff
5 6
8 OF 19
8 OF 19
DSWVRMEN
DPWROK
WAKE#
CLKRUN#/GPIO32
SUS_STAT#/GPIO61
SUSCLK/GPIO62 SLP_S5#/GPIO63
SLP_S4# SLP_S3#
SLP_A#
SLP_SUS# SLP_LAN#
Q1701
Q1701
34 2 1
2N7002KDW-GP
2N7002KDW-GP
DSWODVREN
AW7
PCH_DPW ROK PM_RSMRST#
AV5
PCH_WAKE#_R
AJ5
PM_CLKRUN#
V5
PM_SUS_STAT#
AG4
SUS_CLK
AE6
PM_SLP_S5#
AP5
PM_SLP_S4#
AJ6
PM_SLP_S3#
AT4
PM_SLP_A#
AL5
PM_SLP_SUS#
AP4
PM_SLP_LAN#
AJ7
PCH_DPW ROK
Do Not Stuff
Do Not Stuff
100KR2F-L1-GP
100KR2F-L1-GP
0109 change to 100K 1% ohm
1KR2J-1-GP
1KR2J-1-GP R1702
PM_RSMRST#
R1702
1 2
R1728
R1728
1 2
Do Not Stuff
Do Not Stuff
NON DS3
NON DS3
R1729
R1729
1 2
Do Not Stuff
Do Not Stuff
X02 0510
0117: Add R1722 to change Q1703 Gate Voltage To 13V
X01 0311 Change R1705 to 1k and PH to 3D3V_S5
NON DS3
NON DS3
Do Not Stuff
Do Not Stuff R1704
R1704
1 2
1 1
TP1702
TP1702 Do Not Stuff
Do Not Stuff TP1703
TP1703 Do Not Stuff
Do Not Stuff
1 1
TP1704
TP1704 Do Not Stuff
Do Not Stuff TP1707
TP1707 Do Not Stuff
Do Not Stuff
X02 0510
R1718
R1718
1 2
R1725
R1725
1 2
R1705
R1705 1KR2J-1-GP
1KR2J-1-GP
1 2 1 2
12
DS3
DS3
PM_SLP_SUS#
3D3V_S5SYS_PWROK24,96
X02 0510
R1709
R1709 Do Not Stuff
Do Not Stuff R1710
R1710 Do Not Stuff
Do Not Stuff
PM_SLP_S3# 24,36,48,49,51,52
RSMRST#_KBC 24 3V_5V_POK 45
PM_CLKRUN#_EC 24
PCH_SUSCLK_KBC 24
PM_SLP_S4# 24,49
KBC_DPW ROK 24
PCH_SUSCLK_KBC
XDP_DBRESET# PM_CLKRUN#
PCH strap pin:
On Die DSW VR Enable
DSWODVREN
DSWODVREN
0107 Modify
RN1704
RN1704
1 2 3
SRN8K2J-3-GP
SRN8K2J-3-GP
Do Not Stuff
Do Not Stuff
Low = Disable High = Enable (default)
*
Do Not Stuff
Do Not Stuff
3D3V_S0
4
EC1701
EC1701
R1720
R1720
330KR2J-L1-GP
330KR2J-L1-GP
1 2 1 2
DY
DY
R1721
R1721
DY
DY
1 2
RTC_AUX_S5
A A
5
4
3
2
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
e Document Number Rev
Size Document Number Rev
Size Document Number Rev
Siz
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (PM)
CPU (PM)
CPU (PM)
Hadley 17"
Hadley 17"
Hadley 17"
17 102Tuesday, June 25, 2013
17 102Tuesday, June 25, 2013
17 102Tuesday, June 25, 2013
1
A00
A00
A00
5
SSID = CPU
3D3V_S0
D D
C C
B B
LPC_AD[3..0]24,65
RN1801
RN1801
1 2 3 4 5
SRN10KJ-6-GP
SRN10KJ-6-GP
CLK_PCIE_REQ#20
CLK_PCIE_WLAN_N358 CLK_PCIE_WLAN_P358
CLK_PCIE_WLAN_REQ3#15,58
CLK_PCIE_LAN_N430 CLK_PCIE_LAN_P430
CLK_PCIE_LAN_REQ4#20,30
CLK_PCIE_VGA#73 CLK_PCIE_VGA73 PEG_CLKREQ#73
SPI_SI_R24,25
SPI_SO_R24,25
SPI_WP#25 SPI_HOLD#25
0102 change to signal resister
LPC_AD[3..0]
3D3V_S5
PEG_CLKREQ#
8
BOARD_ID1
7
PIRQA#
6
PIRQC#
X01 0314 Change CLKREQ port PCIE port3 use req2 PCIE port4 use req3 PCIE port5 use req4
X01 0320 Change CLKOUT port mapping with REQ port PCIE port3 use CLK2 PCIE port4 use CLK3 PCIE port5 use CLK4
LPC_FRAME#24,65 SPI_CLK_R24,25
SPI_CS0#_R24,25
LPC_AD0 LPC_AD2 LPC_AD1 LPC_AD3
CLK_PCIE_REQ#
PIRQA# 15 PIRQC# 15
RN1806
RN1806 Do Not Stuff
Do Not Stuff
8 7 6
RN
RN
BOARD_ID1 20
R1801 Do Not StuffR1801 Do Not Stuff
1 2 1 2
1 2
1 2 1 2 1 2 1 2
1 2 3 45
4
HSW_ULT_DDR3L
CPU1F
CPU1F
C43
CLKOUT_PCIE_N0
C42
CLK_PCIE_REQ#
CLK_PCIE_REQ#
CLK_PCIE_WLAN_REQ3#
CLK_PCIE_LAN_REQ4#
PEG_CLKREQ#
CLK_PCIE_REQ#
LPC_LAD0_PCH LPC_LAD1_PCH LPC_LAD2_PCH LPC_LAD3_PCH LPC_LFRAME#_PCH
PCH_SPI_CLK
R180633R2J-2-GP R180633R2J-2-GP
PCH_SPI_CS0# TP_CL_CLK
R1807Do Not Stuff R1807Do Not Stuff
PCH_SPI_SI
R1808Do Not Stuff R1808Do Not Stuff
PCH_SPI_SO
R1809Do Not Stuff R1809Do Not Stuff
PCH_SPI_DQ2
R1811Do Not Stuff R1811Do Not Stuff
PCH_SPI_DQ3
R1812Do Not Stuff R1812Do Not Stuff
LPC_LAD0_PCH LPC_LAD2_PCH LPC_LAD1_PCH LPC_LAD3_PCH
CLKOUT_PCIE_P0
U2
PCIECLKRQ0#/GPIO18
B41
CLKOUT_PCIE_N1
A41
CLKOUT_PCIE_P1
Y5
PCIECLKRQ1#/GPIO19
C41
CLKOUT_PCIE_N2
B42
CLKOUT_PCIE_P2
AD1
PCIECLKRQ2#/GPIO20
B38
CLKOUT_PCIE_N3
C37
CLKOUT_PCIE_P3
N1
PCIECLKRQ3#/GPIO21
A39
CLKOUT_PCIE_N4
B39
CLKOUT_PCIE_P4
U5
PCIECLKRQ4#/GPIO22
B37
CLKOUT_PCIE_N5
A37
CLKOUT_PCIE_P5
T2
PCIECLKRQ5#/GPIO23
HASWELL-6-GP
HASWELL-6-GP
CPU1G
CPU1G
AU14
LAD0
AW12
LAD1
AY12
LAD2
AW11
LAD3
AV12
LFRAME#
AA3
SPI_CLK
Y7
SPI_CS0#
Y4
SPI_CS1#
AC2
SPI_CS2#
AA2
SPI_MOSI
AA4
SPI_MISO
Y6
SPI_IO2
AF1
SPI_IO3
HASWELL-6-GP
HASWELL-6-GP
HSW_ULT_DDR3L
WLAN
LAN
HSW_ULT_DDR3L
HSW_ULT_DDR3L
LPC
LPC
CLOCK
CLOCK
SIGNALS
SIGNALS
SMBUS
SMBUS
C-LINKSPI
C-LINKSPI
3
XTAL24_IN
XTAL24_OUT
RSVD#K21 RSVD#M21
DIFFCLK_BIASREF
TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8
CLKOUT_LPC_0 CLKOUT_LPC_1
CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
SMBALERT#/GPIO11
SMBCLK
SMBDATA
SML0ALERT#/GPIO60
SML0CLK
SML1ALERT#/PCHHOT#/GPIO73
SML0DATA
SML1CLK/GPIO75
SML1DATA/GPIO74
CL_CLK CL_DATA CL_RST#
6 OF 19
6 OF 19
7 OF 19
7 OF 19
A25 B25
K21 M21 C26
C35 C34 AK8 AL8
AN15 AP15
B35 A35
AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3
AF2 AD2 AF4
XTAL24_IN XTAL24_OUT
XCLK_BIASREF MCP_TESTLOW1
MCP_TESTLOW2 MCP_TESTLOW3 MCP_TESTLOW4
CLK_PCI_LPC_R CLK_PCI_KBC_R
MCP_GPIO11 SMB_CLK SMB_DATA
CARD_PW R_EN
SML0_CLK SML0_DATA MCP_GPIO73 SML1_CLK SML1_DATA
1
TP_CL_DATA
1
TP_CL_RST#
1
2
+V1.05S_AXCK_LCPLL
R1803 3KR2F-GPR1803 3KR2F-GP
1 2
RN1803 SRN10KJ-6-GPRN1803 SRN10KJ-6-GP
R1804 Do Not Stuff
R1804 Do Not Stuff
X02 0510
1205 modify GPIO pin
TP1803TP1803 TP1804TP1804 TP1805TP1805
SMB_DATA
SMB_CLK
6 7 8
1 2
LPC
LPC
R1805
R1805
1 2
Do Not Stuff
Do Not Stuff
MCP_GPIO11 20
SML0_CLK 53 SML0_DATA 53
MCP_GPIO73 16 SML1_CLK 24,26,76 SML1_DATA 24,26,76
45 3 2 1
DY
12
EC1801
Do Not StuffDYEC1801
Do Not Stuff
12
DY
3D3V_S0
Q1801
Q1801
6 5
2N7002KDW-GP
2N7002KDW-GP
XTAL24_IN
XTAL24_OUT
CLK_PCI_LPC 65 CLK_PCI_KBC 24
PCIE_CLK_XDP_N 96 PCIE_CLK_XDP_P 96
EC1802
Do Not StuffDYEC1802
Do Not Stuff
USB_OC#0_116,35
EC_SCI#20,24
1 2 34
X02 0510
12
R1802
R1802 1M1R2J-GP
1M1R2J-GP
DSW 20121019
SML0_DATA SML0_CLK SML1_CLK SML1_DATA
CARD_PW R_EN
USB_OC#0_1
EC_SCI#
SMB_CLK SMB_DATA
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F
4th = 84.2N702.F3F
4 1
SRN2K2J-4-GP
SRN2K2J-4-GP
1 2 3 4 5
1 2 3 4 5
RN1805
RN1805
4 5 3
6
2
7
1
8
SRN2K2J-4-GP
SRN2K2J-4-GP
PCH_SMBDATA 12,13,58,62,67
PCH_SMBCLK 12,13,58,62,67
1
C1801
C1801
1 2
SC15P50V2JN-2-GP
23
RN1809
RN1809 SRN10KJ-6-GP
SRN10KJ-6-GP
SC15P50V2JN-2-GP
X1801
X1801 XTAL-24MHZ-86-GP
XTAL-24MHZ-86-GP
82.30004.891
82.30004.891
2nd = 82.30004.841
2nd = 82.30004.841
C1802
C1802
1 2
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
RN1807
RN1807
8 7 6
8 7 6
3D3V_S5_PCH 3D3V_S0
3D3V_S5_PCH
A A
SRN1KJ-7-GP
SRN1KJ-7-GP
RN1802
RN1802
1
4
23
PCH_SPI_DQ2 PCH_SPI_DQ3
1203 remove DY
5
4
3
2
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU (CLK/SMB/LPC/SPI)
CPU (CLK/SMB/LPC/SPI)
CPU (CLK/SMB/LPC/SPI)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Hadley 17"
Hadley 17"
Hadley 17"
18 102Tuesday, June 25, 2013
18 102Tuesday, June 25, 2013
18 102Tuesday, June 25, 2013
1
A00
A00
A00
5
4
3
2
1
SSID = CPU
1 2
R1915 10MR2J-L-GPR1915 10MR2J-L-GP
X1901
X1901
41
2 3
X-32D768KHZ-65-GP
X-32D768KHZ-65-GP
82.30001.A41
82.30001.A41
HSW_ULT_DDR3L
HSW_ULT_DDR3L
RTC
RTC
AUDIO SATA
AUDIO SATA
R1903
R1903
HDA_SDIN027
RTC_AUX_S5
12
12
R1901
R1901 1M1R2J-GP
1M1R2J-GP
RTC_X1 RTC_X2
SRTC_RST# RTC_RST#
HDA_BITCLK HDA_SYNC HDA_RST# HDA_SDIN0
HDA_SDOUT TP_HDA_DOCK_EN#
1
TP1902
TP1902 Do Not Stuff
Do Not Stuff
TP1901 Do Not StuffTP1901 Do Not Stuff
PCH_JTAG_TRST#
1
PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS
XDP_TCK_JTAGX
SM_INTRUDER# PCH_INTVRMEN
C1903
C1903
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
CPU1E
CPU1E
AW5
RTCX1
AY5
RTCX2
AU6
INTRUDER#
AV7
INTVRMEN
AV6
SRTCRST#
AU7
RTCRST#
AW8
HDA_BCLK/I2S0_SCLK
AV11
HDA_SYNC/I2S0_SFRM
AU8
HDA_RST#/I2S_MCLK#
AY10
HDA_SDI0/I2S0_RXD
AU12
HDA_SDI1/I2S1_RXD
AU11
HDA_SDO/I2S0_TXD
AW10
HDA_DOCK_EN#/I2S1_TXD#
AV10
HDA_DOCK_RST#/I2S1_SFRM#
AY8
I2S1_SCLK
AU62
PCH_TRST#
AE62
PCH_TCK
AD61
PCH_TDI
AE61
PCH_TDO
AD62
PCH_TMS
AL11
RSVD#AL11
AC4
RSVD#AC4
AE63
JTAGX
AV2
RSVD#AV2
HASWELL-6-GP
HASWELL-6-GP
12
2nd = 82.30001.841
2nd = 82.30001.841
JTAG
JTAG
D D
RTC_AUX_S5
RN1901
RN1901
SRN20KJ-1-GP
SRN20KJ-1-GP
Q1901
Q1901
RTCRST_ON24
R1902
R1902
10KR2J-3-GP
10KR2J-3-GP
C C
HDA_CODEC_BITCLK27
G
12
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
3rd = 84.07002.I31
3rd = 84.07002.I31
D
C1901
C1901
R1907 33R2J-2-GPR1907 33R2J-2-GP
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
21
G1901
G1901
Do Not Stuff
Do Not Stuff
330KR2J-L1-GP
330KR2J-L1-GP
1
23
4
12
C1902
C1902 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
HDA_BITCLK
X02 0510
R1908 Do Not StuffR1908 Do Not Stuff
Flash Descriptor Security Overide/ Intel ME Debug Mode
HDA_SDOUT
The internal pull-down is disabled after PLTRST# deasserts
B B
R1913
R1913
1 2
DY
DY
Do Not Stuff
Do Not Stuff
Low = Default High = Enable
PCH_INTVRMEN
*
HDA_CODEC_SYNC27 HDA_CODEC_RST#27,29 HDA_CODEC_SDOUT27
ME_UNLOCK24
1D05S_VCCST
Integrated SUS 1V VRM Enable
INTVRMEN
Low = External VRs
gh = Internal VRs
Hi
*
1 2
R1912 Do Not StuffR1912 Do Not Stuff
1 2
R1911 Do Not StuffR1911 Do Not Stuff
1 2 1 2
R1909 1KR2J-1-GPR1909 1KR2J-1-GP
DY
DY
DY
DY DY
DY DY
DY
1 2
DY
DY
12 12 12 12
R1916 Do Not Stuff
R1916 Do Not Stuff R1917 Do Not Stuff
R1917 Do Not Stuff R1918 Do Not Stuff
R1918 Do Not Stuff R1919 Do Not Stuff
R1919 Do Not Stuff
R1920 Do Not Stuff
R1920 Do Not Stuff
HDA_SYNC HDA_RST# HDA_SDOUT
PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS XDP_TCK_JTAGX
PCH_JTAG_TCK
RTC_X1 RTC_X2
0502 X02 change C1903 C1904 from 18pF to 15 pF
12
C1904
C1904
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
5 OF 19
5 OF 19
RSVD#L11
RSVD#K10 SATALED#
J5 H5 B15 A15
J8 H8 A17 B17
J6 H6 B14 C15
F5 E5 C17 D17
V1 U1 V6 AC1
A12 L11 K10 C12 U3
EC_SMI#
MCP_GPIO36
SATA_IREF
SATA_RCOMP SATA_LED#
EC_SMI#
MCP_GPIO36
MSATA_DET#
SATA_ODD_PRSNT#
Layout Note:
4mil trace at break-out and 3 12-15mil trace with <0.2 ohms and length total <= 500mils.
SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3
SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2
SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0
SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37
SATA_IREF
SATA_RCOMP
SATA3_PRX_DTX_N0 56 SATA3_PRX_DTX_P0 56 SATA3_PTX_DRX_N0 56 SATA3_PTX_DRX_P0 56
SATA_PRX_ODDTX_N1 56 SATA_PRX_ODDTX_P1 56 SATA_PTX_ODDRX_N1 56 SATA_PTX_ODDRX_P1 56
SATA3_PRX_DTX_N2 60 SATA3_PRX_DTX_P2 60 SATA3_PTX_DRX_N2 60 SATA3_PTX_DRX_P2 60
0115:Modify
EC_SMI# 24
SATA_ODD_PRSNT# 56
MSATA_DET# 60
X01 0313
SATA_LED# 61
RN1902
RN1902
1
4
2 3
SRN10KJ-5-GP
SRN10KJ-5-GP
1 2 1 2
HDD1
ODD
mSATA
+V1.05S_ASATA3PLL
R1904
R1904
1 2
Do Not Stuff
Do Not Stuff
1 2
R1906
R1906 3KR2F-GP
3KR2F-GP
3D3V_S0
3D3V_S0
R190510KR2J-3-GP R190510KR2J-3-GP R191010KR2J-3-GP R191010KR2J-3-GP
A A
5
4
3
2
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU (RTC/SATA/HDA/JTAG)
CPU (RTC/SATA/HDA/JTAG)
CPU (RTC/SATA/HDA/JTAG)
e Document Number Rev
Size Document Number Rev
Size Document Number Rev
Siz
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Hadley 17"
Hadley 17"
Hadley 17"
19 102Tuesday, June 25, 2013
19 102Tuesday, June 25, 2013
19 102Tuesday, June 25, 2013
1
A00
A00
A00
5
SSID = CPU
4
HSW_ULT_DDR3L
CPU1J
CPU1J
HSW_ULT_DDR3L
3
10 OF 19
10 OF 19
2
1D05S_VCCST
12
R2018
R2018 1KR2J-1-GP
1KR2J-1-GP
1
FFS_INT2 MCP_GPIO8 MCP_GPIO12 MCP_GPIO15
MCP_GPIO16
1
RTC_DET# MCP_GPIO27 MCP_GPIO28 MCP_GPIO26
MCP_GPIO56 MCP_GPIO57
WLAN_PLT_RST# DRAM_SEL0 DRAM_SEL3
BOARD_ID1 BOARD_ID2
MCP_GPIO50
1
MCP_GPIO13 MCP_GPIO14
CAMERA_PWR_EN
1
DRAM_SEL1 DRAM_SEL2
EC_SWI# EC_SCI#
MCP_GPIO70
1
MCP_GPIO38
1
CLK_PCIE_LAN_REQ4# CLK_PCIE_REQ# SATA_ODD_DA# H_RCIN#
HDD_DEVSLP MSATA_DEVSLP
3D3V_S0
12
OPS
OPS
RN2005
RN2005 SRN10KJ-6-GP
SRN10KJ-6-GP
1 2 3 4 5
1210 Add
3D3V_S0
Do Not Stuff
Do Not Stuff
R2009
R2009 R2010
R2010
Do Not Stuff
Do Not Stuff
FFS_INT215,67
TP2004TP2004
TP2002TP2002
TP2020TP2020
TP2009TP2009 TP2003TP2003
8 7 6
1 2
DY
DY
1 2
DY
DY
X01 0311
D D
3D3V_S5
RN2006
RN2006 SRN10KJ-6-GP
SRN10KJ-6-GP
1
8
2
7
3
6
4 5
3D3V_S5_PCH
C C
12
R2013
R2013 10KR2J-3-GP
10KR2J-3-GP
MCP_GPIO_PH
3D3V_S5_PCH
B B
1 2 3 4 5
3D3V_S0
X02 0510
RN2012
RN2012 SRN10KJ-6-GP
SRN10KJ-6-GP
R2024
R2024
1 2
100KR2J-1-GP
100KR2J-1-GP
Add TP2004 and change net name to MCP_GPIO16.
SATA_ODD_DA#56 RTC_DET#25
BATLOW # MCP_GPIO27 MCP_GPIO12
DSW 20121019
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
8 7 6
1205 modify Net name
R2001Do Not Stuff R2001Do Not Stuff R2002Do Not Stuff R2002Do Not Stuff R2004Do Not Stuff R2004Do Not Stuff R2007Do Not Stuff R2007Do Not Stuff R2015Do Not Stuff R2015Do Not Stuff R2016Do Not Stuff R2016Do Not Stuff R2017Do Not Stuff R2017Do Not Stuff R2019Do Not Stuff R2019Do Not Stuff R2020Do Not Stuff R2020Do Not Stuff R2021Do Not Stuff R2021Do Not Stuff R2022Do Not Stuff R2022Do Not Stuff R2023Do Not Stuff R2023Do Not Stuff
RTC_DET#
WLAN_PLT_RST#
MCP_GPIO11 EC_SWI#
HSIOPC
MCP_GPIO58
DRAM_SEL0 DRAM_SEL2
MCP_GPIO26 MCP_GPIO56
DRAM_SEL1
MCP_GPIO14 MCP_GPIO28 MCP_GPIO8 MCP_GPIO13
DRAM_SEL3
MCP_GPIO57
BATLOW # 17
3D3V_S0
MCP_GPIO11 18
BOARD_ID118
HSIOPC21
EC_SWI#24 EC_SCI#18,24
HDD_DEVSLP56
MSATA_DEVSLP60
HDA_SPKR27
BIOS strap pin:
BIOS UMA/DIS Strap pin
BOARD_ID2BOARD_ID1
A A
UMA
Optimus(NV)
0 0
0
1
1
1
0
1
BOARD_ID2
UMA
UMA
12
P1
BMBUSY#/GPIO76
AU2
GPIO8
AM7
LAN_PHY_PWR_CTRL/GPIO12
AD6
GPIO15
Y1
GPIO16
T3
GPIO17
AD5
GPIO24
AN5
GPIO27
AD7
GPIO28
AN3
GPIO26
AG6
GPIO56
AP1
GPIO57
AL4
GPIO58
AT5
GPIO59
AK4
GPIO44
AB6
GPIO47
U4
GPIO48
Y3
GPIO49
P3
GPIO50
Y2
HSIOPC/GPIO71
AT3
GPIO13
AH4
GPIO14
AM4
GPIO25
AG5
GPIO45
AG3
GPIO46
AM3
GPIO9
AM2
GPIO10
P2
DEVSLP0/GPIO33
C4
SDIO_POWER_EN/GPIO70
L2
DEVSLP1/GPIO38
N5
DEVSLP2/GPIO39
V2
SPKR/GPIO81
HASWELL-6-GP
HASWELL-6-GP
CLK_PCIE_LAN_REQ4# 18,30 CLK_PCIE_REQ# 18
R2005
R2005 Do Not Stuff
Do Not Stuff
R2008
R2008 10KR2J-3-GP
10KR2J-3-GP
THRMTRIP#
RCIN#/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD#AF20 RSVD#AB21
GSPI0_CS#/GPIO83
GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86
GSPI1_CS#/GPIO87
GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92 UART0_RTS#/GPIO93 UART0_CTS#/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1 UART1_RST#/GPIO2 UART1_CTS#/GPIO3
I2C0_SDA/GPIO4 I2C0_SCL/GPIO5 I2C1_SDA/GPIO6 I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69
GPIO
GPIO
CPU/
CPU/ MISC
MISC
SERIAL IO
SERIAL IO
PCH strap pin:
NO REBOOT
Low = Disable (Default)
HDA_SPKR
The internal pull-down is disabled after PLTRST# deasserts
Top-Block Swap Override mode (For A1 Stepping)
Low = Disable "Top-Block swap" mode
*
SDIO_D0 / GPIO66
The internal pull-down is disabled after PLTRST# deasserts
(Default)
High = Enable "Top-Block swap"
mode
Need SW double confirm if that's needed Top-Block swap
TLS Confidentiality
Low = Disable Intel ME Crypto TLS
GPIO15
The internal pull-down is disabled after RSMRST# deasserts.
Boot BIOS Destination
The internal pull-down is disabled after PLTRST# deasserts
*
High = Enable Intel ME Crypto TLS
Boot BIOS Strap Bit BBS
Low = SPI
*
High = LPC
*
High = Enable
Need double confirm, GPIO table set to GPI if that's needed PH or PL
5
4
3
PCH_THERMTRIP
D60
H_RCIN#
V4
INT_SERIRQ
T4
PCH_OPIRCOMP
AW15 AF20 AB21
MCP_GPIO83
R6
MCP_GPIO84
L6 N6
LPSS_GSPI0_MOSI_BBS0_RMCP_GPIO58
L8
MCP_GPIO87
R7
MCP_GPIO88
L5
TOUCH_PWR_EN
N7 K2 J1 K3
MCP_GPIO93
J2
MCP_GPIO94
G1
MCP_GPIO0
K4
MCP_GPIO1
G2
MCP_GPIO2
J3 J4
I2C0_SDA
F2
I2C0_SCL
F3
I2C1_SDA
G4
I2C1_SCL
F1
COLOR_ENGINE
E3
MCP_GPIO65
F4
LPSS_SDIO_D0_CMNHDR
D3
MCP_GPIO67
E4
MCP_GPIO68
C3
MCP_GPIO69
E2
3D3V_S0
12
R2011
R2011
DY
DY
Do Not Stuff
Do Not Stuff
LPSS_SDIO_D0_CMNHDR
3D3V_S5_PCH
12
R2014
R2014
DY
DY
Do Not Stuff
Do Not Stuff
3D3V_S0
12
R2012
R2012
DY
DY
Do Not Stuff
Do Not Stuff
LPSS_GSPI0_MOSI_BBS0_R
3D3V_S0
MCP_GPIO15
1 2
R2003
R2003 49D9R2F-GP
49D9R2F-GP
1
TP2010TP2010
1
TP2011TP2011
SATA_ODD_PWRGT 56
1
TP2012TP2012
1
TP2013TP2013
1
TP2014TP2014
KB_DET# 62 KB_LED_BL_DET 62 DBC_EN 52
1
TP2015TP2015
1
TP2016TP2016
1
TP2017TP2017
1
TP2018TP2018
1
TP2019TP2019
COLOR_ENGINE 52
1
TP2005TP2005
1
TP2006TP2006
1
TP2007TP2007
1
TP2008TP2008
Do Not Stuff
Do Not Stuff R2006
R2006
1 2
HDA_SPKR
DY
DY
1219 Modify.EDS Update. SW Suggest To Not Pop R2011 First.
2
H_RCIN# 24
INT_SERIRQ 24
Layout Note:
1.Referenced "continuous" VSS plane only.
2.Avoid routing next to clock pins or noisy signals.
3. Trace width: 12~15mil
4.
Isolation Spacing: 12mil
5. Max length: 500mil
1109 Add KB backlit GPIO pin
RN2014
RN2014 SRN10KJ-6-GP
SRN10KJ-5-GP
SRN10KJ-5-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
1
SRN10KJ-6-GP
1 2 3 4 5
RN2007
RN2007
4
R2027
R2027
1 2
R2028
R2028
1 2
20 102Tuesday, June 25, 2013
20 102Tuesday, June 25, 2013
20 102Tuesday, June 25, 2013
I2C1_SDA
DBC_EN
BLUETOOTH_EN 58
UMA
UMA
UMA
Title
Title
Title
e Document Number Rev
Size Document Number Rev
Size Document Number Rev
Siz
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
INT_SERIRQ BLUETOOTH_EN
I2C0_SCL I2C0_SDA
I2C1_SCL
KB_DET#
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
CPU (GPIO)
CPU (GPIO)
CPU (GPIO)
Hadley 17"
Hadley 17"
Hadley 17"
3D3V_S0
8 7 6
3D3V_S0
1 23
A00
A00
A00
5
4
3
2
1
SSID = CPU
DSW 20121019
3D3V_S5_PCH
D D
+V1.05DX_MODPHY_PCH
1D05V_S0
R2105
R2105
1 2
Do Not Stuff
Do Not Stuff
C2105
Do Not StuffDYC2105
Do Not Stuff
+V3.3A_1.5A_HDA3D3V_S5_PCH
R2108
R2108
1 2
Do Not Stuff
Do Not Stuff
1 2
X01 0313
12
DY
12
R2112
R2112
Do Not Stuff
Do Not Stuff
TP2102TP2102
TP2107TP2107
C2116
SC1U6D3V2KX-GP
C2116
SC1U6D3V2KX-GP
TP2108TP2108
TP2103TP2103 TP2104TP2104 TP2101TP2101
X01 0313
DSW 20121019
X02 0510
C C
3D3V_S5 3D3V_S0
X01 0313
1D05V_S0
X01 0313
R2101
R2101
1 2
Do Not Stuff
Do Not Stuff
R2117
R2117
1 2
Do Not Stuff
Do Not Stuff
DY
DY
12
C2136
C2136 Do Not Stuff
Do Not Stuff
C2137
C2137
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
+V3.3A_DSW_P
+V1.05S_SSCF100
+V1.05DX_MODPHY_PCH
+V1.05S_AIDLE
+V1.05S_AUSB3PLL
+V1.05S_ASATA3PLL
TP_VCCAPLLOPI_VAL
1
+V1.05S_APLLOPI
+V1.05A_VCCUSB3SUS
1
+V3.3A_1.5A_HDA
+V1.05A_USB2SUS
1
+V3.3A_PSUS +V3.3A_DSW_P
12
C2123
C2123 SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
+V1.05S_AXCK_DCB
+V1.05S_AXCK_LCPLL
+V1.05S_SSCF100
+V1.05S_SSCFF
TP_V1.05S_SSCF100
1
TP_V1.05S_AXCK_DCB
1
TP_V1.05S_SSCFF
1
+V3.3A_PSUS
+V3.3S_PCORE
AA21
W21
AH14
AH13
AH10
AE20 AE21
B18 B11
Y20
AC9 AA9
K19 A20
R21 K18
M20 V21
K9 L10 M9
N8
P9
J13
V8 W9
J18
J17 T21
CPU1M
CPU1M
VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL
RSVD#Y20 VCCAPLL VCCAPLL
DCPSUS3
VCCHDA
DCPSUS2
VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3
VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD#K18 RSVD#M20 RSVD#V21 VCCSUS3_3 VCCSUS3_3
HSIO
HSIO
USB3
USB3
HDA
HDA
VRM
VRM
GPIO/LPC
GPIO/LPC
LPT LP POWER
LPT LP POWER
HSW_ULT_DDR3L
HSW_ULT_DDR3L
OPI
OPI
RTC
RTC
SPI
SPI
CORE
CORE
THERMAL SENSOR
THERMAL SENSOR
SERIAL IO
SERIAL IO
SUS OSCILLATOR
SUS OSCILLATOR
USB2
USB2
13 OF 19
13 OF 19
VCCSUS3_3
VCCRTC DCPRTC
VCCSPI
VCCASW VCCASW
VCC1_05 VCC1_05 VCC1_05 VCC1_05
VCC1_05 DCPSUSBYP#AG19 DCPSUSBYP#AG20
VCCASW VCCASW VCCASW
DCPSUS1#AD10
DCPSUS1#AD8
VCCTS1_5
VCC3_3 VCC3_3
VCCSDIO VCCSDIO
DCPSUS4
RSVD#AC20
VCC1_05
VCC1_05
+3.3A_DSW_PRTCSUS
AH11 AG10
+VCCRTCEXT
AE7
Y8
AG14 AG13
J11 H11 H15 AE8 AF22 AG19 AG20 AE9 AF9 AG8 AD10 AD8
J15 K14 K16
U8 T9
AB8
AC20 AG16 AG17
1D05V_S0
+V1.05S_CORE_PCH
+PCH_VCCDSW PCH_VCCDSW_R
+1.05M_ASW
+V1.05A_SUS_PCH
+V1.05A_AOSCSUS
TP_V1.05S_APLLOPI
1
1D5V_S0
+V3.3S_1.8S_LPSS_SDIO
1 2
12
C2109
C2109 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
RTC_AUX_S5
C2110
C2110
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
R2110
R2110 5D1R2F-GP
5D1R2F-GP
1 2
TP2106TP2106
1
1
12
X02 0510
R2102
R2102 Do Not Stuff
Do Not Stuff
3D3V_S0
12
TP2109TP2109
TP2105TP2105
C2135
SC1U6D3V2KX-GP
C2135
SC1U6D3V2KX-GP
3D3V_S5
12
C2147
C2147 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2114
C2114 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C2128
SC1U6D3V2KX-GP
C2128
SC1U6D3V2KX-GP
1 2
1D05V_S0
0508 X02 VCCDSW3_3 Inrush Current
stem Design Guide Clarification
Sy
+V3.3A_DSW_P +PCH_VCCDSW
+V3.3S_1.8S_LPSS_SDIO
1 2
C2103
C2103 SCD47U6D3V2KX-GP
SCD47U6D3V2KX-GP
X01 0313
12
C2104
C2104
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
R2103
R2103
1 2
Do Not Stuff
Do Not Stuff
3D3V_S0
HASWELL-6-GP
5V_S5
HASWELL-6-GP
1D05V_S0 1D05V_HSIO
R2123
R2123
1 2
Do Not Stuff
Do Not Stuff
DY
DY
HSIOPC_R
DY
DY
12
C2102
C2102
Do Not Stuff
Do Not Stuff
X01 0318 Change U2101 from 74.22965.093 to 74.59147.093 for sequence concern. And remove C2140.
1 2
U2101
U2101
1
VDD
2
D#2
3
D#3 D#44S#5
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
3
R2122
R2122 0R5J-5-GP
0R5J-5-GP
9
ON
GND
DY
DY
8
HSIO_OUT
7
S#7
6
S#6
5
R2114
R2114 Do Not Stuff
Do Not Stuff
1 2
DY
DY
1D05V_HSIO
12
DY
C2101
Do Not StuffDYC2101
Do Not Stuff
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
CPU (POWER2)
CPU (POWER2)
CPU (POWER2)
Hadley 17"
Hadley 17"
Hadley 17"
21 102Tuesday, June 25, 2013
21 102Tuesday, June 25, 2013
21 102Tuesday, June 25, 2013
1
A00
A00
A00
1D05V_S0
X01 0313
B B
A A
R2118
R2118
1 2
Do Not Stuff
Do Not Stuff
5
+V1.05S_SSCFF
C2138
SC1U6D3V2KX-GP
C2138
SC1U6D3V2KX-GP
12
HSIOPC20
1D05V_S0
4
5
4
3
2
1
SSID = CPU
D D
HSW_ULT_DDR3L
CPU1Q
CPU1Q
TP2201
TP2201
Do Not Stuff
Do Not Stuff
TP2204
TP2204
Do Not Stuff
Do Not Stuff
C C
DC_TEST_AY2_AW2 TP_DC_TEST_AY60
1
DC_TEST_AY61_AW 61 DC_TEST_AY62_AW 62
1
DC_TEST_A3_B3 DC_TEST_A61_B61 DC_TEST_B62_B63
AY2
DAISY_CHAIN_NCTF_AY2
AY3
DAISY_CHAIN_NCTF_AY3
AY60
DAISY_CHAIN_NCTF_AY60
AY61
DAISY_CHAIN_NCTF_AY61
AY62
DAISY_CHAIN_NCTF_AY62
B2
DAISY_CHAIN_NCTF_B2
B3
DAISY_CHAIN_NCTF_B3
B61
DAISY_CHAIN_NCTF_B61
B62
DAISY_CHAIN_NCTF_B62
B63
DAISY_CHAIN_NCTF_B63
C1
DAISY_CHAIN_NCTF_C1
C2
DAISY_CHAIN_NCTF_C2
HASWELL-6-GP
HASWELL-6-GP
CPU1R
CPU1R
AT2
RSVD#AT2
AU44
RSVD#AU44
AV44
RSVD#AV44
D15
RSVD#D15
F22
RSVD#F22
H22
RSVD#H22
J21
RSVD#J21
HSW_ULT_DDR3L
HSW_ULT_DDR3L
HSW_ULT_DDR3L
DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63
17 OF 19
17 OF 19
18 OF 19
18 OF 19
RSVD#N23 RSVD#R23 RSVD#T23 RSVD#U10
RSVD#AL1
RSVD#AM11
RSVD#AP7 RSVD#AU10 RSVD#AU15
RSVD#AW14
RSVD#AY14
DC_TEST_A3_B3
A3
TP_DC_TEST_A4DC_TEST_AY3_AW3
A4
TP_DC_TEST_A60
A60
DC_TEST_A61_B61
A61
TP_DC_TEST_A62TP_DC_TEST_B2
A62
TP_DC_TEST_AV1
AV1
TP_DC_TEST_AW 1
AW1
DC_TEST_AY2_AW2
AW2
DC_TEST_AY3_AW3
AW3
DC_TEST_AY61_AW 61DC_TEST_C1_C2
AW61
DC_TEST_AY62_AW 62
AW62
TP_DC_TEST_AW 63
AW63
N23 R23 T23 U10
AL1 AM11 AP7 AU10 AU15 AW14 AY14
TP2202TP2202
1 1
TP2203TP2203
1
TP2205TP2205
1
TP2206TP2206
1
TP2207TP2207
1
TP2208TP2208
HASWELL-6-GP
HASWELL-6-GP
B B
A A
5
4
3
2
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
RSVD
RSVD
RSVD
Hadley 17"
Hadley 17"
Hadley 17"
22 102Tuesday, June 25, 2013
22 102Tuesday, June 25, 2013
22 102Tuesday, June 25, 2013
1
A00
A00
A00
5
4
3
2
1
SSID = CPU
HSW_ULT_DDR3L
HSW_ULT_DDR3L
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
HSW_ULT_DDR3L
CPU1N
CPU1N
D D
C C
B B
A11 A14 A18 A24 A28 A32 A36 A40 A44 A48 A52 A56
AA1 AA58 AB10 AB20 AB22
AB7 AC61 AD21
AD3 AD63 AE10
AE5 AE58
AF11 AF12 AF14 AF15 AF17 AF18
AG1 AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57
AJ13 AJ14 AJ23 AJ25 AJ27 AJ29
HASWELL-6-GP
HASWELL-6-GP
14 OF 19
14 OF 19
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20
AP22 AP23 AP26 AP29
AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57
AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49
AR5
AR52
AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63
AU1
AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59
AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55
HSW_ULT_DDR3L
CPU1O
CPU1O
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
HASWELL-6-GP
HASWELL-6-GP
15 OF 19
15 OF 19
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31
A A
5
4
3
2
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (VSS)
CPU (VSS)
CPU (VSS)
Hadley 17"
Hadley 17"
Hadley 17"
23 102Tuesday, June 25, 2013
23 102Tuesday, June 25, 2013
23 102Tuesday, June 25, 2013
1
A00
A00
A00
5
SSID = KBC
D D
C C
1D05V_S0
Layout Note:
Need very close to EC
3D3V_S0
C2412
C2412
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
LCD_TST_EN52
LCD_TST52
1109 Add KB backlit
Don't PD
ALL_SYS_PWRGD de-assert, delay 10ms;
B B
PCH_PWROK assert.
ALL_SYS_PWRGD de-assert, delay 100ms; SYS_PWROK assert.
LVDS backlight Control from PS8625
1210 change AOAC_WLAN_EN
LVDS_R2136_BKLT _EN53
Backlight Control from LVDS Converter
R2401
R2401
1 2
Do Not Stuff
Do Not Stuff
C2413
Do Not StuffDYC2413
Do Not Stuff
12
12
DY
EC_AGND
1127 Add
1127 Charger
Charger
PCH/thermal
1114 Add
R2417
R2417
1 2
Do Not Stuff
Do Not Stuff
X02 0510
0109 Change
1123 change net name
1206 modify
1203 change
1127 Add
1127 Charger
R2446 Do Not StuffR2446 Do Not Stuff
1 2
X02 0510
TP
EC_VTT
12
EC_FB_CLAMP_T GL_REQ#76
VBAT
C2401
C2401
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
AD_IA44
C2414 Do Not Stuff
C2414 Do Not Stuff
1 2
DY
DY
PSID_EC42
PM_SLP_SUS#17,38 BOOST_MON44
USBCHARG ER_CB035
FAN1_DAC_126
AD_IA_HW44
IMVP_PWRGD7,46
BAT_SCL43,44,53 BAT_SDA43,44,53
SML1_CLK18,26,76
SML1_DATA18,26,76
PM_LAN_ENABLE30
RTCRST_O N19
USBCHG_EN35
TPCLK62
TPDATA62
ALL_SYS_PWRG D36
PWR_CH G_AD_OFF42
AD_IA_HW244
BLON_OUT52
FAN_TACH 12 6
PM_PWRBT N#17,9 6
EC_FB_CLAMP75,76,83
PM_SLP_S3#17,36,48,49,51,52
PWRLED #61
KBC_BEEP27
EC_BRIGHTN ESS52
AC_IN_KBC#42
KB_BL_CTRL62
LAN_WAKE#30
KBC_DPW ROK17
CHG_AMBER_L ED#61
PCH_PW ROK17,26,36
USB_PWR _EN#35
AC_PRESENT17,76
SYS_PWROK17,96
AOAC_WLA N_EN58
WIFI_RF_EN58
PM_SUSWA RN#17
DGPU_PW ROK15,82,8 3
DIS_DTM44
E51_TxD58
PM_CLKRUN #_EC17
AMP_MUTE#27
VBAT
3D3V_AUX_KBC _VCC
C2405
Do Not StuffDYC2405
Do Not Stuff
12
12
C2404
C2404
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
EC_AGND
EC_VTT
PCB_VER_AD AMB_TEMP
MODEL_ID_DET
PROCHOT _EC LCD_TST_EN
ECSWI#_KBC
L_BKLT_EN_EC
12
C2406
C2406
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
KBC24
KBC24
19
VCC
46
VCC
76
VCC
88
VCC
115
VCC
102
AVCC
4
VDD
12
VTT
97
GPIO90/AD0
98
GPIO91/AD1
99
GPIO92/AD2
100
GPIO93/AD3
108
GPIO5/AD4
96
GPIO4/AD5
95
GPIO3/EXT_PURST#/AD6
94
GPIO7/AD7/VD_IN2
101
GPIO94/DA0
105
GPIO95/DA1
106
GPIO96/DA2
107
GPIO97/DA3
70
GPIO17/SCL1/N2TCK
69
GPIO22/SDA1/N2TMS
67
GPIO73/SCL2/N2TCK
68
GPIO74/SDA2/N2TMS
119
GPIO23/SCL3/N2TCK
120
GPIO31/SDA3/N2TMS
24
GPIO47/SCL4/N2TCK
28
GPIO53/SDA4/N2TMS
26
GPIO51/TA3/N2TCK
123
GPIO67/N2TMS
72
GPIO37/PSCLK1
71
GPIO35/PSDAT1
10
GPIO26/PSCLK2
11
GPIO27/PSDAT2
25
GPIO50/PSCLK3/TDO
27
GPIO52/PSDAT3/RDY#
31
GPIO56/TA1
117
GPIO20/TA2/IOX_DIN_DIO
63
GPIO14/TB1
64
GPIO1/TB2
32
GPIO15/A_PWM
118
GPIO21/B_PWM
62
GPIO13/C_PWM
65
GPIO32/D_PWM
22
GPIO45/E_PWM
16
GPIO40/F_PWM/1_WIRE
81
GPIO66/G_PWM
66
GPO33/H_PWM/VD1_EN#
104
GPIO80/VD_IN1
110
GPIO82/IOX_LDSH/VD_OUT1
112
GPIO84/IOX_SCLK/VD_OUT2
84
GPIO77/SPI_MISO
83
GPIO76/SPI_MOSI
82
GPIO75/SPI_SCK
79
GPIO2/SPI_CS#
124
GPIO10/LPCPD#
121
GPIO85/GA20
111
GPIO83/SOUT_CR
9
GPIO65/SMI#
8
GPIO11/CLKRUN#
30
GPIO55/CLKOUT/IOX_DIN_DIO
NPCE985PA0DX -1-GP
NPCE985PA0DX -1-GP
71.00985.C0G
71.00985.C0G
AOAC Ambient temperature detect
VBAT
12
R2437
R2437 10KR2F-2-GP
R2441
R2441
EC_AGND
C2419
C2419
1 2
10KR2F-2-GP
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2420
C2420
AMB_TEMP
12
SC100P50V2JN-3GP
SC100P50V2JN-3GP
5
A A
NTC-10K-26- GP
NTC-10K-26- GP
EC_GPIO47 High Active
PROCHOT _EC
12
R2442
R2442
Do Not Stuff
Do Not Stuff
DY
DY
R2438
R2438 Do Not Stuff
Do Not Stuff
1 2
DY
DY
Q2401
Q2401
G
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
3rd = 84.07002.I31
3rd = 84.07002.I31
4th = 84.2N702.W31
4th = 84.2N702.W31
4
X01 0313
R2402
R2402
Do Not Stuff
Do Not Stuff
12
12
C2408
C2408
C2407
C2407
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
KBSIN0/GPIOA0/N2TCK KBSIN1/GPIOA1/N2TMS
KBSOUT0/GPOB0/SOUT_CR/JENK#
KBSOUT1/GPIOB1/TCK KBSOUT2/GPIOB2/TMS
KBSOUT3/GPIOB3/TDI
KBSOUT4/GPOB4/JEN0#
KBSOUT5/GPIOB5/TDO
KBSOUT6/GPIOB6/RDY#
KBSOUT9/GPOC1/SDP_VIS# KBSOUT10/P80_CLK/GPIOC2 KBSOUT11/P80_DAT/GPIOC3
KBSOUT12/GPO64/TEST#
KBSOUT13/GPI/O63/TRIST#
KBSOUT14/GPI/O62/XORTR#
KBSOUT15/GPIO61/XOR_OUT
GPIO81/F_WP#/F_SDIO2 GPIO0/EXTCLK/F_SDIO3
PSL_IN2#/GPI6/EXT_PURST#
GPIO46/CIRRXM/TRST#
GPIO87/CIRRXM/SIN_CR
H_PROCHO T#_EC
D
4
12
2D2R3-1-U- GP
2D2R3-1-U- GP
12
C2409
C2409
C2410
C2410
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
KBSIN2/GPIOA2 KBSIN3/GPIOA3 KBSIN4/GPIOA4 KBSIN5/GPIOA5 KBSIN6/GPIOA6 KBSIN7/GPIOA7
KBSOUT7/GPIOB7 KBSOUT8/GPIOC0
GPIO60/KBSOUT16 GPIO57/KBSOUT17
LAD0/GPIOF1 LAD1/GPIOF2 LAD2/GPIOF3 LAD3/GPIOF4
LCLK/GPIOF5 LFRAME#/GPIOF6 LRESET#/GPIOF7
F_CS0#
F_SCK GPIO30/F_WP# GPIO41/F_WP#
F_SDIO/F_SDIO0
F_SDI/F_SDIO1
PSL_IN1#/GPI70
PSL_OUT#/GPIO71
ECSCI#/GPIO54
EXT_RST#
KBRST#/GPIO86
VSBY VBKUP VCORF
SERIRQ/GPIOF0
GPIO24
GPIO36/TB3
GPIO44/TDI GPIO43/TMS GPIO42/TCK
GPIO34/CIRRXL
AGND
X02 0510
R2440
R2440
1 2
Do Not Stuff
Do Not Stuff
3D3V_AUX_KBC
R2403
R2403
12
PECI
GND GND GND GND GND GND
54 55 56 57 58 59 60 61
53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33
126 127 128 1 2 3 7
90 92 109 80 87 86 91 77
73 93 74
29 85 122
75 114 44 13 125 6 15
21 20 17 23
113 14
5 18 45 78 89 116
103
1 2
12
C2411
C2411
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7
KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 USB_DET#
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
PLT_RST#_EC
EC_SPI_CS#_C EC_SPI_CLK_C
EC_SPI_DI_C EC_SPI_DO_C
PSL_IN1# PSL_IN2# PSL_OUT#
ECSCI#_KBC ECRST#
EC_VBKUP KBC_VCORF PECI
ECSMI#_KBC
EC_AGND
12
C2421
C2421 SC47P50V2JN-3G P
SC47P50V2JN-3G P
A00 0618 Change
Do Not Stuff
Do Not Stuff
ME_UNLOCK 19
WIFI_WAKE# 58
S5_ENABLE 36
12
EC_AGND
H_PROCHO T# 4,42,44, 46
VBAT VBAT
12
R2404
R2404 64K9R2F-1-GP
64K9R2F-1-GP
PCB_VER_AD
R2435
R2435 Do Not Stuff
Do Not Stuff
12
R2406
R2406 100KR2F-L1-GP
C2402
C2402
100KR2F-L1-GP
DY
DY
1 2
EC_AGND
KROW[0..7] 62
KCOL[0..16] 62
LPC_AD[3..0] 18,65
CLK_PCI_KBC 18 LPC_FRAME# 18,65
R2419 Do N ot StuffR2419 Do Not Stuff
1 2
R2412 33R 2J-2-GPR2412 33R2J- 2-GP
12
R2420 Do N ot StuffR2420 Do Not Stuff
1 2
R2422 Do N ot StuffR2422 Do Not Stuff
1 2
Layout Note:
Need very close to EC 1203 R2419,20,22 change to 0R
H_RCIN# 20
R2428
R2428
1 2
Do Not Stuff
Do Not Stuff
INT_SERIRQ 20
OVER_CUR RENT_P8# 76
PM_SLP_S4# 17,49 RSMRST#_KBC 17
LID_CLOSE# 64
D2402
D2402
21
CH751H-40PT -GP
CH751H-40PT -GP
83.R0304.A8F
83.R0304.A8F
X01 0313 Change R2447 to D2402 for leakage issue.
X01 0313
Layout Note:
Connect GND and AGND planes via either 0R resistor or connect directly.
PURE_HW _SHUTDO WN#26,36,76
3
PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
X01 X02 X03 A00
Reserved
Reserved
Reserved 100.0K 215.0K 1.048V
SPI_CS0#_R 18,25 SPI_CLK_R 18,25 CAP_LED# 62 BAT_IN# 42,43,44 SPI_SI_R 18,25 SPI_SO_R 1 8,25
PM_SUSACK# 17
PCH_SUSCL K_KBC 17
100.0KX00
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K 1.358V
X02 0510
R2416
R2416
1 2
Do Not Stuff
Do Not Stuff
12
Do Not Stuff
Do Not Stuff C2415
C2415
DY
DY
1127 Add
10.0K
20.0K
33.0K
47.0K
64.9K
76.8
100.0K
143.0K
174.0KReserved 100.0K
PLT_RST# 17,30,58,65,73
Power Switch Logic(PSL)
3D3V_AUX_S5 RTC_AUX_S5
DY
TOUCH_PAN EL_INTR# 52
12
3
1 2
C2422
Do Not StuffDYC2422
Do Not Stuff
C2416 SC1U 6D3V2KX-GPC2416 SC1U6D3V2K X-GP
1 2
R2429
R2429 43R2J-GP
43R2J-GP
Layout Note:
0114 modify0115 modify
3D3V_AUX_S5
R2439
R2439 10KR2J-3-GP
10KR2J-3-GP
12
2nd = 84.03906.F11
2nd = 84.03906.F11
H_PECI 4
Need very close to EC C2422 PDG is 47p
0103: Reserve R2434
1 2
DY
DY
R2434
R2434
Do Not Stuff
Do Not Stuff
B
Q2404
Q2404
MMBT3906-4-GP
MMBT3906-4-GP
84.T3906.A11
84.T3906.A11
KBC_PWR BTN#61
AC_IN#44
USBDET_CO N#34
ECRST#
C2418
C2418
12
E
DY
DY
C
Do Not Stuff
Do Not Stuff
3.0V
2.75V
2.48V
2.24V
2.0V
1.87V
1.65VReserved
1.204V
R2427
R2427
1 2
Do Not Stuff
Do Not Stuff
X01 0313
R2430
R2430
1 2
Do Not Stuff
Do Not Stuff
D2401
D2401
3
BAT54CPT-2- GP
BAT54CPT-2- GP
75.00054.K7D
75.00054.K7D
PSL_OUT#
2
Do Not Stuff
Do Not Stuff
3D3V_AUX_S5
1
2
R2432
R2432
1 2
1KR2J-1-GP
1KR2J-1-GP
2
MODEL_ID
MODEL_ID
MODEL_ID_DET
C2403
C2403
DY
DY
R2425
R2425 330KR2J-L1-GP
330KR2J-L1-GP
1 2
PSL_IN2#
PSL_IN1#
USB_DET#
KBC_ON#_GAT E_L
MODEL_ID_DET(GPIO07)
UMA
12
R2405
R2405 10KR2F-2-GP
10KR2F-2-GP
12
R2407
R2407 100KR2F-L1-GP
100KR2F-L1-GP
1 2
EC_AGND
3D3V_AUX_S5 3D3V_AUX_S5
TBD TBD DIS_N14P_GT 2.702V TBD DIS_N14E_GL TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
ECSCI#_KBC ECSMI#_KBC ECSWI#_KBC
OVER_CUR RENT_P8#
FAN_TACH 1
C2417
C2417 SCD1U10V2KX- 5GP
R2431
R2431 330KR2J-L1-GP
330KR2J-L1-GP
1 2
1 2
R2433
R2433 20KR2J-L2-GP
20KR2J-L2-GP
SCD1U10V2KX- 5GP
1 2
KBC_ON#_GAT EKBC_ON#_GAT E_L
Q2402
Q2402 DMP2130L-7-GP
DMP2130L-7-GP
84.02130.031
84.02130.031
2ND = 84.03413.A31
2ND = 84.03413.A31
UMA
UMA
UMA
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev A2
A2
A2
Tuesday, June 25, 2013
Tuesday, June 25, 2013
Tuesday, June 25, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
100.0K 3.0V
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
AC_IN_KBC#
USB_DET#
BAT_SCL BAT_SDA
ECRST#
AC_IN# BAT_IN#
LID_CLOSE#
G
G
G
D
D
D
Q2403
Q2403
G
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
3rd = 84.07002.I31
3rd = 84.07002.I31
4th = 84.2N702.W31
4th = 84.2N702.W31
10.0K(64.10025.6DL)
13.7K(64.13725.6DL)
17.8K(64.17825.6DL)
22.1K(64.22125.6DL)
27.0K(64.27025.6DL)
32.4K(64.32425.6DL)
37.4K(64.37425.6DL)
43.2K(64.43225.6DL)
57.6K(64.57625.6DL)
64.9K(64.64925.6DL)
73.2K(64.73225.6DL) 1.905V
82.5K(64.82525.6DL) 1.808V
93.1K(64.93125.6DL) 107K(64.10735.6DL) 120K(64.12035.6DL) 137K(64.13735.6DL) 154K(64.15435.6DL) 200K(64.20035.6DL) 1.099V 232K(64.23236.6DL)
R2408Do Not Stuff R2408Do Not Stuff
12
R2409Do Not Stuff R2409Do Not Stuff
12
R2410Do Not Stuff R2410Do Not Stuff
12
3D3V_AUX_KBC
R2426 100KR2J-1-GPR2426 100KR2J-1-GP
1 2
R2411 100KR2J-1-GPR2411 100KR2J-1-GP
1 2
RN2401
RN2401
23 1
4
SRN4K7J-8-G P
SRN4K7J-8-G P
R2418 10KR2J -3-GPR2418 10KR2J-3-GP
1 2
R2413 Do N ot Stuff
R2413 Do N ot Stuff R2414 100KR2J -1-GPR2414 100KR2J- 1-GP R2424 Do N ot Stuff
R2424 Do N ot Stuff
R2415 10KR2J -3-GPR2415 10KR2J-3-GP
R2421 Do Not Stuff
R2421 Do Not Stuff
S
D
KBC Nuvoton NPCE985
KBC Nuvoton NPCE985
KBC Nuvoton NPCE985
Hadley 17"
Hadley 17"
Hadley 17"
1
3D3V_AUX_KBC
1 2
DY
DY
1 2 1 2
DY
DY
1 2
1 2
DY
DY
3D3V_AUX_KBC
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
2.902V
2.801V
2.598V
2.492V
2.402V
2.304V
2.201V49.9K(64.49925.6DL)
2.093V
2.001V
1.709V
1.594V
1.499V
1.392V
1.299V
0.994V
EC_SCI# 18,20 EC_SMI# 19 EC_SWI# 20
3D3V_AUX_KBC
3D3V_S0
3D3V_S5
3D3V_AUX_KBC
12
R2436
R2436 10KR2J-3-GP
10KR2J-3-GP
S5_ENABLE
24 102
24 102
24 102
A00
A00
A00
5
SSID = Flash.ROM
4
3
2
1
R2501
R2501
4K7R2J-2-GP
4K7R2J-2-GP
12
DY
DY
3D3V_S5
1 2
1203 RN2501 DY
4
RN2501
RN2501 Do Not Stuff
Do Not Stuff
DY
DY
1
2 3
SPI25
SPI25
1
CS#
2
DO/IO1
3
WP#/IO2
4
GND
W25Q64FVSSIQ-GP
W25Q64FVSSIQ-GP
72.25Q64.K01
72.25Q64.K01
VCC
HOLD#/IO3
CLK
DI/IO0
8 7 6 5
Do Not Stuff
Do Not Stuff
3D3V_S5
EC2501
EC2501
DY
DY
DY
12
12
DY
DY
QUAD/DUAL fast read DUAL fast readSource
SPI Flash ROM(8M) for PCH
D D
SPI_CS0#_R18,24
SPI_SO_R18,24
SPI_WP#18
EC2502
Do Not Stuff
Do Not Stuff
C C
EC2502
72.25Q64.K01
X01 0311 Remove SKT25.
72.25647.00A O O
3D3V_S5
C2501
Do Not StuffDYC2501
Do Not Stuff
12
SPI_HOLD# 18 SPI_CLK_R 18,24 SPI_SI_R 18,24
EC2503
EC2503 Do Not Stuff
Do Not Stuff
O O
12
C2502
C2502 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Single SPI shared flash connection (SPI Quad I/O mode)
Refer to "NCPE985x/ NPCE995x board design reference guide"
SSID = RBATT
RTC_AUX_S5+RTC_VCC 3D3V_AUX_S5
+RTC_VCC
B B
RTC1
RTC1
PWR
GND
NP1 NP2
BAT-AAA-BAT-054-P06-GP-U
BAT-AAA-BAT-054-P06-GP-U
A A
5
AFTP2502
AFTP2502 Do Not Stuff
Do Not Stuff
1 2 NP1 NP2
1
R2502
R2502
1KR2J-1-GP
4
1
Do Not Stuff
Do Not Stuff
AFTP2501
AFTP2501
1KR2J-1-GP
12
12
R2504
R2504 10MR2J-L-GP
10MR2J-L-GP
RTC_PW R
Q2505
Q2505
G
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
3rd = 84.07002.I31
3rd = 84.07002.I31
4th = 84.2N702.W31
4th = 84.2N702.W31
D2501
D2501
2
3
1
BAS40CW -GP
BAS40CW -GP
83.00040.E81
83.00040.E81
D
C2503
C2503
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
3
RTC_DET# 20
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
e Document Number Rev
Size Document Number Rev
Size Document Number Rev
Siz A3
A3
A3
Tuesday, June 25, 2013
Tuesday, June 25, 2013
Tuesday, June 25, 2013
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Flash/RTC
Flash/RTC
Flash/RTC
Hadley 17"
Hadley 17"
Hadley 17"
25 102
25 102
25 102
1
A00
A00
A00
5
4
3
2
1
SSID = Thermal
Fan controller1
FAN261
R2605
R2605
Do Not Stuff
3D3V_S0 3D3V_S0
D D
3D3V_S0
1
C2601
SC10U6D3V3MX-GP
C2601
SC10U6D3V3MX-GP
12
12
84.03904.L06
84.03904.L06
2ND = 84.03904.P11
2ND = 84.03904.P11
C C
3
PMBS3904-1-GP
PMBS3904-1-GP
2
Q2603
Q2603
12
C2606
DY
DY
C2606 Do Not Stuff
Do Not Stuff
1
NCT7718_DXP
NCT7718_DXN
C2602
C2602
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2607
C2607 SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
2.System Sensor, Put on palm rest
12
R2601
X02 0510
Layout Note:
C2812 close U2801
Layout Note:
Both DXN and DXP routing 10 mil trace width and 10 mil spacing.
3D3V_S0
R2603 18K7R2F-GPR2603 18K7R2F-GP
B B
1 2
R2604 2KR2F-3-GPR2604 2KR2F-3-GP
1 2
ALERT#
T_CRIT#
R2601 Do Not Stuff
Do Not Stuff
SML1_DATA18,24,76
SML1_CLK18,24,76
THM26
THM26
1
VDD
2
D+
3
D-
T_CRIT#
ALERT#
T_CRIT#4GND
NCT7718W-GP
NCT7718W-GP
74.07718.0B9
74.07718.0B9
1204 change to PCH_PWROK
PCH_PW ROK17,24,36
THERM_SYS_SHDN#
SCL
SDA
6
2
5
34
Q2601
Q2601 2N7002KDW-GP
2N7002KDW-GP
8 7
ALERT#
6 5
Q2602
Q2602
G
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
3rd = 84.07002.I31
3rd = 84.07002.I31
4th = 84.2N702.W31
4th = 84.2N702.W31
1
23
RN2602
RN2602 SRN2K2J-1-GP
SRN2K2J-1-GP
4
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F
4th = 84.2N702.F3F
12
DY
DY
C2608
C2608
D
DY
DY
DY
DY
Do Not Stuff
Do Not Stuff
12
12
C2610
C2610 Do Not Stuff
Do Not Stuff
THM_SML1_DATA
THM_SML1_CLK
THM_SML1_CLK THM_SML1_DATA
C2609
C2609
Do Not Stuff
Do Not Stuff
Layout Note:
Signal Routing Guideline: Trace width = 15mil
PURE_HW _SHUTDOWN# 24,36,76
FAN1_DAC_124
Layout Note:
Need 10 mil trace width.
5V_S0
FAN_TACH124
Do Not Stuff
Do Not Stuff
Do Not Stuff
1 2
DY
DY
FAN_VCC_1
C2604
C2604
X02 0510
Do Not Stuff
Do Not Stuff
12
DY
DY
FAN261
FON#
1
FSM#
2
VIN
3
VOUT VSET4GND
APL5606AKI-TRG-GP
APL5606AKI-TRG-GP
74.05606.A71
74.05606.A71
2nd = 74.02113.0E1
2nd = 74.02113.0E1
R2606
R2606
1 2
21
D2601
D2601
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
2ND = 83.R5003.H8H
2ND = 83.R5003.H8H
3rd = 83.5R003.08F
3rd = 83.5R003.08F
GND GND GND
FAN_TACH1_C
FAN_VCC_1
12
C2603
C2603
DY
DY
Do Not Stuff
Do Not Stuff
8 7 6 5
FAN_TACH1 FAN_VCC_1
ETY-CON3-8-GP
ETY-CON3-8-GP
20.F1841.003
20.F1841.003
5V_S0
12
12
FAN1
FAN1
4
1 2
3
5
AFTP2601AFTP2601
1
AFTP2602AFTP2602
1
C2611
C2611
C2605
C2605
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
A A
5
4
3
2
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Thermal NCT7718W/Fan
Thermal NCT7718W/Fan
Thermal NCT7718W/Fan
e Document Number Rev
Size Document Number Rev
Size Document Number Rev
Siz A3
A3
A3
Tuesday, June 25, 2013
Tuesday, June 25, 2013
Tuesday, June 25, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Hadley 17"
Hadley 17"
Hadley 17"
26 102
26 102
26 102
1
A00
A00
A00
5
4
3
2
1
SSID = AUDIO
D D
12
C2702
C2702 SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
LDO1_CAP
27
25
26
AVSS1
AVDD1
LDO1_CAP
LINE2_L LINE2_R LINE1_L LINE1_R CPVREF
MIC_CAP
MIC2_R/SLEEVE
MIC2_L/RING2
MONO_OUT
SENSE_B SENSE_A
12
AUD_PC_BEEP
MIC2_VREFO 29
AUD_AGND
+5V_AVDD AUD_AGND
JDREF
+3V_AVDD
24 23 22 21 20 19 18 17 16 15 14 13
MIC_CAP
JDREF
AUD_SENSE_A
X02 0510
1 2
12
12
C2711
C2711
C2710
C2710
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
LINE1_L 29 LINE1_R 29
C2713 SC10U6D3V3MX-G PC2713 SC10U6D3V3MX -GP
1 2
SLEEVE 29 RING2 29
R2707 20KR 2F-L-GPR2707 20KR 2F-L-GP
1 2
1 2
R2709
R2709
39K2R2F-L-GP
39K2R2F-L-GP
Layout Note:
Place close to Pin 13
HDA_SPKR20
KBC_BEEP24
Layout Note:
Place close to Pin 26
AUD_AGND
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
AUD_SENSECOMBO-GPI
5V_S0+5V_AVDD
R2703
R2703 Do Not Stuff
Do Not Stuff
AUD_AGND
Layout Note:
Width>40mil, to improve Headpohone Crosstalk noise
AUD_AGND
AUD_SENSE 29
RN2701
RN2701
2 3 1
4
Do Not Stuff
Do Not Stuff
RN
RN
AUD_AGND
AUD_AGND
HDA_SPKR_R
KBC_BEEP_R
EC2707 SCD1 U10V2KX-5GPEC2707 S CD1U10V2KX- 5GP
1 2
EC2706 SCD1 U10V2KX-5GPEC2706 S CD1U10V2KX- 5GP
1 2
EC2705 SCD1 U10V2KX-5GPEC2705 S CD1U10V2KX- 5GP
1 2
EC2704 SCD1 U10V2KX-5GPEC2704 S CD1U10V2KX- 5GP
1 2
EC2703 Do Not Stuff
EC2703 Do Not Stuff
1 2
DY
DY
R2706
R2706
1 2
Do Not Stuff
Do Not Stuff
X02 0510
Layout Note:
Tied at point only under Codec or near the Codec
D2701
D2701
2
1
BAT54CPT-2- GP
BAT54CPT-2- GP
75.00054.K7D
75.00054.K7D
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
3
12
C2720
C2720
AUD_PC_BEEPAUD_PC _BEEP_C
1 2
R2717
R2717 1KR2J-1-GP
1KR2J-1-GP
0115 R2717 change to 1K
LINE1_VREFO_R29 LINE1_VREFO_L29
3D3V_S0 +3V_AVDD
25mA
X02 0510
R2701
R2701
1 2
Do Not Stuff
Do Not Stuff
1.5A
5V_S0 +5V_PVDD
R2702
R2702 Do Not Stuff
Do Not Stuff
R2704
R2704 Do Not Stuff
Do Not Stuff
X02 0510
C C
3D3V_S0
1D5V_S0
X02 0510
R2705
R2705
1 2
Do Not Stuff
Do Not Stuff
R2710 Do Not Stuff
R2710 Do Not Stuff
1 2
DY
DY
Add R2710 DY(3D3V_S0)
Azalia I/F EMI
EC2708
EC2708
12
DY
B B
DY
Do Not Stuff
Do Not Stuff
12
12
Layout Note:
Close pin41
HDA_CODE C_SDOUT HDA_CODE C_BITCLK
EC2709
EC2709
12
DY
DY
Do Not Stuff
Do Not Stuff
12
AUD_AGND
C2706
C2706
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C2701
C2701
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
Close pin36
C2707
C2707
C2708
C2708
12
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
Layout Note:
Close pin46
+3V_1D5V_AVDD
12
C2715
C2715
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
AUD_AGND
C2709
C2709
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Close pin40
DMIC_DATA52 DMIC_CLK52
Close pin3
Do Not Stuff
Do Not Stuff
C2723
C2723
Do Not Stuff
Do Not Stuff
AUD_AGND AUD_AGND
AMP_MUTE#24
C2724
C2724
DY
DY
DY
DY
1 2
Close pin2
1 2
1 2
Do Not Stuff
Do Not Stuff
R2708
R2708
C2712
C2712
1 2
AUD_SPK_L+29
AUD_SPK_L-29 AUD_SPK_R-29 AUD_SPK_R+29
TP2702TP2702
HDA_CODE C_SDOUT19 HDA_CODE C_BITCLK19
HDA_SDIN019
HDA_CODE C_SYNC19
HDA_CODE C_RST#19,29
AUD_HP1_JAC K_L29 AUD_HP1_JAC K_R29
C2703
C2703
SC1U10V2KX-1G P
SC1U10V2KX-1G P
LDO2_CAP
SC10U6D3V3MX- GP
SC10U6D3V3MX- GP
+3V_1D5V_AVDD
+5V_PVDD
AUD_SPK_L+ AUD_SPK_L­AUD_SPK_R­AUD_SPK_R+
+5V_PVDD
EAPD#
1
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
1 2
R2714 Do Not StuffR2714 Do Not Stuff
1 2
R2716 100R2F-L1-GP-UR2716 100R2F-L1-G P-U
A00 0624
R2719 Do Not StuffR2719 Do Not Stuff R2720 Do Not StuffR2720 Do Not Stuff
12
+3V_AVDD
HDA27
HDA27
CBP
37
CBP
38
AVSS2
39
LDO2_CAP
40
AVDD2
41
PVDD1
42
SPK_L+
43
SPK_L-
44
SPK_R-
45
SPK_R+
46
PVDD2
47
PDB
48
SPDIFO/GPIO2
49
GND
ALC3223-CG-G P
ALC3223-CG-G P
+3V_AVDD
12
12
C2717
C2717
C2716
C2716
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DMIC_DATA_R
DMIC_CLK_R
1 2 1 2
1 2
R2718 Do Not StuffR2718 Do Not Stuff
HDA_CODE C_SYNC
HDA_CODE C_RST#
SC1U10V2KX-1G P
SC1U10V2KX-1G P C2704
C2704
1 2
CPVEE
CBN
35
33
34
32
36
CBN
CPVDD
DVDD1GPIO0/DMIC_DATA2GPIO1/DMIC_CLK3DVSS4SDATA_OUT5BIT_CLK6LDO3_CAP7SDATA_IN8DVDD_IO9SYNC10RESET#11PCBEEP
CODEC_SD OUT_R CODEC_BITC LK_R
HDA_CODE C_SDIN0
30
29
31
CPVEE
HP_OUT_L
HP_OUT_R
MIC2_VREFO
LINE1_VREFO_L
LINE1_VREFO_R
LDO3_CAP
C2718SC4D7U6D3V3KX-GP C2718SC4D7U6D3V3KX-GP
12
C2705
C2705
12
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
AUD_VREF
28
VREF
12
C2719SCD1U1 0V2KX-5GP C2719SCD1U10V2KX-5GP
A A
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Title
Title
Title
e Document Numb er Rev
Size Document Num ber Rev
Size Document Num ber Rev
Siz
A2
A2
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O. C.
Audio Codec ALC3223
Audio Codec ALC3223
Audio Codec ALC3223
Hadley 17"
Hadley 17"
Hadley 17"
1
27 102Tuesday, June 25, 2013
27 102Tuesday, June 25, 2013
27 102Tuesday, June 25, 2013
A00
A00
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Hadley 17"
Hadley 17"
Hadley 17"
Reserved
Reserved
Reserved
1
28 102Tuesday, June 25, 2013
28 102Tuesday, June 25, 2013
28 102Tuesday, June 25, 2013
A00
A00
A00
5
4
3
2
1
SSID = AUDIO
Speaker
SPK1
X02 0510
AUD_SPK_R+_C
R2904Do Not Stuff R2904Do Not Stuff
AUD_SPK_R+27 AUD_SPK_R-27
D D
AUD_SPK_L+27 AUD_SPK_L-27
12
DY
DY
EC2901
EC2901
Do Not Stuff
Do Not Stuff
12
DY
DY
DY
DY
EC2902
EC2902
EC2903
Do Not Stuff
Do Not Stuff
EC2903
Do Not Stuff
Do Not Stuff
12
12
DY
DY
EC2904
EC2904
Do Not Stuff
Do Not Stuff
12 12
12 12
R2903Do Not Stuff R2903Do Not Stuff R2902Do Not Stuff R2902Do Not Stuff R2901Do Not Stuff R2901Do Not Stuff
AUD_SPK_R-_C AUD_SPK_L+_C AUD_SPK_L-_C
SPK1
5
1 2
3 4
6
ACES-CON4-29-GP
ACES-CON4-29-GP
20.F1639.004
20.F1639.004
AUD_SPK_L-_C AUD_SPK_L+_C AUD_SPK_R-_C AUD_SPK_R+_C
CONN Pin Pin1 Pin2 Pin3 Pin4
AFTP2901AFTP2901
1
AFTP2902AFTP2902
1
AFTP2903AFTP2903
1
AFTP2904AFTP2904
1
Net name SPK_R+ SPK_R­SPK_L+ SPK_L_
C C
RN2901
RN2901 SRN2K2J-1-GP
SRN2K2J-1-GP
LINE1_L_C
LINE1_R_C
1 2 3
MIC2_VREFO27
RING227
AUD_HP1_JACK_L27
LINE1_L27
LINE1_VREFO_L27
AUD_SENSE27
AUD_HP1_JACK_R27
LINE1_R27
LINE1_VREFO_R27
SLEEVE27
B B
C2907
C2907
1 2
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C2908
C2908
1 2
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
4
R2908 10R2F-L-GPR2908 10R2F-L-GP
1 2
R2921 1KR2J-1-GPR2921 1KR2J-1-GP
1 2
R2912 2K2R2J-2-GPR2912 2K2R2J-2-GP
1 2
R2910 10R2F-L-GPR2910 10R2F-L-GP
1 2
R2922 1KR2J-1-GPR2922 1KR2J-1-GP
1 2
R2913 2K2R2J-2-GPR2913 2K2R2J-2-GP
1 2
AUD_HP1_JACK_R1
Do Not StuffDYEC2908
Do Not Stuff
R2919
10KR2J-3-GP
R2919
10KR2J-3-GP
12
X02 0510
R2906Do Not Stuff R2906Do Not Stuff
12
R2907Do Not Stuff R2907Do Not Stuff
12
R2909Do Not Stuff R2909Do Not Stuff
12
R2911Do Not Stuff R2911Do Not Stuff
EC2907
Do Not StuffDYEC2907
Do Not Stuff
EC2908
12
12
DY
DY
EC2906
SC100P50V2JN-3GP
EC2906
SC100P50V2JN-3GP
EC2905
SC100P50V2JN-3GP
EC2905
SC100P50V2JN-3GP
R2920
10KR2J-3-GP
R2920
10KR2J-3-GP
12
12
12
AUD_AGNDAUD_AGND
12
AUD_AGND
RING2_R
AUD_PORTA_L_R_BAUD_HP1_JACK_L1
AUD_PORTA_R_R_B
SLEEVE_R
1219 Update Connector List
Combo Jack
HPMIC1
HPMIC1
3 1
5 6 2 4
MS
AUDIO-JK404-GP
AUDIO-JK404-GP
22.10270.V01
22.10270.V01
AUD_AGND
AUD_PORTA_L_R_B AUD_PORTA_R_R_B
AUD_SENSE
AFTP2906AFTP2906
1
AFTP2907AFTP2907
1
AFTP2908AFTP2908
1
AFTP2909AFTP2909
1
X01 0311 Change HPMIC1 from 22.10270.S81 to 22.10270.V01
1128
AUD_PORTA_R_R_B
AUD_PORTA_L_R_B
RING2_R
AUD_SENSE
SLEEVE_R
ED2904
Do Not Stuff
ED2904
DY
DY
12
Do Not Stuff
Do Not Stuff
Do Not Stuff
ED2902
Do Not Stuff
ED2902
DY
DY
12
Do Not Stuff
Do Not Stuff
Do Not Stuff
ED2901
Do Not Stuff
ED2901
Do Not Stuff
12
DY
A A
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
5
DY
DY
12
ED2903
Do Not Stuff
ED2903
Do Not Stuff
Do Not Stuff
Do Not Stuff
DY
DY
ED2905
Do Not Stuff
ED2905
Do Not Stuff
12
4
12
R2915
R2915 220KR2J-L2-GP
220KR2J-L2-GP
AUD_AGND
U2901
U2901
S G
5
D
6
2N7002KDW-GP
2N7002KDW-GP
84.2N702.A3F
84.2N702.A3F
2nd = 84.DM601.03F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F
4th = 84.2N702.F3F
Do Not Stuff
Do Not Stuff
D
34
G
2
S
1
3
R2918
R2918
+3V_AVDD5V_PWR_2
12
DY
DY
X02 0510
R2917
R2917
1 2
Do Not Stuff
Do Not Stuff
POP_G2POP_G1
12
C2901
C2901
DY
DY
Do Not Stuff
Do Not Stuff
HDA_CODEC_RST# 19,27
SLEEVE 27
2
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Speaker/HPMIC CONN
Speaker/HPMIC CONN
e Document Number Rev
Size Document Number Rev
Size Document Number Rev
Siz
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Speaker/HPMIC CONN
Hadley 17"
Hadley 17"
Hadley 17"
29 102Tuesday, June 25, 2013
29 102Tuesday, June 25, 2013
29 102Tuesday, June 25, 2013
1
A00
A00
A00
5
LAN CHIP
D D
Q3001
Q3001
DY
DY
12
12
C3012
C3012
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
G
S
2N7002K-2-GP
2N7002K-2-GP
X02 0510
R3006
R3006
1 2
Do Not Stuff
Do Not Stuff
PM_LAN_ENABLE24
R3023
R3023
Do Not Stuff
Do Not Stuff
3D3V_LAN_S5 VDDREG
C C
12
12
C3007
C3007
C3008
C3008
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1127 remove R3017 R3018 0 Ohm Resistance
3D3V_S5
12
C3013
SCD1U10V2KX-5GP
C3013
SCD1U10V2KX-5GP
12
D
LAN_SW
LAN_SW
R3021
R3021 10KR2J-3-GP
10KR2J-3-GP
LAN_ENABLE_R_C
12
C3009
C3009
Do Not Stuff
Do Not Stuff
R3022
R3022 20KR2F-L-GP
20KR2F-L-GP
1 2
LAN_SW
LAN_SW
12
C3010
C3010
Do Not Stuff
Do Not Stuff
PM_LAN_ENABLE_R
main: 84.00102.031 2nd: 84.03403.031
X5R
X02 0510
R3034
R3034
1 2
Do Not Stuff
Do Not Stuff
B B
REGOUT
12
DY
DY
C3018
C3018
Do Not Stuff
Do Not Stuff
L3010
L3010
1 2
Do Not Stuff
Do Not Stuff
LAN_SW
LAN_SW
Do Not Stuff
Do Not Stuff
LAN_SW
LAN_SW
C3024
C3024
12
Do Not Stuff
Do Not Stuff
LAN_SW
LAN_SW
X02 0510
R3007
R3007
1 2
Do Not Stuff
Do Not Stuff
C3014
C3014
12
Do Not Stuff
Do Not Stuff
X5R
4
DS
3D3V_LAN_S5
DY
DY
C3005
C3005
Do Not Stuff
Do Not Stuff
12
12
C3003
C3003 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
PA102FMG-GP-U
PA102FMG-GP-U Q3004
Q3004
G
0109: Modify
X01 0311 Remove R3024. Change R3039 to 10k and PH to 3D3V_LAN_S5
Pin12 Pull VCC33 (3D3V_S0) If RTD3 Not Supported
1110: C3028 Place Near Pin12
VDD10
12
12
C3019
C3019
C3020
C3020
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C3021
C3021
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
EVDD10
12
C3016
C3016
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
C3022
C3022
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C3023
C3023
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1127 Pin 2&4 NC
LANXOUT
LANXIN
LAN_SW
LAN_SW
ENSWREG
3D3V_LAN_S5
LAN_WAKE#
C3028
C3028 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
LAN_WAKE#24
CLK_PCIE_LAN_REQ4#18,20
3
41
3D3V_LAN_S5
12
R3039
R3039 10KR2J-3-GP
10KR2J-3-GP
C3011
C3011
1 2
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
X3001
X3001 XTAL-25MHZ-155-GP
XTAL-25MHZ-155-GP
2nd = 82.30020.G71
2nd = 82.30020.G71
2 3
X01 0319 Change CL cap C3001 C3011 to 15p based on vendor test result.
C3001
C3001
1 2
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
12
R3036
R3036 Do Not Stuff
Do Not Stuff
12
X02 0510
R3037
R3037 Do Not Stuff
Do Not Stuff
LAN_WAKE# ISOLATE#
PLT_RST#_LAN
CLK_PCIE_LAN_P4 CLK_PCIE_LAN_N4
PCIE_PTX_LANRX_P4_C PCIE_PTX_LANRX_N4_C
LAN_TXP_C_PCH_RXP4 LAN_TXN_C_PCH_RXN4
82.30020.D41
82.30020.D41
VDD10 VDD10 VDD10
VDD10 EVDD10 3D3V_LAN_S5
3D3V_LAN_S5 3D3V_S0
3D3V_LAN_S5 CARD_3D3V VDD33/18 VDDREG
VDD33/18
U3001
U3001
3
AVDD10
8
AVDD10
46
AVDD10
33
DVDD10
20
EVDD10
11
AVDD33
48
AVDD33
12
DVDD33
32
DVDD33
13
CARD_3V3
27
VDD33/18
35
VDDREG
39
LANWAKE#
31
ISOLATE#
29
CLKREQ#
30
PERST#
23
REFCLK_P
24
REFCLK_N
21
HSIP
22
HSIN
25
HSOP
26
HSON
RTL8411B-CGT-GP
RTL8411B-CGT-GP
2
CARD_3D3V_S0
R3009
R3009
1 2
Do Not Stuff
Do Not Stuff
Close To Pin 27
12
12
C3017
C3017
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
DY
MDIP0 MDIN0 MDIP1 MDIN1 MDIP2 MDIN2 MDIP3 MDIN3
CKXTAL1 CKXTAL2
ENSWREG_H
REGOUT
RSET
LED_CR
LED0
LED1/GPO
LED3
SD_D0/MS_D1
SD_D1
SD_D2/MS_CLK
SD_D3/MS_D3
SD_CLK/MS_D0
SD_SMD/MS_D2
SD_WP/MS_BS
SD_CD# MS_CD#
GND
C3027
C3027
Do Not Stuff
Do Not Stuff
1 2 4 5 6 7 9 10
44 45
34 36 47
40 41 38 37
15 14 19 18
16 17 28
42 43
49
CARD_3D3V
LED_CR LED0 LED1 LED3
Close To Pin 13
12
LANXIN LANXOUT
ENSWREG REGOUT RSET
TP3004 Do Not StuffTP3004 Do Not Stuff
1
TP3003 Do Not StuffTP3003 Do Not Stuff
1
TP3002 Do Not StuffTP3002 Do Not Stuff
1
TP3001 Do Not StuffTP3001 Do Not Stuff
1
SP2 SP1 SP6 SP5
SP3 SP4 SP7
A00 0625
R3017 0R2J-2-GPR3017 0R2J-2-GP R3018 0R2J-2-GPR3018 0R2J-2-GP R3019 0R2J-2-GPR3019 0R2J-2-GP R3020 0R2J-2-GPR3020 0R2J-2-GP
R3032 10R2J-2-GPR3032 10R2J-2-GP R3033 0R2J-2-GPR3033 0R2J-2-GP R3035 0R2J-2-GPR3035 0R2J-2-GP
C3015
C3015
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PLT_RST#17,24,58,65,73
LAN_MDI0P 31
LAN_MDI0N 31
LAN_MDI1P 31 LAN_MDI1N 31 LAN_MDI2P 31 LAN_MDI2N 31 LAN_MDI3P 31 LAN_MDI3N 31
12 12 12 12
12 12 12
R3038
R3038
2K49R2F-GP
2K49R2F-GP
3D3V_S0
12
1KR2J-1-GP
1KR2J-1-GP
2
1
1 2
3D3V_LAN_S5
DY
DY
Q3003
Q3003 Do Not Stuff
Do Not Stuff
R3016
R3016 Do Not Stuff
Do Not Stuff
ISOLATE#
R3014
R3014
R3015
R3015
DY
DY
Do Not Stuff
Do Not Stuff
1
23
RN3001
RN3001 Do Not Stuff
Do Not Stuff
DY
DY
4
Q402_1
1
PLT_RST#_LAN
3
12
SP2/SD_D0/MS_D1 33 SP1/SD1 33 SP6/SD_D2/MS_CLK 33 SP5/SD_D3/MS_D3 33
SP3/SD_CLK/MS_D0 33 SP4/SD_CMD/MS_D2 33 SP7/SD_W P/MS_BS 33
SD_CD# 33 MS_CD# 33
12
A A
5
4
LAN_TXP_C_PCH_RXP4 LAN_TXN_C_PCH_RXN4
PCIE_PTX_LANRX_P4_C PCIE_PTX_LANRX_N4_C
3
C3025 SCD1U10V2KX-5GPC3025 SCD1U10V2KX-5GP
1 2 1 2
C3026 SCD1U10V2KX-5GPC3026 SCD1U10V2KX-5GP
PCIE_PRX_LANTX_P4 16 PCIE_PRX_LANTX_N4 16
PCIE_PTX_LANRX_P4_C 16 PCIE_PTX_LANRX_N4_C 16
CLK_PCIE_LAN_P4 18 CLK_PCIE_LAN_N4 18
2
UMA
UMA
UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
LOM(RTL8411B)
LOM(RTL8411B)
LOM(RTL8411B)
Hadley 17"
Hadley 17"
Hadley 17"
30 102Tuesday, June 25, 2013
30 102Tuesday, June 25, 2013
30 102Tuesday, June 25, 2013
1
A00
A00
A00
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