Dell LA-5151P KAT00 DIS, Inspiron 1745, Studio 1745 Schematic

A

B

C

D

E

Model Name:

PCB NO:

1 1

PCB P/N: DA80000E400

BOM P/N:

KAT00 DIS

LA-5151P

(M92)43169531L01

(M96)43169531L02

Compal Confidential

2 2

Schematic Document

POITIER Montevina M96/M92

2009 / 06/ 12

Rev:1.0 (A00)

3 3

@ : Nopop component

92@ : Use ATI M92 Graphic solution
96@ : Use ATI M96 Graphic solution

4 4

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

A

B

C

D

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

LA-5151P

LA-5151P

LA-5151P

1 60Friday, June 12, 2009

1 60Friday, June 12, 2009

1 60Friday, June 12, 2009

E

R10 (A00)

R10 (A00)

R10 (A00)

5

Block Diagram
Compal confidential
Model : KAT00

D D

C C

B B

A A

CRT CONN

+5VS

LVDS CONN

+LCDVDD
+3.3V_ALW

DP CONN

+5VS

HDMI CONN

+5VS

P.35

P.37

P.36

To Card-reader subboard

8 IN 1 CONN

+3VS

IEEE1394

Mini Card 3

TV tuner

+3VS

P.28 P.27 P.27

DC IN

P.45

DC/DC Interface

P.45~52 P.52

5

P.35

BATT IN

ME & LEDPower Sequence

FAN

+5V_ALW
+3V_ALW

VGA

LVDS

DPA

DPB

CardBus

OZ888GS0

+3VS
+1.8VS

Express Card

Mini Card 2

WLAN

+3VS
+1.5VS+1.5VS

USB[4]

P.34

P.7

+3.3V_ALW

AMD M96(M92)

29 x 29 mm

VRAM 64Mx16

(M92x4 / M96x8)

P.32

P.28

PCIE2PCIE3

VCORE (IMVP-6)

CHARGER

GPU/1.1V 1.05V/1.8V

4

Thermal

EMC1402

PCIE-E 16X

P.38,39,40,41,42

P.43,44

PCI Express BUS

Mini Card 1

WWAN

+3VS
+1.5VS

USB[5]USB[6]

1.5V/0.75V

P.51 P.49

3V/5V

4

Pentium-M

Penryn -4MB (Socket P)

P.7

+1.5VS

+1.05V_VCCP

+VCC_CORE

H_A#(3..35) H_D#(0..63)

uFCPGA CPU

478pin

System Bus

FSB 1066 MHz

INTEL

Cantiga

+1.5VS

+1.05V_VCCP

+3.3VS

1329pin BGA

DMI

+1.5VS
100MHz

+5V_ALW

+5VS

+RTC_CELL

+3.3VS

+3.3V_ALW_ICH

+1.5VS

+1.05V_VCCP

GPIO5

FFS

P.20

INTEL

ICH9-M

676pin BGA

P.19,20,21,22,23

LPC BUS

+3VS
33MHz

ENE KBC

KB926QFD3

+RTC_CELL

+3.3V_ALW

Int.KBD &
BL

P.47P.46

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

P.48P.50

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

P.7,8,9

P.10,11,12,13,14,15,16

USB2.0

S-ATA(1)

PCI-E

Azalia I/F

S-ATA(3)

SATA2

E-ODD

+3VS

+5VS

P.31

Touch Pad

P.32P.32

3

2

CPU ITP Port

+1.05VS_CK505

Memory BUS (DDR3)

+1.5V 1066 MHz

S-HDD-2

P.29 P.29 P.29

+5VS

16Mx1sector

Flash ROM

SPI

P.31

Right Front Side.

Right behind side.

SATA0SATA1

S-HDD-1

+5VS

MMB

To MMB subboard

P.32

2

P.7

+3.3V_ALW

Azalia Codec

92HD73C

+3.3VS
+VDDA

AMP

MAX4411x2

P.30

HeadPhone &
MIC Jack

+3.3VS

1

Clock Generator

CK505

ICS9LPRS387AKLFT

+3VS_CK505
+1.05VS_CK505

DDRIII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8

+1.5V

USB Port X1

+5V_ALW

USB Port1 X1

+5V_ALW

Bluetooth

Touch Screen

Camera

P.6

P.17,18

To Card-reader
subboard

To Single USB
subboard

P.30

P.32

P.30

Charge USB/E-SATA

RTL8111DL

P.25

P.25

Ports X1

+5V_ALW

P.24

MAX9736A

B+

MAX9736A

B+

AMP

AMP

P.30

RJ45

Speaker

P.26

Subwoofer

P.26

Dig. MIC

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

LA-5151P

LA-5151P

LA-5151P

2 60Friday, June 12, 2009

2 60Friday, June 12, 2009

2 60Friday, June 12, 2009

1

P.30

P.32

P.30

R10 (A00)

R10 (A00)

R10 (A00)

A

Voltage Rails

O MEANS ON X MEANS OFF

Symbol Note :

power
plane

+B

State

1 1

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O

O

O

O

O

X

+5VALW

+3VALW

O

O

O

O

X

X X X

+1.5V

O

X X

X

+5VS

+3VS

+1.8VS

+1.5VS

+1.1VS

+VCCP

+0.75VS

+CPU_CORE

OO

OO

X

X

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
DEBUG@ : means just reserve for debug.

USB Port

0

1

2

3

4

5

6

7

8

9

10

11

Device

USB&ESATA
Reader/BD

USB board
NC

WLAN
WWAN
WPAN
Express

NC
Touch screen
Bluetooth

Camera

SATA Port

0

1

4

5

Device

JSATA1
JSATA2

JESA1
JODD

PCIE Port

1

2

3

4

5

6

Device

JWWAN1
JWLAN1

JWPAN1

Reader/BD (OZ888)

JEXP1
RTL8111DL

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

A

X

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Note List

Note List

Note List

LA-5151P

LA-5151P

LA-5151P

3 60Friday, June 12, 2009

3 60Friday, June 12, 2009

3 60Friday, June 12, 2009

R10 (A00)

R10 (A00)

R10 (A00)

5

4

3

2

1

D D

VR_ON

ISL6266ACRZ-T
(PU10)

ADAPTER

VGA_ON

ISL6268CAZ-T
(PU9)

SYSON

B+

BATTERY

SUSP#

CHARGER

C C

SUSP#

TPS51117RGYR
(PU8)

TPS51117RGYR
(PU6)

TPS51427

44000mA

20000mA

9794mA

9857mA

+CPU_CORE

+GPU_CORE

+1.5V

+1.05V_VCCPP

SUSP#

0 Ohm

SI4392
(Q45)

RT9025
(PU15)

RT9026
(PU11)

+1.05VS_CK505

8881mA

+1.5VS

913mA

+1.1VS

?mA

+0.75VS

(PU5)

+5VALW

4400mA

+5VS

RUNON

SI4800BDY
(Q51)

2000mA 7377mA 669mA160mA 20mA

USB_EN#

TPS2062ADR
(U17)

+5V_CHGUSB

EN_EOL#

SI3456BDY
(Q3)

+LAN_IO

EN_EOL#

RTL8111DL

B B

FUSE

0 Ohm

0 Ohm

+CRT_VCC

+AVDD_AUDIO

+5VS_KBL

(U9)

+LAN_VDD

+3VALW

SUSP

FBM-11-160808-601-T
(L29)

+EC_AVCC

SUSP

SI4392DY
(Q50)

+3VS

0 Ohm

0 Ohm

0 Ohm

0 Ohm

+3VS_CK505

+DVDD_AUDIO

+3V_WLAN

+3V_WLAN

SUSP#

RT9025
(PU13)

+1.8VS

VDDEN

SI2310BDS-T1-E3

(Q25)

+LCDVDD

EN_EOL#

SI2310BDS

(Q34)

+3VS_DELAY

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Power Rail

Power Rail

Power Rail

LA-5151P

LA-5151P

LA-5151P

4 60Friday, June 12, 2009

4 60Friday, June 12, 2009

4 60Friday, June 12, 2009

1

R10 (A00)

R10 (A00)

R10 (A00)

5

D D

G16

A13

ICH9-M

4

ICH_SMBCLK

ICH_SMBDATA

2.2K

2.2K

10K

+3VALW

3

2N7002

2N7002

ICH_SM_DA

ICH_SM_CLK

2.2K

2.2K

+3.3VS

200

202

200

202

2

DIMMA

DIMMB

1

SMBUS Address 0xA0

SMBUS Address 0XA4

10

CLK GEN

2.2K

C C

SCL1

SDA1

77

78

EC_SMB_CK1

EC_SMB_DA1

2.2K

+3VALW

100 ohm

100 ohm

7

6

BATTERY

CONN

9

FFS

SMBUS Address Read D3 (H)
SMBUS Address Write D2 (H)

2.2K

2.2K

KBC

SCL2

SDA2

112

111

EC_SMB_CK2

EC_SMB_DA2

KB926QFD3

17

B B

18

EC_FB_SCLK

EC_FB_DATA

2.2K

2.2K

MMB

+3VS

+3VS

Need make sure EC will disable this SMB port in S5 /AC mode.

32

30

32

30

32

30

32

30

8

7

WLAN

WPAN

WWAN

EXPRESS
CARD

Thermal
Sensor

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address: 100_1100 b

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0

DDR SO-DIMM 1

CLOCK GENERATOR (EXT.)

HEX

A0

D2

ADDRESS

1 0 1 0 0 0 0 0

1 0 1 0 0 1 0 0A4

1 1 0 1 0 0 1 0

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

SMBUS TOPOLOGY

SMBUS TOPOLOGY

SMBUS TOPOLOGY

LA-5151P

LA-5151P

LA-5151P

5 60Friday, June 12, 2009

5 60Friday, June 12, 2009

5 60Friday, June 12, 2009

1

R10 (A00)

R10 (A00)

R10 (A00)

5

Routing the trace at least 10mil

1 2

14.318MHZ_16PF_7A14300083

14.318MHZ_16PF_7A14300083

D D

22P_0402_50V8J~D

22P_0402_50V8J~D

2

C8

C8

1

R10 Moidify (short directly)

CPU_STP

CLK_DEBUG_PORT27

CLK_PCI_EC31

PCI_CLK20

C C

CK_PWRGD21

C1509

@C1509

@

10P_0402_50V8J~D

10P_0402_50V8J~D

CLK_XTAL_OUT

R2
0_0402_5%@R20_0402_5%@

CLK_XTAL_IN

Y1

Y1

12

2

C9

C9

22P_0402_50V8J~D

22P_0402_50V8J~D

1

H_STP_CPU#21

H_STP_PCI#21

R941 33_0402_1%R941 33_0402_1%

1 2

1 2

33_0402_1%

33_0402_1%

1 2

33_0402_1%

33_0402_1%

1

1

C1510

@C1510

@

10P_0402_50V8J~D

10P_0402_50V8J~D

2

2

+3VS_CK505

R548

@R548

@

10K_0402_5%

10K_0402_5%

R20

R20

R24

R24

+3VS_CK505

+1.05VS_CK505

12

12

@R549

@

10K_0402_5%

10K_0402_5%

R549

H_STP_CPU#

H_STP_PCI#

PCI2_TME

R_CLK_PCI_EC

27_SEL

ITP_EN

CLK_XTAL_IN

CLK_XTAL_OUT

Place close U1

CLK_48M_ICH21

CLK_14M_ICH21

C1518

@C1518

@

10P_0402_50V8J~D

10P_0402_50V8J~D

R38 33_0402_1%R38 33_0402_1%

1 2

R41 33_0402_1%R41 33_0402_1%

1 2

1

1

C1511

@ C1511

@

10P_0402_50V8J~D

10P_0402_50V8J~D

2

2

FSA

FSB

FSC

T1PAD T1PAD

(14.318 reference output)

Place clolse U1

B B

PCI

SRC

CPU

CLKSEL1

0

FSA

CLKSEL0

MHz

266

MHz

1000

MHz

33.30

FSC FSB REF

CLKSEL2

*

0 1000 133 33.31 14.318 96.0 48.0

U1

U1

6

VDDREF

19

VDD48

72

VDDCPU

12

VDDPCI

27

VDDPLL3

55

VDDSRC

52

VDDSRC_IO

38

VDDSRC_IO

62

VDDSRC_IO

31

VDDPLL3_IO

66

VDDCPU_IO

23

VDD96_IO

53

CPU_STOP#

54

PCI_STOP#

13

PCI1

14

PCI2/TME

15

PCI3

16

PCI4/27_SELECT

17

PCI_F5/ITP_EN

1

CK_PWRGD/PD#

5

X1

4

X2

11

NC

20

USB_48MHz/FSLA

2

FSLB/TEST_MODE

7

FSLC/TEST_SEL/REF0

8

REF1

69

GNDCPU

3

GNDREF

18

GNDPCI

22

GND48

30

GND

26

GND

34

GNDSRC

59

GNDSRC

42

GNDSRC

ICS9LPRS387BKLFT_MLF72_10x10

ICS9LPRS387BKLFT_MLF72_10x10

DOT_96

MHz

MHz

14.318 96.0 48.0

0 1001 200 33.30 14.318 96.0 48.0

A A

0 1001 166 33.31 14.318 96.0 48.0

1 1000 333 33.30 14.318 96.0 48.0

1 1000 100 33.31 14.318 96.0 48.0

1 1001 400 33.30 14.318 96.0 48.0

1 1 1

5

Reserved

4

27MHz_NonSS/SRCT1_LPR/SE1

27MHz_SS/SRCC1_LPR/SE2

CPUT2_ITP_LPR/SRCT8_LPR

CPUC2_ITP_LPR/SRCC8_LPR

B version P/N :
SA000020H10

USB
MHz

4

SDATA

SCLK

CPUT0_LPR_F

CPUC0_LPR_F

CPUT1_LPR_F

CPUC1_LPR_F

SRCT0_LPR/DOTT_96_LPR

SRCC0_LPR/DOTC_96_LPR

SRCT2_LPR/SATAT_LPR

SRCC2_LPR/SATAC_LPR

SRCT3_LPR

SRCC3_LPR

SRCT4_LPR

SRCC4_LPR

SRCT6_LPR

SRCC6_LPR

SRCT7_LPR

SRCC7_LPR

SRCT9_LPR

SRCC9_LPR

SRCT10_LPR

SRCC10_LPR

SRCT11_LPR

SRCC11_LPR

CR#3

CR#4

CR#6

CR7#

CR#9

CR10#

CR#11

CR#A

FSA

R48 2.2K_0402_5%R48 2.2K_0402_5%

CPU_BSEL08

FSB

CPU_BSEL18

FSC

R55 10K_0402_5%R55 10K_0402_5%

CPU_BSEL28

CLK_SMBDATA

9

CLK_SMBCLK

10

R_CPU_BCLK

71

R_CPU_BCLK#

70

R_MCH_BCLK

68

R_MCH_BCLK#

67

R_MCH_DREFCLK

24

R_MCH_DREFCLK#

25

R_MCH_SSCDREFCLK

28

R_MCH_SSCDREFCLK#

29

R_CLK_SATA

32

R_CLK_SATA#

33

R_CLK_EXPR

35

R_CLK_EXPR#

36

R_CLK_PCIE_WLAN

39

R_CLK_PCIE_WLAN#

40

R_CLK_VGA

57

R_CLK_VGA#

56

R_CLK_CB

61

R_CLK_CB#

60

R_DMI_ICH

64

R_DMI_ICH#

63

R_CLK_PCIE_GLAN

44

R_CLK_PCIE_GLAN#

45

R_CLK_WPAN

50

R_CLK_WPAN#

51

R_MCH_3GPLL

48

R_MCH_3GPLL#

47

37

41

VGA_CLKREQ#

58

65

43

49

46

21

1 2

R54 0_0402_5%R54 0_0402_5%

1 2

1 2

3

R10 Moidify (short directly)

R4 0_0402_5%@R4 0_0402_5%@

1 2

R3 0_0402_5%@R3 0_0402_5%@

1 2

R5 0_0402_5%@R5 0_0402_5%@

12

R6 0_0402_5%@R6 0_0402_5%@

12

R7 0_0402_5%@R7 0_0402_5%@

1 2

R8 0_0402_5%@R8 0_0402_5%@

1 2

R9 0_0402_5%@R9 0_0402_5%@

1 2

R11 0_0402_5%@R11 0_0402_5%@

1 2

R10 0_0402_5%@R10 0_0402_5%@

1 2

R12 0_0402_5%@R12 0_0402_5%@

1 2

R42 0_0402_5%@R42 0_0402_5%@

1 2

R43 0_0402_5%@R43 0_0402_5%@

1 2

R16 0_0402_5%@R16 0_0402_5%@

1 2

R17 0_0402_5%@R17 0_0402_5%@

1 2

R18 0_0402_5%@R18 0_0402_5%@

1 2

R19 0_0402_5%@R19 0_0402_5%@

1 2

R21 0_0402_5%@R21 0_0402_5%@

1 2

R23 0_0402_5%@R23 0_0402_5%@

1 2

R26 0_0402_5%@R26 0_0402_5%@

1 2

R28 0_0402_5%@R28 0_0402_5%@

1 2

R31 0_0402_5%@R31 0_0402_5%@

1 2

R33 0_0402_5%@R33 0_0402_5%@

1 2

R35 0_0402_5%@R35 0_0402_5%@

1 2

R37 0_0402_5%@R37 0_0402_5%@

1 2

R39 0_0402_5%@R39 0_0402_5%@

1 2

R40 0_0402_5%@R40 0_0402_5%@

1 2

R14 0_0402_5%@R14 0_0402_5%@

1 2

R15 0_0402_5%@R15 0_0402_5%@

1 2

EXP_CLKREQ# 28

WLAN_CLKREQ# 27

R25 10K_0402_5%R25 10K_0402_5%

1 2

CB_CLKREQ# 30

GLAN_CLKREQ# 24

WPAN_CLKREQ# 28

MCH_CLKREQ# 11

CLKSATAREQ# 21

R49 1K_0402_5%R49 1K_0402_5%

1 2

R53 1K_0402_5%R53 1K_0402_5%

1 2

R56 1K_0402_5%R56 1K_0402_5%

1 2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

ICH_SM_DA 17,18,20,21

ICH_SM_CLK 17,18,20,21

CLK_CPU_BCLK 7

CLK_CPU_BCLK# 7

CLK_MCH_BCLK 10

CLK_MCH_BCLK# 10

CLK_MCH_DREFCLK 11

CLK_MCH_DREFCLK# 11

MCH_SSCDREFCLK 11

MCH_SSCDREFCLK# 11

CLK_PCIE_SATA 19

CLK_PCIE_SATA# 19

CLK_PCIE_EXPR 28

CLK_PCIE_EXPR# 28

CLK_PCIE_WLAN 27

CLK_PCIE_WLAN# 27

CLK_PCIE_VGA 38

CLK_PCIE_VGA# 38

CLK_PCIE_CB 30

CLK_PCIE_CB# 30

CLK_DMI_ICH 22

CLK_DMI_ICH# 22

CLK_PCIE_GLAN 24

CLK_PCIE_GLAN# 24

CLK_PCIE_WPAN 28

CLK_PCIE_WPAN# 28

CLK_MCH_3GPLL 11

CLK_MCH_3GPLL# 11

R03 Modify

MCH_CLKSEL0 11

MCH_CLKSEL1 11

MCH_CLKSEL2 11

CPU

MCH

SATA

Express Card

WLAN

VGA

Cardbus

DMI (ICH)

GLAN

WPAN

MCH_3GPLL

2

R1

1 2

+3VS

0_0805_5%R10_0805_5%

+1.05V_VCCP

1 2

R13

R13

0_0805_5%

0_0805_5%

ITP_EN

27_SEL 0 = PIN 24/25 : DOT96 / DOT96#

PCI2_TME

+3VS_CK505 +3VS_CK505 +3VS_CK505

12

R45

@R45

@

10K_0402_5%

10K_0402_5%

ITP_EN 27_SEL PCI2_TME

12

R50

R50
10K_0402_5%

10K_0402_5%

2

+3VS_CK505

C4

0.1U_0402_16V4Z~DC40.1U_0402_16V4Z~D

C3

0.1U_0402_16V4Z~DC30.1U_0402_16V4Z~D

C2

0.1U_0402_16V4Z~DC20.1U_0402_16V4Z~D

C1

1

2

+1.05VS_CK505

1

2

22U_0805_6.3V6M~DC122U_0805_6.3V6M~D

C10

22U_0805_6.3V6M~D

C10

22U_0805_6.3V6M~D

EXP_CLKREQ#

WLAN_CLKREQ#

CB_CLKREQ#

GLAN_CLKREQ#

WPAN_CLKREQ#

MCH_CLKREQ#

CLKSATAREQ#

1

2

C11

0.1U_0402_16V4Z~D

C11

0.1U_0402_16V4Z~D

1

2

1

1

2

2

C12

0.1U_0402_16V4Z~D

C12

0.1U_0402_16V4Z~D

C13

0.1U_0402_16V4Z~D

C13

1

2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

0.1U_0402_16V4Z~D

1

2

R34 10K_0402_5%R34 10K_0402_5%

R32 10K_0402_5%R32 10K_0402_5%

R22 10K_0402_5%R22 10K_0402_5%

R30 10K_0402_5%R30 10K_0402_5%

R27 10K_0402_5%R27 10K_0402_5%

R36 10K_0402_5%R36 10K_0402_5%

R29 10K_0402_5%R29 10K_0402_5%

Port Device REQ#

SRC0

SRC2

PCIE_SATA

SRC3

PCIE_EXPR

SRC4

PCIE_WLAN

SRC6

PCIE_VGA

SRC7

PCIE_CB

SRC8

DMI_ICH

SRC9

PCIE_GLAN

SRC10

PCIE_WPAN WPAN_CLKREQ#

SRC11

MCH_3GPLL

0 = SRC8/SRC8#

*

1 = ITP/ITP#

*

PIN 28/29 : LCDCLK / LCDCLK#
1 = PIN 24/25 : SRC_0 / SRC_0#
PIN 28/29 : 27M / 27M_SS

REQ_A#

REQ#3

REQ#4

REQ#6

REQ#7

REQ#9

REQ#10

REQ#11

0 = Overclocking of CPU and SRC Allowed

1 = Overclocking of CPU and SRC NOT allowed

*

12

R46

@R46

@

10K_0402_5%

10K_0402_5%

12

R51

R51

10K_0402_5%

10K_0402_5%

R47

R47

10K_0402_5%

10K_0402_5%

1 2

@R52

@

10K_0402_5%

10K_0402_5%

1 2

R52

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

LA-5151P

LA-5151P

LA-5151P

1

0.1U_0402_16V4Z~DC70.1U_0402_16V4Z~D

C6

0.1U_0402_16V4Z~DC60.1U_0402_16V4Z~D

C5

0.1U_0402_16V4Z~DC50.1U_0402_16V4Z~D

1

2

C14

0.1U_0402_16V4Z~D

C14

0.1U_0402_16V4Z~D

1

2

+3VS

1

1

2

2

C15

0.1U_0402_16V4Z~D

C15

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

1

2

REQ#_NAME

CLKSATAREQ#

EXP_CLKREQ#

WLAN_CLKREQ#

CB_CLKREQ#

GLAN_CLKREQ#

MCH_CLKREQ#

Clock Generator CK505

Clock Generator CK505

Clock Generator CK505

6 60Friday, June 12, 2009

6 60Friday, June 12, 2009

6 60Friday, June 12, 2009

1

C7

C16

C16

R10 (A00)

R10 (A00)

R10 (A00)

5

4

3

XDP / ITP

XDP_TRST#

R59 54.9_0402_1%R59 54.9_0402_1%

XDP_TCK

1 2

R60 54.9_0402_1%R60 54.9_0402_1%

1 2

2

XDP_TDI

R57 51_0402_1%R57 51_0402_1%

XDP_TMS

1 2

R58 54.9_0402_1%R58 54.9_0402_1%

1 2

1

+1.05V_VCCP

This shall place near CPU

D D

Control

+1.05V_VCCP

CONN@

H_A#[3..16]10

H_ADSTB#010

H_REQ#010
H_REQ#110
H_REQ#210
H_REQ#310

C C

B B

H_REQ#410

H_A#[17..35]10

H_ADSTB#110

H_A20M#19

H_FERR#19

H_IGNNE#19

H_STPCLK#19

H_INTR19

H_NMI19

H_SMI#19

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

CONN@

JCPU1A

JCPU1A

J4

ADDR GROUP 0 ADDR G ROUP 1

ADDR GROUP 0 ADDR G ROUP 1

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Penryn

Penryn

DEFER#

DRDY#
DBSY#

IERR#

LOCK#

CONTROL

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TRST#

XDP/ITP SIGNALS

XDP/ITP SIGNALS

THERMAL

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

ICH

THERMTRIP#

H CLK

H CLK

BCLK[0]
BCLK[1]

RESERVED

RESERVED

ADS#
BNR#
BPRI#

BR0#

INIT#

HIT#

TCK

TDO
TMS

DBR#

H_ADS#

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#

G2

H_HIT#

G6

H_HITM#

E4

AD4
AD3
AD1
AC4
AC2
AC1

XDP_TCK

AC5

XDP_TDI

AA6

TDI

XDP_TDO

AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

H_PROCHOT#

D21
A24
B25

H_THERMTRIP#

C7

CLK_CPU_BCLK

12

A22

R932

R932

A21

100_0402_1%

100_0402_1%

CLK_CPU_BCLK#

H_ADS# 10
H_BNR# 10
H_BPRI# 10

H_DEFER# 10

H_DRDY# 10
H_DBSY# 10

H_BR0# 10

H_INIT# 19

H_LOCK# 10

H_RESET# 10
H_RS#0 10
H_RS#1 10
H_RS#2 10

H_TRDY# 10

H_HIT# 10
H_HITM# 10

T2T2

XDP_DBRESET# 21

R63 68_0402_5%R63 68_0402_5%

H_THERMDA
H_THERMDC

H_THERMTRIP# 11,19

CLK_CPU_BCLK 6

12

Qual core request

CLK_CPU_BCLK# 6

+1.05V_VCCP

H_THERMDA, H_THERMDC
routing together,Trace width /
Spacing = 10 / 10 mil

Qual core 50 ohm

H_IERR#

C17

C17

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C18 2200P_0402_50V7K~DC18 2200P_0402_50V7K~D

1 2

1 2

+3VS

R64 10K_0402_5%R64 10K_0402_5%

To power

VR_ON31,39,51

FAN Control circuit

1 2

+3VS

1

2

H_THERMDA

H_THERMDC

CPU_THERM_STP#

CPU_THERM_STP#

CPU_THERM_STP#

EN_DFAN131

10K_0402_5%

10K_0402_5%

FAN_SPEED131

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

R62

R62

49.9_0402_1%

49.9_0402_1%

EN_DFAN1

+3VS

12

R65

R65

2

C22

C22

1

Thermal

H_PROCHOT# OCP#

Thermal Sensor EMC1402-1-ACZL-TR

U2

U2

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

EMC1402-1-ACZL-TR_MSOP8

Address:100_1100

S

S

G

G

SMCLK

SMDATA

ALERT#

D

D

13

Q53

Q53
SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D

2

C19

C19

10U_0805_10V4Z~D

10U_0805_10V4Z~D

12

C20

C20

1000P_0402_50V7K~D

1000P_0402_50V7K~D

12

8

7

6

5

GND

R1563

R1563

0_0402_5%

0_0402_5%

1 2

+FAN1_POWER

+1.05V_VCCP

12

R61

@R61

@

56_0402_5%

56_0402_5%

B

B

2

E

E

3 1

C

C

Q1

@

Q1

@

MMBT3904_SOT23-3~D

MMBT3904_SOT23-3~D

EC_SMB_CK2

EC_SMB_DA2

MAINPWON 39,47,52

+5VS

C21 10U_0805_10V4Z~DC21 10U_0805_10V4Z~D

U3

U3

1

VEN

2

VIN

3

VO

4

VSET

RT9027BPS_SO8

RT9027BPS_SO8

40mil

+FAN1_POWER

MOLEX_53261-0371~D

MOLEX_53261-0371~D

1 2

JFAN1

JFAN1

1
2

CONN@

CONN@

1
2
33G

GND
GND
GND
GND

G

OCP# 21

EC_SMB_CK2 27,28,31,39

EC_SMB_DA2 27,28,31,39

8
7
6
5

4
5

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPI ED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Penryn(1/3)-AGTL+/ITP-XDP

Penryn(1/3)-AGTL+/ITP-XDP

Penryn(1/3)-AGTL+/ITP-XDP

LA-5151P

LA-5151P

LA-5151P

7 60Friday, June 12, 2009

7 60Friday, June 12, 2009

7 60Friday, June 12, 2009

1

R10 (A00)

R10 (A00)

R10 (A00)

5

4

3

2

1

+CPU_CORE +CPU_CORE

CONN@

AD26

AF26

CONN@

JCPU1B

JCPU1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3
TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Penryn

Penryn

DATA GRP 1

DATA GRP 1

MISC

MISC

DATA GRP 0

DATA GRP 0

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#

DATA GRP 2DATA GRP 3

DATA GRP 2DATA GRP 3

D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#
DPWR#

PWRGOOD

SLP#
PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

H_D#[32..47] 10

H_DSTBN#2 10
H_DSTBP#2 10
H_DINV#2 10
H_D#[48..63] 10

H_DSTBN#3 10
H_DSTBP#3 10
H_DINV#3 10

H_DPRSTP# 11,19,51
H_DPSLP# 19

H_DPWR# 10

H_PWRGOOD 19
H_CPUSLP# 10

H_PSI# 51

R67

24.9_0402_1%

R67

24.9_0402_1%

R68

49.9_0402_1%

R68

49.9_0402_1%

R69

24.9_0402_1%

R69

R66

49.9_0402_1%

R66

49.9_0402_1%

12

12

24.9_0402_1%

12

12

H_D#[0..15]10

D D

H_DSTBN#010
H_DSTBP#010

H_DINV#010

H_D#[16..31]10

C C

H_DSTBN#110
H_DSTBP#110

H_DINV#110

CPU_BSEL06
CPU_BSEL16
CPU_BSEL26

+V_CPU_GTLREF

T3T3
T4T4
T5T5
T6T6
T7T7
T8T8

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

B B

Close to CPU pin AD26
within 500mils. Zo = 55 ohm

+V_CPU_GTLREF

+V_CPU_GTLREF

Cpu Quad Core, R=1.74K_0402_1%

Cpu Dual Core, R=2K_0402_1%

+1.05V_VCCP

12

R72

R72
1K_0402_1%

1K_0402_1%

12

R73

R73

1.74K_0402_1%

1.74K_0402_1%

FSB

533

667

800

1067 266 0 0 0

Qual core value

BCLK BSEL2 BSEL1 BSEL0

133

0 0 1

166

200

110

1 00

CONN@

CONN@

JCPU1C

JCPU1C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Penryn

Penryn

For 8 layer condition.
Length match within 25 mils.
The trace width/space/other
is 20/7/25. Zo = 27.4 ohm.

+CPU_CORE

R70 100_0402_1%R70 100_0402_1%

R71 100_0402_1%R71 100_0402_1%

AB20

VCC[068]

AB7

VCC[069]

AC7

VCC[070]

AC9

VCC[071]

AC12

VCC[072]

AC13

VCC[073]

AC15

VCC[074]

AC17

VCC[075]

AC18

VCC[076]

AD7

VCC[077]

AD9

VCC[078]

AD10

VCC[079]

AD12

VCC[080]

AD14

VCC[081]

AD15

VCC[082]

AD17

VCC[083]

AD18

VCC[084]

AE9

VCC[085]

AE10

VCC[086]

AE12

VCC[087]

AE13

VCC[088]

AE15

VCC[089]

AE17

VCC[090]

AE18

VCC[091]

AE20

VCC[092]

AF9

VCC[093]

AF10

VCC[094]

AF12

VCC[095]

AF14

VCC[096]

AF15

VCC[097]

AF17

VCC[098]

AF18

VCC[099]

AF20

VCC[100]

G21

VCCP[01]

V6

VCCP[02]

J6

VCCP[03]

K6

VCCP[04]

M6

VCCP[05]

J21

VCCP[06]

K21

VCCP[07]

M21

VCCP[08]

N21

VCCP[09]

N6

VCCP[10]

R21

VCCP[11]

R6

VCCP[12]

T21

VCCP[13]

T6

VCCP[14]

V21

VCCP[15]

W21

VCCP[16]

B26

VCCA[01]

C26

VCCA[02]

AD6

VID[0]

AF5

VID[1]

AE5

VID[2]

AF4

VID[3]

AE3

VID[4]

AF3

VID[5]

AE2

VID[6]

VCCSENSE

VSSSENSE

1 2

1 2

Close to CPU pin
within 500mils.

VCCSENSE

AF7

VSSSENSE

AE7

.

.

VCCSENSE

VSSSENSE

+1.05V_VCCP

CPU_VID0 51
CPU_VID1 51
CPU_VID2 51
CPU_VID3 51
CPU_VID4 51
CPU_VID5 51
CPU_VID6 51

VCCSENSE 51

VSSSENSE 51

1

+

+

C23

C23
220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

Near pin B26

+1.5VS

1

1

C25

C25

C24

C24

2

2

10U_0805_6.3V6M~D

10U_0805_6.3V6M~D

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPI ED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

Penryn(2/3)-AGTL+/ITP-XDP

Penryn(2/3)-AGTL+/ITP-XDP

LA-5151P

LA-5151P

LA-5151P

8 60Friday, June 12, 2009

8 60Friday, June 12, 2009

8 60Friday, June 12, 2009

1

R10 (A00)

R10 (A00)

R10 (A00)

5

High Frequence Decoupling

10uF 0805 X5R -> 85 degree.

4

3

2

1

D D

C C

B B

CONN@

CONN@

JCPU1D

JCPU1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Penryn

Penryn

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

.

+1.05V_VCCP

1

C62

C62

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

C58

C58

+

+

2

1

C63

C63

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

2

C26

C26
10U_0805_4VAM~D

10U_0805_4VAM~D

C36

C36
10U_0805_4VAM~D

10U_0805_4VAM~D

C46

C46
10U_0805_4VAM~D

10U_0805_4VAM~D

C52

C52
10U_0805_4VAM~D

10U_0805_4VAM~D

330U_D2E_2.5VM_R9~D

330U_D2E_2.5VM_R9~D

330U_D2E_2.5VM_R9~D

330U_D2E_2.5VM_R9~D

1

C59

C59

+

+

2

1

C64

C64

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

2

1

C27

C27
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C37

C37
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C47

C47
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C53

C53
10U_0805_4VAM~D

10U_0805_4VAM~D

2

330U_D2E_2.5VM_R9~D

330U_D2E_2.5VM_R9~D

1

C60

C60

+

+

2

1

2

1

2

1

2

1

2

330U_D2E_2.5VM_R9~D

330U_D2E_2.5VM_R9~D

1

C61

C61

+

+

2

1

C65

C65

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

2

C28

C28
10U_0805_4VAM~D

10U_0805_4VAM~D

C38

C38
10U_0805_4VAM~D

10U_0805_4VAM~D

C48

C48
10U_0805_4VAM~D

10U_0805_4VAM~D

C54

C54
10U_0805_4VAM~D

10U_0805_4VAM~D

1

2

1

C29

C29

10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C39

C39

10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C49

C49

10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C55

C55
10U_0805_4VAM~D

10U_0805_4VAM~D

2

C66

C66

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

1

C30

C30
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C40

C40
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C50

C50
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C56

C56
10U_0805_4VAM~D

10U_0805_4VAM~D

2

ESR <= 1.5m ohm

Capacitor > 880 uF

1

C67

C67

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

2

1

C31

C31
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C41

C41
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C51

C51
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C57

C57
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C32

C32
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C42

C42
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C33

C33
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C43

C43
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C34

C34
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C44

C44
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C35

C35
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C45

C45
10U_0805_4VAM~D

10U_0805_4VAM~D

2

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPI ED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Penryn(3/3)-AGTL+/ITP-XDP

Penryn(3/3)-AGTL+/ITP-XDP

Penryn(3/3)-AGTL+/ITP-XDP

LA-5151P

LA-5151P

LA-5151P

9 60Friday, June 12, 2009

9 60Friday, June 12, 2009

9 60Friday, June 12, 2009

1

R10 (A00)

R10 (A00)

R10 (A00)

5

4

3

2

1

U4A

H_D#[0..63]8

D D

C C

Layout Note :
H_RCOMP / H_VREF / H_SWNG
Trace width and spacing is 10 / 20

+1.05V_VCCP

12

R74

R74
221_0402_1%

221_0402_1%

H_SWNG

Near C5 pin

C68

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C68

R76 16.9_0402_1%R76 16.9_0402_1%

1 2

12

1

R75

R75
75_0402_1%

75_0402_1%

2

Qual core

H_RCOMP

Qual core

+1.05V_VCCP

12

R77

R77
1K_0402_1%

1K_0402_1%

+H_VREF

12

1

R78

R78

2K_0402_1%

C69

@C69

@

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

B B

2K_0402_1%

2

Within 100 mils from NB

H_RCOMP Dual core 24.9 ohm_1% pull down
Qual core 16.9 ohm_1% pull down
H_SWNG Dual core 100 ohm_1% pull down
Qual core 75 ohm_1% pull down

H_RESET#7

H_CPUSLP#8

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
H_RCOMP

H_RESET#
H_CPUSLP#

+H_VREF

U4A

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32

AD14

H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SWING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

H_ADSTB#_0
H_ADSTB#_1

H_DEFER#

HOST

HOST

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DBSY#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#
H_TRDY#

H_RS#_0
H_RS#_1
H_RS#_2

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

J8
L3
Y13
Y1

L10
M7
AA5
AE6

L9
M8
AA6
AE5

B15
K13
F13
B13
B14

B6
F12
C8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

H_A#[3..35] 7

H_ADS# 7
H_ADSTB#0 7
H_ADSTB#1 7
H_BNR# 7

H_BPRI# 7
H_BR0# 7
H_DEFER# 7

H_DBSY# 7
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6

H_DPWR# 8

H_DRDY# 7

H_HIT# 7

H_HITM# 7
H_LOCK# 7
H_TRDY# 7

H_DINV#0 8
H_DINV#1 8
H_DINV#2 8
H_DINV#3 8

H_DSTBN#0 8
H_DSTBN#1 8
H_DSTBN#2 8
H_DSTBN#3 8

H_DSTBP#0 8
H_DSTBP#1 8
H_DSTBP#2 8
H_DSTBP#3 8

H_REQ#0 7
H_REQ#1 7
H_REQ#2 7
H_REQ#3 7
H_REQ#4 7

H_RS#0 7
H_RS#1 7
H_RS#2 7

Poitier
Both DIS & UMA use Cantiga GM45

Note : The difference between GM45 & GM47 is
integrated graphic core freq @ Core voltage
GM45 : 533mHZ@1.05V
GM47 : 640mHZ@1.05V

P/N : SA00002JT3L (S IC AC82GM45 SLB94 B3 FCBGA1329 GM )

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATIO N OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cantiga(1 of 7)

Cantiga(1 of 7)

Cantiga(1 of 7)

LA-5151P

LA-5151P

LA-5151P

R10 (A00)

R10 (A00)

10 60Friday, June 12, 2009

10 60Friday, June 12, 2009

10 60Friday, June 12, 2009

1

R10 (A00)

5

CFG

R79 2.21K_0402_1%@R79 2.21K_0402_1%@

D D

R85 2.21K_0402_1%@R85 2.21K_0402_1%@

R80 2.21K_0402_1%@R80 2.21K_0402_1%@

R86 2.21K_0402_1%@R86 2.21K_0402_1%@

R81 2.21K_0402_1%@R81 2.21K_0402_1%@

1 2

1 2

1 2

1 2

1 2

CFG5

CFG6

CFG7

CFG9

CFG16

CFG[5:16] have internal pullup

+3VS

R87 4.02K_0402_1%@ R87 4.02K_0402_1%@

R88 4.02K_0402_1%@ R88 4.02K_0402_1%@

1 2

1 2

CFG19

CFG20

CFG[19:20] have internal pulldown

Strap Pin Table

CFG5

C C

B B

DMI X2 Select

iTPM Host

CFG6

Interface

Management

CFG7

Engine Crypto
Strap

PCI Express

CFG9

Graphic Lane

FSB Dynamic

CFG16

ODT

CFG19

DMI Lane
Reversal

Digital Display

CFG20

Port
Concurrent
Operation

SDVO_CRTL_DATA Low=No SDVO Device Present

DDPC_CTRLDATA

ICH_PWROK21,31

VGATE21,31,51

PLT_RST#20,27,30,31,38

A A

Low = DMI x 2

High = DMI x 4 (Default)

Low = iTPM enable

High = iTPM disable(Defult)

Low = TLS cipher suite with no confidentiality

High = TLS cipher suite with
confidentiality(Default)
Low = Reverse Lane

High = Normal Operation(Default)

Low=Dynamic ODT Disable

High=Dynamic ODT Enable(default)

Low=Normal (default)

High=Lane Reversed

Low=Only digital display port (SDVO/DP/iHDMI) or
PCIe is operational (default)
High = Digital display port (SDVO/DP/iHDMI) and
PCIe are operating simultaneously via the PEG
port

(default)
High=SDVO Device Present

Low=DisplayPort disabled (default)

High=DisplayPort device present

PM

R96 10K_0402_5%R96 10K_0402_5%

+3VS

R97 10K_0402_5%R97 10K_0402_5%

+3VS

R99 0_0402_5%@R99 0_0402_5%@

R100 0_0402_5%@R100 0_0402_5%@

R102 100_0402_5%R102 100_0402_5%

C957 0.1U_0402_16V4Z~D@C957 0.1U_0402_16V4Z~D@

12

12

12

12

12

1 2

Reserve for CPU, reference HPB

5

PM_EXTTS#0

PM_EXTTS#1

R10 Moidify (short directly)

PM_PWROK_R

PLT_RST#_NB

H_DPRSTP#

4

T10T10
T11T11
T12T12
T20T20
T21T21
T22T22
T23T23
T13T13
T24T24
T14T14
T25T25
T15T15
T26T26
T27T27

T28T28
T16T16
T17T17

T18T18

T29T29
T19T19
T30T30
T31T31

MCH_CLKSEL06
MCH_CLKSEL16
MCH_CLKSEL26

PM_SYNC#21

H_DPRSTP#8,19,51
PM_EXTTS#017
PM_EXTTS#118

H_THERMTRIP#7,19

DPRSLPVR21,51

4

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

T32T32
T33T33

T34T34

T35T35
T36T36
T37T37
T38T38
T39T39
T40T40

T41T41
T42T42

PM_SYNC#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK_R

PLT_RST#_NB

H_THERMTRIP#
DPRSLPVR

MCH_CFG3
MCH_CFG4

MCH_CFG8

MCH_CFG10

MCH_CFG12
MCH_CFG13

MCH_CFG15

MCH_CFG18

CFG5
CFG6
CFG7

CFG9

CFG16

CFG19
CFG20

U4B

U4B

M36

RSVD1

N36

RSVD2

R33

RSVD3

T33

RSVD4

AH9

RSVD5

AH10

RSVD6

AH12

RSVD7

AH13

RSVD8

K12

RSVD9

AL34

RSVD10

AK34

RSVD11

AN35

RSVD12

AM35

RSVD13

T24

RSVD14

B31

RSVD15

B2

RSVD16

M1

RSVD17

AY21

RSVD20

BG23

RSVD22

BF23

RSVD23

BH18

RSVD24

BF18

RSVD25

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC_1

BF48

NC_2

BD48

NC_3

BC48

NC_4

BH47

NC_5

BG47

NC_6

BE47

NC_7

BH46

NC_8

BF46

NC_9

BG45

NC_10

BH44

NC_11

BH43

NC_12

BH6

NC_13

BH5

NC_14

BG4

NC_15

BH3

NC_16

BF3

NC_17

BH2

NC_18

BG2

NC_19

BE2

NC_20

BG1

NC_21

BF1

NC_22

BD1

NC_23

BC1

NC_24

F1

NC_25

A47

NC_26

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

3

M_CLK_DDR0

AP24

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

SA_CS#_0
SA_CS#_1
SB_CS#_0

RSVD CFG PM NC

RSVD CFG PM NC

DDR CLK/ CONTROL/ COMPENSATIONHDA

DDR CLK/ CONTROL/ COMPENSATIONHDA

CLKDMIGRAPHICS VIDMEMISC

CLKDMIGRAPHICS VIDMEMISC

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPI ED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

SB_CS#_1

SA_ODT_0
SA_ODT_1

SB_ODT_O

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK

HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

AT21
AV24
AU20

AR24
AR21
AU24
AV20

BC28
AY28
AY36
BB36

BA17
AY16
AV16
AR13

BD17
AY17
BF15
AY13

BG22
BH21

BF28
BH28

AV42
AR36
BF17

DDR3_DRAMRST#

BC36

B38
A38
E41
F41

F43
E43

AE41
AE37
AE47
AH39

AE40
AE38
AE48
AH40

AE35
AE43
AE46
AH42

AD35
AE44
AF46
AH43

B33
B32
G33
F33
E33

C34

AH37
AH36
AN36
AJ35
AH34

N28
M28
G36
E36
K36
H36

B12

B28
B30
B29
C29
A28

M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT0_DIMMA
M_ODT1_DIMMA
M_ODT2_DIMMB
M_ODT3_DIMMB

SMRCOMP
SMRCOMP#

SMRCOMP_VOH
SMRCOMP_VOL

+V_DDR_MCH_REF
SM_PWROK

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4

GFX_VR_ON

CL_CLK0
CL_DATA0

M_PWROK
CL_RST#
+CL_VREF

SDVO_CTRLDATA
MCH_CLKREQ#
MCH_ICH_SYNC#

MCH_TSATN#

M_CLK_DDR#0 17
M_CLK_DDR#1 17
M_CLK_DDR#2 18
M_CLK_DDR#3 18

DDR_CKE0_DIMMA 17
DDR_CKE1_DIMMA 17
DDR_CKE2_DIMMB 18
DDR_CKE3_DIMMB 18

DDR_CS0_DIMMA# 17
DDR_CS1_DIMMA# 17
DDR_CS2_DIMMB# 18
DDR_CS3_DIMMB# 18

R90 499_0402_1%R90 499_0402_1%

1 2

DDR3_DRAMRST# 17,18

DMI_MRX_ITX_N0 22
DMI_MRX_ITX_N1 22
DMI_MRX_ITX_N2 22
DMI_MRX_ITX_N3 22

DMI_MRX_ITX_P0 22
DMI_MRX_ITX_P1 22
DMI_MRX_ITX_P2 22
DMI_MRX_ITX_P3 22

DMI_MTX_IRX_N0 22
DMI_MTX_IRX_N1 22
DMI_MTX_IRX_N2 22
DMI_MTX_IRX_N3 22

DMI_MTX_IRX_P0 22
DMI_MTX_IRX_P1 22
DMI_MTX_IRX_P2 22
DMI_MTX_IRX_P3 22

T43T43
T44T44
T45T45
T46T46
T47T47

T48T48

R101 56_0402_5%R101 56_0402_5%

2

M_CLK_DDR0 17
M_CLK_DDR1 17
M_CLK_DDR2 18
M_CLK_DDR3 18

M_ODT0_DIMMA 17
M_ODT1_DIMMA 17
M_ODT2_DIMMB 18
M_ODT3_DIMMB 18

CLK_MCH_DREFCLK 6
CLK_MCH_DREFCLK# 6
MCH_SSCDREFCLK 6
MCH_SSCDREFCLK# 6

CLK_MCH_3GPLL 6

CLK_MCH_3GPLL# 6

CL_CLK0 21

CL_DATA0 21

M_PWROK 21

CL_RST# 21

T49T49

MCH_CLKREQ# 6

MCH_ICH_SYNC# 21

1 2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

Compensation

SMRCOMP

+V_DDR_MCH_REF

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C72

C72

1

2

Use for DDR3 signls,
if support DDR2 need
connect to GND

R92

R92

12K_0402_1%

12K_0402_1%

SM_PWROK

1 2

12

R93

R93
10K_0402_5%

10K_0402_5%

+1.05V_VCCP

12

R95

R95
1K_0402_1%

1K_0402_1%

1

R98

R98

C76

C76

511_0402_1%

511_0402_1%

2

1 2

+1.05V_VCCP

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

R83 80.6_0402_1%R83 80.6_0402_1%

SMRCOMP#

R84 80.6_0402_1%R84 80.6_0402_1%

SMRCOMP_VOH

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C71

C71

SMRCOMP_VOL

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

C73

C73

4

O

1

C70

C70

2

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

1

C74

C74

2

2

+3VALW

C75 0.1U_0402_16V4Z~DC75 0.1U_0402_16V4Z~D

1 2

U5

U5

5

74AHC1G08GW_SOT353-5~D

74AHC1G08GW_SOT353-5~D

1

P

IN1

R94 0_0402_5%@R94 0_0402_5%@

2

IN2

G

3

R10 Moidify (short directly)

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Cantiga(2 of 7)

Cantiga(2 of 7)

Cantiga(2 of 7)

LA-5151P

LA-5151P

LA-5151P

12

12

DDR3

+1.5V

1

12

R82

R82
1K_0402_1%

1K_0402_1%

12

R89

R89

3.01K_0402_1%

3.01K_0402_1%

12

R91

R91

1K_0402_1%

1K_0402_1%

12

1

DDR3

+1.5V

1.5V_PGOOD 49

SLP_S4# 21,31

Follow MiniCooper

11 60Friday, June 12, 2009

11 60Friday, June 12, 2009

11 60Friday, June 12, 2009

R10 (A00)

R10 (A00)

R10 (A00)

5

D D

U4C

U4C

L32
G32
M32
M33

K33

J33
M29

C44

B43

E37

E38

C41
C40

B37

A37

H47

E46
G40

A40

H48
D45

F40

B40

A41
H38
G37

J37

B42
G38

F37

K37

F25
H25

K25

H24

C31

E32

E28

G28

J28

G29

H32

J32

J29

E29

L29

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL

LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3

TVA_DAC
TVB_DAC
TVC_DAC

TV_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE

CRT_GREEN

CRT_RED

CRT_IRTN

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF

CRT_VSYNC

T97T97

C C

R1000 75_0402_1%R1000 75_0402_1%

1 2

R1001 75_0402_1%R1001 75_0402_1%

1 2

R1002 75_0402_1%R1002 75_0402_1%

1 2

B B

TVA_DAC
TVB_DAC
TVC_DAC

4

LVDS TV VGA

LVDS TV VGA

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

T37
T36

PCIE_MRX_GTX_N0

H44

PCIE_MRX_GTX_N1

J46

PCIE_MRX_GTX_N2

L44

PCIE_MRX_GTX_N3

L40

PCIE_MRX_GTX_N4

N41

PCIE_MRX_GTX_N5

P48

PCIE_MRX_GTX_N6

N44

PCIE_MRX_GTX_N7

T43

PCIE_MRX_GTX_N8

U43

PCIE_MRX_GTX_N9

Y43

PCIE_MRX_GTX_N10

Y48

PCIE_MRX_GTX_N11

Y36

PCIE_MRX_GTX_N12

AA43

PCIE_MRX_GTX_N13

AD37

PCIE_MRX_GTX_N14

AC47

PCIE_MRX_GTX_N15

AD39

PCIE_MRX_GTX_P0

H43

PCIE_MRX_GTX_P1

J44

PCIE_MRX_GTX_P2

L43

PCIE_MRX_GTX_P3

L41

PCIE_MRX_GTX_P4

N40

PCIE_MRX_GTX_P5

P47

PCIE_MRX_GTX_P6

N43

PCIE_MRX_GTX_P7

T42

PCIE_MRX_GTX_P8

U42

PCIE_MRX_GTX_P9

Y42

PCIE_MRX_GTX_P10

W47

PCIE_MRX_GTX_P11

Y37

PCIE_MRX_GTX_P12

AA42

PCIE_MRX_GTX_P13

AD36

PCIE_MRX_GTX_P14

AC48

PCIE_MRX_GTX_P15

AD40

PCIE_MTX_GRX_N0

J41

PCIE_MTX_GRX_N1

M46

PCIE_MTX_GRX_N2

M47

PCIE_MTX_GRX_N3

M40

PCIE_MTX_GRX_N4

M42

PCIE_MTX_GRX_N5

R48

PCIE_MTX_GRX_N6

N38

PCIE_MTX_GRX_N7

T40

PCIE_MTX_GRX_N8

U37

PCIE_MTX_GRX_N9

U40

PCIE_MTX_GRX_N10

Y40

PCIE_MTX_GRX_N11

AA46

PCIE_MTX_GRX_N12

AA37

PCIE_MTX_GRX_N13

AA40

PCIE_MTX_GRX_N14

AD43

PCIE_MTX_GRX_N15

AC46

PCIE_MTX_GRX_P0

J42

PCIE_MTX_GRX_P1

L46

PCIE_MTX_GRX_P2

M48

PCIE_MTX_GRX_P3

M39

PCIE_MTX_GRX_P4

M43

PCIE_MTX_GRX_P5

R47

PCIE_MTX_GRX_P6

N37

PCIE_MTX_GRX_P7

T39

PCIE_MTX_GRX_P8

U36

PCIE_MTX_GRX_P9

U39

PCIE_MTX_GRX_P10

Y39

PCIE_MTX_GRX_P11

Y46

PCIE_MTX_GRX_P12

AA36

PCIE_MTX_GRX_P13

AA39

PCIE_MTX_GRX_P14

AD42

PCIE_MTX_GRX_P15

AD46

PEGCOMP

+VCC_PEG

1 2

3

Place the resistor within 500mils of the GMCH
PEGCOMP trace widht and spacing is 20/25 mils.

R108

R108

49.9_0402_1%

49.9_0402_1%

PCIE_MRX_GTX_N[0..15] 38

PCIE_MRX_GTX_P[0..15] 38

2

PCE-Express Graphics

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0 PCIE_MTX_C_GRX_N0

PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1

PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2

PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3

PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4

PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5

PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6

PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7

PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8

PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9

PCIE_MTX_GRX_P10
PCIE_MTX_GRX_N10

PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11

PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12

PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13

PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14

PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15

C77 0.1U_0402_10V7K~DC77 0.1U_0402_10V7K~D
C78 0.1U_0402_10V7K~DC78 0.1U_0402_10V7K~D

C79 0.1U_0402_10V7K~DC79 0.1U_0402_10V7K~D
C80 0.1U_0402_10V7K~DC80 0.1U_0402_10V7K~D

C81 0.1U_0402_10V7K~DC81 0.1U_0402_10V7K~D
C82 0.1U_0402_10V7K~DC82 0.1U_0402_10V7K~D

C83 0.1U_0402_10V7K~DC83 0.1U_0402_10V7K~D
C84 0.1U_0402_10V7K~DC84 0.1U_0402_10V7K~D

C85 0.1U_0402_10V7K~DC85 0.1U_0402_10V7K~D
C86 0.1U_0402_10V7K~DC86 0.1U_0402_10V7K~D

C87 0.1U_0402_10V7K~DC87 0.1U_0402_10V7K~D
C88 0.1U_0402_10V7K~DC88 0.1U_0402_10V7K~D

C89 0.1U_0402_10V7K~DC89 0.1U_0402_10V7K~D
C90 0.1U_0402_10V7K~DC90 0.1U_0402_10V7K~D

C91 0.1U_0402_10V7K~DC91 0.1U_0402_10V7K~D
C92 0.1U_0402_10V7K~DC92 0.1U_0402_10V7K~D

C93 0.1U_0402_10V7K~DC93 0.1U_0402_10V7K~D
C94 0.1U_0402_10V7K~DC94 0.1U_0402_10V7K~D

C95 0.1U_0402_10V7K~DC95 0.1U_0402_10V7K~D
C96 0.1U_0402_10V7K~DC96 0.1U_0402_10V7K~D

C97 0.1U_0402_10V7K~DC97 0.1U_0402_10V7K~D
C98 0.1U_0402_10V7K~DC98 0.1U_0402_10V7K~D

C99 0.1U_0402_10V7K~DC99 0.1U_0402_10V7K~D
C100 0.1U_0402_10V7K~DC100 0.1U_0402_10V7K~D

C101 0.1U_0402_10V7K~DC101 0.1U_0402_10V7K~D
C102 0.1U_0402_10V7K~DC102 0.1U_0402_10V7K~D

C103 0.1U_0402_10V7K~DC103 0.1U_0402_10V7K~D
C104 0.1U_0402_10V7K~DC104 0.1U_0402_10V7K~D

C105 0.1U_0402_10V7K~DC105 0.1U_0402_10V7K~D
C106 0.1U_0402_10V7K~DC106 0.1U_0402_10V7K~D

C107 0.1U_0402_10V7K~DC107 0.1U_0402_10V7K~D
C108 0.1U_0402_10V7K~DC108 0.1U_0402_10V7K~D

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

PCIE_MTX_C_GRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15] 38

PCIE_MTX_C_GRX_N[0..15] 38

PCIE_MTX_C_GRX_P0

PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1

PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3

PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4

PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5

PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6

PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7

PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8

PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9

PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10

PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11

PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12

PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13

PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14

PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

1

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPI ED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cantiga(4 of 7)

Cantiga(4 of 7)

Cantiga(4 of 7)

LA-5151P

LA-5151P

LA-5151P

R10 (A00)

R10 (A00)

12 60Friday, June 12, 2009

12 60Friday, June 12, 2009

12 60Friday, June 12, 2009

1

R10 (A00)

5

D D

4

3

2

1

DDR_A_D[0..63]17

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8

DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U4D

U4D

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_10

AT38

SA_DQ_11

AN41

SA_DQ_12

AN39

SA_DQ_13

AU44

SA_DQ_14

AU42

SA_DQ_15

AV39

SA_DQ_16

AY44

SA_DQ_17

BA40

SA_DQ_18

BD43

SA_DQ_19

AV41

SA_DQ_20

AY43

SA_DQ_21

BB41

SA_DQ_22

BC40

SA_DQ_23

AY37

SA_DQ_24

BD38

SA_DQ_25

AV37

SA_DQ_26

AT36

SA_DQ_27

AY38

SA_DQ_28

BB38

SA_DQ_29

AV36

SA_DQ_30

AW36

SA_DQ_31

BD13

SA_DQ_32

AU11

SA_DQ_33

BC11

SA_DQ_34

BA12

SA_DQ_35

AU13

SA_DQ_36

AV13

SA_DQ_37

BD12

SA_DQ_38

BC12

SA_DQ_39

BB9

SA_DQ_40

BA9

SA_DQ_41

AU10

SA_DQ_42

AV9

SA_DQ_43

BA11

SA_DQ_44

BD9

SA_DQ_45

AY8

SA_DQ_46

BA6

SA_DQ_47

AV5

SA_DQ_48

AV7

SA_DQ_49

AT9

SA_DQ_50

AN8

SA_DQ_51

AU5

SA_DQ_52

AU6

SA_DQ_53

AT5

SA_DQ_54

AN10

SA_DQ_55

AM11

SA_DQ_56

AM5

SA_DQ_57

AJ9

SA_DQ_58

AJ8

SA_DQ_59

AN12

SA_DQ_60

AM13

SA_DQ_61

AJ11

SA_DQ_62

AJ12

SA_DQ_63

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

DDR_A_BS0

BD21

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#

SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

BG18
AT25

BB20
BD20
AY20

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7

AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDR_A_BS1
DDR_A_BS2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8

DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_BS0 17
DDR_A_BS1 17
DDR_A_BS2 17

DDR_A_RAS# 17
DDR_A_CAS# 17

DDR_A_WE# 17

DDR_A_DM[0..7] 17

DDR_A_DQS[0..7] 17

DDR_A_DQS#[0..7] 17

DDR_A_MA[0..14] 17

DDR_B_D[0..63]18

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

U4E

U4E

AK47

SB_DQ_0

AH46

SB_DQ_1

AP47

SB_DQ_2

AP46

SB_DQ_3

AJ46

SB_DQ_4

AJ48

SB_DQ_5

AM48

SB_DQ_6

AP48

SB_DQ_7

AU47

SB_DQ_8

AU46

SB_DQ_9

BA48

SB_DQ_10

AY48

SB_DQ_11

AT47

SB_DQ_12

AR47

SB_DQ_13

BA47

SB_DQ_14

BC47

SB_DQ_15

BC46

SB_DQ_16

BC44

SB_DQ_17

BG43

SB_DQ_18

BF43

SB_DQ_19

BE45

SB_DQ_20

BC41

SB_DQ_21

BF40

SB_DQ_22

BF41

SB_DQ_23

BG38

SB_DQ_24

BF38

SB_DQ_25

BH35

SB_DQ_26

BG35

SB_DQ_27

BH40

SB_DQ_28

BG39

SB_DQ_29

BG34

SB_DQ_30

BH34

SB_DQ_31

BH14

SB_DQ_32

BG12

SB_DQ_33

BH11

SB_DQ_34

BG8

SB_DQ_35

BH12

SB_DQ_36

BF11

SB_DQ_37

BF8

SB_DQ_38

BG7

SB_DQ_39

BC5

SB_DQ_40

BC6

SB_DQ_41

AY3

SB_DQ_42

AY1

SB_DQ_43

BF6

SB_DQ_44

BF5

SB_DQ_45

BA1

SB_DQ_46

BD3

SB_DQ_47

AV2

SB_DQ_48

AU3

SB_DQ_49

AR3

SB_DQ_50

AN2

SB_DQ_51

AY2

SB_DQ_52

AV1

SB_DQ_53

AP3

SB_DQ_54

AR1

SB_DQ_55

AL1

SB_DQ_56

AL2

SB_DQ_57

AJ1

SB_DQ_58

AH1

SB_DQ_59

AM2

SB_DQ_60

AM3

SB_DQ_61

AH3

SB_DQ_62

AJ3

SB_DQ_63

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

DDR_B_BS0

BC16

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS#
SB_CAS#

SB_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

BB17
BB33

AU17
BG16
BF14

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6

AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_BS1
DDR_B_BS2

DDR_B_RAS#
DDR_B_CAS#

DDR_B_WE#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

DDR_B_BS0 18
DDR_B_BS1 18
DDR_B_BS2 18

DDR_B_RAS# 18
DDR_B_CAS# 18

DDR_B_WE# 18

DDR_B_DM[0..7] 18

DDR_B_DQS[0..7] 18

DDR_B_DQS#[0..7] 18

DDR_B_MA[0..14] 18

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPI ED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cantiga(3 of 7)

Cantiga(3 of 7)

Cantiga(3 of 7)

LA-5151P

LA-5151P

LA-5151P

R10 (A00)

R10 (A00)

13 60Friday, June 12, 2009

13 60Friday, June 12, 2009

13 60Friday, June 12, 2009

1

R10 (A00)

5

1

+

2

1U_0603_10V6K~D

1U_0603_10V6K~D

1

C121

C121

2

1067M 4140mA
800M 3162mA

C110

22U_0805_6.3V6M~D

C110

22U_0805_6.3V6M~D

C109

330U_D2E_2.5VM_R9~D+C109

330U_D2E_2.5VM_R9~D

1

1

2

2

J1

@J1

@

2

112

JUMP_43X118

JUMP_43X118

J2

@J2

@

2

112

JUMP_43X118

JUMP_43X118

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

1

@

@

C123

C123

2

2

C114

22U_0805_6.3V6M~D

C114

22U_0805_6.3V6M~D

10U_0805_10V4Z~D

10U_0805_10V4Z~D

C124

C124

C115

0.01U_0402_16V7K~D

C115

0.01U_0402_16V7K~D

2

1

+AXG_CORE

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

2

T53PAD T53PAD
T54PAD T54PAD

C125

C125

DDR3

+1.5V

D D

C C

B B

A A

+1.05V_VCCP +AXG_CORE

4

U4F

U4F

AP33

VCC_SM_1

AN33

VCC_SM_2

BH32

VCC_SM_3

BG32

VCC_SM_4

BF32

VCC_SM_5

BD32

VCC_SM_6

BC32

VCC_SM_7

BB32

VCC_SM_8

BA32

VCC_SM_9

AY32

VCC_SM_10

AW32

VCC_SM_11

AV32

VCC_SM_12

AU32

VCC_SM_13

AT32

VCC_SM_14

AR32

VCC_SM_15

AP32

VCC_SM_16

AN32

VCC_SM_17

BH31

VCC_SM_18

BG31

VCC_SM_19

BF31

VCC_SM_20

BG30

VCC_SM_21

BH29

VCC_SM_22

BG29

VCC_SM_23

BF29

VCC_SM_24

BD29

VCC_SM_25

BC29

VCC_SM_26

BB29

VCC_SM_27

BA29

VCC_SM_28

AY29

VCC_SM_29

AW29

VCC_SM_30

AV29

VCC_SM_31

AU29

VCC_SM_32

AT29

VCC_SM_33

AR29

VCC_SM_34

AP29

VCC_SM_35

BA36

VCC_SM_36/NC

BB24

VCC_SM_37/NC

BD16

VCC_SM_38/NC

BB21

VCC_SM_39/NC

AW16

VCC_SM_40/NC

AW13

VCC_SM_41/NC

AT13

VCC_SM_42/NC

Y26

VCC_AXG_1

AE25

VCC_AXG_2

AB25

VCC_AXG_3

AA25

VCC_AXG_4

AE24

VCC_AXG_5

AC24

VCC_AXG_6

AA24

VCC_AXG_7

Y24

VCC_AXG_8

AE23

VCC_AXG_9

AC23

VCC_AXG_10

AB23

VCC_AXG_11

AA23

VCC_AXG_12

AJ21

VCC_AXG_13

AG21

VCC_AXG_14

AE21

VCC_AXG_15

AC21

VCC_AXG_16

AA21

VCC_AXG_17

Y21

VCC_AXG_18

AH20

VCC_AXG_19

AF20

VCC_AXG_20

AE20

VCC_AXG_21

AC20

VCC_AXG_22

AB20

VCC_AXG_23

AA20

VCC_AXG_24

T17

VCC_AXG_25

T16

VCC_AXG_26

AM15

VCC_AXG_27

AL15

VCC_AXG_28

AE15

VCC_AXG_29

AJ15

VCC_AXG_30

AH15

VCC_AXG_31

AG15

VCC_AXG_32

AF15

VCC_AXG_33

AB15

VCC_AXG_34

AA15

VCC_AXG_35

Y15

VCC_AXG_36

V15

VCC_AXG_37

U15

VCC_AXG_38

AN14

VCC_AXG_39

AM14

VCC_AXG_40

U14

VCC_AXG_41

T14

VCC_AXG_42

AJ14

VCC_AXG_SENSE

AH14

VSS_AXG_SENSE

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

VCC_AXG_NTCF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC SM

VCC SM

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43

VCC GFX NCTF

VCC GFX NCTF

VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52

POWER

POWER

VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC GFX

VCC GFX

VCC SM LF

VCC SM LF

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

+AXG_CORE

Layout Note:

Place close to GMCH

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

@

@

C111

C111

2

Layout Note:
Inside GMCH

330U_D2_2.5VY_R15M~D

330U_D2_2.5VY_R15M~D

@

@

1

C1500

C1500

+

+

2

C126 0.1U_0402_16V4Z~DC126 0.1U_0402_16V4Z~D

C127 0.1U_0402_16V4Z~DC127 0.1U_0402_16V4Z~D

1

1

2

2

3

22U_0805_6.3V6M~D

0.47U_0402_10V4Z~D

0.47U_0402_10V4Z~D

1

@

@

C1502

C1502

2

330U_D2_2.5VY_R15M~D

330U_D2_2.5VY_R15M~D

1

+

+

2

C128 0.22U_0402_10V4Z~DC128 0.22U_0402_10V4Z~D

1

2

22U_0805_6.3V6M~D

1U_0603_10V6K~D

1U_0603_10V6K~D

1

1

C1503

C1503

@

@

@

@

C1506

C1506

2

2

@

@

C1501

C1501

C129 0.22U_0402_10V4Z~DC129 0.22U_0402_10V4Z~D

1

2

C132 1U_0402_6.3V4Z~DC132 1U_0402_6.3V4Z~D

C131 1U_0402_6.3V4Z~DC131 1U_0402_6.3V4Z~D

C130 0.47U_0402_10V4Z~DC130 0.47U_0402_10V4Z~D

1

1

1

2

2

2

C117

10U_0805_10V4Z~D

C117

10U_0805_10V4Z~D

C116

220U_D2_4VY_R15M~D+C116

220U_D2_4VY_R15M~D

1

+

2

1

1

2

2

2

Extnal Graphic: 3060mA

+1.05V_VCCP

AG34
AC34
AB34
AA34

Y34
V34

U34
AM33
AK33

AJ33
AG33
AF33

AE33
AC33
AA33

C120

0.1U_0402_16V4Z~D

C120

0.1U_0402_16V4Z~D

C118

0.22U_0402_10V4Z~D

C118

0.22U_0402_10V4Z~D

C119

0.22U_0402_10V4Z~D

C119

0.22U_0402_10V4Z~D

1

1

2

2

W33

AH28
AF28
AC28
AA28

AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24

AJ23
AH23
AF23

Y33

V33
U33

T32

integrated Graphic: 2898mA

U4G

U4G

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

VCC CORE

VCC CORE

POWER

POWER

VCC NCTF

VCC NCTF

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8

VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

1

+1.05V_VCCP

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPI ED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cantiga(6 of 7)

Cantiga(6 of 7)

Cantiga(6 of 7)

LA-5151P

LA-5151P

LA-5151P

R10 (A00)

R10 (A00)

14 60Friday, June 12, 2009

14 60Friday, June 12, 2009

14 60Friday, June 12, 2009

1

R10 (A00)

5

4

3

2

1

Place close to U4.F47

64.8mA Max.

220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

+

+

C1504

C1504

+1.05V_M_DPLLA

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C1505

C1505

2

2

+1.05V_VCCP

10UH_LB2012T100MR_20%_0805~D

10UH_LB2012T100MR_20%_0805~D

D D

L1500

L1500

1 2

+1.05V_VCCP

+1.05V_VCCP

R119

R119
0_0603_5%

0_0603_5%

1 2

L2

L2

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

1 2

Place close to U4.L48

64.8mA Max.

220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

+

+

C1520

C1520

+1.05V_M_DPLLB

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C1519

C1519

2

2

+1.05V_VCCP

10UH_LB2012T100MR_20%_0805~D

10UH_LB2012T100MR_20%_0805~D

C C

B B

A A

L1503

L1503

1 2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

+1.5VS

+1.05V_VCCP

100U_D2E_6.3VM_R18M~D

100U_D2E_6.3VM_R18M~D

1

+

+

C150

C150

2

+1.05V_VCCP

+1.5VS +1.5VS_QDAC

BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

1 2

+1.05V_VCCP

+1.05V_VCCP

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

1 2

C171

C171

10U_0805_10V4Z~D

10U_0805_10V4Z~D

12

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

C133

C133

C145

C145

R123

R123
0_0603_5%

0_0603_5%

L3

L3

R130

R130
0_0402_5%

0_0402_5%

12

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

L4

L4

R131

R131
1_0402_5%

1_0402_5%

12

+1.05V_M_HPLL

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

C134

C134

2

2

+1.05V_M_MPLL

R120

0_0603_5%

R120

0_0603_5%

1

1 2

2

1

2

R121

R121

0_0402_5%

0_0402_5%

12

R126

R126
0_0603_5%

0_0603_5%

12

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C166

C166

+1.05V_M_PEGPLL

C137

0.1U_0402_16V4Z~D

C137

0.1U_0402_16V4Z~D

12

+1.05V_A_SM

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

2

C160

C160

C161

0.01U_0402_25V7K~D

C161

0.01U_0402_25V7K~D

1

2

1

2

C172

0.1U_0402_16V4Z~D

C172

0.1U_0402_16V4Z~D

1

2

+1.05V_M_DPLLA

+1.05V_M_DPLLB

+VCCA_PEG_BG

1

C147

C147

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

C151

C151

C152

4.7U_0603_6.3V6M~D

C152

4.7U_0603_6.3V6M~D

1

2

+1.05V_A_SM_CK

C156

22U_0805_6.3V6M~D

C156

22U_0805_6.3V6M~D

1

2

C173

0.1U_0402_16V4Z~D

C173

0.1U_0402_16V4Z~D

1

2

+1.05V_M_PEGPLL

747mA

C153

1U_0603_10V4Z~D

C153

1U_0603_10V4Z~D

1

2

C157

0.1U_0402_16V4Z~D

C157

0.1U_0402_16V4Z~D

1

2

TVA_DAC 24.15mA
TVB_DAC 39.48mA
TVC_DAC 24.15mA

HDMI disable
connected to GND

35mA

1mA

157.2mA

50mA

60.31mA

64.8mA

64.8mA

24mA

139.2mA

13.2mA

414uA

50mA

37.95mA

50mA

U4H

U4H

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

AD48

VCCA_PEG_BG

AA48

VCCA_PEG_PLL

AR20

VCCA_SM_1

AP20

VCCA_SM_2

AN20

VCCA_SM_3

AR17

VCCA_SM_4

AP17

VCCA_SM_5

AN17

VCCA_SM_6

AT16

VCCA_SM_7

AR16

VCCA_SM_8

AP16

VCCA_SM_9

AP28

VCCA_SM_CK_1

AN28

VCCA_SM_CK_2

AP25

VCCA_SM_CK_3

AN25

VCCA_SM_CK_4

AN24

VCCA_SM_CK_5

AM28

VCCA_SM_CK_NCTF_1

AM26

VCCA_SM_CK_NCTF_2

AM25

VCCA_SM_CK_NCTF_3

AL25

VCCA_SM_CK_NCTF_4

AM24

VCCA_SM_CK_NCTF_5

AL24

VCCA_SM_CK_NCTF_6

AM23

VCCA_SM_CK_NCTF_7

AL23

VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

POWER

POWER

A SM

A SM

HDA

HDA

LVDS D TV/CRT

LVDS D TV/CRT

CRTPLLA LVDSA PEG

CRTPLLA LVDSA PEG

TV

TV

VTT

VTT

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

SM CK

VCC_TX_LVDS

A CK

A CK

HV

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

DMI PEG

DMI PEG

VTTLF

VTTLF

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

VCC_HV_1
VCC_HV_2
VCC_HV_3

VTTLF1
VTTLF2
VTTLF3

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

321.35mA

B22
B21
A21

149mA

BF21
BH20
BG20
BF20

118.8mA

K47

105.3mA

C35
B35
A35

1782mA

V48
U48
V47
U47
U46

456mA

AH48
AF48
AH47
AG47

GMCH_VTTLF1

A8

GMCH_VTTLF2

L1

GMCH_VTTLF3

AB2

+1.05V_VCCP

852mA

+VCC_AXF

+VCC_AXF

+1.5V_SM_CK

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

R129 0_0603_5%R129 0_0603_5%

1

C165

C165

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

1

2

1

2

C158

C158

1 2

C167

0.47U_0402_10V4Z~D

C167

0.47U_0402_10V4Z~D

C138

4.7U_0603_6.3V6M~D

C138

4.7U_0603_6.3V6M~D

1

2

0.47U_0402_10V4Z~D

0.47U_0402_10V4Z~D

1

2

C148

1U_0603_10V4Z~D

C148

1U_0603_10V4Z~D

1

2

+3VS

0.47U_0402_10V4Z~D

0.47U_0402_10V4Z~D

1

2

C142

C142

1 2

C149

C149
10U_0805_10V4Z~D@

10U_0805_10V4Z~D@

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

1

2

C168

C168

1

2

1

+

2

2.2U_0603_10V6K~D

2.2U_0603_10V6K~D

1

2

R122

R122
0_0603_5%

0_0603_5%

C154

C154

1 2

C169

0.47U_0402_10V4Z~D

C169

0.47U_0402_10V4Z~D

C139

220U_D2_4VY_R15M~D+C139

220U_D2_4VY_R15M~D

C143

C143

12

R125

R125
1_0402_5%

1_0402_5%

10U_0805_10V4Z~D

10U_0805_10V4Z~D

R127

@R127

@

10_0402_5%

10_0402_5%

+VCC_PEG+VCC_DMI

C144

4.7U_0603_6.3V6M~D

C144

4.7U_0603_6.3V6M~D

1

2

R124

R124
0_0805_5%

0_0805_5%

C155

C155

1 2

+VCC_PEG

+1.05V_VCCP

12

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

2

DDR3 connect to 1.5V

+1.5V

CRB schematic
HPB & Avia didn 't reserve

D1

@D1

@

1 2

SDMK0340L-7-F_SOD323-2~D

SDMK0340L-7-F_SOD323-2~D

C162

220U_D2_4VY_R15M~D+C162

220U_D2_4VY_R15M~D

C164

22U_0805_6.3V6M~D

C164

22U_0805_6.3V6M~D

C163

C163

1

1

+

2

2

+1.05V_VCCP

1 2

JP2@ J P2@

+1.05V_VCCP

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPI ED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cantiga(5 of 7)

Cantiga(5 of 7)

Cantiga(5 of 7)

LA-5151P

LA-5151P

LA-5151P

R10 (A00)

R10 (A00)

15 60Friday, June 12, 2009

15 60Friday, June 12, 2009

15 60Friday, June 12, 2009

1

R10 (A00)

5

D D

C C

B B

A A

4

U4I

U4I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

AD47

VSS_9

AB47

VSS_10

Y47

VSS_11

T47

VSS_12

N47

VSS_13

L47

VSS_14

G47

VSS_15

BD46

VSS_16

BA46

VSS_17

AY46

VSS_18

AV46

VSS_19

AR46

VSS_20

AM46

VSS_21

V46

VSS_22

R46

VSS_23

P46

VSS_24

H46

VSS_25

F46

VSS_26

BF44

VSS_27

AH44

VSS_28

AD44

VSS_29

AA44

VSS_30

Y44

VSS_31

U44

VSS_32

T44

VSS_33

M44

VSS_34

F44

VSS_35

BC43

VSS_36

AV43

VSS_37

AU43

VSS_38

AM43

VSS_39

J43

VSS_40

C43

VSS_41

BG42

VSS_42

AY42

VSS_43

AT42

VSS_44

AN42

VSS_45

AJ42

VSS_46

AE42

VSS_47

N42

VSS_48

L42

VSS_49

BD41

VSS_50

AU41

VSS_51

AM41

VSS_52

AH41

VSS_53

AD41

VSS_54

AA41

VSS_55

Y41

VSS_56

U41

VSS_57

T41

VSS_58

M41

VSS_59

G41

VSS_60

B41

VSS_61

BG40

VSS_62

BB40

VSS_63

AV40

VSS_64

AN40

VSS_65

H40

VSS_66

E40

VSS_67

AT39

VSS_68

AM39

VSS_69

AJ39

VSS_70

AE39

VSS_71

N39

VSS_72

L39

VSS_73

B39

VSS_74

BH38

VSS_75

BC38

VSS_76

BA38

VSS_77

AU38

VSS_78

AH38

VSS_79

AD38

VSS_80

AA38

VSS_81

Y38

VSS_82

U38

VSS_83

T38

VSS_84

J38

VSS_85

F38

VSS_86

C38

VSS_87

BF37

VSS_88

BB37

VSS_89

AW37

VSS_90

AT37

VSS_91

AN37

VSS_92

AJ37

VSS_93

H37

VSS_94

C37

VSS_95

BG36

VSS_96

BD36

VSS_97

AK15

VSS_98

AU36

VSS_99

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

VSS

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

3

U4J

U4J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

VSS_230

M17

VSS_231

H17

VSS_232

C17

VSS_233

BA16

VSS_235

AU16

VSS_237

AN16

VSS_238

N16

VSS_239

K16

VSS_240

G16

VSS_241

E16

VSS_242

BG15

VSS_243

AC15

VSS_244

W15

VSS_245

A15

VSS_246

BG14

VSS_247

AA14

VSS_248

C14

VSS_249

BG13

VSS_250

BC13

VSS_251

BA13

VSS_252

AN13

VSS_255

AJ13

VSS_256

AE13

VSS_257

N13

VSS_258

L13

VSS_259

G13

VSS_260

E13

VSS_261

BF12

VSS_262

AV12

VSS_263

AT12

VSS_264

AM12

VSS_265

AA12

VSS_266

J12

VSS_267

A12

VSS_268

BD11

VSS_269

BB11

VSS_270

AY11

VSS_271

AN11

VSS_272

AH11

VSS_273

Y11

VSS_275

N11

VSS_276

G11

VSS_277

C11

VSS_278

BG10

VSS_279

AV10

VSS_280

AT10

VSS_281

AJ10

VSS_282

AE10

VSS_283

AA10

VSS_284

M10

VSS_285

BF9

VSS_286

BC9

VSS_287

AN9

VSS_288

AM9

VSS_289

AD9

VSS_290

G9

VSS_291

B9

VSS_292

BH8

VSS_293

BB8

VSS_294

AV8

VSS_295

AT8

VSS_296

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

VSS

VSS

VSS NCTF

VSS NCTF

VSS SCB

VSS SCB

2

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

VSS_351
VSS_352
VSS_353
VSS_354

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5

NC

NC

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

U24
U28
U25
U29

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

1

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPI ED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cantiga(7 of 7)

Cantiga(7 of 7)

Cantiga(7 of 7)

LA-5151P

LA-5151P

LA-5151P

R10 (A00)

R10 (A00)

16 60Friday, June 12, 2009

16 60Friday, June 12, 2009

16 60Friday, June 12, 2009

1

R10 (A00)

5

4

3

2

1

+1.5V

12

R132

R132
1K_0402_1%

1K_0402_1%

D D

12

R133

R133
1K_0402_1%

1K_0402_1%

C C

B B

A A

+V_DDR_MCH_REF

+V_DDR_MCH_REF

+3VS

1

2

+V_DDR_MCH_REF

DDR_CKE0_DIMMA11

DDR_CS1_DIMMA#11

C193

0.1U_0402_16V4Z~D

C193

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

2

JDIMM1

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

2

DDR_A_BS213

M_CLK_DDR011
M_CLK_DDR#011

DDR_A_BS013

DDR_A_WE#13
DDR_A_CAS#13

C194

C194

+V_DDR_MCH_REF

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C175

C175

12

DDR_A_D0
DDR_A_D1

C174

C174

1

DDR_A_DM0

DDR_A_D2

2

DDR_A_D3

DDR_A_D8
DDR_A_D9 DDR_A_D13

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2

DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10

DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

T56T56

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7

DDR_A_D58
DDR_A_D59

R135

10K_0402_5%

R135

10K_0402_5%

R136

10K_0402_5%

R136

10K_0402_5%

+0.75VS +0.75VS

1 2

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4RN-7F

FOX_AS0A626-U4RN-7F

CONN@

CONN@

VSS3

DQS#0

DQS0

VSS6

VSS8
DQ12
DQ13

VSS10

DQ14
DQ15

DQ20
DQ21

DQ23

DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

DQ4
DQ5

DQ6
DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA
SCL

DDR3 SO-DIMM/Standard Type

5

4

+1.5V+1.5V

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D12

22
24
26

DDR_A_DM1

28

DDR3_DRAMRST#

30
32

DDR_A_D14

34

DDR_A_D15

36
38

DDR_A_D20

40

DDR_A_D21

42
44

DDR_A_DM2

46
48

DDR_A_D22

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D30

68

DDR_A_D31

70
72

DDR_CKE1_DIMMA

74
76
78

A15
A14

A11

A7

A6
A4

A2
A0

S0#

G2

DDR_A_MA14

80
82

DDR_A_MA11

84

DDR_A_MA7

86
88

DDR_A_MA6

90

DDR_A_MA4

92
94

DDR_A_MA2

96

DDR_A_MA0

98
100

M_CLK_DDR1

102

M_CLK_DDR#1

104
106

DDR_A_BS1

108

DDR_A_RAS#

110
112

DDR_CS0_DIMMA#

114

M_ODT0_DIMMA

116
118

M_ODT1_DIMMA

120
122
124

+V_DDR_MCH_REF

126
128

DDR_A_D36

130

DDR_A_D37

132
134

DDR_A_DM4

136
138

DDR_A_D38

140

DDR_A_D39

142
144

DDR_A_D44

146

DDR_A_D45

148
150

DDR_A_DQS#5

152

DDR_A_DQS5

154
156

DDR_A_D46

158

DDR_A_D47

160
162

DDR_A_D52

164

DDR_A_D53

166
168

DDR_A_DM6

170
172

DDR_A_D54

174

DDR_A_D55

176
178

DDR_A_D60

180

DDR_A_D61

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196

PM_EXTTS#0_R

198

ICH_SM_DA

200

ICH_SM_CLK

202
204

206

DDR3_DRAMRST# 11,18

DDR_CKE1_DIMMA 11

T55T55

M_CLK_DDR1 11
M_CLK_DDR#1 11

DDR_A_BS1 13
DDR_A_RAS# 13

DDR_CS0_DIMMA# 11
M_ODT0_DIMMA 11

M_ODT1_DIMMA 11

+V_DDR_MCH_REF

C188

2.2U_0603_6.3V6K~D

C188

2.2U_0603_6.3V6K~D

C187

0.1U_0402_16V4Z~D

C187

0.1U_0402_16V4Z~D

1

1

2

2

R10 Moidify (short directly)

@

@

R134 0_0402_5%

R134 0_0402_5%

1 2

ICH_SM_DA 6,18,20,21
ICH_SM_CLK 6,18,20,21

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPI ED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

PM_EXTTS#0 11

Note :
DDR3 command & contorl signals need n o termination.
DDR2 command & command signals 56 ohm pull up to VccSus0_9

DDR_A_D[0..63]13

DDR_A_DQS[0..7]13

DDR_A_DQS#[0..7]13

DDR_A_DM[0..7]13

DDR_A_MA[0..14]13

Place close to SO-DIMM

+1.5V

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

C179

10U_0603_6.3V6M~D

C179

10U_0603_6.3V6M~D

C180

C180

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C185

C185

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

1

C176

C176

C186

C186

+0.75VS

C189

C189

330U_D2_2.5VY_R15M~D

330U_D2_2.5VY_R15M~D

C177

10U_0603_6.3V6M~D

C177

10U_0603_6.3V6M~D

C178

10U_0603_6.3V6M~D

C178

1

+

+

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

C190

C190

2

1

10U_0603_6.3V6M~D

1

1

2

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C183

C183

C184

C184

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

C191

C191

C192

C192

2

2

1

1

Place close to JDIMM pin 203 and 204

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

C182

C182

C181

C181

1

1

2

2

+0.75VS

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

C216

C216

1

2

Place between 2 DIMMs

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DDRIII SO-DIMM A SLOT

DDRIII SO-DIMM A SLOT

DDRIII SO-DIMM A SLOT

LA-5151P

LA-5151P

LA-5151P

R10 (A00)

R10 (A00)

17 60Friday, June 12, 2009

17 60Friday, June 12, 2009

17 60Friday, June 12, 2009

1

R10 (A00)

5

4

3

2

1

VSS3

DQS0

VSS6

VSS8
DQ12
DQ13

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ23

DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

RAS#

ODT0

ODT1

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5

DQ46
DQ47

DQ52
DQ53

DM6

DQ54
DQ55

DQ60
DQ61

DQS7

DQ62
DQ63

VTT2

+1.5V+1.5V

2

DDR_B_D4

4

DQ4
DQ5

DQ6
DQ7

A15
A14

A7

A6
A4

A2
A0

CK1

BA1

S0#

NC2

SDA
SCL

G2

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12

DDR_B_DM1
DDR3_DRAMRST#

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2

DDR_B_D22
DDR_B_D23

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D30
DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_BS1
DDR_B_RAS#

DDR_CS2_DIMMB#
M_ODT2_DIMMB

M_ODT3_DIMMB

+V_DDR_MCH_REF

DDR_B_D36
DDR_B_D37

DDR_B_DM4

DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

DDR_B_DM6

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

PM_EXTTS#1_R
ICH_SM_DA
ICH_SM_CLK

+0.75VS

DDR3_DRAMRST# 11,17

DDR_CKE3_DIMMB 11

T57T57

M_CLK_DDR3 11
M_CLK_DDR#3 11

DDR_B_BS1 13
DDR_B_RAS# 13

DDR_CS2_DIMMB# 11
M_ODT2_DIMMB 11

M_ODT3_DIMMB 11

+V_DDR_MCH_REF

C209

2.2U_0603_6.3V6K~D

C209

2.2U_0603_6.3V6K~D

C208

0.1U_0402_16V4Z~D

C208

0.1U_0402_16V4Z~D

1

1

2

2

R10 Moidify (short directly)

@

@

R137 0_0402_5%

R137 0_0402_5%

1 2

ICH_SM_DA 6,17,20,21
ICH_SM_CLK 6,17,20,21

PM_EXTTS#1 11

DDR_B_D[0..63]13

DDR_B_DQS[0..7]13

DDR_B_DQS#[0..7]13

DDR_B_DM[0..7]13

DDR_B_MA[0..14]13

Place close to SO-DIMM

+1.5V

C198

10U_0603_6.3V6M~D

C198

10U_0603_6.3V6M~D

C199

10U_0603_6.3V6M~D

C199

10U_0603_6.3V6M~D

C197

330U_D2_2.5VY_R15M~D+C197

+0.75VS

330U_D2_2.5VY_R15M~D

1

1

+

2

2

C204

0.1U_0402_16V4Z~D

C204

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

2

2

C211

1U_0402_6.3V6K~D

C211

1U_0402_6.3V6K~D

C212

1U_0402_6.3V6K~D

C212

1U_0402_6.3V6K~D

C210

1U_0402_6.3V6K~D

C210

1U_0402_6.3V6K~D

2

2

1

2

1

1

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

1

2

2

C205

C205

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C206

0.1U_0402_16V4Z~D

C206

0.1U_0402_16V4Z~D

1

1

2

2

C213

1U_0402_6.3V6K~D

C213

1U_0402_6.3V6K~D

2

1

Place close to JDIMM pin 203 and 204

C201

10U_0603_6.3V6M~D

C201

10U_0603_6.3V6M~D

C202

10U_0603_6.3V6M~D

C202

10U_0603_6.3V6M~D

C203

10U_0603_6.3V6M~D

C203

C200

C200

1

2

C207

C207

10U_0603_6.3V6M~D

1

1

2

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPI ED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIII SO-DIMM B SLOT

DDRIII SO-DIMM B SLOT

DDRIII SO-DIMM B SLOT

LA-5151P

LA-5151P

LA-5151P

R10 (A00)

R10 (A00)

18 60Friday, June 12, 2009

18 60Friday, June 12, 2009

18 60Friday, June 12, 2009

1

R10 (A00)

+V_DDR_MCH_REF

1

R138

R138

1 2

10K_0402_5%

10K_0402_5%

2

D D

C C

B B

A A

+3VS

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

DDR_CKE2_DIMMB11

DDR_CS3_DIMMB#11

+3VS

C195

C195

DDR_B_BS213

M_CLK_DDR211
M_CLK_DDR#211

DDR_B_BS013

DDR_B_WE#13
DDR_B_CAS#13

1

2

C196

0.1U_0402_16V4Z~D

C196

0.1U_0402_16V4Z~D

1

2

C214

0.1U_0402_16V4Z~D

C214

0.1U_0402_16V4Z~D

+V_DDR_MCH_REF

DDR_B_D0
DDR_B_D1

DDR_B_DM0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9 DDR_B_D13

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2

DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

T58T58

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM7

DDR_B_D58
DDR_B_D59

+0.75VS

C215

2.2U_0603_6.3V6K~D

C215

2.2U_0603_6.3V6K~D

12

1

R139

R139
10K_0402_5%

10K_0402_5%

2

LINK OK

JDIMM2

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9
VSS925VSS10

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U8RN-7F

FOX_AS0A626-U8RN-7F

CONN@

CONN@

VDD12

VDD14

VDD16

VDD18

VREF_CA

VSS28

VSS30

VSS31

VSS33

VSS35
DQS#5

VSS38

VSS40

VSS42

VSS43

VSS45

VSS47
DQS#7

VSS50

VSS52

EVENT#

DDR3 SO-DIMM/Standard Type

5

4

5

4

3

2

1

12

ICH_RTCRST#
SRTCRST#
INTRUDER#

1 2

R157

R157
332K_0402_1%

332K_0402_1%

HDA_SDIN025

ICH_RTCX1

R140

R140
10M_0402_5%

10M_0402_5%

ICH_RTCX2

ICH_INTVRMEN

R149

R149

24.9_0402_1%

24.9_0402_1%

1 2

SATA_ACT#_R

SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

SATA_ITX_DRX_N1
SATA_ITX_DRX_P1

HDA_BITCLK_ICH
HDA_SYNC_ICH

HDA_RST_ICH#

HDA_SDIN0

HDA_SDOUT_ICH

U6A

U6A

C23

RTCX1

C24

RTCX2

A25

RTCRST#

F20

SRTCRST#

C22

INTRUDER#

B22

INTVRMEN

A22

LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14

LAN_RXD0

G13

LAN_RXD1

D14

LAN_RXD2

D13

LAN_TXD0

D12

LAN_TXD1

E13

LAN_TXD2

B10

GPIO56

B28

GLAN_COMPI

B27

GLAN_COMPO

AF6

HDA_BIT_CLK

AH4

HDA_SYNC

AE7

HDA_RST#

AF4

HDA_SDIN0

AG4

HDA_SDIN1

AH3

HDA_SDIN2

AE5

HDA_SDIN3

AG5

HDA_SDOUT

AG7

HDA_DOCK_EN#/GP IO33

AE8

HDA_DOCK_RST#/G PIO34

AG8

SATALED#

AJ16

SATA0RXN

AH16

SATA0RXP

AF17

SATA0TXN

AG17

SATA0TXP

AH13

SATA1RXN

AJ13

SATA1RXP

AG14

SATA1TXN

AF14

SATA1TXP

ICH9M_FCBGA676~D

ICH9M_FCBGA676~D

RTCLAN / GLANIHDASATA

LPCCPU

RTCLAN / GLANIHDASATA

LPCCPU

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO2 3

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

INIT#
INTR

RCIN#

SMI#

STPCLK#

THRMTRIP#

TP12

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#

SATARBIAS

LPC_AD0

K5

LPC_AD1

K4

LPC_AD2

L6

LPC_AD3

K2

LPC_FRAME#

K3

J3
J1

GATEA20

N7

H_A20M#

AJ27

H_DPRSTP#

AJ25

H_DPSLP#

AE23

R148

R148

AJ26

AD22

AF25

AE22
AG25
L3

AF23

NMI

AF24

AH27

AG26

AG27

AH11
AJ11
AG12
AF12

AH9
AJ9
AE10
AF10

AH18
AJ18

AJ7
AH7

12

56_0402_5%

56_0402_5%

H_PWRGOOD

H_IGNNE#

H_INIT#
H_INTR
KB_RST#

H_NMI
H_SMI#

H_STPCLK#

THERMTRIP_ICH#

ICH_TP12

SATA_ITX_DRX_N4
SATA_ITX_DRX_P4

SATA_ITX_DRX_N5
SATA_ITX_DRX_P5

CLK_PCIE_SATA#
CLK_PCIE_SATA

R156 24.9_0402_1%R156 24.9_0402_1%

LPC_AD[0..3] 27,31

LPC_FRAME# 2 7,31

T59T59
T60T60

GATEA20 31
H_A20M# 7

H_DPRSTP# 8,11 ,51
H_DPSLP# 8

H_FERR# 7

H_PWRGOOD 8

H_IGNNE# 7

H_INIT# 7
H_INTR 7
KB_RST# 31

H_NMI 7
H_SMI# 7

H_STPCLK# 7

R154 54.9_0402_1%R154 54.9_0402_ 1%

1 2

T61T61

C220 0.01U_ 0402_16V7K~DC220 0.01U_ 0402_16V7K~D
C221 0.01U_ 0402_16V7K~DC221 0.01U_ 0402_16V7K~D

C222 0.01U_ 0402_16V7K~DC222 0.01U_ 0402_16V7K~D
C223 0.01U_ 0402_16V7K~DC223 0.01U_ 0402_16V7K~D

CLK_PCIE_SATA# 6
CLK_PCIE_SATA 6

12

placed within 2" from
ICH9M

12
12

12
12

GATEA20

R142 10K_04 02_5%R142 10K_0402_5%

KB_RST#

R145 10K_04 02_5%R145 10K_0402_5%

H_FERR#

R147 49.9_0402_ 1%R147 49.9_0402_1%

dual core 56_5%
quad core 50_5%

+1.05V_VCCP

12

R151

R151

49.9_0402_1%

49.9_0402_1%

SATA_IRX_DTX_N4 29

SATA_IRX_DTX_P4 29
SATA_ITX_C_DRX_N4 29
SATA_ITX_C_DRX_P4 2 9

SATA_IRX_DTX_N5 29

SATA_IRX_DTX_P5 29
SATA_ITX_C_DRX_N5 29
SATA_ITX_C_DRX_P5 2 9

dual core 56_5%
quad core 50_5%

H_THERMTRIP# 7,11

+3VS

12

12

+1.05V_VCCP

12

To ESATA

To ODD

Within 500 mils

C864 15P _0402_50V8J~DC864 15P_0402_50V 8J~D

12

Y2

Y2

D D

Shunt

Open

Shunt

Open

C C

CMOS settingCMOS_CLR1

Clear CMOS

Keep CMOS

R143 20K_0402_5%R143 20K_0402_5%

+RTCVCC

1 2

R144 20K _0402_5%R144 20K_04 02_5%

1 2

R146 1M _0402_5%R1 46 1M_0402_5%

1 2

TPM settingME_CLR1

Clear ME RTC Registers

Keep ME RTC Registers

32.768KHZ_12.5PF_1TJS125BJ4A 421P

32.768KHZ_12.5PF_1TJS125BJ4A 421P

C217 15P_0402_50V8J~DC217 15P_0402_50V8J~D

@

ME1@ME1

HDA_BITCLK_AUDIO25
HDA_SYNC_AUDIO25

HDA_RST_AUDIO#25

2

3

12

C218

1U_0603_10V4Z~D

C218

1U_0603_10V4Z~D

2

12

1

Place close U6

HDA_SDOUT_AUDIO25

To JSATA1

B B

To JSATA2

SATA_IRX_DTX_N029
SATA_IRX_DTX_P029
SATA_ITX_C_DRX_N029
SATA_ITX_C_DRX_P029

SATA_IRX_DTX_N129
SATA_IRX_DTX_P129
SATA_ITX_C_DRX_N129
SATA_ITX_C_DRX_P129

1

IN

NC

4

OUT

NC

12

CMOS1@CMOS1@

1

@C1512

@

2

C224 0.01U_ 0402_16V7K~DC224 0.01U_ 0402_16V7K~D
C225 0.01U_ 0402_16V7K~DC225 0.01U_ 0402_16V7K~D

C226 0.01U_ 0402_16V7K~DC226 0.01U_ 0402_16V7K~D
C227 0.01U_ 0402_16V7K~DC227 0.01U_ 0402_16V7K~D

R141

R141
0_0402_5%

0_0402_5%

1 2

+RTCVCC

2

C219

C219
1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

+1.5VS

R150 33_040 2_5%R150 33_0402_5%

1 2

R152 33_040 2_5%R152 33_0402_5%

1 2

R153 33_0402_5%R 153 33_0402_5%

1 2

C1512
10P_0402_50V8J~D

10P_0402_50V8J~D

R155 33_040 2_5%R155 33_0402_5%

1 2

T62 PAD~DT62 PAD~D
T63 PAD~DT63 PAD~D

T84 PAD~DT84 PAD~D

12
12

12
12

P/N : SA00002G12L (S IC AF82801IEM SLB8P A3 PBGA676P ICH9ME )

+3VS

XOR Chain Entrance Strap

DescriptionICH TP3 HDA SDOUT

0 0

0

1

A A

1 1

1

0

RSVD

Enter XOR Chain

Normal Operation (Default)

Set PCIE port config bit 1

12

R158

@R158

@

1K_0402_5%

1K_0402_5%

HDA_SDOUT_ICH

12

R160

@R160

@

1K_0402_5%

1K_0402_5%

ICH_TP3 21

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATIO N OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

ICH9-M(1/5)

ICH9-M(1/5)

ICH9-M(1/5)

LA-5151P

LA-5151P

LA-5151P

R10 (A00)

R10 (A00)

19 60Friday, June 12, 2009

19 60Friday, June 12, 2009

19 60Friday, June 12, 2009

1

R10 (A00)