Dell Inspiron 15 Gaming 7567 Schematic

A

B

C

D

E

MODEL NAME : PCB NO :

BOM P/N :

1

2

3

BBV00/ BBV10

LA-D993P

Dell/Compal Confidential

Schematic Document

KABYLAKE-H

2016-11-01

Rev: 1.0 (A00)

@ : Nopop Component

CONN@ : Connector Component

R1@ / R3@ : R1/R3 CPN for CPU, GPU, PCB

EMC@ : Pop of EMI parts

S4G@ : Samsung GDDR5 4G for GPU

M4G@ : Micron GDDR5 4G for GPU

H4G@ : Hynix GDDR5 4G for GPU

BreakDown@ : For measure power consumption

14G0@ : 14" N17P-G0 15G1@ : 15" N17P-G1

1

2

3

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONIC S, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONIC S, INC.

C

2011/08/25 2011/08/25

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cover Page

E

of

1 70Tuesday, November 08, 2016

of

1 70Tuesday, November 08, 2016

of

1 70Tuesday, November 08, 2016

0.1(X00)

4

A

B

C

D

E

128M*32 x4 =2G

GPU

1

HDMI 2.0 Conn.

Retimer PS8409A

IFP

P35P.36

N17PG0/ N17P-G1 40W/ 50W

256M*32 x4 =4G

VRAM * 4 GDDR5

GB4-128

P.28~30

P.23~27

PEG 3.0 x16

Intel

KBL-Lake-H

Memory Bus (DDR4)

Dual Channel

DDRIV-DIMM X2

1.2V DDR4 2400 MHz

P.14~15

32GB Max

1

Processor

45W

14.0'' / 15.6'' HD / FHD / UHD

RJ45

P.47

2

Digital Camera Conn.

P.34

USB2.0

M.2 Slot A Key-E

(WLAN+BT4.0)

Port 12

LOM RTL8111H

P.43

USB2.0

P.47

Port 4

SPI Flash (BIOS 16MB)

Subwoofer

3

Subwoofer AMP ALC1302

Main SPKR *2

P.39

P.38

P.17

HDA Codec ALC3246

P.34

Port 5

Port 6

P.37

eDP 1.2 *4 lane

PCI-E x1

SPI

HD Audio

Universal Audio Jack

P.38

Touch Pad

P.41

I2C

PS2

BGA

P.7~13

DMI x4

100MHz 5GB/s

Intel

KBL-H-PCH BGA 837 Balls

P16~22

LPC Bus

33MHz

SATA3.0

PCI-E x4

USB2.0

USB 3.0

USB2.0

USB 3.0

USB2.0

Port 9~12

Port 1

Port 2

USB Powershare TPS2544

USB2.0

Port 3

Port 7

Port 1

Port 0

M.2 Slot C Key-M

(SATA/PCIe SSD)

Port 2

P.45

Port 3

USB 3.0 Re-driver SN65LVPE50

Card Reader 2 in 1 RTS5176E SD / MS

P.44

HDD Conn.

P.44

USB 3.0 Conn.

( USB Charger )

USB 3.0 Conn.

LED Board

USB2.0

P.46

IO Board

Touch Panel Conn.

P.35

Port 9

2

3

SMSC 1404

SIO

4

A

B

Charger & Battery

P.55

KB Conn.

P.40

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

P.48

Compal Secret Data

2011/08/25 2011/08/25

Compal Secret Data

LED Hall Sensor

Power Button

Deciphered Date

D

Power Button Board

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Block diagram

E

of

2 70Tuesday, November 08, 2016

of

2 70Tuesday, November 08, 2016

of

2 70Tuesday, November 08, 2016

0.1(X00)

4

A

Compal Confidential

Project Code : File Name :

B

C

D

E

1

M/B

2

IO Board LED Board PWB Board

2

3

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DB block diagram

E

of

3 70Tuesday, November 08, 2016

of

3 70Tuesday, November 08, 2016

of

3 70Tuesday, November 08, 2016

0.1(X00)

3

4

A

1

Board ID X00 X01 X02 X03 X04 A00

PCI EXPRESS

Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7 Lane 8 None Lane 9 Lane 10 Lane 11 Lane 12 Lane 13 Lane 14 Lane 15 Lane 16

Resistor

N/A

22.1K

DESTINATION NGFF-1 WLAN + BT CARD READER None None None None None

SSD

SSD SSD None None

Alpine Ridge

USB31DESTINATION

USB Conn 1 (Right Side) 2 3 4 5 6

USB Conn 2 (Left Side)

None

DESTINATIONUSB3 7 8 9 10

SATA

0A 1A N/A N/A 0B

None

DESTINATION

SSD

N/ASSD

N/A

None

HDD1B

2 3

None

USB 2.0 DESTINATION

1 2 3 4 5 6 7 8 9 10 11 12

USB Conn 1 (Right Side) USB Conn 2 (Left Side) None None NGFF-1 WLAN + BT None None None None Touch screen None None CAMERA

DESTINATIONCLKOUT_PCIE 0 1 2 3 4

None

NGFF-1 WLAN

CARD READER

Thunderbolt5 6 7 8 9

NGFF-2 SSD

GPU

None

DDI

1 2 3

LPC

LPC1

CLKOUT_PCIE

10 11 12 13 14 15

DESTINATION Alpine Ridge Alpine Ridge

DESTINATION MEC5085LPC0 DEBUG PORT

DESTINATION None None None None None None

1

Symbol Note :

: means Digital Ground : means Analog Ground

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-D991P

of

4 70Tuesday, November 08, 2016

of

4 70Tuesday, November 08, 2016

of

4 70Tuesday, November 08, 2016

0.1(X00)

5

4

3

2

1

SMBUS Address [0x9a]

AW44 BB43

D

PCH

AW42 AW45

SMBCLK SMBDATA

SML1_SMBCLK SML1_SMBDAT

1K

+3V_PCH

+3VS

DMN65D8L

+3V_PCH

DMN65D8L

+3V_PCH

DMN65D8L

1K

DMN65D8L

4.7K

AR41

AR44

I2C1_SCK_TP I2C1_SDA_TP

4.7K

AW42AW45

SML0_SMBCLK

C

SML0_SMBDATA

499

+3V_PCH

+3VS

DMN65D8L DMN65D8L

1K

2.4K

+3VS

+3VALW

+3VS_TP

DIMMA

D

DIMMB

Thermal

GPU

TP

C

4.7K

A5 B6

9 8

PBAT_CHG_SMBCLK PBAT_CHG_SMBDAT

4.7K

2.2K

+3VALW_EC

100 ohm

BATT

0x16

0 ohm

Charger

MEC1404

B

12 11

GPU_THM_SMBCLK GPU_THM_SMBDAT

2.2K

+3VALW_EC

DGPU_PEX_RST#

DMN66D0

DMN66D0 DMN66D0

2.2K

5.1K

+3.3V_GFX_AON

GPU

Thermal

B

0x9E

2.2K

4

+3VALW_EC

0 ohm

MCP23017

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

0x42

Compal Secret Data

2011/08/25 2012/07/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

SMBus Block Diagram

Size Document Number Rev

C

Date: Sheet

1

of

5 70Tuesday, November 08, 2016

of

5 70Tuesday, November 08, 2016

of

5 70Tuesday, November 08, 2016

0.1(X00)

A

5

B4 A3

MCP23017_SMBCLK MCP23017_SMBDAT

2.2K

5

4

3

2

1

D

C

+VCCST

+VCCSTG

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TDI

RH97

RH98

RH100

RH497

RH496

RH56

RH95

RH61

RH60

1

@

1

@

1

@

1

@

1

@

RH115 0_0402_5%@

RH492 0_0402_5%@

RH118 0_0402_5%@

2

51_0402_5%

2

51_0402_5%

2

51_0402_5%

2

51_0402_5%

2

51_0402_5%

2

51_0402_5%

2

51_0402_5%

2

51_0402_5%

2

51_0402_5%

1

PCH_JTAG_TDO

PCH_JTAG_TMS PCH_JTAG_TDI

CPU_XDP_TDO CPU_XDP_TMS

CPU_XDP_TDI

PCH_JTAG_TCK

CPU_XDP_TCK

CPU_XDP_TRST#

2

PCH_JTAG_TDO [18]

PCH_JTAG_TMS [18]

PCH_JTAG_TDI [18]

PCH_JTAG_TCK [18]

CPU_XDP_TCK [9,18]

CPU_XDP_TRST# [9,22]

CPU_XDP_TDO [9]

CPU_XDP_TMS [9]

CPU_XDP_TDI [9]

D

C

Pilot_05

B

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

XDP CONN

1

of

6 70Tuesday, November 08, 2016

of

6 70Tuesday, November 08, 2016

of

6 70Tuesday, November 08, 2016

0.1(X00)

B

A

5

PEG_HTX_C_GRX_P[0..15][23] PEG_HTX_C_GRX_N[0..15][23]

PEG_GTX_C_HRX_P[0..15][23]

PEG_GTX_C_HRX_N[0..15][23]

D

C

PEG_HTX_C_GRX_P[0..15]

PEG_HTX_C_GRX_N[0..15]

PEG_GTX_C_HRX_P[0..15] PEG_GTX_C_HRX_N[0..15]

+VCCIO

RH24

1

24.9_0402_1%

DMI_CRX_PTX_P0[19]

DMI_CRX_PTX_N0[19] DMI_CRX_PTX_P1[19]

DMI_CRX_PTX_N1[19]

DMI_CRX_PTX_P2[19] DMI_CRX_PTX_N2[19]

DMI_CRX_PTX_P3[19]

DMI_CRX_PTX_N3[19]

PEG_GTX_C_HRX_P15

PEG_GTX_C_HRX_N15

PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_N14

PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_N13

PEG_GTX_C_HRX_P12

PEG_GTX_C_HRX_N12

PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_N11

PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_N10

PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_N9

PEG_GTX_C_HRX_P8

PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_P7

PEG_GTX_C_HRX_N7

PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_N6

PEG_GTX_C_HRX_P5

PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_P4

PEG_GTX_C_HRX_N4

PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_N3

PEG_GTX_C_HRX_P2

PEG_GTX_C_HRX_N2

PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_N1

PEG_GTX_C_HRX_P0 PEG_GTX_C_HRX_N0

2

4

PEG_RCOMP

E25

D25

E24

F24 E23

D23

E22

F22

E21

D21 E20

F20

E19

D19

E18 F18

D17

E17

F16

E16

D15 E15

F14

E14 D13

E13

F12

E12

D11

E11

F10

E10

G2

D8

E8

E6 F6

D5

E5

J8

J9

UH1C

PEG_RXP[0]

PEG_RXN[0]

PEG_RXP[1]

PEG_RXN[1] PEG_RXP[2]

PEG_RXN[2]

PEG_RXP[3]

PEG_RXN[3]

PEG_RXP[4]

PEG_RXN[4] PEG_RXP[5]

PEG_RXN[5]

PEG_RXP[6]

PEG_RXN[6]

PEG_RXP[7] PEG_RXN[7]

PEG_RXP[8]

PEG_RXN[8]

PEG_RXP[9]

PEG_RXN[9]

PEG_RXP[10] PEG_RXN[10]

PEG_RXP[11]

PEG_RXN[11] PEG_RXP[12]

PEG_RXN[12]

PEG_RXP[13]

PEG_RXN[13]

PEG_RXP[14]

PEG_RXN[14]

PEG_RXP[15]

PEG_RXN[15]

PEG_RCOMP

DMI_RXP[0]

DMI_RXN[0]

DMI_RXP[1] DMI_RXN[1]

DMI_RXP[2] DMI_RXN[2]

DMI_RXP[3]

DMI_RXN[3]

SKL-H_BGA1440

@

REV = 1

SKYLAKE_HALO

BGA1440

?

3 OF 14

PEG_TXP[0] PEG_TXN[0]

PEG_TXP[1] PEG_TXN[1]

PEG_TXP[2]

PEG_TXN[2]

PEG_TXP[3] PEG_TXN[3]

PEG_TXP[4] PEG_TXN[4]

PEG_TXP[5]

PEG_TXN[5]

PEG_TXP[6] PEG_TXN[6]

PEG_TXP[7]

PEG_TXN[7]

PEG_TXP[8]

PEG_TXN[8] PEG_TXP[9]

PEG_TXN[9]

PEG_TXP[10]

PEG_TXN[10]

PEG_TXP[11]

PEG_TXN[11] PEG_TXP[12]

PEG_TXN[12]

PEG_TXP[13] PEG_TXN[13]

PEG_TXP[14]

PEG_TXN[14]

PEG_TXP[15] PEG_TXN[15]

DMI_TXP[0] DMI_TXN[0]

DMI_TXP[1] DMI_TXN[1]

DMI_TXP[2]

DMI_TXN[2] DMI_TXP[3]

DMI_TXN[3]

B25 A25

B24 C24

B23

A23

B22 C22

B21 A21

B20

C20

B19 A19

B18

C18

A17

B17 C16

B16 A15

B15

C14

B14 A13

B13

C12 B12

A11

B11

C10 B10

B8 A8

C6 B6

B5

A5 D4

B4

?

3

PEG_HTX_GRX_P15 PEG_HTX_GRX_N15

PEG_HTX_GRX_P14

PEG_HTX_GRX_N14

PEG_HTX_GRX_P13

PEG_HTX_GRX_N13

PEG_HTX_GRX_P12 PEG_HTX_GRX_N12

PEG_HTX_GRX_P11 PEG_HTX_GRX_N11

PEG_HTX_GRX_P10 PEG_HTX_GRX_N10

PEG_HTX_GRX_P9 PEG_HTX_GRX_N9

PEG_HTX_GRX_P8 PEG_HTX_GRX_N8

PEG_HTX_GRX_P7 PEG_HTX_GRX_N7

PEG_HTX_GRX_P6

PEG_HTX_GRX_N6

PEG_HTX_GRX_P5

PEG_HTX_GRX_N5

PEG_HTX_GRX_P4

PEG_HTX_GRX_N4

PEG_HTX_GRX_P3 PEG_HTX_GRX_N3

PEG_HTX_GRX_P2 PEG_HTX_GRX_N2

PEG_HTX_GRX_P1 PEG_HTX_GRX_N1

PEG_HTX_GRX_P0 PEG_HTX_GRX_N0

1

2

CH5 0.22U_0201_6.3V6M

1

2

CH6 0.22U_0201_6.3V6M

1

2

CH7 0.22U_0201_6.3V6M

1

2

CH8 0.22U_0201_6.3V6M

1

2

CH9 0.22U_0201_6.3V6M

1

2

CH10 0.22U_0201_6.3V6M

1

2

CH11 0.22U_0201_6.3V6M

1

2

CH12 0.22U_0201_6.3V6M

1

2

CH13 0.22U_0201_6.3V6M

1

2

CH14 0.22U_0201_6.3V6M

1

2

CH15 0.22U_0201_6.3V6M

1

2

CH16 0.22U_0201_6.3V6M

1

2

CH17 0.22U_0201_6.3V6M

1

2

CH18 0.22U_0201_6.3V6M

1

2

CH19 0.22U_0201_6.3V6M

1

2

CH20 0.22U_0201_6.3V6M

1

2

CH21 0.22U_0201_6.3V6M

1

2

CH22 0.22U_0201_6.3V6M

1

2

CH23 0.22U_0201_6.3V6M

1

2

CH24 0.22U_0201_6.3V6M

1

2

CH25 0.22U_0201_6.3V6M

1

2

CH26 0.22U_0201_6.3V6M

1

2

CH27 0.22U_0201_6.3V6M

1

2

CH28 0.22U_0201_6.3V6M

1

2

CH29 0.22U_0201_6.3V6M

1

2

CH30 0.22U_0201_6.3V6M

1

2

CH31 0.22U_0201_6.3V6M

1

2

CH32 0.22U_0201_6.3V6M

1

2

CH33 0.22U_0201_6.3V6M

1

2

CH34 0.22U_0201_6.3V6M

1

2

CH35 0.22U_0201_6.3V6M

1

2

CH36 0.22U_0201_6.3V6M

DMI_CTX_PRX_P0 [19]

DMI_CTX_PRX_N0 [19]

DMI_CTX_PRX_P1 [19]

DMI_CTX_PRX_N1 [19]

DMI_CTX_PRX_P2 [19]

DMI_CTX_PRX_N2 [19]

DMI_CTX_PRX_P3 [19]

DMI_CTX_PRX_N3 [19]

PEG_HTX_C_GRX_P15

PEG_HTX_C_GRX_N15

PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_N14

PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_N13

PEG_HTX_C_GRX_P12

PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_P11

PEG_HTX_C_GRX_N11

PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_N10

PEG_HTX_C_GRX_P9

PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_P8

PEG_HTX_C_GRX_N8

PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_N7

PEG_HTX_C_GRX_P6

PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_P5

PEG_HTX_C_GRX_N5

PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_N4

PEG_HTX_C_GRX_P3

PEG_HTX_C_GRX_N3

PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2

PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1

PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0

2

1

D

C

UH1D

K36

DDI1_TXP[0]

B

A

5

K37

DDI1_TXN[0]

J35

DDI1_TXP[1]

J34

DDI1_TXN[1]

H37

DDI1_TXP[2]

H36

DDI1_TXN[2]

J37

DDI1_TXP[3]

J38

DDI1_TXN[3]

D27

DDI1_AUXP

E27

DDI1_AUXN

H34

DDI2_TXP[0]

H33

DDI2_TXN[0]

F37

DDI2_TXP[1]

G38

DDI2_TXN[1]

F34

DDI2_TXP[2]

F35

DDI2_TXN[2]

E37

DDI2_TXP[3]

E36

DDI2_TXN[3]

F26

DDI2_AUXP

E26

DDI2_AUXN

C34

DDI3_TXP[0]

D34

DDI3_TXN[0]

B36

DDI3_TXP[1]

B34

DDI3_TXN[1]

F33

DDI3_TXP[2]

E33

DDI3_TXN[2]

C33

DDI3_TXP[3]

B33

DDI3_TXN[3]

A27

DDI3_AUXP

B27

DDI3_AUXN

SKL-H_BGA1440

@

4

REV = 1

BGA1440

4 OF 14

EDP_TXP[0] EDP_TXN[0]

EDP_TXP[1]

EDP_TXN[1]

EDP_TXN[2] EDP_TXP[2]

EDP_TXN[3] EDP_TXP[3]

EDP_AUXP EDP_AUXN

EDP_DISP_UTIL

EDP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

D29 E29

F28

E28

B29 A29

B28 C28

C26 B26

A33

EDP_DISP_UTIL

D37

EDP_COMP

G27 G25

G29

?

Close to CPU

3

EDP_TXP0 [34] EDP_TXN0 [34]

EDP_TXP1 [34] EDP_TXN1 [34]

EDP_TXN2 [34] EDP_TXP2 [34]

EDP_TXN3 [34] EDP_TXP3 [34]

EDP_AUXP [34]

EDP_AUXN [34]

1

RH20 0_0402_5%@

RH30 24.9_0402_1%

1

RH145 20_0402_5%

2

1

2

EDP_COMP CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils.

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

BIA_PWM_PCH [16,34]

AUD_AZA_CPU_SCLK [18]

AUD_AZA_CPU_SDO [18]

AUD_AZA_CPU_SDI_R [18]

2011/08/25 2012/07/25

+VCCIO

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Rev

C

Date: Sheet

1

of

7 70Tuesday, November 08, 2016

of

7 70Tuesday, November 08, 2016

of

7 70Tuesday, November 08, 2016

0.1(X00)

B

A

?

SKYLAKE_HALO

Interleave

5

4

3

2

1

?

REV = 1

SKYLAKE_HALO

BGA1440

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[4]/DDR1_DQSP[0]

DDR0_DQSP[5]/DDR1_DQSP[1]

DDR0_DQSP[6]/DDR1_DQSP[4]

DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSP[3]/DDR0_DQSP[5]

DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSN[6]/DDR1_DQSN[4]

DDR0_DQSN[7]/DDR1_DQSN[5]

1 OF 14

DDR0_CKP[0]

DDR0_CKN[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CLKP[2] DDR0_CLKN[2] DDR0_CLKP[3]

DDR0_CLKN[3]

DDR0_CKE[0]

DDR0_CKE[1]

DDR0_CKE[2]

DDR0_CKE[3] DDR0_CS#[0]

DDR0_CS#[1] DDR0_CS#[2]

DDR0_CS#[3]

DDR0_ODT[0]

DDR0_ODT[1] DDR0_ODT[2]

DDR0_ODT[3]

DDR0_MA[3] DDR0_MA[4]

DDR0_PAR

DDR0_ALERT#

DDR0_DQSN[0] DDR0_DQSN[1]

DDR0_DQSP[0] DDR0_DQSP[1]

DDR0_DQSP[8] DDR0_DQSN[8]

?

AG1

AG2 AK1 AK2

AL3 AK3 AL2

AL1 AT1

AT2

AT3

AT5 AD5

AE2 AD2

AE5

AD3

AE4 AE1

AD4 AH5

AH1

AU1 AH4

AG4

AD1 AH3

AP4

AN4 AP5 AP2

AP1 AP3 AN1

AN3 AT4 AH2

AN2 AU4 AE3

AU2 AU3

AG3

AU5

BR5 BL3 BG3

BD3 AB3

V3

R3

M3 BP5

BK3 BF3 BC3

AA3 U3 P3

L3 AY3

BA3

DDR_A_MA0

DDR_A_MA1 DDR_A_MA2

DDR_A_MA3 DDR_A_MA4

DDR_A_MA5

DDR_A_MA6 DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11 DDR_A_MA12

DDR_A_MA13

DDR_A_DQS#0 DDR_A_DQS#1

DDR_A_DQS#2

DDR_A_DQS#3 DDR_A_DQS4

DDR_A_DQS5

DDR_A_DQS6

DDR_A_DQS7

DDR_A_DQS0

DDR_A_DQS1 DDR_A_DQS2

DDR_A_DQS3 DDR_A_DQS#4

DDR_A_DQS#5

DDR_A_DQS#6

DDR_A_DQS#7

M_CLK_DDR0 [14]

M_CLK_DDR#0 [14] M_CLK_DDR#1 [14] M_CLK_DDR1 [14]

DDR_CKE0_DIMMA [14] DDR_CKE1_DIMMA [14]

DDR_CS0_DIMMA# [14]

DDR_CS1_DIMMA# [14]

M_ODT0 [14] M_ODT1 [14]

DDR_A_BS0 [14] DDR_A_BS1 [14] DDR_A_BG0 [14]

DDR_A_RAS# [14] DDR_A_WE# [14] DDR_A_CAS# [14]

DDR_A_BG1 [14]

DDR_A_ACT# [14]

DDR_A_PAR [14] DDR_A_ALERT# [14]

RH148 121_0402_1%

RH149 75_0402_1%

RH150 100_0402_1%

DDR_B_D0

DDR_B_D1 DDR_B_D6

DDR_B_D2

DDR_B_D4

DDR_B_D5

DDR_B_D3

DDR_B_D7

DDR_B_D12

DDR_B_D8

DDR_B_D9

DDR_B_D10

DDR_B_D14

DDR_B_D11

DDR_B_D13

DDR_B_D15

DDR_B_D16

DDR_B_D17

DDR_B_D21

DDR_B_D19

DDR_B_D18

DDR_B_D22

DDR_B_D20

DDR_B_D23

DDR_B_D26

DDR_B_D24

DDR_B_D31

DDR_B_D25

DDR_B_D28

DDR_B_D30 DDR_B_D29

DDR_B_D27

DDR_B_D34

DDR_B_D38 DDR_B_D32

DDR_B_D36

DDR_B_D35 DDR_B_D39

DDR_B_D37

DDR_B_D33 DDR_B_D40

DDR_B_D41

DDR_B_D42

DDR_B_D43

DDR_B_D44

DDR_B_D45

DDR_B_D47

DDR_B_D46

DDR_B_D48

DDR_B_D51

DDR_B_D50 DDR_B_D52 DDR_B_D53

DDR_B_D55

DDR_B_D49

DDR_B_D54

DDR_B_D58

DDR_B_D57

DDR_B_D59

DDR_B_D61

DDR_B_D62

DDR_B_D60

DDR_B_D56

DDR_B_D63

1

2

1

2

1

2

DDR1_DQ[0]/DDR0_DQ[16]

BR11

DDR1_DQ[1]/DDR0_DQ[17]

BT8

DDR1_DQ[2]/DDR0_DQ[18]

BR8

DDR1_DQ[3]/DDR0_DQ[19]

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1_DQ[6]/DDR0_DQ[22]

BN8

DDR1_DQ[7]/DDR0_DQ[23]

BL12

DDR1_DQ[8]/DDR0_DQ[24]

BL11

DDR1_DQ[9]/DDR0_DQ[25]

BL8

DDR1_DQ[10]/DDR0_DQ[26]

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1_DQ[12]/DDR0_DQ[28]

BJ10

DDR1_DQ[13]/DDR0_DQ[29]

BL7

DDR1_DQ[14]/DDR0_DQ[30]

BJ7

DDR1_DQ[15]/DDR0_DQ[31]

BG11

DDR1_DQ[16]/DDR0_DQ[48]

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1_DQ[19]/DDR0_DQ[51]

BF11

DDR1_DQ[20]/DDR0_DQ[52]

BF10

DDR1_DQ[21]/DDR0_DQ[53]

BG7

DDR1_DQ[22]/DDR0_DQ[54]

BF7

DDR1_DQ[23]/DDR0_DQ[55]

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1_DQ[26]/DDR0_DQ[58]

BC8

DDR1_DQ[27]/DDR0_DQ[59]

BC10

DDR1_DQ[28]/DDR0_DQ[60]

BB10

DDR1_DQ[29]/DDR0_DQ[61]

BC7

DDR1_DQ[30]/DDR0_DQ[62]

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1_DQ[32]/DDR1_DQ[16]

AA10

DDR1_DQ[33]/DDR1_DQ[17]

AC11

DDR1_DQ[34]/DDR1_DQ[18]

AC10

DDR1_DQ[35]/DDR1_DQ[19]

AA7

DDR1_DQ[36]/DDR1_DQ[20]

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1_DQ[39]/DDR1_DQ[23]

W8

DDR1_DQ[40]/DDR1_DQ[24]

W7

DDR1_DQ[41]/DDR1_DQ[25]

V10

DDR1_DQ[42]/DDR1_DQ[26]

V11

DDR1_DQ[43]/DDR1_DQ[27]

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

V7

DDR1_DQ[46]/DDR1_DQ[30]

V8

DDR1_DQ[47]/DDR1_DQ[31]

R11

DDR1_DQ[48]

P11

DDR1_DQ[49]

P7

DDR1_DQ[50]

R8

DDR1_DQ[51]

R10

DDR1_DQ[52]

P10

DDR1_DQ[53]

R7

DDR1_DQ[54]

P8

DDR1_DQ[55]

L11

DDR1_DQ[56]

M11

DDR1_DQ[57]

L7

DDR1_DQ[58]

M8

DDR1_DQ[59]

L10

DDR1_DQ[60]

M10

DDR1_DQ[61]

M7

DDR1_DQ[62]

L8

DDR1_DQ[63]

AW11

DDR1_ECC[0]

AY11

DDR1_ECC[1]

AY8

DDR1_ECC[2]

AW8

DDR1_ECC[3]

AY10

DDR1_ECC[4]

AW10

DDR1_ECC[5]

AY7

DDR1_ECC[6]

AW7

DDR1_ECC[7]

G1

DDR_RCOMP[0]

H1

DDR_RCOMP[1]

J2

DDR_RCOMP[2]

SKL-H_BGA1440

@

DDR CHANNEL B

UH1B

BT11

DDR_A_D0

DDR_A_D1

DDR_A_D[0..63][14]

DDR_A_MA[0..13][14]

DDR_A_DQS#[0..7][14] DDR_A_DQS[0..7][14]

D

C

B

DDR_B_D[0..63][15]

DDR_B_MA[0..13][15]

DDR_B_DQS#[0..7][15] DDR_B_DQS[0..7][15]

DDR_A_D2

DDR_A_D7 DDR_A_D4

DDR_A_D5 DDR_A_D6

DDR_A_D3

DDR_A_D9

DDR_A_D13

DDR_A_D10 DDR_A_D11 DDR_A_D12

DDR_A_D8

DDR_A_D14 DDR_A_D15

DDR_A_D20

DDR_A_D16

DDR_A_D23

DDR_A_D19 DDR_A_D21 DDR_A_D17

DDR_A_D22

DDR_A_D18

DDR_A_D24

DDR_A_D25

DDR_A_D26

DDR_A_D27

DDR_A_D28

DDR_A_D29 DDR_A_D30

DDR_A_D31

DDR_A_D32 DDR_A_D33

DDR_A_D34

DDR_A_D35

DDR_A_D36

DDR_A_D37

DDR_A_D38

DDR_A_D39

DDR_A_D44

DDR_A_D45

DDR_A_D43 DDR_A_D47

DDR_A_D41

DDR_A_D40

DDR_A_D42

DDR_A_D46

DDR_A_D53

DDR_A_D51 DDR_A_D49

DDR_A_D55

DDR_A_D52

DDR_A_D54

DDR_A_D48

DDR_A_D50

DDR_A_D56 DDR_A_D57 DDR_A_D58

DDR_A_D63

DDR_A_D60 DDR_A_D61

DDR_A_D62 DDR_A_D59

DDR0_DQ[0]

BT6

DDR0_DQ[1]

BP3

DDR0_DQ[2]

BR3

DDR0_DQ[3]

BN5

DDR0_DQ[4]

BP6

DDR0_DQ[5]

BP2

DDR0_DQ[6]

BN3

DDR0_DQ[7]

BL4

DDR0_DQ[8]

BL5

DDR0_DQ[9]

BL2

DDR0_DQ[10]

BM1

DDR0_DQ[11]

BK4

DDR0_DQ[12]

BK5

DDR0_DQ[13]

BK1

DDR0_DQ[14]

BK2

DDR0_DQ[15]

BG4

DDR0_DQ[16]/DDR0_DQ[32]

BG5

DDR0_DQ[17]/DDR0_DQ[33]

BF4

DDR0_DQ[18]/DDR0_DQ[34]

BF5

DDR0_DQ[19]/DDR0_DQ[35]

BG2

DDR0_DQ[20]/DDR0_DQ[36]

BG1

DDR0_DQ[21]/DDR0_DQ[37]

BF1

DDR0_DQ[22]/DDR0_DQ[38]

BF2

DDR0_DQ[23]/DDR0_DQ[39]

BD2

DDR0_DQ[24]/DDR0_DQ[40]

BD1

DDR0_DQ[25]/DDR0_DQ[41]

BC4

DDR0_DQ[26]/DDR0_DQ[42]

BC5

DDR0_DQ[27]/DDR0_DQ[43]

BD5

DDR0_DQ[28]/DDR0_DQ[44]

BD4

DDR0_DQ[29]/DDR0_DQ[45]

BC1

DDR0_DQ[30]/DDR0_DQ[46]

BC2

DDR0_DQ[31]/DDR0_DQ[47]

AB1

DDR0_DQ[32]/DDR1_DQ[0]

AB2

DDR0_DQ[33]/DDR1_DQ[1]

AA4

DDR0_DQ[34]/DDR1_DQ[2]

AA5

DDR0_DQ[35]/DDR1_DQ[3]

AB5

DDR0_DQ[36]/DDR1_DQ[4]

AB4

DDR0_DQ[37]/DDR1_DQ[5]

AA2

DDR0_DQ[38]/DDR1_DQ[6]

AA1

DDR0_DQ[39]/DDR1_DQ[7]

V5

DDR0_DQ[40]/DDR1_DQ[8]

V2

DDR0_DQ[41]/DDR1_DQ[9]

U1

DDR0_DQ[42]/DDR1_DQ[10]

U2

DDR0_DQ[43]/DDR1_DQ[11]

V1

DDR0_DQ[44]/DDR1_DQ[12]

V4

DDR0_DQ[45]/DDR1_DQ[13]

U5

DDR0_DQ[46]/DDR1_DQ[14]

U4

DDR0_DQ[47]/DDR1_DQ[15]

R2

DDR0_DQ[48]/DDR1_DQ[32]

P5

DDR0_DQ[49]/DDR1_DQ[33]

R4

DDR0_DQ[50]/DDR1_DQ[34]

P4

DDR0_DQ[51]/DDR1_DQ[35]

R5

DDR0_DQ[52]/DDR1_DQ[36]

P2

DDR0_DQ[53]/DDR1_DQ[37]

R1

DDR0_DQ[54]/DDR1_DQ[38]

P1

DDR0_DQ[55]/DDR1_DQ[39]

M4

DDR0_DQ[56]/DDR1_DQ[40]

M1

DDR0_DQ[57]/DDR1_DQ[41]

L4

DDR0_DQ[58]/DDR1_DQ[42]

L2

DDR0_DQ[59]/DDR1_DQ[43]

M5

DDR0_DQ[60]/DDR1_DQ[44]

M2

DDR0_DQ[61]/DDR1_DQ[45]

L5

DDR0_DQ[62]/DDR1_DQ[46]

L1

DDR0_DQ[63]/DDR1_DQ[47]

BA2

DDR0_ECC[0]

BA1

DDR0_ECC[1]

AY4

DDR0_ECC[2]

AY5

DDR0_ECC[3]

BA5

DDR0_ECC[4]

BA4

DDR0_ECC[5]

AY1

DDR0_ECC[6]

AY2

DDR0_ECC[7]

DDR CHANNEL A

SKL-H_BGA1440

@

UH1A

BR6

REV = 1

?

SKYLAKE_HALO

BGA1440

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]

DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]

DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSN[1]/DDR0_DQSN[3]

DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSN[4]/DDR1_DQSN[2]

DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSP[1]/DDR0_DQSP[3]

DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSP[4]/DDR1_DQSP[2]

DDR1_DQSP[5]/DDR1_DQSP[3]

2 OF 14

DDR1_CKP[0]

DDR1_CKN[0]

DDR1_CKN[1] DDR1_CKP[1]

DDR1_CLKP[2] DDR1_CLKN[2] DDR1_CLKP[3]

DDR1_CLKN[3]

DDR1_CKE[0] DDR1_CKE[1]

DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1]

DDR1_CS#[2] DDR1_CS#[3]

DDR1_ODT[0]

DDR1_ODT[1]

DDR1_ODT[2]

DDR1_ODT[3]

DDR1_MA[3] DDR1_MA[4]

DDR1_PAR

DDR1_ALERT#

DDR1_DQSN[6]

DDR1_DQSN[7]

DDR1_DQSP[6] DDR1_DQSP[7]

DDR1_DQSP[8] DDR1_DQSN[8]

DDR_VREF_CA

DDR0_VREF_DQ

DDR1_VREF_DQ

?

AM9

AN9

AM8 AM7

AM11 AM10 AJ10

AJ11 AT8

AT10

AT7 AT11

AF11

AE7

AF10 AE10

AF7

AE8

AE9

AE11

AH10

AH11

AF8

AH8

AH9

AR9

AJ9

AK6 AK5

AL5 AL6

AM6

AN7

AN10 AN8 AR11

AH7 AN11 AR10

AF9 AR7 AT9

AJ7

AR8

BP9 BL9

BG9 BC9 AC9

W9

R9

M9 BR9

BJ9

BF9 BB9 AA9

V9 P9 L9

AW9 AY9

BN13

BP13

BR13

DDR_B_MA0 DDR_B_MA1

DDR_B_MA2

DDR_B_MA3

DDR_B_MA4

DDR_B_MA5 DDR_B_MA6

DDR_B_MA7 DDR_B_MA8

DDR_B_MA9

DDR_B_MA10 DDR_B_MA11

DDR_B_MA12

DDR_B_MA13

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2

DDR_B_DQS#3

DDR_B_DQS#4 DDR_B_DQS#5

DDR_B_DQS#6

DDR_B_DQS#7

DDR_B_DQS0

DDR_B_DQS1

DDR_B_DQS2 DDR_B_DQS3

DDR_B_DQS4 DDR_B_DQS5

DDR_B_DQS6

DDR_B_DQS7

M_CLK_DDR2 [15] M_CLK_DDR#2 [15] M_CLK_DDR#3 [15]

M_CLK_DDR3 [15]

DDR_CKE2_DIMMB [15] DDR_CKE3_DIMMB [15]

DDR_CS2_DIMMB# [15] DDR_CS3_DIMMB# [15]

M_ODT2 [15]

M_ODT3 [15]

DDR_B_RAS# [15] DDR_B_WE# [15]

DDR_B_CAS# [15] DDR_B_BS0 [15]

DDR_B_BS1 [15]

DDR_B_BG0 [15]

DDR_B_BG1 [15]

DDR_B_ACT# [15]

DDR_B_PAR [15]

DDR_B_ALERT# [15]

+V_DDR_REFA_R

+V_DDR_REFB_R

D

C

B

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Title

PROCESSOR(3/7) DDRIII

Size Document Number Rev

C

Date: Sheet

1

of

8 70Tuesday, November 08, 2016

of

8 70Tuesday, November 08, 2016

of

8 70Tuesday, November 08, 2016

0.1(X00)

A

5

CFG Straps for Processor

Stall reset sequence after CPU PLL lock until de-asserted

CFG0

D

PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS

CFG2

Display Port Presence Strap

C

CFG4

PCIE Port Bifurcation Straps

CFG[6:5]

B

PEG DEFER TRAINING

CFG7

A

1 = (Default) Normal Operation; No stall.

*

0 = Stall.

1

CFG0

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

*

CFG2

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

*

CFG4

RH185 1K_0402_5%

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG5

RH186 1K_0402_5%

CFG6

RH187 1K_0402_5%

1: (Default) PEG Train immediately following xxRESETB de assertion

*

2

@

RH183 1K_0402_5%

1

2

RH184 1K_0402_5%

Enable because PS175(DP to HDMI Converter)

1

2

1

2

@

1

2

@

0: PEG Wait for BIOS for training

1

CFG7

2

@

RH188 1K_0402_5%

4

+VCCST

RH163 1K_0402_5%

RH156 51_0402_5%

RH164 1K_0402_5%

RH151 100_0402_5%

RH152 56.2_0402_1%

RH144 49.9_0402_1%

+VCCSTG

1

RH165 1K_0402_5%

3

1

2

H_THERMTRIP#_R

1

2

XDP_PREQ#

@

1

2

H_VCCST_PWRGD

1

2

VR_SVID_DATA

1

2

VR_SVID_ALERT#

1

2

H_CATERR#

@

1

RH153 220_0402_5%

1

RH158 499_0402_1%

1

RH154 60.4_0402_1%

1

RH155 20_0402_5%

1

RH190 0_0402_5%@

1

RH89 0_0402_5%@

DDR_VTT_PG_CTRL

PCH_TRIGGER

CPU_TRIGGER

2

SM_PG_CTRL[57]

H_PROCHOT#

Pilot_05

+1.2V_DDR

+3VS

1

@

CH197

0.1U_0402_10V7K

2

1

RH93 220K_0402_5%

2

VR_SVID_ALERT#[63]

VR_SVID_CLK[63] VR_SVID_DATA[63]

H_PROCHOT#[48,54,55,63]

H_VCCST_PWRGD[18]

H_CPUPWRGD[18]

PLTRST_CPU#[16]

H_PM_SYNC_R[16]

H_PM_DOWN[16]

PECI_EC[16,48]

H_THERMTRIP#_R[16]

PROC_DETECT#[16]

VR_SVID_ALERT#

VR_SVID_DATA

H_PROCHOT#

H_VCCST_PWRGD

H_PM_DOWN

UC1

5

VCC

4

Y

GND

74AUP1G07GW_TSSOP5

PCH_TRIGGER[22]

CPU_TRIGGER[22]

1

NC

2

A

3

PCH_CPU_BCLK_P[17]

PCH_CPU_BCLK_N[17]

PCH_CPU_PCIBCLK_P[17] PCH_CPU_PCIBCLK_N[17]

CPU_24MHZ_P[17] CPU_24MHZ_N[17]

2

VR_SVID_ALERT#_R

2

H_PROCHOT#_R

DDR_VTT_PG_CTRL

2

RH167 30_0402_5%

RH192 30_0402_5%

1

VCCST_PWRGD_CPU

PLTRST_CPU#

H_PM_SYNC_R H_PM_DOWN_R PECI_EC_R

H_THERMTRIP#_R

H_CATERR#

2

PCH_TRIGGER_R

CPU_TRIGGER_R

BH31

BH32

BH29 BR30

BT13

BT31 BP35

BM34 BP31

BT34

BR33

BM30

B31

A32 D35

C36

E31

D31

H13

J31

BN1

UH1E

BCLKP

BCLKN PCI_BCLKP

PCI_BCLKN

CLK24P

CLK24N

VIDALERT#

VIDSCK

VIDSOUT PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD PROCPWRGD

RESET#

PM_SYNC PM_DOWN

PECI

THERMTRIP#

SKTOCC#

PROC_SELECT# CATERR#

SKL-H_BGA1440

@

D1

E1

E3 E2

BR1

BT2

BN35

J24

H24

BN33

BL34

N29

R14

AE29

AA14

A36

A37

H23

J23

F30

E30 B30

C30

G3

J3

BR35

BR31 BH30

SKYLAKE_HALO

BGA1440

REV = 1

UH1K

RSVD_TP RSVD_TP

RSVD_TP

RSVD_TP RSVD

RSVD

RSVD PROC_TRIGIN

PROC_TRIGOUT

RSVD

RSVD RSVD

RSVD

RSVD RSVD

RSVD

RSVD RSVD

SKL-H_BGA1440

@

2

?

5 OF 14

PROC_TDO

PROC_TDI

PROC_TMS

PROC_TCK

PROC_TRST#

PROC_PREQ# PROC_PRDY#

CFG_RCOMP

SKYLAKE_HALO

BGA1440

CFG[0]

CFG[1]

CFG[2]

CFG[3]

CFG[4]

CFG[5] CFG[6] CFG[7]

CFG[8]

CFG[9]

CFG[10] CFG[11] CFG[12]

CFG[13] CFG[14]

CFG[15] CFG[17]

CFG[16]

CFG[19]

CFG[18]

BPM#[0]

BPM#[1] BPM#[2] BPM#[3]

?

11 OF 14

1

BN25

CFG0

BN27

BN26

CFG2

BN28

BR20

CFG4

BM20

CFG5

BT20

CFG6

BP20

CFG7

BR23

BR22

BT23 BT22 BM19

BR19 BP19

BT19 BN23

BP23

BP22

BN22

BR27

BT27 BM31 BT30

BT28

CPU_XDP_TDO

BL32

CPU_XDP_TDI

BP28

CPU_XDP_TMS

BR28

CPU_XDP_TCK

BP30

CPU_XDP_TRST#

BL30

XDP_PREQ#

BP27

XDP_PRDY#

BT25

?

CFG_RCOMP

RSVD_TP RSVD_TP

RSVD_TP

RSVD_TP RSVD_TP

CPU_XDP_TDO [6]

CPU_XDP_TDI [6] CPU_XDP_TMS [6]

CPU_XDP_TCK [6,18]

CPU_XDP_TRST# [6,22]

XDP_PREQ# [22]

XDP_PRDY# [22]

1

RH59

49.9_0402_1%

2

BM33 BL33

BJ14

BJ13

BK28

RSVD

BJ28

RSVD

BJ18

VSS

BJ16

BK16

BK24

BJ24 BK21

RSVD

BJ21

RSVD

BT17

RSVD

BR17

RSVD

BK18

VSS

BJ34 BJ33

G13

RSVD

AJ8

RSVD

BL31

RSVD

B2

NCTF

B38

NCTF

BP1

NCTF

BR2

NCTF

C1

NCTF

C38

NCTF

?REV = 1

D

C

B

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PROCESSOR(4/7) RSVD,CFG

Size Document Number Rev

C

Date: Sheet

1

of

9 70Tuesday, November 08, 2016

of

9 70Tuesday, November 08, 2016

of

9 70Tuesday, November 08, 2016

0.1(X00)

5

4

3

2

1

V32

V33

V34

V35 V36

V37 V38

W13

W14

W29

W30

W31

W32 W35 W36

W37

W38

Y29 Y30 Y31

Y32 Y33 Y34

Y35 Y36

L14

P29 P30 P31

P32

P33 P34 P35

P36 R13

R31

R32

R33

R34 R35 R36

R37

R38

T29

T30 T31

T32 T35

T36 T37

T38

U29 U30

U31

U32

U33 U34

U35

U36

V13

V14

V31 P14

AG37

AG38

+VCC_CORE

1

2

1

2

RH197 100_0402_1%

1

RH198 0_0402_5%@

1

RH28 0_0402_5%@

RH29 100_0402_1%

2

Pilot_05

VCC_SENSE [63]

VSS_SENSE [63]

1

RH166 49.9_0402_1%@

RH57 49.9_0402_1%@

1

RH58 49.9_0402_1%@

UH1J

VCCOPC

VCCOPC VCCOPC

VCCOPC

VCCOPC VCCOPC

VCCOPC VCCOPC VCCOPC

VCCOPC

VCCOPC VCCOPC

VCCOPC

RSVD RSVD

RSVD

RSVD RSVD

RSVD

RSVD RSVD

RSVD

VCCOPC_SENSE

VSSOPC_SENSE

RSVD RSVD

VCCEOPIO

RSVD RSVD

RSVD

VCCEOPIO_SENSE VSSEOPIO_SENSE

RSVD

VCC_OPC_1P8

RSVD

ZVM# MSM#

ZVM2# MSM2#

OPC_RCOMP

OPCE_RCOMP

OPCE_RCOMP2

SKL-H_BGA1440

REV = 1

@

BGA1440

10 OF 14

?

BJ17

BJ19

BJ20 BK17

BK19

BK20 BL16

BL17 BL18 BL19

BL20

BL21

BM17

BN17

BJ23 BJ26

BJ27

BK23

BK26

BK27 BL23

BL24

BL25

BL26

BL27 BL28

BM24

BL15

BM16

BL22

BM22

BP15

BR15

BT15

BP16

BR16

BT16

BN15 BM15

BP17

BN16

BM14

BL14

BJ35

BJ36

AT13

AW13

AU13

AY13

2

BT29

BR25

BP25

D

C

B

?

SKYLAKE_HALO

+VCC_CORE

D

UH1G

AA13

VCC

AA31

VCC

AA32

VCC

AA33

VCC

AA34

VCC

AA35

VCC

AA36

VCC

AA37

VCC

AA38

VCC

AB29

VCC

AB30

VCC

AB31

VCC

AB32

VCC

AB35

VCC

AB36

VCC

AB37

VCC

AB38

VCC

AC13

VCC

AC14

VCC

AC29

VCC

AC30

VCC

AC31

VCC

AC32

VCC

AC33

VCC

AC34

VCC

AC35

VCC

AC36

VCC

AD13

VCC

C

B

AD14 AD31

AD32

AD33

AD34 AD35 AD36

AD37 AD38 AE13

AE14 AE30 AE31

AE32 AE35 AE36

AE37

AE38 AF35 AF36

AF37

AF38

K13 K14

L13 N13

N14 N30 N31

N32 N35 N36

N37 N38 P13

VCC VCC

VCC

VCC VCC VCC

VCC

VCC VCC VCC

VCC

VCC VCC

VCC VCC VCC

SKL-H_BGA1440

@

?

SKYLAKE_HALO

BGA1440

REV = 1 ?

7 OF 14

VCC_SENSE

VSS_SENSE

VCC

VCC VCC

VCC

VCC VCC VCC

VCC

VCC VCC VCC

VCC VCC

VCC

VCC VCC VCC

VCC

VCC VCC VCC

VCC VCC

VCC

VCC VCC VCC

VCC

VCC VCC

VCC

VCC VCC

VCC

VCC VCC

VCC

VCC VCC

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Title

PROCESSOR(5/7) PWR,BYPASS

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

1

of

10 70Tuesday, November 08, 2016

of

10 70Tuesday, November 08, 2016

of

10 70Tuesday, November 08, 2016

0.1(X00)

A

5

4

3

2

1

+VCCIO

10U_0603_6.3V6M

D

+VCCSA

?

SKYLAKE_HALO

UH1I

VCCSA VCCSA

VCCSA

VCCSA VCCSA VCCSA

VCCSA

VCCSA VCCSA

VCCSA

VCCSA VCCSA

VCCSA VCCSA VCCSA

VCCSA

VCCSA VCCSA

VCCIO VCCIO

VCCIO VCCIO VCCIO

VCCIO VCCIO

VCCIO

VCCIO VCCIO

VCCIO

VCCIO VCCIO

SKL-H_BGA1440

@

BGA1440

9 OF 14

VCCPLL_OC

VCCSA_SENSE

VSSSA_SENSE VCCIO_SENSE

VSSIO_SENSE

J30

K29

K30

K31 K32 K33

K34

K35

L31

L32

L35

L36 L37

L38 M29 M30

M31 M32 M33

M34

AG12

M35 M36

G15

G17 G19 G21

H15

H16

H17

H19

H20

H21

H26

H27

J15

J16

J17

J19

J20

J21

J26

J27

C

B B

+VCCIO

VDDQ

VDDQ VDDQ VDDQ

VDDQ VDDQ

VDDQ VDDQ VDDQ

VDDQ

VDDQ VDDQ

VDDQ VDDQ VDDQ

VDDQ

VDDQC

VCCST

VCCSTG

VCCPLL VCCPLL

+1.2V_DDR

AA6

AE12 AF5 AF6

AG5 AG9 AJ12

AL11 AP6

AP7 AR12 AR6

AT12

AW6

AY6

J5 J6

K12 K6 L12

L6 R6 T6

W6 Y12 BH13

G11

H30 H29

G30

H28 J28

M38

M37 H14

J14

?REV = 1

+1.2V_DDR

Pilot_05

1

RH34

@

0_0402_5%

2

+1.2V_VCCPLL_OC

+VCCST

RH201 100_0402_1%

RH202 0_0402_5%@

RH31 0_0402_5%@

RH41 100_0402_1%

RH515 100_0402_1%

RH514 0_0402_5%@

RH513 0_0402_5%@

RH516 100_0402_1%

1

RH107 0_0402_5%@

+VCCSTG

+VCCST

1

+1.2V_DDR

2

+VCCSA

VCCSA_SENSE [63]

VSSSA_SENSE [63]

+VCCIO

VCCIO_SENSE [59]

VSSIO_SENSE [59]

Pilot_05

10U_0603_6.3V6M

CH102

1

2

10U_0603_6.3V6M

CH103

CH104

1

2

+VCCSTG

1

2

1U_0402_6.3V6K

CH106

+VCCST

+1.2V_DDR

1

2

1U_0402_6.3V6K

CH110

1

2

22U_0603_6.3V6M

1

CH129

2

+1.2V_DDR

1U_0402_6.3V6K

CH204

1

2

22U_0603_6.3V6M

1

CH130

CH131

CH132

2

10U_0603_6.3V6M

CH124

CH121

CH118

1

2

+VCCSA

10U_0603_6.3V6M

CH111

1

2

+VCCSA

1U_0402_6.3V6K

CH133

1

2

10U_0603_6.3V6M

CH120

1

2

10U_0603_6.3V6M

CH119

CH122

1

2

1

2

10U_0603_6.3V6M

CH113

CH112

1U_0402_6.3V6K

10U_0603_6.3V6M

CH114

1

2

1U_0402_6.3V6K

CH135

CH134

1

2

10U_0603_6.3V6M

CH123

CH126

CH125

1

2

CH115

10U_0603_6.3V6M

1

2

+VCCSA

CH127

10U_0603_6.3V6M

CH117

CH116

1

2

47U_0603_6.3V6M

CH136

1

2

10U_0603_6.3V6M

CH128

1

2

D

C

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PROCESSOR(6/7) PWR

Size Document Number Rev

Custom

Date: Sheet

1

of

11 70Tuesday, November 08, 2016

of

11 70Tuesday, November 08, 2016

of

11 70Tuesday, November 08, 2016

0.1(X00)

5

4

3

2

1

+VCCGT

?

SKYLAKE_HALO

UH1H

D

C

B B

BG34 BG35 BG36

BH33 BH34

BH35

BH36

BH37 BH38

BJ37 BJ38

BL36

BL37 BM36 BM37

BN36 BN37

BN38

BP37

BP38

BR37

BT37 BE38

BF13

BF14

BF29 BF30

BF31 BF32 BF35

BF36

BF37 BF38

BG29 BG30

BG31 BG32

BG33

BC36 BC37 BC38

BD13 BD14 BD29

BD30 BD31 BD32

BD33 BD34 BD35

BD36 BE31 BE32

BE37

VCCGT VCCGT VCCGT

VCCGT VCCGT

VCCGT

VCCGT VCCGT

VCCGT VCCGT VCCGT

VCCGT VCCGT

VCCGT

VCCGT VCCGT

VCCGT

VCCGT VCCGT

VCCGT VCCGT VCCGT

VCCGT

VCCGT VCCGT

VCCGT

VCCGT VCCGT VCCGT

VCCGT

SKL-H_BGA1440

@

BGA1440

REV = 1

8 OF 14

VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT

VCCGT VCCGT

VCCGT VCCGT VCCGT

VCCGT VCCGT

VCCGT

VCCGT VCCGT VCCGT

VCCGT

VCCGT VCCGT

VCCGT

VCCGT VCCGT

VCCGT

VCCGT VCCGT VCCGT

VCCGT VCCGT

VCCGT

+VCCGT

AV29 AV30 AV31 AV32 AV33

AV34

AV35

AV36 AW14

AW31 AW32 AW33

AW34 AW35 AW36

AW37 AW38

AY29 AY30

AY31

AY32

AY35

AY36

AY37

AY38

BA13

BA14 BA29 BA30

BA31

BA32

BA33

BA34

BA35

BA36 BB13

BB14

BB31

BB32

BB33

BB34 BB35

BB36

BB37

BB38 BC29 BC30

BC31 BC32 BC35

BE33 BE34

BE35

BE36

?

+VCCGT

AJ29

AJ30 AJ31 AJ32

AJ33 AJ34 AJ35

AJ36 AK31 AK32

AK33 AK34 AK35

AK36 AK37 AK38

AL13 AL29 AL30

AL31 AL32 AL35

AL36 AL37 AL38

AM13 AM14 AM29

AM30 AM31 AM32

AM33 AM34 AM35

AM36

AN13 AN14

AN31 AN32 AN33

AN34 AN35 AN36

AN37 AN38 AP13

AP14 AP29 AP30

AP31 AP32 AP35

AP36 AP37 AP38

AR29 AR30 AR31

AR32 AR33 AR34

AR35 AR36 AT14

AT31 AT32 AT33

AT34 AT35 AT36

AT37 AT38 AU14

AU29 AU30 AU31

AU32 AU35 AU36

AU37 AU38

UH1N

VCCGT

VCCGT VCCGT VCCGT

VCCGT VCCGT

SKL-H_BGA1440

REV = 1 @

?

SKYLAKE_HALO

BGA1440

14 OF 14

VCCGTX VCCGTX VCCGTX

VCCGTX VCCGTX

VCCGT_SENSE

VSSGTX_SENSE

VSSGT_SENSE

VCCGTX_SENSE

AF29 AF30 AF31

AF32 AF33 AF34

AG13 AG14 AG31

AG32 AG33 AG34

AG35 AG36 AH13

AH14 AH29 AH30

AH31 AH32

AJ13 AJ14

+VCCGT

1

RH203 100_0402_1%

2

1

AH38

AH35

AH37 AH36

?

RH204 0_0402_5%@

RH32

1

RH33 100_0402_1%

2

1

2

0_0402_5%@

VCCGT_SENSE [63]

VSSGT_SENSE [63]

Pilot_05

D

C

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

PROCESSOR(2/7) PM,XDP,CLK

of

12 70Tuesday, November 08, 2016

of

12 70Tuesday, November 08, 2016

of

1

12 70Tuesday, November 08, 2016

0.1(X00)

5

4

3

2

1

?

SKYLAKE_HALO

UH1F

BGA1440

Y38

VSS

Y37

VSS

Y14

VSS

Y13

W34

W33

W12

M14

M13

M12

Y11

Y10

Y9

Y8

Y7

W5

W4

W3

W2

W1

V30

V29

V12

V6

U38

U37

U6

T34

T33

T14

T13

T12

T11

T10

T9

T8

T7

T5

T4

T3

T2

T1

R30

R29

R12

P38

P37

P12

P6

N34

N33

N12

N11

N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

M6

L34

L33

L30

L29

K38

K11

K10

K9

K8

K7

K5

K4

K3

K2

VSS

SKL-H_BGA1440

REV = 1

@

6 OF 14

D

C

B

NCTFVSS

VSS

VSS VSS VSS

VSS

K1

J36

J33

J32

J25

J22

J18

J10

J7

J4

H35

H32

H25

H22

H18

H12

H11

G28

G26

G24

G23

G22

G20

G18

G16

G14

G12

G10

G9

G8

G6

G5

G4

F36

F31

F29

F27

F25

F23

F21

F19

F17

F15

F13

F11

F9

F8

F5

F4

F3

F2

E38

E35

E34

E9

E4

D33

D30 D28 D26

D24

D22

D20

D18

D16

D14

D12

D10

D9

D6

D3

C37

C31

C29

C27

D38

?

BT32 BT26 BT24

BT21 BT18 BT14

BT12

BR36 BR34 BR29

BR26 BR24 BR21

BR18 BR14 BR12

BP34 BP33

BP29 BP26 BP24

BP21 BP18 BP14

BP12

BN34

BN31 BN30 BN29

BN24 BN21 BN20

BN19 BN18 BN14

BN12

BM38

BM35 BM28

BM27 BM26

BM23 BM21

BM13 BM12

BM9

BM6

BM2

BL29

BK29

BK15 BK14

BJ32 BJ31

BJ25

BJ22

BH14 BH12

BH9 BH8

BH5

BH4

BH1

BG38

BG13 BG12

BF33

BF12

BE29

BD9

BC34

BC12

BB12

C17

C13

BT9 BT5

BR7

BP7

BN9 BN7

BN4 BN2

BE6

C9

REV = 1 @

SKYLAKE_HALO

UH1L

BGA1440

VSS

VSS VSS VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

SKL-H_BGA1440

?

12 OF 14

NCTFVSS NCTFVSS NCTFVSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS VSS

VSS VSS VSS

VSS VSS

SKYLAKE_HALO

UH1M

AW5 AW4 AW3

AW2 AW1

AU9 AU8 AU7

AU6

AR5

AR4 AR3 AR2

AR1

AN6

AN5

AM5 AM4

AM3 AM2 AM1

BB4 BB3

BB2 BB1

BA9 BA8

BA7 BA6

B9

AT6

AP9 AP8

AL9

AL8 AL7 AL4

BGA1440

VSS VSS

VSS VSS VSS

VSS VSS

VSS VSS VSS

SKL-H_BGA1440

REV = 1

@

?

13 OF 14

VSS VSS VSS

VSS VSS

VSS VSS VSS

VSS

NCTFVSS

NCTFVSS NCTFVSS

AK30 AK29 AK4

AJ38 AJ37 AJ6

AJ5 AJ4 AJ3

AJ2 AJ1 AH34

AH33 AH12 AH6

AG30 AG29 AG11

AG10 AG8 AG7

AG6 AF14 AF13

AF12 AF4 AF3

AF2 AF1 AE34

AE33 AE6 AD30

AD29 AD12 AD11

AD10 AD9 AD8

AD7 AD6 AC38

AC37 AC12 AC6

AC5 AC4 AC3

AC2 AC1 AB34

AB33 AB6 AA30

AA29 AA12

A30 A28 A26

A24 A22 A20

A18 A16 A14

A12 A10 A9

A6

B37

B3

A34

A4 A3

?

D

C

B

C25 C23

C21 C19

C15 C11

C8 C5

BM29

BM25

BM18

BM11

BM8 BM7

BM5 BM3

BL38 BL35

BL13 BL6

BK25 BK22

BK13

BK6

BJ30 BJ29

BJ15 BJ12

BH11

BH10

BH7 BH6

BH3 BH2

BG37

BG14

BG6 BF34

BF6 BE30

BE5

BE4 BE3 BE2

BE1 BD38 BD37

BD12 BD11 BD10

BD8 BD7

BD6 BC33

BC14 BC13

BC6 BB30 BB29

BB6 BB5

C2 BT36 BT35

BT4 BT3 BR38

?

BA38

BA37 BA12 BA11

BA10

AY34

AY33 AY14 AY12

AW30 AW29 AW12

AV38

AV37 AU34 AU33

AU12 AU11 AU10

AT30 AT29

AR38 AR37

AR14 AR13

AP34 AP33

AP12 AP11 AP10

AN30

AN29 AN12

AM38 AM37

AM12

AL34 AL33 AL14

AL12 AL10

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(7/7) VSS

1

of

13 70Tuesday, November 08, 2016

of

13 70Tuesday, November 08, 2016

of

13 70Tuesday, November 08, 2016

0.1(X00)

A

5

Layout Note: Place near JDIMM1.257,259

+2.5V_MEM

D

10U_0603_6.3V6M

1

CD9

CD10

2

Layout Note: Place near JDIMM1

1U_0402_6.3V6K

CD3

CD4

1

2

Layout Note: Place near JDIMM1.258

+0.6VS

10U_0603_6.3V6M

1U_0402_6.3V6K

CD12

CD13

1

2

+1.2V_DDR

1U_0402_6.3V6K

CD1

CD2

1

2

C

1U_0402_6.3V6K

CD74

CD75

1

2

1U_0402_6.3V6K

CD76

CD77

1

2

1U_0402_6.3V6K

CD78

CD79

1

2

+1.2V_DDR

10U_0603_6.3V6M

1

CD5

CD6

2

B

DIMM_CHA_SA2

DIMM_CHA_SA1 DIMM_CHA_SA0

+V_DDR_REFA_R

20mil

RH45 2_0402_1%

A

1

CH101

0.022U_0402_16V7K

2

1

RH211

24.9_0402_1%

2

5

10U_0603_6.3V6M

1

CD7

2

10U_0603_6.3V6M

1

CD8

CD70

2

10U_0603_6.3V6M

1

CD71

2

10U_0603_6.3V6M

1

CD72

CD73

2

+1.2V_DDR

1

RH206

1K_0402_1%

1

2

1

1K_0402_1%

2

+V_DDR_REFA

RH209

10U_0603_6.3V6M

CD14

@

10U_0603_6.3V6M

1

2

1

+

CD11 330U_X_2VM_R6M

2

DDR4_DRAMRST#[15]

4

DDR_A_D[0..63][8]

DDR_A_MA[0..13][8]

DDR_A_DQS#[0..7][8] DDR_A_DQS[0..7][8]

Layout Note: Place near JDIMM1.255

CD15

+3VS

0.1U_0402_10V6K CD16

1

CD17

2.2U_0402_6.3V6M

2

DDR_CKE0_DIMMA[8]

DDR_CS0_DIMMA#[8]

DDR_CS1_DIMMA#[8]

+1.2V_DDR

1

RD35 470_0402_1%

2

RD31

1

DDR4_DRAMRST#

4

2

@

0_0402_5%

Pilot_05

+2.5V_MEM

.1U_0402_16V7K

CD69

1

@

2

+3VS

DDR_A_BG1[8] DDR_A_BG0[8]

M_CLK_DDR0[8] M_CLK_DDR#0[8]

DDR_A_PAR[8]

DDR_A_BS1[8]

DDR_A_WE#[8]

M_ODT0[8]

M_ODT1[8]

H_DRAMRST# [18]

3

+1.2V_DDR

JDIMM1

1

VSS1

DDR_A_D5 DDR_A_D1

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D7

DDR_A_D3 DDR_A_D13

DDR_A_D9

DDR_A_D15

DDR_A_D10 DDR_A_D21 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D23 DDR_A_D19 DDR_A_D29

DDR_A_D25

DDR_A_D30 DDR_A_D26

DDR_CKE0_DIMMA DDR_A_BG1

DDR_A_BG0

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8

DDR_A_MA6

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_PAR

DDR_A_BS1

DDR_CS0_DIMMA#

DDR_A_WE#

M_ODT0

DDR_CS1_DIMMA#

M_ODT1

DDR_A_D37 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D38

DDR_A_D34 DDR_A_D44 DDR_A_D40

+1.2V_DDR

DDR_A_D46

DDR_A_D42

DDR_A_D52 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D55

DDR_A_D51 DDR_A_D61 DDR_A_D56

+1.2V_DDR

DDR_A_D62

DDR_A_D58

PCH_SMBCLK[15,18]

3

PCH_SMBCLK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONIC S, INC.

3

DQ5

5

VSS3

7

DQ1

9

VSS5

11

DQS0_c

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25

53

DQS2_c

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DBI3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45

95

DQS8_c

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n ,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

DEREN_40-42271-26001RHF CONN@

Compal Secret Data

2011/08/25 2012/07/25

Compal Secret Data

VSS2

VSS4

VSS6

DM0_n/DBI0_n

VSS7

VSS9

VSS11

DQ12

VSS13

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

DM2_n/DBI2_n

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

DM8_n/DBI_n/NC

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1

VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/NF

VDD10 CK1_t/NF CK1_c/NF

VDD12

A10/AP

VDD14

RAS_n/A1 6

VDD16

CAS_n/A1 5

VDD18

C0/CS2_n/NC

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

Deciphered Date

2

+1.2V_DDR

2

4

DQ4

6 8

DQ0

10 12 14

16

DQ6

18 20

DQ2

22 24 26

28

DQ8

30 32

34 36 38

40 42 44

46 48 50

52 54 56

58 60 62

64 66 68

70 72 74

76 78 80

82 84 86

88 90 92

94 96 98

100 102 104

106 108 110

112 114 116

118 120

A11

122

A7

124 126

A5

128

A4

130 132

A2

134

136 138 140

142 144

A0

146

148 150

BA0

152

154 156 158

A13

160 162 164

166

SA2

168 170

172 174 176

178 180 182

184 186 188

190 192 194

196 198 200

202 204 206

208 210 212

214 216 218

220 222 224

226 228 230

232 234 236

238 240 242

244 246 248

250 252 254

SDA

256

SA0

258

VTT

260

SA1

262

2

DDR_A_D4

DDR_A_D0

DDR_A_D6 DDR_A_D2

DDR_A_D12 DDR_A_D8

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D14

DDR_A_D11 DDR_A_D20 DDR_A_D16

DDR_A_D22 DDR_A_D18 DDR_A_D28

DDR_A_D24 DDR_A_DQS#3

DDR_A_DQS3

DDR_A_D31 DDR_A_D27

DDR4_DRAMRST#

DDR_CKE1_DIMMA

DDR_A_ALERT#

DDR_A_MA11 DDR_A_MA7

DDR_A_MA5

DDR_A_MA4

DDR_A_MA2

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_MA0

DDR_A_MA10

DDR_A_BS0 DDR_A_RAS#

DDR_A_CAS#

DDR_A_MA13

DIMM_CHA_SA2

DDR_A_D36

DDR_A_D32

DDR_A_D39

DDR_A_D35

DDR_A_D45

DDR_A_D41

DDR_A_DQS#5

DDR_A_DQS5

DDR_A_D47

DDR_A_D43

DDR_A_D53

DDR_A_D48

DDR_A_D54

DDR_A_D50

DDR_A_D60

DDR_A_D57

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D63

DDR_A_D59

PCH_SMBDATA

DIMM_CHA_SA0 DIMM_CHA_SA1

1

DDR_CKE1_DIMMA [8]

DDR_A_ACT# [8]

DDR_A_ALERT# [8]

All VREF traces should have 10 mil trace width

M_CLK_DDR1 [8] M_CLK_DDR#1 [8]

DDR_A_BS0 [8]

DDR_A_RAS# [8] DDR_A_CAS# [8]

+V_DDR_REFA

0.1U_0402_10V6K CD96

1

+1.2V_DDR

2

+1.2V_DDR

PCH_SMBDATA [15,18]

Title

Size Document Number Rev

Date: Sheet

+0.6VS

Compal Electronics, Inc.

DDRIII DIMMA

LA-D991P

1

D

C

B

A

0.1(X00)

of

14 70Tuesday, November 08, 2016

of

14 70Tuesday, November 08, 2016

of

14 70Tuesday, November 08, 2016

5

4

3

2

1

Layout Note: Place near JDIMM1.258

+0.6VS

D

Layout Note: Place near JDIMMB

+1.2V_DDR

C

+1.2V_DDR

B

A

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

10U_0603_6.3V6M

1

2

CD32

1

2

CD19

1

2

1

CD23

2

+V_DDR_REFB_R

10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

DIMM_CHB_SA1

DIMM_CHB_SA2 DIMM_CHB_SA0

10U_0603_6.3V6M

1

CD89

CD90

2

1U_0402_6.3V6K

CD20

CD21

1

2

10U_0603_6.3V6M

1

CD24

CD25

2

+3VS

20mil

1

RH46 2_0402_1%

1

CH100

0.022U_0402_16V7K

2

1

RH212

24.9_0402_1%

2

5

Layout Note: Place near JDIMM2.257,259

+2.5V_MEM

CD88

1U_0402_6.3V6K

CD83

CD22

1

2

10U_0603_6.3V6M

1

CD87

CD26

2

+1.2V_DDR

2

1

2

CD81

CD85

1

1K_0402_1%

2

1

1K_0402_1%

2

1U_0402_6.3V6K

CD30

1U_0402_6.3V6K

1

2

10U_0603_6.3V6M

1

2

RH207

+V_DDR_REFB

RH210

DDR_B_D[0..63][8] DDR_B_MA[0..13][8] DDR_B_DQS#[0..7][8] DDR_B_DQS[0..7][8]

1U_0402_6.3V6K

CD31

1

2

CD80

1

2

1

CD84

2

10U_0603_6.3V6M

1

CD27

2

1U_0402_6.3V6K

CD82

10U_0603_6.3V6M

1

+

CD33

CD86

330U_2.5V_M

2

CD28

Layout Note: Place near JDIMM2.255

+3VS

0.1U_0402_10V6K CD34

1

2

CD35

2.2U_0402_6.3V6M

DDR_CKE2_DIMMB[8]

DDR_B_BG1[8] DDR_B_BG0[8]

M_CLK_DDR2[8] M_CLK_DDR#2[8]

DDR_B_PAR[8]

DDR_B_BS1[8]

DDR_CS2_DIMMB#[8]

DDR_B_WE#[8]

M_ODT2[8]

DDR_CS3_DIMMB#[8]

M_ODT3[8]

M_CLK_DDR2

M_CLK_DDR#2

DDR_B_PAR

DDR_B_BS1

DDR_CS2_DIMMB#

DDR_B_WE#

M_ODT2

DDR_CS3_DIMMB#

M_ODT3

+1.2V_DDR

+3VS

+2.5V_MEM

4

PCH_SMBCLK[14,18]

3

+1.2V_DDR

DDR_B_D5

DDR_B_D1

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D7

DDR_B_D3 DDR_B_D13 DDR_B_D9

DDR_B_D15 DDR_B_D10

DDR_B_D21 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D23 DDR_B_D19 DDR_B_D29 DDR_B_D25

DDR_B_D30 DDR_B_D26

DDR_CKE2_DIMMB

DDR_B_BG1 DDR_B_BG0

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8

DDR_B_MA6

DDR_B_MA3 DDR_B_MA1

DDR_B_D37

DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D38

DDR_B_D34

DDR_B_D44

DDR_B_D40

DDR_B_D46

DDR_B_D42

DDR_B_D52

DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D55

DDR_B_D51

DDR_B_D61

DDR_B_D56

DDR_B_D62

DDR_B_D58

PCH_SMBCLK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONT AINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONIC S, INC.

JDIMM2

JP?

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5

11

DQS0_c

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25

53

DQS2_c

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DBI3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45

95

DQS8_c

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n ,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

BELLW_SD-80886-1021 CONN@

2011/08/25 2012/07/25

DM0_n/DBI0_n

DM2_n/DBI2_n

DM8_n/DBI_n/NC

EVENT_n/NF

RAS_n/A1 6

CAS_n/A1 5

C0/CS2_n/NC

DM4_n/DBI4_n

DM6_n/DBI6_n

Compal Secret Data

VSS2

DQ4

VSS4

DQ0

VSS6

VSS7

DQ6

VSS9

DQ2

VSS11

DQ12

VSS13

DQ8

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1

VDD2

ACT_n

ALERT_n

VDD4

A11

A7

VDD6

A5

A4

VDD8

A2

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A0

A10/AP

VDD14

BA0

VDD16

A13

VDD18

VREFCA

SA2

VSS54

DQ36

VSS56

DQ32

VSS58

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

SDA

SA0 VTT SA1

GND2

Deciphered Date

2

4 6

8

10 12

14

16 18

20

22 24

26

28 30

32

34 36

38

40 42

44

46 48

50

52 54

56

58 60

62

64 66

68

70 72

74 76

78

80 82

84

86 88

90

92

94 96

98

100 102

104

106 108

110

112 114

116

118 120

122

124 126

128

130 132

134

136 138

140

142 144

146

148 150

152

154 156

158

160 162

164

166 168

170

172 174

176

178 180

182

184 186

188

190 192

194

196 198

200

202 204

206

208 210 212

214 216 218

220 222 224

226 228 230

232 234 236 238 240 242

244

246 248

250 252 254

256 258 260

262

2

+1.2V_DDR

DIMM_CHB_SA2

DDR_B_D36

DDR_B_D32

DDR_B_D39

DDR_B_D35

DDR_B_D45

DDR_B_D41

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D47

DDR_B_D43

DDR_B_D53

DDR_B_D48

DDR_B_D54

DDR_B_D50

DDR_B_D60

DDR_B_D57

DDR_B_DQS#7

DDR_B_DQS7

DDR_B_D63

DDR_B_D59

PCH_SMBDATA

DIMM_CHB_SA0 DIMM_CHB_SA1

DDR_B_D4

DDR_B_D0

DDR_B_D6 DDR_B_D2

DDR_B_D12 DDR_B_D8

DDR_B_DQS#1

DDR_B_DQS1

DDR_B_D14

DDR_B_D11

DDR_B_D20 DDR_B_D16

DDR_B_D22

DDR_B_D18 DDR_B_D28 DDR_B_D24

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D31

DDR_B_D27

DDR4_DRAMRST#

DDR_CKE3_DIMMB

DDR_B_ALERT#

DDR_B_MA11 DDR_B_MA7

DDR_B_MA5

DDR_B_MA4

DDR_B_MA2

M_CLK_DDR3

M_CLK_DDR#3

DDR_B_MA0

DDR_B_MA10

DDR_B_BS0

DDR_B_RAS#

DDR_B_CAS#

DDR_B_MA13

+1.2V_DDR

DDR4_DRAMRST# [14] DDR_CKE3_DIMMB [8]

DDR_B_ACT# [8]

DDR_B_ALERT# [8]

All VREF traces should

M_CLK_DDR3 [8] M_CLK_DDR#3 [8]

DDR_B_BS0 [8] DDR_B_RAS# [8]

DDR_B_CAS# [8]

+V_DDR_REFB

0.1U_0402_10V6K CD29

1

2

PCH_SMBDATA [14,18]

+0.6VS

Title

DDRIII DIMMB

Size Document Number Rev

LA-D991P

Date: Sheet

have 10 mil trace width

Compal Electronics, Inc.

1

D

C

B

A

0.1(X00)

of

15 70Tuesday, November 08, 2016

of

15 70Tuesday, November 08, 2016

of

15 70Tuesday, November 08, 2016

5

4

3

2

1

UH2C

AV2

CL_CLK

AV3

CL_DATA

AW2

CL_RST#

R44

T91PAD~D@

GPP_G8/FAN_PWM_0

R43

GPP_G9/FAN_PWM_1

U39

GPP_G10/FAN_PWM_2

N42

GPP_G11/FAN_PWM_3

D

SSD

HDD

SSD

C

B

CAM_CBL_DET#[34]

KB_BL_DET[40]

PCIE_PTX_SSDRX_P11[44]

PCIE_PTX_SSDRX_N11[44]

PCIE_PRX_SSDTX_P11[44] PCIE_PRX_SSDTX_N11[44]

SATA_PTX_DRX_N1B[44]

SATA_PTX_DRX_P1B[44]

SATA_PRX_DTX_N1B[44]

SATA_PRX_DTX_P1B[44]

PCIE_PTX_SSDRX_P12[44] PCIE_PTX_SSDRX_N12[44]

PCIE_PRX_SSDTX_P12[44] PCIE_PRX_SSDTX_N12[44]

EDP_HPD[34]

CAM_CBL_DET#

U43

U42

T94PAD~D@

U41 M44

U36

P44 T45

T44 B33

C33

K31 L31

AB33

AB35 AA44 AA45

B38 C38 D39

E37 C36

B36

G35

E35

A35

B35 H33 G33

J45

K44 N38

N39 H44 H43

L39

L37

GPP_G0/FAN_TACH_0

GPP_G1/FAN_TACH_1 GPP_G2/FAN_TACH_2 GPP_G3/FAN_TACH_3

GPP_G4/FAN_TACH_4 GPP_G5/FAN_TACH_5 GPP_G6/FAN_TACH_6

GPP_G7/FAN_TACH_7 PCIE11_TXP

PCIE11_TXN

PCIE11_RXP PCIE11_RXN

GPP_F10/SCLOCK

GPP_F11/SLOAD GPP_F13/SDATAOUT0 GPP_F12/SDATAOUT1

PCIE14_TXN/SATA1B_TXN PCIE14_TXP/SATA1B_TXP PCIE14_RXN/SATA1B_RXN

PCIE14_RXP/SATA1B_RXP PCIE13_TXN/SATA0B_TXN

PCIE13_TXP/SATA0B_TXP

PCIE13_RXN/SATA0B_RXN PCIE13_RXP/SATA0B_RXP

PCIE12_TXP

PCIE12_TXN PCIE12_RXP PCIE12_RXN

PCIE20_TXP PCIE20_TXN PCIE20_RXP

PCIE20_RXN PCIE19_TXP PCIE19_TXN

PCIE19_RXP PCIE19_RXN

SKY-H-PCH_BGA837

@

UH2E

AW4

GPP_I0/DDPB_HPD0

AY2

GPP_I1/DDPC_HPD1

AV4

GPP_I2/DDPD_HPD2

BA4

GPP_I3/DDPE_HPD3

BD7

GPP_I4/EDP_HPD

SKY-H-PCH_BGA837

@

SKY-S-PCH_BGA837

CLINK

FAN

SKY-S-PCH_BGA837

REV = 1.3

PCIe/SATA

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_F0/SATAXPCIE3/SATAGP3 GPP_F1/SATAXPCIE4/SATAGP4 GPP_F2/SATAXPCIE5/SATAGP5

GPP_F3/SATAXPCIE6/SATAGP6 GPP_F4/SATAXPCIE7/SATAGP7

HOST

3 OF 12REV = 1.3

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

5 OF 12

PCIE9_RXN/SATA0A_RXN

PCIE9_RXP/SATA0A_RXP PCIE9_TXN/SATA0A_TXN

PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN PCIE10_RXP/SATA1A_RXP PCIE10_TXN/SATA1A_TXN

PCIE10_TXP/SATA1A_TXP

PCIE15_RXN/SATA2_RXN

PCIE15_RXP/SATA2_RXP

PCIE15_TXN/SATA2_TXN PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN

PCIE16_RXP/SATA3_RXP PCIE16_TXN/SATA3_TXN PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN

PCIE17_RXP/SATA4_RXP PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN

PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN PCIE18_TXP/SATA5_TXP

GPP_E8/SATALED#

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THERMTRIP#

PM_SYNC

PLTRST_CPU#

PM_DOWN

BB3 BD6 BA5

BC4 BE5 BE6

Y44

GPP_F14

V44

GPP_F23

W39

GPP_F22

L43

GPP_G23

L44

GPP_G22

U35

GPP_G21

R35

GPP_G20

BD36

GPP_H23

PECI

G31

H31 C31 B31

G29 E29 C32

B32 F41

E41

B39 A39

D43

E42 A41 A40

H42 H40 E45

F45 K37

G37

G45 G44

AD44

AG36 AG35 AG39

AD35 AD31 AD38

AC43 AB44

W36 W35 W42

AJ3

AL3 AJ4 AK2

AH2

PCH_SATA_LED#

T182 PAD~D @

H_THERMTRIP#

PECI

DDI1_DDPB_CTRLCLK DDI1_DDPB_CTRLDAT

T2 PAD~D @

T4 PAD~D @

T8 PAD~D @

SATA_PRX_SSDTX_N0A [44]

SATA_PRX_SSDTX_P0A [44]

SATA_PTX_SSDRX_N0A [44] SATA_PTX_SSDRX_P0A [44]

PCIE_PRX_SSDTX_N10 [44]

PCIE_PRX_SSDTX_P10 [44]

PCIE_PTX_SSDRX_N10 [44] PCIE_PTX_SSDRX_P10 [44]

PCH_SATA_LED# [49]

mCARD_PCIE#_SATA [44]

BIA_PWM_PCH [7,34]

L_BKLT_EN_EC [48]

ENVDD_PCH [32]

1

2

RH191 620_0402_5%

1

RH138 13_0402_5%

RH189

2

1

2

PLTRST_CPU# [9]

H_PM_DOWN [9]

PROC_DETECT# [9]

30_0402_5%

H_THERMTRIP#_R [9]

PECI_EC [9,48]

H_PM_SYNC_R [9]

SSD

mCARD_PCIE#_SATA

CAM_CBL_DET#

PCH_SATA_LED#

DDI1_DDPB_CTRLCLK DDI1_DDPB_CTRLDAT

1

2

RH68 10K_0402_5%

1

2

RH79 10K_0402_5%

1

2

RH80 10K_0402_5%

1

RH141 2.2K_0402_5%

RH142 2.2K_0402_5%

2

1

2

D

+3VALW

+3VS

C

+3VS

B

PCH Strap PIN

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/08/25 2012/07/25

SSD

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCH (1/8) SATA,HDA

LA-D991P

1

of

16 70Tuesday, November 08, 2016

of

16 70Tuesday, November 08, 2016

of

16 70Tuesday, November 08, 2016

0.1(X00)

A

5

4

3

2

1

UH2G

AR17

+3VS

RP3

4

5

LAN_CLKREQ#

3

6

SRCCLKREQ7#

2

7

WLAN_CLK_REQ#

1

8

D

C

B

10K_0804_8P4R_5%

+3VS

10K_0804_8P4R_5%

+3VS

10K_0804_8P4R_5%

+3VS

10K_0804_8P4R_5%

+3V_ROM

RH74 4.7K_0402_5%

SSD_CLK_REQ#

RP2

@

4

5

3

2

1

RP22

4

3 2

1

RP23

4

3 2

1

SRCCLKREQ5#

6

CLKREQ_PCIE#0

7

SRCCLKREQ4#

8

SRCCLKREQ1#

@

5

SRCCLKREQ15#

6

SRCCLKREQ9#

7

SRCCLKREQ8#

8

SRCCLKREQ10#

5

VGA_CLK_REQ#

6

SRCCLKREQ13#

7

SRCCLKREQ14#

8

SRCCLKREQ11#

1

2

PCH_SPI_CS#

+1VALW

LAN_CLKREQ#[47]

WLAN_CLK_REQ#[43]

SSD_CLK_REQ#[44]

VGA_CLK_REQ#[23]

GPU - N16P-GX

PCH_CPU_BCLK_P[9]

RH71 2.7K_0402_1%

CPU_24MHZ_P[9]

CPU_24MHZ_N[9]

PCH_CPU_BCLK_N[9]

1

CLK_PEG_N16P#[23]

CLK_PEG_N16P[23]

T92PAD~D@

XTAL24_OUT XTAL24_IN

2

PCH_RTCX1 PCH_RTCX2

CLKREQ_PCIE#0 SRCCLKREQ1# LAN_CLKREQ#

WLAN_CLK_REQ#

SRCCLKREQ4#

SRCCLKREQ5# SSD_CLK_REQ#

SRCCLKREQ7#

SRCCLKREQ8#

SRCCLKREQ9# SRCCLKREQ10# SRCCLKREQ11#

VGA_CLK_REQ#

SRCCLKREQ13# SRCCLKREQ14# SRCCLKREQ15#

T17PAD~D@

PCH_SPI_SI

PCH_SPI_SO

PCH_SPI_CS# PCH_SPI_CLK

PCH_SPI_WP# PCH_SPI_HOLD#

GPP_A16/CLKOUT_48

G1

CLKOUT_CPUNSSC_P

F1

CLKOUT_CPUNSSC

G2

CLKOUT_CPUBCLK_P

H2

CLKOUT_CPUBCLK

A5

XTAL24_OUT

A6

XTAL24_IN

E1

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRCCLKREQ0#

AW24

GPP_B6/SRCCLKREQ1#

AT24

GPP_B7/SRCCLKREQ2#

BD25

GPP_B8/SRCCLKREQ3#

BB24

GPP_B9/SRCCLKREQ4#

BE25

GPP_B10/SRCCLKREQ5#

AT33

GPP_H0/SRCCLKREQ6#

AR31

GPP_H1/SRCCLKREQ7#

BD32

GPP_H2/SRCCLKREQ8#

BC32

GPP_H3/SRCCLKREQ9#

BB31

GPP_H4/SRCCLKREQ10#

BC33

GPP_H5/SRCCLKREQ11#

BA33

GPP_H6/SRCCLKREQ12#

AW33

GPP_H7/SRCCLKREQ13#

BB33

GPP_H8/SRCCLKREQ14#

BD33

GPP_H9/SRCCLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

P1

CLKOUT_PCIE_N14

R2

CLKOUT_PCIE_P14

W7

CLKOUT_PCIE_N13

Y5

CLKOUT_PCIE_P13

U2

CLKOUT_PCIE_N12

U3

CLKOUT_PCIE_P12

SKY-H-PCH_BGA837

@

BD17

GPP_A11/PME#

AG15

RSVD_AG15

AG14

RSVD_AG14

AF17

RSVD_AF17

AE17

RSVD_AE17

AR19

TP5

AN17

TP4

BB29

SPI0_MOSI

BE30

SPI0_MISO

BD31

SPI0_CS0#

BC31

SPI0_CLK

AW31

SPI0_CS1#

BC29

SPI0_IO2

BD30

SPI0_IO3

AT31

SPI0_CS2#

AN36

GPP_D1/SPI1_CLK

AL39

GPP_D0/SPI1_CS#

AN41

GPP_D3/SPI1_MOSI

AN38

GPP_D2/SPI1_MISO

AH43

GPP_D22/SPI1_IO3

AG44

GPP_D21/SPI1_IO2

@

UH2A

SKY-H-PCH_BGA837

SKY-S-PCH_BGA837

7 OF 12REV = 1.3

SKY-S-PCH_BGA837

1 OF 12 REV = 1.3

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

CLKOUT_PCIE_N2

CLKOUT_PCIE_P2 CLKOUT_PCIE_N3

CLKOUT_PCIE_P3

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

CLKOUT_PCIE_N5

CLKOUT_PCIE_P5 CLKOUT_PCIE_N6

CLKOUT_PCIE_P6

CLKOUT_PCIE_N7 CLKOUT_PCIE_P7

CLKOUT_PCIE_N8

CLKOUT_PCIE_P8 CLKOUT_PCIE_N9

CLKOUT_PCIE_P9

CLKOUT_PCIE_N10 CLKOUT_PCIE_P10

CLKOUT_PCIE_N11

CLKOUT_PCIE_P11

GPP_B13/PLTRST#

GPP_G16/GSXCLK

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_G14/GSXDIN

GPP_G15/GSXSRESET#

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1

GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

L1

L2 J1

J2

N7 N8

L7 L5

D3

F2 E5

G4

D5 E6

D8

D7 R8

R7

U5 U7

W10

W11 N3

N2

P3 P2

R3

R4

BB27

PCH_PLTRST#

P43

R39 R36 R42

R41

AF41

SIO_EXT_SMI#

AE44

TOUCH_SCREEN_PD#

BC23

TOUCHPAD_INTR#

BD24 BC36

BE34 BD39 BB36

BA35 BC35 BD35

AW35 BD34

BE11

INTRUDER#

+3V_ROM

PCH_CPU_PCIBCLK_N [9] PCH_CPU_PCIBCLK_P [9]

CLK_PCIE_LAN# [47]

CLK_PCIE_LAN [47]

CLK_PCIE_WLAN# [43] CLK_PCIE_WLAN [43]

CLK_PCIE_SSD# [44] CLK_PCIE_SSD [44]

DGPU_PWRGD_EC

LAN

NGFF - WLAN

NGFF - SSD

SIO_EXT_SMI# [48]

TOUCH_SCREEN_PD# [34]

DGPU_PWRGD_EC [48]

+3VALW

SPI ROM FOR ME ( 16MByte )

1

2

@

DI(IO0)

VCC

CLK

RH121 0_0603_5%

8 7

PCH_SPI_HOLD#_R

6

PCH_SPI_CLK_R

5

PCH_SPI_SI_R

PCH_PLTRST#_EC[23,43,44,47,48]

PCH_SPI_CS#

PCH_SPI_HOLD#

PCH

A

EC

PCH_SPI_CLK

PCH_SPI_SO

PCH_SPI_SI PCH_SPI_WP#

EC_SPI_CLK_R[48]

EC_SPI_SI_R[48] EC_SPI_SO_R[48]

EC_SPI_CS#_R[48]

1

RH101 0_0402_5%@

1

RH104 22_0402_1%

1

RH507 22_0402_1%

1

RH508 22_0402_1%

1

RH509 22_0402_1%

1

RH510 22_0402_1%

Pilot_05 Pilot_05

2

1

2

PCH_SPI_HOLD#_R

RE71

15_0402_1%

1

RE126 15_0402_1%

1

RE127 15_0402_1%

1

RE128 15_0402_1%

1

RE129 15_0402_1%

PCH_SPI_CLK_R

PCH_SPI_SO_R

PCH_SPI_SI_R PCH_SPI_WP#_R

PCH_SPI_SO_R PCH_SPI_WP#_R

UH8

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25Q128FVSIQ_SO8

/HOLD(IO3)

RTC CRYSTAL

RH70 10M_0402_5%

32.768KHZ 9PF 20PPM 9H03280012

Max Crystal ESR = 50k Ohm.

1

CH45

8.2P_0402_50V8D

2

RH72 1M_0402_5%

24MHZ_12PF_X3G024000DC1H

1

CH47 15P_0402_50V8J

2

DGPU_PWRGD_EC

TOUCH_SCREEN_PD#

TOUCHPAD_INTR#

SIO_EXT_SMI#

INTRUDER#

TOUCHPAD_INTR#

1

RH77 100K_0402_5%

2

1

2

YH1

1

2

1

2

1

2

YH2

1

3

2

4

1

2

1

2

RH500 10K_0402_5%

1

2

RH69 10K_0402_5%

1

2

RH179 10K_0402_5%

1

2

RH110 10K_0402_5%

1

@

2

+3VS

UH7

4

OUT

2

PTP_INT# [41,48]

1

MC74VHC1G08DFT2G_SC70-5

5

IN1

VCC

IN2

GND

3

RH143 330K_0402_5%

DH1

2

RB751S40T1G_SOD523-2

RH1 0_0402_5%

PCH_RTCX1

PCH_RTCX2

CH46

8.2P_0402_50V8D

XTAL24_IN

XTAL24_OUT

CH48 18P_0402_50V8J

1 2

D

C

+3VS

+3VALW

+RTCVCC

B

PCH_PLTRST#

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCH (2/8) SMBUS, CLK, SPI, LPC

LA-D991P

1

of

17 70Tuesday, November 08, 2016

of

17 70Tuesday, November 08, 2016

of

17 70Tuesday, November 08, 2016

0.1(X00)

5

RP15

1

8

HDA_SDOUT_AUDIO[37]

HDA_BITCLK_AUDIO[37] HDA_SYNC_AUDIO[37]

D

+RTCVCC

1

RH83 20K_0402_5%

+RTCVCC

RH84 20K_0402_5%

+3VALW

C

+3VS

B

2

1

2

1

RH21 1K_0402_5%

1

RH22 1K_0402_5%

1

RH23 1K_0402_5%

1

RH25 1K_0402_5%

1

RH62 499_0402_1%

1

RH63 499_0402_1%

1

RH27 1K_0402_5%

1

RH26 1K_0402_5%

1

RH86 10K_0402_5%

1

RH88 47K_0402_5%@

1

RH13 100K_0402_5%

Service Mode Switch: Add a switch to ME_FWP signal to unlock the ME region and allow the entire region of the SPI flash to be updated using FPT.

CH52

1U_0402_6.3V6K

CH53

1U_0402_6.3V6K

2

2 3

4

7

6 5

33_0804_8P4R_5%

PCH_SRTCRST#

1

2

PCH_RTCRST#

1

CLRP1

SHORT PADS

2

SMBCLK SMBDATA SML1_SMBCLK

SML1_SMBDAT

SML0_SMBCLK SML0_SMBDATA

PCH_RSMRST#_R

PCH_DPWROK

HDA_SDOUT

HDA_BITCLK

HDA_SYNC

@

PCH_SMBCLK

PCH_SMBDATA

DGPU_PWROK

AUD_AZA_CPU_SCLK[7]

AUD_AZA_CPU_SDO[7]

HDA_SDIN0_AUDIO[37]

AUD_AZA_CPU_SDI_R[7]

PCH_RSMRST#[48]

SML1_SMBCLK

SML1_SMBDAT

Pilot_05

QH5A

2

2N7002EDW 2N SOT-363-6

1

4

1

2

RH96 0_0402_5%@

Close to PCH

1

2

RH146 30_0402_5%

1

2

RH147 30_0402_5%

DGPU_PWROK[23,61]

PCH_RTCRST#[49]

1

2

@

RH503 0_0402_5%

1

2

@

RH9 0_0402_5%

+3VALW

6

5

3

4

QH5B

2N7002EDW 2N SOT-363-6

HDA_BITCLK

HDA_SDIN0

HDA_SDOUT

HDA_SYNC

AUD_AZA_CPU_SDO_R AUD_AZA_CPU_SDI_R AUD_AZA_CPU_SCLK_R

DGPU_PWROK

PCH_RTCRST#

PCH_SRTCRST# PCH_PWROK

PCH_RSMRST#_R

PCH_DPWROK

SMBALERT#

SMBCLK SMBDATA

SML0ALERT# SML0_SMBCLK SML0_SMBDATA SML1ALERT#

SML1_SMBCLK SML1_SMBDAT

GPU_THM_SMBCLK [23,42,48]

GPU_THM_SMBDAT [23,42,48]

2N7002EDW 2N SOT-363-6

SMBCLK

SMBDATA

2N7002EDW 2N SOT-363-6

6

QH4A

BA9 BD8

BE7 BC8

BB7

BD9 BD1

BE2

AM1 AN2 AM2

AL42

T120PAD~D@

AN42

AM43

AJ33

AH44

AJ35

AJ38 AJ42

BC10

BB10

AW11

BA11

AV11 BB41

AW44

BB43 BA40 AY44

BB39 AT27

AW42

AW45

2

UH2D

HDA_BCLK HDA_RST#

HDA_SDI0 HDA_SDI1

HDA_SDO

HDA_SYNC RSVD_BD1

RSVD_BE2

DISPA_SDO DISPA_SDI DISPA_BCLK

GPP_D8/SSP0_SCLK GPP_D7/SSP0_RXD GPP_D6/SSP0_TXD

GPP_D5/SSP0_SFRM GPP_D20/DMIC_DATA0 GPP_D19/DMIC_CLK0

GPP_D18/DMIC_DATA1 GPP_D17/DMIC_CLK1

RTCRST#

SRTCRST# PCH_PWROK

RSMRST#

DSW_PWROK GPP_C2/SMBALERT# GPP_C0/SMBCLK

GPP_C1/SMBDATA GPP_C5/SML0ALERT# GPP_C3/SML0CLK

GPP_C4/SML0DATA GPP_B23/SML1ALERT#/PCHHOT# GPP_C6/SML1CLK

GPP_C7/SML1DATA

SKY-H-PCH_BGA837

@

AUDIO

+3VS

PCH to DDR

1

3

QH4B

PCH_SMBCLK

5

4

PCH_SMBDATA

3

SKY-S-PCH_BGA837

GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_A13/SUSWARN#/SUSPWRDNACK

SMBUS

JTAG

4 OF 12REV = 1.3

ALL_SYS_PWRGD[18,48,56]

PCH_SMBCLK [14,15]

PCH_SMBDATA [14,15]

GPP_A8/CLKRUN#

GPD11/LANPHYPC GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B1

GPP_G17/ADR_COMPLETE

GPP_B0

GPP_B11

SYS_PWROK

WAKE#

GPD6/SLP_A#

SLP_LAN#

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#

GPD1/ACPRESENT

SLP_SUS#

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

PROCPWRGD

ITP_PMODE

JTAGX

JTAG_TMS

JTAG_TDO

JTAG_TDI

JTAG_TCK

IMVP_VR_PG[63]

1

RH106 0_0402_5%

Pilot_05

@

BB17 AW22

AR15 AV13 BC14

BD23 AL27 AR27

N44 AN24 AY1

BC13 BC15 AV15

BC26 AW15 BD15

BA13 AN15

BD13

BB19 BD19

BD11

BB15 BB13 AT13

AW1 BD26 AM3

AT2 AR3 AR2

AP1 AP2 AN3

2

CLKRUN#

SIO_SLP_WLAN#

SYS_PWROK

PCH_PCIE_WAKE#

PCH_BATLOW#

ME_SUS_PWR_ACK

LAN_WAKE#

AC_PRESENT

SYS_RESET#

SPKR

PCH_JTAGX

PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI PCH_JTAG_TCK

2

CLKRUN# [48]

T4934 PAD~D @

H_DRAMRST# [14]

LAN_DISABLE#_R [47]

3.3V_CAM_EN# [34,53]

SYS_PWROK [48]

1

RH114 0_0402_5%@

SIO_SLP_A# [49]

SIO_SLP_S0# [49]

SIO_SLP_S3# [32,33,34,39,48,49,57]

SIO_SLP_S4# [32,33,48,49,69] SIO_SLP_S5# [49]

SUSCLK [43,44,48]

ME_SUS_PWR_ACK [48]

1

RH11 0_0402_5%@

1

2

DV1 RB751S40T1G_SOD523-2

SIO_PWRBTN# [48]

SYS_RESET# [49]

SPKR [37]

H_CPUPWRGD [9]

1

RH38 0_0402_5%@

PCH_JTAG_TMS [6]

PCH_JTAG_TDO [6] PCH_JTAG_TDI [6] PCH_JTAG_TCK [6]

@

1

+3VS

5

1

VCC

IN1

OUT

2

IN2

GND

MC74VHC1G08DFT2G_SC70-5

3

2

UH14

4

RH102 0_0402_5%

2

PCIE_WAKE# [43,47,48]

T20 PAD~D @

EC_WAKE# [48]

ACAV_IN [48,54,55]

CPU_XDP_TCK [6,9]

PCH_PWROK

1

RH94 10K_0402_5%

2

Pilot_05

PCH_PCIE_WAKE#

PCH_BATLOW#

LAN_WAKE#

AC_PRESENT

ME_SUS_PWR_ACK

SYS_RESET#

CLKRUN#

RH17 1K_0402_5%

RH81 8.2K_0402_5%

RH181 10K_0402_5%

RH125 8.2K_0402_5%

RH67 1M_0402_5%@

RH193 8.2K_0402_5%

Pilot_05

+3VALW

1

RH82 4.7K_0402_5%@

Top Swap Override (internal PD)

HIGH LOW(DEFAULT)

+3VALW

1

RH66 4.7K_0402_5%

TLS CONFIDENTIALITY

HIGH LOW(DEFAULT)

+3VALW

1

RH64 4.7K_0402_5%@

EC interface

HIGH LOW(DEFAULT)

+3VALW

RH65 150K_0402_5%

PCHHOT#

HIGH LOW(DEFAULT)

1

2

1

2

1

2

1

2

1

2

1

2

1

2

RH85 8.2K_0402_5%

2

ENABLE DISABLE

2

vPRO non-vPRO

2

ESPI LPC

1

2

Enable Disable

+3V_PCH_DSW

+3VALW

+3VS

SPKR

SMBALERT#

SML0ALERT#

SML1ALERT#

D

C

B

Buffer with Open Drain Output For VTT power control

1

HDA_SDOUT

ME_FWP_EC[48]

ME_FWP PCH has internal 20K PD.

FLASH DESCRIPTOR SECURITY OVERRIDE

A

Disable ME Protect (ME can be updated) ----> Pin1 & Pin2 short Enable ME Protect (ME cannot be updated)-->Pin3 & Pin2 short(Default position)

2

RH181K_0402_5%

1

RH470_0402_5% @

Pilot_05

ME_EN

VR_ON[33,63]

0.1U_0402_16V7K

1

NC

2

A

3

GND

74AUP1G07GW_TSSOP5

+3VALW

CC298

1

2

UC16

VCC

Y

5

4

H_VCCST_PWRGD

H_VCCST_PWRGD [9]

+VCCIO_PG[59]

RH103

1

0_0402_5%

+3VS

1

RH180 100K_0402_5%

2

@

1

RH499 0_0402_5%@

RH105

1

2

@

0_0402_5%

2

ALL_SYS_PWRGD [18,48,56]

Reserve for EMI

1

2

CH50 10P_0402_25V8J

EMC@

1

2

CH51 10P_0402_25V8J@

Reserve for RF please close to UH1

IMVP_VR_ON [33,48]

HDA_BITCLK

HDA_SDOUT

A

Pilot_05

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

LA-D991P

1

of

18 70Tuesday, November 08, 2016

of

18 70Tuesday, November 08, 2016

of

18 70Tuesday, November 08, 2016

0.1(X00)

5

4

3

2

1

UH2B

PCIE_RCOMPN PCIE_RCOMPP

L27

DMI_RXN0

N27

DMI_RXP0

C27

DMI_TXN0

B27

DMI_TXP0

E24

DMI_RXN1

G24

DMI_RXP1

B28

DMI_TXN1

A28

DMI_TXP1

G27

DMI_RXN2

E26

DMI_RXP2

B29

DMI_TXN2

C29

DMI_TXP2

L29

DMI_RXN3

K29

DMI_RXP3

B30

DMI_TXN3

A30

DMI_TXP3

B18

PCIE_RCOMPN

C17

PCIE_RCOMPP

H15

PCIE1_RXN/USB3_7_RXN

G15

PCIE1_RXP/USB3_7_RXP

A16

PCIE1_TXN/USB3_7_TXN

B16

PCIE1_TXP/USB3_7_TXP

B19

PCIE2_TXN/USB3_8_TXN

C19

PCIE2_TXP/USB3_8_TXP

E17

PCIE2_RXN/USB3_8_RXN

G17

PCIE2_RXP/USB3_8_RXP

L17

PCIE3_RXN/USB3_9_RXN

K17

PCIE3_RXP/USB3_9_RXP

B20

PCIE3_TXN/USB3_9_TXN

C20

PCIE3_TXP/USB3_9_TXP

E20

PCIE4_RXN/USB3_10_RXN

G19

PCIE4_RXP/USB3_10_RXP

B21

PCIE4_TXN/USB3_10_TXN

A21

PCIE4_TXP/USB3_10_TXP

K19

PCIE5_RXN

L19

PCIE5_RXP

D22

PCIE5_TXN

C22

PCIE5_TXP

G22

PCIE6_RXN

E22

PCIE6_RXP

B22

PCIE6_TXN

A23

PCIE6_TXP

L22

PCIE7_RXN

K22

PCIE7_RXP

C23

PCIE7_TXN

B23

PCIE7_TXP

K24

PCIE8_RXN

L24

PCIE8_RXP

C24

PCIE8_TXN

B24

PCIE8_TXP

SKY-H-PCH_BGA837

@

DMI_CTX_PRX_N0[7] DMI_CTX_PRX_P0[7]

D

C

LAN

NGFF

DMI_CRX_PTX_N0[7] DMI_CRX_PTX_P0[7]

DMI_CTX_PRX_N1[7] DMI_CTX_PRX_P1[7]

DMI_CRX_PTX_N1[7]

DMI_CRX_PTX_P1[7]

DMI_CTX_PRX_N2[7]

DMI_CTX_PRX_P2[7] DMI_CRX_PTX_N2[7] DMI_CRX_PTX_P2[7]

DMI_CTX_PRX_N3[7]

DMI_CTX_PRX_P3[7]

DMI_CRX_PTX_N3[7] DMI_CRX_PTX_P3[7]

1

RH108 100_0402_1%

PCIE_PRX_LANTX_N5[47]

PCIE_PRX_LANTX_P5[47]

PCIE_PTX_LANRX_N5[47]

PCIE_PTX_LANRX_P5[47]

PCIE_PRX_WLANTX_N6[43]

PCIE_PRX_WLANTX_P6[43]

PCIE_PTX_WLANRX_N6[43] PCIE_PTX_WLANRX_P6[43]

2

SKY-S-PCH_BGA837

DMI

PCIe/USB 3

2 OF 12REV = 1.3

USB 2.0

GPP_E9/USB2_OC0#

GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_F15/USB2_OCB_4 GPP_F16/USB2_OCB_5 GPP_F17/USB2_OCB_6

GPP_F18/USB2_OCB_7

USB2_COMP

USB2_VBUSSENSE

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9 USB2N_10 USB2P_10

USB2N_11 USB2P_11 USB2N_12

USB2P_12 USB2N_13 USB2P_13

USB2N_14 USB2P_14

RSVD_AB13

USB2_ID

GPD7/RSVD

AF5 AG7

AD5 AD7 AG8

AG10 AE1 AE2

AC2 AC3 AF2

AF3 AB3 AB2

AL8 AL7 AA1

AA2 AJ8 AJ7

W2 W3 AD3

AD2 V2 V1

AJ11 AJ13

AD43

AD42 AD39 AC44

Y43 Y41 W44

W43

AG3 AD10

AB13 AG2

BD14

USB_OC0#

USB_OC1#

USB_OC2#

USB_OC3# USB_OC4#

USB_OC5#

USB_OC6#

USB_OC7#

USB2_COMP

USB2_VBUSSENSE USB2_ID

USB20_N1 [46] USB20_P1 [46] USB20_N2 [45]

USB20_P2 [45]

USB20_N3 [49]

USB20_P3 [49]

USB20_N4 [43] USB20_P4 [43]

USB20_N7 [49] USB20_P7 [49]

USB20_N9 [34] USB20_P9 [34]

USB20_N12 [34]

USB20_P12 [34]

USB_OC0# [46]

USB_OC1# [45]

USB_OC2# [49]

1

RH109 113_0402_1%

1

RH112 1K_0402_5%

1

RH113 1K_0402_5%

USB Conn 1 USB Conn 2 USB Conn 3 (IO Board) Mini Card(WLAN)

Card Reader

Touch Screen

Camera

2

USB_OC3#

RH134 10K_0402_5%

USB_OC2#

RH135 10K_0402_5%

USB_OC1#

RH132 10K_0402_5%

USB_OC0#

RH131 10K_0402_5%

USB_OC5# USB_OC4#

USB_OC6#

USB_OC7#

1

RP8

4

3 2

1

10K_0804_8P4R_5%

D

+3VALW

2

+3VALW

5 6

7

8

C

UH2F

4

C11

USB3_1_TXN

B11

USB3_1_TXP

B7

USB3_1_RXN

A7

USB3_1_RXP

B12

USB3_2_TXN/SSIC_1_TXN

A12

USB3_2_TXP/SSIC_1_TXP

C8

USB3_2_RXN/SSIC_1_RXN

B8

USB3_2_RXP/SSIC_1_RXP

B15

USB3_6_TXN

C15

USB3_6_TXP

K15

USB3_6_RXN

K13

USB3_6_RXP

B14

USB3_5_TXN

C14

USB3_5_TXP

G13

USB3_5_RXN

H13

USB3_5_RXP

D13

USB3_3_TXP/SSIC_2_TXP

C13

USB3_3_TXN/SSIC_2_TXN

A9

USB3_3_RXP/SSIC_2_RXP

B10

USB3_3_RXN/SSIC_2_RXN

B13

USB3_4_TXP

A14

USB3_4_TXN

G11

USB3_4_RXP

E11

USB3_4_RXN

SKY-H-PCH_BGA837

@

USB3TN1[46]

B

USB Conn 1

USB Conn 2

USB Conn 3 ( IO Board)

A

5

USB3TP1[46]

USB3RN1[46] USB3RP1[46]

USB3TN2[46] USB3TP2[46]

USB3RN2[46] USB3RP2[46]

USB3TP3[49] USB3TN3[49] USB3RP3[49]

USB3RN3[49]

SKY-S-PCH_BGA837

LPC/eSPI

USB

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1

GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A6/SERIRQ

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_E6/DEVSLP2

GPP_E5/DEVSLP1 GPP_E4/DEVSLP0

6 OF 12REV = 1.3

GPP_F9/DEVSLP7

GPP_F8/DEVSLP6 GPP_F7/DEVSLP5 GPP_F6/DEVSLP4

GPP_F5/DEVSLP3

SATA

GPP_G19/SMI#

GPP_G18/NMI#

AT22 AV22

AT19 BD16

BE16

BA17

IRQ_SERIRQ

AW17

PIRQA#

AT17

SIO_RCIN#

BC18

T1

BC17

CLKOUT_LPC0

AV19

CLKOUT_LPC1

M45 N43

AE45

AG43 AG42 AB39

AB36 AB43 AB42

AB41

Security Classification

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

LPC_LAD0 [43,48] LPC_LAD1 [43,48]

LPC_LAD2 [43,48] LPC_LAD3 [43,48]

LPC_LFRAME# [43,48]

IRQ_SERIRQ [48]

SIO_RCIN# [48]

PAD~D

RH168 22_0402_5%

RH16 22_0402_5%

Issued Date

@

1

2

1

2

HDD_DEVSLP [44]

mSATA_DEVSLP [44]

2011/08/25 2012/07/25

CLK_PCI_LPC_MEC [48]

CLK_PCI_LPDEBUG [43,48]

Compal Secret Data

Deciphered Date

2

Reserve for RF

CLK_PCI_LPC_MEC

CLK_PCI_LPDEBUG

IRQ_SERIRQ SIO_RCIN#

PIRQA#

1

RH111 10K_0402_5%

1

RH87 10K_0402_5%

1

RH90 10K_0402_5%

1

2

EMC@12P_0402_50V8J

CC4

1

2

EMC@12P_0402_50V8J

CC5

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCH (4/8) PCI, USB

LA-D991P

+3VS

2

19 70Tuesday, November 08, 2016

1

19 70Tuesday, November 08, 2016

B

A

0.1(X00)

of

+3VS

RH14 5.1K_0402_1%@

RH15 5.1K_0402_1%@

RH10 10K_0402_5%

RH159 49.9K_0402_1%

RH160 49.9K_0402_1%

RH119 2.2K_0402_5%

RH120 2.2K_0402_5%

+3VALW

RH91 10K_0402_5%

D

C

5

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

I2C0_SCK

I2C0_SDA

SIO_EXT_SCI#

UART2_TXD UART2_RXD I2C1_SCK_TP

I2C1_SDA_TP

SIO_EXT_WAKE#

GPU_GC6_FB_EN[23]

+1.8V_GFX_AON

G

2

3

S

QV10 BSS138W 1N SOT-323-3

+3VS

1

RH517 100K_0402_5%

2

1

D

I2C1_SCK_TP[41]

I2C1_SDA_TP[41]

4

UH2K

BBS_BIT0

SIO_EXT_SCI#[48]

WLAN_WIGIG60GHZ_DIS#[43]

GPU_EVENT#[23]

BT_RADIO_DIS#[43]

HDMI_HPD_PCH[36]

SIO_EXT_WAKE#[48]

UART2_TXD[49] UART2_RXD[49]

SIO_EXT_SCI#

NRB_BIT

SIO_EXT_WAKE#

UART2_TXD UART2_RXD

I2C1_SCK_TP I2C1_SDA_TP

I2C0_SCK I2C0_SDA

AT29

GPP_B22/GSPI1_MOSI

AR29

GPP_B21/GSPI1_MISO

AV29

GPP_B20/GSPI1_CLK

BC27

GPP_B19/GSPI1_CS#

BD28

GPP_B18/GSPI0_MOSI

BD27

GPP_B17/GSPI0_MISO

AW27

GPP_B16/GSPI0_CLK

AR24

GPP_B15/GSPI0_CS#

AV44

GPP_C9/UART0_TXD

BA41

GPP_C8/UART0_RXD

AU44

GPP_C11/UART0_CTS#

AV43

GPP_C10/UART0_RTS#

AU41

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AT44

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AT43

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU43

GPP_C12/UART1_RXD/ISH_UART1_RXD

AN43

GPP_C23/UART2_CTS#

AN44

GPP_C22/UART2_RTS#

AR39

GPP_C21/UART2_TXD

AR45

GPP_C20/UART2_RXD

AR41

GPP_C19/I2C1_SCL

AR44

GPP_C18/I2C1_SDA

AR38

GPP_C17/I2C0_SCL

AT42

GPP_C16/I2C0_SDA

AM44

GPP_D4/ISH_I2C2_SDA

AJ44

GPP_D23/ISH_I2C2_SCL

SKY-H-PCH_BGA837

@

3

SKY-S-PCH_BGA837

11 OF 12REV = 1.3

GPP_D9 GPP_D10 GPP_D11

GPP_D16/ISH_UART0_CTS# GPP_D15/ISH_UART0_RTS#

GPP_D12

GPP_D14/ISH_UART0_TXD GPP_D13/ISH_UART0_RXD

GPP_H20/ISH_I2C0_SCL

GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL

GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5 GPP_A22/ISH_GP4 GPP_A21/ISH_GP3

GPP_A20/ISH_GP2 GPP_A19/ISH_GP1 GPP_A18/ISH_GP0

GPP_A17/ISH_GP7

AL44 AL36 AL35

AJ39 AJ43

AL43

AK44 AK45

BC38

BB38 BD38

BE39

BC22 BD18 BE21

BD22 BD21 BB22

BC19

Board_ID_14_15

KB_DET#

CLKDET#

2

IR_CAM_DET# [34]

DGPU_HOLD_RST# [23]

DGPU_PWR_EN [31,62]

KB_DET# [40]

DGPU_PWR_EN

KB_DET# CLKDET#

+3VALW

1

+3VS

14G0@

Board_ID_14_15

15G1@

SYSTEM ID

HIGH LOW

1

RH129 10K_0402_5%@

1

RH127 10K_0402_5%

1

RH128 10K_0402_5%

1

RH126 10K_0402_5%@

1

RH130 4.7K_0402_5%@

Boot BIOS Strap Bit (internal PD)

HIGH LOW(DEFAULT)

2

LPC SPI

1

RH494 10K_0402_5%

2

1

RH495 10K_0402_5%

2

14'' & N16P_GT 15'' & N16P_GX

2

BBS_BIT0

D

+3VS

+3VALW

C

+3VALW

1

RH92 4.7K_0402_5%@

B

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Title

PCH (5/8) GPIO, CPU, MISC

Size Document Number Rev

LA-D991P

Date: Sheet

2

NO REBOOT mode (internal PD)

HIGH LOW(DEFAULT)

Compal Electronics, Inc.

1

ENABLE DISABLE

20 70Tuesday, November 08, 2016

NRB_BIT

B

A

0.1(X00)

of

@

PJP1302

1

PAD-OPEN 43x39

5

+1V_PCH+1VALW

2

4

3

2

1

+1V_PCH_AZPLL

Close to AN19

0.1U_0402_10V6K

CH203

1

2

SKY-S-PCH_BGA837

CORE

MPHY

USB

REV = 1.3

+3VALW

@

0.1U_0402_10V7K

1

2

VCCGPIO

8 OF 12

CH190

VCCPRIM_1P0_AL22 VCCDSW_3P3_BA24

VCCPGPPA

VCCPGPPBH_BC42 VCCPGPPBH_BD40

VCCPGPPEF_AJ41 VCCPGPPEF_AL41

VCCPGPPG

VCCPRIM_3P3_AN5

VCCPRIM_1P0_AD15

VCCATS

VCCRTCPRIM_3P3

VCCRTC DCPRTC

VCCPRIM_1P0_AJ20 VCCPRIM_1P0_AJ21 VCCPRIM_1P0_AJ23

VCCPRIM_1P0_AJ25

VCCSPI_BE41

VCCSPI_BE43

VCCSPI_BE42

VCCPGPPCD_BC44

VCCPGPPCD_BA45

VCCPGPPCD_BC45

VCCPGPPCD_BB45

VCCPRIM_3P3_BD3

VCCPRIM_3P3_BE3 VCCPRIM_3P3_BE4

+1V_VCCDSW

Close to BA29

1U_0402_6.3V6K

CH176

1

2

+3V_PCH_DSW

@

AL22 BA24

BA31

BC42 BD40

AJ41 AL41 AD41

AN5

AD15 AD13

BA20 BA22 BA26

AJ20 AJ21 AJ23

AJ25

BE41

BE43

BE42

BC44

BA45

BC45 BB45

BD3

BE3 BE4

Close to W15

1U_0402_6.3V6K

CH82

1

2

0.0908A

+1V_PCH

+3V_PCH_DSW

+3VALW

+1V_PCH

+3VS

+3VALW

+3V_PCH_SPI

+3VALW

+3V_PCH_AZIO

Close to BA15

0.1U_0402_10V6K

CH200

1

2

+3VALW

Close to AN5Close to AD41 Close to AJ41,AL41Close to BC42,BD40

1

@

2

+RTCVCC

+DCPRTC

+1V_PCH_PRIM

0.1U_0402_10V7K CH189

0.403A

0.92089A

0.0061A

0.0066A

0.0002A

1

RH493 0_0603_5%@

0.0395A

0.0811A

+3VALW

@

+DCPRTC

0.1U_0402_10V6K

CH70

1

2

Pilot_05

1

2

0.1U_0402_10V7K CH192

Close to BA26

2.75835A

+3VALW

0.0121A

+3VS

Close to AD13

1U_0402_6.3V6K

CH188

1

2

+3VALW

0.1U_0402_10V7K

1

CH191

@

2

D

C

B

@

PJP70

@

1

D

+3VALW

+1V_PCH_PRIM

+1VALW

C

+1VALW

+3VALW

+1VALW

+1V_PCH_CLK5

JUMP_43X39

1

@

RH137 0_0603_5%

1

@

RH196 0_0402_5%

1

@

RH124 0_0603_5%

1

@

RH123 0_0603_5%

1

LH2 BLM15PX221SN1D_2P

1

LH1 BLM15PX221SN1D_2P

1

@

RH122 0_0603_5%

+1V_MPHY_MPHYPLL

Close to K2,K3 Close to A43,B43 Close to U21,U23

B

22U_0603_6.3V6M

1

2

1U_0402_6.3V6K

22U_0603_6.3V6M

CH179

1

CH177

CH178

@

2

+1V_MPHY

2

+3V_PCH_DSW

2

Pilot_05

+1V_VCCDSW

2

+1V_MPHY_MPHYPLL

2

+1V_PCH_USBPLL

2

Pilot_05

+1V_PCH_AZPLL

2

+3V_PCH_AZIO

2

+1V_PCH_CLK5

2

Pilot_05

+1V_MPHY

+1V_PCH_USBPLL

Close to AJ5,AL5

22U_0603_6.3V6M

1

@

2

1U_0402_6.3V6K

22U_0603_6.3V6M

CH180

1

CH181

CH182

@

2

10U_0402_6.3V6M

1

2

1U_0402_6.3V6K

CH184

CH185

CH183

1

2

22U_0603_6.3V6M

1

CH202

CH201

@

2

2.75835A

+1VALW

0.0248A

1

PAD-OPEN 43x39

0.0454A

0.0348A

0.0046A

3.53A

+1V_MPHY_MPHYPLL

0.095A

0.533A

+1V_PCH_USBPLL

0.075A

PJP1303

2

+1V_VCCDSW

+1V_PCH

+1V_PCH_CLK5

+1V_MPHY

+1V_PCH

+1V_PCH_AZPLL

+3V_PCH_AZIO

+3V_PCH_DSW

+1V_PCH_PRIM

UH2H

AA23

VCCPRIM_1P0_AA23

AA26

VCCPRIM_1P0_AA26

AA28

VCCPRIM_1P0_AA28

AC23

VCCPRIM_1P0_AC23

AC26

VCCPRIM_1P0_AC26

AC28

VCCPRIM_1P0_AC28

AE23

VCCPRIM_1P0_AE23

AE26

VCCPRIM_1P0_AE26

Y23

VCCPRIM_1P0_Y23

Y25

VCCPRIM_1P0_Y25

BA29

DCPDSW_1P0

N17

VCCCLK1

R19

VCCCLK3

U20

VCCCLK4

V17

VCCCLK2

R17

VCCCLK6

K2

VCCCLK5_K2

K3

VCCCLK5_K3

U21

VCCMPHY_1P0_U21

U23

VCCMPHY_1P0_U23

U25

VCCMPHY_1P0_U25

U26

VCCMPHY_1P0_U26

V26

VCCMPHY_1P0_V26

A43

VCCMPHYPLL_1P0_A43

B43

VCCMPHYPLL_1P0_B43

C44

VCCPCIE3PLL_1P0_C44

C45

VCCPCIE3PLL_1P0_C45

V28

VCCAPLLEBB_1P0

AC17

VCCPRIM_1P0_AC17

AJ5

VCCUSB2PLL_1P0_AJ5

AL5

VCCUSB2PLL_1P0_AL5

AN19

VCCHDAPLL_1P0

BA15

VCCHDA

W15

VCCDSW_3P3_W15

SKY-H-PCH_BGA837

@

+RTCVCC

+3VALW

Close to BA22 Close to BA20

1U_0402_6.3V6K

0.1U_0402_10V6K

1U_0402_6.3V6K

CH173

CH80

1

2

A

5

0.1U_0402_10V6K

CH187

CH186

1

2

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCH (6/8) PWR

LA-D991P

1

of

21 70Tuesday, November 08, 2016

of

21 70Tuesday, November 08, 2016

of

21 70Tuesday, November 08, 2016

0.1(X00)

Dell Inspiron 15 Gaming 7567 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual