Dell Inspiron 15 5575 Schematics

5

PROJECT NAME : CAL51/CLA61/CAL71
P

CB NO :

4

3

2

1

D D

Dell / Compal Confidential

Schematic Document

AMD Raven
AMD R17M-M2-50 (23 X 23mm)+GDDR5 x4

C C

B B

2017-11-09 Rev: 1.00 (A00)

@ : Un-pop Component
R5_PC@/R7_PC@/R3_PC/R5_PR@/R7_PR@/R5_PR_R3@/R7_PR_R3@:APU PN
45@: HDMI LOGO
PCB@/: MB part number
4G_S@/4G_M@/4G_H@/2G_H@/2G_M@/2G_S:
VRAM Strap Pin:
Vram 2G:S2G_R3@ / H2G_R3@ /M2G_R3@
Vram 4G:S4G_R3@ / H4G_R3@ /M4G_R3@
DIS@: GPU only
M50_R3@:GPU R3 PN
UMA@/:UMA only
TI@/PARADE@/NRDSA@ : SATA
3234@ :Audio
EMI@/ESD@/RF@ : EMI, ESD ,RF Component
@EMI@/@ESD@/@RF@ : EMI, ESD,RF unpop
KBBL@:for KB backlight use
PTP@/NPTP@/TP_WAKE@:Touch pad
TYPEC@/NOTYPEC@:TYPEC

@EMI@/Tyepc@ESD@: EMI/ESD typec component

A A

Typec

CRT@:D-sub TPM@:TPM FFS@:free fall sensor
HDT@ /Debug use
MODS@:moderd standby

curity Classification Compal Secret Data

curity Classification Compal Secret Data

curity Classification Compal Secret Data

Se

Se

Se

ed Date

ed Date

ed Date

Issu

Issu

Issu

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

TH

TH

TH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

16/01/07 2017/01/07

16/01/07 2017/01/07

16/01/07 2017/01/07

20

20

20

Deciphered Date

Deciphered Date

Deciphered Date

2

Title

Ti

Ti

Size Document Number Re v

Size Document Number Re v

Size Document Number Rev

Date : Sheet

Date : Sheet

Date: Sheet of

tle

tle

Cover Page

Cover Page

Cover Page

LA

LA

LA

mpal Electronics, Inc.

mpal Electronics, Inc.

mpal Electronics, Inc.

Co

Co

Co

-F121P

-F121P

-F121P

1

1 61Thursday, November 09, 2 017

1 61Thursday, November 09, 2 017

1 61Thursday, November 09, 2 017

of

of

3(X02)

3(X02)

3(X02)

0.

0.

0.

5

D D

AM 256M*16

VR
GDDR5 *4

Page 43,44

Page 43,44

Page 43,44Page 43,44

n IO/B

O

Realtek
RTD2166

C C

B B

UB-BOARDS

S

A A

I/O BOARD

4bit

6

MD R17M-M2-50

A

FCBGA631

25W 23x23mm

DP Conn.

e

H

arade

P
PS8330B

ort 0

P

SD

S

EN3 GEN1 GEN1

G

x

age 34

Page 34

P

Page 34Page 34

C

4

age 38~42

Page 38~42

P

Page 38~42Page 38~42

Page 16

Page 16

Page 16Page 16

DMI Conn.

Page 17

Page 17

Page 17Page 17

RT (Reserve)

age 36

Page 36

P

Page 36Page 36

NGFF 2230

iFi/BT4.0

W

ATA HDD Conn.

S

ATA ODD Conn.

S

x

Page 22

Page 22

Page 22Page 22

age 22

Page 22

P

Page 22Page 22

POWER BOARD

RT BOARD(Reserve)

nterposer board(M2_Sata)

i

5

C

4

EG 3.0 x4

P

DP0

P1

D

P2

D

1

Ethernet

R

(

Page 20

Page 20 Page 19

Page 20Page 20

ort 0

P

ort 1

P

PM 650

T

Reserve)

(

Page 10

Page 10

Page 10Page 10

DD BOARD

O

DP

e

DI

D

DI

D

CI-E

P

1

x

ort 4Port 5

P

TL8106E/RTL8111H(reserve)

10/100) default/1000

Page 19

Page 19Page 19

(Reserve)

FFS

age 22

Page 22

P

Page 22Page 22

ATA Rediver

S

Page 22

Page 22

Page 22Page 22

TPM 750

Reserve)

(

Page 10

P

Page 10Page 10

PI ROM

S

28Mb

1

Page 10

Page 10

Page 10Page 10

nt.KBD

I

ith KBBL

w

4

3

emory Bus

M

SB 3.1(GEN1)/DP(1.2)

U

P1.2

D

MD

HDMI1.4

A
Ravenl
Proces sor
BGA 1140

P1.2

D

MBUS

S

ATA3.0

S

ATA1.0

S

age 10

PI

S

2C to EC

I

E

Page 24 Page 24

Page 24Page 24

KB9022QD

LPC Bus

3MHz

3

NE KBC

Page 27

Page 27Page 24

Page 27Page 27

Page 6~12

Page 6~12

Page 6~12Page 6~12

PS/2

U

SB 3.0

U

SB2.0

U

2C

I

SB2.0

D Audio

H

ouch Pad

T

FAN CONN

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

3

upport two CHs

400M HZ

s

2

USB544

T

age 33

Page 33

P

Page 33Page 33

sb 2.0 mux

u

age 32

Page 32

P

Page 32Page 32

CG4

C

Page 31

Page 31

Page 31Page 31

1_Port 0

USB 2.0 Conn.3

_Port 1

1

2C

I

Page 24

Page 24Page 24

hermal Sensor

T

2

2

2

SB 2.0 HUB IC

U

Audio Codec

LC3234(def ault)

A

age 24

Page 24

P

Page 24Page 24

age 28

Page 28

P

Page 28Page 28

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

016/01/07 2017/01/07

016/01/07 2017/01/07

016/01/07 2017/01/07

eciphered Date

eciphered Date

eciphered Date

D

D

D

2

Digital Mic.

Page 18

Page 18

Page 18Page 18

2

DR4-DIMM X2

D

I2C to EC

0

On IO/B

age 25

Page 25

P

Page 25Page 25

Page 35

P

Page 35Page 35

.2V DDR4

1

_Port 0

0

_Port 0

0

_Port 1

0

0_Port 1

_Port 2

0

0_Port 2

_Port 3

age 35

Page 13~14

Page 13~14

Page 13~14Page 13~14

SB 3.0 TYPEC

U

USB 2.0

USB 3.0 Conn.1
USB 2.0 Conn.1

SB 3.0 Conn.2

U
USB 2.0 Conn.2

Page 32

Page 32

Page 32Page 32

Page 23

Page 23

Page 23Page 23

Page 23

Page 23

Page 23Page 23

Digital Camera

(With Digital MIC)

ard Reader

C

R

Touch Screen

NGFF 2230

W

Finger Printer

Headphone Jack /

Mic. Jack com bo

n IO/B

O

nt. Speaker R / L

I

itle

itle

itle

T

T

T

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheetof

Date : Sheetof

Date : Sheetof

TS517 0

iFi/BT4.0

Page 21

Page 21

Page 21Page 21

Page 18

Page 18

Page 18Page 18

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

Block diagram

Block diagram

Block diagram

A-F121P

A-F121P

A-F121P

L

L

L

Page 16

Page 16

Page 16Page 16

n IO/B

O

Page 25

Page 25

Page 25Page 25

Page 16

Page 16

Page 16Page 16

Page 35

Page 35

Page 35Page 35

1

Page 20

Page 20

Page 20Page 20

1

2 61Thursday, November 09, 2 017

2 61Thursday, November 09, 2 017

2 61Thursday, November 09, 2 017

.3(X02)

.3(X02)

.3(X02)

0

0

0

5

latform Power Sequence

P

LA-F121P

017/02/03

2

D D

C

A
MO DE

C

D
MODE

C C

B B

A1

19V_ADPIN

+

+

PUB01

SL9538HRTZ-T

I

17.4V_BATT+

+

B1

17.4V_BATT+A3PQB03

1

APU_PWRGD

CIN

A

9

1

AON7409

L1

U
RTL8106E-C G

-LAN CTRL

E

0c

A2

H1

D

B5

A3

9

A2

U300

P

PS51285BRUKR

T

19VB

+

2

B

19VB

+

PU_PWRGD_BUF

A

OK

P

3,13

6,20

A4

10d

LAN_PWR_SAVE#

4

+3VALW

B5

+5VALW

A2

4

B

+3VLP,VL

A5

B7

C_ON

E

B6

ON/OFF

LT_RST#

P

DGPU_PWROK

HDT1@

J
Debug connector

I1 SY6288D20AAC

U

5V_USB_PWR1

+

4

3

110

112

14

1

3

1

8

1

726

1

21

1

R_ON
V

9

8

USB_EN#

4

8

E1

U
KB9022QD

4

7

1

GATE
V

d

9

8

.95VS_PWR_ EN#
0

9

9

9

16

SUSP#

9

4 AO4354

U
+0.95Valw-> +0.95VS

U
+3ALW->+LAN_VDD33

OL_EN
W

32

8

9

100

22

1

6

4

1

2

127

5

7

4, EM5209VF

U
+5VS

U6, EM5209VF
+3VS

RZ19

P

c

9

3

L2 SY6288C20AAC

V

c

9

PU_FCH_POK

A

0

1

4

a

6

.95_1.8VALW_PWREN

0

NABLE_APU

E

PU_PWRGD

A

GATE

8a

5

2

b

8

KB_RST#

8

9

1

PU_FCH_PWRGD _R

A

ND

A

UC3

EC_RSMRST#

6

A

PUZ01
ISL62771HRTZ -T

WROK

P

PGOOD

3

TC_CLK

R

0a

BTN_OUT#

P

PM_SLP_S3#

PM_SLP_S5#

APU_RST#

PU_PWRGD

10b

+APU_CORE

+

VGATE

20

W14

A

V6

A

AT16

R15

A

AV13

T14

A

BB11

W4

A

15

D

0d

1

W2

A

H1

A

APU_CORE_NB

D11

B

P
LT_RST#

1

9

PU

A
U1 FP5

D5

B

0c

a

9d

2

W15

A

D15

B

W16

A

P

PU_PCIE_RST#

A

b

9

XS_PWREN

P

11

XS_RST#

WRGD_VGA

P

12

2a

1

8

5
U4&U6 EM 5209VF

USP#

S

DGPU_PWR_EN

ND Gate

A

U3(DIS@)
EM5209VF
CH1 +0.95V SDGPU
CH2 +1.8VGS

VS and 3VS

8

PUV01
ISL62771HRTZ-T

9

WROK

P

PWRGD_VGA

LT_RST_VGA#

P

U
D

1

8c

PGOOD

G1 AU29
GPUUV2

WRGD_VGA

P

0

2

PRV20

DGPU_PWROK

12a

2a

1

A A

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF E NGINEERING DRAWING IS THE PROPRIETARY P ROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFID ENTIAL

HIS SHEET OF E NGINEERING DRAWING IS THE PROPRIETARY P ROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFID ENTIAL

HIS SHEET OF E NGINEERING DRAWING IS THE PROPRIETARY P ROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFID ENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELEC TRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELEC TRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELEC TRONICS, INC.

3

016/01/07 2017/01/07

016/01/07 2017/01/07

016/01/07 2017/01/07

2

2

2

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

Deciphered Date

Deciphered Date

Deciphered Date

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

itle

itle

itle

T

T

T

Power Sequence diagram

Power Sequence diagram

Power Sequence diagram

ize

ocument Numb er Re v

ize

ocument Numb er Re v

ize

ocument Numb er Re v

S

D

S

D

S

D

A-F121P

A-F121P

A-F121P

L

L

L

Date: Sheetof

Date: Sheetof

2

Date: Sheetof

1

0

0

0

3 61Thursday, November 09, 2017

3 61Thursday, November 09, 2017

3 61Thursday, November 09, 2017

.3(X02)

.3(X02)

.3(X02)

5

oard ID Table for AD channel

B

Vcc 3.3V +/- 1%

100K +/- 1%Ra

oard ID

B

0
1
2
3
4
5
6

D D

C C

7 56K +/- 1%
8
9
1
11
12
13
14
15 33 0K + /- 1%
16
17
18
19 N C

SMBUS Control Table

EC_SMB_CK 1
EC_SMB_DA 1

EC_SMB_CK 2
EC_SMB_DA 2

EC_I2C_TPC LK
EC_I2C_TPD AT

PU_SCLK0

A
APU_SDATA 0

APU_SCLK1
APU_SDATA 1

APU_SIC
APU_SID

Rb V m in

0 0.000 V
12K +/- 1%
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%

75K +/- 1% 1. 398V
100K +/- 1%

0

160K +/- 1%
200K +/- 1%
240K +/- 1%
270K +/- 1%

30K +/- 1%

4
560K +/- 1%
750K +/- 1%

SOURCE

KB9022Q

KB9022Q

KB9022Q

APU

PU

A

APU

D_BI D

A

0.347 V

0.423 V 0.430 V

0.541 V

0.691 V

0.807 V

0.978 V 0.992 V

1.169 V

1.634 V

1.849 V 1.865 V

2.015 V

2.185 V

2.316 V

2.395 V 2.408 V

2.521 V

2.667 V

2.791 V

2.905 V 2.912 V

3.000 V

ATT

harger

B

C

V

V

DIMM

V

hermal

T
Sensor

CLKOUT_PCIE0

Note :

Symbol

: means Digital Ground

: means Analog Ground

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

4

typ

V

D_BI D

A

0.000 V 0.300 V

0.354 V

0.550 V

0.702 V

0.819 V

1.185 V

1.414 V 1.430 V

1.650 V

2.031 V

2.200 V

2.329 V

2.533 V

2.677 V

2.800 V

3.300 V

FS CRT

F

V

A

D_BI D

0.360 V

0.438 V

0.559 V

0.713 V

0.831 V

1.006 V

1.200 V

1.667 V

1.881 V130K +/- 1%

2.046 V

2.215 V

2.343 V

2.421 V

2.544 V

2.687 V

2.808 V

2.919 V

3.300 V

V

V

V

V

CLOCK SIGNAL

dGPU

0/100 LAN(GIGA RESERVE)

1

NGFF Card (WLAN)

NVME SSD

m

ax

EC AD3

x00 - 0x13

0
0x14 - 0x1E
0x1F - 0x25
0x26 - 0x30
0x31 - 0x3A
0x3B - 0x45
0x46 - 0x54
0x55 - 0x64

x65 - 0x76

0
0x77 - 0x87
0x88 - 0x96
0x97 - 0xA4
0xA5 - 0xAF

xB0 - 0xB7

0
0xB8 - 0xBF
0xC0 - 0xC9
0xCA - 0xD4
0xD5 - 0xDD
0xDE - 0xF0
0xF1 - 0xFF

3

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7
8
9
10
11

2

1
13
14
15
16
17
18
19

PCI EXPRESS(GFX)

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8

Raven EVT UMA

aven EVT DIS

R

aven DVT1 UMA

R
Raven DVT1 DIS
Raven DVT2 UMA
Raven DVT2 DIS

aven Pilot UMA

R

Raven Pilot DIS

(AMD)M2-50

PEG

(AMD)M2-50

PEG

PEG (AMD)M2-50

PEG (AMD)M2-50

RV2 NA

RV2 NA

RV2 NA

RV2 NA

2

V2 NA

R

RV2 NA

LT

U

RV2 NA

RV2 NA

RV2 Sata only

RV2 Sata only

_Port0

0

_Port1

0

0_Port2

0_Port3

1_Port0

1_Port1

_Port0

0

0_Port1

0_Port2

0_Port3

1_Port0

1_Port1

ane 1

L

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8

ATA0

S

SATA1

1

USB3.0

YPE C

T

USB3 connector 1

SB3 connector 2

U

progaming DP signal

SB2.0

U

YPE C

T

SB connector 1

U

SB connector 2

U

amera

C

USB connector 1(D/B)

USB HUB

PCI EXPRESS(GPP)

NVME SSD

NVME SSD

VME SSD

N

NVME SSD

10/100 LAN(GIGA RESERVE)

GFF Card (WLAN)

N

use sata interface

use sata interface

SATA

DD

H

DD

O

B B

oltage Rails

V

dapter power supply

SDC_IN

+
+17.4V_BATT++
+19VB

APU_VDDCORE

+
+APU_VDDSOC VDDSOC voltage for APU

3VALW_APU 3V_always for APU

+

0.8VALW_APU ON*

+
+1.8V_ALW_APU

0.8VS

+

+VGA_CORE

1.35V_MEM_GFX +1.35VS power rail for G PU and VRAM

+

3VGS

+

+0.95VSDGPU 0.95V power rail for GPU

+3.3V_VDD_PIC
+3VALW System +3VALW always on power rail

3VLP

+

3VS

+

+0.6V_DDR_VTT

2.5V_MEM

+

A A

1.8VS System +1.8VS power rail

+

5VALW

+

5VS System +5VS power rail

+

RTCVCC RTC power

+

A

at t ery po wer s uppl y

B

AC or DC for power circuit

ore voltage for APU

C

0.8V_always for APU
.8V_always for APU

1

.8V_sustain for APU

0

GA core power rail for GPU

V

1.8VS power rail for G PU+1.8VGS

+

.3V power rail for PD chip

3

19VB to +3VLP power rail for suspend power

+

ystem +3VS power rail

S

DR +0.6VS power rail for DDR terminator

D

DR4/L-RS +1.2V power rail+1.2V_DDR

D
DR4/L-RS +2.5V power rail

D

ystem +5VALW power rail

S

S0 S3 S4/S5Power Plane De script i on

N
N/A
N/A

ON
ON
ON
O
ON
O
ON
ON
ON
O
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON

N/A

/A

/A

N

N/A

N/A

N/A

N/A

OFF

OFF

OFF

OFF

N*

N

O

O
ON

N

N

N

ON

FF OFF

O
OFF

FF

O
OFF

OFF
OFF

N

O
ON

FF OFF

O

FF

O

N

O
ON

OFF

N

O

FF

O

N

O

ON*

OFF
O
OFF+3VS power rail for G PU
O
O

O
ON*
O

OFF
O
OFF
OFF

ON*

OFF

O

FF

FFOFF
FF

N*

N

FF

N

Note : ON* means that this power plane is ON on ly with AC power available, otherwise it is OFF

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUTPRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUTPRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUTPRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

016/01/07 2017/01/07

016/01/07 2017/01/07

016/01/07 2017/01/07

2

2

2

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

Deciphered Date

Deciphered Date

Deciphered Date

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

itle

itle

itle

T

T

T

Notes List

Notes List

Notes List

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

LA-F121P

LA-F121P

LA-F121P

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

1

0.3(X02)

0.3(X02)

0.3(X02)

4 61Thursday, November 09, 2017

4 61Thursday, November 09, 2017

4 61Thursday, November 09, 2017

5

MBus Block Diagram

S

RPC64

RPC64

PU_SCLK0

A

BC20

PU_SDATA0

A

BA20

D D

RP4.2

aven

R

C C

A

AT13

H

J14

R13

14

+

PC3.1

R

PU_SIC

A

APU_SID

2C_3_SCL

I

I2C_3_SDA

3VS

K
1

RC24

EC_SMB_CK2

9

7

80

_SMB_DA2

EC

B B

RP4.1

RPC3.3

1K

N-MOS

N-MOS

QC2

3VS

+

RC25

2.2K

2.2K

.2K

2

2.2K

.2K

2

2.2K

EC_SMB_CK2

EC_SMB_DA2

4

3VS

+

3VS_T OUC H

+

EC_SMB_CK2

EC_SMB_DA2

J

Q11

N-MOS

N-MOS

3

TP

3VS

+

31

R

K

R32

1

1K

QV1

N-MOS

N-MOS

8

8 thermal sensor

U

7

RV5DIS@

RV6DIS@

45.3K

5.3K

4

GA_SMB_CK3

V

VGA_SMB_DA3

+

3VGS

2

253

DIMM1

54

2

253

DIMM2

254

1

FFS

4

2

1

CRT

J

11

U7

V1

U

PU

G

U8

1

BC

K
KB9022QD

.2K

RE509

2

3VAL W

+

2.2K

RE510

77

8

7

A A

5

EC_SMB_CK1

EC_SMB_DA1

4

PR770

0 ohm

0 ohm

PR769

PR20

100 ohm

100 ohm

PR18

LK_SMB

C

DAT_SMB

4

CL

S

U703

P

WER

PO

A

SD

harger

3

3

C

6

5

ATT

ATT1

B

PB

ONN

C

ecurity Classification

ecurity Classificati on

ecurity Classificati on

S

S

S

Issued Date

Issued Date

Issued Date

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

2

2

2

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

016/01/07 2017/01/07

016/01/07 2017/01/07

016/01/07 2017/01/07

Deciphered Date

Deciphered Date

Deciphered Date

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

DELL CONFIDENTIAL/PROPRIETARY

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

itle

itle

itle

T

T

T

SMBus block diagram

SMBus block diagram

SMBus block diagram

ize

ocument Number Rev

ize

ocument Number Re v

ize

ocument Number Re v

S

D

S

D

S

D

A-F121P

A-F121P

A-F121P

L

L

L

Date: Sheetof

Date: Sheetof

Date: Sheetof

5 61Thursday, Nov ember 09, 2017

5 61Thursday, Nov ember 09, 2017

5 61Thursday, Nov ember 09, 2017

1

.3(X02)

.3(X02)

.3(X02)

0

0

0

ain Func = CPU

M

5

4

3

2

1

D D

EG_ARX_GTX_P[3..0][38]

P

EG_ARX_GTX_N[3..0][38]

P

CIE_ARX_DTX_P[3..0][34]

P

CIE_ARX_DTX_N[3..0][3 4]

C C

CHANGE LAN/WLAN NET NAME @2/23

B B

A A

P

C1

U

A0000BBJ0L

S

3_PC@

R

IC RAVEN3 ZM2300C4T2OFB 2G BGA 1140 APU

S

C1

U

A0000ASA2L

S

7_PC@

R

IC RAVEN7 ZM2000C4T4MF2 2G BGA 1140 APU

S

C1

U

A0000A8R0L

S

5_PC@

R

IC RAVEN5 ZM1800C4T4MF2 1.8G BGA 1140 APU

S

5

H

ODD

AN

L

WLAN

DD

HANGE PEG NET NAME @2/23

C

PEG

EG_ARX_GTX_P[3..0]

P

EG_ARX_GTX_N[3..0]

P

CHANGE SSD NET NAME @2/23

CIE_ARX_DTX_P[3..0]

P

CIE_ARX_DTX_N[3..0]

P

ATA_ARX_DTX_P0[22]

S

ATA_ARX_DTX_N0[22]

S

ATA_ARX_DTX_P1[22]

S

ATA_ARX_DTX_N1[22]

S

EG_ARX_GTX_P0

P

EG_ARX_GTX_N0

P

EG_ARX_GTX_P1

P

EG_ARX_GTX_N1

P

EG_ARX_GTX_P2

P

EG_ARX_GTX_N2

P

EG_ARX_GTX_P3

P

EG_ARX_GTX_N3

P

CIE_ARX_DTX_P0

P

CIE_ARX_DTX_N0

P

CIE_ARX_DTX_P1

P

CIE_ARX_DTX_N1

P

CIE_ARX_DTX_P2

SSD

CIE_ARX_DTX_P4[19]

P

CIE_ARX_DTX_N4[19]

P

CIE_ARX_DTX_P5[20]

P

CIE_ARX_DTX_N5[20]

P

P

CIE_ARX_DTX_N2

P

CIE_ARX_DTX_P3

P

CIE_ARX_DTX_N3

P

C1

U

A0000BBJ1L

S

3_PR@

R

IC RAVEN3 YM2200C4T2OFB 2.5G BGA 1140 APU

S

C1

U

A0000ASA3L

S

7_PR@

R

IC RAVEN7 YM2700C4T4MFB 2G BGA 1140 APU

S

C1

U

A0000A8R1L

S

5_PR@

R

IC RAVEN5 YM2500C4T4MFB 1.8G BGA 1140 APU

S

4

8

P

P

9

P

P

6

N

P

7

N

P

8

M

P

9

M

P

6

L

P

7

L

P

11

K

P

11

J

P

6

H

P

7

H

P

6

G

P

7

F

P

8

G

P

8

F

P

10

N

P

9

N

P

10

L

P

9

L

P

12

L

P

11

M

P

12

P

P

11

P

P

6

V

P

7

V

P

8

T

P

9

T

P

6

R

P

7

R

P

9

R

P

10

R

P

@

_GFX_RXP0

_GFX_RXN0

_GFX_RXP1

_GFX_RXN1

_GFX_RXP2

_GFX_RXN2

_GFX_RXP3

_GFX_RXN3

_GFX_RXP4

_GFX_RXN4

_GFX_RXP5

_GFX_RXN5

_GFX_RXP6

_GFX_RXN6

_GFX_RXP7

_GFX_RXN7

_GPP_RXP0

_GPP_RXN0

_GPP_RXP1

_GPP_RXN1

_GPP_RXP2

_GPP_RXN2

_GPP_RXP3

_GPP_RXN3

_GPP_RXP4

_GPP_RXN4

_GPP_RXP5

_GPP_RXN5

_GPP_RXP6/SATA_RXP0

_GPP_RXN6/SATA_RXN0

_GPP_RXP7/SATA_RXP1

_GPP_RXN7/SATA_RXN1

UC1B

PCIE

FP5 REV 0.90

ART 2 OF 13

P

P5_BGA1140~D

F

C1

U

A0000ASA4L

S

7_PR_R3@

R

IC RAVEN7 YM2700C4T4MFB 2.2G BGA 1140 APU A31 !

S

C1

U

A0000A8R2L

S

5_PR_R3@

R

IC RAVEN5 YM2500C4T4MFB 2G BGA 1140 APU A31 !

S

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF E NGINEERING DRAWING IS THE PROPRIETARY P ROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFID ENTIAL

HIS SHEET OF E NGINEERING DRAWING IS THE PROPRIETARY P ROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFID ENTIAL

HIS SHEET OF E NGINEERING DRAWING IS THE PROPRIETARY P ROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFID ENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELEC TRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELEC TRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELEC TRONICS, INC.

3

1

N

_GFX_TXP0

P

3

N

_GFX_TXN0

P

2

M

_GFX_TXP1

P

4

M

_GFX_TXN1

P

2

L

_GFX_TXP2

P

4

L

_GFX_TXN2

P

1

L

_GFX_TXP3

P

3

L

_GFX_TXN3

P

2

K

_GFX_TXP4

P

4

K

_GFX_TXN4

P

2

J

_GFX_TXP5

P

4

J

_GFX_TXN5

P

1

H

_GFX_TXP6

P

3

H

_GFX_TXN6

P

2

H

_GFX_TXP7

P

4

H

_GFX_TXN7

P

CIE_ATX_DRX_P0

P

2

N

_GPP_TXP0

P

_GPP_TXN0

P

_GPP_TXP1

P

_GPP_TXN1

P

_GPP_TXP2

P

_GPP_TXN2

P

_GPP_TXP3

P

_GPP_TXN3

P

_GPP_TXP4

P

_GPP_TXN4

P

_GPP_TXP5

P

_GPP_TXN5

P

_GPP_TXP6/SATA_TXP0

P

_GPP_TXN6/SATA_TXN0

P

_GPP_TXP7/SATA_TXP1

P

_GPP_TXN7/SATA_TXN1

P

016/01/07 2017/01/07

016/01/07 2017/01/07

016/01/07 2017/01/07

2

2

2

3

P

4

P

2

P

3

R

1

R

4

T

2

T

2

W

4

W

3

W

2

V

1

V

3

V

2

U

4

U

CIE_ATX_DRX_N0

P

CIE_ATX_DRX_P1

P

CIE_ATX_DRX_N1

P

CIE_ATX_DRX_P2

P

CIE_ATX_DRX_N2

P

CIE_ATX_DRX_P3

P

CIE_ATX_DRX_N3

P

CIE_ATX_DRX_P4

P

CIE_ATX_DRX_N4

P

CIE_ATX_DRX_P5

P

CIE_ATX_DRX_N5

P

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

CIE_ATX_DRX_P[3..0]

P

CIE_ATX_DRX_N[3..0]

P

lace near UC1

p

C1 .1U_0402_16V7K

C

1 2

C2 .1U_0402_16V7K

C

1 2

C3 .1U_0402_16V7K

C

1 2

C4 .1U_0402_16V7K

C

1 2

Deciphered Date

Deciphered Date

Deciphered Date

2

EG_ATX_GRX_P0

P

EG_ATX_GRX_N0

P

EG_ATX_GRX_P1

P

EG_ATX_GRX_N1

P

EG_ATX_GRX_P2

P

EG_ATX_GRX_N2

P

EG_ATX_GRX_P3

P

EG_ATX_GRX_N3

P

PEG

EG_ATX_GRX_P[3..0]

P

EG_ATX_GRX_N[3..0]

P

CIE_ATX_DRX_P[3..0] [34]

P

CIE_ATX_DRX_N[3..0] [34]

P

SSD

CIE_ATX_C_DRX_P4 [19]

P

CIE_ATX_C_DRX_N4 [19]

P

CIE_ATX_C_DRX_P5 [20]

P

CIE_ATX_C_DRX_N5 [20]

ATA_ATX_DRX_P0 [22]

S

ATA_ATX_DRX_N0 [22]

S

ATA_ATX_DRX_P1 [22]

S

ATA_ATX_DRX_N1 [22]

S

P

HDD

ODD

itle

itle

itle

T

T

T

F

F

F

ize

ocument Numb er Re v

ize

ocument Numb er Re v

ize

ocument Numb er Re v

S

D

S

D

S

D

ustom

ustom

ustom

C

C

C

A-F121P

A-F121P

A-F121P

L

L

L

Date: Sheetof

Date: Sheetof

Date: Sheetof

EG_ATX_GRX_P[3..0] [38]

P

EG_ATX_GRX_N[3..0] [38]

P

AN

L

WLAN

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

P4 PCIE/UMI

P4 PCIE/UMI

P4 PCIE/UMI

1

0

0

0

6 61Thursday, November 09, 2017

6 61Thursday, November 09, 2017

6 61Thursday, November 09, 2017

.3(X02)

.3(X02)

.3(X02)

ain Func = CPU

M

D D

C C

B B

5

DR_A_MA[13..0][13]

D

DR_A_MA0

D

DR_A_MA1

D

DR_A_MA2

D

DR_A_MA3

D

DR_A_MA4

D

DR_A_MA5

D

DR_A_MA6

D

DR_A_MA7

D

DR_A_MA8

D

DR_A_MA9

D

DR_A_MA10

D

DR_A_MA11

D

DR_A_MA12

D

DR_A_MA13

D

DR_A_MA14_WE#[13]

D

DR_A_MA15_CAS#[13]

D

DR_A_MA16_RAS#[13]

D

DR_A_BA0[13]

D

DR_A_BA1[13]

D

DR_A_BG0

D

DR_A_BG1

D

DR_A_BG0[1 3]

D

DR_A_BG1[1 3]

D

DR_A_ACT#

D

DR_A_ACT#[13]

D

DR_A_DM0

D

DR_A_DM[7..0][13]

D

DR_A_DM1

D

DR_A_DM2

D

DR_A_DM3

D

DR_A_DM4

D

DR_A_DM5

D

DR_A_DM6

D

DR_A_DM7

D

DR_A_DQS0[13]

D

DR_A_DQS0#[13]

D

DR_A_DQS1[13]

D

DR_A_DQS1#[13]

D

DR_A_DQS2[13]

D

DR_A_DQS2#[13]

D

DR_A_DQS3[13]

D

DR_A_DQS3#[13]

D

DR_A_DQS4[13]

D

DR_A_DQS4#[13]

D

DR_A_DQS5[13]

D

DR_A_DQS5#[13]

D

DR_A_DQS6[13]

D

DR_A_DQS6#[13]

D

DR_A_DQS7[13]

D

DR_A_DQS7#[13]

D

DR_A_CLK0[13]

D

DR_A_CLK0#[13]

D

DR_A_CLK1[13]

D

DR_A_CLK1#[13]

D

DR_A_CS0#[13]

D

DR_A_CS1#[13]

D

DR_A_CKE0[13]

D

DR_A_CKE1[13]

D

DR_A_ODT0[13]

D

DR_A_ODT1[13]

D

DR_A_ALERT#[13]

D

DR_A_EVENT#[13]

D

DR_A_RST#[13]

D

UC1A

MEMORY A

F25

A

A_ADD0

M

E23

A

A_ADD1

M

D27

A

A_ADD2

M

E21

A

A_ADD3

M

C24

A

A_ADD4

M

C26

A

A_ADD5

M

D21

A

A_ADD6

M

C27

A

A_ADD7

M

D22

A

A_ADD8

M

C21

A

A_ADD9

M

F22

A

A_ADD10

M

A24

A

A_ADD11

M

C23

A

A_ADD12

M

J25

A

A_ADD13_BANK2

M

G27

A

A_WE_L_ADD14

M

G23

A

A_CAS_L_ADD15

M

G26

A

A_RAS_L_ADD16

M

F21

A

A_BANK0

M

F27

A

A_BANK1

M

A21

A

A_BG0

M

A27

A

A_BG1

M

A22

A

A_ACT_L

M

21

F

A_DM0

M

27

G

A_DM1

M

24

N

A_DM2

M

23

N

A_DM3

M

L24

A

A_DM4

M

N27

A

A_DM5

M

W25

A

A_DM6

M

T21

A

A_DM7

M

27

T

SVD_36

R

22

F

A_DQS_H0

M

22

G

A_DQS_L0

M

27

H

A_DQS_H1

M

26

H

A_DQS_L1

M

27

N

A_DQS_H2

M

26

N

A_DQS_L2

M

21

R

A_DQS_H3

M

21

P

A_DQS_L3

M

M26

A

A_DQS_H4

M

M27

A

A_DQS_L4

M

N24

A

A_DQS_H5

M

N25

A

A_DQS_L5

M

U23

A

A_DQS_H6

M

T23

A

A_DQS_L6

M

V20

A

A_DQS_H7

M

W20

A

A_DQS_L7

M

24

V

SVD_41

R

23

V

SVD_40

R

D25

A

A_CLK_H0

M

D24

A

A_CLK_L0

M

E26

A

A_CLK_H1

M

E27

A

A_CLK_L1

M

G21

A

A_CS_L0

M

J27

A

A_CS_L1

M

23

Y

A_CKE0

M

26

Y

A_CKE1

M

G24

A

A_ODT0

M

J22

A

A_ODT1

M

A25

A

A_ALERT_L

M

E24

A

A_EVENT_L

M

24

Y

A_RESET_L

M

FP5 REV 0.90

ART 1 OF 13

P

P5_BGA1140~D

F

@

4

DR_A_DQ[63..0] [13]

D

DR_A_DQ0

D

21

J

A_DATA0

M

DR_A_DQ1

D

21

H

A_DATA1

M

DR_A_DQ2

D

23

F

A_DATA2

M

DR_A_DQ3

D

23

H

A_DATA3

M

DR_A_DQ4

D

20

G

A_DATA4

M

DR_A_DQ5

D

20

F

A_DATA5

M

DR_A_DQ6

D

22

J

A_DATA6

M

DR_A_DQ7

D

23

J

A_DATA7

M

DR_A_DQ8

D

25

G

A_DATA8

M

DR_A_DQ9

D

26

F

A_DATA9

M

DR_A_DQ10

D

24

L

A_DATA10

M

DR_A_DQ11

D

26

L

A_DATA11

M

DR_A_DQ12

D

23

L

A_DATA12

M

DR_A_DQ13

D

25

F

A_DATA13

M

DR_A_DQ14

D

25

K

A_DATA14

M

DR_A_DQ15

D

27

K

A_DATA15

M

DR_A_DQ16

D

25

M

A_DATA16

M

DR_A_DQ17

D

27

M

A_DATA17

M

DR_A_DQ18

D

27

P

A_DATA18

M

DR_A_DQ19

D

24

R

A_DATA19

M

DR_A_DQ20

D

27

L

A_DATA20

M

DR_A_DQ21

D

24

M

A_DATA21

M

DR_A_DQ22

D

24

P

A_DATA22

M

DR_A_DQ23

D

25

P

A_DATA23

M

DR_A_DQ24

D

22

M

A_DATA24

M

DR_A_DQ25

D

21

N

A_DATA25

M

DR_A_DQ26

D

22

T

A_DATA26

M

DR_A_DQ27

D

21

V

A_DATA27

M

DR_A_DQ28

D

21

L

A_DATA28

M

DR_A_DQ29

D

20

M

A_DATA29

M

DR_A_DQ30

D

23

R

A_DATA30

M

DR_A_DQ31

D

21

T

A_DATA31

M

DR_A_DQ32

D

L27

A

A_DATA32

M

DR_A_DQ33

D

L25

A

A_DATA33

M

DR_A_DQ34

D

P26

A

A_DATA34

M

DR_A_DQ35

D

R27

A

A_DATA35

M

DR_A_DQ36

D

K26

A

A_DATA36

M

DR_A_DQ37

D

K24

A

A_DATA37

M

DR_A_DQ38

D

M24

A

A_DATA38

M

DR_A_DQ39

D

P27

A

A_DATA39

M

DR_A_DQ40

D

M23

A

A_DATA40

M

DR_A_DQ41

D

M21

A

A_DATA41

M

DR_A_DQ42

D

R25

A

A_DATA42

M

DR_A_DQ43

D

U27

A

A_DATA43

M

DR_A_DQ44

D

L22

A

A_DATA44

M

DR_A_DQ45

D

L21

A

A_DATA45

M

DR_A_DQ46

D

P24

A

A_DATA46

M

DR_A_DQ47

D

P23

A

A_DATA47

M

DR_A_DQ48

D

W26

A

A_DATA48

M

DR_A_DQ49

D

V25

A

A_DATA49

M

DR_A_DQ50

D

V22

A

A_DATA50

M

DR_A_DQ51

D

W22

A

A_DATA51

M

DR_A_DQ52

D

U26

A

A_DATA52

M

DR_A_DQ53

D

V27

A

A_DATA53

M

DR_A_DQ54

D

W23

A

A_DATA54

M

DR_A_DQ55

D

T22

A

A_DATA55

M

DR_A_DQ56

D

W21

A

A_DATA56

M

DR_A_DQ57

D

U21

A

A_DATA57

M

DR_A_DQ58

D

P21

A

A_DATA58

M

DR_A_DQ59

D

N20

A

A_DATA59

M

DR_A_DQ60

D

R22

A

A_DATA60

M

DR_A_DQ61

D

N22

A

A_DATA61

M

DR_A_DQ62

D

T20

A

A_DATA62

M

DR_A_DQ63

D

R20

A

A_DATA63

M

24

T

SVD_34

R

25

T

SVD_35

R

25

W

SVD_51

R

27

W

SVD_52

R

26

R

SVD_27

R

27

R

SVD_28

R

27

V

SVD_43

R

26

V

SVD_42

R

DR_A_PAR

D

F24

A

A_PAROUT

M

DR_A_PAR [13]

D

3

DR_B_MA[13..0][14]

D

D
D
D
D
D
D
D
D
D
D
D
D
D
D

DR_B_MA14_WE#[14]

D

DR_B_MA15_CAS#[14]

D

DR_B_MA16_RAS#[14]

D

DR_B_BA0[14]

D

DR_B_BA1[14]

D

D
D

DR_B_BG0[1 4]

D

DR_B_BG1[1 4]

D

D

DR_B_ACT#[14]

D

D

DR_B_DM[7..0][14]

D

D
D
D
D
D
D
D

DR_B_DQS0[14]

D

DR_B_DQS0#[14]

D

DR_B_DQS1[14]

D

DR_B_DQS1#[14]

D

DR_B_DQS2[14]

D

DR_B_DQS2#[14]

D

DR_B_DQS3[14]

D

DR_B_DQS3#[14]

D

DR_B_DQS4[14]

D

DR_B_DQS4#[14]

D

DR_B_DQS5[14]

D

DR_B_DQS5#[14]

D

DR_B_DQS6[14]

D

DR_B_DQS6#[14]

D

DR_B_DQS7[14]

D

DR_B_DQS7#[14]

D

DR_B_CLK0[14]

D

DR_B_CLK0#[14]

D

DR_B_CLK1[14]

D

DR_B_CLK1#[14]

D

DR_B_CS0#[14]

D

DR_B_CS1#[14]

D

DR_B_CKE0[14]

D

DR_B_CKE1[14]

D

DR_B_ODT0[14]

D

DR_B_ODT1[14]

D

DR_B_ALERT#[14]

D

DR_B_EVENT#[14]

D

DR_B_RST#[14]

D

DR_B_MA0
DR_B_MA1
DR_B_MA2
DR_B_MA3
DR_B_MA4
DR_B_MA5
DR_B_MA6
DR_B_MA7
DR_B_MA8
DR_B_MA9
DR_B_MA10
DR_B_MA11
DR_B_MA12
DR_B_MA13

DR_B_BG0
DR_B_BG1

DR_B_ACT#

DR_B_DM0
DR_B_DM1
DR_B_DM2
DR_B_DM3
DR_B_DM4
DR_B_DM5
DR_B_DM6
DR_B_DM7

2

UC1I

MEMORY B

G30

A

B_ADD0

M

C32

A

B_ADD1

M

C30

A

B_ADD2

M

B29

A

B_ADD3

M

B31

A

B_ADD4

M

A30

A

B_ADD5

M

A29

A

B_ADD6

M

30

Y

B_ADD7

M

A31

A

B_ADD8

M

29

W

B_ADD9

M

H29

A

B_ADD10

M

32

Y

B_ADD11

M

31

W

B_ADD12

M

L30

A

B_ADD13_BANK2

M

K30

A

B_WE_L_ADD14

M

K32

A

B_CAS_L_ADD15

M

J30

A

B_RAS_L_ADD16

M

H31

A

B_BANK0

M

G32

A

B_BANK1

M

31

V

B_BG0

M

29

V

B_BG1

M

30

V

B_ACT_L

M

21

C

B_DM0

M

25

C

B_DM1

M

32

E

B_DM2

M

30

K

B_DM3

M

P30

A

B_DM4

M

W31

A

B_DM5

M

B26

B

B_DM6

M

D22

B

B_DM7

M

32

N

SVD_21

R

22

D

B_DQS_H0

M

22

B

B_DQS_L0

M

25

D

B_DQS_H1

M

25

B

B_DQS_L1

M

29

F

B_DQS_H2

M

30

F

B_DQS_L2

M

31

K

B_DQS_H3

M

29

K

B_DQS_L3

M

R29

A

B_DQS_H4

M

R31

A

B_DQS_L4

M

W30

A

B_DQS_H5

M

W29

A

B_DQS_L5

M

C25

B

B_DQS_H6

M

A25

B

B_DQS_L6

M

C22

B

B_DQS_H7

M

A22

B

B_DQS_L7

M

31

N

SVD_20

R

29

N

SVD_18

R

C31

A

B_CLK_H0

M

D30

A

B_CLK_L0

M

D29

A

B_CLK_H1

M

D31

A

B_CLK_L1

M

E30

A

B_CLK_H2

M

E32

A

B_CLK_L2

M

F29

A

B_CLK_H3

M

F31

A

B_CLK_L3

M

J31

A

B0_CS_L0

M

M31

A

B0_CS_L1

M

J29

A

B1_CS_L0

M

M29

A

B1_CS_L1

M

29

U

B0_CKE0

M

30

T

B0_CKE1

M

32

V

B1_CKE0

M

31

U

B1_CKE1

M

L31

A

B0_ODT0

M

M32

A

B0_ODT1

M

L29

A

B1_ODT0

M

M30

A

B1_ODT1

M

30

W

B_ALERT_L

M

G29

A

B_EVENT_L

M

31

T

B_RESET_L

M

@

FP5 REV 0.90

P

ART 9 OF 13

P5_BGA1140~D

F

21

B

B_DATA0

M

21

D

B_DATA1

M

23

B

B_DATA2

M

23

D

B_DATA3

M

20

A

B_DATA4

M

20

C

B_DATA5

M

22

A

B_DATA6

M

22

C

B_DATA7

M

24

D

B_DATA8

M

25

A

B_DATA9

M

27

D

B_DATA10

M

27

C

B_DATA11

M

23

C

B_DATA12

M

24

B

B_DATA13

M

26

C

B_DATA14

M

27

B

B_DATA15

M

30

C

B_DATA16

M

29

E

B_DATA17

M

29

H

B_DATA18

M

31

H

B_DATA19

M

28

A

B_DATA20

M

28

D

B_DATA21

M

31

F

B_DATA22

M

30

G

B_DATA23

M

29

J

B_DATA24

M

31

J

B_DATA25

M

29

L

B_DATA26

M

31

L

B_DATA27

M

30

H

B_DATA28

M

32

H

B_DATA29

M

30

L

B_DATA30

M

32

L

B_DATA31

M

P29

A

B_DATA32

M

P32

A

B_DATA33

M

T29

A

B_DATA34

M

U32

A

B_DATA35

M

N30

A

B_DATA36

M

P31

A

B_DATA37

M

R30

A

B_DATA38

M

T31

A

B_DATA39

M

U29

A

B_DATA40

M

V30

A

B_DATA41

M

B30

B

B_DATA42

M

A28

B

B_DATA43

M

U30

A

B_DATA44

M

U31

A

B_DATA45

M

Y32

A

B_DATA46

M

Y29

A

B_DATA47

M

A27

B

B_DATA48

M

C27

B

B_DATA49

M

A24

B

B_DATA50

M

C24

B

B_DATA51

M

D28

B

B_DATA52

M

B27

B

B_DATA53

M

B25

B

B_DATA54

M

D25

B

B_DATA55

M

C23

B

B_DATA56

M

B22

B

B_DATA57

M

C21

B

B_DATA58

M

D20

B

B_DATA59

M

B23

B

B_DATA60

M

A23

B

B_DATA61

M

B21

B

B_DATA62

M

A21

B

B_DATA63

M

31

M

SVD_17

R

30

N

SVD_19

R

31

P

SVD_26

R

32

R

SVD_29

R

30

M

SVD_16

R

29

M

SVD_15

R

30

P

SVD_25

R

29

P

SVD_24

R

G31

A

B_PAROUT

M

DR_B_DQ0

D

DR_B_DQ1

D

DR_B_DQ2

D

DR_B_DQ3

D

DR_B_DQ4

D

DR_B_DQ5

D

DR_B_DQ6

D

DR_B_DQ7

D

DR_B_DQ8

D

DR_B_DQ9

D

DR_B_DQ10

D

DR_B_DQ11

D

DR_B_DQ12

D

DR_B_DQ13

D

DR_B_DQ14

D

DR_B_DQ15

D

DR_B_DQ16

D

DR_B_DQ17

D

DR_B_DQ18

D

DR_B_DQ19

D

DR_B_DQ20

D

DR_B_DQ21

D

DR_B_DQ22

D

DR_B_DQ23

D

DR_B_DQ24

D

DR_B_DQ25

D

DR_B_DQ26

D

DR_B_DQ27

D

DR_B_DQ28

D

DR_B_DQ29

D

DR_B_DQ30

D

DR_B_DQ31

D

DR_B_DQ32

D

DR_B_DQ33

D

DR_B_DQ34

D

DR_B_DQ35

D

DR_B_DQ36

D

DR_B_DQ37

D

DR_B_DQ38

D

DR_B_DQ39

D

DR_B_DQ40

D

DR_B_DQ41

D

DR_B_DQ42

D

DR_B_DQ43

D

DR_B_DQ44

D

DR_B_DQ45

D

DR_B_DQ46

D

DR_B_DQ47

D

DR_B_DQ48

D

DR_B_DQ49

D

DR_B_DQ50

D

DR_B_DQ51

D

DR_B_DQ52

D

DR_B_DQ53

D

DR_B_DQ54

D

DR_B_DQ55

D

DR_B_DQ56

D

DR_B_DQ57

D

DR_B_DQ58

D

DR_B_DQ59

D

DR_B_DQ60

D

DR_B_DQ61

D

DR_B_DQ62

D

DR_B_DQ63

D

DR_B_PAR

D

DR_B_DQ[63..0] [14]

D

DR_B_PAR [14]

D

1

VENT# pull high

E

1.2V_DDR

+

1 2

C1 1K_0402_5%

R

1.2V_DDR

+

C2 1K_0402_5%

R

A A

1 2

DR_B_EVENT#

D

DR_A_EVENT#

D

5

ecurity Classification

ecurity Clas sification

ecurity Clas sification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

016/01/0 7 2017/01/07

016/01/0 7 2017/01/07

016/01/0 7 2017/01/07

2

2

2

2

eciphered Date

eciphered Date

eciphered Date

D

D

D

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

itle

itle

itle

T

T

T

P4 DDR4 MEMORY I/F

P4 DDR4 MEMORY I/F

P4 DDR4 MEMORY I/F

F

F

F

ze

ze

ze

Si

Si

Si

ocument Number Rev

ocument Number Rev

ocument Number Rev

D

D

D

ustom

ustom

ustom

C

C

C

A-F121P

A-F121P

A-F121P

L

L

L

Date: Sheetof

Date: Sheetof

Date: Sheetof

1

7 61Thursday, November 09, 20 17

7 61Thursday, November 09, 20 17

7 61Thursday, November 09, 20 17

.3(X02)

.3(X02)

.3(X02)

0

0

0

1 2

1 2

1 2

E

E

A

18

A

27

A

36
45

H

HERMTRIP#

T

R
1K_0402_5%

R
1K_0402_5%

R
1K_0402_5%

C_SMB_CK2[27,28,39]

C_SMB_DA2[27,28,39]

PU_SID
PU_ALERT#
PU_SIC

_PROCHOT#

A

1.8VS

+

PC30

@

R

18
27
36
45

10K_0804_8P4R_5%

@

C6

@

C7

@

C8

C250

C

1 2

0.1U_0402_16V7K

@ESD@

1 2

@ESD@

1 2

1 2

PU_SVT

A

PU_SVC

A

PU_SVD

A

C_SMB_CK2

E

C_SMB_DA2

E

C_SMB_CK2

E

C_SMB_DA2

E

PU at EC side

@ESD@

PU_RST#

A

C527P_0402_50V8F

C

PU_PWRGD

A

C627P_0402_50V8F

C

C27220_0402_5%

R

@

DP_TXP0[16]

E

DP_TXN0[16]

E

DP

e

DP_TXP1[16]

E

DP_TXN1[16]

E

PU_DP1_P0[17]

A

PU_DP1_N0[17]

A

PU_DP1_P1[17]

A

PU_DP1_N1[17]

A

DMI

H

PU_DP1_P2[17]

A

PU_DP1_N2[17]

A

PU_DP1_P3[17]

A

PU_DP1_N3[17]

A

C616 0_0402_5%

R

1 2

C617 0_0402_5%

R

1 2

_PROCHOT#[10,27,46,48,53]

H

PU_SVC[53]

A

PU_SVD[53]

A

PU_SVT[53]

A

ain Func = CPU

M

1 1

PU_TEST14

A

PU_TEST15

A

PU_TEST16

A

PU_TEST17

A

1.8VS

+

2 2

3VS

+

PC3

R

1K_0804_8P4R_5%

3VS

+

C24 1K_0402_5%@

R

1 2

C25 1K_0402_5%@

R

1 2

3 3

3VS

+

1 2

C26

R
1K_0402_5%

1 2

C664

R
1K_0402_5%

4 4

DP_TXP0

E

DP_TXN0

E

DP_TXP1

E

DP_TXN1

E

PU_SIC

A

PU_SID

A

C12 300_0402_5%

R

1.8VS

+

C15 300_0402_5%

R

1.8VS

+

PU_PWRGD[53]

A

C18 0_0402_5%

R

C20 0_0402_5%

R

C22 0_0402_5%

R

B

1 2
1 2

1 2
1 2
1 2

C

P3: Typec

D
DP2: CRT
DP1: HDMI
DP0: eDP

UC1C

DISPLAY/SVI2/JTA G/TES T

8

C

P0_TXP0

D

8

A

P0_TXN0

D

8

D

P0_TXP1

D

8

B

P0_TXN1

D

6

B

P0_TXP2

D

7

C

P0_TXN2

D

6

C

P0_TXP3

D

6

D

P0_TXN3

PU_DP1_P0

A

PU_DP1_N0

A

PU_DP1_P1

A

PU_DP1_N1

A

PU_DP1_P2

A

PU_DP1_N2

A

PU_DP1_P3

A

PU_DP1_N3

A

PU_TDI

A

PU_TDO

A

PU_TCK

A

PU_TMS

A

PU_TRST#

A

PU_DBREQ#

A

PU_RST#

A

PU_PWRGD

A

PU_SIC

A

PU_SID

A

PU_ALERT#

A

HERMTRIP#

T

HERMTRIP#[27]

T

PU_SVC_R

A

PU_SVD_R

A

PU_SVT_R

A

D

6

E

P1_TXP0

D

5

D

P1_TXN0

D

1

E

P1_TXP1

D

1

C

P1_TXN1

D

3

F

P1_TXP2

D

4

E

P1_TXN2

D

4

F

P1_TXP3

D

2

F

P1_TXN3

D

U2

A

DI

T

U4

A

DO

T

U1

A

CK

T

U3

A

MS

T

V3

A

RST_L

T

W3

A

BREQ_L

D

W4

A

ESET_L

R

W2

A

WROK

P

14

H

IC

S

14

J

ID

S

15

J

LERT_L

A

P16

A

HERMTRIP_L

T

19

L

ROCHOT_L

P

16

F

VC0

S

16

H

VD0

S

16

J

VT0

S

@

PU_TRST#

A

H21 33_0402_5%@

R

1 2

H22 10K_0402_5%@

R

1 2

H23 10K_0402_5%@

R

1 2

H24 10K_0402_5%@

R

1 2

FP5 REV 0.90
ART 3 OF 13

P

P5_BGA1140~D

F

D

P_STEREOSYNC

D

C

DDP_SENSE

V

DDCR_SOC_SENSE

V

DDCR_SENSE

V

SS_SENSE_A

V

SS_SENSE_B

V

PU_TRST#_R

A

P_BLON

D

P_DIGON

D

P_VARY_BL

P0_AUXP

D

P0_AUXN

D

P0_HPD

D

P1_AUXP

D

P1_AUXN

D

P1_HPD

D

P2_AUXP

D

P2_AUXN

D

P2_HPD

D

P3_AUXP

D

P3_AUXN

D

P3_HPD

D

SVD_4

R

SVD_3

R

SVD_2

R

T

T

T

EST14

T

EST15

T

EST16

T

EST17

T

EST31

T

EST41

T

EST470

T

EST471

T

MU_ZVDD

S

ORETYPE

ANEL_BKLEN_EC

P

15

G

NVDD_R

E

15

F

NVTPWM_R

I

14

L

9

D

9

B

10

C

11

G

11

F

13

G

12

J

12

H

13

K

10

J

10

H

8

K

P_STEREOSYNC

D

15

K

14

F

12

F

10

F

P14

A

EST4

N14

A

EST5

13

F

EST6

18

G

19

H

18

F

19

F

24

W

R11

A

J21

A

K21

A

MU_ZVDDP

S

4

V

W11

A

N11

A

19

J

18

K

SS_SENSEA

V

18

J

M11

A

P

2

T

3

T

4

T

PU_TEST4

A

PU_TEST5

A

PU_TEST6

A

PU_TEST14

A

PU_TEST15

A

PU_TEST16

A

PU_TEST17

A

PU_TEST31

A

PU_TEST41

A

PU_TEST470

A

PU_TEST471

A

C13 196_0402_1%

R

1 2

C17 10K_0402_5%@

R

1 2

16

T

18

T

100

T

120

T

121

T

122

T

ANEL_BKLEN_EC[9]

DP_AUXP [16]

E

DP_AUXN [16]

E

DP_HPD [16]

E

PU_DP1_CTRL_CLK [17]

A

PU_DP1_CTRL_DATA [17]

A

PU_DP1_HPD [17]

A

PU_DP2_AUXP [36]

A

PU_DP2_AUXN [36 ]

A

PU_DP2_HPD [36]

A

PU_DP3_AUXP [33]

A

PU_DP3_AUXN [33 ]

A

PU_DP3_HPD [31,33]

A

5

T

6

T

7

T

8

T

9

T

10

T

11

T

12

T

13

T

14

T

15

T

DDP_SENSE_H [51]

V

PU_VDDSOC_SEN [53 ]

A

PU_VDDCR_SEN [53]

A

DDP_SENSE_L [51]

V

123

T

124

T

125

T

NVDD_R[9]

E

0.9VS

+

3VALW

+

C19 0_0402_5%

R

R

PU_TCK

A

H27 0_0402_5%

@

1 2

PU_TMS

A

A

D

ANEL_BKLEN_EC

P

1.8VS

+

NVDD_R

E

NVTPWM_R

I

12

PU_PWRGD_BUF

PU_RST#_BUF

A

PU_DBREQ#_R

A

D

S

123

C1 MESS138W-G_SOT323-3

Q

G

1.8VS

+

5

C5

U

1

P

C

N

4

Y

2

A

G

NL17SZ07DFT2G_SC70-5

3

SA00004BV00

1.8VS

+

5

C2

U

1

P

C

N

4

Y

2

A

G

NL17SZ07DFT2G_SC70-5

3

SA00004BV00

17

T

PU_VDD_RUN_FB_L

A

DT+

H

DT debug + HDT@

H

R

PU_TDI

A

H28 0_0402_5%

@

1 2

PU_TDO

A

@

H1 DB2J31400 L_SOD323-2

D

21

H2 DB2J31400 L_SOD323-2

D

21

@

1 2

H25 33_0402_5%

R

A

@

E

PU_DBREQ#

NVDD [16]

NVTPWM [16]

I

A
A

3VS

+

C3

R

2.2K_0402_5%

1 2

NVDD

E

NVTPWM

I

ANEL_BKLEN_EC

P

NVDD_R

E

P_STEREOSYNC

D

PU_VDD_RUN_FB_L [53]

A

PU_TRST#

A

PU_PWRGD
PU_RST#

E

P

1 2

C4

R

4.7K_0402_5%

1 2

C5

R

4.7K_0402_5%

R

100K_0804_8P4R_5%

1 2

R
1K_0402_5%

1 2

R
1K_0402_5%

@

H26 1K_0402_5%@

R

1 2

PU_TCK

A

PU_TMS

A

PU_TDI

A

PU_DBREQ#

A

PU_TDI

A

PU_DBREQ#

A

PU_TRST#

A

ANEL_BKLEN [27]

3VS

+

PC1

18
27
36
45

1.8VS

+

C10

C16

PH1

R

1 8
2 7
3 6
4 5

1K_0804_8P4R_5%

@

1 2

1 2

1 2

C251

C

@ESD@

1 2

0.1U_0402_16V7K

1.8V_ALW

+

1.8V_ALW

+

H40.01U_0402_16V7K @

C

H30.01U_0402_16V7K @

C

H20.01U_0402_16V7K HDT@

C

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF E NGINEERING DRAWING IS THE PROPRIETARY P ROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFID ENTIAL

HIS SHEET OF E NGINEERING DRAWING IS THE PROPRIETARY P ROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFID ENTIAL

HIS SHEET OF E NGINEERING DRAWING IS THE PROPRIETARY P ROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFID ENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELEC TRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELEC TRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELEC TRONICS, INC.

C

016/01/07 2017/01/07

016/01/07 2017/01/07

016/01/07 2017/01/07

2

2

2

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

Deciphered Date

Deciphered Date

Deciphered Date

T

S

S

S

Date: Sheetof

Date: Sheetof

D

Date: Sheetof

P4 DISP/MISC/HDT

P4 DISP/MISC/HDT

P4 DISP/MISC/HDT

F

F

F

ize

ocument Numb er Re v

ize

ocument Numb er Re v

ize

ocument Numb er Re v

D

D

D

ustom

ustom

ustom

C

C

C

A-F121P

A-F121P

A-F121P

L

L

L

8 61Thursday, November 09, 2017

8 61Thursday, November 09, 2017

8 61Thursday, November 09, 2017

E

.3(X02)

.3(X02)

.3(X02)

0

0

0

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

itle

itle

itle

T

T

ain Func = CPU

M

A

1 2

3VS

+

1 2
1 2

B

EVSLP0_HDD

D

C62010K_0402_5% @

R

SD_DEVSLP

S

C66310K_0402_5% @

R

ATA_ACT#

S

C62110K_0402_5%

R

C

D

E

C630 0_040 2_5%MODS@

R

0A3_GPIO

S

1 2

C28 0_0402_5%@

R

12

GATE [27,51,53]

PU_FCH_PWRGD

A

C30 0_0402_5%

.1U_0402_16V7K

+

C8 100P_0 402_50V8J

C

PU_FCH_PWRGD

A

2

C9

C

1

DA_BIT_CLK_R[18]

H

DA_SDOUT_R[18]

H

DA_SYNC_R[18]

H

DA_RST#_R[18]

H

3VS

2.2K_0804_8P4R_5%

3VALW

+

C6130 10K_0402_5%

R

C6122 10K_0402_5%

R

C53 10K_0402_5%

R

C56 10K_0402_5%PTP @

R

C57 10K_0402_5%NPTP@

R

C58 10K_0402_5%

R

C59 10K_0402_5%

R

C60 10K_0402_5%@

R

C62 10K_0402_5%@

R

R

@ESD@

12

H23 close to UC1

C

2

C10

C

.1U_0402_16V7K

1

PC64

R

1 2
1 2
1 2

1 2

1 2
1 2

1 2
1 2
1 2

C39 0_0402_5%@

R

18
27
36
45

1 1

2 2

3 3

4 4

V

12

PU_FCH_POK [27]

A

INPU T

PU_FCH_PWRGD

A

3VALW_EC+3VALW+3VS

+

12

C33

R

@

5

C3

U

1

.7K_0402_5%

P

4

PU_FCH_PWRGD_R

A

C

N

4

Y

2

A

G

NL17SZ07DFT2G_SC70-5

3

SA00004BV00

12

EMI@

PC4

R

DA_BIT_CLK

H

1 8

DA_SDOUT

H

2 7

DA_SYNC

H

3 6

DA_RST#

H

4 5

33_0804_8P4R_5%

1 8
2 7
3 6
4 5

PU_SCLK0

A

PU_SDATA0

A

swap @04/14

TC_DET#

R

ATA_ODD_PRSNT#

S

BTN_OUT#

P

GPIO8

A

GPIO8

A

DA_SDIN1

H

DA_SDIN2

H

DA_SDIN0

H

DA_BIT_CLK

H

0A3_GPIO[20,26,27]

S

12

@

.7K_0402_5%
4

PC5

R

1K_0804_8P4R_5%

MC74VHC1G08DFT2G SC70 5P

0A3_GPIO

S

C34

R

4

C9

U

swap @04/14

1

1

C
10P_0402_50V8J

2

C12 0.1U_0402_16V7K

C

C14 0.1U_0402_16V7K

C

3VALW

+

5

2

P

B

Y

1

A

G

3

MODS@

PU_PCIE_WAKE#[19,27,34]

A

M_SLP_S3#_R[27]

P

M_SLP_S5#[27]

P

@RF@

eed check with ESD

n

@ESD@

12

@ESD@

12

0.1U_0402_16V7K

ODS@

M

PU_PCIE_RST#_C

A

PU_PCIE1_RST#_C

A

C_RSMRST#

E

YS_RESET_L

S

+

MODS@

1

2

3VALW

C
C94

C

1 2

C100 150P_0402_50V8J@

R
10K_0402_5%

0.1U_0402_16V7K

1 2

ATA_ODD_PRSNT#[22,27]

S

C619

C618 0_0402_5%MODS@

R

1

ODS@

M

2

R
R

PU_PCIE_WAKE#

A

M_SLP_S3#_R

P

DA_SDIN0[18]

H

C_RSMRST#[27]

E

1 2

C
C95

1 2

C7 150P_0 402_50V8J

C

C29 33_0402_5%

1 2

C704 33_0402_5%

1 2

@

BTN_OUT#[27]

P

C631 0_040 2_5%

R

1 2

115

T

EM_ERROR_B[27 ]

M

TC_DET#[11]

R

PU_PCIE_RST#_C

A

PU_PCIE1_RST#_C

A

C_RSMRST#

E

M_SLP_S3#

P

0A3

S

PU_PCIE_RST#_R

A

PU_PCIE1_RST#_R

A

C_RSMRST#

E

PU_FCH_PWRGD_R

A

YS_RESET_L

S

M_SLP_S3#

P

EM_ERROR_B

M

ATA_ODD_PRSNT#

S

DA_BIT_CLK

H

DA_SDIN0

H

DA_SDIN1

H

DA_SDIN2

H

DA_RST#

H

DA_SYNC

H

DA_SDOUT

H

PU_PCIE1_RST#_U

A

C700 0_0402_5%

R

1 2

C701 0_0402_5%

R

1 2

@

0A3

S

TC_DET#

R

GPIO8

A

PU_PCIE1_RST#_U

A

D5

B

CIE_RST0_L/EGPIO26

P

B6

B

CIE_RST1_L/EGPIO27

P

T16

A

SMRST_L

R

R15

A

WR_BTN_L/AGPIO0

P

V6

A

WR_GOOD

P

P10

A

YS_RESET_L/AGPIO1

S

V11

A

AKE_L/AGPIO2

W

V13

A

LP_S3_L

S

T14

A

LP_S5_L

S

R8

A

0A3_GPIO/AGPIO10

S

T10

A

C_PRES/AGPIO23

A

N6

A

LB_L/AGPIO12

L

W8

A

GPIO42

E

R2

A

Z_BITCLK/TDM_BCLK_MIC

A

P7

A

Z_SDIN0/CODEC_GPI

A

P1

A

Z_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK

A

P4

A

Z_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK

A

P3

A

Z_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC

A

R4

A

Z_SYNC/TDM_FRM_MIC

A

R3

A

Z_SDOUT/TDM_FRM_PLAYBACK

A

T2

A

W_MCLK/TDM_BCLK_BT

S

T4

A

W_DATA0/TDM_DOUT_BT

S

R6

A

GPIO7/FCH_ACP_I2S_SDIN_BT

A

P6

A

GPIO8/FCH_ACP_I2S_LRCLK_BT

A

@

1 2

R
C703 10K_0402_5%

@

1 2

+

C54

R

22K_0402_5%

C
C16

MC74VHC1G08DFT2G SC70 5P

1.8V_ALW

UC1D

ACPI/AUDIO/I2 C/GPI O/ MIS C

3.3VS input

3.3VS input

FP5 REV 0.90

ART 4 OF 13

P

P5_BGA1140~D

F

6

D

1 2

RB751V-40_SOD323-2

5

D

1 2

RB751V-40_SOD323-2

PU_PCIE_RST#

A

C440_0402_5%

R

3VALW

+

C13

@

C

1 2

0.1U_0402_16V7K

5

2

P

B

4

Y

1

A

G

C4

U

3

@

12

R
0_0402_5%

GPIO41/SFI_S5_EGPIO41

E

GPIO39/SFI_S5_AGPIO39

A

2C0_SCL/SFI0_I2C_SCL/EGPIO151

I

2C0_SDA/SFI0_I2C_SDA/EGPIO152

I

2C1_SCL/SFI1_I2C_SCL/EGPIO149

I

2C1_SDA/SFI1_I2C_SDA/EGPIO150

I

2C2_SCL/EGPIO113/SCL0

I

2C2_SDA/EGPIO114/SDA0

I

2C3_SCL/AGPIO19/SCL1

I

2C3_SDA/AGPIO20/SDA1

I

GPIO4/SATA E_IFDET

A

ATA_ACT_L/AGPIO130

S

3.3VALW input

3.3VALW input

3.3VS input

.3VS Output

3

G

G

ANEL_BKLEN_EC

P

NVDD_R

E

PU_PCIE_RST# [19,20,34,38]

A

@

C49

LT_RST#

P

GPIO5/DEVSLP0

A

GPIO6/DEVSLP1

A

NTRUDER_ALERT

I

S

B

ENINT1_L/AGPIO89

ENINT2_L/AGPIO90

ANIN0/AGPIO84

F

ANOUT0/AGPIO85

F

PKR/AGPIO91

LINK/AGPIO11

SA_I2C_SCL

P

SA_I2C_SDA

P

GPIO3

A

GPIO9

A

GPIO40

A

GPIO69

A

GPIO86

A

W12

A

U12

A

R13

A

T13

A

N8

A

N9

A

PU_SCLK0

A

C20

B

PU_SDATA0

A

A20

B

2C_3_SCL

I

M9

A

2C_3_SDA

I

M10

A

16

L

16

M

T15

A

GPIO3

A

W10

A

P9

A

U10

A

ATA_ACT#

S

V15

A

DD_EN#

H

U7

A

KU_ID

S

U6

A

.3V_TS_EN

3

W13

A

W15

A

U14

A

U16

A

EM_ERROR_A

M

V8

A

W16

A

PIO89

G

B_DET#

K

D15

B

R18

A

T18

A

LT_RST# [10 ,19,20,27]

P

need set pull down by SW

PU_SCLK0 [13,14,22,36]

A

PU_SDATA0 [13,14,22,36]

A

2C_3_SCL [24]

I
2C_3_SDA [24]

I

C36 0_0402_5%

R

add hdd_en# @3/7

add 3.3V_TS_EN@3/7

PIO89 [34]

G

B_DET# [24]

K

ANEL_BKLEN_EC [8]

P

NVDD_R [8]

E

12

EVSLP0_HDD [22]

D

SD_DEVSLP [34]

S
ATA_ACT# [27,29,34]

S

DD_EN# [22]

H

.3V_TS_EN [16]

3

EM_ERROR_A [27]

M

FS_INT1 [22]

F

FS_INT2 [22]

F

FS_INT1

F

FS_INT2

F

set to SMbus

set to I2C

P_I2C_INT#_APU

T

PU_SPKR [18]

A

C11

C

1 2

0.1U_0402_16V7K

FFS@

C6123 10K_0402_5%

R

1 2

C6124 10K_0402_5%FFS@

R

1 2

T

@

P_I2C_INT#_APU [24]

3VS

+

3VALW

+

R
10K_0402_5%

1 2

KU_ID

S

R
10K_0402_5%

1 2

trap pin

S

PU_SPI_CLK_R

A

PU_SPI_CLK_R[10]

A

C41

C42

DIS@

MA: LOW

U
DIS: HIGH

UMA@

1.8VS+1.8V_ALW

+

10K_0402_5%

12

R

R

C47

C622

@

12

12

A

10K_0402_5%

@

C51

R
2K_0402_5%

GPIO3

3VALW

+

1 2

12

C48

R
10K_0402_5%

@

C52

R
2K_0402_5%

YS_RESET_L

S

3VALW

+

C4010K_04 02_5%

R

12

12

10U_0603_6.3V6M

1U_0603_25V6K

C

1

12

C15

2

C61

R

@

@

10K_0402_5%

1 2

or Modern standby

f

A

ecurity C lassificatio n

ecurity C lassificatio n

ecurity C lassificatio n

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PRO PERTY OF CO MPAL ELEC TRONICS, INC. AND CO NTAINS CO NFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PRO PERTY OF CO MPAL ELEC TRONICS, INC. AND CO NTAINS CO NFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PRO PERTY OF CO MPAL ELEC TRONICS, INC. AND CO NTAINS CO NFIDENTIAL

T

T

T
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF T HE COMPETENT DIVISION OF R &D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF T HE COMPETENT DIVISION OF R &D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF T HE COMPETENT DIVISION OF R &D
DEPARTMENT E XCEPT AS AUTHORIZED BY C OMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CO NTAINS

DEPARTMENT E XCEPT AS AUTHORIZED BY C OMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CO NTAINS

DEPARTMENT E XCEPT AS AUTHORIZED BY C OMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CO NTAINS
MAY BE USED BY OR DISCLOS ED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOS ED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

B

C

MAY BE USED BY OR DISCLOS ED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

016/01/07 2017/01/07

016/01/07 2017/01/07

016/01/07 2017/01/07

2

2

2

eciphered Date

eciphered Date

eciphered Date

D

D

D

D

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

itle

itle

itle

T

T

T

P4 GPIO/AZ/MISC/STRAPS

P4 GPIO/AZ/MISC/STRAPS

P4 GPIO/AZ/MISC/STRAPS

F

F

F

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

ustom

ustom

ustom

C

C

C

A-F121P

A-F121P

A-F121P

L

L

L

Date: Sheetof

Date: Sheetof

Date: Sheetof

E

9 61Thursday, November 09, 2017

9 61Thursday, November 09, 2017

9 61Thursday, November 09, 2017

.3(X02)

.3(X02)

.3(X02)

0

0

0

1 2

1 2

1 2

914

RC
20M_0402_5%

1

4

169510K_0402_5%

RC

169610K_0402_5%

RC

169710K_0402_5%

RC

48

48

1

2

YC

48MHZ_8PF_X3S048000D81H-W

Part Number = SJ10000AF00

4

1

97

C7

3.9P_0402_50V8B

2

SJ100001K00

12

1

682

CC
15P_0402_50V8J

2

.8V_ALW

+1

1 2

RC

1 2

RC

A

M_X2

M_X1

SU

944.7K_0402_5% TYPEC@

954.7K_0402_5% TYPEC@

CL

CL

CL

SCLK_WLAN[20]

YC

_ON#_R

BT

KREQ_PEG#0

KREQ_PCIE#2

KREQ_PCIE#3

12

3

DGPU

LA

WLAN

SSD

K_X1

32

K_X2

32

USB 3.0 TYPEC

USB Conn MB

USB Conn MB

USB Cam

USB Conn DB

2

G

QC

6 1

S

D

DMN63D8LDW-7

TYPEC@

VALW

+3

905 100K_0402_5%

RC

906 100K_0402_5%

RC

6121 100K_0402_5%TYPEC@

RC

U_USBC_SCL

AP

U_USBC_SDA

AP

TPM_S@

RX

10K_0402_5%

_ON#_R[20]

BT

N

SU

3A

1 2
1 2
1 2

+SPI

12

13

CL
CL

CL
CL

CL
CL

CL
CL

SCLK_WLAN

3B

QC

change port @ 1/23

_VCC

12

M_20

TP

K_PEG_P0[38]
K_PEG_N0[38]

K_PCIE_P1[19]
K_PCIE_N1[19]

K_PCIE_P2[20]
K_PCIE_N2[20]

K_PCIE_P3[34]
K_PCIE_N3[34]

5

3 4

D

TYPEC@

TPM_S@

10K_0402_5%

M_24

TP

RC

B HUB

US

G

S

14

RX

KREQ_PEG#0[39]

CL

KREQ_PCIE#1[19]

CL

KREQ_PCIE#2[20]

CL

KREQ_PCIE#3[34]

CL

902 0_0402_5%@

RC

M_X1

48

M_X2

48

@

1689 22 +-5% 0402

B20_0_P0[32]

US

B20_0_N0[32]

US

B20_0_P1[23]

US

B20_0_N1[23]

US

B20_0_P2[23]

US

B20_0_N2[23]

US

B20_0_P3[16]

US

B20_0_N3[16]

US

B20_1_P0[25]

US

B20_1_N0[25]

US

B20_1_P1[35]

US

B20_1_N1[35]

US

DMN63D8LDW-7

B_OC0#[23]

US

B_OC1#[25]

US

B_OC2#[32]

US

B_OC0#

US

B_OC1#

US

B_OC2#

US

39

TPM_L@

RX

10K_0402_5%

Main Func = CPU

VS

+3

1 2

615 10K_0402_5%

RC

VS

+3

1 1

48MHz CRYSTAL

1 2

939

RC

1M_0402_5%

2

2

3

3

1

96

C7

3.9P_0402_50V8B

2

.768KHz CRYSTAL

32

2 2

32.768KHZ_12.5PF_CM31532768DZFT

1

686

CC
18P_0402_50V8J

2

3 3

G4_APU_USBC_SCL[31,33]

CC

G4_APU_USBC_SDA[31,33]

CC

.8V_ALW

+1

4 4

1

2

A

1 2

12

CC_TPM

+V

12

10U_0402_6.3V6M

B

UC1E

KREQ_PEG#0

CL
CL
CL
CL

C_CLK

RT

K_X1

32

K_X2

32

B20_0_P0

US

B20_0_N0

US

B20_0_P1

US

B20_0_N1

US

B20_0_P2

US

B20_0_N2

US

B20_0_P3

US

B20_0_N3

US

B20_1_P0

US

B20_1_N0

US

U_USBC_SCL

AP

U_USBC_SDA

AP

12

TPM_L@

10K_0402_5%

KRUN#_R_TPM

CL

CPD#_R

LP

CC_TPM

+V

0.1U_0402_10V7K

0.1U_0402_10V7K

1

1

CX

CX

CX

13

11

10

2

2

@

TPM@

TPM@

KREQ_PCIE#1
KREQ_PCIE#2
KREQ_PCIE#3

CL
CL

CL
CL

CL
CL

CL
CL

B20_1_P1

US

B20_1_N1

US

US
US
US

38

RX

B

BT

K_PEG_P0
K_PEG_N0

K_PCIE_P1
K_PCIE_N1

K_PCIE_P2
K_PCIE_N2

K_PCIE_P3
K_PCIE_N3

B_OC0#
B_OC1#
B_OC2#

18

AV

19

AN

19

AP

19

AT

19

AU

_ON#

18

AW

19

AW

1

AK

3

AK

2

AM

4

AM

1

AM

3

AM

2

AL

4

AL

2

AN

4

AN

3

AN

2

AP

2

AJ

4

AJ

3

AJ

3

BB

5

BA

8

AF

9

AF

14

AW

1

AY

4

AY

C_AD2

LP

C_AD1

LP

C_AD0

LP

AP
AP

CC_TPM

+V

0.1U_0402_10V7K

10U_0402_6.3V6M

1

1

CX
9

2

2

TPM@

K_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO9 2

CL

K_REQ1_L/AGPIO115

CL

K_REQ2_L/AGPIO116

CL

K_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO1 31

CL

K_REQ4_L/OSCIN/EGPIO132

CL

K_REQ5_L/EGPIO120

CL

K_REQ6_L/EGPIO121

CL

P_CLK0P

GP

P_CLK0N

GP

P_CLK1P

GP

P_CLK1N

GP

P_CLK2P

GP

P_CLK2N

GP

P_CLK3P

GP

P_CLK3N

GP

P_CLK4P

GP

P_CLK4N

GP

P_CLK5P

GP

P_CLK5N

GP

P_CLK6P

GP

P_CLK6N

GP

M_OSC

48

8M_X1

X4

8M_X2

X4

VD_76

RS

VD_77

RS

CCLK

RT

2K_X1

X3

2K_X2

X3

@

VS

+3

7

AE

B_0_DP0

US

6

AE

B_0_DM0

US

10

AG

B_0_DP1

US

9

AG

B_0_DM1

US

12

AF

B_0_DP2

US

11

AF

B_0_DM2

US

10

AE

B_0_DP3

US

9

AE

B_0_DM3

US

12

AJ

B_1_DP0

US

11

AJ

B_1_DM0

US

9

AD

B_1_DP1

US

8

AD

B_1_DM1

US

6

AM

BC_I2C_SCL

US

7

AM

BC_I2C_SDA

US

10

AK

B_OC0_L/AGPIO16

US

9

AK

B_OC1_L/AGPIO17

US

9

AL

B_OC2_L/AGPIO18

US

8

AL

B_OC3_L/AGPIO24

US

7

AW

PIO14/USB_OC4_L

AG

12

AT

PIO13/USB_OC5_L

AG

@

CC_TPM

+V

28 0_0201_5%TPM_L@

RX

U_SPI_D1

AP

1 0_0201_5%TPM_S@

RX

U_SPI_D0

AP

2 0_0201_5%TPM_S@

RX

I_IRQ#

SP

3 0_0201_5%TPM_S@

RX

C_AD3

LP

32 0_0201_5%TPM_L@

RX

U_SPI_CLK_R

4 0_0201_5%TPM_S@

RX

U_SPI_TPMCS#

5 0_0201_5%TPM_S@

RX

6 0_0201_5%TPM_S@

RX

KRUN#

36 0_0201_5%TPM_L@

CL

RX

CPD#

37 0_0201_5%TPM_L@

LP

RX

RIRQ

SE

CI_CLK_TPM

LP

C_FRAME#

LP

CX
12

TPM@

CLK/LPC/EMMC/SD/SPI/eSPI /UAR T

FP5 REV 0.90

RT 5 OF 13

PA

FP

FP5 REV 0.90

RT 10 OF 13

PA

1 2

31 0_0201_5%TPM_L@

RX

1 2

30 0_0201_5%TPM_L@

RX

1 2

29 0_0201_5%TPM_L@

RX

1 2

1 2
1 2
1 2
1 2

1 2
1 2

1 2
1 2
1 2

1 2

35 0_0201_5%TPM_L@

RX

1 2

33 0_0201_5%TPM_L@

RX

1 2

34 0_0201_5%TPM_L@

RX

5_BGA1140~D

1 2

UC1J

USB

5_BGA1140~D

FP

@

EG

C_PD_L/SD_CMD/AGPIO21

LP

D0/SD_DATA0/EGPIO104

LA

D1/SD_DATA1/EGPIO105

LA

D2/SD_DATA2/EGPIO106

LA

D3/SD_DATA3/EGPIO107

LA

LP

C_CLKRUN_L/AGPIO88

LP

LP

SE

RAME_L/EGPIO109

LF

C_RST_L/SD_WP_L/AGPIO32

LP

C_PME_L/SD_PWR_CTRL/AGPIO22

LP

I_ROM_REQ/EGPIO67

SP

I_ROM_GNT/AGPIO76

SP

PI_RESET_L/KBRST_L/AGPIO129

ES

PI_ALERT_L/LDRQ0_L/EGPIO10 8

ES

SP

SP

I_WP_L/ESPI_DAT2

SP

I_HOLD_L/ESPI_DAT3

SP

I_CS1_L/EGPIO118

SP

I_CS2_L/ESPI_CS_L/AGPIO30

SP

I_CS3_L/AGPIO31

SP

I_TPM_CS_L/AGPIO29

SP

RT0_RXD/EGPIO136

UA

RT0_TXD/EGPIO138

UA

RT0_RTS_L/UART2_RXD/EGPIO137

UA

RT0_CTS_L/UART2_TXD/EGPIO135

UA

RT0_INTR/AGPIO139

UA

PIO141/UART1_RXD

EG

PIO143/UART1_TXD

EG

PIO142/UART1_RTS_L/UART3_RXD

EG

PIO140/UART1_CTS_L/UART3_TXD

EG

PIO144/UART1_INTR

AG

4610K_0402_5%

RC

BC0_A2/USB_0_TXP0/DP3_TXP2

US

BC0_A3/USB_0_TXN0/DP3_TXN2

US

BC0_B11/USB_0_RXP0/DP3_TXP3

US

BC0_B10/USB_0_RXN0/DP3_TXN3

US

BC0_B2/DP3_TXP1

US

BC0_B3/DP3_TXN1

US

BC0_A11/DP3_TXP0

US

BC0_A10/DP3_TXN0

US

BC1_A2/USB_0_TXP3/DP2_TXP2

US

BC1_A3/USB_0_TXN3/DP2_TXN2

US

BC1_B11/USB_0_RXP3/DP2_TXP3

US

BC1_B10/USB_0_RXN3/DP2_TXN3

US

BC1_B2/DP2_TXP1

US

BC1_B3/DP2_TXN1

US

BC1_A11/DP2_TXP0

US

BC1_A10/DP2_TXN0

US

16

T1

M_20

TP

T_RST#

PL

KRUN#_R_TPM

CL

CPD#_R

LP

PIO70/SD_CLK

CCLK0/EGPIO74

CCLK1/EGPIO75

RIRQ/AGPIO87

PIO68/SD_CD

AG

I_CLK/ESPI_CLK

I_DI/ESPI_DATA

WL

B_0_TXP1

US

B_0_TXN1

US

B_0_RXP1

US

B_0_RXN1

US

B_0_TXP2

US

B_0_TXN2

US

B_0_RXP2

US

B_0_RXN2

US

B_1_TXP0

US

B_1_TXN0

US

B_1_RXP0

US

B_1_RXN0

US

M_24

TP

C

13

BD

14

BB

12

BB

11

BC

15

BB

15

BC

15

BA

13

BC

13

BB

12

BC

12

BA

11

BD

11

BA

13

BA

8

BC

8

BB

11

BB

6

BC

7

BB

9

BA

10

BB

I_DO

SP

10

BA

10

BC

9

BC

8

BA

6

BA

8

BD

16

BA

18

BB

17

BC

18

BA

18

BD

18

BC

17

BA

16

BC

19

BB

16

BB

_OFF#

2

AD

4

AD

2

AC

4

AC

4

AF

2

AF

3

AE

1

AE

3

AG

1

AG

9

AJ

8

AJ

4

AG

2

AG

7

AG

6

AG

2

AA

4

AA

Y1
Y3

1

AC

3

AC

2

AB

4

AB

4

AH

2

AH

7

AK

6

AK

UX

29

GP

30

GP

3

GP

6

GP

24

LA

21

LA

18

LA

15

LA

19

LC

20

LF

17

LR

27

SE

13

CL

28

LP

4

PP

5

TE

NPCT650VB2YX QFN 32P 5X5

UX

C

1

11

T1

IOS_ID1

VB

CPD#

LP

T1

KRUN#

CL

CI_CLK_TPM

KRUN# [27]

LP

CL

C_RST_A#

LP

RC

1 2

PIO25

661 0_0402_5%@

AG

RC

12

T1

RC

U_SPI_CLK

AP

1 2

U_SPI_D1

AP

U_SPI_D0

AP

U_SPI_D2

AP

U_SPI_D3

AP

U_SPI_CS1#

AP

I_IRQ#

SP

extra spi device

no

U_SPI_TPMCS#

AP

RT0_RXD

UA

01

T1

RT0_TXD

UA

02

T1

RT0_RTS#

UA

17

T1

RT0_CTS#

UA

18

T1

RT0_INTR

UA

19

T1

RGD_VGA

S_PWREN [26,55,57]

PW

PX

RGD_VGA [55]

PW

_OFF#

S_RST# [38]

WL

PX

_OFF# [20]

WL

PI_VCC

+S

B3_DP3_MTX_DRX_P2

US

B3_DP3_MTX_DRX_N2

US

B3_DP3_MRX_DTX_P3

US

B3_DP3_MRX_DTX_N3

US

B3_DP3_MTX_DRX_P1

US

B3_DP3_MTX_DRX_N1

US

B3_DP3_MRX_DTX_P0

US

B3_DP3_MRX_DTX_N0

US

B3_ATX_DRX_0_P1

US

B3_ATX_DRX_0_N1

US

B3_ARX_DTX_0_P1

US

B3_ARX_DTX_0_N1

US

B3_ATX_DRX_0_P2

US

B3_ATX_DRX_0_N2

US

B3_ARX_DTX_0_P2

US

B3_ARX_DTX_0_N2

US

U_DP2_P1

AP

U_DP2_N1

U_DP2_P0
U_DP2_N0

U_DP2_P1 [36]

AP

U_DP2_N1 [36]

AP

U_DP2_P0 [36]

AP

U_DP2_N0 [36]

AP

AP

AP
AP

TP

TPM_L@

IO0/SDA /XOR_OUT
IO1/SCL
IO2/GPX
IO3/BAD D

D0/MISO
D1/MOSI
D2/SPI_ IRQ#
D3

KL/SCLK
RAME#/SC S#
ESET#/S PI_RST #/SRES ET#
RIRQ
KRUN#/GPI O4/SINT#
CPD#

ST

VS

D

VD

D

VD

D

VD

NC
NC
NC
NC
NC
NC
NC

D

GN

D

GN

D

GN

D

GN

ND

PG
served

Re

1 place colse to UC7

D

VS

12

U_SPI_CLK_R [9]

AP

S_PWREN

PX

U_SPI_CS1#

AP

U_SPI_D2

AP

U_SPI_D3

AP

B 3.0 TYPEC

US

B 3.0 JUSB1

US

USB 3.0 JUSB2

+3

03~T109 T111~T114 put together as possible

T1

09

08

T1

T1

PL

1 2

14

T1

1

CONN@

JH

1

#

CS

3

#

WP

7

LD#

HO

4

D

SO

GN

ACES_91960-0084N_MX25L3206EM2I

MB SPI ROM

16

U_SPI_CS1#

AP

1

U_SPI_D1

AP

2

U_SPI_D2

AP

3

4

U_SPI_CLK

AP

RIRQ [27]

SE

C_FRAME# [27]

LP

T_RST# [9,19,20,27]

change to pop@0426

RC

12

615150P_0402_50V8J

CC

12

93810K_0402_5%

RC

8

C

VC

6

LK

SC

5

/SIO0

SI

2

/SIO1

.8VS

+1

.8V_ALW

+1

RC
RC

7

UC

#

CS

VC

SO

2

IO

SC

S

VS

W25Q128FWSIQ SOIC

1 2

680

RC
10_0402_5%

681100K_0402_5%

VS

+3

PI_VCC

+S

U_SPI_CLK_R

AP

U_SPI_D0

AP

U_SPI_D1

AP

1 2

1672 0_0603_5%

1 2

1700 0_0603_5%@

8

C

AP

7

3

IO

6

LK

5

SI

@EMI@

36

C6
10P_0402_50V8J

_RST#

KB

07

05

04

06

T1

T1

T1

T1

03

12

44922_0402_5%

RC

1 2

602 33_0402_5%

_SCI# [27]

EC

_RST# [27]

KB

74 10_0402_1%

U_SPI_CLK_R

AP

EMI@

CHANGE PORT @3/2

ed bios confirm

ne

AP

12

646

RC
10K_0402_5%

U_SPI_D3

AP

12

642 10K_0402_5%

RC

U_SPI_D2

AP

12

640 10K_0402_5%

RC

U_SPI_CS1#

AP

12

639 10K_0402_5%

RC

U_SPI_D0

AP

12

1706 10K_0402_5%

RC

B3_DP3_MTX_DRX_P2 [33]

US

B3_DP3_MTX_DRX_N2 [33]

US

B3_DP3_MRX_DTX_P3 [33]

US

B3_DP3_MRX_DTX_N3 [33]

US

B3_DP3_MTX_DRX_P1 [33]

US

B3_DP3_MTX_DRX_N1 [33]

US

B3_DP3_MRX_DTX_P0 [33]

US

B3_DP3_MRX_DTX_N0 [33]

US

B3_ATX_DRX_0_P1 [23]

US

B3_ATX_DRX_0_N1 [23]

US

B3_ARX_DTX_0_P1 [23]

US

B3_ARX_DTX_0_N1 [23]

US

B3_ATX_DRX_0_P2 [23]

US

B3_ATX_DRX_0_N2 [23]

US

B3_ARX_DTX_0_P2 [23]

US

B3_ARX_DTX_0_N2 [23]

US

1707 10K_0402_5%

RC

C_AD0 [27]

LP

C_AD1 [27]

LP

C_AD2 [27]

LP

C_AD3 [27]

LP

C_CLK0_EC [27]

LP

13

T1

PROCHOT# [8,27,46,48,53]

H_

U_SPI_TPMCS#

CRT

ALW

+3V

0.1U_0402_10V7K

10U_0402_6.3V6M

2, CX8: colse to Pin1

CX

1

1

CX

CX

2

M

1

B

+V

8
14
22

2
7

0

1

1

1

5

2

6

2

1

3

9
16
23
32
33
12

curity Classification

curity Classification

curity Classification

Se

Se

Se

ed Date

ed Date

ed Date

Issu

Issu

Issu

IS SHEE T OF ENGINEERING DRAWING IS THE P ROPRIETARY P ROPERTY OF CO MPAL ELEC TRONICS, INC. AND CONTAINS C ONFIDENTIAL

IS SHEE T OF ENGINEERING DRAWING IS THE P ROPRIETARY P ROPERTY OF CO MPAL ELEC TRONICS, INC. AND CONTAINS C ONFIDENTIAL

IS SHEE T OF ENGINEERING DRAWING IS THE P ROPRIETARY P ROPERTY OF CO MPAL ELEC TRONICS, INC. AND CONTAINS C ONFIDENTIAL

TH

TH

TH
AND TRAD E SECRE T INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUS TODY OF THE COMPETE NT D IVISION OF R&D

AND TRAD E SECRE T INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUS TODY OF THE COMPETE NT D IVISION OF R&D

AND TRAD E SECRE T INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUS TODY OF THE COMPETE NT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCL OSED TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF COMPA L E LECTRONICS, INC.

MAY BE USED BY OR DISCL OSED TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF COMPA L E LECTRONICS, INC.

MAY BE USED BY OR DISCL OSED TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF COMPA L E LECTRONICS, INC.

8

2

2

TPM@

TPM@

CC_TPM

CC_TPM

+V

12

27 0_0603_5%TPM_S@

RX

12

26 0_0603_5%TPM_L@

RX

_VCC

+SPI

TPM_S@

1 2

16

RX

10K_0402_5%

mpal Secret Data

mpal Secret Data

mpal Secret Data

Co

Co

Co

16/01/07 2017/01/07

16/01/07 2017/01/07

16/01/07 2017/01/07

20

20

20

D

+1.8VS+3V

I_IRQ#

SP

Deciphered Date

Deciphered Date

Deciphered Date

S

E

VS

+3

712

4G@

RC
10K_0402_5%

1 2

IOS_ID1

VB

711

2G@

RC
10K_0402_5%

1 2

12

635

@

CC
.1U_0402_16V7K

PI_VCC

+S

U_SPI_D3

U_SPI_CLK_R

AP

U_SPI_D0

AP

1 2

@EMI@

1

UX

0000AQ200

SA

M_S@

TP

IC NPCT750JAAYX QFN 32P TPM

S

TPM_L@: TPM LPC 650
TPM_S@:TPM SPI 750

mpal Electronics, Inc.

mpal Electronics, Inc.

mpal Electronics, Inc.

Co

Co

Co

e

e

e

Titl

Titl

Titl

4 SATA/CLK/USB/SPI

4 SATA/CLK/USB/SPI

4 SATA/CLK/USB/SPI

FP

FP

FP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

stom

stom

stom

Cu

Cu

Cu

-F121P

-F121P

-F121P

LA

LA

LA

Date: Sheet

Date: Sheet

Date: Sheet

10 61Thursday, November 09, 2017

10 61Thursday, November 09, 2017

10 61Thursday, November 09, 2017

E

of

of

of

3(X02)

3(X02)

3(X02)

0.

0.

0.

ain Func = CPU

M

C

1 1

C21 22U_0603_6.3V6M

1

2

A

CC32 180P_0402_50V8J

1.2V_DDR

C

C

C

C

C

C

C

C

C27 22U_0603_6.3V6M

C23 22U_0603_6.3V6M

C25 22U_0603_6.3V6M

C24 22U_0603_6.3V6M

C26 22U_0603_6.3V6M

C22 22U_0603_6.3V6M

1

1

1

1

1

2

2

2

2

2

C

C

C28 22U_0603_6.3V6M

C30 1U_0402_6.3V6K

C31 1U_0402_6.3V6K

C29 22U_0603_6.3V6M

1

1

1

1

1

2

2

2

2

2

+

1

2

All BU(on bottom side under SOC)

FOR DEBUG ONLY

C96 0_0402_5%

R

1 2

@

3VS

+

2 2

3VALW_APU

+

C

C

C

C67 1U_0402_6.3V6K

C68 1U_0402_6.3V6K

C66 22U_0603_6.3V6M

1

1

1

2

2

2

3 3

4 4

C

C

1

2

C
C80 22U_0603_6.3V6M

1

2

B

3VALW

+

C81 1U_0402_6.3V6K

C82 1U_0402_6.3V6K

1

1

2

2

O

1

0.1U_0603_25V7K

2

C
C83 1U_0402_6.3V6K

C6126 0_0402_5%

R

@

C
C1193

C
C79 22U_0603_6.3V6M

CH_PWR_EN[27]

P

3VS_APU

+

C

C

C

C1189 1U_0402_6.3V6K

C1190 1U_0402_6.3V6K

C65 10U_0603_6.3V6M

1

1

1

2

2

2

1.8V_ALW

+

C

C

C

C71 1U_0402_6.3V6K

C69 22U_0603_6.3V6M

C70 1U_0402_6.3V6K

1

1

1

2

2

2

1.8VS

+

CC73 1U_0402_6.3V6K

CC74 1U_0402_6.3V6K

CC72 22U_0603_6.3V6M

1

1

1

2

2

2

BU BO B U

0.9VS

C
C84 1U_0402_6.3V6K

1

1

2

2

C86 1U_0402_6.3V6K

C85 1U_0402_6.3V6K

1

2

C

C

+

CC87 1U_0402_6.3V6K

CC89 180P_0402_50V8J

CC88 1U_0402_6.3V6K

1

1

1

1

2

2

2

2

BU

1 2

C20

U

1

5

UT

N

O

I

2

ND

G

3

4

C

N

O

E

SY6288C20AAC_SOT23-5

@

TC (gen 9)reset circuit

R

A

C6127 10K_0402_5%@

R

3VALW_APU

+

1 2

3VALW

+

1.8V_ALW

+

0.9VALW

+

B

1.2V_DDR

+

CROSS VDDIO AND VSS SPLIT

A

1.8VS

+

1.8V_ALW

+

C
C33 180P_0402_50V8J

1

2

1 2

C97 0_0402_5%

R

1 2

C6125 0_0402_5%@

R

+

C

C

C75 22U_0603_6.3V6M

C76 1U_0402_6.3V6K

1

1

2

2

C
C34 180P_0402_50V8J

1

2

VDDP_ ALW

C

C

C77 1U_0402_6.3V6K

C78 1U_0402_6.3V6K

1

1

2

2

BO B UBO B U BO

1 2

C6129 0_0402_5%@

R

C6128 0_0402_5%@

R

B

12

0.22U_0402_10V6K

1.8V_ALW_APU

+

0.9VALW_APU

+

TC OF APU

R

RTC_APU_R

+

C90

C

lose to UC1

c

12

C801

R
10M_0402_5%

C

C

C36 0.22U_0402_10V6K

C35 0.22U_0402_10V6K

1

2

V

+

1

1U_0402_6.3V6K

2

C
C37 0.22U_0402_10V6K

1

2

DDIO_AUDIO

0.9VALW

C
C38 0.22U_0402_10V6K

1

1

2

2

C
C1191 22U_0603_6.3V6M

1

2

=20mil s

W

1

C91

C

2

RTCBATT_R

+

2

G

D

S

C27

Q
2N7002K_SOT23-3

13

APU_VDDSOC

+

1.2V_DDR

+

C
C1192 1U_0402_6.3V6K

1

2

+

1.8V_ALW_APU

+

3VALW_APU

+

0.9VALW_APU

+

+

+

0.9VS

TDC :10A
EDC: 13A

TDC :6A

TDC :0.2A

DDIO_AUDIO

V

TDC :0.25A

3VS_APU

TDC :2A

1.8VS

+

TDC :0.5A

TDC :0.25A

TDC :1A

TDC :4A

TDC :4.5UA

RTC_APU_R

+

RTC_APU_R

1 2

C98 1K_0402_5%

R

12

@

LRP1

C
SHORT PADS

TC_DET# [9]

R

C

15

M

18

M

19

M

16

N

18

N

20

N

17

P

19

P

18

R

20

R

19

T

18

U

20

U

19

V

18

W

20

W

19

Y

32

T

28

V

28

W

32

W

22

Y

25

Y

28

Y

A20

A

A23

A

A26

A

A28

A

A32

A

C20

A

C22

A

C25

A

C28

A

D23

A

D26

A

D28

A

D32

A

E20

A

E22

A

E25

A

E28

A

F23

A

F26

A

F28

A

F32

A

G20

A

G22

A

G25

A

G28

A

J20

A

J23

A

J26

A

J28

A

J32

A

K28

A

L28

A

L32

A

P12

A

L18

A

M17

A

L20

A

M19

A

L19

A

M18

A

L17

A

M16

A

L14

A

L15

A

M14

A

L13

A

M12

A

M13

A

N12

A

N13

A

T11

A

RTC_APU

+

eed OPEN

N
for Clear CMOS

C

DDCR_SOC_1

V

DDCR_SOC_2

V

DDCR_SOC_3

V

DDCR_SOC_4

V

DDCR_SOC_5

V

DDCR_SOC_6

V

DDCR_SOC_7

V

DDCR_SOC_8

V

DDCR_SOC_9

V

DDCR_SOC_10

V

DDCR_SOC_11

V

DDCR_SOC_12

V

DDCR_SOC_13

V

DDCR_SOC_14

V

DDCR_SOC_15

V

DDCR_SOC_16

V

DDCR_SOC_17

V

DDIO_MEM_S3_1

V

DDIO_MEM_S3_2

V

DDIO_MEM_S3_3

V

DDIO_MEM_S3_4

V

DDIO_MEM_S3_5

V

DDIO_MEM_S3_6

V

DDIO_MEM_S3_7

V

DDIO_MEM_S3_8

V

DDIO_MEM_S3_9

V

DDIO_MEM_S3_10

V

DDIO_MEM_S3_11

V

DDIO_MEM_S3_12

V

DDIO_MEM_S3_13

V

DDIO_MEM_S3_14

V

DDIO_MEM_S3_15

V

DDIO_MEM_S3_16

V

DDIO_MEM_S3_17

V

DDIO_MEM_S3_18

V

DDIO_MEM_S3_19

V

DDIO_MEM_S3_20

V

DDIO_MEM_S3_21

V

DDIO_MEM_S3_22

V

DDIO_MEM_S3_23

V

DDIO_MEM_S3_24

V

DDIO_MEM_S3_25

V

DDIO_MEM_S3_26

V

DDIO_MEM_S3_27

V

DDIO_MEM_S3_28

V

DDIO_MEM_S3_29

V

DDIO_MEM_S3_30

V

DDIO_MEM_S3_31

V

DDIO_MEM_S3_32

V

DDIO_MEM_S3_33

V

DDIO_MEM_S3_34

V

DDIO_MEM_S3_35

V

DDIO_MEM_S3_36

V

DDIO_MEM_S3_37

V

DDIO_MEM_S3_38

V

DDIO_MEM_S3_39

V

DDIO_MEM_S3_40

V

DDIO_AUDIO

V

DD_33_1

V

DD_33_2

V

DD_18_1

V

DD_18_2

V

DD_18_S5_1

V

DD_18_S5_2

V

DD_33_S5_1

V

DD_33_S5_2

V

DDP_S5_1

V

DDP_S5_2

V

DDP_S5_3

V

DDP_1

V

DDP_2

V

DDP_3

V

DDP_4

V

DDP_5

V

DDBT_RTC_G

V

@

D

UC1F

POWER

DDCR_1

V

DDCR_2

V

DDCR_3

V

DDCR_4

V

DDCR_5

V

DDCR_6

V

DDCR_7

V

DDCR_8

V

DDCR_9

V

DDCR_10

V

DDCR_11

V

DDCR_12

V

DDCR_13

V

DDCR_14

V

DDCR_15

V

DDCR_16

V

DDCR_17

V

DDCR_18

V

DDCR_19

V

DDCR_20

V

DDCR_21

V

DDCR_22

V

DDCR_23

V

DDCR_24

V

DDCR_25

V

DDCR_26

V

DDCR_27

V

DDCR_28

V

DDCR_29

V

DDCR_30

V

DDCR_31

V

DDCR_32

V

DDCR_33

V

DDCR_34

V

DDCR_35

V

DDCR_36

V

DDCR_37

V

DDCR_38

V

DDCR_39

V

DDCR_40

V

DDCR_41

V

DDCR_42

V

DDCR_43

V

DDCR_44

V

DDCR_45

V

DDCR_46

V

DDCR_47

V

DDCR_48

V

DDCR_49

V

DDCR_50

V

DDCR_51

V

DDCR_52

V

DDCR_53

V

DDCR_54

V

DDCR_55

V

DDCR_56

V

DDCR_57

V

DDCR_58

V

DDCR_59

V

DDCR_60

V

DDCR_61

V

DDCR_62

V

DDCR_63

V

DDCR_64

V

DDCR_65

V

DDCR_66

V

DDCR_67

V

DDCR_68

V

DDCR_69

V

DDCR_70

V

DDCR_71

V

DDCR_72

V

DDCR_73

V

DDCR_74

V

DDCR_75

V

DDCR_76

V

DDCR_77

V

DDCR_78

V

DDCR_79

V

DDCR_80

V

DDCR_81

V

DDCR_82

V

DDCR_83

V

FP5 REV 0.90

ART 6 OF 13

P

P5_BGA1140~D

F

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

I

I

I

HIS SHEE T OF ENGINEERING DRAWING IS THE P ROPRIETARY P ROPERTY OF CO MPAL ELEC TRONICS, INC. AND CONTAINS C ONFIDENTIAL

HIS SHEE T OF ENGINEERING DRAWING IS THE P ROPRIETARY P ROPERTY OF CO MPAL ELEC TRONICS, INC. AND CONTAINS C ONFIDENTIAL

HIS SHEE T OF ENGINEERING DRAWING IS THE P ROPRIETARY P ROPERTY OF CO MPAL ELEC TRONICS, INC. AND CONTAINS C ONFIDENTIAL

T

T

T
AND TRAD E SECRE T INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUS TODY OF THE COMPETE NT D IVISION OF R&D

AND TRAD E SECRE T INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUS TODY OF THE COMPETE NT D IVISION OF R&D

AND TRAD E SECRE T INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUS TODY OF THE COMPETE NT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCL OSED TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF COMPA L E LECTRONICS, INC.

MAY BE USED BY OR DISCL OSED TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF COMPA L E LECTRONICS, INC.

MAY BE USED BY OR DISCL OSED TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF COMPA L E LECTRONICS, INC.

G
G
G
G
H
H
H
K
K
K
L
M
M
N
P
P
P
P
R
R
R
T
T
T
T
T
U
U
V
V
V
W
W
W
W
Y
Y
Y
Y
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

RTC_APU

+

ssued Date

ssued Date

ssued Date

7
10
12
14
8
11
15
7
12
14
8
7
10
14
7
10
13
15
8
14
16
7
10
13
15
17
14
16
13
15
17

7
10
14

16
8
13
15
17
A7
A10
A14
A16
A18
B13
B15
B17
B19
C14
C16
C18
D7
D10
D13
D15
D17
D19
E8
E14
E16
E18
F7
F10
F13
F15
F17
F19
G14
G16
G18
H13
H15
H17
H19
J7
J10
J14
J16
J18
K13
K15
K17
K19

1

C

0.1U_0603_25V7K

2

DC: 35A

T
EDC: 45A

APU_VDDCORE

+

ll BU(on bottom side under SOC)

A

APU_VDDCORE

+

APU_VDDSOC

+

APU_VDDCORE

+

o=1.5V

V

3

out

V

1

in

V

2

ND

G

C8

U

C92

AP2138N-1.5TRG1_SOT23-3

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

016/01/07 2017/01/07

016/01/07 2017/01/07

016/01/07 2017/01/07

2

2

2

D

CHGRTC

+

1

2

+

C
680P_0603_50V8J

RTCVCC

C93

Deciphered Date

Deciphered Date

Deciphered Date

C
C51 22U_0603_6.3V6M

1

2

2

C
C39 180P_0402_50V8J

1

2

C
C52 22U_0603_6.3V6M

1

2

P2

J

JUMP_43X39

HORT

S

1

C
C61 180P_0402_50V8J

C

C

C54 22U_0603_6.3V6M

C53 22U_0603_6.3V6M

1

2

112

C1

D

athode

c

BAS40C_SOT23-3

E

C

C

C

C

C

C42 22U_0603_6.3V6M

C43 22U_0603_6.3V6M

C41 22U_0603_6.3V6M

C40 22U_0603_6.3V6M

C44 22U_0603_6.3V6M

1

1

1

1

2

2

2

2

C
C62 1U_0402_6.3V6K

1

1

2

2

C
C55 22U_0603_6.3V6M

1

1

2

2

3VLP

+

RTCBATT_R

+

3

node

a

2

node

a

C

C

C

C

C

C

C50 22U_0603_6.3V6M

C46 22U_0603_6.3V6M

C47 22U_0603_6.3V6M

C48 22U_0603_6.3V6M

C49 22U_0603_6.3V6M

C45 22U_0603_6.3V6M

1

1

1

1

1

1

1

2

2

2

2

2

2

2

C

C

C

C

C

C

C

C63 22U_0603_6.3V6M

C60 22U_0603_6.3V6M

C57 22U_0603_6.3V6M

C58 22U_0603_6.3V6M

C56 22U_0603_6.3V6M

C64 22U_0603_6.3V6M

C59 22U_0603_6.3V6M

1

1

1

1

1

1

1

2

2

2

2

2

2

2

1 2

C99 1K_0402_5%

R

itle

itle

itle

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

ustom

ustom

ustom

C

C

C

Date: Sheetof

Date: Sheetof

Date: Sheetof

RTCBATT

+

CHGRTC

+

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

P4 PWR

P4 PWR

P4 PWR

F

F

F

A-F121P

A-F121P

A-F121P

L

L

L

E

11 61Thursday, November 09, 2017

11 61Thursday, November 09, 2017

11 61Thursday, November 09, 2017

.3(X02)

.3(X02)

.3(X02)

0

0

0

ain Func = CPU

M

D D

C C

5

UC1G

ND

G

12

N

SS_316

V

3

A

SS_1

V

5

A

SS_2

V

7

A

SS_3

V

10

A

SS_4

V

12

A

SS_5

V

14

A

SS_6

V

16

A

SS_7

V

19

A

SS_8

V

21

A

SS_9

V

23

A

SS_10

V

26

A

SS_11

V

30

A

SS_12

V

3

C

SS_13

V

32

C

SS_14

V

16

D

SS_15

V

18

D

SS_16

V

20

D

SS_17

V

7

E

SS_18

V

8

E

SS_19

V

10

E

SS_20

V

11

E

SS_21

V

12

E

SS_22

V

13

E

SS_23

V

14

E

SS_24

V

15

E

SS_25

V

16

E

SS_26

V

18

E

SS_27

V

19

E

SS_28

V

20

E

SS_29

V

21

E

SS_30

V

22

E

SS_31

V

23

E

SS_32

V

25

E

SS_33

V

26

E

SS_34

V

27

E

SS_35

V

5

F

SS_36

V

28

F

SS_37

V

1

G

SS_38

V

5

G

SS_39

V

16

G

SS_40

V

19

G

SS_41

V

21

G

SS_42

V

23

G

SS_43

V

26

G

SS_44

V

28

G

SS_45

V

32

G

SS_46

V

5

H

SS_47

V

13

H

SS_48

V

18

H

SS_49

V

20

H

SS_50

V

22

H

SS_51

V

25

H

SS_52

V

28

H

SS_53

V

1

K

SS_54

V

5

K

SS_55

V

16

K

SS_56

V

19

K

SS_57

V

21

K

SS_58

V

22

K

SS_59

V

26

K

SS_60

V

28

K

SS_61

V

FP5 REV 0.90

ART 7 OF 13

P

@

P5_BGA1140~D

F

32

K

SS_62

V

5

L

SS_63

V

13

L

SS_64

V

15

L

SS_65

V

18

L

SS_66

V

20

L

SS_67

V

25

L

SS_68

V

28

L

SS_69

V

1

M

SS_70

V

5

M

SS_71

V

12

M

SS_72

V

21

M

SS_73

V

23

M

SS_74

V

26

M

SS_75

V

28

M

SS_76

V

32

M

SS_77

V

4

N

SS_78

V

5

N

SS_79

V

8

N

SS_80

V

11

N

SS_81

V

13

N

SS_82

V

15

N

SS_83

V

17

N

SS_84

V

19

N

SS_85

V

22

N

SS_86

V

25

N

SS_87

V

28

N

SS_88

V

1

P

SS_89

V

5

P

SS_90

V

14

P

SS_91

V

16

P

SS_92

V

18

P

SS_93

V

20

P

SS_94

V

23

P

SS_95

V

26

P

SS_96

V

28

P

SS_97

V

32

P

SS_98

V

5

R

SS_99

V

11

R

SS_100

V

12

R

SS_101

V

13

R

SS_102

V

15

R

SS_103

V

17

R

SS_104

V

19

R

SS_105

V

22

R

SS_106

V

25

R

SS_107

V

28

R

SS_108

V

30

R

SS_109

V

1

T

SS_110

V

5

T

SS_111

V

14

T

SS_112

V

16

T

SS_113

V

18

T

SS_114

V

20

T

SS_115

V

23

T

SS_116

V

26

T

SS_117

V

28

T

SS_118

V

13

U

SS_119

V

15

U

SS_120

V

17

U

SS_121

V

19

U

SS_122

V

5

V

SS_123

V

UC1M

B B

A A

18

A

18

C

15

A

15

C

16

B

16

C

19

C

18

B

17

B

17

D

12

D

12

B

13

C

13

A

11

B

12

C

13

J

AM0_CSI2_CLOCKP

C

AM0_CSI2_CLOCKN

C

AM0_CSI2_DATAP0

C

AM0_CSI2_DATAN0

C

AM0_CSI2_DATAP1

C

AM0_CSI2_DATAN1

C

AM0_CSI2_DATAP2

C

AM0_CSI2_DATAN2

C

AM0_CSI2_DATAP3

C

AM0_CSI2_DATAN3

C

AM1_CSI2_CLOCKP

C

AM1_CSI2_CLOCKN

C

AM1_CSI2_DATAP0

C

AM1_CSI2_DATAN0

C

AM1_CSI2_DATAP1

C

AM1_CSI2_DATAN1

C

SVD_6

R

@

CAMERAS

FP5 REV 0.90
ART 13 OF 13

P

P5_BGA1140~D

F

AM0_CLK

C

AM0_I2C_SCL

C

AM0_I2C_SDA

C

AM0_SHUTDOWN

C

AM1_CLK

C

AM1_I2C_SCL

C

AM1_I2C_SDA

C

AM1_SHUTDOWN

C

AM_PRIV_LED

C

AM_IR_ILLU

C

4

A
A
A
A
A
A

A
A
A
A

3

UC1H

ND

G

8

V

SS_124

V

11

V

SS_125

V

12

V

SS_126

V

14

V

SS_127

V

16

V

SS_128

V

18

V

SS_129

V

20

V

SS_130

V

22

V

SS_131

V

25

V

SS_132

V

1

W

SS_133

V

5

W

SS_134

V

13

W

SS_135

V

15

W

SS_136

V

17

W

SS_137

V

19

W

SS_138

V

23

W

SS_139

V

26

W

SS_140

V

5

Y

SS_141

V

11

Y

SS_142

V

12

Y

SS_143

V

14

Y

SS_144

V

16

Y

SS_145

V

18

Y

SS_146

V

20

Y

SS_147

V

A1

A

SS_148

V

A5

A

SS_149

V

A13

A

SS_150

V

A15

A

SS_151

V

A17

A

SS_152

V

A19

A

SS_153

V

B14

A

SS_154

V

B16

A

SS_155

V

B18

A

SS_156

V

B20

A

SS_157

V

C5

A

SS_158

V

C8

A

SS_159

V

C11

SS_160

V

C12

SS_161

V

C13

SS_162

V

C15

SS_163

V

C17

SS_164

V

C19

SS_165

V

D1

A

SS_166

V

D5

A

SS_167

V

D14

SS_168

V

D16

SS_169

V

D18

SS_170

V

D20

SS_171

V

E5

A

SS_172

V

E11

A

SS_173

V

E12

A

SS_174

V

E13

A

SS_175

V

E15

A

SS_176

V

E17

A

SS_177

V

E19

A

SS_178

V

F1

A

SS_179

V

F5

A

SS_180

V

F14

A

SS_181

V

F16

A

SS_182

V

F18

A

SS_183

V

F20

A

SS_184

V

G5

A

SS_185

V

FP5 REV 0.90

ART 8 OF 13

P

@

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

P5_BGA1140~D

F

SS_186

SS_187

SS_188

SS_189

SS_190

SS_191

SS_192

SS_193

SS_194

SS_195

SS_196

SS_197

SS_198

SS_199

SS_200

SS_201

SS_202

SS_203

SS_204

SS_205

SS_206

SS_207

SS_208

SS_209

SS_210

SS_211

SS_212

V

SS_214

SS_215

SS_216

SS_217

SS_218

SS_219

SS_220

SS_221

SS_222

SS_223

SS_224

SS_225

SS_226

SS_227

SS_228

SS_229

SS_230

SS_231

SS_232

SS_233

SS_234

SS_235

SS_236

SS_237

SS_238

SS_239

SS_240

SS_241

SS_242

SS_243

SS_244

SS_245

SS_246

SS_247

G8

A

G11

A

G12

A

G13

A

G15

A

G17

A

G19

A

H14

A

H16

A

H18

A

H20

A

J1

A

J5

A

J13

A

J15

A

J17

A

J19

A

K5

A

K8

A

K11

A

K12

A

K14

A

K16

A

K18

A

K20

A

K22

A

K25

A

L1

A

SS_213

L5

A

L7

A

L10

A

L12

A

L16

A

L23

A

L26

A

M5

A

M8

A

M15

A

M20

A

M22

A

M25

A

M28

A

N1

A

N5

A

N7

A

N10

A

N15

A

N18

A

N21

A

N23

A

N26

A

N28

A

N32

A

P5

A

P8

A

P13

A

P15

A

P18

A

P20

A

P25

A

P28

A

R1

A

2

1

UC1K

GND/RSVD

R5

A

SS_248

V

R7

A

SS_249

V

R12

A

SS_250

V

R14

A

SS_251

V

R16

A

SS_252

V

R19

A

SS_253

V

R21

A

SS_254

V

R26

A

SS_255

V

R28

A

SS_256

V

R32

A

SS_257

V

U5

A

SS_258

V

U8

A

SS_259

V

U11

A

SS_260

V

U13

A

SS_261

V

U15

A

SS_262

V

U18

A

SS_263

V

U20

A

SS_264

V

U22

A

SS_265

V

U25

A

SS_266

V

U28

A

SS_267

V

V1

A

SS_268

V

V5

A

SS_269

V

V7

A

SS_270

V

V10

A

SS_271

V

V12

A

SS_272

V

V14

A

SS_273

V

V16

A

SS_274

V

V19

A

SS_275

V

V21

A

SS_276

V

V23

A

SS_277

V

V26

A

SS_278

V

V28

A

SS_279

V

V32

A

SS_280

V

W5

A

SS_281

V

W28

A

SS_282

V

Y6

A

SS_283

V

Y7

A

SS_284

V

Y8

A

SS_285

V

Y10

A

SS_286

V

Y11

A

SS_287

V

Y12

A

SS_288

V

Y13

A

SS_289

V

Y14

A

SS_290

V

Y15

A

SS_291

V

Y16

A

SS_292

V

Y18

A

SS_293

V

Y19

A

SS_294

V

Y20

A

SS_295

V

Y21

A

SS_296

V

Y22

A

SS_297

V

Y23

A

SS_298

V

Y25

A

SS_299

V

Y26

A

SS_300

V

Y27

A

SS_301

V

B1

B

SS_302

V

B20

B

SS_303

V

B32

B

SS_304

V

D3

B

SS_305

V

D7

B

SS_306

V

D10

B

SS_307

V

D12

B

SS_308

V

D14

B

SS_309

V

FP5 REV 0.90

ART 11 OF 13

P

@

V

V

V

V

V

V

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

P5_BGA1140~D

F

SS_310

SS_311

SS_312

SS_313

SS_314

SS_315

R

R

R

R

R

SVD_10

SVD_11

SVD_12

SVD_13

SVD_22

SVD_23

SVD_30

SVD_31

SVD_37

SVD_44

SVD_49

SVD_50

SVD_57

SVD_58

SVD_59

SVD_60

SVD_69

SVD_70

SVD_71

SVD_74

SVD_75

SVD_78

SVD_79

SVD_80

SVD_81

SVD_82

SVD_83

SVD_87

SVD_88

SVD_14

SVD_84

SVD_85

SVD_86

D16

B

D19

B

D21

B

D23

B

D26

B

D30

B

20

B

SVD_1

3

G

SVD_5

20

J

SVD_7

3

K

SVD_8

6

K

SVD_9

20

K

3

M

6

M

13

M

6

P

22

P

3

T

6

T

29

T

6

W

21

W

22

W

21

Y

27

Y

A3

A

A6

A

C29

A

D3

A

D6

A

F3

A

F6

A

F30

A

J6

A

J24

A

K23

A

K27

A

L3

A

N29

A

N31

A

14

M

L6

A

L11

A

N16

A

UC1L

SVD

P5 REV 0.90

F

ART 12 OF 13

P

R

P5_BGA1140~D

F

A9

A

SVD_62

R

A8

A

SVD_61

R

C6

A

SVD_65

R

D11

A

SVD_72

R

C9

A

SVD_67

R

A11

A

SVD_63

R

12

T

SVD_33

R

D12

A

SVD_73

R

6

Y

SVD_53

R

7

Y

SVD_54

R

8

W

SVD_45

R

9

W

SVD_46

R

11

T

SVD_32

15

B

15

D

14

C

13

B

10

B

11

A

11

C

11

D

13

D

10

D

R

C7

A

SVD_66

R

9

Y

SVD_55

R

10

Y

SVD_56

R

11

W

SVD_47

R

12

W

SVD_48

R

9

V

SVD_38

R

10

V

SVD_39

R

A12

A

SVD_64

R

C10

A

SVD_68

R

@

curity Classification

curity Classification

curity Classification

Se

Se

Se

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFEREDF ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFEREDF ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFEREDF ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUTPRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUTPRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUTPRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

016/01/07 2017/01/07

016/01/07 2017/01/07

016/01/07 2017/01/07

2

2

2

3

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

Deciphered Date

Deciphered Date

Deciphered Date

T

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet

Date: Sheet

2

Date: Sheet

P4 GND

P4 GND

P4 GND

F

F

F

ustom

ustom

ustom

C

C

C

A-F121P

A-F121P

A-F121P

L

L

L

12 61Thursday, November 09, 2017

12 61Thursday, November 09, 2017

12 61Thursday, November 09, 2017

1

.3(X02)

.3(X02)

.3(X02)

0

0

0

f

f

f

o

o

o

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

itle

itle

itle

T

T

ain Func = DIMM1

M

1 1

2 2

3 3

Address: 000>

<

4 4

3VS

+

A

1.2V_DDR

+

DR_A_DQ5

D

DR_A_DQ1

D

DR_A_DQS0#

+

2.5V_MEM

1

C

2

D

DR_A_DQS0

D

DR_A_DQ7

D

DR_A_DQ3

D

DR_A_DQ13

D

DR_A_DQ9

D

DR_A_DM1

D

DR_A_DQ15

D

DR_A_DQ10

D

DR_A_DQ21

D

DR_A_DQ17

D

DR_A_DQS2#

D

DR_A_DQS2

D

DR_A_DQ23

D

DR_A_DQ19

D

DR_A_DQ29

D

DR_A_DQ25

D

DR_A_DM3

D

DR_A_DQ30

D

DR_A_DQ26

D

DR_A_CKE0

D

DR_A_BG1

D

DR_A_BG0

D

DR_A_MA12

D

DR_A_MA9

D

DR_A_MA8

D

DR_A_MA6

D

DR_A_MA3

D

DR_A_MA1

D

DR_A_CLK0

D

DR_A_CLK0#

D

DR_A_PAR

D

DR_A_BA1

D

DR_A_CS0#

D

DR_A_WE#

D

DR_A_ODT0

D

DR_A_CS1#

D

DR_A_ODT1

D

DR_A_DQ37

D

DR_A_DQ33

D

DR_A_DQS4#

D

DR_A_DQS4

D

DR_A_DQ38

D

DR_A_DQ34

D

DR_A_DQ44

D

DR_A_DQ40

D

DR_A_DM5

D

DR_A_DQ46

D

DR_A_DQ42

D

DR_A_DQ52

D

DR_A_DQ49

D

DR_A_DQS6#

D

DR_A_DQS6

D

DR_A_DQ55

D

DR_A_DQ51

D

DR_A_DQ61

D

DR_A_DQ56

D

DR_A_DM7

D

DR_A_DQ62

D

DR_A_DQ58

D

1
U_0402_6.3V6K

D39

DR_A_DQS0#[7]

D

DR_A_DQS0[7]

D

DR_A_DQS2#[7]

D

DR_A_DQS2[7]

D

DR_A_CKE0[7]

D

DR_A_BG1[7]

D

DR_A_BG0[7]

D

DR_A_CLK0[7]

D

DR_A_CLK0#[7]

D

DR_A_PAR[7]

D

DR_A_BA1[7]

D

DR_A_CS0#[7]

D

DR_A_MA14_WE#[7]

D

DR_A_ODT0[ 7]

D
DR_A_CS1#[7]

D

DR_A_ODT1[ 7]

D

DR_A_DQS4#[7]

D

DR_A_DQS4[7]

D

DR_A_DQS6#[7]

D

DR_A_DQS6[7]

D

PU_SCLK0[9,14,2 2,36]

A

1

D38

C
1

U_0402_6.3V6K

2

A

JDIMM1

1

SS1

V

3

Q5

D

5

SS3

V

7

Q1

D

9

SS5

V

11

QS0_c

D

13

QS0_t

D

15

SS8

V

17

Q7

D

19

SS10

V

21

Q3

D

23

SS12

V

25

Q13

D

27

SS14

V

29

Q9

D

31

SS16

V

33

M1_n/DBI_n

D

35

SS17

V

37

Q15

D

39

SS19

V

41

Q10

D

43

SS21

V

45

Q21

D

47

SS23

V

49

Q17

D

51

SS25

V

53

QS2_c

D

55

QS2_t

D

57

SS28

V

59

Q23

D

61

SS30

V

63

Q19

D

65

SS32

V

67

Q29

D

69

SS34

V

71

Q25

D

73

SS36

V

75

M3_n/DBI3_n

D

77

SS37

V

79

Q30

D

81

SS39

V

83

Q26

D

85

SS41

V

87

B5/NC

C

89

SS43

V

91

B1/NC

C

93

SS45

V

95

QS8_c

D

97

QS8_t

D

99

SS48

V

101

B2/NC

C

103

SS50

V

105

B3/NC

C

107

SS52

V

109

KE0

C

111

DD1

V

113

G1

B

115

G0

B

117

DD3

V

119

12

A

121

9

A

123

DD5

V

125

8

A

127

6

A

129

DD7

V

131

3

A

133

1

A

135

DD9

V

137

K0_t

C

139

K0_c

C

141

DD11

V

143

ARITY

P

145

A1

B

147

DD13

V

149

S0_n

C

151

E_n/A14

W

153

DD15

V

155

DT0

O

157

S1_n

C

159

DD17

V

161

DT1

O

163

DD19

V

165

1, CS3_n,NC

C

167

SS53

V

169

Q37

D

171

SS55

V

173

Q33

D

175

SS57

V

177

QS4_c

D

179

QS4_t

D

181

SS60

V

183

Q38

D

185

SS62

V

187

Q34

D

189

SS64

V

191

Q44

D

193

SS66

V

195

Q40

D

197

SS68

V

199

M5_n/DBI5_n

D

201

SS69

V

203

Q46

D

205

SS71

V

207

Q42

D

209

SS73

V

211

Q52

D

213

SS75

V

215

Q49

D

217

SS77

V

219

QS6_c

D

221

QS6_t

D

223

SS80

V

225

Q55

D

227

SS82

V

229

Q51

D

231

SS84

V

233

Q61

D

235

SS86

V

237

Q56

D

239

SS88

V

241

M7_n/DBI7_n

D

243

SS89

V

245

Q62

D

247

SS91

V

249

Q58

D

251

SS93

V

253

CL

S

255

DDSPD

V

257

PP1

V

259

PP2

V

261

ND1

G

OTES_ADDR0206-P00 1A02~D

L

DEREN_40-4227 1-26001RHF

SP07001CY0 L

IMM_A H:4mm RVS

D

CONN@

M0_n/DBI0_n

D

M2_n/DBI2_n

D

M8_n/DBI_n/NC

D

VENT_n/NF

E

R

C

0/CS2_n/NC

C

M4_n/DBI4_n

D

M6_n/DBI6_n

D

V

V

V
QS1_c

D
D

V

V

V

V

V

V

V

V

V

V
QS3_c

D
D

V

V

V
B4/NC

C

V
B0/NC

C

V

V
B6/NC

C

V
B7/NC

C

V

ESET_n

R

A

LERT_n

A

V

K1_t/NF

C

K1_c/NF

C

V

A
V

AS_n/A16

V

AS_n/A15

V

REFCA

V

V

V

V

V

V

V

V

V
QS5_c

D
D

V

V

V

V

V

V

V

V

V

V
QS7_c

D
D

V

V

V

B

1.2V_DDR

DR_A_DQ4

D

DR_A_DQ0

D

DR_A_DM0

D

DR_A_DQ6

D

DR_A_DQ2

D

DR_A_DQ12

D

DR_A_DQ8

D

DR_A_DQS1#

D

DR_A_DQS1

D

DR_A_DQ14

D

DR_A_DQ11

D

DR_A_DQ20

D

DR_A_DQ16

D

DR_A_DM2

D

DR_A_DQ22

D

DR_A_DQ18

D

DR_A_DQ28

D

DR_A_DQ24

D

DR_A_DQS3#

D

DR_A_DQS3

D

DR_A_DQ31

D

DR_A_DQ27

D

DR_A_RST#

D

DR_A_CKE1

D

DR_A_ACT#

D

DR_A_ALERT#

D

DR_A_MA11

D

DR_A_MA7

D

DR_A_MA5

D

DR_A_MA4

D

DR_A_MA2

D

DR_A_EVENT#

D

DR_A_CLK1

D

DR_A_CLK1#

D

DR_A_MA0

D

DR_A_MA10

D

DR_A_BA0

D

DR_A_RAS#

D

DR_A_CAS#

D

DR_A_MA13

D

DR_A_DQ36

D

DR_A_DQ32

D

DR_A_DM4

D

DR_A_DQ39

D

DR_A_DQ35

D

DR_A_DQ45

D

DR_A_DQ41

D

DR_A_DQS5#

D

DR_A_DQS5

D

DR_A_DQ47

D

DR_A_DQ43

D

DR_A_DQ53

D

DR_A_DQ48

D

DR_A_DM6

D

DR_A_DQ54

D

DR_A_DQ50

D

DR_A_DQ60

D

DR_A_DQ57

D

DR_A_DQS7#

D

DR_A_DQS7

D

DR_A_DQ63

D

DR_A_DQ59

D

+

DR_A_DQS1# [7 ]

D

DR_A_DQS1 [7]

D

DR_A_DQS3# [7]

D

DR_A_DQS3 [ 7]

D

DR_A_RST# [7]

D

DR_A_CKE1 [7 ]

D

DR_A_ACT# [7]

D

DR_A_ALERT# [7 ]

D

DR_A_EVENT# [7]

D

DR_A_CLK1 [7 ]

D
DR_A_CLK1# [7]

D

DR_A_BA0 [7]

D

DR_A_MA16_RAS# [7]

D

DR_A_MA15_CAS# [7]

D

DR_A_DQS5# [7]

D

DR_A_DQS5 [ 7]

D

DR_A_DQS7# [7]

D

DR_A_DQS7 [ 7]

D

PU_SDATA0 [9,14, 22,36]

A

2

SS2

V

4

Q4

D

6

SS4

V

8

Q0

D

10

SS6

V

12
14

SS7

V

16

Q6

D

18

SS9

V

20

Q2

D

22

SS11

24

Q12

D

26

SS13

28

Q8

D

30

SS15

32
34

QS1_t

36

SS18

38

Q14

D

40

SS20

42

Q11

D

44

SS22

46

Q20

D

48

SS24

50

Q16

D

52

SS26

54
56

SS27

58

Q22

D

60

SS29

62

Q18

D

64

SS31

66

Q28

D

68

SS33

70

Q24

D

72

SS35

74
76

QS3_t

78

SS38

80

Q31

D

82

SS40

84

Q27

D

86

SS42

88
90

SS44

92
94

SS46

96
98

SS47

100
102

SS49

104
106

SS51

108
110

KE1

C

112

DD2

V

114

CT_n

116
118

DD4

V

120

11

A

122

7

A

124

DD6

V

126

5

A

128

4

A

130

DD8

V

132

2

A

134
136

DD10

138
140
142

DD12

144

0

A

146

10/AP

148

DD14

150

A0

B

152
154

DD16

156
158

13

A

160

DD18

162
164
166

A2

S

168

SS54

170

Q36

D

172

SS56

174

Q32

D

176

SS58

178
180

SS59

182

Q39

D

184

SS61

186

Q35

D

188

SS63

190

Q45

D

192

SS65

194

Q41

D

196

SS67

198
200

QS5_t

202

SS70

204

Q47

D

206

SS72

208

Q43

D

210

SS74

212

Q53

D

214

SS76

216

Q48

D

218

SS78

220
222

SS79

224

Q54

D

226

SS81

228

Q50

D

230

SS83

232

Q60

D

234

SS85

236

Q57

D

238

SS87

240
242

QS7_t

244

SS90

246

Q63

D

248

SS92

250

Q59

D

252

SS94

254

DA

S

256

A0

S

258

TT

V

260

A1

S

262

ND2

G

B

0.6V_DDR_VTT

+

C

DR_A_DQ[0..63]

D

DR_A_DM[0..7]

D

DR_A_MA[0..13]

D

DR_A_RST#

D

+

4.7U_0402_6 .3V6K

VREF_CA

+

1

D32
C

2

1000P_0402_50V7K

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DR_A_DQ[0..63] [7]

D

DR_A_DM[0..7] [7]

D

DR_A_MA[0..13] [7]

D

1 2

D1

@ESD@

C
100P_0402 _50V8J

1.2V_DDR

1

D2

C

1
0U_0603_6.3V6M

2

0.6V_DDR_VTT

+

1

2

ollow CRB design

F

VREF_CA

+

@

D24

C

1

1

D4

D3

C

C

1

1

0U_0603_6.3V6M

0U_0603_6.3V6M

2

2

1

1

D17

D18

C

C

D16

C

1

1

0U_0603_6.3V6M

0U_0603_6.3V6M
1
U_0402_6.3V6K

2

2

VREF_CA

+

1

1

D25

C

2

2

.1U_0402_16V4Z

.1U_0402_16V4Z

0

0

1.2V_DDR

+

330U_D2_2V_Y

1

C

+

D35

2

016/01/07 2017/01/07

016/01/07 2017/01/07

016/01/07 2017/01/07

2

2

2

1

D5

C

1
0U_0603_6.3V6M

2

+

1

D26

C

2

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

eciphered Date

eciphered Date

eciphered Date

D

D

D

1

2

1.2V_DDR

R
1K_0402_1 %

1 2

R
1K_0402_1 %

1 2

D

1

D7

D6

C

C

1

1

0U_0603_6.3V6M

0U_0603_6.3V6M

2

D1

D2

1

D36

C

1
U_0402_6.3V6K

2

D

2.5V_MEM

+

1

2

1.2V_DDR

+

D37

C

1
0U_0603_6.3V6M

1

C

1
U_0402_6.3V6K

2

D8

1

2

1

1

D9

C

C

1

1

U_0402_6.3V6K

U_0402_6.3V6K

2

2

1

1

D10

D12

D11

C

C

1

1

U_0402_6.3V6K

U_0402_6.3V6K

2

2

reserve

C

C

C

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

D21

D19

D20

1

1

1

@RF@

@RF@

@RF@

2

2

2

C

C

2.2U_0402_6.3V6M

D27

D28

1

@RF@

@RF@

2

itle

itle

itle

C

C

C

C

2.2U_0402_6.3V6M
D29

1

@RF@

2

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

DR4 SODIMM-I Socket

DR4 SODIMM-I Socket

DR4 SODIMM-I Socket

D

D

D

A-F121P

A-F121P

A-F121P

L

L

L

2.2U_0402_6.3V6M

1

2

D34

C

1
0U_0603_6.3V6M

T

T

T

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheetof

Date : Sheetof

Date : Sheetof

1

2

E

D13

C

1
U_0402_6.3V6K

E

0.6V_DDR_VTT

+

1

1

D15

D14

C

C

1

1

U_0402_6.3V6K

U_0402_6.3V6K

2

2

C

C

10P_0402_50V8J

10P_0402_50V8J

D23

D22

1

1

@RF@

@RF@

2

2

C

C

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

D30

D31

1

1

@RF@

@RF@

2

2

3 61Thursday, November 09, 2 017

3 61Thursday, November 09, 2 017

3 61Thursday, November 09, 2 017

1

1

1

.3(X02)

.3(X02)

.3(X02)

0

0

0

ain Func = DIMM2

M

1 1

2 2

3 3

4 4

3VS

+

A

1.2V_DDR

+

DR_B_DQ5

D

DR_B_DQ1

D

DR_B_DQS0#

2.5V_MEM

+

1

D68

C

2

Address: 100>

<

1
U_0402_6.3V6K

D

DR_B_DQS0

D

DR_B_DQ7

D

DR_B_DQ3

D

DR_B_DQ13

D

DR_B_DQ9

D

DR_B_DM1

D

DR_B_DQ15

D

DR_B_DQ10

D

DR_B_DQ21

D

DR_B_DQ17

D

DR_B_DQS2#

D

DR_B_DQS2

D

DR_B_DQ23

D

DR_B_DQ19

D

DR_B_DQ29

D

DR_B_DQ25

D

DR_B_DM3

D

DR_B_DQ30

D

DR_B_DQ26

D

DR_B_CKE0

D

DR_B_BG1

D

DR_B_BG0

D

DR_B_MA12

D

DR_B_MA9

D

DR_B_MA8

D

DR_B_MA6

D

DR_B_MA3

D

DR_B_MA1

D

DR_B_CLK0

D

DR_B_CLK0#

D

DR_B_PAR

D

DR_B_BA1

D

DR_B_CS0#

D

DR_B_WE#

D

DR_B_ODT0

D

DR_B_CS1#

D

DR_B_ODT1

D

DR_B_DQ37

D

DR_B_DQ33

D

DR_B_DQS4#

D

DR_B_DQS4

D

DR_B_DQ38

D

DR_B_DQ34

D

DR_B_DQ44

D

DR_B_DQ40

D

DR_B_DM5

D

DR_B_DQ46

D

DR_B_DQ42

D

DR_B_DQ52

D

DR_B_DQ49

D

DR_B_DQS6#

D

DR_B_DQS6

D

DR_B_DQ55

D

DR_B_DQ51

D

DR_B_DQ61

D

DR_B_DQ56

D

DR_B_DM7

D

DR_B_DQ62

D

DR_B_DQ58

D

DR_B_DQS0#[7]

D

DR_B_DQS0[7]

D

DR_B_DQS2#[7]

D

DR_B_DQS2[7]

D

DR_B_CKE0[7]

D

DR_B_BG1[7]

D

DR_B_BG0[7]

D

DR_B_CLK0[7]

D

DR_B_CLK0#[7]

D

DR_B_PAR[7]

D

DR_B_BA1[7]

D

DR_B_CS0#[7]

D

DR_B_MA14_W E#[7]

D

DR_B_ODT0[ 7]

D
DR_B_CS1#[7]

D

5mil

1

DR_B_ODT1[ 7]

D

DR_B_DQS4#[7]

D

DR_B_DQS4[7]

D

DR_B_DQS6#[7]

D

DR_B_DQS6[7]

D

PU_SCLK0[9,13,2 2,36]

A

1

D67

C

1
U_0402_6.3V6K

2

A

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229
231
233
235
237
239
241
243
245
247
249
251
253
255
257
259
261

IMM_B H:4mm STD

D

JDIMM2

CONN@

1

SS1

V

3

Q5

D

5

SS3

V

7

Q1

D

9

SS5

V

QS0_c

D

QS0_t

D

SS8

V

Q7

D

SS10

V

Q3

D

SS12

V

Q13

D

SS14

V

Q9

D

SS16

V

M1_n/DBI_n

D

SS17

V

Q15

D

SS19

V

Q10

D

SS21

V

Q21

D

SS23

V

Q17

D

SS25

V

QS2_c

D

QS2_t

D

SS28

V

Q23

D

SS30

V

Q19

D

SS32

V

Q29

D

SS34

V

Q25

D

SS36

V

M3_n/DBI3_n

D

SS37

V

Q30

D

SS39

V

Q26

D

SS41

V

B5/NC

C

SS43

V

B1/NC

C

SS45

V

QS8_c

D

QS8_t

D

SS48

V

B2/NC

C

SS50

V

B3/NC

C

SS52

V

KE0

C

DD1

V

G1

B

G0

B

DD3

V

12

A

9

A

DD5

V

8

A

6

A

DD7

V

3

A

1

A

DD9

V

K0_t

C

K0_c

C

DD11

V

ARITY

P

A1

B

DD13

V

S0_n

C

E_n/A14

W

DD15

V

DT0

O

S1_n

C

DD17

V

DT1

O

DD19

V

1, CS3_n,NC

C

SS53

V

Q37

D

SS55

V

Q33

D

SS57

V

QS4_c

D

QS4_t

D

SS60

V

Q38

D

SS62

V

Q34

D

SS64

V

Q44

D

SS66

V

Q40

D

SS68

V

M5_n/DBI5_n

D

SS69

V

Q46

D

SS71

V

Q42

D

SS73

V

Q52

D

SS75

V

Q49

D

SS77

V

QS6_c

D

QS6_t

D

SS80

V

Q55

D

SS82

V

Q51

D

SS84

V

Q61

D

SS86

V

Q56

D

SS88

V

M7_n/DBI7_n

D

SS89

V

Q62

D

SS91

V

Q58

D

SS93

V

CL

S

DDSPD

V

PP1

V

PP2

V

ND1

G

OTES_ADDR0205-P00 1A02~D

L

DEREN_40-4226 1-26001RHF

SP07001HW0 L

B

M0_n/DBI0_n

D

M2_n/DBI2_n

D

M8_n/DBI_n/NC

D

R

A

VENT_n/NF

E

C

C

AS_n/A16

R

AS_n/A15

C

0/CS2_n/NC

C

V

M4_n/DBI4_n

D

M6_n/DBI6_n

D

B

V

V

V
QS1_c

D

D

V

V

V

V

V

V

V

V

V

V
QS3_c

D

D

V

V

V
B4/NC

C

V
B0/NC

C

V

V
B6/NC

C

V
B7/NC

C

V

ESET_n

A

LERT_n

V
K1_t/NF
K1_c/NF

V

A

V

V

V

REFCA

V

V

V

V

V

V

V

V
QS5_c

D

D

V

V

V

V

V

V

V

V

V

V
QS7_c

D

D

V

V

V

C

1.2V_DDR

DR_B_DQ4

D

DR_B_DQ0

D

DR_B_DM0

D

DR_B_DQ6

D

DR_B_DQ2

D

DR_B_DQ12

D

DR_B_DQ8

D

DR_B_DQS1#

D

DR_B_DQS1

D

DR_B_DQ14

D

DR_B_DQ11

D

DR_B_DQ20

D

DR_B_DQ16

D

DR_B_DM2

D

DR_B_DQ22

D

DR_B_DQ18

D

DR_B_DQ28

D

DR_B_DQ24

D

DR_B_DQS3#

D

DR_B_DQS3

D

DR_B_DQ31

D

DR_B_DQ27

D

DR_B_RST#

D

DR_B_CKE1

D

DR_B_ACT#

D

DR_B_ALERT#

D

DR_B_MA11

D

DR_B_MA7

D

DR_B_MA5

D

DR_B_MA4

D

DR_B_MA2

D

DR_B_EVENT#

D

DR_B_CLK1

D

DR_B_CLK1#

D

DR_B_MA0

D

DR_B_MA10

D

DR_B_BA0

D

DR_B_RAS#

D

DR_B_CAS#

D

DR_B_MA13

D

DR_B_DQ36

D

DR_B_DQ32

D

DR_B_DM4

D

DR_B_DQ39

D

DR_B_DQ35

D

DR_B_DQ45

D

DR_B_DQ41

D

DR_B_DQS5#

D

DR_B_DQS5

D

DR_B_DQ47

D

DR_B_DQ43

D

DR_B_DQ53

D

DR_B_DQ48

D

DR_B_DM6

D

DR_B_DQ54

D

DR_B_DQ50

D

DR_B_DQ60

D

DR_B_DQ57

D

DR_B_DQS7#

D

DR_B_DQS7

D

DR_B_DQ63

D

DR_B_DQ59

D

+

3VS

+

0.6V_DDR_VTT

+

DR_B_DQS1# [7 ]

D

DR_B_DQS1 [7]

D

DR_B_DQS3# [7]

D

DR_B_DQS3 [ 7]

D

DR_B_RST# [7]

D

DR_B_CKE1 [7]

D

DR_B_ACT# [7]

D

DR_B_ALERT# [7 ]

D

DR_B_EVENT# [7]

D

DR_B_CLK1 [7 ]

D

DR_B_CLK1# [7]

D

DR_B_BA0 [7]

D

DR_B_MA16_RAS# [7]

D

DR_B_MA15_CAS# [7]

D

DR_B_DQS5# [7]

D

DR_B_DQS5 [ 7]

D

DR_B_DQS7# [7]

D

DR_B_DQS7 [ 7]

D

PU_SDATA0 [9,13, 22,36]

A

DR_B_DQ[0..63 ]

D

DR_B_DM[0..7]

D

DR_B_MA[0..13]

D

DR_B_RST#

D

D40

C
100P_0402 _50V8J

1.2V_DDR

+

1

1

D41

C

1
0U_0603_6.3V6M

2

0.6V_DDR_VTT

+

1

C

2

VREFB_CA

+

1

D58
C

2

1000P_0402_50V7K

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

1

D42

D43

C

C

1

1

0U_0603_6.3V6M

0U_0603_6.3V6M

2

2

1

1

D57

D56

C

C

D55

1

1

0U_0603_6.3V6M

0U_0603_6.3V6M
1
U_0402_6.3V6K

2

2

VREFB_CA

+

@

1

D59

C

4.7U_0402_6 .3V6K

2

016/01/07 2017/01/07

016/01/07 2017/01/07

016/01/07 2017/01/07

2

2

2

2

SS2

V

4

Q4

D

6

SS4

V

8

Q0

D

10

SS6

V

12
14

SS7

V

16

Q6

D

18

SS9

V

20

Q2

D

22

SS11

24

Q12

D

26

SS13

28

Q8

D

30

SS15

32
34

QS1_t

36

SS18

38

Q14

D

40

SS20

42

Q11

D

44

SS22

46

Q20

D

48

SS24

50

Q16

D

52

SS26

54
56

SS27

58

Q22

D

60

SS29

62

Q18

D

64

SS31

66

Q28

D

68

SS33

70

Q24

D

72

SS35

74
76

QS3_t

78

SS38

80

Q31

D

82

SS40

84

Q27

D

86

SS42

88
90

SS44

92
94

SS46

96
98

SS47

100
102

SS49

104
106

SS51

108
110

KE1

C

112

DD2

V

114

CT_n

116
118

DD4

V

120

11

A

122

7

A

124

DD6

V

126

5

A

128

4

A

130

DD8

V

132

2

A

134
136

DD10

138
140
142

DD12

144

0

A

146

10/AP

148

DD14

150

A0

B

152
154

DD16

156
158

13

A

160

DD18

162
164
166

A2

S

168

SS54

170

Q36

D

172

SS56

174

Q32

D

176

SS58

178
180

SS59

182

Q39

D

184

SS61

186

Q35

D

188

SS63

190

Q45

D

192

SS65

194

Q41

D

196

SS67

198
200

QS5_t

202

SS70

204

Q47

D

206

SS72

208

Q43

D

210

SS74

212

Q53

D

214

SS76

216

Q48

D

218

SS78

220
222

SS79

224

Q54

D

226

SS81

228

Q50

D

230

SS83

232

Q60

D

234

SS85

236

Q57

D

238

SS87

240
242

QS7_t

244

SS90

246

Q63

D

248

SS92

250

Q59

D

252

SS94

254

DA

S

256

A0

S

258

TT

V

260

A1

S

262

ND2

G

D

1 2

@ESD@

1

D44

C

1
0U_0603_6.3V6M

2

VREFB_CA

+

1

D60

C

2

.1U_0402_16V4Z
0

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

eciphered Date

eciphered Date

eciphered Date

D

D

D

D

DR_B_DQ[0..63 ] [7]

D

DR_B_DM[0..7] [ 7]

D

DR_B_MA[0..13] [7]

1

1

D45

C

1
0U_0603_6.3V6M

2

2

1

D61

C

2

.1U_0402_16V4Z
0

D

C

1
0U_0603_6.3V6M

+

D46

1.2V_DDR

R
1K_0402_1 %

1 2

R
1K_0402_1 %

1 2

E

1

1

1

1

1

D47

D48

C

1
U_0402_6.3V6K

2

D3

D4

1

C

2

D49

C

C

1
U_0402_6.3V6K

2

2.5V_MEM

+

1

D64

1
U_0402_6.3V6K

2

C

1
U_0402_6.3V6K

2

2

1

D66

D65

C

C

1

1

0U_0603_6.3V6M

0U_0603_6.3V6M

2

Title

itle

itle

T

T

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

C

C

C

Date : Sheetof

Date : Sheetof

Date : Sheetof

1

D50

D51

C

1
U_0402_6.3V6K

C

1
U_0402_6.3V6K

2

2

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

DR4 SODIMM-II Socket

DR4 SODIMM-II Socket

DR4 SODIMM-II Socket

D

D

D

A-F121P

A-F121P

A-F121P

L

L

L

E

1

1

D52

1
U_0402_6.3V6K

D54

D53

C

C

1

1

U_0402_6.3V6K

U_0402_6.3V6K

2

2

4 61Thursday, November 09, 2 017

4 61Thursday, November 09, 2 017

4 61Thursday, November 09, 2 017

1

1

1

.3(X02)

.3(X02)

.3(X02)

0

0

0

5

UM01

P
PWM
RT8207PGQW

UH1

D D

PU PWR

C

Peripheral Dev ice PW R

PU PWR

G

DAPTER

C C

A

UB01

P
CHARGER
ISL9538H RTZ-T

+PWR_SRC

+19VB)

(

P
PWM

T6226AGQUF

R

PUW01
PWM

T6226AGQUF

R

U501

P
PWM

Y8180CRAC

S

BATTERY

U301

P
PWM

Y8286BRAC

S

B B

UZ01

P
PWM

SL62771HRTZ-T

A A

5

I

UV01

P
PWM

SL62771HRTZ-T

I

50

P

51

P

56

P

EN_5V

49

P

P49

53

P

55

P

4

PJPM4
PJPM0 2

+1.2VP

PJPM0 3

+0.6VSP +0.6V_DDR_VTT

.8_1.8VALW _PWREN

0

GPU_PWROK

D

14.51A

JPW0 2

P
PJP50 3

5VALW+5VALW P

+

JP30 2

P

3VALWP +3 VALW

+

11.652A

VR_ON

+APU_VDDCORE

APU_VDDSOC

+

PXS_PWREN

+VGA_CORE

4

1.2V_DDR

+

JPW0 2

P

45A

13A

40A

PUF01
RT9059GSP

9.87A

1.5A

PJPH3
PJPH02

0.8VALW+VDDP_ALW P

+

+1.35V_MEM_GFX+1.35VGPUP

4

U
EM5209VF

T8

U
G518A1TO1 U

I1

U
SY6288 D20AA C

U1

U
SY6288 D20AA C

5V_CONN_P1

+

6

U
EM5209VF

3VALW_EC(+EC_VCCA)

+

3VALW ( TPM)

+

UL2
SY6288C20A AC

PU1801
RT8061A ZQW

U2501

P
RT9059G SP

3VS_TOUCH

+

DD_33_S5

V

3VLP

+

5A

5.68A

S0A3_GPIO
SUSP#

VP_TRIP_P1

O
VBUS_P_CTRL_P1

SB_EN#

U

USB_EN#

0.5A

0A3_GPIO

S
SUSP#

.05A

0

WOL_EN

0.8_1.8VALW _PWREN

SYSON

.5A

0

.25A

0

.05A

0

3

+0.95VSDGPU

5VS

+

.51A

6

CCG_VBUS

+

6.352A

+3VS

1.8VALWP

+

2.5VP

+

5V_USB_PWR1

+

5V_USB_PWR2

+

.5A

0

LAN_VDD33

+

.95A

1

3

F

RA38
0ohm 0805

I1

F

RW3
0ohm 0603

LS11 , PLS12

P
5A_Z120_25M_0805_2P

.5A

2

A

2

2

U
SY6288C20A AC

U3
EM5209VF

3.3V_VDD_PIC

+

3VS(SATA redriver)

+

.5A

1

JP18 2

P

1.8V_ALW

+

PJP25 02

2.5V_MEM

+

A

2

5VS_KBL

+

+5V_PVDD

+5V_HDDJP4

+5V_HDMI

+TPAN_VDD_F

0.2A

ENVDD
EC_ENVDD

PXS_PWREN

0.1A

0

0.5A

1.5A

1.5A

0.2A

3A

+CCG_VBUS_1

+LCDVDD

3VGS

+

.5A

3

U
EM5209VF

6

U
EM5209VF

0.45A

ecurity Classificati on

ecurity Classificati on

ecurity Classificati on

S

S

S

Issued Date

Issued Date

Issued Date

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

3

2

2

2

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

016/01/07 2017/01/07

016/01/07 2017/01/07

016/01/07 2017/01/07

2

VDD_TOUCH

+

0.7A

25mA

PXS_P WRE N

SUSP #

Deciphered Date

Deciphered Date

Deciphered Date

2

QS01

P
AON7409

T4

U
RT9069-33G B

1.8VGS

+

1.8VS

+

+5V_AVDD

5VS(FPR)

+

5VS_ODD

+

+5VS_FAN

RT

C

+VBUS_DC_SS

OK

P

VS_APU(Debug)

3

VS(FPR)

3

3VS_CAM

+

VS(SSD)

3

3V_HUB

+

3VS_WLAN_NGF F

+

3V_DVDD

+

0.5A

1.5A

1

.5A

0

.05mA

0

.5A

1

.5A

0

.11A

0

QS02

P
AON7409

3.3V_VDD_PIC

+

.05mA

0

.05mA

0

.15A

0

.5A

2

.27A

0

2A

07mA

1

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

itle

itle

itle

T

T

T

Green CLK

Green CLK

Green CLK

ize

ocument Number Re v

ize

ocument Number Re v

ize

ocument Number Re v

S

D

S

D

S

D

A-F121P

A-F121P

A-F121P

L

L

L

Date: Sheetof

Date: Sheetof

Date: Sheetof

1

UB01

P
CHARGER
ISL9538H RTZ-T

15 61Thursday, November 09, 2017

15 61Thursday, November 09, 2017

15 61Thursday, November 09, 2017

.3(X02)

.3(X02)

.3(X02)

0

0

0

ain Func = LCD

M

D D

NVDD[8]

E

C_ENVDD[27]

E

C C

5

12

X8 0_0402_5%

R

12

X9 0_0402_5%@

R

LCDVDD

+

19VB

+

W=40mil s

@

1 2

5 0_0805_5%

R

1 2

1

F

SMD1812P150 TF/24 1.5A UL/CSA/TUV

3VS

+

1

5

C

4.7U_0603_6 .3V6K

2

NVDD_RE

E

W=60mil s

1 2

HCB2012KF-221 T30_2P

X1

L

INV_PWR_SRC

+

SY6288C20AAC_SOT2 3-5

+

1

12

C

2

0.1U_0603_25V7K

5

N

I

4

N

E

LCDVDD_CONN

INV_PWR_SRC

+

13

C

@

2

U

1

UT

O

2

ND

G

3

C

O

1

2

0U_0603_25V6M
1

0mil

6

R

10K_0402_ 5%

4

3 0_0402_5%@

RB751V-40_SOD3 23-2

BC_EN

D

R

X1

D

NVTPWM[8]

I

4 0_0402_5%@

R

DP_HPD[8]

LCDVDD

+

3VS

+

12

X7

E

KOFF#[27]

B

BC_EN[27]

D

12

1M +-5% 0402

3

DP_HPD_R

12

12

E

12

P1

R
100K_0402 _5%

ISPOFF#

D

12

10K_0402_ 5%

P2

R

NVTPWM

I

12

P3

R

BC_EN_R

D

12

@

6

R
0_0402_5%

2

=40mils

INV_PWR_SRC

+

CD_TEST[27]

L

DP_AUXP[8]

E

DP_AUXN[8]

E

DP_TXN0[8]

E

DP_TXP0[8]

E

DP_TXN1[8]

E

DP_TXP1[8]

E

S_EN_R[27]

T

W

LCDVDD_CONN

+

1 2

X15

100_0402_ 5%

R

R

12
12

12
12

12
12

3VS_CAM

+

_MIC_DATA[18 ]

A

_MIC_CLK[18]

A

12

X25 33_0402_5%

VDD_TOUCH

+

43210.1U_04 02_16V7K

C

43220.1U_04 02_16V7K

C

43110.1U_04 02_16V7K

C

43120.1U_04 02_16V7K

C

43130.1U_04 02_16V7K

C

43140.1U_04 02_16V7K

C

SB20_0_N3_R

U

SB20_0_P3_ R

U

SB20_TOUCH_N2

U

SB20_TOUCH_P2

U

CD_TST_C

L

BC_EN_R

D

DP_HPD_R

E

DP_AUXP_C

E

DP_AUXN_C

E

DP_TXN0_C

E

DP_TXP0_C

E

DP_TXN1_C

E

DP_TXP1_C

E

NVTPWM

I

ISPOFF#

D

_MIC_DATA

A

_MIC_CLK

A

S_EN_RR

T

1

J

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

0

1

11

1

1

12

2

1

13

3

1

14

4

1

15

5

1

16

6

1

17

7

1

18

8

1

19

9

1

20

0

2

21

1

2

22

2

2

23

3

2

24

4

2

25

5

2

26

6

2

27

7

2

28

8

2

29

9

2

30

0

3

31

1

3

32

2

3

33

3

3

34

4

3

35

5

3

36

6

3

37

7

3

38

8

3

39

9

3

40

0

4

ACES_51540-04 001-P01

CONN@

EDP1

41

1

G

42

2

G

MCM1012B900F 06BP_4P

+

1 2

VDD_TOUCH

1 2

1

L

EMI@

1 2

7 0_0402_5%

R

@EMI@

1 2

8 0_0402_5%

R

@EMI@

VDD_TOUCH

+

SB20_0_P3[10]

B B

A A

Webcam PWR CTRL

Touch Screen Panel

*

5VS

3VS

+

+

12

12

@

9

R
0_0603_5%

PAN_VDD_F

T

5

3VS

+

150mA

W2 0_0603_ 5%@

R

TPAN_VDD_F

+

W3

R
0_0603_5%

@

2

F

1 2

1.1A_24V_SMD181 2P110TF-24

@

1 2

W4 0 _0603_5%

R

3VS_CAM

+

12

1

14

C

4.7U_0603_6 .3V6K

2

or modern standby

f

TPAN_VDD_F

VDD_TOUCH

+

@

+

mils

8

.3V_TS_EN[9]

3

1

310

C
1U_0402_10V6K@

2

4

U

SB20_0_N3[10]

U

5

U

UT

O

5

N

I

ND

G

4

N

E

CB

O

SY6288D20AAC_SOT2 3-5

@

8 mils

1

2

3

300 10K_0402_5%@

R

SB20_0_P3_ R

U

SB20_0_N3_R

U

34

SB20_TOUCH_N2

SB20_TOUCH_N2[35]

U

SB20_TOUCH_P2[35]

U

3

U

SB20_TOUCH_P2

U

3

223

@ESD@

AZC199-02SPR7 G_SOT23-3

1

X3

D

1

ollow esd require @0619

f

ecurity Classificati on

ecurity Classificati on

ecurity Classificati on

S

S

S

Issued Date

Issued Date

Issued Date

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

2

2

2

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

016/01/07 2017/01/07

016/01/07 2017/01/07

016/01/07 2017/01/07

Deciphered Date

Deciphered Date

Deciphered Date

F require 12/22

LCDVDD_CONN

3VS

+

+

10P_0402_50V8J

0.1U_0402_10V7K
C
W5

C

1

1

X3

@RF@

2

2

ace close to JEDP

Pl

2

R

10P_0402_50V8J

C
W6

1

1

1

16

15

C

C

1

@RF@

0

U_0402_10V6K

.1U_0402_16V7K

2

2

2

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

itle

itle

itle

T

T

T

eDP / webcam / TouchScree n

eDP / webcam / TouchScree n

eDP / webcam / TouchScree n

ize

ocument Number Re v

ize

ocument Number Re v

ize

ocument Number Re v

S

D

S

D

S

D

A-F121P

A-F121P

A-F121P

L

L

L

Date: Sheetof

Date: Sheetof

Date: Sheetof

1

16 61Thursday, November 09, 2017

16 61Thursday, November 09, 2017

16 61Thursday, November 09, 2017

.3(X02)

.3(X02)

.3(X02)

0

0

0

ain Func = HDMI

M

5

4

3

2

1

D D

DMI_CLKN

5V_HDMI

+

PU_DP1_CTRL_CLK[8]

H

DMI_CLKP

H

DMI_TX_N0

H

DMI_TX_P0

H

DMI_TX_N1

H

DMI_TX_P1

H

DMI_TX_N2

H

DMI_TX_P2

H

I21499_0402_1%

I23499_0402_1%

I24499_0402_1%

I22499_0402_1%

R

R

R

R

12

12

12

12

3VS

+

12

I20

R

100K_0402 _5%

3VS

+

PI3

R

PU_DP1_CTRL_CLK

A

18

PU_DP1_CTRL_DATA

A

27

DMI_CTRL_DATA

H

36

DMI_CTRL_CLK

H

45

2.2K_0804_ 8P4R_5%

CRB use 4.7k, bristol use 2.2k

3VS

+

2

G

S

D

5

34

SGD

I3A

Q

L2N7002DW1 T1G

I25499_0402_1%
R

12

2

G

I3B

Q
L2N7002DW1 T1G

H

61

H

I28499_0402_1%

I26499_0402_1%

I27499_0402_1%

R

R

R

12

12

12

13

D

Q
2N7002K_SOT23-3

S

DMI_CTRL_CLK

DMI_CTRL_DATA

I1

12

I1 0.1U_0 402_10V7K

PU_DP1_N3[8]

A

PU_DP1_P3[8]

A

PU_DP1_N2[8]

A

PU_DP1_P2[8]

A

PU_DP1_N1[8]

A

PU_DP1_P1[8]

A

PU_DP1_N0[8]

A

PU_DP1_P0[8]

A

C C

B B

A A

C

12

I2 0.1U_0 402_10V7K

C

12

I4 0.1U_0 402_10V7K

C

12

I5 0.1U_0 402_10V7K

C

12

I6 0.1U_0 402_10V7K

C

12

I7 0.1U_0 402_10V7K

C

12

I8 0.1U_0 402_10V7K

C

12

I9 0.1U_0 402_10V7K

C

A

PU_DP1_CTRL_DATA[8]

A

DMI_CLKN

H

DMI_CLKP

H

DMI_TX_N0

H

DMI_TX_P0

H

DMI_TX_N1

H

DMI_TX_P1

H

DMI_TX_P2

H

DMI_TX_N2

H

Place close to JHDMI

1 2

I1 0_0402_5%@EMI @

R

I1

EMI@

L

3 4

HCM1012GH900BP_4 P

1 2

I3 0_0402_ 5%@EMI@

R

1 2

I4 0_0402_ 5%@EMI@

R

I2

EMI@

L

3 4

HCM1012GH900BP_4 P

1 2

I7 0_040 2_5%@EMI@

R

1 2

@EMI@

I8 0_0402_ 5%

R

I3

EMI@

L

3 4

HCM1012GH900BP_4 P

1 2

I10 0_04 02_5%@EMI@

R

1 2

@EMI@

I12 0_04 02_5%

R

HCM1012GH900BP_4 P

3 4

I4

EMI@

L

1 2

I14 0_04 02_5%@EMI@

R

PU_DP1_HPD[8]

A

DMI_L_CLKN

H

12

DMI_L_CLKP

H

DMI_L_TX_N0

H

12

DMI_L_TX_P0

H

DMI_L_TX_N1

H

12

DMI_L_TX_P1

H

DMI_L_TX_P2

H

DMI_L_TX_N2

H

12

MMBT3904_NL_SOT23- 3

DMI_L_CLKN

H

DMI_L_CLKP

H

DMI_L_TX_N0

H

12

DMI_L_TX_P0

H

DMI_L_TX_N1

H

12

DMI_L_TX_P1

H

DMI_L_TX_P2

H

DMI_L_TX_N2

H

+

I2

Q

12

@EMI@

150_0402_ 5%

I6

R

@EMI@

150_0402_ 5%

I9

R

12

3VS

C

E

3 1

12

R
100K_0402 _5%

@EMI@

150_0402_ 5%

I2

R

@EMI@

150_0402_ 5%

I13

R

2

B

I17

1 2

I15

R
150K_0402 _5%

5VS

+

1

I10

C
220P_0402 _50V8J

2

F

1.5A_6V_1206L 150PR~D

DMI_HPD

H

12

@

I16

R
20K_0402_ 5%

5V_HDMI

+

=20mils

12

I1

DMI_HPD

H

DMI_CTRL_DATA

H

DMI_CTRL_CLK

H

DMI_L_CLKN

H

DMI_L_CLKP

H

DMI_L_TX_N0

H

DMI_L_TX_P0

H

DMI_L_TX_N1

H

DMI_L_TX_P1

H

DMI_L_TX_N2

H

DMI_L_TX_P2

H

W

HDMI1

J

19

P_DET

H

18

5V

+

17

DC/CEC_GND

D

16

DA

S

15

CL

S

14

eserved

R

13

EC

C

12

K-

C

11

K_shield

C

10

K+

C

9

0-

D

8

0_shield

D

7

0+

D

6

1-

D

5

1_shield

D

4

1+

D

3

2-

D

2

2_shield

D

1

2+

D

CONCR_099AKAC19NBLCNF

DC02170213 1

OYALTY HDMI W/LOGO45@

R

art Number Descripti on

P

HDMI W/Logo:RO0000002HM

O0000002HM

R

CONN@

1

2

ND

G

ND

G

ND

G

ND

G

I3

C
.1U_0402_16 V7K

20
21
22
23

ecurity Classificati on

ecurity Classificati on

ecurity Classificati on

S

S

S

Issued Date

Issued Date

Issued Date

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

3

2

2

2

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

016/01/07 2017/01/07

016/01/07 2017/01/07

016/01/07 2017/01/07

Deciphered Date

Deciphered Date

Deciphered Date

2

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

itle

itle

itle

T

T

T

DMI

DMI

DMI

H

H

H

ize

ocument Number Re v

ize

ocument Number Re v

ize

ocument Number Re v

S

D

S

D

S

D

A-F121P

A-F121P

A-F121P

L

L

L

Date: Sheetof

Date: Sheetof

Date: Sheetof

7 61Thursday, Nov ember 09, 2017

7 61Thursday, Nov ember 09, 2017

7 61Thursday, Nov ember 09, 2017

1

1

1

1

.3(X02)

.3(X02)

.3(X02)

0

0

0

.5A

1

12

A2 0_0402_5%@

R

5mA

2

A41 200K_04 02_1%

R

A57 0_0603_ 5%

R

A43 33_0402 _5%

R

IC_CLK_C

M

_MIC_CLK

A

_MIC_DATA

A

5

5V_PVDD

+

A1

C

C

1

12

2

0U_0603_10V6M
1

ayout Note:

L

lose pin41

C

3V_DVDD

+

12

A16

C

12

0U_0603_10V6M
1

ayout Note:

L

lace close to Pin 13

P

ACK_SENSE_1#

J

1 2

ACK_SENSE#

J

12

1 2

DA_BIT_CLK_R

H

_MIC_CLKA_MIC_DATA

A

12

@EMI@

A19

R
22 +-5% 040 2

@EMI@

1

A49

C
10P_0402_ 50V8J

2

A5 ,CA37,CA38 close UA1

L

EMI@

1 2

A10 BLM15BB22 1SN1D_2P

L

1 2

A55 3 3_0402_5%

R

5

A2

1U_0402_16V7K
.

1

2

@EMI@

R
0_0402_5%

1 2

A3

C

12

10U_0603_10V6M

ayout Note:

L

lose pin46

C

A7.1U_0402_16V7K
C

lose pin9

C

A44

EMI@

1

A50

C
10P_0402_ 50V8J

2

A4

C

1

2

.1U_0402_16V7K

ACK_SENSE# [21 ]

J

DA_SDIN0 [9]

H

1

@EMI@

C
22P_0402_ 50V8J

2

ayout Note:

L

A31

H

ollow vendor 100k change to 10K @03/28

f

3V_DVDD

+

C_MUTE#[27]

E

3V_DVDD

+

EMI@

1

A51

C
10P_0402_ 50V8J

2

M
M

ain Func = Audio

M

5VS

+

A38 0 _0805_5%@

R

D D

3VS

+

C C

UD_SENSE_A

A

ACK_SENSE_1#

J

DA_SDIN0_R

H

B B

o eDP

T

_MIC_CLK[16]

A

_MIC_DATA[16 ]

A

A A

4

12

A56 0_040 2_5%

R

1.8VS

+

3V_DVDD

+

1

12

A46

A9

C

A9, CA46 close

C
to UA1 pin1

A14 0 _0402_5%323 4@

DA_RST#_R[9 ]

R

C_BEEP_C

P

C

DA_SYNC_R[9]

H

DA_BIT_CLK_R[9]

H

DA_SDOUT_R[9]

H

12

A8 10K_0402_5%@

R

C_MUTE#

E

A13 100K_0402_5%

R

A19 10U_0603_10V6M

C

A20 10U_0603_6.3V6M

C

A21 10U_0603_10V6M

C

peaker trace width >40mil

S
@ 2W4ohm speaker power

A10 100K_0402_5%

R

moat

race width for SPK-L+/SPK-L-/SPK-R+/SPK-R-

T
Speaker 4 ohm : 40mil
Speaker 8 ohm : 20mil

IC_CLK_C
IC_DATA_C

4

C

0U_0603_10V6M
1

1 2

1 2

A47 0.1 U_0402_16V7K

3234@

DA_SDIN0_R

H

IC_DATA_C

M

IC_CLK_C

M

12
1 2
1 2
1 2

NT-SPK-L+

I
NT-SPK-L-

I
NT-SPK-R-

I
NT-SPK-R+

I

UD_SENSE_A

A

12

1

A48

@

C
.1U_0402_16 V7K

2

NT-SPK-R+

I

NT-SPK-R-

I

NT-SPK-L+

I

NT-SPK-L-

I

EC Beep

CU Beep

M

C Beep

P

2

3234@

A1

U

1U_0402_16V7K
.

11

2C_SDA

I

12

2C_SCL

I

10

YNC

S

6

IT-CLK

B

5

DATA-OUT

S

8

DATA-IN

S

4

APD/DC DET

E

2

PIO0/DMIC-DATA12

G

3

PIO1/DMIC-CLK

G

47

DB

P

48

PDIFO/GPIO2/DMIC-D ATA-34/DMIC-CLK-In/MIC-GPI

S

27

DO1-CAP

L

39

DO2-CAP

L

7

DO3-CAP

L

42

PK-L+

S

43

PK-L-

S

44

PK-R-

S

45

PK-R+

S

13

P/LINE1 JD1

H

14

IC2/LINE2 JD2

M

15

PDIFO/FRONT JD3/GPIO3

S

ALC3234-CG_MQFN48 _6X6

1 2

A1 TAI-TECH HCB1005KF-8 00T20 0402EMI@

L

1 2

A2 TAI-TECH HCB1005KF-8 00T20 0402EMI@

L

1 2

A3 TAI-TECH HCB1005KF-8 00T20 0402EMI@

L

1 2

A4 TAI-TECH HCB1005KF-8 00T20 0402EMI@

L

EEP#[27]

B

PU_SPKR[9]

A

.
1U_0402_16V7K

1

VDD
D

2

A17

C

1

5V_PVDD
+

9

41

46

VDD1
P

VDD-IO
D

A3

D

2

3

BAT54C SOT23-3

3

5V_AVDD

+

26

36

40

VDD1

VDD2

VDD2

PVDD

A

A

P

C

INE1-VREFO-L

L

INE1-VREFO-R

L

IC2-VREFO

M

IC2-L/RING2

M

IC2-R/SLEEVE

M

M

H

H

HERMAL PAD

T

S
S
S
S

1

change part SCSBAT5407L 04/18

3

2

moat

5V_AVDD

Line1-VREFO-L

+

Line1-VREFO-R

+

1 2
1 2

12

A56 10U_0603_6.3V6M

C

POUT-L

H

POUT-R

H

1

L03ESDL5V0CC3-2_SOT23-3
A30
C

2

EMI@

1000P_0402_50V7K

1000P_0402_50V7K

+

A52 0_0 603_5%

R

A10.1U_0402_16V7K

1

C

12

A6

C

2

0U_0603_10V6M
1

MIC2-VREFO

+

ING2 [21]

R

LEEVE [ 21]

S

1 2

INE1-L [21]

L

INE1-R [21]

L

C_BEEP_C

P

POUT-L [21]

H

POUT-R [21]

H

2

3

D

L03ESDL5V0CC3-2_SOT23-3

A1

@ESD@

1

016/01/07 2017/01/07

016/01/07 2017/01/07

016/01/07 2017/01/07

2

2

2

lace close to Pin 26

P

1.8V_AVDD

+

3V_1.8V_CPVDD

+

31
30
29

MIC2-VREFO

+

28

A23 2.2 U_0603_6.3V6K

C

REF

V

35

A24 1U_06 03_16V7

C

BN

C

37

BP

C

3D3_STB

V

20

VSTB

5

34

A54 1U_0603_1 6V7

C

PVEE

C

17

ING2

R

18

LEEVE

S

19

IC-CAP

24

IC1-L

M

INE2-L

L

23

INE2-R

L

22

INE1-L

L

INE1-L

L

21

INE1-R

L

INE1-R

L

16

1 2

A57 0.1 U_0402_16V7K

C

CBEEP

P

32

3246@

P-OUT-L

33

P-OUT-R

25

VSS1

A

38

VSS2

A

49

A1

U

A00008GJ00

S

246@

3

LC3246-CG_MQFN48_6X6

A

PK_R+_CONN
PK_R-_CONN
PK_L+_CONN
PK_L-_CONN

1

1

1

A52

A66

A55

C

C

C

2

2

2

EMI@

EMI@

EMI@

1000P_0402_50V7K

1000P_0402_50V7K

C_BEEP

P

ecurity Classificati on

ecurity Classificati on

ecurity Classificati on

S

S

S

Issued Date

Issued Date

Issued Date

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

5VS

+

12

@

3V_DVDD

+

moat

12

A54 0_040 2_5%@

R

1 2

A12 0 _0402_5%

R

1 2

A49 1 K_0402_1%

R

12

A45

R

10K_0402_ 5%

2

3

D
A2

@ESD@

1

follow esd require @0619

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

Deciphered Date

Deciphered Date

Deciphered Date

2

A7 0_04 02_5%3234@

R

1 2

3VALW

+

1.8VS

+

RTCVCC

+

C_BEEP

P

SPK1

J

1

1

2

2

3

3

4

4

5

1

G

6

2

G

ACES_50224-00 401-001

CONN@
SP02000GC10

LN2306LT1G_SOT23 -3

3VS

+

3V_1.8V_CPVDD

+

oat

m

1.8V_AVDD

A53 0 _0402_5%@

R

A58 0 _0402_5%324 6@

R

1 2

C
C
C
C
C

A25 .1 U_0402_16V7KEMI@
A26 .1 U_0402_16V7KEMI@
A27 .1 U_0402_16V7KEMI@
A28 .1 U_0402_16V7KEMI@
A29 .1 U_0402_16V7KEMI@

R

+

12

12

3V_1.8V_CPVDD

+

12

oat

m

A51 0_0805_5%@

A53

C

0U_0603_10V6M
1

A12

C

0U_0603_10V6M
1

A1

Q

1 3

D

S

G

2

GNDA GND

Place on the moat between GND & GNDA .

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

itle

itle

itle

T

T

T

Audio Codec ALC3234

Audio Codec ALC3234

Audio Codec ALC3234

ize

ocument Number Re v

ize

ocument Number Re v

ize

ocument Number Re v

S

D

S

D

S

D

A-F121P

A-F121P

A-F121P

L

L

L

Date: Sheetof

Date: Sheetof

Date: Sheetof

1

lose pin40

C

1

2

12
12
12
12
12

12

1

A14

C

1U_0402_16V7K
.

18 61Thursday, November 09, 2017

18 61Thursday, November 09, 2017

18 61Thursday, November 09, 2017

.3(X02)

.3(X02)

.3(X02)

0

0

0

LAN_VDD33

+

C
LK_PCIE_N1[10]

C

+

LK_PCIE_P1[1 0]

C

LAN_VDD10

LKREQ_PCIE#1[10]

1

LAN_VDDREG

+

1 2

AN_MDIP0

L

AN_MDIP1

L

AN_MDIN0

L

AN_MDIN1

L

T
T

43
44

W

TLI

X

TLO

X

L82.49K_0402_1% ~D

R

LAN_VDD33

+

LKREQ_PCIE#1

C

OL_EN

W

OL_EN[2 7]

OL_EN

W

L1

U

1

DIP0

M

4

DIP1

M

2

DIN0

M

5

DIN1

M

8

VDD10

A

30

VDD10

A

32

VDD33

A

23

VDD33

D

15

EFCLK_P

R

16

EFCLK_N

R

L

12

LKREQB

C

28

KXTAL1

C

29

KXTAL2

C

27

ED0

L

25

ED1

L

31

SET

R

33

ND

G

RTL8106E-CG_QF N32_4X4

@

PU_PCIE_WAKE#

A

1 2

L10 10K_0402_5%

R

1 2

L15 10K_0402_5%

R

1 2

L16 10K_0402_5%@

R

LAN_VDD33 rising time(10%~90%) : >0.5ms and <100ms

+

+

L3

C

1U_0402_6.3 V6K

12

L2

R
100K_0402 _5%

1 2

CL1, CL2 close to UL1 Pin 17, 18

CIE_ARX_C_DTX_P4

P

17

CIE_ARX_C_DTX_N4

P

SOP

H

18

SON

H

13

SIP

H

14

SIN

H

LT_RST#_R

P

19

ERSTB

P

20

SOLATEB

I

PU_PCIE_WAKE#

A

21

ANWAKEB

26

PO

G

LAN_VDD10

+

3

AN_MDIP2

L

C

N

6

AN_MDIN2

L

C

N

7

AN_MDIP3

L

C

N

9

AN_MDIN3

L

C

N

10

LAN_VDD33

+

C

N

11

LAN_VDD10

+

C

N

22

C

N

24

EGOUT

R

C

N

3VS+LAN_VDD33

+

ain Func = LAN

M

A A

AN power Noise +LAN_VDD33 < 200mV Vpeak to Vpeak.

L
LAN power N oise +LAN_VDD10 < 100mV Vpeak to Vpeak.

B B

L1

000@

U

1

C C

TL8111H-CG QFN 32P E-LAN CTRL

R

A000080P0 0

S

L1

00@

U

1

TL8106E-CG_QFN32_4X4

R

A000065Y0 0

S

D D

Reserve 10K pull LAN_IO

1

2

3VALW

+

PEN

O

P3

J

2 1

2MM

=60mils W=60mil s

W

3VALW

I

SOLATEB

5

N

I

4

N

E

SY6288C20AAC_SOT2 3-5

PU_PCIE_WAKE# [9,27, 34]

A

12

+

L610K_0402_ 5% @

R

1 2

L22 1U_0402_10V6K

C

1 2

L23 .1U_0402_16V7K

C

3VS

+

12

L12

R
1K_0402_5 %

SOLATEB

I

12

L14

R
15K_0402_ 1%

2

L2

U

1

UT

O

2

ND

G

3

C

O

CIE_ATX_C_DRX_P4

P

CIE_ATX_C_DRX_N4

P

LAN_VDD33

LAN_VDD33

+

LAN_VDD33

+

@

12
12

12
12

12

R

10K_0402_ 5%

L70.1U_0402_1 0V7K

C

L80.1U_0402_1 0V7K

C

L40_040 2_5%

R

L50_040 2_5%

R

L170_0402_ 5% @

R

12

L1

LT_RST#

P

PU_PCIE_RST#

A

OL_EN

W

L11

C

10P_0402_ 50V8J

L12

C

10P_0402_ 50V8J

3VALW

+

CIE_ARX_DTX_P4 [6]

P

CIE_ARX_DTX_N4 [6]

P

CIE_ATX_C_DRX_P4 [6]

P

CIE_ATX_C_DRX_N4 [ 6]

P

12

TLI

X

1

3

25MHZ_10PF_7 V25000014

12

TLO

X

TAL

X

LT_RST# [9 ,10,20,27]

P

PU_PCIE_RST# [9,20,34, 38]

A

L1

Y

2

TAL0

ND0

X

G

4

TAL1

ND1

X

G

el 33 ohm follow emi @1/3

d

3

L15,RL1:

C
Only for
RTL8111 LDO mode.

EGOUT

R

ayout:

L
For RTL8111H-CG
* Place CL4 and CL5 and CL6 close to each VDD33 pin 11, 32 ,23
For RTL8106E
* Place CL5 and CL6 close to each VDD33 pin 23, 32

L2

T

AN_MDIP2

L

16

AN_MDIN2

L

L
L

L
L

L

V_DAC

+

2

1

L

L9

C

0.01U_0402_ 16V7K

ecurity Classificati on

ecurity Classificati on

ecurity Classificati on

S

S

S

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECT RONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPALELECT RONICS, INC.

3

V_DAC

+

V_DAC

+
AN_MDIP3
AN_MDIN3

AN_MDIP1
AN_MDIN1

V_DAC

+

V_DAC

+
AN_MDIP0
AN_MDIN0

Issued Date

Issued Date

Issued Date

R

15

R

14

C

13

N

12

N

11

C

10

T

9

T

350uH_NS0013LF

1000@

L1

T

16

R

15

R

14

C

13

N

12

N

11

C

10

T

9

T

350uH_NS0013LF

X+
X-

T
C
C

T
X+
X-

X+

X-

T
C
C

T
X+
X-

J45_MDIP2

R

1

J45_MDIN2

R

D+

R

2

D-

R

3

CT0

M

T

C

4

C

N

5

C

N

6

CT1

M

J45_MDIP3

R

T

C

7

J45_MDIN3

R

D+

T

8

D-

T

J45_MDIP1

R

1

J45_MDIN1

R

D+

R

2

D-

R

3

CT2

M

T

C

4

C

N

5

C

N

6

CT3

M

J45_MDIP0

R

T

C

7

J45_MDIN0

R

D+

T

8

D-

T

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

016/01/07 2017/01/07

016/01/07 2017/01/07

016/01/07 2017/01/07

2

2

2

4

Layout:
For RTL8111H-CG
* Place CL19,CL21,CL18,CL20 close to each VDD10 pin 8, 30, 3, 22
For RTL8106E
* Place CL19,CL21 close to each VDD10 pin 8, 30

1000@

1 2

L18 0_0603_5%

R

L15.1U_0402_16V7K

1

C

2

1000@

LAN_VDD33

+

1.5A

L5.1U_0402_16V7K

L4.1U_0402_16V7K

1

1

C

C

2

2

1000@

lace close to TCT pin

P

1 2

CT3

L20 75_0603_5%

M

R

1 2

CT2

M

L19 75_0603_5%

R

1 2

CT1

M

L7 75_0603 _5%1000@

R

1 2

CT0

L9 75_0603 _5%1000@

M

R

JRJ45

CONN@

J45_MDIP0

R

1

R1+

P

J45_MDIN0

R

2

R1-

P

J45_MDIP1

R

3

R2+

P

J45_MDIP2

R

4

R3+

P

J45_MDIN2

R

5

R3-

P

J45_MDIN1

R

6

R2-

P

J45_MDIP3

R

7

R4+

P

J45_MDIN3

R

8

R4-

P

ANTA_130460-N

S

DC02170213 0

Deciphered Date

Deciphered Date

Deciphered Date

4

5

L19: close to Pin8

C
CL21: close to Pin30
CL18: close to Pin3
CL20: close to Pin22

LAN_VDD10

+

mils

40

L18.1U_0402_16V7K

L21.1U_0402_16V7K

L19.1U_0402_16V7K

1

1

C

C

2

2

L20.1U_0402_16V7K

1

1

C

C

2

2

1000@

1000@

W=60mils

LAN_VDDREG

+

12

L3 0 _0603_5%

R

-GND_L
T

1

EMI@

C
10P_1206_ 2KV8J

2

12

ND

G

11

ND

G

10

ND

G

9

ND

G

itle

itle

itle

T

T

T

AN RTL8106EUS

AN RTL8106EUS

AN RTL8106EUS

L

L

L

ize

ocument Number Re v

ize

ocument Number Re v

ize

ocument Number Re v

S

D

S

D

S

D

ustom

ustom

ustom

C

C

C

Date: Sheetof

Date: Sheetof

Date: Sheetof

L6.1U_0402_16V7K

1

C

2

LAN_VDD33

+

1

1

L24

@

2

-GND

T

A-F121P

A-F121P

A-F121P

5

L25

C

4.7U_0603_6 .3V6K

@

2

Layout:
CL24: close to Pin32
CL25: close to Pin11

19 61Thursday, November 09, 2017

19 61Thursday, November 09, 2017

19 61Thursday, November 09, 2017

C

4.7U_0603_6 .3V6K

L10

-GND

T

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

L

L

L

.3(X02)

.3(X02)

.3(X02)

0

0

0