Dell Inspiron 15 3542 Schematic

5

Project code:4PD00I010001

Cedar/Janus Block Diagram

PCB P/N: 13269-1 Revision: X02

D D

GPU

VRAM(DDR3L)

2GB

78,79

*4

DDR3L

DIS only

VGA Conn. (Ja

C C

nus only)

14.0"/15"/17" LC (16:9)

Touch Pan

B B

29

Combo Ja

ck

el

MIC_IN/GND

HP_R/L

2CH SPEAKER (2CH 2W/4ohm)

29

VGA

HDMI V1 (Cedar only)

D

52

LPC debug

NVIDIA N15VGB2-64 (23x23) 25W

DP/VGA Co

.4a

Camera

MIC

Digital

HDA CODEC

Realtek ALC3234

port

GM-S-A2

nverter (Janus only)

RTD2168

54

52

27

65

4

73,74,75,76,77

HDMI

eDP

USB2.0 x 1

HDA

LPC BUS

PCIE x 4

55

3

Intel CPU

Broadwell

28W (UMA) 15W

(DIS)

ULT

DDR3L 1333/1600MHz Channel A

LAN

WPT-LP

8 USB 2.0/1.1 ports

4 USB 3.0

ports

inition Audio

High Def

4

DP

SATA ports 8 PCIE ports LPC I/F ACPI 4.0a

PCIE x 1

USB2.0 x 1

10/100 & 10/100/1000 co-

RealTek Ce

dar:(10/100)RTL8106E

Janus:(10/100/1000)RTL8111G

WLAN

802.11a/

b/g/n

BT V4.0 combo

Left side

USB1(USB3

USB3.0 x 1

Left side

USB2.0 x 1

USB2(USB2

USB3(USB2

CardReade

Realtek RTS

5170

Right side

r

.0)

34,35

2

58

DDR3L 1333/1600

SODIMM A

lay

30

IO Board

SD Card Slot

12

RJ45 Conn.

1

CHARGER

HPA02224RGRR-1-GP

INPUTS

AD+

BT+

SYSTEM DC/DC

TPS51225RUKR-GP

INPUTS

DCBATOUT

CPU Core Power

ISL95813HRZ-GP

INPUTS

DCBATOUT

DDR3L SUS

TPS51716RUKR-GP

DCBATOUT 1D35V_S3

CPU 1.05V

RT8237CZQW-2-GP

31

DCBATOUT

CPU 1D5V_S0

TLV70215DBVR-GP

3D3V_S5

OUTPUTS

DCBATOUT

OUTPUTS

3D3V_AUX_S5 5V_AUX_S5 5V_S5 3D3V_S5

OUTPUTS

VCC_CORE

OUTPUTSINPUTS

0D65V_S0

OUTPUTSINPUTS

1D05V_S0

OUTPUTSINPUTS

1D5V_S0

Switches

46,47

33

36 83

44

45

49

48

51

INPUTS OUTPUTS

1D35V_S3 5V_S5 5V_S0

1D05V_S0 3D3V_S0 1D35V_S3

1D35V_S0

3D3V_S03D3V_S5 1D05V_VGA_S0 3D3V_VGA_S0 1D35V_VGA_S0

PCB LAYER

L1:Top L2:VCC L3:Signal L4:Signal L5:GND L6:Signal

Thermal

NUVOTON NCT7718W

Fan Co

ANPEC

A A

APL5606AKI

FAN

5

26

ntrol

26

SMBUS

Int. KB

KBC

NUVOTON

NPCE285P

62

Image sen

PS2

Touch PAD

sor

SATA(Gen3) x 1

SPI

24

Flash ROM

8MB

ead

Quad R

25

SATA(Gen1) x 1

I2C

62

4

3

HDD

ODD

56

2

Wistron C

21F, 88, Sec

.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size D

ocument Number Rev

C

Date: Sheet

February 07, 2014

Date: Sheet

February 07, 2014

Date: Sheet

February 07, 2014

Taipei Hsien 221, Taiwan, R.O.C.

Block Dia

Janus HSW

1

gram

40/50/70

orporation

of

2104Friday,

of

2104Friday,

of

2104Friday,

X02

5

D D

4

3

2

1

(Blanking)

C C

B B

Wistron Corporation

A A

Title

(Reserved)

Size Document Number Rev

A4

Date: Sheet

5

4

3

Date: Sheet

2

(Reserved)

Janus HSW 40/50/70

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

3104Friday, February 07, 2014

of

1

5

4

3

2

1

SSID = CPU

1D05S_VCCST

RN401

XDP_TMS

D D

XDP_TDI XDP_TDO

XDP_TRST# XDP_TCLK

R402 51R2J-2-GP

R402 51R2J-2-GP R406 51R2J-2-GPR406 51R2J-2-GP

RN401

1 2 3

DY

4 5

SRN51J-1-GP

DY

1 2 1 2

8 7 6

1D05S_VCCST

Remove TP401 for TP604 spacing.

12

R401

62R2J-GP

Layout Note:

C C

Impedance control:50 ohm

H_PROCHOT#[24,42,44,46]

DY

H_THERMTRIP_EN[36]

1 2

R411

R411 0R2J-2-GP

0R2J-2-GP

TP403TP403

TP402TP402

H_PECI[24]

1 2

R403

1

56R2J-4-GP

Layout Note: Close to CPU

DDR_PG_CTRL[12]

B B

R407 200R2F-L-GPR407 200R2F-L-GP

1 2

R408 121R2F-GPR408 121R2F-GP

1 2

R409 100R2F-L1-GP-UR409 100R2F-L1-GP-U

1 2

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

H_CATERR#

1

H_PROCHOT#_R XDP_TRST#

H_CPUPWRGD

R405

12

10KR2J-3-GP

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 SM_DRAMRST# DDR_PG_CTRL

CPU1B

D61

PROC_DETECT#

K61

CATERR#

N62

PECI

K63

PROCHOT#

C61

PROCPWRGD

AU60

SM_RCOMP0

AV60

SM_RCOMP1

AU61

SM_RCOMP2

AV15

SM_DRAMRST#

AV61

SM_PG_CNTL1

HASWELL-6-GP-U

71.HASWE.G0U

SM_DRAMRST#

Layout Note:

Design Guideline:

MISC

THERMAL

PWR

DDR3L

HSW_ULT_DDR3L

1D35V_S3

12

R410

R410 470R2J-2-GP

470R2J-2-GP

JTAG

R404

1 2

0R0402-PAD

2 OF 19

XDP_PRDY#

J62

PRDY#

PREQ#

PROC_TCK

PROC_TMS

PROC_TRST#

PROC_TDI

PROC_TDO

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

K62 E60 E61 E59 F63 F62

J60 H60 H61 H62 K59 H63 K60 J61

XDP_PREQ# XDP_TCLK XDP_TMS

XDP_TDI XDP_TDO

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

Layout Note:

Place close to DIMM

DDR3_DRAMRST# [12]

XDP_PRDY# [96] XDP_PREQ# [96] XDP_TCLK [96] XDP_TMS [96] XDP_TRST# [96] XDP_TDI [96] XDP_TDO [96]

XDP_BPM[7:0]

XDP_BPM[7:0] [96]

SM_RCOMP keep routing length less than 500 mils.

Wistron Corporation

A A

Title

CPU (THERMAL/MISC/PM)

Size Document Number Rev

A4

Date: Sheet

5

4

3

Date: Sheet

2

CPU (THERMAL/MISC/PM)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

4104Friday, February 07, 2014

of

1

A00

5

4

3

2

1

SSID = CPU

DDR3L ball type: Non-Interleaved Type

HSW_ULT _DDR3 L

CPU1D

AW31 AW29

AW27 AW25

AM29

AM26

AW23 AW21

AW19 AW17

AM22

AM20

AY31 AY29 AV31

AU31 AV29 AU29 AY27

AY25 AV27

AU27 AV25 AU25

AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26

AK25 AL25 AY23

AY21 AV23

AU23 AV21 AU21 AY19

AY17 AV19

AU19 AV17 AU17 AR21 AR22 AL21

AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20

AR18 AP18

CPU1D

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

HSW_ULT _DDR3 L

CPU1C

AW58 AW56

AW54 AW52

AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58

AY56 AV58

AU58 AV56 AU56 AY54

AY52 AV54

AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51

CPU1C

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

M_A_DQ[63:0][12]

D D

C C

M_A_DQ[63:0]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

HSW_ULT _DDR3 L

DDR CHANNEL A

3 OF 19

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1 SA_CKE0

SA_CKE1 SA_CKE2 SA_CKE3

SA_CS#0 SA_CS#1

SA_ODT0 SA_RAS#

SA_WE#

SA_CAS#

SA_BA0 SA_BA1 SA_BA2

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32 AY34

AW34 AU34

AU35 AV35 AY41

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AP49 AR51 AP51

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

+V_SM_VREF_CNT

M_A_DIMA_CLK_DDR#0 [12] M_A_DIMA_CLK_DDR0 [12] M_A_DIMA_CLK_DDR#1 [12] M_A_DIMA_CLK_DDR1 [12]

M_A_DIMA_CKE0 [12] M_A_DIMA_CKE1 [12]

M_A_DIMA_CS#0 [12] M_A_DIMA_CS#1 [12]

TP_M_A_DIMA_ODT0

M_A_RAS# [12]

M_A_WE# [12]

M_A_CAS# [12]

M_A_BS0 [12] M_A_BS1 [12] M_A_BS2 [12]

M_A_A[15:0] [12]

M_A_DQS#[7:0] [12]

M_A_DQS[7:0] [12]

+V_SM_VREF_CNT [37] DDR_WR_VREF01 [37]

TP501TP501

1

HSW_ULT _DDR3 L

DDR CHANNEL B

4 OF 19

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_CS#0 SB_CS#1

SB_ODT0 SB_RAS#

SB_WE#

SB_CAS#

SB_BA0 SB_BA1 SB_BA2

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AM38 AN38 AK38 AL38

AY49 AU50 AW49 AV50

AM32 AK32

AL32 AM35

AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

HASWELL-6-GP-U

B B

A A

5

4

3

HASWELL-6-GP-U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u R d., Hsichih,

21F, 88, Sec.1, Hsin Tai W u R d., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU (DDR)

Janus HSW 40/50/70

1

5104Friday, February 07, 2014

A00

of

5

SSID = CPU

4

3

2

1

D D

CFG[19:0][96]

C C

PCH strap pin:

#514405

CFG[19:0]

1 2

R601

R601 49D9R2F-GP

49D9R2F-GP

1 2

R603

R603 8K2R2F-1-GP

8K2R2F-1-GP

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCOMP

TD_IREF

CFG3

AC60 AC62 AC63 AA63 AA60

Y62 Y61 Y60 V62 V61 V60 U60 T63 T62 T61 T60

AA62

U63

AA61

U62 V63

H18 B12

J20

CPU1S

A5 E1

D1

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCOMP RSVD#A5 RSVD#E1

RSVD#D1 RSVD#J20 RSVD#H18 TD_IREF

12

DY

R604

R604 1KR2J-1-GP

1KR2J-1-GP

HSW_ULT_DDR3L

RESERVED

PROC_OPI_RCOMP

19 OF 19

RSVD_TP#AV63 RSVD_TP#AU63

RSVD_TP#C63 RSVD_TP#C62

RSVD#B43

RSVD_TP#A51 RSVD_TP#B51

RSVD_TP#L60

RSVD#N60

RSVD#W23

RSVD#Y22

RSVD#AV62

RSVD#D58

VSS VSS

RSVD#P20 RSVD#R20

PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

0 : ENABLED

CFG[3]

SET DFX ENABLED BIT IN DEBUG INTERFACE MSR

AV63 AU63

C63 C62 B43

A51 B51

L60 N60 W23

PROC_OPI_COMP3

Y22

PROC_OPI_COMP

AY15 AV62

D58 P22

N21

HVM_CLK#

P20

HVM_CLK

R20

RSVDAV63 RSVDAU63

RSVDC63 RSVDC62 EDP_SPARE

RSVDA51 RSVDB51

RSVDL60

TP601TP601

1

TP602TP602

1

TP603TP603

1

TP604TP604

1

TP605TP605

1

TP606TP606

1

TP607TP607

1

TP608TP608

1

Intel Recommend

R606 49D9R2F-GP

1 2

DY

R602 49D9R2F-GPR602 49D9R2F-GP

1 2

1

TP619TP619

1

TP620TP620

#514405

Layout Note:

1.Referenced "continuous" VSS plane only.

2.Avoid routing next to clock pins or noisy signals.

3.Trace width: 12~15mil

4.Isolation Spacing: 12mil

5.Max length: 500mil

1 : DISABLED

B B

CFG4

12

R605

R605 1KR2J-1-GP

1KR2J-1-GP

DISPLAY PORT PRESENCE STRAP

0 : ENABLED

CFG[4]

AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE EMBEDDED DISPLAY PORT

1 : DISABLED

NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU (CFG)

Janus HSW 40/50/70

6104Friday, February 07, 2014

1

of

A00

5

SSID = CPU

4

3

2

1

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57

VCC_CORE

HSW_ULT_DDR3L

CPU1L

D D

1D35V_S3

1D05S_VCCST

NC#1

VCC

A

DY

GND3Y

VR_SVID_ALERT#

H_CPU_SVIDDAT

3D3V_S5

SCD1U16V2KX-3GP

C702

1D05S_VCCST

12

DY

12

R706

R706 10KR2J-3-GP

10KR2J-3-GP

DY

R709

R709 47KR2F-GP

47KR2F-GP

DY

5

4

12

Need to fine tune to 1.05V.

EC701

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Length match<25mil

VCC_SENSE[46]

VR_SVID_ALERT#[46]

H_CPU_SVIDCLK[46] H_CPU_SVIDDAT[46]

H_VR_ENABLE[46]

PWR_DEBUG[96]

1D05S_VCCST

H_VCCST_PWRGD [96]

12

DY

SCD1U16V2KX-3GP

1D05V_S0

0R0603-PAD-1-GP-U

R711

1 2

1D05S_VCCST

DY

VCC_CORE

12

R702

100R2F-L1-GP-U

TP701TP701

R701

43R2J-GP

1 2

H_CPU_SVIDCLK H_CPU_SVIDDAT

R710 10KR2J-3-GP

1 2

DY

1 2

TP702TP702 TP703TP703 TP704TP704 TP705TP705

DY

1 1 1 1

IMVP_PW RGD_R

R705 150R2J-L1-GP-UR705 150R2J-L1-GP-U

0.1A

12

C701

C703

DY

C703

DY

SC1U10V2KX-1GP

SC22U6D3V5MX-2GP

VCC_CORE

TP_VCCIO_OUT

1

+VCCIOA_OUT

H_CPU_SVIDALRT#

H_VCCST_PWRGD

PWR_DEBUG RSVDP60

RSVDP61 RSVDN59 RSVDN61

1D05S_VCCST

VCC_CORE

R703 75R2F-2-GPR703 75R2F-2-GP

1 2

R704 130R2F-1-GPR704 130R2F-1-GP

1 2

#487822

C C

U701

1

1D05V_VTT_PWRGD[36,48]

B B

2

74LVC1G07GW-GP

73.01G07.0HG

1 2

R707

R707 100KR2F-L1-GP

100KR2F-L1-GP

CPU1L

L59

J58

AH26

AJ31 AJ33

AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

F59 N58

AC58

E63

AB23

A59

E20 AD23 AA23 AE59

L62

N63

L63

B59

F60

C59

D63

H59

P62

P60

P61

N59

N61

T59 AD60 AD59 AA59 AE60 AC59 AG58

U59

V59 AC22

AE22 AE23

AB57 AD57 AG57

C24

C28

C32

HASWELL-6-GP-U

RSVD#L59 RSVD#J58

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCC RSVD#N58 RSVD#AC58

VCC_SENSE RSVD#AB23 VCCIO_OUT VCCIOA_OUT RSVD#AD23 RSVD#AA23 RSVD#AE59

VIDALERT# VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY

VSS PWR_DEBUG# VSS RSVD_TP#P60 RSVD_TP#P61 RSVD_TP#N59 RSVD_TP#N61 RSVD#T59 RSVD#AD60 RSVD#AD59 RSVD#AA59 RSVD#AE60 RSVD#AC59 RSVD#AG58 RSVD#U59 RSVD#V59

VCCST VCCST VCCST

VCC VCC VCC VCC VCC VCC

HSW_ULT_DDR3L

HSW ULT POWER

12 OF 19

IMVP_PW RGD[24,46]

A A

5

4

1 2

R713

R713 100KR2F-L1-GP

100KR2F-L1-GP

IMVP_PW RGD_R

12

R712

R712 47KR2F-GP

47KR2F-GP

3

EC702

12

DY

SCD1U16V2KX-3GP

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, February 07, 2014

Date: Sheet

CPU (VCC CORE)

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

7104

of

1

of

A00

5

www.vinaﬁx.vn

4

3

2

1

SSID = CPU

D D

HSW_ULT_DDR3L

CPU1A

HSW_ULT_DDR3L

1 OF 19

PCH_DPB_N0[55]

PCH_DPB_P0[55]

PCH_DPB_N1[55]

PCH_DPB_P1[55]

C C

DP to VGA Converter

C54

DDI1_TXN0

C55

DDI1_TXP0

B58

DDI1_TXN1

C58

DDI1_TXP1

B55

DDI1_TXN2

A55

DDI1_TXP2

A57

DDI1_TXN3

B57

DDI1_TXP3

C51

DDI2_TXN0

C50

DDI2_TXP0

C53

DDI2_TXN1

B54

DDI2_TXP1

C49

DDI2_TXN2

B50

DDI2_TXP2

A53

DDI2_TXN3

B53

DDI2_TXP3

HASWELL-6-GP-U

EDPDDI

EDP_RCOMP

EDP_DISP_UTIL

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

C45 B46 A47 B47

C47 C46 A49 B49

A45 B45

D20 A43

EDP_COMP EDP_BRIGHTNESS

EDP_TX0_DN [52] EDP_TX0_DP [52] EDP_TX1_DN [52] EDP_TX1_DP [52]

EDP_AUX_DN [52] EDP_AUX_DP [52]

1

TP801TP801

R801

24D9R2F-L-GP

+VCCIOA_OUT

Design Guideline: EDP_COMP keep routing length max 100 mils.

12

Trace Width:20 mils.

B B

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU (DDI/EDP)

Janus HSW 40/50/70

8104Friday, February 07, 2014

of

X02

5

4

3

2

1

SSID = CPU

HSW_ULT_DDR3L

CPU1P

D33

VSS

D34

D D

C C

B B

VSS

D35

VSS

D37

VSS

D38

VSS

D39

VSS

D41

VSS

D42

VSS

D43

VSS

D45

VSS

D46

VSS

D47

VSS

D49

VSS

D5

VSS

D50

VSS

D51

VSS

D53

VSS

D54

VSS

D55

VSS

D57

VSS

D59

VSS

D62

VSS

D8

VSS

E11

VSS

E17

VSS

F20

VSS

F26

VSS

F30

VSS

F34

VSS

F38

VSS

F42

VSS

F46

VSS

F50

VSS

F54

VSS

F58

VSS

F61

VSS

G18

VSS

G22

VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS

H13

VSS

HASWELL-6-GP-U

HSW_ULT_DDR3L

16 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS_SENSE

VSS

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

V58 AH46 V23 E62 AH16

VSS_SENSE

12

VSS_SENSE [46]

Layout Note:

R901

100R2F-L1-GP-U

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Length match<25mil

Wistron Corporation

A A

Title

CPU (VSS)

Size Document Number Rev

A4

Date: Sheet

5

4

3

Date: Sheet

2

CPU (VSS)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

9104Friday, February 07, 2014

of

1

A00

5

4

3

2

1

SSID = CPU

1D35V_S3

D D

12

C1002

C1001

SC10U10V5KX-2GP

12

C C

C1018

C1017

SC2D2U6D3V2MX-GP

12

DY

C1003

C1004

SC10U10V5KX-2GP

12

DY

C1020

C1019

DY

SC2D2U6D3V2MX-GP

12

DY

C1006

C1005

SC10U10V5KX-2GP

Layout Note:

Direct tie to CPU VccIn/Vss balls

Layout Note:

As close to CPU as possible

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (Power CAP1)

Size Document Number Rev

A3

Date: Sheet

CPU (Power CAP1)

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

10 104Friday, February 07, 2014

of

1

of

A00

5

4

3

2

1

MAX: 1.92A

1.838A 41mA 42mA

D D

R1101

1 2

0R0805-PAD-1-GP-U

CAP need close to pin K9 L10

+V1.05DX_MODPHY_PCH1D05V_HSIO

C1101

C1102

12

SC1U10V2KX-1GP

1D05V_HSIO

L1101 0R3J-0-U-GPL1101 0R3J-0-U-GP

1 2

12

CAP need close to pin B18

+V1.05S_AUSB3PLL

C1103

12

DY

C1104

SC1U10V2KX-1GP

+V1.05S_AUSB3PLL

12

DY

C1123

SC10U10V5KX-2GP

1D05V_HSIO

L1102 0R3J-0-U-GPL1102 0R3J-0-U-GP

1 2

C1105

12

SC10U10V5KX-2GP

CAP need close to pin B11

+V1.05S_ASATA3PLL

12

DY

C1106

SC1U10V2KX-1GP

SC10U10V5KX-2GP

C1107

SC10U10V5KX-2GP

57mA 62mA 185mA

DY

SC1U10V2KX-1GP

12

+V1.05S_APLLOPI

12

DY

C1110

SC10U10V5KX-2GP

+V3.3A_PSUS3D3V_S5_PCH

R1103

1 2

0R0603-PAD-1-GP-U

C1124

SC10U10V5KX-2GP

CAP need close to pin AC9

DY

12

C1108

SC10U10V5KX-2GP

L1103 IND-2D2UH-196-GP

1 2

68.2R21D.10R

C1111

12

SC1U10V2KX-1GP

CAP need close to pin J18

12

DY

+V1.05S_AXCK_DCB1D05V_S0

+V1.05S_AXCK_DCB

12

DY

C1112

C1125

SC10U10V5KX-2GP

1D05V_S0

C C

R1102

1 2

0R0603-PAD-1-GP-U

+V1.05S_APLLOPI

C1109

12

CAP need close to pin AA21

31mA 658mA 1.632A 1mA

1D05V_S0

IND-2D2UH-196-GP

IND-2D2UH-196-GP L1104

L1104

1 2

68.2R21D.10R

B B

+V1.05S_AXCK_LCPLL

C1113

12

DY

C1114

1D05V_S0

R1104

1 2

0R0603-PAD-1-GP-U

DY

C1116

12

C1115

1D05V_S0

12

R1105

1 2

0R0805-PAD-1-GP-U

C1117

12

C1118

+V1.05S_CORE_PCH+1.05M_ASW

C1120

SCD1U16V2KX-3GP

12

DY

C1119

SCD1U16V2KX-3GP

12

DY

C1121

SCD1U16V2KX-3GP

RTC_AUX_S5

12

C1122

12

SC1U10V2KX-1GP

SC10U10V5KX-2GP

SC1U10V2KX-1GP

SC10U10V5KX-2GP

CAP need close to pin A20

A A

5

SC10U10V5KX-2GP

CAP need close to pin AE9

4

SC10U10V5KX-2GP

CAP need close to pin AE8 J11

3

SC1U10V2KX-1GP

SC10U10V5KX-2GP

CAP need close to pin AG10

2

SC1U10V2KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (Power CAP2)

Size Document Number Rev

A3

Date: Sheet

CPU (Power CAP2)

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

11 104Friday, February 07, 2014

of

1

of

A00

5

4

3

2

1

SSID = MEMORY

SA0_DIMA SA1_DIMA

12

R1202

0R0402-PAD

DM1

D D

M_VREF_CA_DIMMA

12

DY

12

C1215

DY

12

C1218

C1202

SCD1U16V2KX-3GP

M_VREF_DQ_DIMMA

12

C1206

C1205

SC2D2U10V3KX-1GP

12

C1216

SC1U10V2KX-1GP

12

C1201

C C

B B

A A

SCD1U16V2KX-3GP

12

C1204

0D675V_S0

SCD1U16V2KX-3GP

12

C1214

SC1U10V2KX-1GP

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

Layout Note:

Place these caps close to VREF_CA

SCD1U16V2KX-3GP

Layout Note:

Place these caps close to VREF_DQ

SCD1U16V2KX-3GP

DDR3_DRAMRST#[4]

M_A_A[15:0][5]

M_A_BS2[5] M_A_BS0[5]

M_A_BS1[5]

M_A_DQ[63:0][5]

Layout Note:

Place these caps close to VTT1 and VTT2.

M_A_DQS#[7:0][5]

M_A_DQS[7:0][5]

M_VREF_CA_DIMMA M_VREF_DQ_DIMMA

M_A_DIMA_ODT0 M_A_DIMA_ODT1

0D675V_S0

12

C1217

SCD1U16V2KX-3GP

DY

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ13 M_A_DQ8 M_A_DQ14 M_A_DQ10 M_A_DQ9 M_A_DQ12 M_A_DQ15 M_A_DQ11 M_A_DQ29 M_A_DQ28 M_A_DQ30 M_A_DQ31 M_A_DQ25 M_A_DQ24 M_A_DQ27 M_A_DQ26 M_A_DQ44 M_A_DQ41 M_A_DQ43 M_A_DQ47 M_A_DQ45 M_A_DQ40 M_A_DQ42 M_A_DQ46 M_A_DQ51 M_A_DQ50 M_A_DQ49 M_A_DQ48 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ6 M_A_DQ5 M_A_DQ4 M_A_DQ3 M_A_DQ7 M_A_DQ21 M_A_DQ20 M_A_DQ17 M_A_DQ16 M_A_DQ18 M_A_DQ19 M_A_DQ22 M_A_DQ23 M_A_DQ36 M_A_DQ33 M_A_DQ34 M_A_DQ38 M_A_DQ37 M_A_DQ32 M_A_DQ35 M_A_DQ39 M_A_DQ62 M_A_DQ58 M_A_DQ60 M_A_DQ61 M_A_DQ63 M_A_DQ59 M_A_DQ56 M_A_DQ57

M_A_DQS#1 M_A_DQS#3 M_A_DQS#5 M_A_DQS#6 M_A_DQS#0 M_A_DQS#2 M_A_DQS#4 M_A_DQS#7

M_A_DQS1 M_A_DQS3 M_A_DQS5 M_A_DQS6 M_A_DQS0 M_A_DQS2 M_A_DQS4 M_A_DQS7

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-48-GP-U

62.10017.P41

RAS# CAS#

CKE0 CKE1

EVENT#

VDDSPD

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

CS0# CS1#

CK0#

CK1#

NC#1 NC#2

NP1

NP2

110 113

WE#

115 114

121 73

74 101

CK0

103 102

CK1

104 11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198 199

SA0_DIMA

197

SA0

SA1_DIMA

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D35V_S3

M_A_RAS# [5] M_A_WE# [5] M_A_CAS# [5]

M_A_DIMA_CS#0 [5] M_A_DIMA_CS#1 [5]

M_A_DIMA_CKE0 [5] M_A_DIMA_CKE1 [5]

M_A_DIMA_CLK_DDR0 [5] M_A_DIMA_CLK_DDR#0 [5]

M_A_DIMA_CLK_DDR1 [5] M_A_DIMA_CLK_DDR#1 [5]

PCH_SMBDATA [18,62,96] PCH_SMBCLK [18,62,96]

3D3V_S0

12

C1203

DY

SCD1U16V2KX-3GP

1D35V_S3

Layout Note:

Place these Caps near SO-DIMMA.

0R0402-PAD

TC1201

C1210

12

DY

C1207

SC10U10V5KX-2GP

ST330U2VDM-4-GP

12

C1211

SCD1U16V2KX-3GP

12

DY

12

DY

DDR_PG_CTRL[4]

Q1201 must use Vth=1V.

close to dimm

5

4

3

Note: SA0 DIM0 = 0, SA1_DIM0 = 0

12

SO-DIMMA SPD Address is 0xA0

R1201

0R0402-PAD

SO-DIMMA TS Address is 0x30

12

C1208

C1209

SC10U10V5KX-2GP

12

C1213

C1212

SC1U10V2KX-1GP

R1205

DDR_PG_CTRL_R

1 2

0R0402-PAD

C1220SCD1U16V2KX-3GP C1220SCD1U16V2KX-3GP12C1221SCD1U16V2KX-3GP C1221SCD1U16V2KX-3GP

84.05067.031

12

C1222SCD1U16V2KX-3GP C1222SCD1U16V2KX-3GP

1D35V_S3

Q1201

DMN5L06K-7-GP

G

Vth = 1V max.

DS

2

5V_S5

12

DY

R1208

R1208 220KR2J-L2-GP

220KR2J-L2-GP

DDR_VTT_PG_CTRL

R1204

R1204 2MR2-GP

2MR2-GP

1D35V_S3

D

G

Q1202

Q1202 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

S

M_A_B_DIMM_ODT

DDR_VTT_PG_CTRL [49]

R1206 66D5R2F-GPR1206 66D5R2F-GP

1 2

R1207 66D5R2F-GPR1207 66D5R2F-GP

1 2

Title

Size Document Number Rev

Size Document Number Rev A2

A2

A2 Date: Sheet

Date: Sheet

Friday, February 07, 2014

DDR3-SODIMM1

Janus HSW 40/50/70

M_A_DIMA_ODT0 M_A_DIMA_ODT1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u R d., Hsichih,

21F, 88, Sec.1, Hsin Tai W u R d., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

12 104

1

12 104

of

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)DDR3-SODIMM2

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, February 07, 2014

Date: Sheet

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

13 104

of

1

of

A00

5

D D

4

3

2

1

C C

(Blanking)

B B

Wistron Corporation

A A

Title

(Reserved)_SODIMM _SODIMM4

Size Document Number Rev

A4

Date: Sheet

5

4

3

Date: Sheet

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

14 104Friday, February 07, 2014

of

1

A00

5

4

3

2

1

SSID = CPU

PCH strap pin:

Port B Detected

DDPB_CTRLDATA

D D

DDPC_CTRLDATA

Low = Disable Port B (default) High = Enable Port B

*

Low = Disable Port C (default)

*

High = Enable Port C

The internal pull-down is disabled after PLTRST# deasserts

3D3V_S0

1

RN1501

SRN2K2J-1-GP

HSW_ULT_DDR3L

eDP SIDEBAND

PCIE

HSW_ULT_DDR3L

DISPLAY

CPU1I

L_BKLT_CTRL[52] L_BKLT_EN[24] EDP_VDD_EN[52]

RN1503

1 2 3

OPS

C C

3D3V_S0

SRN10KJ-5-GP

R1509

1 2

OPS

UMA

RN1505

1 2 3 4 5

SRN10KJ-6-GP

DGPU_HOLD_RST#

4

DGPU_PWR_EN PIRQB#

DGPU_PWROK

100KR2J-1-GP

8 7 6

PIRQC# PIRQD#

PIRQB#

INT_TP#[20,24,62]

CLK_PCIE_WLAN_REQ3# [18,58]

PIRQA#[20]

TP1501TP1501

R1512

R1512 0R2J-2-GP

0R2J-2-GP

DGPU_PWR_EN[82,83]

DGPU_HOLD_RST#[73]

1 2

DGPU_PWROK[24,82,83]

12

DY

EC1501

SC1KP50V2KX-1GP

PIRQC# PIRQD# PCI_PME#

1

INT_TP#_GPIO55

12

DY

EC1502

SC1KP50V2KX-1GP

B8

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

U6

PIRQA#/GPIO77

P4

PIRQB#/GPIO78

N4

PIRQC#/GPIO79

N2

PIRQD#/GPIO80

AD4

PME#

U7

GPIO55

L1

GPIO52

L3

GPIO54

R5

GPIO51

L4

GPIO53

HASWELL-6-GP-U

9 OF 19

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP

DDPB_HPD DDPC_HPD

EDP_HPD

B9 C9 D9 D11

C5 B6 B5 A6

C8 A8 D6

SRN2K2J-1-GP

DDPB_CTRLCLK DDPB_CTRLDATA

DDPC_CTRLDATA

EE Note: If layout is on constraint, please reserve TP for DDPC_CTRLCLK.

CRT_PCH_HPD [55] EDP_HPD [52]

23

4

1

TP1502TP1502

PCH_DPB_AUXN [55] PCH_DPB_AUXP [55]

B B

A A

5

3D3V_S0

12

R1510

R1510 10KR2J-3-GP

10KR2J-3-GP

Cedar

CEDAR/JANUS_ID

R1511

R1511 10KR2J-3-GP

10KR2J-3-GP

Janus

CEDAR/JANUS_ID [19]

4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

3

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

PCH ( EDP/GPIO/DDI )

Janus HSW 40/50/70

15 104Friday, February 07, 2014

of

1

of

X02

5

4

3

2

1

SSID = PCH

HSW_ULT_DDR3L

CPU1K

CPU_RXN_C_dGPU_TXN0[73] CPU_RXP_C_dGPU_TXP0[73]

dGPU_RXN_C_CPU_TXN0[73] dGPU_RXP_C_CPU_TXP0[73]

D D

CPU_RXN_C_dGPU_TXN1[73] CPU_RXP_C_dGPU_TXP1[73]

dGPU_RXN_C_CPU_TXN1[73] dGPU_RXP_C_CPU_TXP1[73]

CPU_RXN_C_dGPU_TXN2[73] CPU_RXP_C_dGPU_TXP2[73]

dGPU_RXN_C_CPU_TXN2[73] dGPU_RXP_C_CPU_TXP2[73]

CPU_RXN_C_dGPU_TXN3[73] CPU_RXP_C_dGPU_TXP3[73]

dGPU_RXN_C_CPU_TXN3[73] dGPU_RXP_C_CPU_TXP3[73]

PCIE_PRX_WLANTX_N3[58] PCIE_PRX_WLANTX_P3[58]

PCIE_PTX_WLANRX_N3_C[58] PCIE_PTX_WLANRX_P3_C[58]

PCIE_PRX_LANTX_N4[30] PCIE_PRX_LANTX_P4[30]

PCIE_PTX_LANRX_N4_C[30]

C C

PCIE_PTX_LANRX_P4_C[30]

+V1.05S_AUSB3PLL

B B

C1606

C1606 C1605

C1605

C1608

C1608 C1607

C1607

C1610

C1610 C1609

C1609

C1612

C1612 C1611

C1611

C1601

C1601 C1602

C1602

C1603

C1603 C1604

C1604

Layout Note:

1. PCIE_RCOMP/ PCIE_IREF trace width=12~15mil

2. Isolation Spacing: 12mil

3. Total trace length<500mil

1 2 1 2

R1601

3KR2F-GP

1 2

SCD1U16V2KX-3GP

dGPU_RXN_CPU_TXN0

OPS

dGPU_RXP_CPU_TXP0

OPS

SCD1U16V2KX-3GP

dGPU_RXN_CPU_TXN1

OPS

dGPU_RXP_CPU_TXP1

OPS

SCD1U16V2KX-3GP

dGPU_RXN_CPU_TXN2

OPS

dGPU_RXP_CPU_TXP2

OPS

SCD1U16V2KX-3GP

dGPU_RXN_CPU_TXN3

OPS

dGPU_RXP_CPU_TXP3

OPS

SCD1U16V2KX-3GP

PCIE_PTX_WLANRX_N3 PCIE_PTX_WLANRX_P3

SCD1U16V2KX-3GP

PCIE_PTX_LANRX_N4 PCIE_PTX_LANRX_P4

SCD1U16V2KX-3GP

PCIE_RCOMP

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

C22

PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

E6

PERN5_L3

F6

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

RSVD#E15

E13

RSVD#E13

A27

PCIE_RCOMP

B27

PCIE_IREF

GPU

WLAN

LAN

HASWELL-6-GP-U

HSW_ULT_DDR3L

PCIE USB

11 OF 19

USB2N0

USB2P0

USB2N1

USB2P1

USB2N2

USB2P2

USB2N3

USB2P3

USB2N4

USB2P4

USB2N5

USB2P5

USB2N6

USB2P6

USB2N7

USB2P7

USB3RN1 USB3RP1

USB3TN1

USB3TP1

USB3RN2 USB3RP2

USB3TN2

USB3TP2

USBRBIAS#

USBRBIAS RSVD#AN10 RSVD#AM10

OC0/GPIO40# OC1/GPIO41# OC2/GPIO42# OC3/GPIO43#

AN8 AM8

AR7 AT7

AR8 AP8

AR10 AT10

AM15 AL15

AM13 AN13

AP11 AN11

AR13 AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10 AJ11 AN10 AM10

AL3 AT1 AH2 AV3

USB_PN3 USB_PP3

USB_COMP

USB_OC#0_1 USB_OC#2_3 USB_OC#4_5 USB_OC#6_7

PM_SUSWARN#_R[17]

USB 2.0 Table

Pair

USB_PN0 [34] USB_PP0 [34]

USB_PN1 [34] USB_PP1 [34]

USB_PN2 [63]

1 2

USB_OC#0_1 [18,35] USB_OC#2_3 [35]

USB_OC#4_5 [20]

USB_OC#2_3 USB_OC#6_7

USB_PP2 [63]

USB_PN4 [52] USB_PP4 [52]

USB_PN5 [58] USB_PP5 [58]

USB_PN6 [52] USB_PP6 [52]

USB_PN7 [63] USB_PP7 [63]

USB3_PRX_CTX_N0 [34] USB3_PRX_CTX_P0 [34]

USB3_PTX_CRX_N0 [34] USB3_PTX_CRX_P0 [34]

1. USB_COMP using 50 ohm single-ended impedance

2. Isolation Spacing :15mil

3. Total trace length<500mil

RN1601

8 7 6

SRN10KJ-6-GP

Layout Note:

3D3V_S5_PCH

1 2 3 45

TP1601TP1601

1

TP1602TP1602

1

R1602

R1602 22D6R2F-L1-GP

22D6R2F-L1-GP

MCP_GPIO73[18]

Device

USB3.0 port1

0

USB2.0 Port2 (Debug Port)

1

USB2.0 Port3 (IOBD)

2

X

3

CAMERA

4

WLAN

5

Touch Panel

6

Card Reader

7

#515621

PCIE Table

Port

1

2

3

4

5(L0~L3)

A A

6(L3)

6(L2)

6(L0~L1)

5

Device

N/A

Share BUS

USB3.0_3

USB3.0_4

WLAN

LAN

GPU

HDD

SATA0

ODD SATA1

N/A

GPU GPU GPU GPU

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

GPU GPU GPU GPU

Title

Size Document Number Rev

A3

Date: Sheet

4

3

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

PCH (PCIE/USB)

Janus HSW 40/50/70

16 104Friday, February 07, 2014

1

A00

of

A00

5

4

3

2

1

SSID = PCH

RN1703

1

D D

R1717 10KR2J-3-GP

XDP_DBRESET#[96]

SYS_PWROK[24,96] PCH_PWROK[24,26,36]

C C

PM_SUSWARN#_R[16]

PM_PWRBTN#[24,96] AC_PRESENT[24,76]

BATLOW#[20]

AC_PRESENT

EC1707

12

DY

SCD1U16V2KX-3GP

3D3V_S5

B B

A A

SCD1U16V2KX-3GP

RN1701

1 2 3

SRN10KJ-5-GP

SRN10KJ-5-GP R1703

R1703

1 2

1KR2J-1-GP

3D3V_S5_PCH

1 2

DY

R1724 10KR2J-3-GP

12

DY

EC1706

SC1KP50V2KX-1GP

EC1702

4

(CRB#514469)

12

DY

SC1KP50V2KX-1GP

EC1703

5

MCP_GPIO12 AC_PRESENT

PM_SUS_STAT#

SC1KP50V2KX-1GP

2 3

SRN10KJ-5-GP

12

DY

PCH_WAKE#

12

DY

EC1704

SC1KP50V2KX-1GP

12

DY

4

EC1705

3D3V_S0

12

R1706

1 2

0R0402-PAD

PLT_RST#[24,30,36,52,58,65,73,96]

100KR2J-1-GP

12

DY

SC1KP50V2KX-1GP

PM_RSMRST# PM_PCH_PWROK

SYS_PWROK

R1701

R1701 10KR2J-3-GP

10KR2J-3-GP

TP1706TP1706 TP1705TP1705

R1715

DY

MCP_GPIO12 [20]

XDP_DBRESET#

SYS_PWROK PLT_RST# PCH_PWROK KBC_DPWROK

R1707

1 2

0R0402-PAD

12

DY

PM_SUSACK#_R XDP_DBRESET# PCH_DPWROK PM_RSMRST# SYS_PWROK

PM_PCH_PWROK

MPWROK PCI_PLTRST#

PM_RSMRST# PM_SUSWARN#_R PM_PWRBTN# AC_PRESENT BATLOW#

R1713

PCH_SLP_S0# PCH_SLP_WLAN#

PCI_PLTRST#

4

1 1

1 2

0R0402-PAD

0R0402-PAD C1701

C1701 SC220P50V2KX-3GP

SC220P50V2KX-3GP

CPU1H

AK2

SUSACK#

AC3

SYS_RESET#

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST#

AW6

RSMRST#

AV4

SUSWARN#/SUSPWRDNACK#/GPIO30

AL7

PWRBTN#

AJ8

ACPRESENT/GPIO31

AN4

BATLOW#/GPIO72

AF3

SLP_S0#

AM5

SLP_WLAN#/GPIO29

HASWELL-6-GP-U

PM_SUSACK#[24]

PM_SUSWARN#[24]

HSW_ULT_DDR3L

SYSTEM POWER MANAGEMENT

NON DS3

R1708

1 2

0R2J-2-GP

RN1702

2 3

DS3

1

4

SRN0J-6-GP

3D3V_AUX_S5

R1726

R1726 10KR2J-3-GP

10KR2J-3-GP

1 2

3V_5V_POK#

SUS_STAT#/GPIO61

PM_SUSACK#_RPM_SUSWARN#_R

PM_SUSACK#_R PM_SUSWARN#_R

R1727

100KR2J-1-GP

1 2

NON DS3

5 6

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

3

PCH strap pin:

On Die DSW VR Enable

DSWVRMEN

This signal has no integrated pull-up/pull-down.

8 OF 19

DPWROK

WAKE#

SLP_S4# SLP_S3#

SLP_A#

SLP_SUS#

SLP_LAN#

AW7 AV5 AJ5

V5 AG4 AE6 AP5

AJ6 AT4 AL5 AP4 AJ7

PCH_DPWROK

PM_RSMRST# 3V_5V_POK_C

DSWVRMEN

CLKRUN#/GPIO32

SUSCLK/GPIO62

SLP_S5#/GPIO63

Q1701

34 2 1

2N7002KDW-GP

Low = Disable High = Enable (default)

*

DSWODVREN PCH_WAKE#

PM_CLKRUN# PM_SUS_STAT# SUS_CLK_PCH PM_SLP_S5#

PM_SLP_S4# PM_SLP_S3# PM_SLP_A# PM_SLP_SUS# PM_SLP_LAN#

R1718 0R2J-2-GP

1KR2J-1-GP

1KR2J-1-GP R1702

R1702

1 2

R1728

1 2

NON DS3

0R2J-2-GP

DS3

R1729

1 2

0R2J-2-GP

NON DS3

1 1

1 2

DS3

R1704

0R2J-2-GP

1 2 1 2

DY

R1705

R1705 0R2J-2-GP

0R2J-2-GP

R1709

1 2

TP1702TP1702

R1710

1 2

TP1703TP1703

TP1704TP1704 TP1707TP1707

DS3

1 2

RSMRST#_KBC [24] 3V_5V_POK [45]

PM_SLP_SUS#

DSWODVREN

R1705: DY for OBFF disable

0R0402-PAD

0R0402-PAD 0R2J-2-GP

0R2J-2-GP

PM_SLP_S4# [24,49]

PM_SLP_S3# [24,36,48,49,51]

PM_SLP_SUS# [24,38]

R1725

R1725 100KR2F-L1-GP

100KR2F-L1-GP

2

PCIE_WAKE# [24,30]

PM_CLKRUN#_EC [24]

SUS_CLK [24]

KBC_DPWROK [24]

PM_CLKRUN#

SUS_CLK_PCH

Title

Size Document Number Rev

Date: Sheet

A3

R1720

330KR2J-L1-GP

1 2 1 2

DY

R1721

330KR2J-L1-GP

R1714

8K2R2F-1-GP

1 2

RTC_AUX_S5

3D3V_S0

EC1701

DY

SC4D7P50V2CN-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (PM)

Janus HSW 40/50/70

DY

1 2

17 104Friday, February 07, 2014

1

A00

of

A00

5

4

3

2

1

SSID = PCH

C1801

R1810

XTAL24_IN XTAL24_IN_R

D D

3D3V_S0

RN1801

LPC_AD2 LPC_AD1 LPC_AD3 LPC_AD0

MCP_GPIO76

8

PEG_CLKREQ#

7

CLK_PCIE_REQ#

6

8 7 6

SRN0J-7-GP-U

LPC_FRAME#[24,65]

SPI_CLK_R[24,25] SPI_CS0#_R[24,25]

SPI_SI_R[24,25 ]

SPI_SO_R[24,25]

SPI_WP#[25] SPI_HOLD#[25]

Based on the swap report.

RN1806

LPC_LAD2_PCH

1

LPC_LAD1_PCH

2

LPC_LAD3_PCH

3

LPC_LAD0_PCH

45

1

23

RN1802

RN1802 SRN1KJ-7-GP

SRN1KJ-7-GP

4

PCH_SPI_DQ3 PCH_SPI_DQ2

MCP_GPIO76 [20]

CLK_PCIE_REQ#

CLK_PCIE_WLAN_REQ3#

CLK_PCIE_LAN_REQ4#

PEG_CLKREQ#

CLK_PCIE_REQ#

LPC_LAD0_PCH LPC_LAD1_PCH LPC_LAD2_PCH LPC_LAD3_PCH

1 2

1 2 1 2

1 2 1 2 1 2 1 2

LPC_LFRAME#_PCH

PCH_SPI_CLK

R180633R2J-2-GP R180633R2J-2-GP

PCH_SPI_CS0#

R18070R0402-PAD R18070R0402-PAD

PCH_SPI_SI

R18080R0402-PAD R18080R0402-PAD

PCH_SPI_SO

R18090R0402-PAD R18090R0402-PAD

PCH_SPI_DQ2

R18110R0402-PAD R18110R0402-PAD

PCH_SPI_DQ3

R18120R0402-PAD R18120R0402-PAD

R1801 0R0402-PADR1801 0R0402-PAD

CPU1F

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0#/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1#/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2#/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3#/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4#/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5#/GPIO23

HASWELL-6-GP-U

CPU1G

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME#

AA3

SPI_CLK

Y7

SPI_CS0#

Y4

SPI_CS1#

AC2

SPI_CS2#

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

HASWELL-6-GP-U

HSW_ULT_DDR3L

WLAN

LAN

GPU

HSW_ULT_DDR3L

LPC

CLOCK

SIGNALS

SMBUS

C-LINKSPI

DIFFCLK_BIASREF

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SML1ALERT#/PCHHOT#/GPIO73

SML1DATA/GPIO74

6 OF 19

XTAL24_IN

XTAL24_OUT

RSVD#K21 RSVD#M21

TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8

CLKOUT_LPC_0 CLKOUT_LPC_1

7 OF 19

SMBCLK

SMBDATA SML0CLK

SML0DATA

SML1CLK/GPIO75

CL_CLK

CL_DATA

CL_RST#

A25 B25

K21 M21 C26

C35 C34 AK8 AL8

AN15 AP15

B35 A35

AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3

AF2 AD2 AF4

XTAL24_IN XTAL24_OUT

XCLK_BIASREF MCP_TESTLOW1

MCP_TESTLOW2 MCP_TESTLOW3 MCP_TESTLOW4

CLK_PCI_LPC_R CLK_PCI_KBC_R

MCP_GPIO11 SMB_CLK SMB_DATA CARD_PWR_EN SML0_CLK SML0_DATA MCP_GPIO73 SML1_CLK SML1_DATA

TP_CL_CLK TP_CL_DATA TP_CL_RST#

R1803 3KR2F-GPR1803 3KR2F-GP

1 2

RN1803

4

SRN10KJ-5-GP

DEBUG

R1804 0R2J-2-GP

1 2

R1805 33R2J-2-GPR1805 33R2J-2-GP

1 2

MCP_GPIO73 [16] SML1_CLK [24,26,76] SML1_DATA [24,26,76]

TP1801TP1801

1

TP1802TP1802

1

TP1803TP1803

1

SMB_DATA

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

SMB_CLK

+V1.05S_AXCK_LCPLL

1

RN1804

23

4

DY

12

23 1

SRN10KJ-5-GP

EC1801

SC10P50V2JN-4GPDYEC1801

SC10P50V2JN-4GP

12

DY

3D3V_S03D3V_S5

2N7002KDW-GP

6 5

Q1801

XTAL24_OUT

CLK_PCI_LPC [65] CLK_PCI_KBC [24]

PCIE_CLK_XDP_N [96] PCIE_CLK_XDP_P [96]

EC1802

SC10P50V2JN-4GPDYEC1802

SC10P50V2JN-4GP

1 2 34

USB_OC#0_1[16,35]

1 2 3 4 5

SRN10KJ-6-GP

CLK_PCIE_WLAN_N3[58 ] CLK_PCIE_WLAN_P3[58]

CLK_PCIE_WLAN_REQ3#[15,58]

CLK_PCIE_LAN_N4[30] CLK_PCIE_LAN_P4[30]

CLK_PCIE_LAN_REQ4#[20,30]

CLK_PCIE_VGA#[73] CLK_PCIE_VGA[73]

C C

LPC_AD[3..0][24,65]

B B

PEG_CLKREQ#[73]

LPC_AD[3..0]

R1810

1 2

0R0402-PAD

R1802

R1802 1MR2J-1-GP

1MR2J-1-GP

CLK_PCI_LPC_R

RN1810

4

SRN10KJ-5-GP

23

4 1

R1813 0R2J-2-GP

SML1_CLK SML1_DATA SML0_DATA SML0_CLK

CARD_PWR_EN

MCP_GPIO11

SMB_CLK SMB_DATA

23 1

PCH_SMBDATA [12,55,62,96]

PCH_SMBCLK [12,55,62,96]

12

EC_SCI#[20,24]

C1801

SC15P50V2JN-2-GP

X1801

X1801 XTAL-24MHZ-81-GP

XTAL-24MHZ-81-GP

82.30004.841

C1802

SC15P50V2JN-2-GP

1 2

CRT_DEBUG

RN1807

8 7 6

SRN2K2J-4-GP

RN1809

SRN10KJ-6-GP

8 7 6

SRN2K2J-1-GP

4

RN1811

3D3V_S0

12

CLK_DP2VGA [55]

3D3V_S5_PCH

1 2 3 45

23 1

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (CLOCK/SMBUS/CL/LPC/SPI)

Size Document Number Rev

Custom

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

18 104Friday, February 07, 2014

1

X02

5

4

3

2

1

SSID = CPU

RTC_X1

1 2

R1915 10MR2J-L-GPR1915 10MR2J-L-GP

X1901

1

4

2 3

XTAL-32D768KHZ-65-GP

82.30001.841

HSW_ULT_DDR3L

RTC

AUDIO SATA

Unused SATA[3:0]GP pins must be terminated to either

3.3V rail or GND using 8.2K motherboard. Either pull-up or pull-down is acceptable.

HDA_SDIN0[27]

R1903

TP1902TP1902

TP1901TP1901

RTC_AUX_S5

12

HDA_BITCLK HDA_SYNC HDA_RST# HDA_SDIN0

HDA_SDOUT TP_HDA_DOCK_EN#

1

PCH_JTAG_TRST#

1

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

XDP_TCK_JTAGX

R1901

R1901 1MR2J-1-GP

1MR2J-1-GP

RTC_X1 RTC_X2

SM_INTRUDER#

PCH_INTVRMEN SRTC_RST# RTC_RST#

C1903

SC15P50V2JN-2-GP

CPU1E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER#

AV7

INTVRMEN

AV6

SRTCRST#

AU7

RTCRST#

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST#/I2S_MCLK#

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN#/I2S1_TXD#

AV10

HDA_DOCK_RST#/I2S1_SFRM#

AY8

I2S1_SCLK

AU62

PCH_TRST#

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD#AL11

AC4

RSVD#AC4

AE63

JTAGX

AV2

RSVD#AV2

HASWELL-6-GP-U

1 2

JTAG

D D

PCH strap pin:

R1913

Integrated SUS 1V VRM Enable

INTVRMEN

C C

Low = External VRs High = Internal VRs

RTCRST_ON[24]

*

R1902

10KR2J-3-GP

R1913

1 2

DY

330KR2J-L1-GP

12

PCH_INTVRMEN

Q1901

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

D

(#514849)

C1901

SC1U10V2KX-1GP

RTC_AUX_S5

21

12

G1901

GAP-OPEN

1

23

RN1901

RN1901 SRN20KJ-1-GP

SRN20KJ-1-GP

4

12

C1902

C1902 SC1U10V2KX-1GP

SC1U10V2KX-1GP

330KR2J-L1-GP

Layout: Place at the open door area.

R1907 33R2J-2-GPR1907 33R2J-2-GP

HDA_CODEC_BITCLK[27] HDA_CODEC_SYNC[27]

PCH strap pin:

Flash Descriptor Security Overide/ Intel ME Debug Mode

HDA_SDOUT

The internal pull-down is disabled after PLTRST# deasserts

B B

Low = Default High = Enable

EC1901

SC10P50V2JN-4GP

HDA_CODEC_BITCLK SATA_LED#

1 2

DY

*

HDA_CODEC_RST#[27,29]

HDA_CODEC_SDOUT[27]

ME_UNLOCK[24]

1D05S_VCCST

1 2

R1908 0R0402-PADR1908 0R0402-PAD

1 2

R1911 0R0402-PADR1911 0R0402-PAD

1 2

R1912 33R2J-2-GPR1912 33R2J-2-GP

1 2

R1909 1KR2J-1-GPR1909 1KR2J-1-GP

1 2

DY

DY DY

DY

1 2

DY

12 12 12 12

R1916 51R2J-2-GP

R1916 51R2J-2-GP R1917 51R2J-2-GP

R1917 51R2J-2-GP R1918 51R2J-2-GP

R1918 51R2J-2-GP R1919 1KR2J-1-GP

R1919 1KR2J-1-GP

R1920 51R2J-2-GP

HDA_BITCLK HDA_SYNC HDA_RST#

HDA_SDOUT

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS XDP_TCK_JTAGX

PCH_JTAG_TCK

RTC_X2

C1904

C1904 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

1 2

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3

SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2

SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0

SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0

SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_IREF

RSVD#L11 RSVD#K10

SATA_RCOMP

SATALED#



to 10K on the

5 OF 19

J5 H5 B15 A15

J8 H8 A17 B17

J6 H6 B14 C15

F5 E5 C17 D17

V1 U1 V6 AC1

A12 L11 K10 C12 U3

EC_SMI# MCP_GPIO36

SATA_IREF

SATA_RCOMP SATA_LED#

SATA_ODD_PRSNT# EC_SMI#

MCP_GPIO36

SATA3_PRX_HDDTX_N0 [56] SATA3_PRX_HDDTX_P0 [56] SATA3_PTX_HDDRX_N0 [56] SATA3_PTX_HDDRX_P0 [56]

SATA_PRX_ODDTX_N2 [56] SATA_PRX_ODDTX_P2 [56] SATA_PTX_ODDRX_N2 [56] SATA_PTX_ODDRX_P2 [56]

EC_SMI# [24]

SATA_ODD_PRSNT# [56] CEDAR/JANUS_ID [15]

Layout Note:

4mil trace at break-out and 3 12-15mil trace with <0.2 ohms and length total <= 500mils.

RN1902

1

8

2

7

3

6

4 5

SRN10KJ-6-GP

R1905

DY

10KR2J-3-GP

3D3V_S0

12

HDD1

ODD

+V1.05S_ASATA3PLL

R1904

1 2

0R0402-PAD

1 2

R1906

R1906 3KR2F-GP

3KR2F-GP

3D3V_S0

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (RTC/SATA/HDA/JTAG)

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

19 104Friday, February 07, 2014

1

of

A00

SSID = CPU

5

3D3V_S5

RN2006

BATLOW#

1

4

MCP_GPIO27

2 3

SRN10KJ-5-GP

3D3V_S5_PCH

R2015

10KR2J-3-GP

1 2

R2010

10KR2J-3-GP

1 2

3D3V_S5_PCH

R2013

R2013 10KR2J-3-GP

10KR2J-3-GP

1 2

MCP_R

3D3V_S5_PCH

3D3V_S0

R2010

HSW

D D

C C

INT_T P#_G PIO8

INT_T P#_G PIO46 MCP_GPIO56

1 2 1 2 1 2 1 2

1 2 1 2

RN2012

RN2012 SRN10KJ-6-GP

SRN10KJ-6-GP

1

8

2

7

3

6

4 5

RN2011

RN2011 SRN10KJ-6-GP

SRN10KJ-6-GP

1

8

2

7

3

6

4 5

BIOS strap pin:

BIOS VRAM Size Stra p pin

1G

2G

B B

BIOS strap pin:

BIOS UMA/DIS Str ap pi n

UMA

DIS

BIOS strap pin:

BIOS UMA/DIS Str ap pi n

N15V-GM-S(DVC40/50)

A A

N15S-GT (DVC70)

GPU_EVENT#[76]

GC6_FB_EN[24,75,76,83]

R20010R 0402-PAD-1-GP R20010R0402-PAD-1-GP R20020R 0402-PAD-1-GP R20020R0402-PAD-1-GP R20040R 0402-PAD-1-GP R20040R0402-PAD-1-GP R20090R 0402-PAD-1-GP R20090R0402-PAD-1-GP

R20160R 0402-PAD-1-GP R20160R0402-PAD-1-GP R20170R 0402-PAD-1-GP R20170R0402-PAD-1-GP

R20200R 0402-PAD-1-GP R20200R0402-PAD-1-GP R20220R 0402-PAD-1-GP R20220R0402-PAD-1-GP

EC_SWI# RTC_DET#

WLAN_PLT_RST#

PIRQA# DBC_EN

BLUETOOTH_EN

BOARD_ID2

BOARD_ID3

BATLOW# [17]

MCP_GPIO58 MCP_GPIO44

MCP_GPIO56 MCP_GPIO26

MCP_GPIO14

MCP_GPIO28 MCP_GPIO13 MCP_GPIO57

BOARD_ID1

0

1

0

1

0

1

5

MCP_GPIO76[18] MCP_GPIO12[17]

SATA_ODD_DA#[56] RTC_DET#[25]

R2029

1 2

0R0402-PAD

HSIOPC[21]

R2028 0R0402-PADR2028 0R0402-PAD

1 2

INT_T P#[15,24,62] EC_SWI#[24]

EC_SCI#[18,24]

HDA_SPKR[27]

USB_OC#4_5 [16]

CLK_PCIE_LAN_REQ4# [18,30] PIRQA# [15]

VRAM_2G

BOARD_ID1

VRAM_1G

BOARD_ID2

BOARD_ID3

N15V-GM

INT_T P#[15,24,62]

OPS

UMA

N15S-GT

3D3V_S0

1 2

0R2J-2-GP

TP2002TP2002

1 2

0R2J-2-GP

TP2001TP2001

12

R2023

R2023 10KR2J-3-GP

10KR2J-3-GP

12

R2024

R2024 10KR2J-3-GP

10KR2J-3-GP

12

R2005

R2005 10KR2J-3-GP

10KR2J-3-GP

12

R2008

R2008 10KR2J-3-GP

10KR2J-3-GP

12

R2025

R2025 10KR2J-3-GP

10KR2J-3-GP

12

R2026

R2026 10KR2J-3-GP

10KR2J-3-GP

R2031

DY

R2030

BDW

MCP_GPIO76 INT_T P#_G PIO8 MCP_GPIO12 MCP_GPIO15

RTC_DET# MCP_GPIO27 MCP_GPIO28 MCP_GPIO26

MCP_GPIO57 MCP_GPIO58 WLAN_PLT_RST# MCP_GPIO44 GPU_EVENT_MCP# BOARD_ID1 BOARD_ID2 BOARD_ID3 HSIOPC MCP_GPIO13 MCP_GPIO14

CAMERA_PWR_EN

1

GC6_FB_EN_MCP INT_T P#_G PIO46

EC_SWI# EC_SCI# HDD_DEVSLP

1

HDA_SPKR

4

HSW_ULT _DDR3 L

CPU1J

P1

BMBUSY#/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

HASWELL-6-GP-U

HSW_ULT _DDR3 L

GPIO

CPU/

CPU/ MISC

MISC

SERIAL IO

10 OF 19

THRMTRIP#

RCIN#/GPIO82

SERIRQ

PCH_OPI_RCOMP

RSVD#AF20 RSVD#AB21

GSPI0_CS#/GPIO83

GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86

GSPI1_CS#/GPIO87

GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90 UART0_RXD/GPIO91 UART0_TXD/GPIO92

UART0_RTS#/GPIO93 UART0_CTS#/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1 UART1_RST#/GPIO2 UART1_CTS#/GPIO3

I2C0_SDA/GPIO4

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69

PCH_THERMTRIP

D60

H_RCIN#

V4

INT_S ERIR Q

T4

PCH_OPIRCOMP

AW15 AF20 AB21

R6 L6 N6

LPSS_GSPI0_MOSI_BBS0_R

L8 R7 L5 N7 K2 J1 K3 J2 G1 K4 G2 J3 J4

I2C0_S DA

F2

I2C0_S CL

F3

I2C1_S DA

G4

I2C1_S CL

F1 E3

COLOR_ENGINE

F4

LPSS_SDIO_D0_CMNHD R

D3 E4 C3 E2

PCH strap pin:

NO REBOOT

HDA_SPKR

The internal pull-down is disabled after PLTRST# deasserts

High = Disable

Low = Enable (Default)

*

PCH strap pin:

Top-Block Swap Override mode

High = Enable "Top-Block swap" mode

SDIO_D0

Low = Disable "Top-Block swap" mode (Default)

/ GPIO66

*

The internal pull-down is disabled after PLTRST# deasserts

Need SW double confirm if that's needed Top-Block swap

PCH strap pin:

TLS Confidentiality

Low = Disable Intel ME Crypto TLS (Default)

*

GPIO15

The internal pull-down is disabled after RSMRST# deasserts.

High = Enable Intel ME Crypto TLS

PCH strap pin:

Boot BIOS Strap Bit BBS

Boot BIOS Destination

The internal pull-down is disabled after PLTRST# deasserts

Need double confirm, GPIO table set to GPI if that's needed PH or PL

Low = SPI (Default)

*

High = LPC

4

3D3V_S0

1KR2J-1-GP

1KR2J-1-GP R2006

R2006

1 2

3D3V_S0

12

DY

3D3V_S5_PCH

12

DY

3D3V_S0

12

R2012

DY

1KR2J-1-GP

LPSS_GSPI0_MOSI_BBS0_R

HDA_SPKR

DY

R2011

R2011 1KR2J-1-GP

1KR2J-1-GP

LPSS_SDIO_D0_CMNHD R

R2014

R2014 1KR2J-1-GP

1KR2J-1-GP

KB_DET# [62] KB_LED_BL_DET [62] DBC_EN [52] PANEL_SIZE_ID [52]

BLUETOOTH_EN [58]

MCP_GPIO15

3

1D05S_VCCST

12

R2018

R2018 1KR2J-1-GP

1KR2J-1-GP

1 2

R2003

R2003 49D9R2F-GP

49D9R2F-GP

I2C1_S DA [62 ]

I2C1_S CL [6 2]

3

R2027

1 2

DY

SATA_ODD_PWRGT [56]

SATA_ODD_DA#[56]

TP2003TP2003

1

0R2J-2-GP

H_THERMTRIP# [36] H_RCIN# [24]

INT_S ERIR Q [24]

Layout Note:

1.Referenced "continuous" VSS plane only.

2.Avoid routing next to clock pins or noisy signals.

3. Trace width: 12~15mil

4. Isolation Spacing: 12mil

5. Max length: 500mil

3D3V_S0

RN2002

SRN10KJ-6-GP

H_RCIN# INT_S ERIR Q

KB_DET#

I2C0_S DA I2C0_S CL

HSIOPC

I2C1_S DA I2C1_S CL

R2007

8 7 6

SRN10KJ-5-GP

SRN10KJ-5-GP RN2007

RN2007

1 2 3

1 2

RN2008

1

DY

2 3

SRN10KJ-5-GP

1 2 3 45

3D3V_S0

4

100KR2J-1-GP

4

3D3V_S0

2

Title

Size Document Number Rev

A2

Date: Sheet of

Date: Sheet

2

Date: Sheet

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u R d., Hsichih,

21F, 88, Sec.1, Hsin Tai W u R d., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (GPIO/MISC)

Janus HSW 40/50/70

1

A00

20 104Friday, February 07, 2014

A00

of

SSID = CPU

WWW.AliSaler.Com

5

4

3

2

1

DSW

3D3V_S5_PCH

+3.3A_DSW_PRTCSUS

C2105

SC1U10V2KX-1GPDYC2105

SC1U10V2KX-1GP

12

SC1U10V2KX-1GP

12

+V1.05DX_MODPHY_PCH

+V1.05S_AIDLE

+V1.05S_AUSB3PLL

+V1.05S_ASATA3PLL

TP2102TP2102

TP2107TP2107

TP2108TP2108

TP2103TP2103 TP2104TP2104 TP2101TP2101

TP_VCCAPLLOPI_VAL

1

+V1.05S_APLLOPI

+V1.05A_VCCUSB3SUS

1

+V3.3A_1.5A_HDA

+V1.05A_USB2SUS

1

+V3.3A_PSUS

+V3.3A_DSW_P

12

C2123

SC10U6D3V3MX-GP

+V1.05S_AXCK_DCB

+V1.05S_AXCK_LCPLL

+V1.05S_SSCF100

+V1.05S_SSCFF

TP_V1.05S_SSCF100

1

TP_V1.05S_AXCK_DCB

1

TP_V1.05S_SSCFF

1

+V3.3A_PSUS

+V3.3S_PCORE

B18 B11

Y20

AA21

W21

AH14

AH13

AC9 AA9

AH10

J18 K19 A20

J17 R21

T21 K18 M20 V21

AE20 AE21

K9

L10

M9 N8 P9

J13

V8

W9

CPU1M

VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL

RSVD#Y20 VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3

VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD#K18 RSVD#M20 RSVD#V21 VCCSUS3_3 VCCSUS3_3

HSIO

OPI

USB3

HDA

VRM

GPIO/LPC

LPT LP POWER

HSW_ULT_DDR3L

RTC

SPI

CORE

THERMAL SENSOR

SERIAL IO

SUS OSCILLATOR

USB2

13 OF 19

VCCSUS3_3

VCCRTC DCPRTC

VCCSPI

VCCASW VCCASW

VCC1_05 VCC1_05 VCC1_05 VCC1_05

VCC1_05 DCPSUSBYP#AG19 DCPSUSBYP#AG20

VCCASW

DCPSUS1#AD10

DCPSUS1#AD8

VCCTS1_5

VCC3_3 VCC3_3

VCCSDIO VCCSDIO

DCPSUS4

RSVD#AC20

VCC1_05

AH11 AG10 AE7

Y8

AG14 AG13

J11 H11 H15 AE8 AF22 AG19 AG20 AE9 AF9 AG8 AD10 AD8

J15 K14 K16

U8 T9

AB8

AC20 AG16 AG17

D D

1D05V_S0

R2105

1 2

0R0402-PAD

DY

+V3.3A_1.5A_HDA3D3V_S5_PCH

R2108

1 2

0R0603-PAD-1-GP-U

3D3V_S5 3D3V_S0

C C

1D05V_S0

R2101

1 2

0R0402-PAD

R2117

1 2

0R0402-PAD

DY

12

+V3.3A_DSW_P

C2136

C2136 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

+V1.05S_SSCF100

C2137

SC1U10V2KX-1GP

C2116

R2112

1 2

0R0402-PAD

C2109

+VCCRTCEXT

1D05V_S0

+V1.05S_CORE_PCH

+1.05M_ASW

+V1.05A_SUS_PCH

1D5V_S0

+V3.3S_1.8S_LPSS_SDIO

+V1.05A_AOSCSUS

TP_V1.05S_APLLOPI

SCD1U16V2KX-3GP

R2102

1 2

12

0R0603-PAD-1-GP-U

SC1U10V2KX-1GP

RTC_AUX_S5

1 2

C2110

Broadwell(#514849): No series resistors (0 ohm). Haswell(#486713):Series resistor:5 ohm.

R2110

R2110 5D1R2F-GP

5D1R2F-GP

1 2

BDW/HSW

1

3D3V_S0

PCH_VCCDSW_R+PCH_VCCDSW

TP2106TP2106

WistronSKB: match Intel design_20130417 (#489999_2013WW15)

12

TP2109TP2109

1

TP2105TP2105

1

C2135

SC1U10V2KX-1GP

C2135

SC1U10V2KX-1GP

12

Intel Recommend

3D3V_S5

12

C2147

SCD1U16V2KX-3GP

C2114

SC1U10V2KX-1GP

1 2

C2101

C2128

SC1U10V2KX-1GP

C2128

SC1U10V2KX-1GP

C2101

1 2

SCD47U6D3V2KX-GP

1D05V_S0

+V3.3A_DSW_P +PCH_VCCDSW

HASWELL-6-GP-U

1D05V_S0

B B

A A

R2118

1 2

0R0402-PAD

12

5

+V1.05S_SSCFF

C2138

SC1U10V2KX-1GP

+V1.05S_SSCFF

R2123

HSIOPC[20]

4

1 2

DY

0R2J-2-GP

5V_S5

1D05V_S0

DY

HSIOPC_R

12

C2141

C2141 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

HASWELL-6-GP-U

1 2

Non-HSIO

9

U2101

ON

1

VDD

2

D#2

3

D#3 D#44S#5

DY

SLG59M1470VTR-GP

74.59147.093

3

R2122

0R5J-5-GP

GND

S#7 S#6

1D05V_HSIO1D05V_S0

+V3.3S_1.8S_LPSS_SDIO

1 2

0R0402-PAD

1D05V_HSIO

R2114

8 7 6 5

HSIO_OUT

R2114 0R5J-5-GP

0R5J-5-GP

1 2

DY

12

C2142

C2142 SC10U10V5KX-2GP

SC10U10V5KX-2GP

2

Title

Size Document Number Rev

A3

Date: Sheet

12

CPU (POWER2)

Janus HSW 40/50/70

0R0402-PAD

C2104

C2104 SC1U10V2KX-1GP

SC1U10V2KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

R2103

1

3D3V_S0

A00

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SSID = PCH

D D

HSW_ULT_DDR3L

CPU1Q

HSW_ULT_DDR3L

17 OF 19

DC_TEST_AY2_AW2

TP2201TP2201

TP2204TP2204

C C

B B

TP_DC_TEST_AY60

1

DC_TEST_AY61_AW61 DC_TEST_AY62_AW62

1

DC_TEST_A3_B3 DC_TEST_A61_B61 DC_TEST_B62_B63

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

HASWELL-6-GP-U

CPU1R

AT2

RSVD#AT2

AU44

RSVD#AU44

AV44

RSVD#AV44

D15

RSVD#D15

F22

RSVD#F22

H22

RSVD#H22

J21

RSVD#J21

HASWELL-6-GP-U

HSW_ULT_DDR3L

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63

18 OF 19

RSVD#N23 RSVD#R23

RSVD#T23

RSVD#U10

RSVD#AL1

RSVD#AM11

RSVD#AP7 RSVD#AU10 RSVD#AU15

RSVD#AW14

RSVD#AY14

DC_TEST_A3_B3

A3

TP_DC_TEST_A4DC_TEST_AY3_AW3

A4

TP_DC_TEST_A60

A60

DC_TEST_A61_B61

A61

TP_DC_TEST_A62TP_DC_TEST_B2

A62

TP_DC_TEST_AV1

AV1

TP_DC_TEST_AW1

AW1

DC_TEST_AY2_AW2

AW2

DC_TEST_AY3_AW3

AW3

DC_TEST_AY61_AW61DC_TEST_C1_C2

AW61

DC_TEST_AY62_AW62

AW62

TP_DC_TEST_AW63

AW63

N23 R23 T23 U10

AL1 AM11 AP7 AU10 AU15 AW14 AY14

TP2202TP2202

1

TP2203TP2203

1

TP2205TP2205

1

TP2206TP2206

1

TP2207TP2207

1

TP2208TP2208

1

Wistron Corporation

A A

Title

CPU (RSVD)

5

Size Document Number Rev

A4

Date: Sheet

4

3

Date: Sheet

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

22 104Friday, February 07, 2014

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SSID = PCH

D D

HSW_ULT_DDR3L

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

HSW_ULT_DDR3L

CPU1N

A11 A14 A18 A24 A28 A32 A36 A40 A44 A48 A52 A56

AA1 AA58 AB10 AB20 AB22

AB7 AC61 AD21

AD3 AD63

C C

B B

AE10

AE5 AE58 AF11 AF12 AF14 AF15 AF17 AF18

AG1

AG11 AG21 AG23 AG60 AG61 AG62 AG63

AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57

AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

HASWELL-6-GP-U

14 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20

AP22 AP23 AP26 AP29

AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49

AR5 AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63

AU1 AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

HSW_ULT_DDR3L

CPU1O

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

HASWELL-6-GP-U

15 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU(VSS)

Janus HSW 40/50/70

23 104Friday, February 07, 2014

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3

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SSID = KBC

D D

C C

B B

1D05V_S0

R2401

1 2

0R0402-PAD

Layout Note:

Need very close to EC

3D3V_S0

C2412SCD1U16V2KX-3 GP C2412SCD1U16V2KX-3GP

12

C2413

DY

SC2D2U10V3KX-1GP

ALL_SYS_PWRGD assert, delay 10ms; PCH_PWROK assert.

GC6_FB_EN[20,75,76,83]

R2417

1 2

LCD_TST[52]

0R0402-PAD

LCD_TST_EN[52]

TP_LID_CLOSE#[62]

DGPU_PWROK[15,82,83]

ALL_SYS_PWRGD de-assert, delay 100ms; SYS_PWROK assert.

LVDS backlight Control from PS8625

TOUCH_PANEL_INTR#[52]

INT_TP#[15,20,62]

3D3V_AUX_KBC

R2453

12

DY

10KR2J-3-GP

L_BKLT_EN[15]

eDP backlight Control from PCH

R2437

1 2

OPS

0R2J-2-GP

EC_AGND

R2451

1 2

0R2J-2-GP

DY

R2450

1 2

0R2J-2-GP

DY

R2411

1 2

DY

R2448 0R2J-2-GPR2448 0R2J-2-GP

1 2

R2444

1 2

0R0402-PAD

EC_VTT

12

C2401

C2414

1 2

OVER_CURRENT_P8#[76]

0R2J-2-GP

SCD1U16V2KX-3GP

AD_IA[44]

SCD1U16V2KX-3GP

PCH_PWROK[17,26,36] PM_SLP_SUS#[17,38] BOOST_MON[44]

FAN1_DAC_1[26]

AD_IA_HW[44]

IMVP_PWRGD[7,46]

BAT_SCL[43,44] BAT_SDA[43,44]

SML1_CLK[18,26,76]

SML1_DATA[18,26,76]

PM_LAN_ENABLE[30]

RTCRST_ON[19]

ALL_SYS_PWRGD[36]

PWR_CHG_AD_OFF[42]

AD_IA_HW2[44]

BLON_OUT[52]

FAN_TACH1[26]

PM_PWRBTN#[17,96]

PM_SLP_S3#[17,36,48,49,51]

EC_BRIGHTNESS[52]

KBC_BEEP[27]

BATT_WHITE_LED#[61]

AC_IN_KBC#[42]

KB_BL_CTRL[62]

CHG_AMBER_LED#[61]

KBC_DPWROK[17]

VD_IN1[26]

VD_OUT1#[26]

AC_PRESENT[17,76]

SYS_PWROK[17,96]

USB_PWR_EN#[35]

WIFI_RF_EN[58] PM_SUSWARN#[17]

TOUCH_PANEL_INTR_KBC#

E51_TxD[58]

PM_CLKRUN#_EC[17]

AMP_MUTE#[27]

12

R2447

R2447 100KR2J-1-GP

100KR2J-1-GP

VBAT

C2404

SCD1U16V2KX-3GP

PSID_EC[42]

TPCLK[62]

TPDATA[62]

1 2

1KR2J-1-GP

L_BKLT_EN_EC

3D3V_AUX_KBC_VCC

12

C2405

DY

SC2D2U10V3KX-1GP

EC_AGND

19 46 76 88

115 102

4

EC_VTT

12

97

PCB_VER_AD

98

99 100 108

96

95

MODEL_ID_DET

94

101 105

GC6_FB_EN_KBC

106 107

BAT_SCL

70

BAT_SDA

69

67

68 119 120

PROCHOT_EC

24

LCD_TST_EN

28

TP_LID_CLOSE#_KBC

26

ECSWI#_KBC

123

72

71

10

11

25

27

31 117

DGPU_PWROK_KBC

R2449

INT_T P#_KBC L_BKLT_EN_EC

VD1_EN#

63

64

32 118

62

65

22

16

81

66 104 110

112

84

83

82

79

124 121 111

9 8

30

EC_GPIO47 High Active

PROCHOT_EC

12

R2442

100KR2J-1-GP

DY

12

DY

C2407SCD1U16V2KX-3 GPDYC2407SCD1U16V2KX-3 GP

C2406SCD1U16V2KX-3 GP C2406SCD1U16V2KX-3GP

KBC24

VCC VCC VCC VCC VCC

AVCC VDD VTT

KBSOUT0/GPOB0/SOUT_CR/JENK#

GPIO90/AD0 GPIO91/AD1 GPIO92/AD2 GPIO93/AD3 GPIO05/AD4 GPIO04/AD5 GPIO03/EXT_PURST#/AD6 GPIO07/AD7/VD_IN2

GPIO94/DA0 GPIO95/DA1 GPIO96/DA2 GPIO97/DA3

GPIO17/SCL1/N2TCK GPIO22/SDA1/N2TMS GPIO73/SCL2/N2TCK GPIO74/SDA2/N2TMS GPIO23/SCL3/N2TCK GPIO31/SDA3/N2TMS GPIO47/SCL4A/N2TCK GPIO53/SDA4A/N2TMS GPIO51/TA3/N2TCK GPIO67/SOUT1/N2TMS

GPIO37/PSCLK1 GPIO35/PSDAT1 GPIO26/PSCLK2 GPIO27/PSDAT2 GPIO50/PSCLK3 GPIO52/PSDAT3

GPIO56/TA1 GPIO20/TA2/IOX_DIN_DIO GPIO14/TB1 GPIO01/TB2

GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PWM GPIO32/D_PWM GPIO45/E_PWM/DTR1#_BOUT1 GPIO40/F_PWM/1_WIRE/RI1# GPIO66/G_PWM/PSL_GPIO66 GPO33/H_PWM/VD1_EN#

GPIO80/VD_IN1 GPIO82/IOX_LDSH/VD_OUT1

GPIO84/IOX_SCLK/VD_OUT2

GPIO77/SPI_MISO GPIO76/SPI_MOSI GPIO75/SPI_SCK GPIO02/SPI_CS#

GPIO10/LPCPD# GPIO85/GA20 GPIO83/SOUT_CR GPIO65/SMI#

GPIO11/CLKRUN# GPIO55/CLKOUT/IOX_DIN_DIO

NPCE285PA0DX-GP

071.00285.000G

R2438

R2438 0R2J-2-GP

0R2J-2-GP

1 2

DY

Q2401

G

D

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

KBSOUT10/P80_CLK/GPIOC2 KBSOUT11/P80_DAT/GPIOC3

KBSOUT14/GP(I)O62/XORTR#

KBSOUT15/GPIO61/XOR_OUT

PSL_IN2#/GPI06/EXT_PURST#

3D3V_AUX_KBC

R2402

1 2

0R0603-PAD-1-GP-U

R2403

2D2R3-1-U-GP

1 2

PCB_VER_AD

12

DY

C2408SCD1U16V2KX-3 GP C2408SCD1U16V2KX-3GP

C2410SCD1U16V2KX-3 GP C2410SCD1U16V2KX-3GP

C2409SCD1U16V2KX-3 GPDYC2409SCD1U16V2KX-3 GP

C2411SC2D2U10V3KX-1GP C2411SC2D2U10V3KX-1GP

KROW0

54

KBSIN0/GPIOA0/N2TCK KBSIN1/GPIOA1/N2TMS

KBSIN2/GPIOA2 KBSIN3/GPIOA3 KBSIN4/GPIOA4 KBSIN5/GPIOA5 KBSIN6/GPIOA6 KBSIN7/GPIOA7

KBSOUT1/GPIOB1/TCK KBSOUT2/GPIOB2/TMS

KBSOUT3/GPIOB3/TDI

KBSOUT4/GPOB4

KBSOUT5/GPIOB5/TDO

KBSOUT6/GPIOB6/RDY#

KBSOUT7/GPIOB7 KBSOUT8/GPIOC0

KBSOUT9/GPOC1/SDP_VIS#

KBSOUT12/GPO64/TEST#

KBSOUT13/GP(I)O63/TRIST#

GPIO60/KBSOUT16/DSR1# GPIO57/KBSOUT17/DCD1#

LFRAME#/GPIOF6 LRESET#/GPIOF7

GPIOC6/F_CS0#

GPIOC7/F_SCK

GPIO30/F_WP#/RTS1#

GPIO41/F_WP#/PSL_GPIO41

GPIOC5/F_SDIO/F_SDIO0

GPIOC4/F_SDI/F_SDIO1 GPIO81/F_WP#/F_SDIO2

GPIO00/32KCLKIN/F_SDIO3

PSL_IN1#/GPI70

PSL_OUT#/GPIO71

ECSCI#/GPIO54

KBRST#/GPIO86

SERIRQ/GPIOF0

GPIO36/TB3/CTS1#

GPIO44/SCL4B PSL_IN4#/GPI43 PSL_IN3#/GPI42

GPIO46/SDA4B/CIRRXM

GPIO87/CIRRXM/SIN_CR

GPIO34/SIN1/CIRRXL

Layout Note:

Connect GND and AGND planes via either 0R resistor or connect directly.

H_PROCHOT#_EC

LAD0/GPIOF1 LAD1/GPIOF2 LAD2/GPIOF3 LAD3/GPIOF4 LCLK/GPIOF5

EXT_RST#

VBKUP

VCORF

GPIO24

1 2

VSBY

PECI

GND GND GND GND GND GND

AGND

R2440

R2440 0R0402-PAD

0R0402-PAD

55 56 57 58 59 60 61

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33

126 127 128 1 2 3 7

90 92 109 80 87 86 91 77

73 93 74

29 85 122

75 114 44 13 125 6 15

21 20 17 23

113 14

5 18 45 78 89 116

103

DY

EC_AGND

12

C2421

C2421 SC47P50V2JN-3GP

SC47P50V2JN-3GP

KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

PLT_RST#_EC

EC_SPI_CS#_C EC_SPI_CLK_C

BAT_IN# EC_SPI_DI_C EC_SPI_DO_C

SUSCLK_KBC

PSL_IN1# PSL_IN2# PSL_OUT#

ECSCI#_KBC ECRST#

EC_VBKUP KBC_VCORF PECI

ECSMI#_KBC

EC_AGND

C2402

12

A00

DY

1 2

SCD1U16V2KX-3GP

0R0402-PAD

0R0402-PAD R2435

R2435

VBAT

12

R2404

64K9R2F-1-GP

12

R2406

R2406 100KR2F-L1-GP

100KR2F-L1-GP

EC_AGND

KROW[0..7] [62]

KCOL[0..16] [62]

3D3V_AUX_KBC

1 2

LPC_AD[3..0] [18,65]

CLK_PCI_KBC [18] LPC_FRAME# [18,65]

33R2J-2-GPR2419 33R2J-2-GPR2419

12

33R2J-2-GPR2420 33R2J-2-GPR2420

12

R2422 33R2J-2-GPR2422 33R2J-2-GP

12

R2423 33R2J-2-GPR2423 33R2J-2-GP

12

R2441

1 2

0R0402-PAD

Layout Note:

Need very close to EC

H_RCIN# [20]

R2428

1 2

0R0402-PAD

INT_SERIRQ [20] RSMRST#_KBC [17] PM_SLP_S4# [17,49]

BOOST_MODE# [44] LID_CLOSE# [64] ME_UNLOCK [19]

PCIE_WAKE# [17,30] S5_ENABLE [36]

VBAT

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

X01 X02 X03 2.304V A00

Reserved

100.0KX00

100.0K

100.0K 1.358V

Reserved 100.0K 215.0K 1.048V

R2452

R2452 1KR2J-1-GP

1KR2J-1-GP

TP_ON# [62]

3D3V_AUX_S5 RTC_AUX_S5

DY

LID_CLOSE#

SPI_CS0#_R [18,25] SPI_CLK_R [18,25] CAP_LED# [62] BAT_IN# [42,43,44] SPI_SI_R [18,25] SPI_SO_R [18,25] PM_SUSACK# [17] SUS_CLK [17]

1 2

C2422

SC100P50V2JN-3GPDYC2422

SC100P50V2JN-3GP

12

RB751V-40-H-GP

R2429

R2429 43R2J-GP

43R2J-GP

K A

D2401

D2402

DY

PURE_HW_SHUTDOWN#[26,36,76]H_PROCHOT# [4,42,44,46]

C2416

1 2

83.R2004.H8F

C2415

DY

SC220P50V2KX-3GP

1 2

SC1U10V2KX-1GP

H_PECI [4]

Layout Note:

Need very close to EC

TOUCH_PANEL_INTR# [52]

TP_LID_CLOSE# [62]

R2416

1 2

0R0402-PAD

10KR2J-3-GP

3D3V_AUX_S5

R2439

12

LMBT3906LT1G-1-GP

10.0K

3.0V

20.0K

2.75V

33.0K

2.48V

2.24V

47.0K

2.0V

64.9K

1.87V

76.8

1.65VReserved

100.0K

143.0K

1.204V

174.0KReserved 100.0K

PLT_RST# [17,30,36,52,58,65,73,96]

Power Switch Logic(PSL)

KBC_PWRBTN#[61]

AC_IN#[44]

PSL_OUT#

R2424

0R2J-2-GP

1 2

ECRST#

DY

C2418

SC1U10V2KX-1GP

12

E

DY

B

Q2404

C

64K9R2F-1-GP

R2427

1 2

0R0402-PAD

R2430

1 2

0R0402-PAD

R2446

Cedar_UMA

MODEL_ID_DET

3D3V_AUX_S5

R2432

1 2

1KR2J-1-GP

1 2

R2445

12

57K6R2F-GP

Cedar_OPS

C2403

R2425

R2425 330KR2J-L1-GP

330KR2J-L1-GP

PSL_IN2#

PSL_IN1#

SCD1U16V2KX-3GP

KBC_ON#_GATE_L

MODEL_ID_DET(GPIO07)

Janus-OPS

12

1 2

DY

EC_AGND

12

Janus_OPS

12

Janus-UMA

R2405

TBD

10KR2F-2-GP

TBD 2.702V TBD TBD TBD TBD TBD

Cedar-OPS CedarUMA

TBD

R2407

TBD

100KR2F-L1-GP

TBD TBD TBD TBD TBD TBD TBD

3D3V_AUX_S5 3D3V_AUX_S5

R2431

R2431 330KR2J-L1-GP

330KR2J-L1-GP

1 2

R2433

R2433 20KR2F-L-GP

20KR2F-L-GP

PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

100.0K 3.0V

100.0K

ECSCI#_KBC ECSMI#_KBC ECSWI#_KBC

BAT_SCL BAT_SDA

ECRST#

AC_IN# BAT_IN#

AC_IN_KBC#

FAN_TACH1 TOUCH_PANEL_INTR#

Touch Panel PH internally.

LID_CLOSE# USB_PWR_EN#

C2417 SCD1U16V2KX-3GPC2417 SCD1U16V2KX-3GP

1 2

G

Q2402

Q2402 DMP2130L-7-GP

DMP2130L-7-GP

84.02130.031

2ND = 84.03413.A31

G

S

G

D

Q2403

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

KBC_ON#_GATE

10.0K(64.10025.6DL)

13.7K(64.13725.6DL)

17.8K(64.17825.6DL)

22.1K(64.22125.6DL)

27.0K(64.27025.6DL)

32.4K(64.32425.6DL)

37.4K(64.37425.6DL)

43.2K(64.43225.6DL)

57.6K(64.57625.6DL)

64.9K(64.64925.6DL)

73.2K(64.73225.6DL) 1.905V

82.5K(64.82525.6DL) 1.808V

93.1K(64.93125.6DL) 107K(64.10735.6DL) 120K(64.12035.6DL) 137K(64.13735.6DL) 154K(64.15435.6DL) 200K(64.20035.6DL) 1.099V 232K(64.23236.6DL)

R24080R0402-PAD-1-GP R24080R0402-PAD-1-GP

1 2

R24090R0402-PAD-1-GP R24090R0402-PAD-1-GP

1 2

R24100R0402-PAD-1-GP R24100R0402-PAD-1-GP

1 2

RN2401

1234

SRN4K7J-8-GP

R2418 10KR2J-3-GPR2418 10KR2J-3-GP

1 2

3D3V_AUX_KBC

R2413 100KR2J-1-GP

1 2

DY

R2414 10KR2J-3-GPR2414 10KR2J-3-GP

1 2

R2426 100KR2J-1-GPR2426 100KR2J-1-GP

1 2

R2415 10KR2J-3-GPR2415 10KR2J-3-GP

1 2

R2443 10KR2J-3-GP

1 2

DY

R2421 100KR2J-1-GP

1 2

DY

R2412 100KR2J-1-GP

1 2

DY

R2434

DY

0R2J-2-GP

1 2

3D3V_AUX_KBC

D

EC_SCI# [18,20] EC_SMI# [19]

EC_SWI# [20]

3D3V_AUX_KBC

3D3V_S0

3D3V_S5

3D3V_AUX_KBC

12

R2436

R2436 10KR2J-3-GP

10KR2J-3-GP

S5_ENABLE

2.902V

2.801V

2.598V

2.492V

2.402V

2.201V49.9K(64.49925.6DL)

2.093V

2.001V

1.709V

1.594V

1.499V

1.392V

1.299V

0.994V

A A

5

Title

Size Document Number Rev

Size Document Number Rev A1

A1

Friday, February 07, 2014

Date: Sheet

4

3

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

KBC Nuvoton NPCE885

Janus HSW 40/50/70

24 104

of

A00

5

WWW.AliSaler.Com

SSID = Flash.ROM

4

3

2

1

R2501

4K7R2J-2-GP

12

DY

8 7

5

3D3V_S5

1 2

4

DY

1

3D3V_S5

SPI_HOLD# SPI_CLK_R SPI_SI_R

RN2501

RN2501 SRN4K7J-8-GP

SRN4K7J-8-GP

2 3

SPI25

1

CS#

2

DO/IO1

3

WP#/IO2

4

GND

W25Q64FVSSIQ-GP

72.25Q64.K01

VCC

HOLD#/IO3

CLK

DI/IO0

3D3V_S5

8 7 6 5

EC2501

SC4D7P50V2CN-1GP

Source

72.25Q64.K01

72.25647.00A

C2501

SC10U10V5KX-2GP

12

DY

QUAD/DUAL fast read DUAL fast read

SPI Flash ROM(8M) for PCH

D D

SPI_CS0#_R[18,24]

SPI_SO_R[18,24]

SPI_WP#[18]

EC2502

SC4D7P50V2CN-1GP

C C

SPI_CS0#_R SPI_SO_R SPI_WP#

EC2502

SKT25

1 2

DY

3 6 4

SKT-G6179HT0321-001-GP

62.10089.011

072.25B64.0001

3D3V_S5

12

DY

EC2503

EC2503 SC10P50V2JN-4GP

SC10P50V2JN-4GP

O

12

C2502

C2502 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SPI_HOLD# [18] SPI_CLK_R [18,24] SPI_SI_R [18,24]

O

OO

Single SPI shared flash connection (SPI Quad I/O mode)

Refer to "NCPE985x/ NPCE995x board design reference guide"

SSID = RBATT

B B

A A

5

AFTP2502AFTP2502

RTC1

PWR GND

NP1 NP2

BAT-060003HA002M213ZL-GP-U1

62.70014.001

2nd = 62.70001.061

2nd = 62.70001.061 3rd = 20.F2316.002

3rd = 20.F2316.002

1 2 NP1 NP2

+RTC_VCC

1

D2501

R2502

1KR2J-1-GP

AFTP2501AFTP2501

1

12

4

12

R2504

R2504 10MR2J-L-GP

10MR2J-L-GP

RTC_PWR

1

2

BAS40C-2-GP

75.00040.07D

75.00040.07D 2nd = 75.00040.C7D

2nd = 75.00040.C7D 3rd = 75.00040.A7D

3rd = 75.00040.A7D

Q2505

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

D

RTC_AUX_S5+RTC_VCC 3D3V_AUX_S5

3

12

C2503

SCD47U6D3V2KX-GP

DY

3

RTC_DET# [20]

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, February 07, 2014

Date: Sheet

2

Date: Sheet

Flash/RTC

Janus HSW 40/50/70

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

25 104

of

1

of

A00

5

WWW.AliSaler.Com

SSID = Thermal

4

3

2

1

Fan controller1

12

FAN1

5 3 2

1

4

AFTP2803AFTP2803

FAN_TACH1_C FAN_VCC1

26 104

5V_S0

C2605

12

C2611

SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP

1

A00

of

A00

FAN261

R2605

0R2J-2-GP

1 2

5V_S0

FAN_TACH1[24]

SC4D7U6D3V3KX-GP

EC2602

12

SC10P50V2JN-4GP

2

0R2J-2-GP

DY

FAN_VCC1

C2604

FAN_TACH1 FAN_VCC1

12

DY

SCD1U16V2KX-3GP

12

DY

EC2601

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

6 5

8 7

ALERT#

6 5

3D3V_S0 3D3V_S0

2N7002KDW-GP

1 2

DY

34

Q2601

Q2602

G

D

S

T8

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

THERM_SYS_SHDN#

Close to Thermal sensor

1

T8

4

DY

23

12

DY

RN2602

RN2602 SRN2K2J-1-GP

SRN2K2J-1-GP

12

DY

C2608

SCD1U16V2KX-3GP

12

DY

C2610

12

R2609

24K9R2F-L-GP

R2610

NTC-100K-8-GP

THM_SML1_DATA

THM_SML1_CLK

THM_SML1_CLK THM_SML1_DATA

C2609

SCD1U16V2KX-3GP

PURE_KBCT8

1 2

R2612 0R2J-2-GP

SCD1U16V2KX-3GP

3D3V_AUX_KBC

R2602

1 2

T8

0R2J-2-GP

3D3V_AUX_KBC3D3V_AUX_S5

12

3

Layout Note:

Signal Routing Guideline: Trace width = 15mil

PURE_HW_SHUTDOW N# [24,36,76]

VD_OUT1#

R2607 2KR2F-3-GP

1 2

T8

Close to KBC VD_IN1 for system thermal sensor

R2608

24K9R2F-L-GP

C2612

12

SCD1U16V2KX-3GP

VD_IN1_C

12

C2613

SC100P50V2JN-3GP

VD_OUT1# [24]

VD_IN1 [24]

R2611

1 2

0R0402-PAD

FAN1_DAC_1[24]

Layout Note:

Need 10 mil trace width.

DY

D D

3D3V_S0

SML1_DATA[18,24,76]

84.2N702.A3F

2nd = 84.2N702.E3F

12

C2601

C2602

DY

84.T3904.H11

C C

B B

A A

Q2603

C

T8

E

LMBT3904LT1G-GP

2.System Sensor, Put on palm rest

3D3V_S0

R2603 18K7R2F-GP

R2603 18K7R2F-GP R2604 2KR2F-3-GP

R2604 2KR2F-3-GP

12

C2606

DY

1 2

T8

1 2

T8

5

C2606 SC470P50V3JN-2GP

SC470P50V3JN-2GP

B

Layout Note:

Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

C2602

T8

SCD1U16V2KX-3GP

SC10U6D3V3MX-GP

NCT7718_DXP

12

T8

NCT7718_DXN

Layout Note:

C2812 close U2801

ALERT#

T_CRIT#

C2607

C2607 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

DY

12

T_CRIT#

R2601

R2601 0R2J-2-GP

0R2J-2-GP

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

SML1_CLK[18,24,76]

THM26

1

VDD

2

D+

3

T8

DT_CRIT#4GND

NCT7718W-GP

74.07718.0B9

PCH_PWROK[17,24,36]

THERM_SYS_SHDN#

ALERT#

4

SCL SDA

FAN261

FON#

1

FON#

2

VIN

3

VOUT VSET4GND

AP2113MTR-G1-GP

74.02113.0E1

R2606

1 2

0R0402-PAD

D2601

KA

DY

RB551V30-GP

83.R5003.H8H

THERMAL NCT7718W/Fan

Janus HSW 40/50/70

Friday, February 07, 2014

GND GND GND

FAN_TACH1_C

FAN_VCC1

12

C2603

2nd = 20.F1295.003

DY

SC2200P50V2KX-2GP

AFTP2802AFTP2802 AFTP2801AFTP2801

8 7 6 5

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

ETY-CON3-8-GP

20.F1841.003

1 1

1

5

WWW.AliSaler.Com

www.vinaﬁx.vn

SSID = AUDIO

4

3

2

1

D D

3D3V_S0 +3V_AVDD

25mA

R2701

1 2

0R0402-PAD

1.5A

5V_S0 +5V_PVDD

R2702

1 2

0R0805-PAD-1-GP-U

R2704

1 2

0R0805-PAD-1-GP-U

C C

moat

3D3V_S0

1D5V_S0

R2705 0R0402-PADR2705 0R0402-PAD

1 2

R2710 0R2J-2-GP

1 2

DY

Azalia I/F EMI

EC2708

12

DY

SCD1U16V2KX-3GP

B B

SCD1U16V2KX-3GP

Layout Note:

Close pin41

HDA_CODEC_SDOUT HDA_CODEC_BITCLK

EC2709

12

DY

SCD1U16V2KX-3GP

12

C2701

SC4D7U6D3V3KX-GP

Close pin36

C2708

C2706

12

SC4D7U6D3V3KX-GP

+3V_1D5V_AVDD

AUD_AGND

C2709

C2707

12

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP

Layout Note:

Close pin46

Speaker trace width >40mil @ 2W4ohm speaker power

12

C2715

SC4D7U6D3V3KX-GP

Close pin40

Layout Note:

AMP_MUTE#[24]

DMIC_CLK[52]

SC22P50V2JN-4GP

Close pin3

AUD_AGND AUD_AGND

DMIC_DATA_R

DY

C2723

DY

1 2

C2712 SC10U6D3V3MX-GPC2712 SC10U6D3V3MX-GP

1 2

AUD_SPK_L+[29]

AUD_SPK_L-[29] AUD_SPK_R-[29] AUD_SPK_R+[29]

R2708

0R0402-PAD

TP2702TP2702

EC2701

SC10P50V2JN-4GPDYEC2701

SC10P50V2JN-4GP

12

DMIC_DATA[52]

HDA_CODEC_SDOUT[19]

HDA_CODEC_BITCLK[19]

HDA_SDIN0[19]

HDA_CODEC_SYNC[19]

HDA_CODEC_RST#[19,29]

+3V_1D5V_AVDD

+5V_PVDD

AUD_SPK_L+ AUD_SPK_LAUD_SPK_RAUD_SPK_R+

+5V_PVDD

1

LINE1_VREFO_R[29] LINE1_VREFO_L[29]

AUD_HP1_JACK_L[29] AUD_HP1_JACK_R[29]

12

C2703

C2703 SC1U10V2KX-1GP

SC1U10V2KX-1GP

CBP

LDO2_CAP

EAPD#

COMBO-GPI

C2716

SC4D7U6D3V3KX-GP

R2714

1 2

0R0402-PAD

R27160R2J-2-GP R27160R2J-2-GP

1 2

SC1U10V2KX-1GP

+3V_AVDD

HDA27

37

CBP

38

AVSS2

39

LDO2-CAP

40

AVDD2

41

PVDD1

42

SPK-OUT-L+

43

SPK-OUT-L-

44

SPK-OUT-R-

45

SPK-OUT-R+

46

PVDD2

47

PDB

48

SPDIF-OUT/GPIO2

49

GND

ALC3234-CG-GP

+3V_AVDD

12

DMIC_DATA_R DMIC_CLK_R

R27190R0402-PAD R27190R0402-PAD

1 2

R27200R2J-2-GP R27200R2J-2-GP

1 2

R27180R0402-PAD R27180R0402-PAD

1 2

HDA_CODEC_SYNC

HDA_CODEC_RST#

C2704

1 2

CPVEE

CBN

34

33

36

35

CBN

CPVDD

DVDD1GPIO0/DMIC-DATA2GPIO1/DMIC-CLK3DVSS4SDATA-OUT5BCLK6LDO3-CAP7SDATA-IN8DVDD-IO9SYNC10RESET#11PCBEEP

C2717

12

SCD1U16V2KX-3GP

CODEC_SDOUT_R CODEC_BITCLK_R HDA_CODEC_SDIN0

32

CPVEE

HPOUT-L/PORT-I-L

HPOUT-R/PORT-I-R

71.03234.003

30

31

29

MIC2-VREFO

LINE1-VREFO-L

LINE1-VREFO-R

MIC2_R/PORT-F-R/SLEEVE

SPDIFO/FRONT_JD/ JD3/GPIO3

LDO3_CAP

C2718SC4D7U6D3V3KX-GP C2718SC4D7U6D3V3KX-GP

12

C2705

12

SC2D2U6D3V2MX-GP

AUD_VREF

28

VREF

MIC2_L/PORT-F-L/RING

C2719SCD1U16V2KX-3GP C2719SCD1U16V2KX-3GP

12

Reserved for ALC3234

12

R2711

R2711 100KR2J-1-GP

100KR2J-1-GP

12

C2702

SC4D7U6D3V3KX-GP

LDO1_CAP

25

26

27

AVSS1

AVDD1

LDO1-CAP

LINE2_L/PORT-E-L

LINE2_R/PORT-E-R

LINE1_L/PORT-C-L

LINE1_R/PORT-C-R

NC#20

MIC-CAP

MONO-OUT

MIC2/LINE2_JD/JD2

HP/LINE1_JD/JD1

12

AUD_PC_BEEP

+3V_AVDD

MIC2_VREFO [29]

AUD_AGND

+5V_AVDD AUD_AGND

24 23 22 21

V3D3_STB

20

MIC_CAP

19 18 17 16

JDREF

15 14

AUD_SENSE_A

13

moat

12

C2711

Layout Note:

Place close to Pin 26

AUD_AGND

SC4D7U6D3V3KX-GP

LINE1_L [29] LINE1_R [29]

R2712 0R2J-2-GPR2712 0R2J-2-GP

1 2

SLEEVE [29] RING2 [29]

AUD_SENSE

Layout Note:

Place close to Pin 13

1 2

C2710

SCD1U16V2KX-3GP

C2713 SC10U6D3V3MX-GPC2713 SC10U6D3V3MX-GP

1 2

R2707 20KR2F-L-GP

1 2

DY

1 2

R2709

200KR2F-L-GP

HDA_SPKR[20]

KBC_BEEP[24]

R2703

0R0603-PAD-1-GP-U

RN2701

2 3 1

SRN0J-6-GP

moat

EC2707 SC1KP50V2KX-1GP

1 2

DY

EC2706 SC1KP50V2KX-1GP

1 2

DY

EC2705 SCD1U25V2KX-GPEC2705 SCD1U25V2KX-GP

1 2

EC2704 SC1KP50V2KX-1GP

1 2

DY

EC2703 SCD1U25V2KX-GPEC2703 SCD1U25V2KX-GP

5V_S0+5V_AVDD

AUD_AGND

Layout Note:

AUD_AGND

AUD_SENSE [29]

4

AUD_AGND

3D3V_S5

Width>40mil, to improve Headpohone Crosstalk noise Change it to sharp will be better. Add 2 vias (>0.5A) when trace layer change.

HDA_SPKR_R

KBC_BEEP_R

2nd = 83.R2003.W81

3rd = 75.00054.A7D

3rd = 75.00054.A7D 4th = 83.R2003.V81

4th = 83.R2003.V81

1 2

Layout Note:

Tied at point only under Codec or near the Codec

AUD_SENSE_A

moat

D2701

2

1

BAT54C-7-F-3-GP

75.00054.E7D

0R0805-PAD-1-GP-U

R2722

100KR2J-1-GP

AUD_PC_BEEP_C

3

R2706

12

+3V_AVDD

C2720

1 2

R2717

R2717 1KR2J-1-GP

1KR2J-1-GP

AUD_PC_BEEP

SCD1U16V2KX-3GP

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u R d., Hsichih,

21F, 88, Sec.1, Hsin Tai W u R d., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Audio Codec ALC3234

Janus HSW 40/50/70

1

27 104Monday, February 10, 2014

A00

of

5

Title

Size Document Number Rev

A2

Date: Sheet

4

3

2

Date: Sheet

5

WWW.AliSaler.Com

D D

4

3

2

1

C C

B B

A A

5

4

(Blanking)

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document Number Rev

A4

Date: Sheet

2

Janus HSW 40/50/70

Reserved

28 104Friday, February 07, 2014

of

1

A00

5

WWW.AliSaler.Com

SSID = AUDIO

4

3

2

1

Layout Note:

Speaker trace width >40mil @ 2W4ohm speaker power

AUD_SPK_R+_C

R29040R0603-PAD-1-GP-U R29040R0603-PAD-1-GP-U

12

SC100P50V2JN-3GPDYEC2906

SC100P50V2JN-3GP

DY

12

AUD_SPK_R-_C

R29030R0603-PAD-1-GP-U R29030R0603-PAD-1-GP-U

12

AUD_SPK_L+_C

R29020R0603-PAD-1-GP-U R29020R0603-PAD-1-GP-U

12

AUD_SPK_L-_C

R29010R0603-PAD-1-GP-U R29010R0603-PAD-1-GP-U

12

AUD_AGND

EC2906

EC2905

SC100P50V2JN-3GPDYEC2905

SC100P50V2JN-3GP

12

DY

LINE1-L_C

LINE1-L_R

AUD_SPK_R+[27] AUD_SPK_R-[27]

AUD_SPK_L+[27] AUD_SPK_L-[27]

RN2901

1

4

2 3

SRN2K2J-1-GP

R2908 10R2F-L-GPR2908 10R2F-L-GP

1 2

R2922 1KR2J-1-GPR2922 1KR2J-1-GP

1 2

R2912 4K7R2J-2-GPR2912 4K7R2J-2-GP

1 2

R2910 10R2F-L-GPR2910 10R2F-L-GP

1 2

R2921 1KR2J-1-GPR2921 1KR2J-1-GP

1 2

R2913 4K7R2J-2-GPR2913 4K7R2J-2-GP

1 2

12

DY

EC2901

SC2K2P50V3KX-GP

12

DY

EC2902

EC2903

SC2K2P50V3KX-GP

12

DY

EC2904

SC2K2P50V3KX-GP

AUD_HP1_JACK_L1

AUD_HP1_JACK_R1

EC2908

SC100P50V2JN-3GPDYEC2908

SC100P50V2JN-3GP

R2920

10KR2J-3-GPDYR2920

10KR2J-3-GP

12

DY

EC2907

SC100P50V2JN-3GPDYEC2907

SC100P50V2JN-3GP

R2919

10KR2J-3-GPDYR2919

10KR2J-3-GP

12

DY

D D

C C

MIC2_VREFO[27]

RING2[27]

AUD_HP1_JACK_L[27]

LINE1_L[27]

LINE1_VREFO_L[27]

AUD_HP1_JACK_R[27]

LINE1_R[27]

LINE1_VREFO_R[27]

SLEEVE[27]

C2907

C2908

1 2

SC4D7U6D3V3KX-GP

1 2

SC4D7U6D3V3KX-GP

Speaker

SPK1

1 2

3 4

ACES-CON4-29-GP

20.F1639.004

2nd = 20.F1804.004

AUD_SPK_L-_C AUD_SPK_L+_C AUD_SPK_R-_C

AUD_SPK_R+_C

AUD_PORTA_L_R_B AUD_PORTA_R_R_B

AUD_SENSE

R29060R0603-PAD-1-GP-U R29060R0603-PAD-1-GP-U

12

R29070R0603-PAD-1-GP-U R29070R0603-PAD-1-GP-U

12

R29090R0603-PAD-1-GP-U R29090R0603-PAD-1-GP-U

12

R29110R0603-PAD-1-GP-U R29110R0603-PAD-1-GP-U

12

5

6

CONN Pin Pin1 Pin2 Pin3 Pin4

AFTP2901AFTP2901

1

AFTP2902AFTP2902

1

AFTP2903AFTP2903

1

AFTP2904AFTP2904

1

AFTP2906AFTP2906

1

AFTP2907AFTP2907

1 1 1

RING2_R AUD_PORTA_L_R_B

JACK_PLUG AUD_PORTA_R_R_B

SLEEVE_R

AFTP2908AFTP2908 AFTP2909AFTP2909

AUD_AGND

Combo Jack

Net name SPK_R+ SPK_RSPK_L+ SPK_L-

HPMIC1

3 1

5 6 2 4

MS

AUDIO-JK430-GP

022.10002.0001

JACK_PLUG_DETJACK_PLUG_DET

10 mils

3D3V_S0

12

AUD_AGND

R2914

R2914 10KR2J-3-GP

10KR2J-3-GP

AUD_DELAY

0R0402-PAD

0R0402-PAD R2916

R2916

NON_DELAY

B B

AUD_AGND AUD_AGND

AUD_PORTA_R_R_B

AUD_PORTA_L_R_B

RING2_R

AUD_SENSE

SLEEVE_R

AZ2025-01H-R7G-GP

DY

AZ2025-01H-R7G-GP

DY

AZ2025-01H-R7G-GP

ED2905

1 2

4

ED2904

1 2

AZ2025-01H-R7G-GP

DY

AZ2025-01H-R7G-GP

ED2903

ED2902

DY

1 2

AZ2025-01H-R7G-GP

ED2901

DY

ED2901

1 2

A A

moat

5

12

R2915

DY

470KR2J-2-GP

AUD_AGND

4th = 84.DMN66.03F

3rd = 75.00601.07C

2nd = 84.2N702.E3F

84.2N702.A3F

S

5

D

6

U2901

DY

2N7002KDW-GP

3

R2918

100KR2J-1-GP

D

34

GG

MUTE_CTRLSLEEVE_CTRL

2

S

1

+3V_AVDD5V_PWR_2

12

DY

12

DY

Delay circuit

R2917

DY

0R3J-0-U-GP

C2901

C2901 SC1U10V2KX-1GP

SC1U10V2KX-1GP

JACK_PLUG

AUD_DELAY

12

AUD_AGND

10 mils

AUD_DELAY

R2905

R2905 100KR2J-1-GP

100KR2J-1-GP

AUD_DELAY

AUD_AGND

R2923

1 2

0R0603-PAD-1-GP-U

HDA_CODEC_RST# [19,27]

SLEEVE [27]

2

12

C2902

C2902 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

NON_DELAY

AUD_AGND

G

Q2901

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, February 07, 2014

Date: Sheet

S

AUD_DELAY

D

10 mils

Speaker/HPMIC

Janus HSW 40/50/70

AUD_SENSE [27]

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

29 104

of

A00

5

WWW.AliSaler.Com

4

3

2

1

Layout: For RTL8111G(S) * Place C3021 to C3024 close to each VDD10 pin--3, 8, 22, 30 For RTL8106E * Place C3021,C3022 cl ose to each VDD10 pin-- 8, 30

D D

C C

B B

C3002,R3001: Only for RTL8111 LDO mode.

C3002

8111G

Layout: For RTL8111G(S) * Place C3007 and C3008 close to each VDD33 pin-- 11, 32 For RTL8106E * Place C3003 and C3008 close to each VDD33 pin-- 23, 32

3D3V_LAN_S5 VDDREG

12

C3007

8111G/LAN_SW

C3007

12

SCD1U16V2KX-3GP

40 mils

SCD1U16V2KX-3GP

1 2

68.4R71E.10G

12

C3008

SCD1U16V2KX-3GP

R3001

1 2

8111G

0R3J-0-U-GP

L3001

L3001 IND- 4D7U H-24 2-GP

IND- 4D7U H-24 2-GP

LAN_SW

12

8106E

LAN_SW

12

C3012SC4D7U6D3V3KX-GP

0R0603-PAD-1-GP-U

C3003

SCD1U16V2KX-3GP

C3008: close to Pin32 C3007: close to Pin11 C3003: close to Pin23

PM_LAN_ENABLE[24]

12

R3006

1 2

R3023

100KR2J-1-GP

C3019 SCD1U16V2KX-3GP

PLT_RST#[17,24,36,52,58,65,73,96]

12

C3021: colse to Pin8 C3022 close to Pin30 C3023: close to Pin3 C3024: close to Pin22

VDD10REGOUT

C3021 SCD1U16V2KX-3GPC3021 SCD1U16V2KX-3GP

C3009

84.T3904.H11

3D3V_S5

Q3001

G

S

2N7002K-2-GP

8111G/LAN_SW

C3022 SCD1U16V2KX-3GPC3022 SCD1U16V2KX-3GP

12

LAN_SW

12

C3010

SCD1U16V2KX-3GP

3D3V_LAN_S5

1

23

RN3001

DY

SRN10KJ-5-GP

4

Q402_1

Q3003 LMBT3904LT1G-GP

CBE

DY

R3016

1 2

0R0603-PAD

12

R3021

C3013

10KR2J-3-GP

SCD1U16V2KX-3GP

LAN_ENABLE_R_C

D

8111G/LAN_SW

C3023 SCD1U16V2KX-3GP

12

SC4D7U6D3V3KX-GP

X5R

PLT_RST#_LAN

85mA

R3022

1 2

20KR2J-L2-GP

C3024 SCD1U16V2KX-3GP

12

C3015

C3015 SC1U10V2KX-1GP

SC1U10V2KX-1GP

PM_LAN_ENABLE_R

84.02130.031

84.02130.031 2nd = 84.00102.031

2nd = 84.00102.031 3rd = 84.03413.B31

3rd = 84.03413.B31

RTL8111G-CGTRTL8111GUS-CG RTL8106EUS-CG RTL8106E-CG

71.08111.W03 71.08111.U03

SWR mode SWR mode

LDO mode

10/100/1000M 10/100/1000M

3D3V_LAN_S5

C3004

12

DY

SC4D7U6D3V3KX-GP

3D3V_LAN_S5 rise time must be controlled between 0.5 mS and 100 mS.

3D3V_LAN_S5

Q3004

DMP2130L-7-GP

S

D

G

DY

LAN CHIP (10/100/1000M & 10/100M co-lay)

R3032

71.08106.003

10/100M

LAN_MDI0P[31] LAN_MDI0N[31]

LAN_MDI1P[31] LAN_MDI1N[31] LAN_MDI2P[31] LAN_MDI2N[31]

C3005

12

DY

SC4D7U6D3V3KX-GP

Layout: C3004: close to Pin32 C3005: close to Pin11

12

C3017

SCD1U16V2KX-3GP

071.08106.0003

LDO mode

10/100M

LANXOUT

LANXIN

VDD10

RTL8111G-CGT-1-GP-U1

LAN_MDI3P[31] LAN_MDI3N[31]

41

C3001

SC15P50V2JN-2-GP

R3032 2K49R2F-GP

2K49R2F-GP

1 2

LOM30

33

GND

1

MDIP0

2

MDIN0

3

AVDD10

4

MDIP1

5

MDIN1

6

(NC)

MDIP2

7

(NC)

MDIN2

8

AVDD10

3D3V_LAN_S5 CLK_LAN_REQ4#_R PCIE_PTX_LANRX_P4_C PCIE_PTX_LANRX_N4_C CLK_PCIE_LAN_P4 CLK_PCIE_LAN_N4

C3011

1 2

SC15P50V2JN-2-GP

X3001

X3001 XTAL-25MHZ-181-GP

XTAL-25MHZ-181-GP

82.30020.G71

2 3

1 2

3D3V_LAN_S5

32

AVDD33

(NC)

71.08111.U03

(071.08106.0003)

(NC)

MDIP39MDIN3

LED0 LED1

RSET

LANXIN

LANXOUT

VDD10

LED2

30

31

25

27

26

28

LED2

LED0

RSET

AVDD10

CKXTAL229CKXTAL1

LED1/GPO

(LED1) (NC)

(GPO)

(DVDD33)

(NC)

HSIP13HSIN14REFCLK_P15REFCLK_N

CLKREQ#

AVDD33

16

12

10

11

LAN_TXP_C_PCH_R XP4 LAN_TXN_C_PCH _RXN4

PCIE_PTX_LANRX_P4_C PCIE_PTX_LANRX_N4_C

TP3003 TPAD14-OP-GPTP3003 TPAD14-OP-GP

1

TP3002 TPAD14-OP-GPTP3002 TPAD14-OP-GP

1

TP3001 TPAD14-OP-GPTP3001 TPAD14-OP-GP

1

REGOUT

24

REGOUT VDDREG

LANWAKE#

ISOLATE#

071.08106.0003(DVC)/71.08111.U03(DVJ)

RTL8111G-CGT (71.08111.U03/LDO Mode): 10/100/1000M < 252 mW. RTL8106E-CG (071.08106.0003): 10/100M <70mW.

DVDD10

PERST#

HSON HSOP

23 22 21 20 19 18 17

CLK_PCIE_LAN_REQ4#[18,20]

PCIE_WAKE#

VDDREG VDD10 PCIE_WAKE# ISOLAT E#

PLT_RST#_LAN

LAN_TXN_C_PCH _RXN4 LAN_TXP_C_PCH_R XP4

R3033

1 2

10KR2J-3-GP

C3014

SCD1U16V2KX-3GP

1 2

SCD1U16V2KX-3GP

1 2

C3016

C3018

1 2

SC1U10V2KX-1GP

C3025 SCD1U16V2KX-3GPC3025 SCD1U16V2KX-3GP

1 2

PCIE_WAKE# [17,24]

12

3D3V_S5

3D3V_LAN_S5

12

R3003

DY

10KR2J-3-GP

CLK_LAN_REQ#_EN

84.T3904.H11

Q3002 LMBT3904LT1G-GP

CBE

DY

R3005

1 2

0R0402-PAD

PCIE_PRX_LANTX_P4 [16] PCIE_PRX_LANTX_N4 [16]

PCIE_PTX_LANRX_P4_C [16] PCIE_PTX_LANRX_N4_C [16]

CLK_PCIE_LAN_P4 [18] CLK_PCIE_LAN_N4 [18]

3D3V_S0

12

R3014

R3014 1KR2J-1-GP

1KR2J-1-GP

R3015

R3015 15KR2J-1-GP

15KR2J-1-GP

3D3V_LAN_S5

12

R3004

R3004 10KR2J-3-GP

10KR2J-3-GP

DY

CLK_LAN_REQ4#_R

1.0V Source

RTL8111G-CGT (71.08111.U03)

A A

5

4

RTL8111GUS-CG (71.08111.W03)/ RTL8106EUS-CG (71.08106.003)

RTL8106E-CG (071.08106.0003)

LDO

SWR

LDO

R3001 C3002 C3023 C3024 C3007

OOOOO

XXO OO

X

XXX

3

L3001 C3012 C3019 C3010C3009 C3003

XXX XX

OOOOO

XX

XXXX

2

X

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u R d., Hsichih,

O

Title

LAN RTL8111/RTL8106

Size Document Number Rev

A2

Date: Sheet

21F, 88, Sec.1, Hsin Tai W u R d., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

1

A00

30 104Friday, February 07, 2014

A00

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SSID = LOM

LAN TransFormer (10/100/1000M & 10/100M co-lay)

Layout note: 30 mil spacing between MDI differential pairs.

D D

MCT0 MCT1 MCT2

XF3102 XFORM-12P-48-GP

1CT:1CT

LAN_MDI3N[30]

LAN_MDI3P[30]

LAN_MDI2N[30]

LAN_MDI2P[30]

C C

LOM_TCT

12

C3106

C3106 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

LAN_MDI1N[30]

LAN_MDI1P[30]

LAN_MDI0N[30]

LAN_MDI0P[30]

1 2

DY

EC3108 SC10P50V2JN-4GP

1 2

DY

EC3107 SC10P50V2JN-4GP

1 2

DY

EC3106 SC10P50V2JN-4GP

1 2

DY

EC3105 SC10P50V2JN-4GP

1 2

DY

EC3104 SC10P50V2JN-4GP

1 2

DY

EC3103 SC10P50V2JN-4GP

1 2

DY

EC3102 SC10P50V2JN-4GP

1 2

DY

EC3101 SC10P50V2JN-4GP

12

11 10

10/100/1000

1CT:1CT

8

7 9

XF3101

9 7

8 10 11

12

XFORM-12P-48-GP

68.68167.30D

1CT:1CT

1

MCT0

3 2

5

MCT1

4 6

6

MCT2

4 5

2

MCT3

3 1

MDO3-

MDO3+

MDO2-

MDO2+

MDO1-

MDO1+

MDO0-

MDO0+

MCT3

123

45

RN3101

RN3101 SRN75J-1-GP

SRN75J-1-GP

678

MCT

12

C3101

C3101 SC100P3KV8JN-2-GP

SC100P3KV8JN-2-GP

78.1013N.1AL

LAN_MDI0P LAN_MDI0N

LAN_MDI1P LAN_MDI1N

LAN_MDI2P LAN_MDI2N

LAN_MDI3P LAN_MDI3N

MDO0+ MDO0-

MDO1+ MDO2+ MDO2MDO1MDO3+ MDO3-

Follow Reference Schematic 0.01uF~0.4uF

B B

2nd = 022.10001.0561

U3101

1

IN1

NC#10

2

IN2

NC#9

GND3GND

4

IN3

NC#7

5

DY

IN4

NC#6

TVWDF1004AD0-1-GP

75.01004.073

U3102

1

IN1

NC#10

2

IN2

NC#9

GND3GND

4

IN3

NC#7

5

DY

IN4

NC#6

TVWDF1004AD0-1-GP

75.01004.073

RJ45-8P-165-GP

9

CHASSIS#9

1

MDO0+

2

MDO0-

3

MDO1+

4

MDO2+

5

MDO2-

6

MDO1-

7

MDO3+

8

MDO3-

10

CHASSIS#10

RJ45

022.10001.0551

LAN_MDI0P

10

LAN_MDI0N

9 8

LAN_MDI1P

7

LAN_MDI1N

6

LAN_MDI2P

10

LAN_MDI2N

9 8

LAN_MDI3P

7

LAN_MDI3N

6

Layout: Place near RJ45

AFTP3107AFTP3107 AFTP3102AFTP3102 AFTP3101AFTP3101 AFTP3103AFTP3103 AFTP3104AFTP3104 AFTP3106AFTP3106 AFTP3105AFTP3105 AFTP3108AFTP3108

A A

5

4

3

1 1 1 1 1 1 1 1

2

MDO0+ MDO0MDO1+ MDO2+ MDO2MDO1MDO3+ MDO3-

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

XFOM&RJ45

31 104Monday, February 10, 2014

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