Dell Inspiron 15 3467,Inspiron 153567 Schematics

5

D D

4

3

2

1

Vegas Schematic

SKL/KBL-U

C C

2016/06/27 REV : A00

B B

DY : None Installed

A A

UMA: UMA only installed OPS: DISCRTE OPTIMUS installed

5

4

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Cover Page

Size Document Number Rev

Size Document Number Rev A4

A4

Monday, June 27, 2016

Date: Sheet of

2

Cover Page

Vegas SKL/KBL-U

1 105

1

A00

5

WWW.AliSaler.Com

Project code:4PD09P010001 PCB P/N: 15341-SD Revision: A00

D D

2GB = 256b x 16 x 4pcs

VRAM(DDR3L) *4

2GB(256Mbx16)

78,79

GDDR5

DIS only

14"/15" LCD

Touch Panel

C C

B B

Universal Jack

A A

Camera

Digital MIC

RJ45 Conn.

HDMI V1.4a

VGA Conn.

USB1(USB3.0)

USB2(USB3.0)

2CH SPEAKER (2CH 2W/4ohm)

29

USB3(USB2.0)

SD Card Slot

IO Board

5

55

32

56

Left side

57

36

MIC_IN/GND HP_R/L

Realtek RTS5170

LAN 10/100

REALTEK RTL8106G

LAN 10/100/1000

REALTEK RTL8111G

DP/VGA Converter

REALTEK RTD2166

Audio Codec

ALC3246

CardReader

4

3

2

Vegas SKL-U/KBL-U Block Diagram

GPU

AMD R16M-M1-20 25W

73,74,75,76,77

TURIS only

31

VEGAS only

56

VEGAS only VEGAS only

27

4

PCIE x 4

eDP x2

USB2.0 x1

PCIE x1

DDI1

DDI2

USB2.0 x1

USB3.0 x1

USB2.0 x1

USB3.0 x1

HDA

USB2.0 x1

Intel CPU

Skylake-U 2+3e Kabylake-U 2+3e

15W (UMA&DIS) 28W (UMA)

SKL PCH-LP KBL PCH-LP

10 USB 2.0/1.1 ports

6 USB 3.0 ports

High Definition Audio

3 SATA ports 6 PCIE ports LPC I/F ACPI 5.0

3

DDR4 1866/2133MHz Channel A

VEGAS only

DDR4 1866/2133MHz Channel B

USB2.0 x1

PCIE x1

USB2.0 x1

SATA (Gen3) x1

SATA (Gen1) x1

LPC BUS

SPI

I2C

Flash ROM

16MB

FRINGERPRINT

CRW-CP-GHC-F1

VEGAS only

NGFF WLAN

802.11a/b/g/n BT V4.0 combo

HDD

ODD

EC

SMSC MEC1404-NU-GP

25

Int. KB

PS2

2

92

61

60

24

65

PrecisionTouch pad

1

CHARGER

ISL88739

INPUTS

AD+

BT+

SYSTEM DC/DC

TPS51225RUKR-GP

INPUTS

DCBATOUT

DDR4 1866

SODIMM A

DDR4 1866

SODIMM B

12

CPU Core Power

NCP81208MNTXG NCP81382MNTXG x 2 NCP81382MNTXG (23e) NCP81253MNTBG

INPUTS

DCBATOUT

DCBATOUT+VCCSA

DDR4 SUS

RT8231AGQW-GP APL5930KAI-TRG

INPUTS

DCBATOUT 3D3V_S5

CPU VCCPRIM_CORE 1V

INPUTS OUTPUTS

1D0V_S5

CPU DCDC-V1D00A

AOZ2262QI-10-GP-U

DCBATOUT

LDO-V1D8V

APL5930KAI-TRG

TPM 2.0

NPCT650JBAWX

LPC debug port

91

68

FAN Control

26

65

Title

Size Document Number Rev

C

Date: Sheet of

3D3V_S5

5V/3V S0

TPS22966DPUR-GP

5V_S5 3D3V_S5

EOPIO/EDRAM (23e)

TPS22961DNYT

INPUTS

1D0V_S5 1D0V_S5

3D3V VGA

AO3419L

INPUTS

3D3V_S0

VGA_CORE

ISL62771HRTZ-GP-U

INPUTS

DCBATOUT

1D5V_VGA_S0

Y8288RAC-GP

INPUTS

DCBATOUT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

Vegas SKL/KBL-U

1

OUTPUTS

44

DCBATOUT

45

OUTPUTS

3D3V_PWR 3D3V_S5 5V_PWR 5V_S5

46~50

33

OUTPUTS

VCC_CORE

+VCCGTDCBATOUT

+VCCGT (23e)

51

OUTPUTS

1D2V_S3 0D6V_S0 2D5V_S3

11

+VCCPRIM_CORE

53

OUTPUTSINPUTS

1D0V_S5

54

OUTPUTSINPUTS

1D8V_S5

40

OUTPUTSINPUTS

5V_S0 3D3V_S0

40

OUTPUTS

+V_EDRAM_VR

+V_EOPIO_VR

86

OUTPUTS

3D3V_VGA_S0

85

OUTPUTS

VGA_CORE

86

OUTPUTS

1D5V_VGA_S0

A00

2 105Tuesday, June 21, 2016

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

(Reserved)

2

Vegas SKL/KBL-U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

3 105Thursday, June 16, 2016

1

5

WWW.AliSaler.Com

4

3

2

1

Main Func = CPU

#544669 CRB Rev0.52

R419

R419 1KR2J-1-GP

1KR2J-1-GP

R420

1 2

DY

0R2J-2-GP

JTAG

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

4 OF 20

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PCH_TRST#

JTAGX

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

H_THERMTRIP# 40

XDP_TCLK XDP_TDI XDP_TDO_CPU XDP_TMS XDP_TRST#

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS XDP_TRST# XDP_TCK_JTAGX

XDP_TMS XDP_TDI

XDP_TDO_CPU

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

XDP_TCK_JTAGX

XDP_TRST# XDP_TCLK

PCH_JTAG_TCK

XDP_TRST#

EC401

12

DY

SC1KP50V2KX-1GP

1 2

DY

R42151R2J-2-GP

DY

DY DY

DY

DY DY

DY

R42151R2J-2-GP R42251R2J-2-GP

R42251R2J-2-GP R42351R2J-2-GP

R42351R2J-2-GP

R40851R2J-2-GP R40851R2J-2-GP R409100R2J-2-GP R409100R2J-2-GP R41651R2J-2-GP R41651R2J-2-GP R4171KR2J-1-GP

R4171KR2J-1-GP

1 2 1 2

1 2 1 2 1 2 1 2

R402 51R2J-2-GP

1 2

R406 51R2J-2-GPR406 51R2J-2-GP

1 2

R407 51R2J-2-GP

1 2

+VCCSTG

SKYLAKE_ULT

CPU MISC

+VCCST_CPU

12

#543016 Rev0.7: Ra = 500 ohm / Rb = 1k ohm #544669 Rev0.52: Ra = 56 ohm (TO BE CHANGED TO 100 OHMS) / Rb = 62 ohm and 150 ohm

+VCCSTG

D D

[PECI] and [PROCHOT#] Impedance control: 50 ohm

H_PECI24

H_PROCHOT#24,44,46

INT_TP#24,65

C C

Rb

R410

1 2

0R0402-PAD

+VCCSTG = 1.0 V +VCCSTG = 1.0 V

R41249D9R2F-GP R41249D9R2F-GP R41349D9R2F-GP R41349D9R2F-GP

R41449D9R2F-GP R41449D9R2F-GP R41549D9R2F-GP R41549D9R2F-GP

PCH_THERMTRIP

CPU1D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKYLAKE-U-GP

071.SKYLA.000U

CPU_POPIRCOMP

12

PCH_POPIRCOMP

12

EDRAM_OPIO_RCOMP

12

EOPIO_RCOMP

12

R401

R401 1KR2J-1-GP

1KR2J-1-GP

TPAD14-OP-GP

TOUCH_PANEL_INTR#24,55

TPAD14-OP-GP

R403499R2F-2-GP R403499R2F-2-GP

1 2

Ra

TPAD14-OP-GP

TPAD14-OP-GP TPAD14-OP-GP

TPAD14-OP-GP

TP403

TP404

TP401

TPAD14-OP-GP

1

TP402

TP402 TP405

TP405 TP406

TP406 TP407

TP407 TP408

TP408

GPP_E3/CPU_GP0

1

GPP_B4/CPU_GP3

1

H_CATERR# H_PROCHOT#_R

PCH_THERMTRIP SKTOCC#

1

XDP_BPM0

1

XDP_BPM1

1

XDP_BPM2

1

XDP_BPM3

1

TOUCHPAD_INTR#

CPU_POPIRCOMP PCH_POPIRCOMP EDRAM_OPIO_RCOMP EOPIO_RCOMP

(#543016) PROCHOT# Routing Guidelines

B B

M1,2,3,4,5: <3 inches M6: 1-11 inches MCPU: 0.3-1.5 inches Mt <0.3 mils Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(JTAG/CPU SIDE BAND)

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Vegas SKL/KBL-U

4 105Monday, June 27, 2016

1

A00

5

4

3

2

1

Main Func = CPU

DDR4 ball type: Interleaved Type

D D

CPU1C

AY39

AW39

AY37

AW37

BB39 BA39 BA37 BB37 AY35

AW35

AY33

AW33

BB35 BA35 BA33 BB33 AU40 AT40 AT37 AU37 AR40 AP40 AP37 AR37 AT33 AU33 AU30 AT30 AR33 AP33 AR30 AP30 AY31

AW31

AY29

AW29

BB31 BA31 BA29 BB29 AY27

AW27

AY25

AW25

BB27 BA27 BA25 BB25 AU27 AT27 AT25 AU25 AP27 AN27 AN25 AP25 AT22 AU22 AU21 AT21 AN22 AP22 AP21 AN21

Q502

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

CPU1C

DDR0_DQ[32]/DDR1_DQ[0] DDR0_DQ[33]/DDR1_DQ[1] DDR0_DQ[34]/DDR1_DQ[2] DDR0_DQ[35]/DDR1_DQ[3] DDR0_DQ[36]/DDR1_DQ[4] DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQ[47]/DDR1_DQ[15] DDR1_DQ[32]/DDR1_DQ[16] DDR1_DQ[33]/DDR1_DQ[17] DDR1_DQ[34]/DDR1_DQ[18] DDR1_DQ[35]/DDR1_DQ[19] DDR1_DQ[36]/DDR1_DQ[20] DDR1_DQ[37]/DDR1_DQ[21] DDR1_DQ[38]/DDR1_DQ[22] DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQ[47]/DDR1_DQ[31] DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQ[61]/DDR1_DQ[45] DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQ[63]/DDR1_DQ[47] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]

SKYLAKE-U-GP

071.SKYLA.000U

3D3V_S0

12

R506

R506 220KR2F-GP

220KR2F-GP

D

SKYLAKE_ULT

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[ 5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[ 9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[ 6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[ 8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[ 7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[ 12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[ 11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT # DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[ 13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[ 2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[ 10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[ 1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[ 0]

DDR CH - B

SM_PGCNTL_R 51

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

Design Guideline: SM_RCOMP keep routing length less than 500 mils.

3 OF 20

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

BA38 AY38 AY34 BA34 AT38 AR38 AT32 AR32 BA30 AY30 AY26 BA26 AR25 AR27 AR22 AR21

AN43 AP43 AT13 AR18 AT18 AU18

M_B_A5 M_B_A9 M_B_A6 M_B_A8 M_B_A7

M_B_A12 M_B_A11 M_B_ACT_N

M_B_A13 M_B_A15 M_B_A14 M_B_A16

M_B_A2 M_B_A10

M_B_A1 M_B_A0 M_B_A3 M_B_A4

M_A_DQS_DN4 M_A_DQS_DP4 M_A_DQS_DN5 M_A_DQS_DP5 M_B_DQS_DN4 M_B_DQS_DP4 M_B_DQS_DN5 M_B_DQS_DP5 M_A_DQS_DN6 M_A_DQS_DP6 M_A_DQS_DN7 M_A_DQS_DP7 M_B_DQS_DN6 M_B_DQS_DP6 M_B_DQS_DN7 M_B_DQS_DP7

SM_DRAMRST # SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

#543016

M_B_CLK#0 13 M_B_CLK#1 13 M_B_CLK0 13 M_B_CLK1 13

M_B_CKE0 13 M_B_CKE1 13

M_B_CS#0 13 M_B_CS#1 13 M_B_DIMB_ODT0 13 M_B_DIMB_ODT1 13

M_B_A5 13 M_B_A9 13 M_B_A6 13 M_B_A8 13 M_B_A7 13

M_B_BG0 13

M_B_A12 13

M_B_A11 13 M_B_ACT_N 13 M_B_BG1 13

M_B_A13 13

M_B_A15 13

M_B_A14 13

M_B_A16 13 M_B_BA0 13

M_B_A2 13

M_B_BA1 13

M_B_A10 13

M_B_A1 13 M_B_A0 13 M_B_A3 13 M_B_A4 13

M_A_DQS4 M_A_DQS5 M_B_DQS4 M_B_DQS5 M_A_DQS6 M_A_DQS7 M_B_DQS6 M_B_DQS7

M_B_ALERT_N 13 M_B_PARITY 13

R501 121R2F-GPR501 121R2F-GP

1 2

R502 80D6R2F-L-GPR502 80D6R2F-L-GP

1 2

R503 100R2F-L1-GP-UR503 100R2F-L1-GP-U

1 2

Layout Note:

1D2V_S3

12

R505

R505 470R2F-GP

470R2F-GP

R504

1 2

0R0402-PAD

ED502

AZ5725-01FDR 7G-GP

DY

1 2

83.05725.0A0

close to CPU

DDR4_DR AMRST# 12,13

CPU1B

M_A_DQ0

M_A_DQ012 M_A_DQ112 M_A_DQ212

M_A_DQ[0:7]

M_A_DQ[8:15]

M_B_DQ[0:7]

M_B_DQ[8:15]

C C

M_A_DQ[16:23]

M_A_DQ[24:31]

M_B_DQ[16:23]

M_B_DQ[24:31]

DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel.

B B

Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential clock pair to clock pair swapping within a channel is not allowed.

M_A_DQ312 M_A_DQ412 M_A_DQ512 M_A_DQ612 M_A_DQ712 M_A_DQ812

M_A_DQ912 M_A_DQ1012 M_A_DQ1112 M_A_DQ1212 M_A_DQ1312 M_A_DQ1412 M_A_DQ1512 M_B_DQ013 M_B_DQ113 M_B_DQ213 M_B_DQ313 M_B_DQ413 M_B_DQ513 M_B_DQ613 M_B_DQ713 M_B_DQ813 M_B_DQ913 M_B_DQ1013 M_B_DQ1113 M_B_DQ1213 M_B_DQ1313 M_B_DQ1413 M_B_DQ1513 M_A_DQ1612 M_A_DQ1712 M_A_DQ1812 M_A_DQ1912 M_A_DQ2012 M_A_DQ2112 M_A_DQ2212 M_A_DQ2312 M_A_DQ2412 M_A_DQ2512 M_A_DQ2612 M_A_DQ2712 M_A_DQ2812 M_A_DQ2912 M_A_DQ3012 M_A_DQ3112 M_B_DQ1613 M_B_DQ1713 M_B_DQ1813 M_B_DQ1913 M_B_DQ2013 M_B_DQ2113 M_B_DQ2213 M_B_DQ2313 M_B_DQ2413 M_B_DQ2513 M_B_DQ2613 M_B_DQ2713 M_B_DQ2813 M_B_DQ2913 M_B_DQ3013 M_B_DQ3113

M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

SKYLAKE-U-GP

071.SKYLA.000U

SKYLAKE_ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[ 5]

DDR0_DQ[16]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[ 9]

DDR0_DQ[17]

DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[ 6]

DDR0_DQ[18]

DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[ 8]

DDR0_DQ[19]

DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[ 7]

DDR0_DQ[20]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_DQ[21]

DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[ 12]

DDR0_DQ[22]

DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[ 11]

DDR0_DQ[23]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT # DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[ 13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[ 2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[ 10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[ 1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[ 0]

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7]

DDR CH - A

PDG: DDR/ODT

2 OF 20

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52

AM70 AM69 AT69 AT70 AH66 AH65 AG69 AG70 BA64 AY64 AY60 BA60 AR66 AR65 AR61 AR60

AW50 AT52

AY67 AY68 BA67

AW67

M_A_A5 M_A_A9 M_A_A6 M_A_A8 M_A_A7

M_A_A12 M_A_A11

M_A_A13 M_A_A15 M_A_A14 M_A_A16

M_A_A2 M_A_A10

M_A_A1 M_A_A0 M_A_A3 M_A_A4

M_A_DQS_DN0 M_A_DQS_DP0 M_A_DQS_DN1 M_A_DQS_DP1 M_B_DQS_DN0 M_B_DQS_DP0 M_B_DQS_DN1 M_B_DQS_DP1 M_A_DQS_DN2 M_A_DQS_DP2 M_A_DQS_DN3 M_A_DQS_DP3 M_B_DQS_DN2 M_B_DQS_DP2 M_B_DQS_DN3 M_B_DQS_DP3

SM_PGCNTL

M_A_CLK#0 12 M_A_CLK0 12 M_A_CLK#1 12 M_A_CLK1 12

M_A_CKE0 1 2 M_A_CKE1 1 2

M_A_CS#0 12 M_A_CS#1 12 M_A_DIMA_ODT0 12 M_A_DIMA_ODT1 12

M_A_A5 12 M_A_A9 12 M_A_A6 12 M_A_A8 12 M_A_A7 12

M_A_BG0 12

M_A_A12 12

M_A_A11 12 M_A_ACT_N 12 M_A_BG1 12

M_A_A13 12

M_A_A15 12

M_A_A14 12

M_A_A16 12 M_A_BA0 12

M_A_A2 12

M_A_BA1 12

M_A_A10 12

M_A_A1 12 M_A_A0 12

M_A_A3 12 M_A_A4 12

M_A_DQS0 M_A_DQS1 M_B_DQS0 M_B_DQS1

M_A_DQS2

M_A_DQS3 M_B_DQS2 M_B_DQS3

M_A_ALERT_N 12 M_A_PARITY 12

V_SM_VREF_CN TA 12 V_SM_VREF_CN TB 13

SM_PGCNTL

M_A_DQ[32:39]

M_A_DQ[40:47]

M_B_DQ[32:39]

M_B_DQ[40:47]

M_A_DQ[48:55]

M_A_DQ[56:63]

M_B_DQ[48:55]

M_B_DQ[56:63]

3D3V_S5

12

DS

G

R507

R507 10KR2J-3-GP

10KR2J-3-GP

Q501

Q501 DMN5L06K-7-G P

DMN5L06K-7-G P

84.05067.031

Q502_G

M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_A_DQ3212 M_A_DQ3312 M_A_DQ3412 M_A_DQ3512 M_A_DQ3612 M_A_DQ3712 M_A_DQ3812 M_A_DQ3912 M_A_DQ4012 M_A_DQ4112 M_A_DQ4212 M_A_DQ4312 M_A_DQ4412 M_A_DQ4512 M_A_DQ4612 M_A_DQ4712 M_B_DQ3213 M_B_DQ3313 M_B_DQ3413 M_B_DQ3513 M_B_DQ3613 M_B_DQ3713 M_B_DQ3813 M_B_DQ3913 M_B_DQ4013 M_B_DQ4113 M_B_DQ4213 M_B_DQ4313 M_B_DQ4413 M_B_DQ4513 M_B_DQ4613 M_B_DQ4713 M_A_DQ4812 M_A_DQ4912 M_A_DQ5012 M_A_DQ5112 M_A_DQ5212 M_A_DQ5312 M_A_DQ5412 M_A_DQ5512 M_A_DQ5612 M_A_DQ5712 M_A_DQ5812 M_A_DQ5912 M_A_DQ6012 M_A_DQ6112 M_A_DQ6212 M_A_DQ6312 M_B_DQ4813 M_B_DQ4913 M_B_DQ5013 M_B_DQ5113 M_B_DQ5213 M_B_DQ5313 M_B_DQ5413 M_B_DQ5513 M_B_DQ5613 M_B_DQ5713 M_B_DQ5813 M_B_DQ5913 M_B_DQ6013 M_B_DQ6113 M_B_DQ6213 M_B_DQ6313

M_A_DQS_DN0 M_A_DQS_DN1 M_A_DQS_DN2 M_A_DQS_DN3 M_A_DQS_DN4 M_A_DQS_DN5 M_A_DQS_DN6 M_A_DQS_DN7

A A

5

4

M_A_DQS_DP0 M_A_DQS_DP1 M_A_DQS_DP2 M_A_DQS_DP3 M_A_DQS_DP4 M_A_DQS_DP5 M_A_DQS_DP6 M_A_DQS_DP7

3

M_A_DQS_DN[7 :0] 12 M_B_DQS_DN[7 :0] 13

M_A_DQS_DP[7:0] 12

M_B_DQS_DN0 M_B_DQS_DN1 M_B_DQS_DN2 M_B_DQS_DN3 M_B_DQS_DN4 M_B_DQS_DN5 M_B_DQS_DN6 M_B_DQS_DN7

M_B_DQS_DP0 M_B_DQS_DP1 M_B_DQS_DP2 M_B_DQS_DP3 M_B_DQS_DP4 M_B_DQS_DP5 M_B_DQS_DP6 M_B_DQS_DP7

2

M_B_DQS_DP[7:0] 13

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O .C.

Taipei Hsie n 221, Taiwan, R.O .C.

Title

Size Documen t Number Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O .C.

CPU_(DDR)

Vegas SKL/KBL-U

1

5 105Monday, June 27, 2016

A00

5

WWW.AliSaler.Com

Main Func = CPU

TP618TPAD14-OP-GP TP618TPAD14-OP-GP TP619TPAD14-OP-GP TP619TPAD14-OP-GP TP620TPAD14-OP-GP TP620TPAD14-OP-GP TP621TPAD14-OP-GP TP621TPAD14-OP-GP TP622TPAD14-OP-GP TP622TPAD14-OP-GP TP623TPAD14-OP-GP TP623TPAD14-OP-GP TP624TPAD14-OP-GP TP624TPAD14-OP-GP TP625TPAD14-OP-GP TP625TPAD14-OP-GP

D D

C C

PCH strap pin:

B B

CFG3

DY

12

R604

R604 1KR2J-1-GP

1KR2J-1-GP

TP626TPAD14-OP-GP TP626TPAD14-OP-GP TP627TPAD14-OP-GP TP627TPAD14-OP-GP TP628TPAD14-OP-GP TP628TPAD14-OP-GP TP629TPAD14-OP-GP TP629TPAD14-OP-GP TP630TPAD14-OP-GP TP630TPAD14-OP-GP TP631TPAD14-OP-GP TP631TPAD14-OP-GP TP632TPAD14-OP-GP TP632TPAD14-OP-GP TP633TPAD14-OP-GP TP633TPAD14-OP-GP

TP634TPAD14-OP-GP TP634TPAD14-OP-GP TP635TPAD14-OP-GP TP635TPAD14-OP-GP

TP636TPAD14-OP-GP TP636TPAD14-OP-GP TP637TPAD14-OP-GP TP637TPAD14-OP-GP

TP638TPAD14-OP-GP TP638TPAD14-OP-GP

TP601TPAD14-OP-GP TP601TPAD14-OP-GP TP602TPAD14-OP-GP TP602TPAD14-OP-GP

TP612TPAD14-OP-GP TP612TPAD14-OP-GP TP613TPAD14-OP-GP TP613TPAD14-OP-GP

[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

CFG[3]

CFG0

1

CFG1

1

CFG2

1

CFG3

1

CFG4

1

CFG5

1

CFG6

1

CFG7

1

CFG8

1

CFG9

1

CFG10

1

CFG11

1

CFG12

1

CFG13

1

CFG14

1

CFG15

1

CFG16

1

CFG17

1

CFG18

1

CFG19

1

CFG_RCOMP

R60149D9R2F-GP R60149D9R2F-GP

12

ITP_PMODE

1

RSVD_TP_BA70

1

RSVD_TP_BA68

1

RSVD_F65

1

RSVD_G65

1

0 : ENABLED SET DFX ENABLED BIT IN DEBUG INTERFACE MSR

4

CPU1S

E68

CFG[0]

B67

CFG[1]

D65

CFG[2]

D67

CFG[3]

E70

CFG[4]

C68

CFG[5]

D68

CFG[6]

C67

CFG[7]

F71

CFG[8]

G69

CFG[9]

F70

CFG[10]

G68

CFG[11]

H70

CFG[12]

G71

CFG[13]

H69

CFG[14]

G70

CFG[15]

E63

CFG[16]

F63

CFG[17]

E66

CFG[18]

F66

CFG[19]

E60

CFG_RCOMP

E8

ITP_PMODE

AY2

RSVD#AY2

AY1

RSVD#AY1

D1

RSVD#D1

D3

RSVD#D3

K46

RSVD#K46

K45

RSVD#K45

AL25

RSVD#AL25

AL27

RSVD#AL27

C71

RSVD#C71

B70

RSVD#B70

F60

RSVD#F60

A52

RSVD#A52

BA70

RSVD_TP#BA70

BA68

RSVD_TP#BA68

J71

RSVD#J71

J68

RSVD#J68

F65

VSS

G65

VSS

F61

RSVD#F61

E61

RSVD#E61

SKYLAKE-U-GP

071.SKYLA.000U

RESERVED SIGNALS-1

SKYLAKE_ULT

RSVD_TP_AW71 RSVD_TP_AW70

19 OF 20

RSVD_TP#BB68 RSVD_TP#BB69

RSVD_TP#AK13 RSVD_TP#AK12

RSVD#BB2 RSVD#BA3

TP5 TP6

RSVD#D5 RSVD#D4 RSVD#B2 RSVD#C2

RSVD#B3 RSVD#A3

RSVD#AW1

RSVD#E1 RSVD#E2

RSVD#BA4 RSVD#BB4

RSVD#A4 RSVD#C4

TP4

RSVD#A69 RSVD#B69

RSVD#AY3 RSVD#D71

RSVD#C70 RSVD#C54

RSVD#D54

TP1 TP2

VSS

ZVM#

RSVD_TP#AW71 RSVD_TP#AW70

MSM#

PROC_SELECT#

BB68 BB69

AK13 AK12

BB2 BA3

AU5 AT5

D5 D4 B2 C2

B3 A3

AW1 E1

E2 BA4

BB4 A4

C4 BB5 A69

B69 AY3 D71

C70 C54

D54 AY4

BB3 AY71

AR56 AW71

AW70 AP56

C64

3

RSVD_TP_BB68 RSVD_TP_BB69

TP4_BB5

TP1_AY4 TP2_BB3

VSS_AY71 ZVM#

RSVD_TP_AW71 RSVD_TP_AW70

MSM#

PROC_SELECT#

R602

1 2

0R0402-PAD

1 1

1

1 1

1

1 2

R603

100KR2J-1-GP

TP603 TPAD14-OP-GPTP603 TPAD14-OP-GP TP604 TPAD14-OP-GPTP604 TPAD14-OP-GP

TP609 TPAD14-OP-GPTP609 TPAD14-OP-GP

TP610 TPAD14-OP-GPTP610 TPAD14-OP-GP TP611 TPAD14-OP-GPTP611 TPAD14-OP-GP

ZVM# 40

TP614 TPAD14-OP-GPTP614 TPAD14-OP-GP TP615 TPAD14-OP-GPTP615 TPAD14-OP-GP

TP617 TPAD14-OP-GPTP617 TPAD14-OP-GP

#54469 CRB.

2

+VCCST_CPU

1

1 : DISABLED

CFG4

12

R605

R605 1KR2J-1-GP

1KR2J-1-GP

(#543016)

DISPLAY PORT PRESENCE STRAP

0 : ENABLED

CFG[4]

An external Display Port device is connected to the Embedded Display Port.

1 : DISABLED (Default) No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.

CFG TERMINATIONS

20140807 david

A A

SKL(#543016): Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*

5

#544669 Rev0.52 (CRB)

4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(RESERVED)

Vegas SKL/KBL-U

6 105Monday, June 27, 2016

1

A00

Main Func = CPU

5

CPU1L

A30 A34 A39

A44 AK33 AK35 AK37 AK38 AK40

AL33 AL37

AL40 AM32 AM33 AM35 AM37 AM38

G30

K32 AK32 AB62

P62

V62

H63

G61 AC63

AE63 AE62

AG62

AL63 AJ62

+V_EOPIO_VR

1 2

23e

1 2

23e

CPU1L

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

RSVD_K32

RSVD#K32

RSVD_AK32

RSVD#AK32 VCCOPC

VCCOPC VCCOPC

VCC_OPC_1P8 VCC_OPC_1P8 VCCOPC_SENSE

VSSOPC_SENSE VCCEOPIO

VCCEOPIO VCCEOPIO_SENSE

VSSEOPIO_SENSE

SKYLAKE-U-GP

071.SKYLA.000U

R707

100R2F-L1-GP- U

VCCSENSE_E OPIO_VR VSSSENSE_EOPIO_V R

R708

100R2F-L1-GP- U

CPU POWER 1 OF 4

SKYLAKE_ULT

VCC_CORE

D D

+VCCCOR EG0

TP701TPA D14-OP-GP TP701TPAD14-OP-G P

1

+VCCCOR EG1

TP702TPA D14-OP-GP TP702TPAD14-OP-G P

1

+V_EDRAM_VR

R704

1 2

0R2J-2-GP

100R2F-L1-GP- U

1 2

23e

1 2

23e

R706

R706 100R2F-L1-GP- U

100R2F-L1-GP- U

3A

23e

3A

R701

VCCSENSE_E DRAM_VR VSSSENSE_EDR AM_VR

VCC_EDRA M_FUSEPRG VCCSENSE_E DRAM_VR

VSSSENSE_EDR AM_VR

+V_EOPIO_VR

VCCSENSE_E OPIO_VR VSSSENSE_EOPIO_V R

RN701 RN702 change to Single for cost change 2/26

140mA

+V1.8S_EDRAM

+V_EDRAM_VR

12

2

1

1 C70

C70

C C

+V_EOPIO_VR

3

3 C70

C70

2

23e

C70

SC10U6D3V2MX-GP-U

12

23e

SC10U6D3V2MX-GP-U

+V_EDRAM_VR

12

4

23e

C70

SC10U6D3V2MX-GP-U

Layout Note: The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch). Route the Alert signal between the Clock and the Data signals.

12 OF 20

VCC_SENSE VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG

4

+VCCGT

VCC_CORE

G32

VCC

G33

VCC

G35

VCC

G37

VCC

G38

VCC

G40

VCC

G42

VCC

J30

VCC

J33

VCC

J37

VCC

J40

VCC

K33

VCC

K35

VCC

K37

VCC

K38

VCC

K40

VCC

K42

VCC

K43

VCC

E32 E33

B63 A63 D64

G20

H_CPU_SVIDALR T# H_CPU_SVIDC LK H_CPU_SVIDD AT

+VCCFUSE PRG

VCC_CORE

+VCCGT

VCC_SENSE 46 VSS_SENSE 46

R703

1 2

0R0402-PAD

100R2F-L1-GP- U

R710

1 2 1 2

R711

100R2F-L1-GP- U

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Length match<25mil

100R2F-L1-GP- U

R712

1 2 1 2

R713

100R2F-L1-GP- U

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Length match<25mil

VCCGT_SEN SE46 VSSGT_SENSE46

+VCCSTG

VCC_SENSE 46

VSS_SENSE 46

VCCGT_SEN SE 46

VSSGT_SENSE 46

3

CPU1M

A48

VCCGT

A53

VCCGT

A58

VCCGT

A62

VCCGT

A66

VCCGT

AA63

VCCGT

AA64

VCCGT

AA66

VCCGT

AA67

VCCGT

AA69

VCCGT

AA70

VCCGT

AA71

VCCGT

AC64

VCCGT

AC65

VCCGT

AC66

VCCGT

AC67

VCCGT

AC68

VCCGT

AC69

VCCGT

AC70

VCCGT

AC71

VCCGT

J43

VCCGT

J45

VCCGT

J46

VCCGT

J48

VCCGT

J50

VCCGT

J52

VCCGT

J53

VCCGT

J55

VCCGT

J56

VCCGT

J58

VCCGT

J60

VCCGT

K48

VCCGT

K50

VCCGT

K52

VCCGT

K53

VCCGT

K55

VCCGT

K56

VCCGT

K58

VCCGT

K60

VCCGT

L62

VCCGT

L63

VCCGT

L64

VCCGT

L65

VCCGT

L66

VCCGT

L67

VCCGT

L68

VCCGT

L69

VCCGT

L70

VCCGT

L71

VCCGT

M62

VCCGT

N63

VCCGT

N64

VCCGT

N66

VCCGT

N67

VCCGT

N69

VCCGT

J70

VCCGT_SENSE

J69

VSSGT_SENSE

SKYLAKE-U-GP

071.SKYLA.000U

SVID_543016:

CPU POWER 2 OF 4

SKYLAKE_ULT

13 OF 20

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX

VCCGTX_SENSE VSSGTX_SENSE

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

+VCCGT

for 2+3E

12

DY

2

C722

C722 SC1U10V2KX-1G P

SC1U10V2KX-1G P

1D2V_S3+VDDQ_CPU_CLK

12

DY

R705

1 2

0R0603-PAD

12

DY

12

DY

12

DY

12

DY

C719

C719 SC1U10V2KX-1G P

SC1U10V2KX-1G P

+VDDQ_CPU _CLK1D2V_S3

C715SC10U6D3V3MX- GPDYC715SC10U6D3V3MX- GP

+VCCST_CP U

C716SC1U10V2KX-1G PDYC716SC1U10V2KX-1G P

+VCCSTG

C717SC1U10V2KX-1G PDYC717SC1U10V2KX-1G P

1D2V_S3

C718SCD1U16V2KX- 3GPDYC718SCD1U16V2KX- 3GP

+V1.00U_CPU

12

1

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

VCCIO_VR_FB VSSIO_VR_FB

+VCCIO

VCCIO_VR_FB VSSIO_VR_FB

+VCCIO(ICCMAX.=2.73A

+VCCSA

100R2F-L1-GP- U

R714

1 2 1 2

R715

100R2F-L1-GP- U

VSSSA_SENSE 46 VCCSA_SENS E 46

+VCCIO

CPU1N

CPU POWER 3 OF 4

AU23

VDDQ

AU28

VDDQ

AU35

VDDQ

AU42

VDDQ

BB23

VDDQ

BB32

VDDQ

BB41

VDDQ

BB47

VDDQ

BB51

VDDQ

AM40

C721

SCD1U16V2KX-3GP

0.12 A

A18 A22

AL23

K20 K21

VDDQC VCCST VCCSTG VCCPLL_OC VCCPLL

VCCPLL

SKYLAKE-U-GP

071.SKYLA.000U

0.04 A

12

C720

DY

SCD1U16V2KX-3GP

SKYLAKE_ULT

14 OF 20

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Length match<25mil

+VCCSA

100R2F-L1-GP- U

VCCSA_SENS E VSSSA_SENSE

100R2F-L1-GP- U

R716

1 2 1 2

R717

100R2F-L1-GP- U

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Length match<25mil

SVID DATA

H_CPU_SVIDD AT

+VCCST_CP U

12

R726

R726 100R2F-L1-GP- U

100R2F-L1-GP- U

#544669

R709 0R0402-PADR709 0R0402-PAD

1 2

VR_SVID_DATA 46

B B

CLOSE TO CPU

+VCCST_CP U

R723

R723 54D9R2F-L1-G P

54D9R2F-L1-G P

#544669 CLOSE TO CPU

#544669 CLOSE TO VR

VR_SVID_ALERT# 46

VR_SVID_CLK 46

4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O .C.

Taipei Hsie n 221, Taiwan, R.O .C.

Title

Size Documen t Number Rev

Size Documen t Number Rev A2

A2

Monday, June 27, 2016

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O .C.

CPU(VCC_CORE)

Vegas SKL/KBL-U

1

7 105

A00

12

+VCCST_CP U

12

DY

R727

R727 56R2J-4-GP

56R2J-4-GP

SVID CLOCK

H_CPU_SVIDC LK

A A

H_CPU_SVIDALR T#

5

1 2

0R0402-PAD

R728

220R2J-L2-GP

R732

5

WWW.AliSaler.Com

4

3

2

1

Main Func = CPU

D D

CPU1A

SKYLAKE_ULT

HDMI_DATA2#57

HDMI_DATA257

CPU_DP1_CTRL_CLK57

CPU_DP1_CTRL_DATA57

HDMI_DATA1#57

HDMI_DATA157

HDMI_DATA0#57

HDMI_DATA057

HDMI_CLK#57

HDMI_CLK57

TPAD14-OP-GP

TP802

CPU_DP2_CTRL_CLK CPU_DP2_CTRL_DATA

DDPD_CTRLDATA

1

EDP_COMP

HDMI

PCH_DPC_N056

+VCCIO

PCH_DPC_P056

PCH_DPC_N156

PCH_DPC_P156

R801

1 2

24D9R2F-L-GP

DP to VGA

3D3V_S0

RN801

3D3V_S0

RN801

2 3 1

SRN2K2J-1-GP

RN803

2 3 1

Vegas

SRN2K2J-1-GP

CPU_DP1_CTRL_CLK CPU_DP1_CTRL_DATA

4

CPU_DP2_CTRL_DATA CPU_DP2_CTRL_CLK

4

HDMI

Check

C C

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22

N12

GPP_E23

E52

EDP_RCOMP

SKYLAKE-U-GP

071.SKYLA.000U

SKYLAKE_ULT

DDI

DISPLAY SIDEBANDS

Strap

EDP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

(#543016) The Skylake U/Y processor supports only two DDI ports - Port 1 and Port 2.

1 OF 20

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP

RSVD#G46

RSVD#F46

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52 G50

F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

EDP_DISP_UTIL

eDP_TX_CPU_N0 55 eDP_TX_CPU_P0 55 eDP_TX_CPU_N1 55 eDP_TX_CPU_P1 55

eDP_AUX_CPU_N 55 eDP_AUX_CPU_P 55

1

TP801 TPAD14-OP-GPTP801 TPAD14-OP-GP

PCH_DPC_AUXN 56 PCH_DPC_AUXP 56

CPU_DP1_HPD 57 CPU_DP2_HPD 56 SIO_EXT_SMI#_R 24

EDP_HPD 55

L_BKLT_EN 24 L_BKLT_CTRL 55 EDP_VDD_EN 55

(#543016) eDP_RCOMP Guideline

Signal Trace

Width

eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1%

B B

(#543016) DDI Disabling and Termination Guidelines

Port Strap Enable Port Disable Port

Port 1

Port 2

DDPB_CTRLDATA

DDPC_CTRLDATA

Isolation Spacing

PU to 3.3 V with 2.2-k ±5% resistor

Resistor Value

Length

Max = 100 mils

NC

Strap pin:

Port B / Port C Detected

DDPB_CTRLDATA

DDPC_CTRLDATA

Sampled at rising edge of PCH_PWROK

0 = Port B is not detected. 1 = Port B is detected.

*

0 = Port C is not detected. 1 = Port C is detected.

*

SIO_EXT_SMI#_R

Vegas

12

R806

R806 100KR2J-1-GP

100KR2J-1-GP

1 2

3D3V_S0

R802 10KR2J-3-GPR802 10KR2J-3-GP

CPU_DP2_HPD

These two signals have weak internal pull-down.

Design Guideline: Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor.

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(DISPLAY)

Vegas SKL/KBL-U

8 105Monday, June 27, 2016

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

(Reserved)

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Vegas SKL/KBL-U

9 105Thursday, June 16, 2016

1

A00

5

WWW.AliSaler.Com

4

3

2

1

Main Func = CPU

(#543016 PDG)

CORE

U-line 23e 28W IccMax current-10ms max = 34 A

D D

VCC_CORE

PC1007

PC1009

12

PC1016

12

PC1027

12

PC1009

PC1008

12

SC22U6D3V3MX-1-GP

PC1020

PC1018

12

PC1029

12

PC1020

PC1019

12

SC22U6D3V3MX-1-GP

22U 0603 x 22

PC1030

12

SC22U6D3V3MX-1-GP

PC1017

12

SC22U6D3V3MX-1-GP

PC1028

12

SC22U6D3V3MX-1-GP

PC1006

PC1004

12

PC1013

12

PC1024

12

PC1006

PC1005

12

SC22U6D3V3MX-1-GP

PC1014

PC1015

12

SC22U6D3V3MX-1-GP

PC1026

PC1025

12

SC22U6D3V3MX-1-GP

PC1002

PC1003

PC1001

12

SC22U6D3

V3MX-1-GP

PC1012

PC1010

PC1011

12

SC22U6D3

V3MX-1-GP

PC1023

PC1021

PC1022

12

C C

12

SC22U6D3

V3MX-1-GP

1D2V_S3

PC1055SC10U6D3V3MX-GP PC1 055SC10U6D3V3MX-GP

PC1062SC22U6D3V3MX-1-GPDYPC1062SC22U6D3V3MX-1-GP

DY

10U 0603 x 4

12

PC1057SC10U6D3V3MX-GP PC1 057SC10U6D3V3MX-GP

PC1056SC4D7P50V2BN-GP PC1056SC4D7P50V2B N-GP

PC1058SC10U6D3V3MX-GP PC1 058SC10U6D3V3MX-GP

PC1064

12

PC1063SC22U6D3V3MX-1-GPDYPC1063SC22U6D3V3MX-1-GP

DY

SC22U6D3V5MX-2GP

12

PC1059SC4D7P50V2BN-GPDYPC1059SC4D7P50V2BN-GP

DY

12

PC1060SC4D7P50V2BN-GPDYPC1060SC4D7P50V2BN-GP

PC1061SC4D7P50V2BN-GPDYPC1061SC4D7P50V2BN-GP

DY

+VCCIO

1D0V_S5

+VCCIO(ICCMAX.=2.73A)

12

PC1037S

PC1036S

PC1035S

C22U6D3V3MX-1-GP

B B

A A

SLICED GT

U-line 23e 28W IccMax current-10ms max[A] = 67 A

+VCCGT

PC1031

12

SC22U6D3

V3MX-1-GP

PC1044

12

SC22U6D3

V3MX-1-GP

PC1082

12

SC22U6D3

V3MX-1-GP

DY

PC1032

12

PC1069

12

PC1083

12

PC1038

PC1039

12

V5MX-2GP

SC22U6D3

SC22U6D3V5MX-2GP

PC1033

PC1041

PC1034

PC1042

12

PC1071

12

PC1085

12

PC1042

12

SC22U6D3V3MX-1-GP

SC22U6D3

V3MX-1-GP

PC1073

PC1072

12

SC22U6D3

SC22U6D3V3MX-1-GP

DY

V3MX-1-GP

PC1086

PC1087

12

SC22U6D3V3MX-1-GP

SC22U6D3

V3MX-1-GP

12

SC22U6D3

V3MX-1-GP

PC1070

12

SC22U6D3

DY

V3MX-1-GP

PC1084

12

SC22U6D3

V3MX-1-GP

5

SC22U6D3V3MX-1-GP

PC1043

12

PC1074

12

PC1088

12

SC22U6D3V3MX-1-GP

VCCSA

+VCCSA

PC1045

12

DY

PC1076

PC1075

12

SC22U6D3V3MX-1-GP

PC1089

PC1090

12

SC22U6D3V3MX-1-GP

DY

SC22U6D3V3MX-1-GP

PC1077

12

PC1091

12

DY

PC1046

12

SC22U6D3V3MX-1-GP

PC1078

12

PC1092

12

PC1054

PC1047

PC1048

12

SC22U6D3V3MX-1-GP

PC1079

PC1080

12

SC22U6D3V3MX-1-GP

DY

SC22U6D3V3MX-1-GP

PC1081

12

PC1049

12

SC22U6D3V3MX-1-GP

PC1050

PC1051

PC1052

12

SC22U6D3V3MX-1-GP

PC1052

12

SC22U6D3V3MX-1-GP

DY

PC1054

PC1053

12

SC22U6D3V3MX-1-GP

DY

PC1066

PC1065

12

SC22U6D3V3MX-1-GP

DY

PC1068

PC1067

12

SC22U6D3V3MX-1-GP

DY

PC1098

PC1097

12

SC22U6D3V3MX-1-GP

DY

22U 0603 x 8

22U 0603 x28

PC1094

PC1096

PC1093

12

SC22U6D3V3MX-1-GP

DY

PC1096

PC1095

12

SC22U6D3V3MX-1-GP

DY

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O .C.

Taipei Hsie n 221, Taiwan, R.O .C.

Title

Size Documen t Number Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O .C.

CPU_(Power CAP1)

Vegas SKL/KBL-U

1

10 105Thursday, June 16, 2016

A00

5

Main Func = CPU

4

3

2

1

PCH DERIVED RAILS

1D0V_S5

D D

3D3V_S5_PCH +V3.3A_SIP

C C

R1117

1 2

0R0603-PAD-2-GP-U

R1101

0R1206-PAD

1 2

R1110

1 2

0R0603-PAD-2-GP-U

+V1.00A_SIP

C1108

12

+VCCPRIM_CORE

C1104

12

SC22U6D3V3MX-1-GP

+VCCGT

DY

12

C1136

SC1U10V2KX-1GP

1U 0402 x 6

12

C1138

DY

SC1U10V2KX-1GP

DY

12

C1147

12

C1148

SC1U10V2KX-1GP

DY

C1149

C1150

SC1U10V2KX-1GP

12

VCCIOUNSLICED GT

+VCCIO

+VCCIO(ICCMAX.=2.73A)

12

C1152

C1151

DY

SC1U10V2KX-1GP

12

C1153

12

C1154

SC1U10V2KX-1GP

+VCCMPHYGTAON_1P0(ICCMAX.=2.12A)

1D8V_S5 +V1.8A_SIP

R1139

0R0603-PAD-2-GP-U

B B

12

SC22U6D3V3MX-1-GP

C1106

12

SC22U6D3V3MX-1-GP

SC1U10V2KX-1GP

C1182

C1174

12

+VCCMPHYGTAON_1P0_LS_SIP +VCCMPHYGTAON_1P0_LS_SIP+VCCMPHYGTAON_1P0_LS_SIP+VCCMPHYGTAON_1P0_LS_SIP

SC1U10V2KX-1GP

C1173

C1180

12

SC22U6D3V3MX-1-GP

SC1U10V2KX-1GP

C1184

12

SC1U10V2KX-1GP

C1172

12

C1176

SC10U6D3V3MX-GP

SC1U10V2KX-1GP

C1175

12

Layout Note:

1uF:

C1174 near N15

C1180 near K15

C1173 near AF20

C1172 near N18

C1175 near AB19

22uF :

C1182 C1184 near N15

10uF:

C1176 near N15

+VCCPRIM_CORE

3

+V3.3A_SIP

12

C1183

SC10U6D3V3MX-GP

12

PC1105

PC1106

SC22U6D3V3MX-1-GP

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(Power CAP2)

Size Document Number Rev

A3

Date: Sheet of

CPU_(Power CAP2)

Vegas SKL/KBL-U

Taipei Hsien 221, Taiwan, R.O.C.

11 105Friday, June 24, 2016

1

A00

VCC_CORE

12

C1101

SC1U10V2KX-1GP

A A

U-line 23e 28W IccMax current-10ms max = 34 A

5

4

12

C1102

SC1U10V2KX-1GP

1U 0402 x 5

12

C1116

C1103

SC1U10V2KX-1GP

12

C1117

SC1U10V2KX-1GP

1D2V_S3

WWW.AliSaler.Com

DDR4_DR AMRST#

12

ED1217

ED1217 AZ5725-01FDR 7G-GP

AZ5725-01FDR 7G-GP

5

1 2

DY

R1215 240R2F-1-GP

DM1A

SA0_CHA_DIM0 SA1_CHA_DIM0 SA2_CHA_DIM0

TS#_DIMM0_1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10/AP

120

A11

119

A12

158

A13

151

WE#/A14

156

CAS#/A15

152

RAS#/A16

150

BA0

145

BA1

115

BG0

113

BG1

92

CB0/NC

91

CB1/NC

101

CB2/NC

105

CB3/NC

88

CB4/NC

87

CB5/NC

100

CB6/NC

104

CB7/NC

137

CK0_T

139

CK0_C

138

CK1_T/NF

140

CK1_C/NF

109

CKE0

110

CKE1

149

CS0#

157

CS1#

162

C0/CS2#/NC

165

C1/CS3#/NC

155

ODT0

161

ODT1

256

SA0

260

SA1

166

SA2

254

SDA

253

SCL

108

RESET#

114

ACT#

116

ALERT#

134

EVENT#/NF

143

PARITY

164

VREFCA

DDR4-260P-24-GP

062.10011.00U1

M_A_A05 M_A_A15 M_A_A25 M_A_A35 M_A_A45 M_A_A55 M_A_A65 M_A_A75 M_A_A85 M_A_A95 M_A_A105 M_A_A115 M_A_A125 M_A_A135 M_A_A145 M_A_A155 M_A_A165

M_A_BA05

M_A_BA15

M_A_BG05

M_A_BG15

M_A_CLK05

M_A_CLK#05

M_A_CLK15

M_A_CLK#15

M_A_CKE05 M_A_CKE15

M_A_CS#05 M_A_CS#15

M_A_DIMA_ODT05 M_A_DIMA_ODT15

PCH_SMBDAT A13,18,56,65,67

PCH_SMBCLK13,18,56,65,67

DDR4_DR AMRST#5,13 M_A_ACT_N5 M_A_ALERT_N5

M_A_PARITY5

M_VREF_CA_D IMMA

12

C1229

SCD1U16V2KX-3GP

Main Func = DDR4 SODIMM

D D

C C

Layout note: closed to Dimm

1D2V_S3

RN1201

1

4

2 3

SRN1KJ-7-G P

B B

M_VREF_CA_D IMMA

R1206

1 2

2R2F-GP

12

C1222

SCD022U16V2KX -3GP

+V_VREF_PATH 1

12

R1209

24D9R2F-L-G P

V_SM_VREF_CN TA 5

1 OF 4

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

4

8 7 20 21 4 3 16 17 28 29 41 42 24 25 38 37 50 49 62 63 46 45 58 59 70 71 83 84 66 67 79 80 174 173 187 186 170 169 183 182 195 194 207 208 191 190 203 204 216 215 228 229 211 212 224 225 237 236 249 250 232 233 245 246

DDR4 SWAP 0212

3D3V_S0

M_A_DQ0 5 M_A_DQ1 5 M_A_DQ2 5 M_A_DQ3 5 M_A_DQ4 5 M_A_DQ5 5 M_A_DQ6 5 M_A_DQ7 5 M_A_DQ8 5 M_A_DQ9 5 M_A_DQ10 5 M_A_DQ11 5 M_A_DQ12 5 M_A_DQ13 5 M_A_DQ14 5 M_A_DQ15 5 M_A_DQ16 5 M_A_DQ17 5 M_A_DQ18 5 M_A_DQ19 5 M_A_DQ20 5 M_A_DQ21 5 M_A_DQ22 5 M_A_DQ23 5 M_A_DQ24 5 M_A_DQ25 5 M_A_DQ26 5 M_A_DQ27 5 M_A_DQ28 5 M_A_DQ29 5 M_A_DQ30 5 M_A_DQ31 5 M_A_DQ32 5 M_A_DQ33 5 M_A_DQ34 5 M_A_DQ35 5 M_A_DQ36 5 M_A_DQ37 5 M_A_DQ38 5 M_A_DQ39 5 M_A_DQ40 5 M_A_DQ41 5 M_A_DQ42 5 M_A_DQ43 5 M_A_DQ44 5 M_A_DQ45 5 M_A_DQ46 5 M_A_DQ47 5 M_A_DQ48 5 M_A_DQ49 5 M_A_DQ50 5 M_A_DQ51 5 M_A_DQ52 5 M_A_DQ53 5 M_A_DQ54 5 M_A_DQ55 5 M_A_DQ56 5 M_A_DQ57 5 M_A_DQ58 5 M_A_DQ59 5 M_A_DQ60 5 M_A_DQ61 5 M_A_DQ62 5 M_A_DQ63 5

󴴨󴴨󴴨󴴨sw󳠃󳠃󳠃󳠃󴧖󴧖󴧖󴧖

R1204 10KR2F-L1-G P

12

DY

0R0402-PAD

12

R1208 10KR2F-L1-G P

12

DY

12

R1211 10KR2F-L1-G P

12

DY

12

1D2V_S3

R1205

0R0402-PAD

R1210

0R0402-PAD

R1212

DM1B

DM8#/DBI#/NC

DDR4-260P-24-GP

SA0_CHA_DIM0

SA1_CHA_DIM0

SA2_CHA_DIM0

2 OF 4

DQS0_C DQS0_T DQS1_C DQS1_T DQS2_C DQS2_T DQS3_C DQS3_T DQS4_C DQS4_T DQS5_C DQS5_T DQS6_C DQS6_T DQS7_C DQS7_T DQS8_C DQS8_T

DM0#/DBI0#

DM1#/DBI# DM2#/DBI2# DM3#/DBI3# DM4#/DBI4# DM5#/DBI5# DM6#/DBI6# DM7#/DBI7#

111 112 117 118 123 124 129 130 135 136 141 142 147 148 153 154 159 160 163

11 13 32 34 53 55 74 76 177 179 198 200 219 221 240 242 95 97

12 33 54 75 178 199 220 241 96

DM1C

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

DDR4-260P-24-GP

1D2V_S3

M_A_DQS_DN0 M_A_DQS_DP0 M_A_DQS_DN1 M_A_DQS_DP1 M_A_DQS_DN2 M_A_DQS_DP2 M_A_DQS_DN3 M_A_DQS_DP3 M_A_DQS_DN4 M_A_DQS_DP4 M_A_DQS_DN5 M_A_DQS_DP5 M_A_DQS_DN6 M_A_DQS_DP6 M_A_DQS_DN7 M_A_DQS_DP7

3 OF 4

VDDSPD

VPP VPP

VTT

261 262

NP1 NP2

12

C1208

SC10U6D3V3MX-GP

12

C1214

SC1U10V2KX-1GP

12

C1202

12

C1215

3

DM1D

VSS1VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

1D2V_S3

3D3V_S0

255

257 259

258

261 262

NP1 NP2

0D6V_S0

2D5V_S3

12

C1228

R1216

SCD1U16V2KX-L-GP

SC2D2U10V3KX-L-GP

DY

39 40 43 44 47 48 51 52 56 57 60 61 64 65 68 69 72 73 77 78 81 82 85 86 89 90 93 94 98

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

DDR4-260P-24-GP

4 OF 4

2

99 102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

1

UN 0225

0D6V_S0

12

C1226

C1225

SC1U10V2KX-1GP

12

C1204

12

C1206

C1210

C1205

SC10U6D3V3MX-GP

DY

12

C1203

C1209

SC10U6D3V3MX-GP

DY

12

C1223

SC4D7U6D3V2MX-1-GP

DY

0D6V_S00D6V_S0

12

C1230

SC4D7U6D3V2MX-1-GP

DY

12

C1227

C1224

SC4D7U6D3V2MX-1-GP

DY

for placement modifu 2015/10/19

2D5V_S3

12

C1218

12

C1220

C1219

C1221

SC1U10V2KX-1GP

DY

M_A_DQS_DN[7 :0] 5

M_A_DQS_DP[7:0] 5

12

C1211

DY

12

C1231

C1232

SC4D7U6D3V2MX-1-GP

DY

12

C1212

12

C1213

C1207

SC1U10V2KX-L1-GP

SC1U10V2KX-1GP

DY

SC4D7U6D3V2MX-1-GP

12

C1217

C1216

SC1U10V2KX-1GP

DY

M_A_DQS_DN0 M_A_DQS_DN1 M_A_DQS_DN2 M_A_DQS_DN3 M_A_DQS_DN4 M_A_DQS_DN5 M_A_DQS_DN6 M_A_DQS_DN7

M_A_DQS_DP0 M_A_DQS_DP1 M_A_DQS_DP2 M_A_DQS_DP3 M_A_DQS_DP4 M_A_DQS_DP5 M_A_DQS_DP6 M_A_DQS_DP7

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O .C.

Taipei Hsie n 221, Taiwan, R.O .C.

Vegas SKL/KBL-U

1

12 106

A00

5

Title

DDR3-SODIMM1

Size Documen t Number Rev

Size Documen t Number Rev A2

A2

Monday, June 27, 2016

Date: Sheet of

4

3

2

Date: Sheet of

5

4

3

2

1

Main Func = DDR4 SODIMM

DM2A

SA0_CHB_DIM0 SA1_CHB_DIM0 SA2_CHB_DIM0

TS#_DIMM1_1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10/AP

120

A11

119

A12

158

A13

151

WE#/A14

156

CAS#/A15

152

RAS#/A16

150

BA0

145

BA1

115

BG0

113

BG1

92

CB0/NC

91

CB1/NC

101

CB2/NC

105

CB3/NC

88

CB4/NC

87

CB5/NC

100

CB6/NC

104

CB7/NC

137

CK0_T

139

CK0_C

138

CK1_T/NF

140

CK1_C/NF

109

CKE0

110

CKE1

149

CS0#

157

CS1#

162

C0/CS2#/NC

165

C1/CS3#/NC

155

ODT0

161

ODT1

256

SA0

260

SA1

166

SA2

254

SDA

253

SCL

108

RESET#

114

ACT#

116

ALERT#

134

EVENT#/NF

143

PARITY

164

VREFCA

DDR4-260P-23-GP

062.10011.00T1

M_B_A05 M_B_A15 M_B_A25 M_B_A35 M_B_A45 M_B_A55 M_B_A65 M_B_A75 M_B_A85 M_B_A95 M_B_A105 M_B_A115 M_B_A125

D D

C C

1D2V_S3

DDR4_DR AMRST#

12

ED1302

ED1302 AZ5725-01FDR 7G-GP

AZ5725-01FDR 7G-GP

DY

PCH_SMBDAT A12,18,56,65,67

R1312

1 2

M_B_A135 M_B_A145 M_B_A155 M_B_A165

M_B_BA05

M_B_BA15

M_B_BG05

M_B_BG15

M_B_CLK05

M_B_CLK#05

M_B_CLK15

M_B_CLK#15

M_B_CKE05 M_B_CKE15

M_B_CS#05 M_B_CS#15

M_B_DIMB_ODT05 M_B_DIMB_ODT15

PCH_SMBCLK12,18,56,65,67

DDR4_DR AMRST#5,12 M_B_ACT_N5 M_B_ALERT_N5

240R2F-1-GP

DY

M_B_PARITY5

M_VREF_CA_D IMMB

12

C1301

SCD1U16V2KX-3GP

Layout note: closed to Dimm

1D2V_S3

B B

RN1301

1 2 3

SRN1KJ-7-G P

4

M_VREF_CA_D IMMB

R1305

1 2

2R2F-GP

12

C1323

SCD022U16V2KX -3GP

+V_VREF_PATH 2

12

R1309

24D9R2F-L-G P

1 OF 4

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

V_SM_VREF_CN TB 5

SA0_CHB_DIM0

SA1_CHB_DIM0

SA2_CHB_DIM0

1D2V_S3

111 112 117 118 123 124 129 130 135 136 141 142 147 148 153 154 159 160 163

DM2B

DM8#/DBI#/NC

DDR4-260P-23-GP

12

C1303

SC10U6D3V3MX-GP

DY

12

C1315

SC1U10V2KX-1GP

DY

DM2C

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

DDR4-260P-23-GP

2 OF 4

DQS0_C DQS0_T DQS1_C DQS1_T DQS2_C DQS2_T DQS3_C DQS3_T DQS4_C DQS4_T DQS5_C DQS5_T DQS6_C DQS6_T DQS7_C DQS7_T DQS8_C DQS8_T

DM0#/DBI0#

DM1#/DBI# DM2#/DBI2# DM3#/DBI3# DM4#/DBI4# DM5#/DBI5# DM6#/DBI6# DM7#/DBI7#

12

C1304

SC10U6D3V3MX-GP

DY

12

C1316

SC1U10V2KX-1GP

12

C1305

12

C1317

11 13 32 34 53 55 74 76 177 179 198 200 219 221 240 242 95 97

12 33 54 75 178 199 220 241 96

SC10U6D3V3MX-GP

SC1U10V2KX-1GP

3 OF 4

VDDSPD

VPP VPP

VTT

261 262

NP1 NP2

M_B_DQS_DN1 M_B_DQS_DP1 M_B_DQS_DN0 M_B_DQS_DP0 M_B_DQS_DN2 M_B_DQS_DP2 M_B_DQS_DN3 M_B_DQS_DP3 M_B_DQS_DN4 M_B_DQS_DP4 M_B_DQS_DN5 M_B_DQS_DP5 M_B_DQS_DN6 M_B_DQS_DP6 M_B_DQS_DN7 M_B_DQS_DP7

12

C1306

DY

12

C1318

DY

255

2D5V_S3 257 259

0D6V_S0 258

261 262

NP1 NP2

M_B_DQS_DN1 5 M_B_DQS_DP1 5 M_B_DQS_DN0 5 M_B_DQS_DP0 5 M_B_DQS_DN2 5 M_B_DQS_DP2 5 M_B_DQS_DN3 5 M_B_DQS_DP3 5 M_B_DQS_DN4 5 M_B_DQS_DP4 5 M_B_DQS_DN5 5 M_B_DQS_DP5 5 M_B_DQS_DN6 5 M_B_DQS_DP6 5 M_B_DQS_DN7 5 M_B_DQS_DP7 5

1D2V_S3

12

C1307

C1308

C1309

SC10U6D3V3MX-GP

12

C1319

SC1U10V2KX-1GP

SC10U6D3V3MX-GP

DY

12

C1320

C1321

SC1U10V2KX-1GP

DY

8

DQ0

7

DQ1

20

DQ2

21

DQ3

4

DQ4

3

DQ5

16

DQ6

17

DQ7

28

DQ8

29

DQ9

41 42 24 25 38 37 50 49 62 63 46 45 58 59 70 71 83 84 66 67 79 80 174 173 187 186 170 169 183 182 195 194 207 208 191 190 203 204 216 215 228 229 211 212 224 225 237 236 249 250 232 233 245 246

M_B_DQ8 5

M_B_DQ9 5 M_B_DQ10 5 M_B_DQ11 5 M_B_DQ12 5 M_B_DQ13 5 M_B_DQ14 5 M_B_DQ15 5

M_B_DQ0 5

M_B_DQ1 5

M_B_DQ2 5

M_B_DQ3 5

M_B_DQ4 5

M_B_DQ5 5

M_B_DQ6 5

M_B_DQ7 5 M_B_DQ16 5 M_B_DQ17 5 M_B_DQ18 5 M_B_DQ19 5 M_B_DQ20 5 M_B_DQ21 5 M_B_DQ22 5 M_B_DQ23 5 M_B_DQ24 5 M_B_DQ25 5 M_B_DQ26 5 M_B_DQ27 5 M_B_DQ28 5 M_B_DQ29 5 M_B_DQ30 5 M_B_DQ31 5 M_B_DQ32 5 M_B_DQ33 5 M_B_DQ34 5 M_B_DQ35 5 M_B_DQ36 5 M_B_DQ37 5 M_B_DQ38 5 M_B_DQ39 5 M_B_DQ40 5 M_B_DQ41 5 M_B_DQ42 5 M_B_DQ43 5 M_B_DQ44 5 M_B_DQ45 5 M_B_DQ46 5 M_B_DQ47 5 M_B_DQ48 5 M_B_DQ49 5 M_B_DQ50 5 M_B_DQ51 5 M_B_DQ52 5 M_B_DQ53 5 M_B_DQ54 5 M_B_DQ55 5 M_B_DQ56 5 M_B_DQ57 5 M_B_DQ58 5 M_B_DQ59 5 M_B_DQ60 5 M_B_DQ61 5 M_B_DQ62 5 M_B_DQ63 5

DDR4 SWAP 0212

3D3V_S0

󴴨󴴨󴴨󴴨sw󳠃󳠃󳠃󳠃󴧖󴧖󴧖󴧖

DY

R1302 10KR2F-L1-GP

12

0R0402-PAD

12

R1303

R1306 10KR2F-L1-GPR1306 10KR2F-L1-GP

12

R1307 0R2J-L-GP

12

DY

R1310 10KR2F-L1-GP

12

0R0402-PAD

12

R1311

3D3V_S0

4 OF 4

DM2D

4 OF 4

C1329

DM2D

VSS1VSS

2

VSS

5

VSS

12

C1328

SCD1U16V2KX-L-GP

SC2D2U10V3KX-L-GP

DY

6

9 10 14 15 18 19 22 23 26 27 30 31 35 36 39 40 43 44 47 48 51 52 56 57 60 61 64 65 68 69 72 73 77 78 81 82 85 86 89 90 93 94 98

DDR4-260P-23-GP

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

99 102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

UN 0225

2D5V_S30D6V_S0 0D 6V_S0 0D6V _S0

12

C1325

C1324

SC10U6D3V3MX-GP

12

C1310

SC10U6D3V3MX-GP

DY

12

C1322

SC1U10V2KX-1GP

DY

SC10U6D3V3MX-GP

12

C1326

SC1U10V2KX-1GP

M_B_DQS_DN0 M_B_DQS_DN1 M_B_DQS_DN2 M_B_DQS_DN3 M_B_DQS_DN4 M_B_DQS_DN5 M_B_DQS_DN6 M_B_DQS_DN7

M_B_DQS_DP0 M_B_DQS_DP1 M_B_DQS_DP2 M_B_DQS_DP3 M_B_DQS_DP4 M_B_DQS_DP5 M_B_DQS_DP6 M_B_DQS_DP7

12

C1327

SC1U10V2KX-1GP

12

C1311

DY

M_B_DQS_DN[7 :0] 5

M_B_DQS_DP[7:0] 5

12

C1331

C1330

SC4D7U6D3V2MX-1-GP

DY

SC4D7U6D3V2MX-1-GP

12

C1312

12

C1314

C1313

SC1U10V2KX-L1-GP

SC1U10V2KX-1GP

DY

SC4D7U6D3V2MX-1-GP

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O .C.

Taipei Hsie n 221, Taiwan, R.O .C.

Title

DDR3-SODIMM1

Size Documen t Number Rev

Size Documen t Number Rev A2

A2

Monday, June 27, 2016

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O .C.

Vegas SKL/KBL-U

1

13 106

A00

5

WWW.AliSaler.Com

D D

4

3

2

1

C C

(Blanking)

B B

Wistron Corporation

A A

Title

(Reserved)_SODIMM _SODIMM4

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Vegas SKL/KBL-U

14 105Thursday, June 16, 2016

1

A00

5

Main Func = PCH

4

3

2

1

CPU1I

SKYLAKE_ULT

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

D D

C C

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKYLAKE-U-GP

071.SKYLA.000U

SKYLAKE_ULT

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

9 OF 20

CSI2_CLKN0

CSI2_CLKP0

CSI2_CLKN1

CSI2_CLKP1

CSI2_CLKN2

CSI2_CLKP2

CSI2_CLKN3

CSI2_CLKP3 CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

C37 D37 C32 D32 C29

DC resistance < 0.5ohm.

D29 B26 A26

CSI2_COMP

E13

WIFI_RF_EN

B7

AP2 AP1 AP3

GPP_F: VCCPGPPF = 1.8V Only

AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

EMMC_RCOMP

AT1

1 2

WIFI_RF_EN

R1501 100R2F-L1-GP-UR1501 100R2F-L1-GP-U

1 2

WIFI_RF_EN 61

R1502

200R2F-L-GP

R1503

1 2

10KR2J-3-GP

3D3V_S0

DY

[#545659 Rev0.7]

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(CS-2/EMMC)

Vegas SKL/KBL-U

15 105Monday, June 27, 2016

1

A00

Main Func = PCH

WWW.AliSaler.Com

#543016: 220 nF nominal capacitors are r ecommended for Gen 3. 100 nF nominal capacitors are r ecommended for Gen 2.

PEG_RX_CPU_N076 PEG_RX_CPU_P076 PEG_TX_GPU_N076 PEG_TX_GPU_P076

PEG_RX_CPU_N176 PEG_RX_CPU_P176 PEG_TX_GPU_N176 PEG_TX_GPU_P176

GPU

PEG_RX_CPU_N276 PEG_RX_CPU_P276 PEG_TX_GPU_N276 PEG_TX_GPU_P276

WLAN

LAN

HDD1

ODD

3D3V_S0

PEG_RX_CPU_N376 PEG_RX_CPU_P376 PEG_TX_GPU_N376 PEG_TX_GPU_P376

PCIE_RX_CPU_N561 PCIE_RX_CPU_P561 PCIE_TX_CON_N561 PCIE_TX_CON_P561

PCIE_RX_CPU_N631 PCIE_RX_CPU_P631 PCIE_TX_CON_N631 PCIE_TX_CON_P631

SATA_RX_CPU_N060 SATA_RX_CPU_P060 SATA_TX_CPU_N060 SATA_TX_CPU_P060

SATA_RX_CPU_N160

SATA_RX_CPU_P160

SATA_TX_CPU_N160

SATA_TX_CPU_P160

Layout Note:

PCIE Table

Port

1

2

3

4

5(L0~L3)

6(L3)

6(L2)

6(L0~L1)

D D

C C

5

SCD1U16V2KX-3GP

1 2 1 2

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

USB 2.0 Table

PEG_TX_CPU_N0 PEG_TX_CPU_P0

PEG_TX_CPU_N1 PEG_TX_CPU_P1

PEG_TX_CPU_N2 PEG_TX_CPU_P2

PEG_TX_CPU_N3 PEG_TX_CPU_P3

PCIE_TX_CPU_N5 PCIE_TX_CPU_P5

PCIE_TX_CPU_N6 PCIE_TX_CPU_P6

PCIE_RCOMPN PCIE_RCOMPP

XDP_PRDY# XDP_PREQ# PIRQA#

Pair

0

1

2

3

4

5

6

7

Device

USB3.0 port1

USB3.0 Port2

USB2.0 Port3 (IOBD)

Finger Print

CAMERA

Card Reader

Touch Panel

WLAN

C1606

GEN2/GEN3

GEN2/GEN3 GEN2/GEN3

GEN2/GEN3

C1605

C1608

GEN2/GEN3

GEN2/GEN3 GEN2/GEN3

GEN2/GEN3

C1607

C1610

GEN2/GEN3

GEN2/GEN3 GEN2/GEN3

GEN2/GEN3

C1609

C1612

GEN2/GEN3

GEN2/GEN3 GEN2/GEN3

GEN2/GEN3

C1611

C1601

C1601 C1602

C1602

C1603

C1603 C1604

C1604

1. Trace Width: 4 mils min (bre akout) 12-15 mils (trace) Note: Must maintain low DC resi stance routing (<0.1 ohm).

2. Isolation Spacing: At least 12 mils to any adjacent high speed I/O.

R1604

1 2

100R2F-L1-GP-U

1

TP1601TPAD14-OP-GP TP1601TPAD14-OP-GP

1

TP1602TPAD14-OP-GP TP1602TPAD14-OP-GP

PIRQA#

R160710KR2J-3-GP R160710KR2J-3-GP

12

Device

Share BUS

USB3.0_3

N/A

USB3.0_4

N/A

WLAN

LAN

GPU

HDD

SATA0

ODD SATA1

N/A

CPU1H

PCIE/USB3/SATA

H13

PCIE1_ RXN/USB3_ 5_RXN

G13

PCIE1_ RXP/USB3 _5_RXP

B17

PCIE1_ TXN/USB3_ 5_TXN

A17

PCIE1_ TXP/USB3 _5_TXP

G11

PCIE2_ RXN/USB3_ 6_RXN

F11

PCIE2_ RXP/USB3 _6_RXP

D16

PCIE2_ TXN/USB3_ 6_TXN

C16

PCIE2_ TXP/USB3 _6_TXP

H16

PCIE3_ RXN

G16

PCIE3_ RXP

D17

PCIE3_ TXN

C17

PCIE3_ TXP

G15

PCIE4_ RXN

F15

PCIE4_ RXP

B19

PCIE4_ TXN

A19

PCIE4_ TXP

F16

PCIE5_ RXN

E16

PCIE5_ RXP

C19

PCIE5_ TXN

D19

PCIE5_ TXP

G18

PCIE6_ RXN

F18

PCIE6_ RXP

D20

PCIE6_ TXN

C20

PCIE6_ TXP

F20

PCIE7_ RXN/SATA 0_RXN

E20

PCIE7_ RXP/SAT A0_RXP

B21

PCIE7_ TXN/SATA 0_TXN

A21

PCIE7_ TXP/SAT A0_TXP

G21

PCIE8_ RXN/SATA 1A_RXN

F21

PCIE8_ RXP/SAT A1A_RX P

D21

PCIE8_ TXN/SATA 1A_TXN

C21

PCIE8_ TXP/SAT A1A_TX P

E22

PCIE9_ RXN

E23

PCIE9_ RXP

B23

PCIE9_ TXN

A23

PCIE9_ TXP

F25

PCIE10 _RXN

E25

PCIE10 _RXP

D23

PCIE10 _TXN

C23

PCIE10 _TXP

F5

PCIE_R COMPN

E5

PCIE_R COMPP

D56

PROC_P RDY#

D61

PROC_P REQ#

BB11

GPP_A7 /PIRQA#

E28

PCIE11 _RXN/SAT A1B_RX N

E27

PCIE11 _RXP/SA TA1B_R XP

D24

PCIE11 _TXN/SAT A1B_TX N

C24

PCIE11 _TXP/SA TA1B_T XP

E30

PCIE12 _RXN/SAT A2_RXN

F30

PCIE12 _RXP/SA TA2_RX P

A25

PCIE12 _TXN/SAT A2_TXN

B25

PCIE12 _TXP/SA TA2_TX P

SKYLAKE-U-GP

071.SKYLA.000U

SKYLAKE_ULT

4

SSIC / USB3

USB3_2_ RXN/SSIC _RXN USB3_2_ RXP/SSI C_RXP USB3_2_ TXN/SSIC _TXN USB3_2_ TXP/SSI C_TXP

USB2

USB2_VB USSENSE

GPP_E9 /USB2_OC 0# GPP_E1 0/USB2_O C1# GPP_E1 1/USB2_O C2# GPP_E1 2/USB2_O C3#

GPP_E4 /DEVSLP 0 GPP_E5 /DEVSLP 1 GPP_E6 /DEVSLP 2

GPP_E0 /SATAXP CIE0/SA TAGP0 GPP_E1 /SATAXP CIE1/SA TAGP1 GPP_E2 /SATAXP CIE2/SA TAGP2

GPP_E8 /SATALE D#

8 OF 20

H8

USB3_1_ RXN

G8

USB3_1_ RXP

C13

USB3_1_ TXN

D13

USB3_1_ TXP

J6 H6 B13 A13

J10

USB3_3_ RXN

H10

USB3_3_ RXP

B15

USB3_3_ TXN

A15

USB3_3_ TXP

E10

USB3_4_ RXN

F10

USB3_4_ RXP

C15

USB3_4_ TXN

D15

USB3_4_ TXP

AB9

USB2N_1

AB10

USB2P_1

AD6

USB2N_2

AD7

USB2P_2

AH3

USB2N_3

AJ3

USB2P_3

AD9

USB2N_4

AD10

USB2P_4

AJ1

USB2N_5

AJ2

USB2P_5

AF6

USB2N_6

AF7

USB2P_6

AH1

USB2N_7

AH2

USB2P_7

AF8

USB2N_8

AF9

USB2P_8

AG1

USB2N_9

AG2

USB2P_9

USB2N_10 USB2P_1 0

USB2_CO MP

USB2_ID

DC resistance < 0.5ohm.

AH7 AH8

USBCOMP

AB6

USB2_ID

AG3

USB2_VBUSSENSE

AG4 A9

USB_OC1#

C9

USB_OC2#

D9

USB_OC3#

B9 J1

J2 J3

GPP_E0/SATAXPCIE0/SATAGP0

H2 H3

GPP_E2/SATAXPCIE2/SATAGP2

G4 H1

USB2_ID USB2_VBUSSENSE

(#543016) Unused SATAGP[2:0]/GP P_E[2:0] pins must be terminat ed to either 3.3 V rail or GND using 8.2 KΩ to 10 KΩ on the m otherboard. Do not use both pull-up and pul l-down. Either pull-up or pull -down is acceptable.

R1603 113R2F-GPR1603 113R2F-GP

1 2

SIO_EXT_SCI#_R 24

R1601 0R0402-PADR1601 0R0402-PAD

1 2

R1602 0R0402-PADR1602 0R0402-PAD

1 2

USB30_RX_CPU_N1 36 USB30_RX_CPU_P1 36 USB30_TX_CPU_N1 36 USB30_TX_CPU_P1 36

USB30_RX_CPU_N2 36 USB30_RX_CPU_P2 36 USB30_TX_CPU_N2 36 USB30_TX_CPU_P2 36

USB_CPU_PN0 36 USB_CPU_PP0 36

USB_CPU_PN1 36 USB_CPU_PP1 36

USB_CPU_PN2 37 USB_CPU_PP2 37

USB_CPU_PN3 92 USB_CPU_PP3 92

USB_CPU_PN4 55 USB_CPU_PP4 55

USB_CPU_PN5 33 USB_CPU_PP5 33

USB_CPU_PN6 55 USB_CPU_PP6 55

USB_CPU_PN7 61 USB_CPU_PP7 61

USB_OC0# 35 USB_OC2# 35

USB_OC3# 24

HDD_DEVSLP 60

1 1

TP1603 TPAD14-OP-GPTP1603 TPAD14-OP-GP

SATA_ODD_PRSNT# 60

TP1604 TPAD14-OP-GPTP1604 TPAD14-OP-GP

SATA_LED#_R 64

USB1 (USB3.0 Port1)

USB2 (USB3.0 Port2)

USB1 (USB3.0 port1)

USB2 (USB3.0 Port2)

USB3 (IO BD/USB2.0 Port3)

Finger Print (USB2.0 Port4)

CAMERA (USB2.0 Port5)

Card Reader (USB2.0 Port6)

Touch Panel (USB2.0 Port7)

WLAN (USB2.0 Port8)

(#543016) When used as DEVSLP, no external pull-up or pull-dow n termination required from SATA Host DEVSLP.

R1608

10KR2J-3-GP

R1608

1 2

SATA_ODD_PRSNT#

3

(#545659) The xHCI controller s upports USB Debug port on all USB3.0 capable ports.

Unused SATA[3:0]GP pins must be terminated to either

3.3V rail or GND using 8.2K to 10K on the motherboard. Either pull-up or pull-down is acceptable.

3D3V_S0

USB_OC2# USB_OC3# USB_OC0# USB_OC1#

RN802

8 7

SRN10KJ-6-GP

3D3V_S5_PCH

1 2 3456

SATA_LED#_R

(#543611) The SATALED# signal is open-col lector and requires a weak ext ernal pull-up (8.2 kΩ to 10 kΩ) to Vcc3_3.

R1606

10KR2J-3-GP

2

3D3V_S0

R1610

SIO_EXT_SCI#_R

R1610

10KR2J-3-GP

12

3D3V_S0

12

1

#545659 (SKL_PCH_U_Y_EDS Rev0.7 )

B B

A A

5

Title

Size Document Number Rev

A1

Date: Sheet of

4

3

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(PCIE/SATA/USB)

Vegas SKL/KBL-U

16 105Monday, June 27, 2016

A00

5

4

3

2

1

Main Func = PCH

3D3V_S5

BATLOW#: Pull-up required even if not implemented.

D D

3D3V_S5

RTC_AUX_S5

3D3V_S5_PCH

R1717 10KR2J-3-GP

C C

B B

ME_SUS_PW R_ACK24

A A

RN1704

1

8

2

7

3

6

4 5

SRN10KJ-6-G P

R1711

1 2

0R0603-PAD

Layout note: 3 PAD SHARING

#544669 (CRB): 330k.

R1730

330KR2J-L1-GP

1 2

R1731 20KR2J-L2-GPR1731 20KR2J-L2-GP

1 2

R1718 10KR2J-3-GP

1 2

1 2 3

SRN10KJ-5-G P

DY

RN1701

SM_INTRUDER #

4

12

+VCCMPHYGTAON_1P0(ICCMAX.=3.5A)

R1724

1 2

0R0805-PAD

R1735

1 2

0R0805-PAD

3D3V_AUX_S5

R1726

R1726 10KR2J-3-GP

10KR2J-3-GP

1 2

3V_5V_POK#

R1727

100KR2J-1-GP

1 2

NON DS3

S

G

6

D

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

Q1701

2N7002KDW -GP

AC_PRESENT PCH_WA KE# PCH_BATLOW # GPD11/LANPH YPC

GPD11 pull high by Intel PDG1.3 request

+VCCPDSW _3P3

#544669 Rev0.52 CRB:

EXT_PWR _GATE# ME_SUS_PW R_ACK_R

PM_RSMRST# PM_PCH_PW ROK

SYS_PWROK

No PL resistor on THERMTRIP#.

H_CPUPW RGD

+VCCMPHYGTAON_1P0

SKL: 1.0V

+VCCMPHYGTA ON_1P0_LS_SIP1D0V_S5

12

C1704

C1704 SC10U6D3V3MX- GP

SC10U6D3V3MX- GP

SUSACK#_RME_SUS_PW R_ACK_R

R1708

1 2

0R0402-PAD

R1709

1 2

0R0402-PAD

5

ME_SUS_PW R_ACK_R

1KR2J-1-GP

PM_RSMRST# 3V_5V_POK_C

1KR2J-1-GP

R1702

1 2

R1728

1 2

0R0402-PAD

D

G

2345 1

S

PCH_PLTRST #

R1713

1 2

0R0402-PAD

12

C1701

C1701 SC220P50V2KX-3GP

SC220P50V2KX-3GP

DY

CPU1K

SYSTEM POWER MANAGEMENT

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD#AT15

SKYLAKE-U-GP

071.SKYLA.000U

3D3V_S5

SCD1U16V2KX-3GP

C1702

12

DY

5

VCC

DY

4

12

R1719

R1719 47KR2F-GP

47KR2F-GP

12

DY

EC1702

EC1706

EC1703

SC1KP50V2KX-1GP

+VCCSTG

12

DY

SC1KP50V2KX-1GP

R1722

R1722 100KR2J-1-GP

100KR2J-1-GP

12

DY

SKYLAKE_ULT

DY

12

EC1705

EU1701AZ5325-01FDR7G-GP EU1701AZ5325-01FDR7G-GP

H_VCCST_PW RGD_R

12

EC1708

EC1708 SCD01U50V2KX- 1GP

SCD01U50V2KX- 1GP

XDP_DBRESE T#

12

DY

SC1KP50V2KX-1GP

11 OF 20

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

SYS_PWROK PLT_RST#

RESET_OUT #

3V_5V_POK

[#543016 Rev0.7] EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k pull-down that is active during the early portion of the power up sequence

SIO_SLP_S0#

AT11 AP15 BA16

SIO_SLP_S5#

AY16

SLP_SUS#

AN15

SLP_LAN#

AW15

GPD9/SLP_W LAN#

BB17

SIO_SLP_A#

AN16 BA15

AC_PRESENT

AY15

PCH_BATLOW #

AU13

PME#

AU11

SM_INTRUDER #

AP16

EXT_PWR _GATE#

AM10 AM11

3D3V_AUX_S5

1 2

#543016 Rev0.7

1. VCCST_PWRGD is only 1.0 V tolerant.

2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST

2

1 1

1 1 1

1

R1737

NON DS3

100KR2J-1-GP

TP1701 TP AD14-OP-GPTP1701 TP AD14-OP-GP

1

TP1703 TPAD14-OP -GPTP1703 TPAD14-OP -GP TP1702 TPAD14-OP -GPTP1702 TPAD14-OP -GP TP1704 TPAD14-OP -GPTP1704 TPAD14-OP -GP TP1705 TPAD14-OP -GPTP1705 TPAD14-OP -GP TP1706 TPAD14-OP -GPTP1706 TPAD14-OP -GP

TP1707 TPAD14-OP-G PTP1707 TPAD14-OP-G P

PM_RSMRST#_M

SIO_SLP_S3# 24,27,40,51

SIO_SLP_S4# 24,4 0,44,51

SIO_PWRBT N# 24

S

Q1702

G

NON DS3

6

D

2N7002KDW -GP

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

AC_PRESENT

EC1707

12

DY

SCD1U16V2KX-3GP

D1702

KA

RB751V-40H-G P

83.R2004.G8F

D

G

2345 1

S

Title

CPU_(POWER MANAGEMENT)

Size Documen t Number Rev

A2

Date: Sheet of

AC_PRESENT PM_RSMRST#

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O .C.

Taipei Hsie n 221, Taiwan, R.O .C.

Vegas SKL/KBL-U

1

ACOK_IN 24, 44

17 105Monday, June 27, 2016

A00

PCH_PLTRST # XDP_DBRESE T# PM_RSMRST#

H_CPUPW RGD H_VCCST_PW RGD

SYS_PWROK PM_PCH_PW ROK PCH_DPW ROKPM_RSMRST#

ME_SUS_PWR_ACK_R SUSACK#_R

PCH_WA KE# GPD2/LAN_W AKE# GPD11/LANPH YPC

3D3V_S5

C1703

DY

12

EC1709

DY

SCD1U16V2KX- 3GP

PLT_RST#24,31,40,55,6 1,68,76,91

12

R1715

100KR2J-1-GP

SCD1U16V2KX-3GP

U1701

1

NC

2

A GND3Y

U74LVC1G07G-A L5-R-GP

73.01G07.AHG

1 2

R1716

R1716 100KR2F-L1-GP

100KR2F-L1-GP

3

+V3.3A_SIP

12

R1701

R1701 10KR2J-3-GP

10KR2J-3-GP

TP1710TPAD14-OP-GP TP1710TPAD14-OP-GP

1

H_THERMT RIP_EN40

SYS_PWROK24

12

R405

R405 10KR2J-3-GP

10KR2J-3-GP

DY

RESET_OUT #24,26,4 0

3V_5V_POK 40,45,53,54

EC1712

12

DY

SCD1U16V2KX-3GP

4

H_VCCST_PW RGD_R

+VCCPDSW _3P3

(PDG#543016) WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns.

EC_WAKE#24

SIO_SLP_S3#24,27,40,51

ALL_SYS_PWRG D2 4,40

PCH_RSMRS T# 24

DY

R4110R2J-2-GPDYR4110R2J-2-GP

1 2

R1706 0R0402-P ADR1706 0R0402-PAD

1 2

R1704 0R2J-2-G PR1704 0R2J- 2-GP

1 2

DY for OBFF disable

R1707 10KR 2J-3-GPR 1707 10KR2 J-3-GP

1 2

GPD2/LAN_W AKE#

R1710

1 2

0R0402-PAD

U1702

1

5

NC

VCC

2

DY

A

4

GND3Y

U74LVC1G07G-A L5-R-GP

73.01G07.AHG

60D4R2F-GP

60D4R2F-GP R1734

R1734

RN1802

WWW.AliSaler.Com

RN1802

SRN1KJ-7-G P

RN1812

1 2 3 4 5

RN1813

1 2 3

4

SIO_RCIN#

SERIRQ

5

SPI_HOLD_ROM

SPI_WP_ROM

CLKREQ_PCIE#5

8

CLKREQ_PEG#0

7

CLKREQ_PCIE#1

6

CLKREQ_PCIE#2

CLKREQ_PCIE#3

4

CLKREQ_PCIE#4

GPU WLAN

LAN

5

PCH strap pin:

Sampled at rising edge of RSMRST#

eSPI or LPC

SML0ALERT# / GPP_C5

This signal has a weak internal pull-down.

SPI_CS_ROM_N024, 25

CL_CLK61 CL_DATA61

PEG_CLK_CPU #76 PEG_CLK_CPU76

CLKREQ_PEG#079

PEG_CLK1_CPU #61 PEG_CLK1_CPU61

CLKREQ_PCIE#161

PEG_CLK2_CPU #31 PEG_CLK2_CPU31

CLKREQ_PCIE#231

This signal has a weak internal pull-down. 0 = LPC Is selected for EC. 1 = eSPI Is selected for EC.

Resister value will check later

SPI_CLK_ROM24,25

SPI_SO_ROM24,25

SPI_SI_ROM24,25 SPI_WP_ROM25 SPI_HOLD_ROM25

HDD_FALL_INT67

DVT1 add FFS 2/18

CL_RST#61

SIO_RCIN#24

SERIRQ24,91

R18060R 0402-PAD R18060R0402-PAD

1 2

R18070R 0402-PAD R18070R0402-PAD

1 2

R18080R 0402-PAD R18080R0402-PAD

1 2

R18090R 0402-PAD R18090R0402-PAD

1 2

R18110R 0402-PAD R18110R0402-PAD

1 2

R18120R 0402-PAD R18120R0402-PAD

1 2

SCD1U16V2KX-3GP

12

EC1805

DY

Main Func = PCH

D D

C C

B B

A A

R1835 and R1834 merge to RN1802 Follow Starlord

3D3V_S5_PCH

3D3V_S0

R2021

1 2

10KR2J-3-GP

R2032

1 2

10KR2J-3-GP

SERIRQ PH: PDG: 8.2k CRB: 10k

RCIN#: Frequency to Avoid: 33 MHz

3D3V_S0

SRN10KJ-6-G P

1 2 3

SRN10KJ-5-G P

GPP_C5/SML0ALER T#

SPI_CLK_CPU SPI_SO_CPU SPI_SI_CPU SPI_WP_CPU SPI_HOLD_CPU SPI_CS_CPU_N0

TP1801TPA D14-OP-GP TP1801TPAD14-OP-GP TP1803TPA D14-OP-GP TP1803TPAD14-OP-GP

TP1804TPA D14-OP-GP TP1804TPAD14-OP-GP TP1805TPA D14-OP-GP TP1805TPAD14-OP-GP TP1806TPA D14-OP-GP TP1806TPAD14-OP-GP

4

CPU_D1_TP

1

CPU_D3_TP

1

CPU_D4_TP

1

CPU_D5_TP

1

CPU_D6_TP

1

CLKREQ_PEG#0

CLKREQ_PCIE#1

CLKREQ_PCIE#3

CLKREQ_PCIE#4

CLKREQ_PCIE#5

4

PCH Prim

3D3V_S5_PCH

12

DY

12

DY

CPU1E

AV2

AW3

AV3

AW2

AU4 AU3 AU2 AU1

M2 M3

J4 V1 V2 M1

G3 G2 G1

AW13

AY11

SKYLAKE-U-GP

071.SKYLA.000U

R1822

R1822 1KR2J-1-GP

1KR2J-1-GP

R1823

R1823 1KR2J-1-GP

1KR2J-1-GP

SPI - FLASH

SPI0_CLK SPI0_MISO

Strap

SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

C LINK

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN# GPP_A6/SERIRQ

CPU1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKYLAKE-U-GP

071.SKYLA.000U

PCH strap pin:

BOOT HALT

SKYLAKE_ULT

CLOCK SIGNALS

SKYLAKE_ULT

LPC

0 = ENABLED 1 = DISABLED WEAK INTERNAL PU

SMBUS, SMLINK

GPP_A14/SUS_STAT#/ESPI_RESET#

SPI0_MOSI

This signal has a weak internal pull-up.

3

LPC_LAD[3..0]24,68,91

5 OF 20

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

Strap

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

20140820 DAIVD

SC3D9P50V2CN -1GP

10 OF 20

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

F43 E43

BA17 E37

E35 E42 AM18

AM20 AN18

AM16

3

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

SPI_SI_CPU

MEM_SMBCLK

R7

MEM_SMBDATA

R8

GPP_C2/SMBALER T#

R10

SML0_SMBCLK

R9

SML0_SMBDATA

W2

GPP_C5/SML0ALER T#

W1

SML1_SMBCLK

W3

SML1_SMBDATA

V3

GPP_B23/SML1ALERT #

AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

PCI_CLK_LPC0 PCI_CLK_LPC1

C1804

PCIE_CLK_XDP_N PCIE_CLK_XDP_P

SUSCLK_R XTAL24_IN

XTAL24_OUT XCLK_BIASREF RTC_X1

RTC_X2 SRTC_RST #

RTC_RST#

PCH Prim

3D3V_S5_PCH

12

DY

12

DY

LPC_LAD[3..0]

LPC_LAD0_R LPC_LAD1_R LPC_LAD2_R LPC_LAD3_R LPC_LFRAME#_R

PCI_CLK_LPC1 CLKRUN#_R

R1804 0R2J-2-GP

1 2

R1815 10M R2J-L-GPR1815 10MR2J-L- GP

X1802

12

2 3

XTAL-32D768KH Z-68-GP

82.30001.G01

2rd = 82.30001.G11

R1813 0R0402-PADR1 813 0R 0402-PAD

1 2

R1803

1 2

2K7R2F-GP

Intel recommend: 2.71k ohm 5%

RTCRST_O N24

R1824

R1824 1KR2J-1-GP

1KR2J-1-GP

R1825

R1825 1KR2J-1-GP

1KR2J-1-GP

LPC_LAD2 LPC_LAD1 LPC_LAD3 LPC_LAD0

SML1_SMBCLK 24,79 SML1_SMBDATA 24,79

R1801 0R0402- PADR1801 0R 0402-PAD

12

PCI_CLK_LPC0 91

1 2

R1819

0R2J-2-GP

1 2

LPC

R1805 0R0402-PADR1 805 0R 0402-PAD

1 2

41

+V1.00A_SIP

SCD1U16V2KX-3GP

12

EC1808

DY

RN1806

LPC_LAD2_R

1

8 7 6

DY

10KR2J-3-GP

SRN0J-7-GP -U

SUS_STAT#/LPC PD# 91

EC1801

SC10P50V2JN-4GP

12

RTC_X1 RTC_X2

12

C1803

C1803 SC3D9P50V2CN -1GP

SC3D9P50V2CN -1GP

TP1807 TPAD14-OP-GPTP1807 TPAD14-OP-GP

1

TP1808 TPAD14-OP-GPTP1808 TPAD14-OP-GP

1

12

R1902

LPC_LAD1_R

2

LPC_LAD3_R

3

LPC_LAD0_R

45

LPC_LFRAME# 24,68,91

CLKRUN# 24,91

SUS_CLK 24

Q1901

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

SUS_STAT#/LPC PD#

CLKRUN#_R

Layout: Place at the open door area.

2

CLK_PCI_LPC 68 CLK_PCI_LPC_MEC 24

D

C1901

SC1U10V2KX-1GP

(#514849)

2

3D3V_S5_PCH

R1814

12

DY

10KR2J-3-GP

3D3V_S0

R1818

8K2R2F-1-GP

1 2

MEM_SMBDATA

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

MEM_SMBCLK

XTAL24_IN XTAL24_IN_R

XTAL24_OUT

RTC_AUX_S5

21

12

G1901

GAP-OPEN

1

23

RN1901

RN1901 SRN20KJ-1-G P

SRN20KJ-1-G P

4

12

C1902

C1902 SC1U10V2KX-1G P

SC1U10V2KX-1G P

12

R1810

1 2

0R0402-PAD

R1802

R1802 1MR2J-1-GP

1MR2J-1-GP

SUSCLK_R

23

12

DY

1

RN1807

SML1_SMBDATA SML1_SMBCLK SML0_SMBDATA SML0_SMBCLK

GPP_B23/SML1ALERT #

GPP_C2/SMBALER T#

MEM_SMBCLK MEM_SMBDATA

3D3V_S0

2N7002KDW -GP

1

6

2345

Q1801

X1801

X1801 XTAL-24MHZ- 81-GP

XTAL-24MHZ- 81-GP

82.30004.841

4 1

DY

1 2

SRTC_RST # RTC_RST#

SCD1U16V2KX-3GP

12

EC1806

EC1807

DY

Title

Size Documen t Number Rev

Date: Sheet of

RN1807

1

8

2

7

3

6

45

SRN2K2J-4-G P

R1820

150KR2F-L-GP

12

R1821

12

2K2R2J-2-GP

SRN2K2J-1-G P

23 1

4

RN1811

RN1810

23 1

4

SRN10KJ-5-G P

PCH_SMBDAT A 12,13,56,65,67

PCH_SMBCLK 12,13,56,65,67

C1801

12

SC15P50V2JN-2- GP

C1802

12

SC15P50V2JN-2- GP

EC1803

SC4D7P50V2BN-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O .C.

Taipei Hsie n 221, Taiwan, R.O .C.

CPU_(LPC/SPI/SMBUS/CL/CLK)

A2

Vegas SKL/KBL-U

1

3D3V_S5_PCH

3D3V_S0

18 105Monday, June 27, 2016

A00

5

4

3

2

1

Main Func = PCH

PCH strap pin:

Flash Descriptor Security Overide/

D D

C C

Intel ME Debug Mode

HDA_SDOUT

Low = Default High = Enable

*

The internal pull-down is disabled after PLTRST# deasserts

HDA_SDIN027

DGPU_PWROK24,79,85

HDA_SYNC HDA_BITCLK HDA_SDOUT

12

FC1902

DY

SC2P50V2CN-GP

SPKR27

CPU1G

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

AUDIO

SKYLAKE_ULT

7 OF 20

SDIO/SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

CPU_A16_TP SD_RCOMP

200R2F-L-GP

KB_LED_BL_DET_R 65

1

R1901

1 2

TP1902

TP1902 TPAD14-OP-GP

TPAD14-OP-GP

SKYLAKE-U-GP

071.SKYLA.000U

PCH strap pin:

B B

NO REBOOT

Low = Enable (Default)

HDA_SPKR

The internal pull-down is disabled after PLTRST# deasserts

A A

*

5

High = Disable

3D3V_S0

R2006 1KR2J-1-GP

1 2

DY

R1904 100KR2J-1-GP

1 2

UMA

EC1901 SC10P50V2JN-4GP

1 2

DY

EC1903 SC1KP50V2KX-1GP

4

DY

12

SPKR

DGPU_PWROK

HDA_CODEC_BITCLK DGPU_PWROK

3

R1907 0R0402-PADR1907 0R0402-PAD

HDA_CODEC_BITCLK27 HDA_CODEC_SYNC27

HDA_CODEC_SDOUT27

ME_FWP_EC24

Title

CPU_(AUDIO/SDIO/SDXC)

Size Document Number Rev

A4

Date: Sheet of

CPU_(AUDIO/SDIO/SDXC)

2

1 2

R1908 0R0402-PADR1908 0R0402-PAD

1 2

R1912 0R0402-PADR1912 0R0402-PAD

1 2

R1909 1KR2J-1-GPR1909 1KR2J-1-GP

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Vegas SKL/KBL-U

HDA_BITCLK HDA_SYNC

12

DY

19 105Monday, June 27, 2016

1

HDA_SDOUT

FC1901

FC1901 SC2P50V2CN-GP

SC2P50V2CN-GP

A00

5

WWW.AliSaler.Com

4

3

2

1

Main Func = PCH

3D3V_S0

SRN10KJ-5-G P

CAMERA_DET #

3D3V_S0

12

TPM

12

NON_TPM

SRN10KJ-5-G P RN2007

RN2007

1 2 3

DY

RN2008

1

DY

2 3

SRN2K2J-1-G P

R2003

10KR2J-3-GP

1 2

GPP_A18GPP_A19

PROJECT_ID1

0

1X

X

4

3D3V_S0

BIOS strap pin:

BIOS UMA/DIS Strap pin

TPM

NON_TPM

GPP_A22

TPM_SELECT

1

0

EC2002

12

DY

SC1KP50V2KX-1G P

RN2009

1

4

2 3

DY

SRN10KJ-5-G P

D D

(PDG#543016) If the UART/GPIO functionality is also not used, the signals can be left as no-connect.

3D3V_S0

R2048 51KR2J-1-GPR2048 51KR2J-1-GP

1 2

R2049 51KR2J-1-GPR2049 51KR2J-1-GP

1 2

R2046 51KR2J-1-GPR2046 51KR2J-1-GP

1 2

R2002 10KR2J-3-GP

1 2

DY

1

4

2 3

RN2012

SRN10KJ-5-G P

RN2010

1

4

2 3

DY

SRN2K2J-1-G P

3D3V_S5_PCH

SRN10KJ-5-G P

SRN10KJ-5-G P RN2011

RN2011

1

4

2 3

PCH strap pin:

No Reboot

GSPI0_MOSI / GPP_B18

C C

The signal has a weak internal pull-down.

Sampled at rising edge of PCH_PWROK

0 = Disable “No Reboot” mode. 1 = Enable “No Reboot” mode (PCH will disable the TCO Timer system reboot feature). This function is useful when running ITP/XDP.

DGPU_HOLD _RST# DGPU_PW R_EN

LPSS_UART2_R XD LPSS_UART2_T XD

LPSS_UART2_C TS# BLUETOOTH _EN

DBC_PANEL_E N KB_DET#

I2C0_SDA_TCH_ PAD I2C0_SCL_TCH_P AD

RTC_DET# SIO_EXT_WAKE #

DGPU_HOLD _RST# 76

PCH Prim

3D3V_S5_PCH

DY

12

R2007

R2007 1KR2J-1-GP

1KR2J-1-GP

GPP_B18/GSPI0_MOSI

12

R2019

R2019 1KR2J-1-GP

1KR2J-1-GP

PTP

BLUETOOTH _EN61

DBC_PANEL_E N55

SIO_EXT_WAKE #24

I2C0_SDA_TCH_ PAD6 5 I2C0_SCL_TCH_P AD65

CPU1F

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKYLAKE-U-GP

071.SKYLA.000U

TPAD14-OP-G P

TP2008

VRAM_ID1 GPP_B18/GSPI0_MOSI

GPP_B22

1

BOARD_ID2 LPSS_UART2_R XD

LPSS_UART2_T XD LPSS_UART2_C TS#

For debug USB/UART:

5V_S5

LPSS_UART2_T XD LPSS_UART2_R XD

TPAD14-OP-G P

TP2009

LPSS_UART2_C TS#

1

Intel has removed EHCI controller from BDW and proposed to use UART interface for Win7 debug.

LPSS ISH

SKYLAKE_ULT

Strap

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

SX_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ISH_GP6

56

DB2

1 2

DY

3

20.F1897.004

4

ACES-CON 4-37-GP

6 OF 20

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

Vegas

PROJECT_ID1

BOARD_ID2

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

3D3V_S0 3D3V_S0

12

R2015

10KR2J-3-GP

12

R2016

10KR2J-3-GP

Turis

3D3V_S0

12

R2005

OPS

10KR2J-3-GP

12

R2008

R2008 10KR2J-3-GP

10KR2J-3-GP

UMA

USB_UART_S EL_D9

P2

DGPU_HOLD _RST#

P3 P4

RTC_DET#

P1

I2C0_SDA

M4

I2C0_SCL

N3

I2C1_SDA

N1

I2C1_SCL

N2

1.8V Only

AD11 AD12

U1

UART0_TXD

U2

UART0_RTS #

U3

UART0_CTS #

U4

UART1_RXD

AC1 AC2 AC3

UART1_CTS #

AB4

PROJECT_ID1

AY8

PROJECT_ID2

BA8

KB_DET#

BB7

CAMERA_DET #

BA7

TPM_SELECT

AY7 AW7 AP13

R2017

10KR2J-3-GP

PROJECT_ID2

R2018

10KR2J-3-GP

BIOS strap pin:

BIOS UMA/DIS Strap pin

UMA

DIS

PANEL_SIZE_ID 55

12

SKL

12

KBL

I2C0_SCL I2C0_SDA

TP2006 TPAD14-OP-GPTP2006 TPAD14-OP-GP

1

RTC_DET# 25

(PDG#543016) Ensure that all I2C interface on-board terminations are pulled up to the same voltage rail as the device/end point.

TP2007 TPAD14-OP-GPTP2007 TPAD14-OP-GP

1

TP2010 TPAD14-OP-GPTP2010 TPAD14-OP-GP

1

TP2011 TPAD14-OP-GPTP2011 TPAD14-OP-GP

1

TP2012 TPAD14-OP-GPTP2012 TPAD14-OP-GP

1

FFS_INT2 67

DVT1 add FFS 2/18

TP2015TPAD14- OP-GPTP2015TPAD14 -OP-GP

KB_DET# 65

CAMERA_DET # 55

I2C1_SCL I2C1_SDA

DGPU_PW R_EN 85,86

BIOS strap pin:

10KR2J-3-GP

TPM_SELECT

10KR2J-3-GP

PROJECT_ID2

X

0

1

R2022

R2020

PROJECT Strap pin

Turis

Vegas

KBL

SKL

GPP_C11

BOARD_ID2

0

1

VRAM_2G

VRAM_4G

3

3D3V_S0

12

R2023

R2023 10KR2J-3-GP

10KR2J-3-GP

12

10KR2J-3-GP

R2024

BIOS strap pin:

BIOS VRAM Size Strap pin

4G

2G

GPP_B17

VRAM_ID1

0

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O .C.

Taipei Hsie n 221, Taiwan, R.O .C.

Title

Size Documen t Number Rev

A2

Date: Sheet of

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O .C.

CPU_(LPSS/ISH)

Vegas SKL/KBL-U

1

A00

20 105Monday, June 27, 2016

A00

B B

VRAM_ID1

A A

5

4

5

4

3

2

1

Main Func = PCH

RTC_AUX_S5

+V1.00A_SIP

D D

+VCCPRIM_CORE

2.57A

EC2101

C2120

SC

12

C C

SC

12

D1U25V2KX-L-GP

1U10V2KX-1GP

DY

+VCCMPHYGTAON_1P0_LS_SIP

+V3.3A_SIP

+VCCMPHYGTAON_1P0_LS_SIP

+VCCDSW _1P0

+V1.00A_SIP

+VCCAMPHYPLL_1P0

+VCCAPLL_1P0

+V1.00A_SIP

+VCCPDSW_3P3

+VCCPAZIO

R2101

1 2

0R0402-PAD

+V3.3A_SIP

+V3.3A_SIP +V1.00A_SIP

CPU1O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0

N16

VCCMPHYGT_1P0

N17

VCCMPHYGT_1P0

P15

VCCMPHYGT_1P0

P16

VCCMPHYGT_1P0

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0

Y18

VCCPRIM_1P0

AD17

VCCDSW_3P3

AD18

VCCDSW_3P3

AJ17

VCCDSW_3P3

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3

AK20

VCCPRIM_1P0

N18

VCCAPLLEBB_1P0

SKYLAKE-U-GP

071.SKYLA.000U

CPU POWER 4 OF 4

SKYLAKE_ULT

1.8V Only

15 OF 20

VCCPGPPA

VCCPGPPB VCCPGPPC VCCPGPPD

VCCPGPPE

VCCPGPPF VCCPGPPG

VCCPRIM_3P3 VCCPRIM_1P0

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC VCCRTC

DCPRTC VCCCLK1 VCCCLK2 VCCCLK3 VCCCLK4 VCCCLK5 VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19 T1 AA1 AK17 AK19

BB14 BB10 A14 K19 L21 N20 L19 A10 AN11

AN13

+V3.3A_SIP

VCCRTCEXT

V0.85A_VID1

+V1.8A_SIP

+V3.3A_SIP

+V1.00A_SIP +V1.8A_SIP +V3.3A_SIP

+VCCPRTC_3P3

C2112 SCD1U16V2KX-3GPC2112 SCD1U16V2KX-3GP

1 2

+V1.00A_SIP

TP2102 TPAD14-OP-GPTP2102 TPAD14-OP-GP

1

C2118

C2119

SCD1U16V2KX-3GP

12

DY

C2118

C2117

SCD1U16V2KX-3GP

SC1U10V2KX-1GP

12

CAP need close to VCCRTC

+VCCPRTC_3P3RTC_AUX_S5

R2107

1 2

0R0603-PAD-2-GP-U

R2112

1 2

0R3J-0-U-GP

R2108

1 2

0R3J-0-U-GP

+VCCAMPHYPLL_1P0+VCCMPHYGTAON_1P0_LS_SIP

+VCCAPLL_1P0+V1.00A_SIP

B B

C2

C2106

C2107

SC1U10V2KX-1GP

12

DY

C2107

SC1U10V2KX-1GP

DY

Layout Note:

22uF: C2113 near K15

SC1U10V2KX-1GP

105

12

DY

+VCCAMPHYPLL_1P0 +V1.00A_SIP+VCCAPLL_1P0

A A

SC22U6D3V3MX-1-GP

C2

C2 113

113

12

DY

5

C2110

C2109

SC1U10V2KX-1GP

12

C2111

SCD1U16V2KX-3GP

12

1uF:

SCD1U16V2KX-3GP

C2105 near V19 C2106 near AK17 C2107 near AG15 C2109 near Y16 C2110 near T16 C2111 near AJ19

Layout Note:

22uF:

SC22U6D3V3MX-1-GP

C2114

12

DY

C2113 near K15

4

C2108

SC1U10V2KX-1GP

12

+V1.00A_SIP

SC1U10V2KX-1GP

C2116

12

DY

12

C2103

SC1U10V2KX-1GP

12

SC22U6D3V3MX-1-GP

C2122

3

C2

Layout Note:

+V1.00A_SIP+VCCDSW _1P0+V1.8A_SIP+V3.3A_SIP

C2101

SC1U10V2KX-1GP

12

DY

Layout Note:

1uF: C2116 near A10 22uF: C2115 near K19 C2119 near N20 C2122 near L19

C2104

SC1U10V2KX-1GP

DY

C2121

SC1U10V2KX-1GP

12

Layout Note:

1uF: C2101 near AB19 C2104 near K17 C2116 near A10 C2121 near AL1

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(POWER1)

Vegas SKL/KBL-U

21 105Friday, June 24, 2016

1

A00

5

WWW.AliSaler.Com

4

3

2

1

Main Func = PCH

D D

CPU1T

AW69

RSVD#AW69

AW68

C C

AU56

AW48

U12 U11 H11

C7

SKYLAKE-U-GP

RSVD#AW68 RSVD#AU56 RSVD#AW48 RSVD#C7 RSVD#U12 RSVD#U11 RSVD#H11

SKYLAKE_ULT

SPARE

20 OF 20

RSVD#F6

RSVD#E3 RSVD#C11 RSVD#B11 RSVD#A11 RSVD#D12 RSVD#C12 RSVD#F52

F6 E3 C11 B11 A11 D12 C12 F52

071.SKYLA.000U

B B

Wistron Corporation

A A

Title

CPU_(RSVD)

5

Size Document Number Rev

A4

Date: Sheet of

4

3

Date: Sheet of

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Vegas SKL/KBL-U

22 105Thursday, June 16, 2016

1

A00

5

4

3

2

1

Main Func = PCH

CPU1P

GND 1 OF 3

TPAD14-OP-GP

TP2307

D D

TP2301

C C

B B

NCTF_A5

1

NCTF_A70

1

TPAD14-OP-GP

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

VSS

AA65

VSS

AA68

VSS

AB15

VSS

AB16

VSS

AB18

VSS

AB21

VSS

AB8

VSS

AD13

VSS

AD16

VSS

AD19

VSS

AD20

VSS

AD21

VSS

AD62

VSS

AD8

VSS

AE64

VSS

AE65

VSS

AE66

VSS

AE67

VSS

AE68

VSS

AE69

VSS

AF1

VSS

AF10

VSS

AF15

VSS

AF17

VSS

AF2

VSS

AF4

VSS

AF63

VSS

AG16

VSS

AG17

VSS

AG18

VSS

AG19

VSS

AG20

VSS

AG21

VSS

AG71

VSS

AH13

VSS

AH6

VSS

AH63

VSS

AH64

VSS

AH67

VSS

AJ15

VSS

AJ18

VSS

AJ20

VSS

AJ4

VSS

AK11

VSS

AK16

VSS

AK18

VSS

AK21

VSS

AK22

VSS

AK27

VSS

AK63

VSS

AK68

VSS

AK69

VSS

AK8

VSS

AL2

VSS

AL28

VSS

AL32

VSS

AL35

VSS

AL38

VSS

AL4

VSS

AL45

VSS

AL48

VSS

AL52

VSS

AL55

VSS

AL58

VSS

AL64

VSS

SKYLAKE-U-GP

071.SKYLA.000U

GND 1 OF 3

SKYLAKE_ULT

16 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

TP2305

NCTF_BA1

1

TPAD14-OP-GP

CPU1Q

AT63

VSS

AT68

VSS

AT71

VSS

AU10

VSS

AU15

VSS

AU20

VSS

AU32

VSS

AU38

VSS

AV1

VSS

AV68

VSS

AV69

VSS

AV70

VSS

AV71

VSS

AW10

VSS

AW12

VSS

AW14

VSS

AW16

VSS

AW18

VSS

AW21

VSS

AW23

VSS

AW26

VSS

AW28

VSS

AW30

VSS

AW32

VSS

AW34

VSS

AW36

VSS

AW38

VSS

AW41

VSS

AW43

VSS

AW45

VSS

AW47

VSS

AW49

VSS

AW51

VSS

AW53

VSS

AW55

VSS

AW57

VSS

AW6

VSS

AW60

VSS

AW62

VSS

AW64

VSS

AW66

VSS

AW8

VSS

AY66

VSS

B10

VSS

B14

VSS

B18

VSS

B22

VSS

B30

VSS

B34

VSS

B39

VSS

B44

VSS

B48

VSS

B53

VSS

B58

VSS

B62

VSS

B66

VSS

B71

VSS

BA1

VSS

BA10

VSS

BA14

VSS

BA18

VSS

BA2

VSS

BA23

VSS

BA28

VSS

BA32

VSS

BA36

VSS

F68

VSS

BA45

VSS

SKYLAKE-U-GP

071.SKYLA.000U

GND 2 OF 3

SKYLAKE_ULT

17 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

TPAD14-OP-GP

NCTF_BB70

TP2304

1

[#543016 Rev0.9]

CPU1R

GND 3 OF 3

F8

VSS

G10

VSS

G22

VSS

G43

VSS

G45

VSS

G48

VSS

G5

VSS

G52

VSS

G55

VSS

G58

VSS

G6

VSS

G60

VSS

G63

VSS

G66

VSS

H15

VSS

H18

VSS

H71

VSS

J11

VSS

J13

VSS

J25

VSS

J28

VSS

J32

VSS

J35

VSS

J38

VSS

J42

VSS

J8

VSS

K16

VSS

K18

VSS

K22

VSS

K61

VSS

K63

VSS

K64

VSS

K65

VSS

K66

VSS

K67

VSS

K68

VSS

K70

VSS

K71

VSS

L11

VSS

L16

VSS

L17

VSS

SKYLAKE-U-GP

071.SKYLA.000U

SKYLAKE_ULT

18 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(VSS)

Vegas SKL/KBL-U

23 105Thursday, June 16, 2016

1

A00

5

WWW.AliSaler.Com

Main Func = KBC

1D0V_S5

R2402

1 2

0R0402-PAD

+VCCSTG

R2440

1 2

DY

0R2J-2-GP

+V1.00U_CPU

R2492

1 2

DY

0R2J-2-GP

D D

3D3V_S5_KBC

C C

EC2401

12

DY

U16V2KX-3GP

SCD1

EC LCD test

EC_BRIGHTNESS55

B B

Layout Note:

Need very close to EC

KSI7

R2403 10KR2J-3-GPR2403 10KR2J-3-GP

1 2 1 2 1 2 1 2

DGPU_PWROK

R2404 10KR2J-3-GPR2404 10KR2J-3-GP R2405 10KR2J-3-GPR2405 10KR2J-3-GP R2406 10KR2J-3-GPR2406 10KR2J-3-GP

R2407 10KR2J-3-GPR2407 10KR2J-3-GP R2408 10KR2J-3-GPR2408 10KR2J-3-GP R2409 10KR2J-3-GPR2409 10KR2J-3-GP R2413 10KR2J-3-GPR2413 10KR2J-3-GP

R2425 100KR2J-1-GPR2425 100KR2J-1-GP R2426 100KR2J-1-GPR2426 100KR2J-1-GP R2433 100KR2J-1-GPR2433 100KR2J-1-GP R2447 100KR2J-1-GPR2447 100KR2J-1-GP

R2454 100KR2J-1-GPR2454 100KR2J-1-GP R2459 100KR2J-1-GPR2459 100KR2J-1-GP R2460 100KR2J-1-GPR2460 100KR2J-1-GP R2467 100KR2J-1-GPR2467 100KR2J-1-GP

PLT_RST#17,31,40,55,61,68,76,91

Layout Note:

Need very close to EC

KSI4 KSI2 KSI1

KSI0 KSI3 KSI5 KSI6

KSO5 KSO7 KSO12 KSO16

KSO15 KSO13 KSO11 KSO10

delay 10ms; RESET_OUT# assert.

LCD_TST_R55

3D3V_S5_KBC

SPI_CLK_ROM18,25

SPI_SO_ROM18,25

SPI_SI_ROM18,25

R2456

1 2

0R0402-PAD

R2419

1 2

0R0402-PAD

3D3V_S5 3D3V_S5_KBC

EC_VTT

12

C2406

U16V2KX-3GP

SCD1

R2468 100KR2J-1-GPR2468 100KR2J-1-GP

1 2

R2477 100KR2J-1-GPR2477 100KR2J-1-GP

1 2

R2480 100KR2J-1-GPR2480 100KR2J-1-GP

1 2

R2482 100KR2J-1-GPR2482 100KR2J-1-GP

1 2

R2483 100KR2J-1-GPR2483 100KR2J-1-GP

1 2

R2484 100KR2J-1-GPR2484 100KR2J-1-GP

1 2

R2488 100KR2J-1-GPR2488 100KR2J-1-GP

1 2

R2494 100KR2J-1-GPR2494 100KR2J-1-GP

1 2

R2410

12

SC220P50V2KX-3GP

EVT1 2014/10/20

3D3V_S5_KBC

1 2

DY

1 2

EC_AGND

R2450

R2450 100KR2J-1-GP

100KR2J-1-GP

KSO9

R2449

R2449 100KR2J-1-GP

100KR2J-1-GP

C2402

4 5 3 2 1

SRN10J-1-GP

LCD_TST

12

C2421

SCD1U16V2KX-3GP

KSO14 KSO0 KSO2 KSO1

KSO3 KSO8 KSO6 KSO4

DY

1 2

RN2401

PM_LAN_ENABLE31

ALL_SYS_PWRGD17,40

3D3V_S5

3D3V_S5_KBC

12

C2420

C2412

SCD1U16V2KX-3GP

SIO_PWRBTN#17 PCH_RSMRST#17

LPC_LAD[3..0]18,68,91

R2510

12

10KR2F-2-GP

DY

SATA_LED#64

RTCRST_ON18

SIO_SLP_S4#17,40,44,51

AC_DIS43,44

INT_TP#4,65

RESET_OUT#17,26,40

SUS_CLK18

12

C2411

DY

SCD1U16V2KX-3GP

KSO[0..16]65

KSI[0..7]65

CLK_TP_SIO65

DAT_TP_SIO65

LPC_LFRAME#18,68,91

CLK_PCI_LPC_MEC18

BLON_OUT_R BLON_OUT_R_R

R2491

1 2

0R0402-PAD

0R0402-PAD R2481 0R0402-PADR2481 0R0402-PAD

C2425

SC12P50V2JN-3GP

DY

1 2

12

C2415

C2416

DY

SCD1U16V2KX-3GP

SC2D2U10V3KX-1GP

CLKRUN#18,91

EC_SPI_CLK EC_SPI_MISO

6

EC_SPI_MOSI

7 8

SPI_CS_ROM_N018,25

ME_SUS_PWR_ACK17

R2446

1 2

0R0603-PAD

12

C2410

C2413

C2414

DY

SCD1U16V2KX-3GP

CAP_LED#

PCH_PLTRST#_EC

SERIRQ18,91

SIO_EXT_SMI# TP_EN#

SIO_RCIN#18

SIO_EXT_SCI#

SATA_LED# EC_SPI_CS0#

R2490

1 2

0R0402-PAD

12

DY

R2475 0R2J-2-GPDYR2475 0R2J-2-GP

PTP_INT#_EC

R2431

1 2

LAN_EN

0R0402-PAD

USB_EN# RUNPWROK

12

XTAL2

R2428

12

XTAL1

0R2J-2-GP

X2401

1 2

DY

XTAL-32D768KHZ-89-GP

082.30003.0201

Microchip: Use CL=9p Xtal󶁜C = 10p

12

SCD1U16V2KX-3GP

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

EC_SPI_CLK EC_SPI_MOSI EC_SPI_MISO

C2417

DY

C2428

DY

1 2

DY

1 2

12

SC2D2U10V3KX-1GP

R2458

R2458 0R2J-2-GP

0R2J-2-GP

XTAL_KBC_2

4

If don't need RTC alarm wake up, can change to 3D3V_AUX_S5

RTC_AUX_S53D3V_AUX_S5

R2473

DY

0R2J-2-GP

1 2

ECVBAT

12

KBC24

2

GPIO02 7/KSO00 /PVT_IO 1

14

GPIO01 5/KSO01 /PVT_CS #

15

GPIO01 6/KSO02 /PVT_SC LK

16

GPIO01 7/KSO03 /PVT_IO 0

37

GPIO04 5/BCM_INT 1#/KSO0 4

38

GPIO04 6/BCM_DA T1/KSO0 5

39

GPIO04 7/BCM_CL K1/KSO0 6

50

GPIO02 5/KSO07 /PVT_IO 2

46

GPIO05 5/PWM2/K SO08/PV T_IO3

68

GPIO10 2/KSO09 /CR_STR AP

72

GPIO10 6/KSO10

74

GPIO11 0/KSO11

75

GPIO11 1/KSO12

76

GPIO11 2/PS2_C LK1A/KS O13

77

GPIO11 3/PS2_D AT1A/KS O14

86

GPIO12 5/KSO15

92

GPIO13 2/KSO16

93

GPIO14 0/KSO17

98

GPIO14 3/KSI0/D TR#

99

GPIO14 4/KSI1/D CD#

6

GPIO00 5/SMB00_ DATA/SMB 00_DAT A18/KSI 2

7

GPIO00 6/SMB00_ CLK/SMB0 0_CLK1 8/KSI3

104

GPIO14 7/KSI4/D SR#

105

GPIO15 0/KSI5/R I#

107

GPIO15 1/KSI6/R TS#

108

GPIO15 2/KSI7/C TS#

78

GPIO11 4/PS2_C LK0

79

GPIO11 5/PS2_D AT0

52

GPIO02 6/PS2_C LK1B

88

GPIO12 7/PS2_D AT1B

59

GPIO04 0/LAD0

60

GPIO04 1/LAD1

61

GPIO04 2/LAD2

62

GPIO04 3/LAD3

58

GPIO04 4/LFRAME #

56

GPIO06 4/LRESE T#

57

GPIO03 4/PCI_C LK

63

GPIO06 7/CLKRUN#

55

GPIO06 3/SER_I RQ

10

GPIO01 1/SMI#/EMI _INT#

49

GPIO06 0/KBRST

53

GPIO06 1/LPCPD #

66

GPIO10 0/EC_SC I#

32

GPIO12 6/SHD_SC LK

28

GPIO13 3/SHD_IO 0

29

GPIO13 4/SHD_IO 1

30

GPIO13 5/SHD_IO 2

31

GPIO13 6/SHD_IO 3

27

GPIO12 3/SHD_CS #

67

GPIO10 1/SPI_C LK

69

GPIO10 3/SPI_I O0

71

GPIO10 5/SPI_I O1

42

GPIO05 2/SPI_I O2

33

GPIO06 2/SPI_I O3

3

GPIO00 1/SPI_C S#/32KHZ _OUT

13

RESET_ IN#/GPIO 014

48

GPIO05 7/VCC_P WRGD

73

GPIO10 7/RESET _OUT#

125

XTAL2

123

XTAL1

MEC1404-NU-GP

071.01404.000E

C2424

SC12P50V2JN-3GP

1 2

R2472

R2472 0R0402-PAD

0R0402-PAD

VSS_VBAT

124

1 2

0R0402-PAD

122

84

R2445

VBAT

MEC1404

43

103

VTR_33 _18

VTR5VTR19VTR

VTR65VTR82VTR

GPIO00 7/SMB01_ DATA/SMB 01_DAT A18

GPIO01 0/SMB01_ CLK/SMB0 1_CLK1 8

GPIO01 2/SMB02_ DATA/SMB 02_DAT A18

GPIO01 3/SMB02_ CLK/SMB0 2_CLK1 8

GPIO13 0/SMB03_ DATA/SMB 03_DAT A18

GPIO13 1/SMB03_ CLK/SMB0 3_CLK1 8

GPIO14 1/SMB04_ DATA/SMB 04_DAT A18

GPIO14 2/SMB04_ CLK/SMB0 4_CLK1 8

GPIO05 0/TACH0 GPIO05 1/TACH1

GPIO05 3/PWM0 GPIO05 4/PWM1

GPIO05 6/PWM3 GPIO03 0/BCM_INT 0#/PWM4 GPIO03 1/BCM_DA T0/PWM5 GPIO03 2/BCM_CL K0/PWM6

GPIO00 2/PWM7

GPIO15 7/LED0/T ST_CLK _OUT

GPIO15 6/LED1 GPIO10 4/LED2

GPIO11 6/TFDP_ DATA/UAR T_RX

GPIO11 7/TFDP_ CLK/UART _TX

GPIO03 5/SB-TSI _CLK

GPIO03 3/PECI_ DAT/SB_ TSI_DA T

VREF_C PU

GPIO14 5/ICSP_ CLOCK

GPIO14 6/ICSP_ DATA

ICSP_MC LR

BGPO/GP IO004

SYSPWR _PRES/G PIO003

VCI_OUT /GPIO03 6 VCI_IN1 #/GPIO1 62 VCI_IN0 #/GPIO1 63

VCI_OV RD_IN/GP IO164

GPIO16 0/DAC_0

GPIO16 1/DAC_1

DAC_VR EF

GPIO12 4/CMP_VO UT0

GPIO02 0/CMP_VI N0

GPIO16 5/CMP_VR EF0 GPIO12 0/CMP_VO UT1

GPIO02 1/CMP_VI N1

GPIO16 6/CMP_VR EF1/UART _CLK

GPIO02 4/CMP_ST RAP0

GPIO02 3/ADC6/A 20M

GPIO02 2/ADC5 GPIO15 3/ADC4 GPIO15 4/ADC3 GPIO15 5/ADC2 GPIO12 2/ADC1 GPIO12 1/ADC0

ADC_VR EF

VR_CAP18VSS17VSS51AVSS

VSS

VSS64VSS

112

100

EC_AGND

VR_CAP

12

C2418

C2418 SC1U10V2KX-1GP

SC1U10V2KX-1GP

Layout Note:

EC_AGND

Connect GND and AGND planes via either 0R resistor or connect directly.

3D3V_S5_KBC

0R0402-PAD

R2462

BOARD_ID

1 2

12

C2423

SCD1U16V2KX-3GP

3D3V_AUX_KBC_33

54

SMBDA1

8

SMBCLK1

9

SMBDA2

11

SMBCLK2

12 89

L_BKLT_EN_EC

91

GPIO141/SMB04_DATA/SMB04_DATA18

96

PBAT_PRES#

97

FAN1_TACH

40 41

44 45

DGPU_PWROK_KBC

47

GPIO030/BCM_INT0#/PWM4

34 35 36 4

BAT1_LED#

1

BAT2_LED#

106

SIO_SLP_S3#_R

70 80

81 90

94 95 101

102 87

119 120 121 126 127 128

23 24 22

85 20 25

83 21 26

118 117 116 109 110 111 113 114 115

1 2

PTP_DIS# PECI_EC

EC_VTT ICSP_CLOCK

ICSP_DATA ICSP_CLR

EC_MUTE# +3VLP

ALWON VCI_IN1# POWER_SW_IN# ACAV_IN

LCD_VCC_TEST_EN_R

1 2

C2429SCD1U16V2KX-3GP C2429SCD1U16V2KX-3GP

CMP_VOUT0 CMP_VIN0

R2470 0R0402-PADR2470 0R0402-PAD

VCREF0 CMP_VOUT1 LCD_TST CMP_STRAP0

PANEL_BKEN_EC BLON_OUT_R

R2497 0R2J-2-GPR2497 0R2J-2-GP

1 2

MODEL_ID I_ADP BOARD_ID I_SYS I_BATT

3D3V_S5_KBC

C2435

EC_AGND

C2422

SCD1U16V2KX-3GP

12

CMP_STRAP0

EC_AGND

R2474

0R0402-PAD

1 2

R2486 0R2J-2-GPR2486 0R2J-2-GP

SC100P50V2JN-3GP

C2405

12

DY

R2469 0R0402-PADR2469 0R0402-PAD

12

R2495 0R2J-2-GPR2495 0R2J-2-GP

1 2

R2421

330R2J-3-GP

Need very close to ECALL_SYS_PWRGD assert,

12

SC2200P50V2KX-2GP

3D3V_S5_KBC

BOARD_ID_R

12

C2408

R2427

OPS

0R2J-2-GP

1 2

R2437

R2437 43R2J-GP

43R2J-GP

12

PANEL_BKEN_EC

R2493

R2493 10KR2F-2-GP

10KR2F-2-GP

1 2

EC_AGND

SCD1U16V2KX-3GP

12

3

3D3V_S5

12

R2443

R2443 10KR2F-2-GP

10KR2F-2-GP

PCB_REV

12

R2444

R2444 100KR2F-L1-GP

100KR2F-L1-GP

TP2401 TPAD14-OP-GPTP2401 TPAD14-OP-GP

1

PBAT_PRES# 43,44

1

TPAD14-OP-GP

TP2403

Need very close to EC

ECVBAT

100KR2J-1-GP

EC_MUTE# 27

1 2

ALWON 40

add LCD_VCC_TEST_EN

ACOK_IN 17,44

for customer request DVT1 3/1

LCD_VCC_TEST_EN 55 FAN1_DAC_1 26

3D3V_S5_KBC

CMP_VOUT0 26 CMP_VIN0_R 26

GPU_PWR_LEVEL 79

SIO_EXT_WAKE# 20

AD_IA 44

R2471

12

DY

0R2J-2-GP

I_SYS

12

C2427

SC2200P50V2KX-2GP

EC_AGND

I_BATT

12

C2441

SC2200P50V2KX-2GP

EC_AGND

LCD_VCC_TEST_EN_R

GPIO030/BCM_INT0#/PWM4

R2424

20KR2F-L-GP

R2448

10KR2F-2-GP

CMP_VIN0_R 26

P_SYS 44,46

boost_mon 44

Layout Note:

100.0K

100.0KReserved 174.0K

3D3V_S0

3D3V_AUX_S5

Vref = 1.117 temp around 85

1 2

12

DY

M00 (SA) X01 (SB) X02 (SC) X03(SD)

A00 (1) Reserved Reserved 1.65V Reserved 1.358V100.0K 143.0K

Reserved

SMBDA1 43,44 SMBCLK1 43,44

SYS_PWROK 17

LID_CL_SIO# 64 BKLGT_PWM 65

BEEP 27 DGPU_PWROK 19,79,85

EC_WAKE# 17 PS_ID 43 PCIE_WAKE# 31

SIO_SLP_S3# 17,27,40,51

ME_FWP_EC 19

HOST_DEBUG_TX 61

H_PECI 4

R2452

For T8 TEMP test

R2422

12

330R2J-3-GP

R2423

12

330R2J-3-GP

Need very close to EC

10.0K

20.0K

33.0K

47.0K

64.9K

76.8

100.0K

R2430

R2430 10KR2J-3-GP

10KR2J-3-GP

1 2

R2461 0R2J-2-GP

1 2

DY

KA

D2403

RB751V-40H-GP

83.R2004.G8F

R2487 0R2J-2-GP

1 2

DY

R2496 0R2J-2-GP

1 2

DY

C2409

C2409 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

I_SYS LCD_VCC_TEST_EN

VOLTAGEPULL-HIGH RESISTORPULL-LOW RESISTORPCB VERSION A/D(PIN98)

FAN_TACH1 26

SIO_SLP_S3# 17,27,40,51

LCD_VCC_TEST_EN 55

3D3V_AUX_S5

+3VLP

R2498

0R2J-2-GP

1 2

DY

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.204V

1.048V215.0K10 0.0K

12

R2455

R2455 100KR2J-1-GP

100KR2J-1-GP

1 2

R2453

R2453 1KR2J-1-GP

1KR2J-1-GP

L_BKLT_EN8

BLON_OUT

100KR2J-1-GP

R2485

2

D2401

3

12

BAT54C-7-F-3-GP

75.00054.E7D

DY

2nd = 83.R2003.W81

3rd = 75.00054.A7D

TOUCH_PANEL_INTR#

Touch Panel PH internally.

R2401

1 2

0R2J-2-GP

DY

R2435

1 2

DY

0R2J-2-GP

100KR2J-1-GP

1

2

64K9R2F-1-GP

MODEL_ID

C2407

SCD1U16V2KX-3GP

BLON_OUT 55

L_BKLT_EN_EC

12

R2436

DY

BLON_OUT_R

Power Switch Logic(PSL)

3D3V_S5

R2442

12

MODEL_ID

12

R2441

R2441 100KR2F-L1-GP

100KR2F-L1-GP

1 2

EC_AGND

R2429 10KR2J-3-GP

1 2

DY

L_BKLT_EN 8

KBC_PWRBTN#64

MODEL_ID_DET(GPIO07) PULL-HIGH RESISTORPULL-LOW RESISTOR

Vegas_SKL_UMA

Vegas_KBL_UMA

Turis_SKL_UMA

Turis_KBL_UMA

Vegas_SKL_DIS

Vegas_KBL_DIS

Turis_SKL_DIS

Turis_KBL_DIS

3D3V_S0

3D3V_S5 3D3V_S5

CHG_AMBER_LED#64

Q2412 and Q2413 merge

3D3V_S0

CAP_LED#

3D3V_S0

R2432

1 2

1KR2J-1-GP

SMBCLK1 SMBDA1

PBAT_PRES# SIO_EXT_SCI# SIO_EXT_SMI#

BAT1_LED#

R2489

R2489 100KR2J-1-GP

100KR2J-1-GP

1 2

S

G

Q2414

100.0K

R2415 10KR2J-3-GPR2415 10KR2J-3-GP

R2457 0R2J-2-GP

Q2412

1 2 3 4

2N7002KDW-GP

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

D

2ND = 84.2N702.031

RN2402

SRN4K7J-8-GP

1 2

R2411 0R0402-PADR2411 0R0402-PAD

1 2

R2412 0R0402-PADR2412 0R0402-PAD

1 2 1 2

DY

6 5

2N7002K-2-GP

84.2N702.J31

3rd = 84.07002.I31

ECVBAT

R2451

R2451 100KR2J-1-GP

100KR2J-1-GP

1 2

1234

POWER_SW_IN#

12

1

VOLTAGE

3.0V10.0K(64.1002 5.6DL)

BAT2_LED#

3D3V_S5_KBC

2.702V

2.492V

2.001V

1.709V9 3.1K(64.93125 .6DL)

1.499V

1.099V100.0K

SIO_EXT_SCI#_R 16 SIO_EXT_SMI#_R 8

USB_OC3# 16

CAP_LED#_S 65

22.1K(64.22125 .6DL)

32.4K(64.32425 .6DL)

49.9K(64.49925 .6DL) 2 .201V

64.9K(64.64925 .6DL) 120K(64.12035. 6DL)

200K(64.20035. 6DL)

BATT_WHITE_LED# 64

C2426

C2426 SC1U10V2KX-1GP

SC1U10V2KX-1GP

TP_EN#65

LID_CL_SIO#

RN2405

1 2 3 4 5

SRN100KJ-5-GP

3D3V_S5

8 7 6

D2402

LID_CL_SIO#

K A

TOUCH_PANEL_INTR# 4,55

RB751V-40H-GP

83.R2004.G8F

PTP_DIS#

83.R2004.G8F

D2405

K A

PTP

RB751V-40H-GP

83.R2004.G8F

TP_LOCK# 65

Title

KBC SMSC 1404

Size Document Number Rev

Size Document Number Rev A1

A1

Monday, June 27, 2016

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Vegas SKL/KBL-U

24 105

R2479 0R0402-PADR2479 0R0402-PAD

1 2

3D3V_S5

1 2

R2434

R2434 100KR2J-1-GP

100KR2J-1-GP

USB_PWR_EN# 35

EC_GPIO47 High Active

CMP_VOUT1 CMP_VOUT1_R

R2420

1 2

0R0402-PAD

12

C2419

R2417

SCD0

100K

DY

R2J-1-GP

R2J-1-GP 1U50V2KX-1GP

1U50V2KX-1GP

A A

R2418

R2418 0R2J-2-GP

0R2J-2-GP

1 2

DY

Q2408

G

H_PROCHOT#_EC

R2416

1 2

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

D

0R0402-PAD

12

DY

5

DY

12

C2403

C2403 SC47P50V2JN-3GP

SC47P50V2JN-3GP

H_PROCHOT# 4,44,46

USB_EN#

4

3D3V_S5_KBC

R2478

R2478 100KR2J-1-GP

100KR2J-1-GP

EC_DEBUG

DY

R2414

1 2

4K7R2J-2-GP

HOST_DEBUG_TX E51_TXD_R

ICSP_CLOCK ICSP_DATA

ICSP_CLR

R2476 0R0402-PADR2476 0R0402-PAD

R2463 0R0402-PADR2463 0R0402-PAD

R2464 0R0402-PADR2464 0R0402-PAD R2466 0R0402-PADR2466 0R0402-PAD

R2465 0R0402-PADR2465 0R0402-PAD

DB3

7

3D3V_AUX_KBC_R ICSP_CLK_R

ICSP_DATA_R

ICSP_MCLR_R

3

1 2

3 4

EC_DEBUG

5 6 8

20.K0691.006

ACES-CON6-58-GP

SMBDA2

SMBCLK2

R2438

0R0402-PAD

R2439

0R0402-PAD

2

12

SML1_SMBDATA

SML1_SMBCLK

SML1_SMBDATA 18,79

SML1_SMBCLK 18,79

12 12

12

A00

5

Main Func = SPI Flash

4

3

2

1

D D

4K7R2J-2-GP

C C

SPI_CS_ROM_N018,24 SPI_SO_ROM18,24

R2507 10R2F-L-GPR2507 10R2F-L-GP

1 2

3D3V_S5_PCH

R2501

1 2

SPI_WP_ROM_R

SPI Flash ROM1(16M) for PCH

4

RN2501

RN2501 SRN4K7J-8-GP

SRN4K7J-8-GP

DY

1

2 3

8 7 6 5

3D3V_S5_PCH

SPI_HOLD_ROM_RSPI_SO_ROM_R SPI_CLK_ROM_R SPI_SI_ROM_R

SPI_WP_ROM_R

SPI25

1

CS#

2

SO/SIO1

3

SIO2

4

GND

MX25L12873FM2I-10G-GP

72.12873.001

VCC

SIO3

SCLK

SI/SIO0

C2501

SC10U10V5KX-2GP

C2501

3D3V_S5_PCH

12

DY

RN2503

1 2 3

RN2502

1 2 3

12

C2502

C2502 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SRN0J-6-GP

4

SRN0J-6-GP

4

SPI_CLK_ROM 18,24 SPI_SI_ROM 18,24

SPI_HOLD_ROM 18

SPI_WP_ROM 18

Main Func = RTC

B B

AFTP2502AFTP2502

RTC1

1

PWR

2

GND

NP1

NP2

BAT-40-42010-00211RHF-GP-U2

20.F2316.002

A A

5

+RTC_VCC

1

D2501

1

R2502

1KR2J-1-GP

1

AFTP2501AFTP2501

12

4

R2504

R2504 10MR2J-L-GP

10MR2J-L-GP

12

RTC_PWR

75.00040.07D

75.00040.07D 2nd = 75.00040.C7D

2nd = 75.00040.C7D

Q2505

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

2

BAS40C-2-GP

D

RTC_AUX_S5+RTC_VCC 3D3V_AUX_S5

3

12

C2503

DY

SCD22U10V2KX-1GP

Wistron Corporation

RTC_DET# 20

Title

Flash/RTC

Size Document Number Rev

Size Document Number Rev A4

A4

Monday, June 27, 2016

Date: Sheet of

3

Date: Sheet of

2

Flash/RTC

Vegas SKL/KBL-U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

25 105

1

5

WWW.AliSaler.Com

Main Func = Thermal Sensor

4

3

2

1

Fan controller1

AFTP2602AFTP2602 AFTP2603AFTP2603

D D

DY

C C

3D3V_S5_KBC

12

R2607

10KR2J-3-GP

CMP_VOUT024

DY

RESET_OUT#17,24,40

R2602

1 2

DY

0R2J-2-GP

THERM_SYS_SHDN#

R26120R0402-PAD R26120R0402-PAD

1 2

KBC T8

Q2602

G

DY

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

D

DY

12

C2610

SCD1U16V2KX-3GP

PURE_HW _SHUTDOWN# 40,79

FAN_TACH1_C

1

FAN_VCC1

1

FAN_TACH1 FAN_VCC1

12

EC2602

EC2601

SC10P50V2JN-4GP

SCD1U16V2KX-3GP

DY

Layout Note:

Signal Routing Guideline: Trace width = 15mil

FAN1_DAC_124

FAN_VCC1

Layout Note:

Need 10 mil trace width.

FAN_VCC1

SC4D7U6D3V3KX-GP

5V_S0

FAN_TACH124

R2605

0R2J-2-GP

1 2

DY

C2604

FAN_VCC1

12

DY

FAN261

FON#

1

FSM#

2

VIN

3

VOUT VSET4GND

APL5606AKI-TRG-GP

74.05606.A71

2rd = 74.02113.0E1

3rd = 74.03940.A71

R2606

1 2

0R0402-PAD

D2601

KA

DY

RB551V30-GP

83.R5003.H8H

change the fan define & connect P/N 020.F0283.0003 by Andy 1/27

GND GND GND

FAN_TACH1_C FAN_VCC1

12

C2603

DY

SC2200P50V2KX-2GP

8 7 6 5

ETY-CON3-11-GP

020.F0283.0003

AFTP2601AFTP2601

5V_S0

12

C2611

C2605

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP

FAN1

5 3 2

1

4

1

Close to KBC

B B

Close to Thermal sensor

3D3V_S5_KBC3D3V_AUX_S5

12

DY

R2609

24K9R2F-L-GP

12

R2610

NTC-100K-8-GP

12

R2608

R2608 25K5R2F-GP

25K5R2F-GP

C2612

12

SCD1U16V2KX-3GP

VD_IN1_C

VD_IN1 for system thermal sensor

CMP_VIN0_R 24

12

C2613

SC100P50V2JN-3GP

R2611

1 2

0R0402-PAD

thermistor

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

THERMAL NCT7718W/Fan

Size Document Number Rev

Size Document Number Rev A3

A3

Vegas SKL/KBL-U

Monday, June 27, 2016

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

26 105

1

A00

Main Func = Audio

5

4

3

2

1

3D3V_S0

R2731 0R0805-PADR27 31 0R 0805-PAD

D D

moat

C C

1D8V_S0

3D3V_S0

1 2

R2710 0R2J-2-GP

1 2

DY

AVDD2: +1.8VD@3246 +1.5VD@3234

1 2

25mA

1D8V_S0

R2726

1 2

0R0402-PAD

1.5A

5V_S0 +5V_PVDD

R2702

1 2

0R0805-PAD

R2704

1 2

0R0805-PAD

+3V_1D8V_AVDD

R2713

0R0402-PAD

12

C2715

AUD_AGND

Layout Note:

Close pin41

+3V_AVDD

CPVDD

C2714

12

C2701

SC4D7U6D3V 3KX-GP

Close pin36

SCD1U16V2KX-3GP

C2707

C2708

C2709

12

SCD1U16V2KX-3GP

C2709

12

SCD1U16V2KX-3GP

SC10U6D3V3MX-GP

Layout Note:

Close pin46

C2706

12

DY

SC10U6D3V3MX-GP

Speaker trace width >40mil @ 2W4ohm speaker power

12

C2721

SC4D7U6D3V3KX-GP

Close pin40

SCD1U16V2KX-3GP

+3V_AVDD

AUD_AGND AUD_AGND

Layout Note:

EC_MUTE#24

R2724

1 2

DY

0R2J-2-GP

C2712 SC10U6D3V3MX-GPC2712 SC10U6D3V3MX-GP

1 2

+3V_1D8V_AVDD

AUD_SPK_L+29

AUD_SPK_L-29 AUD_SPK_R-29 AUD_SPK_R+29

R2708

1 2

0R0402-PAD

TP2701

TPAD14-OP-G P

Azalia I/F EMI

HDA_CODE C_SDOUT HDA_CODE C_BITCLK

DMIC_DATA

12

EC2708

SC22P50V2JN-4GP

B B

A A

5

12

EC2701

EC2709

SC22P50V2JN-4GP

C2723

DMIC_DATA55

1 2

HDA_CODE C_SDOUT19

HDA_CODE C_BITCLK19

HDA_SDIN019

HDA_CODE C_SYNC19

R2728

SIO_SLP_S3#17,24,40,51

1 2

0R0402-PAD

DMIC_CLK55

SC22P50V2JN-4G P

Close pin3

4

Audio Codec Chip ALC3246

LINE1_VREFO_R29 LINE1_VREFO_L29

AUD_HP1_JAC K_L29 AUD_HP1_JAC K_R29

C2704

1 2

SC1U10V2KX-1G P

+5V_PVDD

AUD_SPK_L+ AUD_SPK_LAUD_SPK_RAUD_SPK_R+

+5V_PVDD

COMBO-GPI

1

SC4D7U6D3V 3KX-GP

R271422R2J -2-GP R271422R2 J-2-GP

1 2

R270522R2J -2-GP R270522R2 J-2-GP

1 2

12

LDO2_CAP

PD#

3D3V_S0

12

CPVDD

C2703

C2703 SC1U10V2KX-1G P

SC1U10V2KX-1G P

36

HDA27

CBP

37 38 39 40 41 42 43 44 45 46 47 48 49

+3V_AVDD

C2716

DMIC_DATA_R DMIC_CLK_R

1 2 1 2 1 2

HDA_CODE C_SYNC

R2729

R2729 0R2J-2-GP

0R2J-2-GP

DY

Q4009_G

G

S

R27190R 0402-PAD R27190R0402-PAD R27200R 0402-PAD R27200R0402-PAD R27180R 0402-PAD R27180R0402-PAD

Q2702

2N7002K-2-GP

CPVDD

CBP AVSS2 LDO2-CAP AVDD2 PVDD1 SPK-OUT-L+ SPK-OUT-LSPK-OUT-RSPK-OUT-R+ PVDD2 PDB SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC -CLK-IN GND

DVDD1GPIO0/DMIC-DATA122GPIO1/DMIC-CLK3DC_DET4SDATA-OUT5BCLK6LDO3-CAP7SDATA-IN8DVDD-IO9SYNC10I2C-DATA11I2C-CLK

ALC3246-CG-G P-U

C2717

12

SCD1U16V2KX-3GP

HDA_SDOU T_CODEC_ R HDA_BITCLK_C ODEC_R HDA_CODE C_SDIN0

1D8V_S5 1D 8V_S0

12

C2724

SCD1U16V2KX-3GP

D

3

CPVEE

CBN

34

35

CBN

CPVEE

071.03246.0003

DY

R2721

12

1D8V_EN#

32

33

HPOUT-L_PORT-I-L

HPOUT-R_PORT-I-R

DVSS

12

0R2J-2-GP

R2701

1 2

0R3J-0-U-G P

R2715

R2715 10KR2J-3-GP

10KR2J-3-GP

R2733

1 2

4K7R2J-2-GP

31

LINE1-VREFO-L

DY

30

LINE1-VREFO-R

SPDIFO/FRONT-JD_JD3/GPIO3

LDO3_CAP

C2718SC4D7U6D3V3KX-GP C2718SC4D7U6D3V 3KX-GP

12

150mA

12

C2705

12

C2702

SC2D2U10V3KX-1GP

SC4D7U6D3V3KX-GP

AUD_VREF

LDO1_CAP

25

26

27

28

29

VREF

AVSS1

AVDD1

LDO1-CAP

LINE2-L_PORT-E-L

MIC2-VREFO

LINE2-R_PORT-E-R

LINE1-L_PORT-C-L

LINE1-R_PORT-C-R

VD33STB

MIC2-CAP

MIC2-R_PORT-F-R/SLEEVE

MIC2-L_PORT-F-L/RING2

PCBEEP

MIC2/LINE2-JD_JD2

HP/LINE1-JD_JD1

12

+3V_AVDD

C2719SCD1U16V2KX-3GP C2719SCD1U16V2KX-3GP

12

S

12

C2722

SCD22U10V2KX- 1GP

1D8V_EN_R#

84.02130.031

84.02130.031 2nd = 84.00102.031

2nd = 84.00102.031 3rd = 84.03413.B31

3rd = 84.03413.B31

MIC2_VREFO 29

R2711

R2711 100KR2J-1-GP

100KR2J-1-GP

+5V_AVDD AUD_AGND

Q2701

DMP2130L-7-GP

D

G

AUD_AGND

24 23 22 21 20 19 18 17 16 15 14 13

D

1D8V_S01D8V_S5

V3D3_STB MIC_CAP

C2713 SC10U6D3V3MX-GPC2713 SC10U6D3V3MX-GP

AUD_PC_BEEP _3246 JDREF

R2707 20KR2F-L-GP

AUD_SENSE_A

12

C2725

SCD1U16V2KX-3GP

DY

SPKR19

C2710

SCD1U16V2KX-3GP

1 2

DY

1 2

R2709

200KR2F-L-GP

moat

BEEP24

12

C2711

LINE1_L 29 LINE1_R 29

SLEEVE 29 RING2 29

moat

1 2

R2703

R2703 0R0603-PAD

0R0603-PAD

12

Layout Note:

Place close to Pin 26

AUD_AGND

SC4D7U6D3V3KX-GP

moat

0R0402-PAD

1 2

R2723

1 2

0R0402-PAD

AUD_SENSE

Layout Note:

Place close to Pin 13

RN2701

2 3 1

SRN1KJ-7-G P

2

5V_S0+5V_AVDD

3D3V_S5

R2712

AUD_AGND

Layout Note:

AUD_PC_BEEP _R

AUD_AGND

AUD_SENSE 29

4

moat

EC2707 SCD1U25V2KX-GPEC2707 SCD1U25V2KX- GP

1 2

EC2706 SCD1U25V2KX-GPEC2706 SCD1U25V2KX- GP

1 2

EC2705 SCD1U25V2KX-GPEC2705 SCD1U25V2KX- GP

1 2

EC2704 SCD1U25V2KX-GPEC2704 SCD1U25V2KX- GP

1 2

EC2703 SCD1U25V2KX-GPEC2703 SCD1U25V2KX- GP

1 2

AUD_AGND

1 2

R2706 0R0603-P ADR 2706 0R0603-PAD

1 2

R2727 0R0603-P ADR 2727 0R0603-PAD

1 2

R2730 0R0603-P ADR 2730 0R0603-PAD

Layout Note:

AUD_AGND

Tied at point only under Codec or near the Codec

Width>40mil, to improve Headpohone Crosstalk noise Change it to sharp will be better. Add 2 vias (>0.5A) when trace layer change.

moat

R2722

100KR2J-1-GP

C2720

AUD_PC_BEEP _R

1 2

SCD1U16V2KX- 3GP

R2717

R2717 2K2R2J-2-GP

2K2R2J-2-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O .C.

Taipei Hsie n 221, Taiwan, R.O .C.

Vegas SKL/KBL-U

1

HDA_SPKR_R

KBC_BEEP_R

75.00054.E7D

75.00054.E7D 2nd = 83.R2003.W81

2nd = 83.R2003.W81 3rd = 75.00054.A7D

3rd = 75.00054.A7D

AUD_SENSE_A

+3.3VD@3234 follow Pin1 Power setting@3246

D2701

2

AUD_PC_BEEP _C

3

1

BAT54C-7-F- 3-GP

12

Title

Audio Codec ALC3246

Size Document N umber Rev

A2

Date: Sheet of

+3V_AVDD

12

A00

27 109Monday, June 27, 2016

A00

5

WWW.AliSaler.Com

D D

C C

4

3

2

1

(Blanking)

B B

Wistron Corporation

A A

Title

Size Document Number Rev

A4

5

A4

Date: Sheet of

4

3

Date: Sheet of

2

Vegas SKL/KBL-U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

(Reserved)

28 105Thursday, June 16, 2016

1

A00

5

Main Func = Audio

4

3

2

1

Layout Note:

Speaker trace width >40mil @ 2W4ohm speaker power

AUD_SPK_R+_C

12

AUD_SPK_R-_C

12

AUD_SPK_L+_C

12

AUD_SPK_L-_C

12

SC100P50V2JN-3GP

EC2906

EC2905

12

DY

R29040R0603-PAD-2-GP-U R29040R0603-PAD-2-GP-U R29030R0603-PAD-2-GP-U R29030R0603-PAD-2-GP-U

R29020R0603-PAD-2-GP-U R29020R0603-PAD-2-GP-U R29010R0603-PAD-2-GP-U R29010R0603-PAD-2-GP-U

SC100P50V2JN-3GP

12

R2919

10KR2J-3-GP

DY

LINE1-L_C

LINE1-L_R

AUD_SPK_R+27 AUD_SPK_R-27

AUD_SPK_L+27 AUD_SPK_L-27

RN2901

SRN2K2J-1-GP

2 3 1

4

R2908 10R2F-L-GPR2908 10R2F-L-GP

1 2

R2922 1KR2J-1-GPR2922 1KR2J-1-GP

1 2

R2912 4K7R2J-2-GPR2912 4K7R2J-2-GP

1 2

R2910 10R2F-L-GPR2910 10R2F-L-GP

1 2

R2921 1KR2J-1-GPR2921 1KR2J-1-GP

1 2

R2913 4K7R2J-2-GPR2913 4K7R2J-2-GP

1 2

12

EC2903

EC2901

SC1KP50V2KX-1GP

EC2903

EC2902

SC1KP50V2KX-1GP

12

EC2904

SC1KP50V2KX-1GP

AUD_HP1_JACK_L1

AUD_HP1_JACK_R1

SC100P50V2JN-3GP

EC2908

12

10KR2J-3-GP

R2920

DY

SC100P50V2JN-3GP

EC2907

12

DY

D D

C C

MIC2_VREFO27

RING227

AUD_HP1_JACK_L27

LINE1_L27

LINE1_VREFO_L27

AUD_HP1_JACK_R27

LINE1_R27

LINE1_VREFO_R27

SLEEVE27

C2907

C2908

1 2

SC4D7U6D3V3KX-GP

1 2

SC4D7U6D3V3KX-GP

Speaker

SPK1

1 2

3 4

ACES-CON4-29-GP

20.F1639.004

2nd = 20.F1804.004

AUD_SPK_L-_C AUD_SPK_L+_C AUD_SPK_R-_C

AUD_SPK_R+_C

R2906 0R0603-PAD-2-GP-UR2906 0R0603-PAD-2-GP-U

12

R2907 0R0603-PAD-2-GP-UR2907 0R0603-PAD-2-GP-U

12

R2909 0R0603-PAD-2-GP-UR2909 0R0603-PAD-2-GP-U

12

R2911 0R0603-PAD-2-GP-UR2911 0R0603-PAD-2-GP-U

12

5

6

CONN Pin Pin1 Pin2 Pin3 Pin4

AFTP2901AFTP2901

1

AFTP2902AFTP2902

1

AFTP2903AFTP2903

1

AFTP2904AFTP2904

1

Net name SPK_R+ SPK_RSPK_L+ SPK_L-

Universal Jack (Moved to I/O Board)

RING2_R AUD_PORTA_L_R_B

JACK_PLUG AUD_PORTA_R_R_B

SLEEVE_R

RING2_R 66

AUD_PORTA_L_R_B 66

JACK_PLUG 66

AUD_PORTA_R_R_B 66

SLEEVE_R 66

Delay circuit

B B

(JACK_PLUG_DET: on IO Board)

AUD_AGND AUD_AGND

JACK_PLUG

A A

5

4

3

2

R29230R0603-PAD-2-GP-U R29230R0603-PAD-2-GP-U

1 2

12

DY

AUD_AGND

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

Audio IO

Vegas SKL/KBL-U

Monday, June 27, 2016

10 mils10 mils

C2902

C2902 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

AUD_SENSE 27

29 105

1

A00

5

WWW.AliSaler.Com

D D

C C

4

3

2

1

(Blanking)

B B

Wistron Corporation

A A

Title

(Reserved)

Vegas SKL/KBL-U

Thursday, June 16, 2016

2

5

Size Document Number Rev

Size Document Number Rev A4

A4

A4 Date: Sheet of

Date: Sheet of

4

3

Date: Sheet of

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

30 105

1

A00

Dell Inspiron 15 3467,Inspiron 153567 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual