Dell Inspiron 14z-5423 Schematics

5

4

3

2

1

BMW Z4 14" Schematics Document

D D

Ivy/Sandy Bridge

Panther Point

2012-04-02

C C

DY : None Installed UMA: UMA only installed SG: PX solution installed.

B B

REV : A00

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Monday, April 02, 2012

Date: Sheet of

Cover Page

Cover Page BMW Z4 DIS

BMW Z4 DIS

Taipei Hsien 221, Taiwan, R.O.C.

1 105

1

A00

5

D D

VRAM(GDDR5)

128M x 16b x 4(1GB)

GDDR5

88,89

HDMI

C C

LCD

Camera

Internal Digital MIC

10/100 Lan

ATHEROS AR8162

Left side

RJ45

59

AMD

Thames Pro

51

49

31

USB3.0 / PowerShare

62

B B

Thermal

NUVOTON NCT7718W

Fan Control

GMT G991P11U

SMBUS

28

28 27

USB PowerShare

TI

TPS2541A

LPC debug port

KBC

NUVOTON

NPCE885P

Int. KB

62

71

83.84,85,86,87

TMDS

LVDS

USB2.0 x 1

PCIE x 1

USB3.0 x 1

USB2.0 x 1

LPC BUS

Touch PAD

6969

4

Block Diagram (Discrete / UMA)

Intel CPU

Ivy / Sandy Bridge

17W

BGA1023

4,5,6,7,8,9,10

DMIx4FDIx4x2

*1

PS2

SPI

I C

Flash ROM

2

PCH Panther Point

BGA989

14 USB 2.0/1.1 ports

4 USB 3.0 ports

High Definition Audio

60

8MB

Intel

HM77

6 SATA ports 8 PCIE ports

LPC I/F

ACPI 4.0a

17,18,19,20,21, 22,23,24,25

3

DDRIII 1600MHz Channel A

DDRIII 1600MHz Channel BPCIe x 8

USB2.0 x 1

PCIE x 1

USB2.0 x 1

HDA

USB3.0 x 1

USB2.0 x 1

SATA GenIII x 1

SATA GenII x 1

SATA GENIII x 1

DDRIII

Slot A

1600MHz

DDRIII

Slot B

1600MHz

Mini-Card

802.11a/b/g/n BT V4.0 combo

Mini-Card

mSATA

WWAN

Codec

IDT 92HD94

USB3.0 Redriver

TI SN65LVPE502RGER

CardReader

Realtek RTS5179

HDD

ODD

2

Project Code: 91.4UV01.001 PCB P/N : 48.4SB02.011 Revision : 11289-1

14

15

65

SIM

66

56

66

Daughter Board

Combo Jack

2CH Speaker ( 2W, 4ohm /channel )

Right side Debug Port

USB 3.0

Connector SD/SDHC/SDXC/SD UHS-I MMC/MMC+, MS/MS Pro

1

CHARGER

BQ24727

INPUTS

AD+

SYSTEM DC/DC

TPS51125RGER

INPUTS

DCBATOUT 5V_S5

CPU DC/DC

VT1318+VT1326

INPUTS

5V_S5

GFX DC/DC

VT1318+VT1323

INPUTS

5V_S5

SYSTEM DC/DC

VT386

INPUTS

5V_S5

SYSTEM DC/DC

VT385(DIS)/RT9026 VT386(UMA)/RT9026

INPUTS

DCBATOUT

26

SYSTEM DC/DC

RT8068A

INPUTS

3D3V_S5

SYSTEM DC/DC

APL5916

INPUTS

VCCP_CPU

VGA DC/DC

VT358

INPUTS OUTPUTS

5V_S5

VGA DC/DC

APL5930

INPUTS OUTPUTS

26

1D5V_S3 1V_VGA_S0

Switches

INPUTS OUTPUTS

1D5V_S3 5V_S5

3D3V_S5 3D3V_WLAN_AOAC 3D3V_S5 3D3V_VGA_S0

1D5V_S3 1D5V_VGA_S0

UMA/Discrete PCB LAYER

L1:Top L2:GND L3:Signal L4:Signal

OUTPUTS

BT+

OUTPUTS

5V_AUX_S5 3D3V_AUX_S5

3D3V_S5 15V_S5

OUTPUTS

VCC_CORE

OUTPUTS

VCC_GFXCORE

OUTPUTS

1D05V_PCH VCCP_CPU

OUTPUTS

1D5V_S3 0D75V_S0 DDR_VREF_S3

OUTPUTS

1D8V_S0

OUTPUTS

0D85_S0

VGA_CORE

1D5V_S0 5V_S0 3D3V_S03D3V_S5

1D8V_VGA_S01D8V_S0

L5:VCC L6:Signal L7:GND L8:Bottom

40

41

42,43

44

45

46

47

48

92

93

A A

DMB40

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

A2

5

4

3

2

*1: Transition minimized differential signaling

A2

BMW Z4 DIS

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Block Diagram

1

A00

2 105Friday, March 30, 2 012

A00

PCH Strapping

A

Name Schematics Notes

Chief River Schematic Checklist Rev.0_72

B

Sandy & Ivy Bridge Compatibility

C

Pin Name Configuration Schematic Notes

D

Chief River Schematic Checklist Rev.0_xx

E

SPKR

INIT3_3V# Weak internal pull-up. Leave as "No Connect".

4 4

INTVRMEN GNT3#/GPIO55

GNT2#/GPIO53 GNT1#/GPIO51

DF_TVS HAD_DOCK_EN#

/GPIO[33]

HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. HDA_SYNC GPIO15

3 3

Power Plane

5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 1V_S0 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE 1D8V_VGA_S0 3D3V_VGA_S0 1V_VGA_S0

2 2

5V_USBX_S3 1D5V_S3 DDR_VREF_S3

BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5

3D3V_LAN_S5 3.3V

3D3V_AUX_KBC DSW, Sx ON for supporting

3D3V_AUX_S5

1 1

The signal has a weak internal pull-down. If the signal is sampled high, this indicates that the system is strapped to the "No Reboot" mode (Panther Point will disable the TCO Timer system reboot feature).

Integrated 1 V VRMs is enabled when high, External when low. GNT[3:0]# functionality is not available on Mobile.

Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail.

DF_TVS needs to be pulled up to VccDFTERM power rail through 2.2 kOhms ±5% resistor. This signal controls the external Intel HD Audio docking isolation logic. This is

an active-low-signal. When deasserted the external docking switch is in isolate mode. When asserted the external docking switch electrically connects the Intel HD Audio dock signals to the corresponding Panther Point signals. This signal can instead be used as GPIO33.

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. Low (0)

Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High (1) Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality

Voltage DescriptionActice StatusPower Plane

5V

3.3V

1.8V

1.5V

1.05V 1V

0.85V

0.75V

0.3V to 1.3V 0 to 1.25V

1.8V

3.3V 1V

5V

1.5V

0.75V

6V-14.1V 6V-14.1V 5V 5V

3.3V

S0

S3

All S states

WOL_EN

G3, Sx

CPU Core Rail Graphics Core Rail

AC Brick Mode only

Legacy WOL

Deep Sleep states

Powered by Li Coin Cell in G3 and +V3ALW in Sx

DDR3 VREF

PROC_SELECT# & DF_TVS

VCCIO_SEL

VCCSA_VID[0:1]

Sandy Bridge + Ivy Bridge

Ivy Bridge

Sandy Bridge + Ivy Bridge

Ivy Bridge

Sandy Bridge + Ivy Bridge

Ivy Bridge

Sandy Bridge + Ivy Bridge

Ivy Bridge

Processor Strapping

Pin Name Strap Description

CFG[2]

CFG[4]

CFG[6:5]

Pair

0 1 2 3 4 5 6 7 8 9 10 11 12 13

PCI-Express Static Lane Reversal

PCI-Express Port Bifurcation Straps

Device USB3.0 port1, with Power Share Pair USB3.0 port2, debug port NC NC Touch Panel NC NC NC WWAN NC Card reader WLAN CAMERA NC

DDR3 VREF, M1 and M3 function are required.

No change.

Connect DF_TVS signal of the PCH to PROC_SELECT# of the processor through a 1K±5% series resistor. PROC_SELECT# also needs a 2.2K±5% pull up resistor to PCH VccDFTERM rail.

No change.

The POR for Ivy Bridge mobile parts is now 1.05 V. There is no longer a need for a separate VR for the processor at 1.0 V and the PCH at 1.05 V. A single VR may be shared for both.

No change.

VCCSA[0:1] are the select pin of VCCSA's power control.

No change.

Chief River Schematic Checklist Rev.0_72

Configuration (Default value for each bit is 1 unless specified otherwise)

1:

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Disabled - No Physical Display Port attached to

1:

Embedded DisplayPort. Enabled - An external Display Port device is

0:

connectd to the EMBEDDED display Port

11:

1x16 PCI Express 2 x8 - PCI Express

10:

Reserved

01:

1x8, 2x4 PCI Express

00:

PCIE Table SATA TableUSB Table

PCIE

Lane

1 2 3 4 5 6 7 8

Device

NC NC NC WLAN NC Onboard LAN NC NC

DMB40

Title

Size Document Number Rev

A3

Date: Sheet of

Default Value

1

11

HDD1

0

mSATA

1

NC

2

NC

3

ODD

4

NC

5

Table of Content

BMW Z4 DIS

POP Value

0

1

10

SATA Device

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

3 105Friday, March 30, 2012

A00

5

4

3

2

1

SSID = CPU

Layout Note:

Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.

D D

1 OF 9

CPU1A

DMI_TXN[3:0][19]

Layout Note:

DMI trace length 2000~8000mil

C C

Layout Note:

FDI trace length 2000~6500mil

B B

Layout Note:

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

VCCP_CPU

DMI_TXP[3:0][19]

DMI_RXN[3:0][19]

DMI_RXP[3:0][19]

FDI_TXN[7:0][19]

FDI_TXP[7:0][19]

FDI_FSYNC0[19] FDI_FSYNC1[19]

FDI_INT[19] FDI_LSYNC0[19]

FDI_LSYNC1[19]

R402 24D9R2F-L-GPR402 24D9R2F-L-GP

1 2

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT FDI_LSYNC0

FDI_LSYNC1

DP_COMP

M2

DMI_RX#0

P6

DMI_RX#1

P1

DMI_RX#2

P10

DMI_RX#3

N3

DMI_RX0

P7

DMI_RX1

P3

DMI_RX2

P11

DMI_RX3

K1

DMI_TX#0

M8

DMI_TX#1

N4

DMI_TX#2

R2

DMI_TX#3

K3

DMI_TX0

M7

DMI_TX1

P4

DMI_TX2

T3

DMI_TX3

U7

FDI0_TX#0

W11

FDI0_TX#1

W1

FDI0_TX#2

AA6

FDI0_TX#3

W6

FDI1_TX#0

V4

FDI1_TX#1

Y2

FDI1_TX#2

AC9

FDI1_TX#3

U6

FDI0_TX0

W10

FDI0_TX1

W3

FDI0_TX2

AA7

FDI0_TX3

W7

FDI1_TX0

T4

FDI1_TX1

AA3

FDI1_TX2

AC8

FDI1_TX3

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

EDP_COMPIO

AD2

EDP_ICOMPO

AG11

EDP_HPD#

AG4

EDP_AUX#

AF4

EDP_AUX

AC3

EDP_TX#0

AC4

EDP_TX#1

AE11

EDP_TX#2

AE7

EDP_TX#3

AC1

EDP_TX0

AA4

EDP_TX1

AE10

EDP_TX2

AE6

EDP_TX3

IVY-BRIDGE-GP-NF

71.00IVY.A0U

DMI

Intel(R) FDI

eDP

1 OF 9

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8

PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PCI EXPRESS -- GRAPHICS

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

PEG_IRCOMP_R

G3 G1 G4

H22 J21 B22 D21 A19 D17 B14 D13

PEG_RXN7

A11

PEG_RXN6

B10

PEG_RXN5

G8

PEG_RXN4

A8

PEG_RXN3

B6

PEG_RXN2

H8

PEG_RXN1

E5

PEG_RXN0

K7 K22

K19 C21 D19 C19 D16 C13 D12

PEG_RXP7

C11

PEG_RXP6

C9

PEG_RXP5

F8

PEG_RXP4

C8

PEG_RXP3

C5

PEG_RXP2

H6

PEG_RXP1

F6

PEG_RXP0

K6 G22

C23 D23 F21 H19 C17 K15 F17

PEG_C_TXN7

F14

PEG_C_TXN6

A15

PEG_C_TXN5

J14

PEG_C_TXN4

H13

PEG_C_TXN3

M10

PEG_C_TXN2

F10

PEG_C_TXN1

D9

PEG_C_TXN0

J4 F22

A23 D24 E21 G19 B18 K17 G17

PEG_C_TXP7

E14

PEG_C_TXP6

C15

PEG_C_TXP5

K13

PEG_C_TXP4

G13

PEG_C_TXP3

K10

PEG_C_TXP2

G10

PEG_C_TXP1

D8

PEG_C_TXP0

K4

Layout Note:

PEG trace length 1500~9000mil

R401 24D9R2F-L-GPR401 24D9R2F-L-GP

PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

VCCP_CPU

1 2

PEG_RXN[7..0] [83]

PEG_RXP[7..0] [83]

C401 SCD1U10V2KX-5GP

1 2

SG

C402 SCD1U10V2KX-5GP

1 2

SG

C403 SCD1U10V2KX-5GP

1 2

SG

C404 SCD1U10V2KX-5GP

1 2

SG

C405 SCD1U10V2KX-5GP

1 2

SG

C406 SCD1U10V2KX-5GP

1 2

SG

C407 SCD1U10V2KX-5GP

1 2

SG

C408 SCD1U10V2KX-5GP

1 2

SG

C417 SCD1U10V2KX-5GP

1 2

SG

C418 SCD1U10V2KX-5GP

1 2

SG

C419 SCD1U10V2KX-5GP

1 2

SG

C420 SCD1U10V2KX-5GP

1 2

SG

C421 SCD1U10V2KX-5GP

1 2

SG

C422 SCD1U10V2KX-5GP

1 2

SG

C423 SCD1U10V2KX-5GP

1 2

SG

C424 SCD1U10V2KX-5GP

1 2

SG

PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0

PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0

PEG_TXN[7..0] [83]

PEG_TXP[7..0] [83]

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

BMW Z4 DIS

Taipei Hsien 221, Taiwan, R.O.C.

CPU(PCIE/DMI/FDI)

4 105Friday, March 30, 2012

A00

5

4

3

2

1

SSID = CPU

2 OF 9

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

MISC

2 OF 9

BCLK

BCLK#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

PRDY# PREQ#

TCK TMS

TRST#

TDO

DBR#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

CLK_EXP_P

J3

CLK_EXP_N

H2

CLK_DP_P_R

AG3

CLK_DP_N_R

AG1

SM_DRAMRST#

AT30

SM_RCOMP_0

BF44

SM_RCOMP_1

BE43

SM_RCOMP_2

BG43

XDP_PRDY#

N53

XDP_PREQ#

N55

XDP_TCLK

L56

XDP_TMS

L55

XDP_TRST#

J58

XDP_TDI

M60

TDI

L59

K58

G58 E55 E59 G55 G59 H60 J59 J61

XDP_TDO

XDP_DBRESET#

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

RN503

1 2 3

4

SRN1KJ-7-GP

R507

4K99R2F-L-GP

1 2

R506 140R2F-GPR506 140R2F-GP

1 2

R508 25D5R2F-GPR508 25D5R2F-GP

1 2

R511 200R2F-L-GPR511 200R2F-L-GP

1 2

XDP_PRDY# [71]

XDP_PREQ# [71]

XDP_DBRESET# [19]

XDP_BPM0 [71] XDP_BPM1 [71] XDP_BPM2 [71] XDP_BPM3 [71] XDP_BPM4 [71] XDP_BPM5 [71] XDP_BPM6 [71] XDP_BPM7 [71]

CLK_EXP_P [20] CLK_EXP_N [20]

VCCP_CPU

SM_DRAMRST# [37]

Layout Note:

Checking the connector pin's LAYOUT

Layout Note:

Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils. Trace width = 15mil

RN501

XDP_TDI XDP_TMS XDP_TDO

XDP_TRST# XDP_TCLK

RN501

1 2 3

XDP

4 5

SRN51J-1-GP

RN502

1 2 3

XDP

SRN51J-GP

8 7 6

4

VCCP_CPU

CPU1B

D D

R513

R504

R503

R509

H_SNB_IVB#

SKTOCC#_R

H_CATERR#

H_PECI

H_PROCHOT#_R

H_THERMTRIP#

H_PM_SYNC

H_CPUPW RGD_R

VDDPWRGOOD

BUF_CPU_RST#

12

DY

C501

C501 SC220P50V2KX-3GP

SC220P50V2KX-3GP

H_SNB_IVB#[22]

TP501TPAD14-OP-GP TP501TPAD14-OP-GP

VCCP_CPU

R501

1 2

62R2J-GP

C C

H_PROCHOT#

Layout Note:

R501, R513 place near to CPU

TP502TPAD14-OP-GP TP502TPAD14-OP-GP

H_PECI[22,27]

H_PROCHOT#[27,40]

H_THERMTRIP#[22]

H_PM_SYNC[19]

H_CPUPW RGD[22]

VDDPWRGOOD[37]

PLT_RST#[18,27,31,65,66,71]

1

1 2

56R2J-4-GP

X03 2/6

0R0402-PAD-2-GP

1 2 1 2

10KR2J-3-GP

1 2

R510

1K5R2F-2-GP

698R2F-GP

CPU1B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

MISC

CLOCKS

THERMAL

DDR3

PWR MANAGEMENT

JTAG & BPM

IVY-BRIDGE-GP-NF

71.00IVY.A0U

B B

Layout Note:

C501 place near to CPU

A A

71.00IVY.A0U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

CPU(THERMAL/CLOCK/PM)

BMW Z4 DIS

Taipei Hsien 221, Taiwan, R.O.C.

5 105Friday, March 30, 2012

A00

5

4

3

2

1

SSID = CPU

4 OF 9

CPU1D

AL4

AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9

BD13

BF12

BF8

BD10 BD14 BE13

BF16 BE17 BE18 BE21 BE14 BG14 BG18

BF19 BD50

BF48 BD53

BF52 BD49 BE49 BD54 BE53

BF56 BE57 BC59 AY60 BE54 BG54 BA58

AW59 AW58

AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58

AL58 AG58 AG59 AM60

AL59

AF61 AH60

BG39 BD42

AT22

AV43

BF40 BD45

CPU1D

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

3 OF 9

CPU1C

D D

C C

B B

M_A_DQ[63:0][14]

M_A_DQ[63:0]

M_A_BS0[14] M_A_BS1[14] M_A_BS2[14]

M_A_CAS#[14] M_A_RAS#[14] M_A_WE#[14]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AG6

AP11

AL6

AJ10

AL8 AL7

AR11

AP6 AU6 AV9 AR6

AP8 AT13 AU13

BC7

BB7 BA13 BB11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53

AG56 AG53

AN55 AN52

AG55

AK56

BD37 BF36 BA28

BE39 BD39 AT41

CPU1C

SA_DQ0

AJ6

SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4

AJ8

SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

3 OF 9

SA_CK0

SA_CK#0

SA_CKE0

SA_CK1

SA_CK#1

SA_CKE1

SA_CS#0 SA_CS#1

SA_ODT0 SA_ODT1

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AU36 AV36 AY26

AT40 AU40 BB26

BB40 BC41

AY40 BA41

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DIMA_CLK_DDR0 [14] M_A_DIMA_CLK_DDR#0 [14] M_A_DIMA_CKE0 [14]

M_A_DIMA_CLK_DDR1 [14] M_A_DIMA_CLK_DDR#1 [14] M_A_DIMA_CKE1 [14]

M_A_DIMA_CS#0 [14] M_A_DIMA_CS#1 [14]

M_A_DIMA_ODT0 [14] M_A_DIMA_ODT1 [14]

M_A_DQS#[7:0] [14]

M_A_DQS[7:0] [14]

M_A_A[15:0] [14]

M_B_DQ[63:0][15]

M_B_DQ[63:0]

M_B_BS0[15] M_B_BS1[15] M_B_BS2[15]

M_B_CAS#[15] M_B_RAS#[15] M_B_WE#[15]

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

4 OF 9

SB_CK0 SB_CK#0 SB_CKE0

SB_CK1 SB_CK#1 SB_CKE1

SB_CS#0 SB_CS#1

SB_ODT0 SB_ODT1

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0

SB_MA1

SB_MA2

SB_MA3

SB_MA4

SB_MA5

SB_MA6

SB_MA7

SB_MA8

SB_MA9

SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

BA34 AY34 AR22

BA36 BB36 BF27

BE41 BE47

AT43 BG47

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DIMB_CLK_DDR0 [15] M_B_DIMB_CLK_DDR#0 [15] M_B_DIMB_CKE0 [15]

M_B_DIMB_CLK_DDR1 [15] M_B_DIMB_CLK_DDR#1 [15] M_B_DIMB_CKE1 [15]

M_B_DIMB_CS#0 [15] M_B_DIMB_CS#1 [15]

M_B_DIMB_ODT0 [15] M_B_DIMB_ODT1 [15]

M_B_DQS#[7:0] [15]

M_B_DQS[7:0] [15]

M_B_A[15:0] [15]

IVY-BRIDGE-GP-NF

71.00IVY.A0U

A A

5

4

3

IVY-BRIDGE-GP-NF

71.00IVY.A0U

2

DMB40

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, March 30, 2012

Date: Sheet of

CPU (DDR)

BMW Z4 DIS

Taipei Hsien 221, Taiwan, R.O.C.

6 105

1

A00

5

SSID = CPU

4

3

2

1

CFG6

CFG2

CFG5

DY

12

R701

R701 1KR2J-1-GP

1KR2J-1-GP

SG

12

R702

R702 1KR2J-1-GP

1KR2J-1-GP

R704

R704 1KR2J-1-GP

1KR2J-1-GP

PEG Static Lane Reversal

CFG[2]

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

Display Port Presence Strap

CFG[4]

1: Disabled; No Physical Display Port attached to Embedded Display Port

0: Enabled; An external Display Port device is connected to the Embedded Display Port

PCIE Port Bifurcation Straps

CFG[6:5]

11:

1x16 PCI Express

2 x8 - PCI Express

10:

Reserved

01:

1x8, 2x4 PCI Express

00:

5 OF 9

CPU1E

D D

CFG0[71]

TP701TPAD14-OP-GP TP701TPAD14-OP-GP TP702TPAD14-OP-GP TP702TPAD14-OP-GP

TP703TPAD14-OP-GP TP703TPAD14-OP-GP

TP704TPAD14-OP-GP TP704TPAD14-OP-GP TP705TPAD14-OP-GP TP705TPAD14-OP-GP TP706TPAD14-OP-GP TP706TPAD14-OP-GP TP707TPAD14-OP-GP TP707TPAD14-OP-GP TP708TPAD14-OP-GP TP708TPAD14-OP-GP TP709TPAD14-OP-GP TP709TPAD14-OP-GP TP710TPAD14-OP-GP TP710TPAD14-OP-GP TP711TPAD14-OP-GP TP711TPAD14-OP-GP TP712TPAD14-OP-GP TP712TPAD14-OP-GP TP713TPAD14-OP-GP TP713TPAD14-OP-GP TP714TPAD14-OP-GP TP714TPAD14-OP-GP

TP715TPAD14-OP-GP TP715TPAD14-OP-GP TP716TPAD14-OP-GP TP716TPAD14-OP-GP

C C

B B

TP717TPAD14-OP-GP TP717TPAD14-OP-GP TP718TPAD14-OP-GP TP718TPAD14-OP-GP

TP719TPAD14-OP-GP TP719TPAD14-OP-GP TP720TPAD14-OP-GP TP720TPAD14-OP-GP

CFG0 CFG1

1

CFG2 CFG3

1

CFG4

1

CFG5 CFG6 CFG7

1

CFG8

1

CFG9

1

CFG10

1

CFG11

1

CFG12

1

CFG13

1

CFG14

1

CFG15

1

CFG16

1

CFG17

1

VCC_VAL_SENSE

1

VSS_VAL_SENSE

1

VAXG_VAL_SENSE

1

VSSAXG_VAL_SENSE

1

VCC_DIE_SENSE

1

VSS_DIE_SENSE

1

CPU1E

B50

CFG0

C51

CFG1

B54

CFG2

D53

CFG3

A51

CFG4

C53

CFG5

C55

CFG6

H49

CFG7

A55

CFG8

H51

CFG9

K49

CFG10

K53

CFG11

F53

CFG12

G53

CFG13

L51

CFG14

F51

CFG15

D52

CFG16

L53

CFG17

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

G48

RSVD47

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

RESERVED

5 OF 9

BCLK_ITP

BCLK_ITP#

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RSVD45

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59

DC_TEST_C59

DC_TEST_A61

DC_TEST_C61

DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4

DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1

DC_TEST_BD1

BCLK_ITP

N59

BCLK_ITP#

N58

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

TP_DC_TEST_A4

A4 C4

DC_TEST_C4_D3

D3

TP_DC_TEST_D1

D1

TP_DC_TEST_A58

A58 A59

TP_DC_TEST_A59_C59

C59 A61

TP_DC_TEST_A61_C61

C61

TP_DC_TEST_D61

D61

TP_DC_TEST_BD61

BD61 BE61

TP_DC_TEST_BE59_BE61

BE59 BG61

DC_TEST_BG59_BG61

BG59

TP_DC_TEST_BG58

BG58

TP_DC_TEST_BG4

BG4 BG3

DC_TEST_BE3_BG3

BE3 BG1

DC_TEST_BE1_BG1

BE1

TP_DC_TEST_BD1

BD1

TP721 TPAD14-OP-GPTP721 TPAD14-OP-GP

1

TP722 TPAD14-OP-GPTP722 TPAD14-OP-GP

1

1 1

1

TP723 TPAD14-OP-GPTP723 TPAD14-OP-GP

TP724 TPAD14-OP-GPTP724 TPAD14-OP-GP TP725 TPAD14-OP-GPTP725 TPAD14-OP-GP

TP726 TPAD14-OP-GPTP726 TPAD14-OP-GP TP727 TPAD14-OP-GPTP727 TPAD14-OP-GP

TP728 TPAD14-OP-GPTP728 TPAD14-OP-GP TP729 TPAD14-OP-GPTP729 TPAD14-OP-GP

TP730 TPAD14-OP-GPTP730 TPAD14-OP-GP

IVY-BRIDGE-GP-NF

71.00IVY.A0U

DMB40

A A

5

4

3

2

DMB40

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, March 30, 2012

Date: Sheet of

CPU (RESERVED)

BMW Z4 DIS

Taipei Hsien 221, Taiwan, R.O.C.

7 105

1

A00

5

4

3

2

1

SSID = CPU

POWER

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76

POWER

CORE SUPPLY

CPU1F

A00 3/30 X01 12/21 X01 12/16 X01 12/15 X01 12/09

VCC_CORE

D D

12

C801

C821

SC22U6D3V5MX-2GP

12

C811

SC22U6D3V5MX-2GP

12

C825

C830

SC22U6D3V5MX-2GP

C C

B B

12

DY

C802

SC10U6D3V5KX-1GP

12

C822

SC22U6D3V5MX-2GP

12

C812

C813

SC22U6D3V5MX-2GP

12

C831

C832

SC22U6D3V5MX-2GP

12

C814

C803

DY

SC10U6D3V5KX-1GP

12

C804

C805

C806

SC22U6D3V5MX-2GP

12

C823

C824

DY

SC22U6D3V5MX-2GP

12

C847

C843

DY

SC10U6D3V3MX-GP

SC22U6D3V5MX-2GP

12

C815

C827

C817

DY

SC10U6D3V5KX-1GP

12

C807

C808

DY

SC22U6D3V5MX-2GP

12

C828

C816

SC22U6D3V5MX-2GP

12

C840

C829

DY

SC2D2U6D3V2MX-GP

SC10U6D3V3MX-GP

12

C809

C810

SC22U6D3V5MX-2GP

12

C818

SC22U6D3V5MX-2GP

C820

SC22U6D3V5MX-2GP

VCC_CORE

33A

A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

IVY-BRIDGE-GP-N F

71.00IVY.A0U

6 OF 9

VCCIO1 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29

VCCIO30 VCCIO31 VCCIO32

PEG IO AND DDR IO

VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 VCCIO40 VCCIO41 VCCIO42 VCCIO43 VCCIO44 VCCIO45 VCCIO46 VCCIO47 VCCIO48 VCCIO49

VCCIO50 VCCIO51

VCCIO_SEL

VCCPQE1 VCCPQE2

RAILS

VIDALERT#

VIDSCLK VIDSOUT

SVID QUIET

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES

AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

H_CPU_SVIDALR T# H_CPU_SVIDC LK H_CPU_SVIDD AT

VCCSENSE VSSSENSE

12

H_SNB_IVB#_PW RCTRL

+V1.05S_VCCPQE _R

12

C862

SC1U6D3V2KX-GP

C862

SC1U6D3V2KX-GP

12

DY

12

DY

C871

SC22U6D3V5MX-2GP

Added, cause the

1.05V far away CPU

C885

SC1U6D3V2KX-GP

C885

SC1U6D3V2KX-GP12C883

SC1U6D3V2KX-GPDYC883

SC1U6D3V2KX-GP

12

DY

1

X03 2/6

R812

R812 0R0402-PAD-2- GP

0R0402-PAD-2- GP

1 2

C826

C826 SC1U6D3V2KX- GP

SC1U6D3V2KX- GP

VCCP_CPU

12

R807

R807 10R2F-L-GP

10R2F-L-GP

12

R806

R806 10R2F-L-GP

10R2F-L-GP

C869

SC1U6D3V2KX-GPDYC869

C864

SC1U6D3V2KX-GPDYC864

SC1U6D3V2KX-GP

C865

SC1U6D3V2KX-GPDYC865

SC1U6D3V2KX-GP

12

DY

12

C873

C872

SC22U6D3V5MX-2GP

C884

SC1U6D3V2KX-GPDYC884

SC1U6D3V2KX-GP

C886

SC1U6D3V2KX-GP

C886

SC1U6D3V2KX-GP

12

TP801 TP AD14-OP-GPTP801 TP AD14-OP-GP

R803

R803 43R2J-GP

43R2J-GP

1 2

VCCIO_SENSE [45] VSSIO_SENSE [4 5]

Layout Note:

1. PH/PL resisors place close CPU

2. SENSE signal recommend differential routing

12

DY

12

DY

12

DY

75R2F-2-GP

SC1U6D3V2KX-GP

C867

SC1U6D3V2KX-GPDYC867

12

DY

12

DY

12

DY

C876

SC1U6D3V2KX-GPDYC876

SC1U6D3V2KX-GP

C879

SC10U6D3V3MX-GP

C879

SC10U6D3V3MX-GP

C887

SC1U6D3V2KX-GP

C887

SC1U6D3V2KX-GP

C897

SC10U6D3V3MX-GPDYC897

SC10U6D3V3MX-GP

VCCP_CPUVCCP_CPU

12

VCC_CORE

12

SC1U6D3V2KX-GP

12

DY

C875

SC1U6D3V2KX-GPDYC875

SC1U6D3V2KX-GP

12

DY

C880

SC10U6D3V3MX-GP

C880

SC10U6D3V3MX-GP

12

C889

SC1U6D3V2KX-GP

C889

SC1U6D3V2KX-GP

12

C893

SC10U6D3V3MX-GP

C893

SC10U6D3V3MX-GP

12

R804

R804 130R2F-1-GP

130R2F-1-GP

R801

R801 100R2F-L1-GP- U

100R2F-L1-GP- U

R802

R802 100R2F-L1-GP- U

100R2F-L1-GP- U

DY

C866

SC1U6D3V2KX-GPDYC866

SC1U6D3V2KX-GP

C874

SC1U6D3V2KX-GPDYC874

SC1U6D3V2KX-GP

C863

SC10U6D3V3MX-GP

C863

SC10U6D3V3MX-GP

C888

SC1U6D3V2KX-GP

C888

SC1U6D3V2KX-GP

C895

SC10U6D3V3MX-GPDYC895

SC10U6D3V3MX-GP

R805

8.5A

C868

SC1U6D3V2KX-GPDYC868

SC1U6D3V2KX-GP

12

DY

C877

SC1U6D3V2KX-GPDYC877

SC1U6D3V2KX-GP

12

C881

SC10U6D3V3MX-GPDYC881

SC10U6D3V3MX-GP

12

DY

C890

SC1U6D3V2KX-GP

C890

SC1U6D3V2KX-GP

12

DY

C894

SC10U6D3V3MX-GPDYC894

SC10U6D3V3MX-GP

12

DY

VCCP_CPU

C870

SC1U6D3V2KX-GPDYC870

SC1U6D3V2KX-GP

12

C878

SC1U6D3V2KX-GP

C878

SC1U6D3V2KX-GP

12

C882

SC10U6D3V3MX-GPDYC882

SC10U6D3V3MX-GP

12

VCCP_CPU

C892

SC1U6D3V2KX-GPDYC892

SC1U6D3V2KX-GP

C891

SC1U6D3V2KX-GPDYC891

SC1U6D3V2KX-GP

12

DY

C896

SC10U6D3V3MX-GPDYC896

SC10U6D3V3MX-GP

12

Layout Note:

R803, R804, R805 need close to CPU Alert# signal must be routed between the Clock and Data lines to reduce the cross talk between them

VR_SVID_ALERT# [42]

H_CPU_SVIDC LK [42]

H_CPU_SVIDD AT [42]

Layout Note:

1. PH/PL resisors place close CPU

2. SENSE signal recommend differential routing

VCCSENSE [42] VSSSENSE [42]

Voltage Rail

VCC_CORE(ULV) VAXG(ULV) VCCIO VDDQ 1.5 VCCSA VCCPLL

Need place Pull Hi at IMVP page

Voltage(V)

0.3~1.52 0~1.52

1.05

0.9

1.8

Iccmax(A)

33 33

8.5 5 4

1.2

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Friday, March 30, 2 012

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

CPU (VCC_CORE)

BMW Z4 DIS

1

8 105

A00

5

4

3

2

1

SSID = CPU

Layout Note:

X01 12/09 X01 12/15

VCC_GFXCO RE

D D

C C

B B

12

C901

12

C955

12

C906

12

DY

Layout Note:

1. PH/PL resisors place close CPU

2. SENSE signal recommend differential routing

12

C902

C903

SC22U6D3V5MX-2GP

12

C920

C923

SC22U6D3V5MX-2GP

12

C908

C907

SC22U6D3V5MX-2GP

12

C914

C912

C913

DY

SC1U6D3V2KX-GP

0D85V_S0

12

C905

C904

SC22U6D3V5MX-2GP

12

C921

C922

SC22U6D3V5MX-2GP

12

C909

C910

SC22U6D3V5MX-2GP

12

C915

C916

DY

SC1U6D3V2KX-GP

VCC_AXG_SEN SE[42]

VSS_AXG_SENSE[42]

6A

C929

SC10U6D3V3MX-GPDYC929

SC10U6D3V3MX-GP

C930

SC10U6D3V3MX-GPDYC930

SC10U6D3V3MX-GP

12

DY

C935

SC1U6D3V2KX-GP

C935

SC1U6D3V2KX-GP

12

SC22U6D3V5MX-2GP

C917

DY

SC1U6D3V2KX-GP

1D8V_S0

12

33A

12

C911

C919

SC22U6D3V5MX-2GP

12

C918

SC1U6D3V2KX-GP

VCC_GFXCO RE

12

R903

R903 100R2F-L1-GP- U

100R2F-L1-GP- U

VCC_AXG_SEN SE VSS_AXG_SENSE

12

R904

R904 100R2F-L1-GP- U

100R2F-L1-GP- U

1.2A

C925

SC1U6D3V2KX-GP

C925

SC1U6D3V2KX-GP

C924

SC1U6D3V2KX-GPDYC924

SC1U6D3V2KX-GP

12

DY

C926

SC10U6D3V3MX-GPDYC926

SC10U6D3V3MX-GP

C927

SC10U6D3V3MX-GPDYC927

SC10U6D3V3MX-GP

C928

SC10U6D3V3MX-GPDYC928

SC10U6D3V3MX-GP

12

DY

C933

C934

SC1U6D3V2KX-GP

C934

SC1U6D3V2KX-GP

12

DY

12

DY

SC1U6D3V2KX-GPDYC933

SC1U6D3V2KX-GP

C932

SC1U6D3V2KX-GPDYC932

SC1U6D3V2KX-GP

12

DY

CPU1G

AA46

VAXG1

AB47

VAXG2

AB50

VAXG3

AB51

VAXG4

AB52

VAXG5

AB53

VAXG6

AB55

VAXG7

AB56

VAXG8

AB58

VAXG9

AB59

VAXG10

AC61

VAXG11

AD47

VAXG12

AD48

VAXG13

AD50

VAXG14

AD51

VAXG15

AD52

VAXG16

AD53

VAXG17

AD55

VAXG18

AD56

VAXG19

AD58

VAXG20

AD59

VAXG21

AE46

VAXG22

N45

VAXG23

P47

VAXG24

P48

VAXG25

P50

VAXG26

P51

VAXG27

P52

VAXG28

P53

VAXG29

P55

VAXG30

P56

VAXG31

P61

VAXG32

T48

VAXG33

T58

VAXG34

T59

VAXG35

T61

VAXG36

U46

VAXG37

V47

VAXG38

V48

VAXG39

V50

VAXG40

V51

VAXG41

V52

VAXG42

V53

VAXG43

V55

VAXG44

V56

VAXG45

V58

VAXG46

V59

VAXG47

W50

VAXG48

W51

VAXG49

W52

VAXG50

W53

VAXG51

W55

VAXG52

W56

VAXG53

W61

VAXG54

Y48

VAXG55

Y61

VAXG56

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL1

BC1

VCCPLL2

BC4

VCCPLL3

L17

VCCSA1

L21

VCCSA2

N16

VCCSA3

N20

VCCSA4

N22

VCCSA5

P17

VCCSA6

P20

VCCSA7

R16

VCCSA8

R18

VCCSA9

R21

VCCSA10

U15

VCCSA11

V16

VCCSA12

V17

VCCSA13

V18

VCCSA14

V21

VCCSA15

W20

VCCSA16

C931

SC1U6D3V2KX-GPDYC931

SC1U6D3V2KX-GP

IVY-BRIDGE-GP-N F

71.00IVY.A0U

POWER

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

VCCSA VID

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VREF

DDR3 - 1.5V RAILS

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

SENSE LINES

VCCSA_VID0 VCCSA_VID1

lines

SM_VREF

+V_SM_VREF_CNT should have 10 mil trace width

7 OF 9

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26

VCCDQ1 VCCDQ2

AY43

DDR_W R_VREFA

BE7

DDR_W R_VREFB

BG7

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

BC43 BA43

U10

D48 D49

+V_SM_VREF_C NT

C944

12

DY

TP_VDDQ_SEN SE TP_VDDQ_VSS

VCCSA_SEL0 VCCSA_SEL1

RN902

4

SRN1KJ-7-G P

SC1U6D3V2KX-GPDYC944

SC1U6D3V2KX-GP

C945

12

C954

SC1U6D3V2KX-GP

C954

SC1U6D3V2KX-GP

12

1 1

23

23 1

DY

5A

C946

SC1U6D3V2KX-GPDYC946

SC1U6D3V2KX-GP

12

DY

C936

SC10U6D3V3MX-GPDYC936

SC10U6D3V3MX-GP

12

DY

X03 2/6

R909

R909 0R0402-PAD-2- GP

0R0402-PAD-2- GP

1 2

TP901 TP AD14-OP-GPTP901 TP AD14-OP-GP TP902 TP AD14-OP-GPTP902 TP AD14-OP-GP

VCCSA_SENS E [48]

VCCSA_SEL0 [48 ] VCCSA_SEL1 [48 ]

1

RN901

RN901 SRN1KJ-7-G P

SRN1KJ-7-G P

4

C947

SC1U6D3V2KX-GPDYC947

SC1U6D3V2KX-GP

C948

SC1U6D3V2KX-GPDYC948

SC1U6D3V2KX-GP

12

DY

C937

12

DY

C938

SC10U6D3V3MX-GPDYC938

SC10U6D3V3MX-GP

12

DY

1D5V_S0+V1.5S_VCCD_Q

C949

SC1U6D3V2KX-GPDYC949

SC1U6D3V2KX-GP

12

DY

C939

SC10U6D3V3MX-GPDYC939

SC10U6D3V3MX-GP

12

Voltage Rail

VCC_CORE(ULV) VAXG(ULV) VCCIO VDDQ 1.5 VCCSA VCCPLL

C950

SC1U6D3V2KX-GPDYC950

SC1U6D3V2KX-GP

C951

SC1U6D3V2KX-GPDYC951

SC1U6D3V2KX-GP

12

DY

C940

SC10U6D3V3MX-GP

C940

SC10U6D3V3MX-GP

C941

SC10U6D3V3MX-GP

C941

SC10U6D3V3MX-GP

12

DY

VCCSA Power Select

Voltage(V)

0.9

0.85

0.775

0.75

Voltage(V)

0.3~1.52 0~1.52

C952

SC1U6D3V2KX-GPDYC952

SC1U6D3V2KX-GP

12

C942

SC10U6D3V3MX-GPDYC942

SC10U6D3V3MX-GP

12

DY

VID[0] VID[1]

1.05

0.9

1.8

C953

SC1U6D3V2KX-GP

C953

SC1U6D3V2KX-GP

C943

SC10U6D3V3MX-GPDYC943

SC10U6D3V3MX-GP

0

0 1

Iccmax(A)

1D5V_S0

33 33

8.5 5 6

1.2

0

01

11

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Friday, March 30, 2 012

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

CPU (VCC_GFXCORE)

BMW Z4 DIS

1

9 105

A00

5

SSID = CPU

CPU1H

4

8 OF 9

3

CPU1I

2

9 OF 9

1

A13

VSS1

A17

VSS2

A21

VSS3

A25

VSS4

D D

C C

B B

A A

A28 A33 A37 A40 A45 A49 A53

AA1 AA13 AA50 AA51 AA52 AA53 AA55 AA56

AA8 AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46

AC6 AD17 AD20

AD4 AD61 AE13

AE8

AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59 AG10 AG14 AG18 AG47 AG52 AG61

AG7 AH4

AH58

AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48

AJ7

AK1

AK52

AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47

AL61 AM13 AM20 AM22 AM26 AM30 AM34

VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11

A9

VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90

VSS

VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53

BG9

C29 C35 C40 D10 D14 D18 D22 D26 D29 D35

D4 D40 D43 D46 D50 D54 D58

D6 E25 E29

E3 E35 E40 F13 F15 F19 F29 F35 F40 F55

G51

G6

G61

H10 H14 H17 H21

H4 H53 H58

J1 J49 J55 K11 K21 K51

K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61

M11 M15

IVY-BRIDGE-GP-NF

71.00IVY.A0U

VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249

VSS

NCTF TEST PIN：A5,A57,BC61,BG5

NCTF

VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300

VSS_NCTF_1#A5

VSS_NCTF_2#A57

VSS_NCTF_3#BC61

VSS_NCTF_8#BG5

VSS_NCTF_9#BG57

VSS_NCTF_10#C3

VSS_NCTF_13#E1

VSS_NCTF_14#E61

BG57,C3,E1,E61

VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6

VSS_NCTF_7 VSS_NCTF_11 VSS_NCTF_12

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59

A5 A57 BC61 BG5 BG57 C3 E1 E61

BD3 BD59 BE4 BE58 C58 D59

DMB40

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

IVY-BRIDGE-GP-NF

71.00IVY.A0U

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, March 30, 2012

Date: Sheet of

CPU (VSS)

BMW Z4 DIS

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

10 105

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DMB40

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, March 30, 2012

Date: Sheet of

XDP

BMW Z4 DIS

Taipei Hsien 221, Taiwan, R.O.C.

11 105

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DMB40

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document Number Rev

A3

Date: Sheet of

Reserved

BMW Z4 DIS

Taipei Hsien 221, Taiwan, R.O.C.

12 105Friday, March 30, 2012

1

A00

5

D D

4

3

2

1

C C

B B

A A

(Blanking)

DMB40

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)

Size Document Number Rev

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

(Reserved)

BMW Z4 DIS

Taipei Hsien 221, Taiwan, R.O.C.

13 105Friday, March 30, 2012

1

A00

5

SSID = MEMORY

M_A_A[15:0][6]

D D

DDR_VREF _S3

X03 2/6

12

R1405

R1405 0R0402-PAD-2- GP

0R0402-PAD-2- GP

12

C1427

SCD1U10V2KX-5GP

X03 2/16

DDR_VREF _S3

C C

0D75V_S0

B B

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

12

R1404

R1404 0R0402-PAD-2- GP

0R0402-PAD-2- GP

12

C1411

12

C1419

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

DY

X03 2/6

12

DY

12

M_VREF_CA_D IMMA

12

EC1428

SCD1U10V2KX-5GP

M_VREF_DQ_D IMMA

12

C1423

SC2D2U10V3KX-1GP

12

C1420

C1418

SC1U6D3V2KX-GP

Layout Note:

Place these caps close to VREF_CA

C1426

Layout Note:

Place these caps close to VREF_DQ

C1429

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

Layout Note:

Place these caps close to VTT1 and VTT2.

M_A_DQS#[7:0][6]

M_A_DIMA_ODT0[6] M_A_DIMA_ODT1[6]

DDR3_DR AMRST#[15,37]

M_A_BS2[6] M_A_BS0[6]

M_A_BS1[6]

M_A_DQ[63:0][6]

M_A_DQS[7:0][6]

M_VREF_CA_D IMMA M_VREF_DQ_D IMMA

0D75V_S0

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

X01 12/15 X01 12/02

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P- 73-GP

62.10017.U81

2nd = 62.10017.P31

3rd = 62.10017.K11

4th = 62.10017.N91

RAS# CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

4

NP1

NP2

110 113

WE#

115 114

121 73

74 101

CK0

103 102

CK1

104 11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198 199

SA0_DIMA

197

SA0

SA1_DIMA

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D5V_S3

M_A_RAS# [6] M_A_WE# [6] M_A_CAS# [6]

M_A_DIMA_CS#0 [6] M_A_DIMA_CS#1 [6]

M_A_DIMA_CKE0 [6] M_A_DIMA_CKE1 [6]

M_A_DIMA_CLK_DD R0 [6] M_A_DIMA_CLK_DD R#0 [6]

M_A_DIMA_CLK_DD R1 [6] M_A_DIMA_CLK_DD R#1 [6]

PCH_SMBDAT A [15,20,65,66,69] PCH_SMBCLK [15,20,65,66,69]

C1401

SCD1U10V2KX- 5GP

3D3V_S0

12

DY

Layout Note:

Place these Caps near SO-DIMMA.

3

SA0_DIMA SA1_DIMA

0R0402-PAD-2- GP

1D5V_S3

12

TC1401

DY

C1403

ST330U2VDM-4-GP

SC10U6D3V5KX-1GP

12

C1414

C1415

SCD1U10V2KX-5GP

1D5V_S31D5V_S0

1 2

DY

C1421

SCD1U10V2KX- 5GP

1 2

DY

C1424

SCD1U10V2KX- 5GP

Layout Note:

For S3 reduction circuit's 1D5V return pass.

R1401

12

X03 2/21

C1404

SC10U6D3V5KX-1GP

C1416

SC1U6D3V2KX-GP

12

C1405

SC10U6D3V5KX-1GP

12

C1417

SC1U6D3V2KX-GP

X01 12/20

R1402

0R0402-PAD-2- GP

12

EC1406

SCD1U10V2KX-5GP

Note: SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

12

EC1408

EC1407

SCD1U10V2KX-5GP

2

1

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Friday, March 30, 2 012

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

DDR3-SODIMM1

BMW Z4 DIS

1

14 105

A00

5

SSID = MEMORY

DDR_VREF _S3

D D

DDR_VREF _S3

C C

0D75V_S0

B B

X03 2/6

12

R1505

R1505 0R0402-PAD-2- GP

0R0402-PAD-2- GP

M_VREF_CA_D IMMB

12

C1523

EC1524

SCD1U10V2KX-5GP

X03 2/16

X03 2/6

12

R1503

R1503 0R0402-PAD-2- GP

0R0402-PAD-2- GP

M_VREF_DQ_D IMMB

12

DY

C1516

C1515

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

12

C1518

C1519

DY

C1519

SC1U6D3V2KX-GP

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

12

C1522

12

C1517

12

C1521

SC1U6D3V2KX-GP

Layout Note:

Place these caps close to VREF_CA

SCD1U10V2KX-5GP

M_B_A[15:0][6]

M_B_BS2[6] M_B_BS0[6]

M_B_BS1[6]

M_B_DQ[63:0][6]

Layout Note:

Place these caps close to VREF_DQ

Layout Note:

Place these caps close to VTT1 and VTT2.

M_B_DQS#[7:0][6]

M_B_DQS[7:0][6]

M_B_DIMB_ODT0[6] M_B_DIMB_ODT1[6]

M_VREF_CA_D IMMB M_VREF_DQ_D IMMB

DDR3_DR AMRST#[14,37]

0D75V_S0

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

X01 12/13 X01 12/15

107

119

109 108

129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

135 152 169 186

137 154 171 188

116 120

126

203 204

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9 A10/AP

84

A11

83

A12 A13

80

A14

78

A15

79

A16/BA2 BA0

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3# DQS4# DQS5# DQS6# DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3 DQS4 DQS5 DQS6 DQS7

ODT0 ODT1

VREF_CA

1

VREF_DQ

30

RESET#

VTT1 VTT2

DDR3-204P- 75-GP

62.10017.Z81

2nd = 62.10017.N41

3rd = 62.10017.P61

4th = 62.10017.P41

4

EVENT#

VDDSPD

NC#/TEST

RAS# CAS# CS0#

CS1# CKE0

CKE1

CK0#

CK1#

NC#1 NC#2

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

3

NP1

NP2

110 113

WE#

115 114

121 73

74 101

CK0

103 102

CK1

104 11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198 199

SA0_DIMB

197

SA0

SA1_DIMB

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D5V_S3

M_B_RAS# [6] M_B_WE# [6] M_B_CAS# [6]

M_B_DIMB_CS#0 [6] M_B_DIMB_CS#1 [6]

M_B_DIMB_CKE0 [6] M_B_DIMB_CKE1 [6]

M_B_DIMB_CLK_DD R0 [6] M_B_DIMB_CLK_DD R#0 [6]

M_B_DIMB_CLK_DD R1 [6] M_B_DIMB_CLK_DD R#1 [6]

PCH_SMBDAT A [14,20,65,66,69] PCH_SMBCLK [14,20,65,66,69]

12

DY

C1501

SCD1U10V2KX- 5GP

1D5V_S3

Layout Note:

Place these Caps near SO-DIMMA.

3D3V_S0

12

DY

12

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

3D3V_S0

12

R1501

R1501 10KR2J-3-GP

10KR2J-3-GP

SA1_DIMB SA0_DIMB

X01 12/20

12

R1502

R1502 0R0402-PAD-2- GP

0R0402-PAD-2- GP

X01 01/09

12

C1504

C1503

DY

SC10U10V5ZY-1GP

12

C1511

C1512

SCD1U10V2KX-5GP

12

C1507

DY

SC10U6D3V5KX-1GP

12

C1513

SCD1U10V2KX-5GP

12

C1509

C1510

C1508

EC1514

SCD1U10V2KX-5GP

C1510

SC10U6D3V5KX-1GP

X03 02/16

2

1

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Friday, March 30, 2 012

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

DDR3-SODIMM2

BMW Z4 DIS

1

15 105

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DMB40

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

BMW Z4 DIS

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

16 105Friday, March 30, 2012

A00

5

4

3

2

1

SSID = PCH

D D

3D3V_S0

RN1701

1 2 3

SRN2K2J-1-GP

RN1702

2 3 1

SRN100KJ-6-GP

C C

B B

L_CTRL_DATA

4

L_CTRL_CLK

L_BKLT_EN LVDS_VDD_EN

4

Layout Note:

Place near PCH; trace to trace spacing=20mil

L_BKLT_EN[27] LVDS_VDD_EN[49]

L_BKLT_CTRL[49] LVDS_DDC_CLK_R[49]

LVDS_DDC_DATA_R[49]

12

R1701

R1701 2K37R2F-GP

2K37R2F-GP

Layout Note:

LVDS signal trace length max 4000mil

Layout Note:

Place near PCH; trace to trace spacing=30mil

LVDSA_CLK#[49] LVDSA_CLK[49]

LVDSA_DATA0#[49] LVDSA_DATA1#[49] LVDSA_DATA2#[49]

LVDSA_DATA0[49] LVDSA_DATA1[49] LVDSA_DATA2[49]

TP1701TPAD14-OP-GP TP1701TPAD14-OP-GP

RN1707

SRN2K2J-1-GP

R1702

1KR2J-1-GP

LVDS_DDC_CLK_R LVDS_DDC_DATA_R

L_CTRL_CLK L_CTRL_DATA

LVDS_IBG LVDS_VBG

1

3D3V_S0

4

1

2 3

CRT_DDCCLK CRT_DDCDATA

DAC_IREF_R

12

M45

AF37 AF36

AE48 AE47

AK39 AK40

AN48

AM47

AK47

AJ48

AN47 AM49

AK49

AJ47

AF40 AF39

AH45 AH47

AF49 AF45

AH43 AH49

AF47 AF43

N48

M40

M47 M49

J47

P45 T40

K47 T45

P39

P49 T49

T39

T43 T42

PCH1D

L_BKLTEN L_VDD_EN

L_BKLTCTL L_DDC_CLK

L_DDC_DATA L_CTRL_CLK

L_CTRL_DATA LVD_IBG

LVD_VBG LVD_VREFH

LVD_VREFL

LVDSA_CLK# LVDSA_CLK

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSB_CLK# LVDSB_CLK

LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

DAC_IREF CRT_IRTN

PANTHER-GP-NF

71.PANTH.00U

LVDS

Digital Display Interface

CRT

4 OF 10

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SRN2K2J-1-GP

RN1706

3D3V_S0

4

1

2 3

Layout Note:

Close HDMI port

PCH_HDMI_CLK [51] PCH_HDMI_DATA [51]

HDMI_PCH_DET [51] HDMI_DATA2_R# [51]

HDMI_DATA2_R [51] HDMI_DATA1_R# [51] HDMI_DATA1_R [51] HDMI_DATA0_R# [51] HDMI_DATA0_R [51] HDMI_CLK_R# [51] HDMI_CLK_R [51]

Layout Note:

HDMI trace length to DC CAP. max 10000mil

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, March 30, 2012

Date: Sheet of

PCH (LVDS/CRT/DDI)

BMW Z4 DIS

Taipei Hsien 221, Taiwan, R.O.C.

17 105

1

A00

5

4

3

2

1

SSID = PCH

5 OF 10

PCH1E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

D D

Layout Note:

Trace Length : PCH ~~9000mil~~Cap~~1000mil~~CONN

R1823

1

USB3_RX1_N USB3_RX2_N

USB3_RX1_P USB3_RX2_P

USB3_TX1_N USB3_TX2_N

USB3_TX1_P USB3_TX2_P

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

PCH_GPIO50 PCH_GPIO52 PCH_GPIO54

BBS_BIT1 PCH_GPIO53 PCI_GNT3#

PCH_GPIO02

PCH_GPIO05

PCI_PME# PCI_PLTRST#

CLK_PCI_LPC_R CLK_PCI_FB_R CLK_PCI_KBC_R

PCI_PLTRST#

1 2

PLT_RST#[5,27,31,65,66,71]

USB3_RX1_N[62] USB3_RX2_N[82]

USB3_RX1_P[62] USB3_RX2_P[82]

USB3_TX1_N[62] USB3_TX2_N[82]

USB3_TX1_P[62] USB3_TX2_P[82]

TP1801TPAD14-OP-GP TP1801TPAD14-OP-GP

SATA_ODD_DA#[56]

BLUETOOTH_EN[65]

TP1802TPAD14-OP-GP TP1802TPAD14-OP-GP

ER1807 0R2J-2-GP

1 2

DY

R1805 22R2J-2-GPR1805 22R2J-2-GP

1 2

R1806 22R2J-2-GPR1806 22R2J-2-GP

1 2

EC1804

1 2

DY

SC4D7P50V2CN-1GP

12

R1816

100KR2J-1-GP

DY

X02 2/13

1 2

12

0R0402-PAD-2-GP

DY

C1801

C1801 SC220P50V2KX-3GP

SC220P50V2KX-3GP

C C

3D3V_S0

RN1803

SRN10KJ-6-GP

8 7 6

TP1803TPAD14-OP-GP TP1803TPAD14-OP-GP

B B

TP1804TPAD14-OP-GP TP1804TPAD14-OP-GP

PCH_GPIO50

1

PCH_GPIO54

2

PCH_GPIO02

3 45

1 1

Boot Bios Strap

GNT1#/GPIO51

0 0

10

1

0

1 1

PCI_GNT3#

12

DY

R1801

A A

R1801 4K7R2J-2-GP

4K7R2J-2-GP

A16 Swap Override jumper

PCI_GNT#3 Low = A16 swap override/Top-Block

Swap Override enabled High = Default

5

USB 3.0 Port USB 2.0 port Port 1 Port 2 Port 3 Port 4

BBS_BIT1 BBS_BIT0

Port 0 Port 1 Port 2 Port 3

BBS_BIT0 [21]

Boot BIOS LocationSATA1GP/GPIO19

LPC

Reserved

SPI(Default)

CLK_PCI_LPC[71] CLK_PCI_FB[20] CLK_PCI_KBC[27]

EC1802

DY

SC4D7P50V2CN-1GP

4

USB3.0/2.0 Mapping Table

BG16 AH38 AH37 AK43 AK45

C18 N30

AH12

AM4 AM5 Y13 K24

AB46 AB45

B21

M20 AY16 BG46

BE28 BC30 BE32

BJ32 BC28 BE30

BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

G38 C46

C44 E40

D47 E42

G42 G40 C42 D44

K10

H49 H43

K42 H40

L24

K40 K38 H38

F46

J48

H3

C6

TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

USB3RN1 USB3RN2 USB3RN3 USB3RN4 USB3RP1 USB3RP2 USB3RP3 USB3RP4 USB3TN1 USB3TN2 USB3TN3 USB3TN4 USB3TP1 USB3TP2 USB3TP3 USB3TP4

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PME# PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

PANTHER-GP-NF

3D3V_S0

3

RSVD

PCI

USB

PCH_GPIO52 INT_PIRQB# SATA_ODD_DA#

5 OF 10

RSVD1 RSVD2 RSVD3 RSVD4

RSVD5 RSVD6

RSVD7 RSVD8

RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22

RSVD23 RSVD24

RSVD25 RSVD26

RSVD27 RSVD28

RSVD29

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

RN1801

RN1801 SRN8K2J-2-GP-U

SRN8K2J-2-GP-U

1 2 3 4 5 6

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5 AV10

AT8 AY5

BA2 AT12

X01 12/20

BF3

X01 12/13

USB2.0 Signal Group

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB_RBIAS

C33

B33

USB_OC#0_1

A14

USB_OC#2_3

K20

USB_OC#4_5

B17

USB_OC#6_7

C16

USB_OC#8_9

L16

USB_OC#10_11

A16

USB_OC#12_13

D14

PCH_GPIO14

C14

3D3V_S5

10

INT_PIRQD#

9

PCH_GPIO05

8

INT_PIRQC#INT_PIRQA#

7

BLUETOOTH_EN

3D3V_S0

2

USB_PN0 [62] USB_PP0 [62] USB_PN1 [82] USB_PP1 [82]

USB_PN4 [82] USB_PP4 [82]

USB_PN8 [66] USB_PP8 [66]

USB_PN10 [82] USB_PP10 [82] USB_PN11 [65] USB_PP11 [65] USB_PN12 [49] USB_PP12 [49]

1 2

R1811

R1811 22D6R2F-L1-GP

22D6R2F-L1-GP

USB_OC#0_1 [62,82]

USB Table

Pair

USB3.0 port1, with Power Share

0

USB3.0 port2

1

NC

2

NC

3

Touch Panel

4

NC

5

NC

6

NC

7

WWAN

8

NC

9

Card reader

10

WLAN

11

CAMERA

12

NC

13

1. USB Ext. port 9 (HS) External debug port use on Chief River platform.

2. 2011 July; Microsoft will support USB3.0 debug--> Port1 useable.

Layout Note:

1. USBRBIAS/# use 50ohm single-ended impedance spacing to other signal=15mil

2. Length < 500mil

RN1802

SRN8K2J-2-GP-U

USB_OC#2_3 PCH_GPIO14

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, March 30, 2012

Date: Sheet of

SRN8K2J-2-GP-U

1 2 3 4 5 6

PCH (PCI/USB/NVRAM)

BMW Z4 DIS

Device

10

USB_OC#12_13

9

USB_OC#8_9USB_OC#6_7

8

USB_OC#10_11USB_OC#0_1

7

USB_OC#4_5

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

3D3V_S5

18 105

A00

5

4

3

2

1

SSID = PCH

3 OF 10

PCH1C

DMI_RXN[3:0][4]

D D

Layout Note:

DMI_ZCOMP keep W=4 mils and routing length less than 500 mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.

C C

PM_DRAM_PWRGD[37]

B B

Sequence: S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

3D3V_S0

XDP_DBRESET#[5]

SYS_PWROK[36]

S0_PWR_GOOD[27,36]

RUNPWROK[45,46,47]

RSMRST#_KBC[27]

PM_PWRBTN#[27]

AC_PRESENT[27]

X03 2/6

DMI_RXP[3:0][4]

DMI_TXN[3:0][4]

DMI_TXP[3:0][4]

1D05V_PCH

R1901 49D9R2F-GPR1901 49D9R2F-GP

1 2

R1902 750R2F-GPR1902 750R2F-GP

1 2

R1921

0R0402-PAD-2-GP

1 2

R1907 0R2J-2-GP

X02 2/6

1 2

0R0402-PAD-2-GP

TP1907TPAD14-OP-GP TP1907TPAD14-OP-GP

R1905 10KR2J-3-GPR1905 10KR2J-3-GP

1 2

X03 2/6

PWROK

R1916 0R0402-PAD-2-GPR1916 0R0402-PAD-2-GP

1 2

DY

R1924

1

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_COMP_R RBIAS_CPY

SUSACK#

MEPWROK

PM_RSMRST#

SUS_PW R_ACK

PM_PWRBTN#

AC_PRESENT

BATLOW #

PM_RI#

PCH1C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT/GPIO31

E10

BATLOW#/GPIO72

A10

RI#

PANTHER-GP-NF

71.PANTH.00U

DMI

SUS_STAT#/GPIO61

System Power Management

3 OF 10

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

FDI

FDI_RXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN#/GPIO32

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN#/GPIO29

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16 AV12 BC10 AV14 BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWODVREN

PCH_DPW ROK

PCH_WAKE#

PM_CLKRUN#

PM_SUS_STAT#

SUS_CLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_A#

PM_SLP_SUS#

H_PM_SYNC

PM_SLP_LAN#

FDI_TXN[7:0] [4]

FDI_TXP[7:0] [4]

FDI_INT [4] FDI_FSYNC0 [4] FDI_FSYNC1 [4] FDI_LSYNC0 [4] FDI_LSYNC1 [4]

R1911 10KR2J-3-GP

1 2

DY

R1927 0R0402-PAD-2-GPR1927 0R0402-PAD-2-GP

1 2

X03 2/13

R1910 0R2J-2-GP

1 2

DY

X03 2/6

DY

R1929 0R0402-PAD-2-GPR1929 0R0402-PAD-2-GP

1 2

TP1901 TPAD14-OP-GPTP1901 TPAD14-OP-GP

1

R1925 0R0402-PAD-2-GPR1925 0R0402-PAD-2-GP

1 2

TP1902 TPAD14-OP-GPTP1902 TPAD14-OP-GP

1

TP1903 TPAD14-OP-GPTP1903 TPAD14-OP-GP

1

TP1904 TPAD14-OP-GPTP1904 TPAD14-OP-GP

1

TP1905 TPAD14-OP-GPTP1905 TPAD14-OP-GP

1

RTC_AUX_S5

PM_RSMRST#

PCH_WAKE#_EC [27]

PM_CLKRUN#_EC [27]

PCH_SUSCLK_KBC [27]

PM_SLP_S4# [27,46]

PM_SLP_S3# [27,36,37,47]

H_PM_SYNC [5]

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled

DSWODVREN

PM_CLKRUN#

PCH_SUSCLK_KBC

R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP

1 2

R1919 8K2R2J-3-GPR1919 8K2R2J-3-GP

1 2

EC1901

SC4D7P50V2CN-1GP

EC1901

RTC_AUX_S5

3D3V_S0

DY

1 2

3D3V_S5

RN1901

1

8

2

7

3

6

45

SRN10KJ-6-GP

R1909 100KR2J-1-GPR1909 100KR2J-1-GP

1 2

R1920 10KR2J-3-GP

A A

R1908 10KR2J-3-GPR1908 10KR2J-3-GP

R1926 100KR2J-1-GP

R1926 100KR2J-1-GP R1904 100KR2J-1-GPR1904 100KR2J-1-GP

5

DY

1 2

DY

1 2

12

BATLOW # PM_RI# SUS_PW R_ACK PCH_WAKE#

AC_PRESENT

PM_SLP_LAN#

PM_RSMRST#

SYS_PWROK PWROK

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, March 30, 2012

Date: Sheet of

4

3

2

Date: Sheet of

PCH (DM I/FDI/PM)

BMW Z4 DIS

Taipei Hsien 221, Taiwan, R.O.C.

19 105

1

A00

5

SSID = PCH

3D3V_S5

D D

Layout Note:

C C

Layout trace < 14000mil

RN2001

1 2 3 4 5

SRN10KJ-6-GP

RN2002

1 2 3 4 5

SRN10KJ-6-GP

PCIE_RXN4[65] PCIE_RXP4[65] PCIE_TXN4[65] PCIE_TXP4[65]

PCIE_RXN6[31] PCIE_RXP6[31] PCIE_TXN6[31] PCIE_TXP6[31]

PCIE_CLK_REQ6#

8

CLK_PCIE_WLAN_REQ#

7

PCIE_CLK_REQ0#

6

PCIE_CLK_REQ4#

X01 12/09

8 7 6

EC_SWI#

PCIE_CLK_LAN_REQ#

CLK_PCIE_REQ7# CLK_PEG_B_REQ#

C2005 SCD1U10V2KX-5GPC2005 SCD1U10V2KX-5GP

1 2

C2006 SCD1U10V2KX-5GPC2006 SCD1U10V2KX-5GP

1 2

C2001 SCD1U10V2KX-5GPC2001 SCD1U10V2KX-5GP

1 2

C2002 SCD1U10V2KX-5GPC2002 SCD1U10V2KX-5GP

1 2

S5 power rail CLKREQ#: PCIECLKRQ[0]# PCIECLKRQ[7:3]#

PCIE_CLK_RQ6# PCIE_CLK_RQ3# PCIE_CLK_RQ0# PCIE_CLK_RQ4#

PCIE_CLK_RQ5# PCIE_CLK_RQ7#

PCIE_TXN4_C PCIE_TXP4_C

PCIE_TXN6_C PCIE_TXP6_C

PCIE_CLK_REQ0#

X01 12/09

Layout Note:

CLKOUT termination place close to PCH <500mil

A00 3/23 X02 2/6

CLK_PCIE_WLAN#[65]

B B

CLK_PCIE_WLAN[65]

CLK_PCIE_WLAN_REQ#[65]

CLK_PCIE_LAN#[31] CLK_PCIE_LAN[31]

PCIE_CLK_LAN_REQ#[31]

1 2 3

RN2012RN0R4P2R-PAD

RN2012

1 2 3

RN2014RN0R4P2R-PAD

RN2014

RN

4

0R4P2R-PAD

RN

4

0R4P2R-PAD

CLK_PCIE_REQ1#

PCIE_CLK_REQ2#

CLK_PCH_SRC3_N CLK_PCH_SRC3_P

PCIE_CLK_REQ4#

CLK_PCH_SRC5_N CLK_PCH_SRC5_P

X01 12/09

Layout Note:

Layout trace < 14000mil

CLK_PEG_B_REQ#

PCIE_CLK_REQ6#

X01 12/09

A A

TP2007TPAD14-OP-GP TP2007TPAD14-OP-GP TP2008TPAD14-OP-GP TP2008TPAD14-OP-GP

5

CLK_PCIE_REQ7#

PCIE_CLK_XDP_N_R

1

PCIE_CLK_XDP_P_R

1

4

PCH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0#/GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1#/GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2#/GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4#/GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5#/GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ#/GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6#/GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7#/GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

PANTHER-GP-NF

71.PANTH.00U

4

3D3V_S0

NC

WLAN

NC

LAN

NC

RN2018

1 2 3

SRN10KJ-5-GP

PCI-E*

NC

WLAN CLK

NC

LAN CLK

NC

X01 12/09

PCIE_CLK_REQ2#

4

CLK_PCIE_REQ1#

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SMBUSController

SML1ALERT#/PCHHOT#/GPIO74

SML1DATA/GPIO75

Link

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLOCKS

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64 CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67

FLEX CLOCKS

PCIE_CLK_RQ2# PCIE_CLK_RQ1#

2 OF 10

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK/GPIO58

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

3

S0 power rail CLKREQ#: PCIECLKRQ[2:1]#

EC_SWI#

E12

SMB_CLK

H14

SMB_DATA

C9

DRAMRST_CNTRL_PCH

A12

SML0_CLK

C8

SML0_DATA

G12

PCH_GPIO74

C13

SML1_CLK

E14

SML1_DATA

M16

CL_CLK

M7

CL_DATA

T11

CL_RST#

P10

PEG_CLKREQ#_R

M10

CLKOUT_PEG_A_N

AB37

CLKOUT_PEG_A_P

AB38

CLKOUT_DMI_N

AV22

CLKOUT_DMI_P

AU22

AM12 AM13

CLK_BUF_EXP_N

BF18

CLK_BUF_EXP_P

BE18

CLK_BUF_CPYCLK_N

BJ30

CLK_BUF_CPYCLK_P

BG30

CLK_BUF_DOT96_N

G24

CLK_BUF_DOT96_P

E24

CLK_BUF_CKSSCD_N

AK7

CLK_BUF_CKSSCD_P

AK5

CLK_BUF_REF14

K45

CLK_PCI_FB

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

JTAG_TCK

K43

CARD_READER_48M

F47

CLK_27M_VGA_R

H47

BOARD_ID1

K49

3

TP2001 TPAD14-OP-GPTP2001 TPAD14-OP-GP

1

TP2002 TPAD14-OP-GPTP2002 TPAD14-OP-GP

1

TP2003 TPAD14-OP-GPTP2003 TPAD14-OP-GP

1

A00 3/23

CLK_PCI_FB [18]

R2007

1 2

90D9R2F-1-GP

EC_SWI# [27]

SML1_CLK [27,28,85] SML1_DATA [27,28,85]

R2003

R2003 0R2J-2-GP

0R2J-2-GP

1 2

DY

RN2016

1

RN

2 3

SG

SRN0J-6-GP

1 2 3

RN2017RN0R4P2R-PAD

RN2017

RN2019

SRN10KJ-5-GP

RN2008

SRN10KJ-5-GP

RN2020

SRN10KJ-5-GP

RN2021

SRN10KJ-5-GP

R2008

10KR2J-3-GP

TP2004 TPAD14-OP-GPTP2004 TPAD14-OP-GP

1

TP2005 TPAD14-OP-GPTP2005 TPAD14-OP-GP

1

TP2006 TPAD14-OP-GPTP2006 TPAD14-OP-GP

1

2

3D3V_S5

UMA

PEG_CLKREQ#_R

SG

DRAMRST_CNTRL_PCH [37]

Layout Note:

Can Place Far away PCH

SMB_DATA

SMB_CLK

Layout Note:

CLKOUT termination place close to PCH <500mil

PEG_CLKREQ# [85]

4

0R4P2R-PAD

2 3 1

1 2

+VCCDIFFCLKN

CLK_PCIE_VGA# [83] CLK_PCIE_VGA [83]

CLK_EXP_N [5] CLK_EXP_P [5]

4

Layout Note:

1500mil < Layout trace < 10000mil

2

12

R2004

R2004 10KR2J-3-GP

10KR2J-3-GP

12

R2005

R2005 10KR2J-3-GP

10KR2J-3-GP

3D3V_S0

1

RN2007

2 3 1

SRN2K2J-1-GP

6 5

Q2001

Q2001 2N7002KDW-GP

2N7002KDW-GP

XTAL25_IN

R2006

1M1R2J-GP

XTAL25_OUT

BOARD_ID2[22]

SMB_CLK SMB_DATA

SML0_DATA SML0_CLK SML1_CLK SML1_DATA

PCH_GPIO74 DRAMRST_CNTRL_PCH

4

1 2 34

2 3

1 2

82.30020.D41

2nd = 82.30020.G61

10KR2J-3-GP

BOARD_ID1 BOARD_ID2

10KR2J-3-GP

4

1 2 3 4 5

R2011 10KR2J-3-GPR2011 10KR2J-3-GP

1 2

R2009 1KR2J-1-GPR2009 1KR2J-1-GP

CRB : 1K CEKLT: 10K

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

X2001

41

XTAL-25MHZ-155-GP

3D3V_S0

12

R2013

UMA

12

R2012

SG

RN2003

1

SRN2K2J-1-GP

23

RN2004

8

SRN2K2J-2-GP

7 6

PCH_SMBDATA [14,15,65,66,69]

PCH_SMBCLK [14,15,65,66,69]

1 2

C2008

SC15P50V2JN-2-GP

C2007

SC15P50V2JN-2-GP

1 2

12

R2010

10KR2J-3-GP

BIOS UMA/DIS Strap pin

BOARD_ID1

PX(AMD)

DIS

UMA

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

Optimus(NV)

PCH (PCI-E/SMBUS/CLOCK/CL)

BMW Z4 DIS

Friday, March 30, 2012

BMW Z4 DIS

0 0

0

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

BOARD_ID2

20 105

1

0

1

3D3V_S5

A00

5

4

3

2

1

SSID = PCH

D D

HDA_SPKR

HDA_SYNC

G

S

R2123

R2123 33R2J-2-GP

33R2J-2-GP

R2125

R2125 33R2J-2-GP

33R2J-2-GP

R2126

R2126 33R2J-2-GP

33R2J-2-GP

RTCRST_ON[27]

12

R2122

10KR2J-3-GP

HDA_CODEC_SDOUT[82]

C C

HDA_CODEC_RST#[82]

HDA_CODEC_BITCLK[82]

Layout Note:

Place at the separated point

3D3V_S0

R2106 1KR2J-1-GP

1 2

DY

B B

HDA_SPKR

+3VS_+1.5VS_HDA_IO

R2103 1KR2J-1-GPR2103 1KR2J-1-GP

DY

No Reboot Strap

Low = Default High = No Reboot

1 2

*

RTC_AUX_S5

RN2102

1 2 3

SRN20KJ-1-GP

Q2102

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

HDA_SDOUT

12

Flash Descriptor Security Overide/ Intel ME Debug Mode

HDA_SDOUT

HDA_RST#

HDA_BITCLK

Low = Default High = Enable

SC1U6D3V2KX-GP

Layout Note:

Place close together. For RNxxxx later.

4

12

C2104

SC1U6D3V2KX-GP

12

C2103

Layout Note:

HDA_SDO and HDA_BCLK must be length matched to within 500 mils

ME_UNLOCK[27]

3D3V_S5

*

PLL ODVR VOLTAGE

HDA_SYNC

HDA_CODEC_SYNC[82]

A A

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.

Low = 1.8V High = 1.5V

*

R2124

12

33R2J-2-GP

5

RUN_ENABLE[36,37]

HDA_CODEC_SYNC_R

1 2

R2117

R2117 1M1R2J-GP

1M1R2J-GP

Q2101

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

4

Layout Note:

Place it at the open door location.

21

G2101

G2101 GAP-OPEN

GAP-OPEN

RTC_AUX_S5

R2111 51R2J-2-GP

R2111 51R2J-2-GP R2118 210R2F-L-GP

R2118 210R2F-L-GP R2119 210R2F-L-GP

R2119 210R2F-L-GP R2120 210R2F-L-GP

R2120 210R2F-L-GP

SPI_CLK_R[27,60] SPI_CS0#_R[27,60]

SPI_SI_R[27,60]

SPI_SO_R[27,60]

Integrated SUS 1V VRM Enable

INTVRMEN

R2104

1M1R2J-GP

1 2

R2105

R2105 330KR2F-L-GP

330KR2F-L-GP

HDA_SPKR[82]

HDA_SDIN0[82]

R2107

1KR2J-1-GP

1 2

DY

1 2

DY

1 2

DY

1 2

DY

HDA_SDOUT

TP2101TPAD14-OP-GP TP2101TPAD14-OP-GP TP2102TPAD14-OP-GP TP2102TPAD14-OP-GP

1 2

R2108 33R2J-2-GPR2108 33R2J-2-GP

1 2

R2109 33R2J-2-GPR2109 33R2J-2-GP

1 2

R2110 33R2J-2-GPR2110 33R2J-2-GP

1 2

R2115 33R2J-2-GPR2115 33R2J-2-GP

X01 12/21

HDA_SYNC

D

HDA_CODEC_BITCLK HDA_CODEC_SDOUT

EC2103

DY

EC2102

1 2

SC4D7P50V2CN-1GP

DY

EC2103

1 2

SC4D7P50V2CN-1GP

Low = External VRs High = Internal VRs

RTC_X1 RTC_X2 RTC_RST# SRTC_RST# SM_INTRUDER#

12

PCH_INTVRMEN

HDA_BITCLK HDA_SYNC

HDA_RST#

PCH_GPIO33

1

PCH_GPIO13

1

PCH_JTAG_TCK_BUF PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO

PCH_SPI_CLK PCH_SPI_CS0#

PCH_SPI_SI PCH_SPI_SO

*

1 OF 10

PCH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN#/GPIO33

N32

HDA_DOCK_RST#/GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER-GP-NF

71.PANTH.00U

3

RTCIHDA

JTAG

SPI

R2101 10MR2J-L-GPR2101 10MR2J-L-GP

12

SC15P50V2JN-2-GP

2 3

2nd = 82.30001.841

C2101

1 OF 10

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LPC

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED# SATA0GP/GPIO21 SATA1GP/GPIO19

1 2

X2101

41

X-32D768KHZ-65-GP

82.30001.A41

LPC_LAD0_PCH

C38

LPC_LAD1_PCH

A38

LPC_LAD2_PCH

B37

LPC_LAD3_PCH

C37

LPC_LFRAME#_PCH

D36 E36

K36 V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

AB12 AB13

AH1

SATA_LED#

P3

PCH_GPIO21

V14

BBS_BIT0

P1

RTC_X1 RTC_X2

12

C2102

C2102 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

2

A00 3/27

R2116 0R0402-PAD-2-GPR2116 0R0402-PAD-2-GP

1 2

R2121 0R0402-PAD-2-GPR2121 0R0402-PAD-2-GP

1 2

R2127 0R0402-PAD-2-GPR2127 0R0402-PAD-2-GP

1 2

R2128 0R0402-PAD-2-GPR2128 0R0402-PAD-2-GP

1 2 1 2

R2136 0R0402-PAD-2-GPR2136 0R0402-PAD-2-GP

KB_DET# [69] INT_SERIRQ [27]

SATA_RXN0 [56] SATA_RXP0 [56] SATA_TXN0 [56] SATA_TXP0 [56]

SATA_RXN1 [66] SATA_RXP1 [66] SATA_TXN1 [66] SATA_TXP1 [66]

SATA_RXN4 [56] SATA_RXP4 [56] SATA_TXN4 [56] SATA_TXP4 [56]

Layout Note:

HDD < 6000mil, mSATA < 6000mil, ODD < 12500mil

SATA_COMP

SATA3_COMP

RBIAS_SATA3

R2112 37D4R2F-GPR2112 37D4R2F-GP

R2113 49D9R2F-GPR2113 49D9R2F-GP

R2114 750R2F-GPR2114 750R2F-GP

INT_SERIRQ PCH_GPIO21

Layout Note:

Place near PCH

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME# [27,71]

LPC_AD[3..0]

LPC_AD[3..0] [27,71]

HDD1

mSATA

ODD

1D05V_PCH

1 2

SATA_LED# [68]

BBS_BIT0 [18]

RN2103

1

4

2 3

SRN10KJ-5-GP

Title

PCH (SPI/RTC/LPC/SATA/IHDA)

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, March 30, 2012

Date: Sheet of

1D05V_PCH

Layout Note:

Place close PCH(<500mil)

3D3V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

BMW Z4 DIS

1

21 105

A00

5

4

3

2

1

SSID = PCH

6 OF 10

PCH1F

PCH_GPIO00

EC_SMI#[27]

3D3V_S0

D D

3D3V_S0

C C

3D3V_S5

B B

RN2203

RN2203 SRN10KJ-5-GP

SRN10KJ-5-GP

1

4

2 3

RN2205

RN2205 SRN10KJ-5-GP

SRN10KJ-5-GP

1

4

2 3

RN2206

SRN10KJ-6-GP

1

8

2

7

3

6

4 5

RN2201

RN2201 SRN10KJ-6-GP

SRN10KJ-6-GP

1

8

2

7

3

6

4 5

RN2204

RN2204 SRN10KJ-5-GP

SRN10KJ-5-GP

1

4

2 3

12

DY

R2221 10KR2J-3-GP

DY

12 12

R2224 10KR2J-3-GP

R2224 10KR2J-3-GP R2201 1KR2J-1-GP

R2201 1KR2J-1-GP

H_A20GATE_PCH H_RCIN#

SATA_ODD_PRSNT# PCH_GPIO00

PCH_GPIO49 MSATA_DET# PCH_GPIO38 DBC_EN

EC_SMI# EC_SCI# PCH_GPIO6 DGPU_PW ROK

RTC_DET# PCH_GPIO57

COLOR_ENGINE

PCH_GPIO08 PCH_GPIO15

EC_SCI#[27]

RTC_DET#[60]

SATA_ODD_PRSNT#[56]

DGPU_PW ROK[27,86,92,93]

DBC_EN[49]

COLOR_ENGINE[49]

TP2209TPAD14-OP-GP TP2209TPAD14-OP-GP

MSATA_DET#[66]

TP2210TPAD14-OP-GP TP2210TPAD14-OP-GP

DGPU_HOLD_RST#[83] DGPU_PW R_EN#[93]

TP2211TPAD14-OP-GP TP2211TPAD14-OP-GP TP2212TPAD14-OP-GP TP2212TPAD14-OP-GP

EC_SMI# PCH_GPIO6 EC_SCI# PCH_GPIO08 RTC_DET# PCH_GPIO15

SATA_ODD_PRSNT#

DGPU_PW ROK DBC_EN COLOR_ENGINE

PCH_GPIO27

1

PLL_ODVR_EN MSATA_DET# PCH_GPIO35

1

PCH_GPIO36 PCH_GPIO37 PCH_GPIO38 DGPU_HOLD_RST# DGPU_PW R_EN# PCH_GPIO49 PCH_GPIO57

1 1

X01 12/09

3D3V_S0

DY

12

DY

R2225 10KR2J-3-GP

R2225 10KR2J-3-GP R2226 10KR2J-3-GP

R2226 10KR2J-3-GP R2227 10KR2J-3-GPR2227 10KR2J-3-GP

R2228 10KR2J-3-GPR2228 10KR2J-3-GP

RN2202

RN2202 SRN10KJ-5-GP

SRN10KJ-5-GP

1 2 3

12 12

12

4

DGPU_PW R_EN#

DGPU_HOLD_RST#

DGPU_PW R_EN#

DGPU_HOLD_RST#

PCH_GPIO36 PCH_GPIO37

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49/TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1#A4

A44

VSS_NCTF_2#A44

A45

VSS_NCTF_3#A45

A46

VSS_NCTF_4#A46

A5

VSS_NCTF_5#A5

A6

VSS_NCTF_6#A6

B3

VSS_NCTF_7#B3

B47

VSS_NCTF_8#B47

BD1

VSS_NCTF_9#BD1

BD49

VSS_NCTF_10#BD49

BE1

VSS_NCTF_11#BE1

BE49

VSS_NCTF_12#BE49

BF1

VSS_NCTF_13#BF1

BF49

VSS_NCTF_14#BF49

PANTHER-GP-NF

71.PANTH.00U

GPIO

NCTF

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,

BD1,BD49,BE1,BE49,BF1,BF49,

BG2,BG48,BH3,BH47,BJ4,BJ44,

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,

D49,E1,E49,F1,F49

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,

BD1,BD49,BE1,BE49,BF1,BF49,

BG2,BG48,BH3,BH47,BJ4,BJ44,

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,

D49,E1,E49,F1,F49

6 OF 10

TACH4/GPIO68 TACH5/GPIO69 TACH6/GPIO70 TACH7/GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

VSS_NCTF_15#BG2

VSS_NCTF_16#BG48

VSS_NCTF_17#BH3

VSS_NCTF_18#BH47

VSS_NCTF_19#BJ4 VSS_NCTF_20#BJ44 VSS_NCTF_21#BJ45 VSS_NCTF_22#BJ46

VSS_NCTF_23#BJ5

VSS_NCTF_24#BJ6

VSS_NCTF_25#C2

VSS_NCTF_26#C48

VSS_NCTF_27#D1

VSS_NCTF_28#D49

VSS_NCTF_29#E1

VSS_NCTF_30#E49

VSS_NCTF_31#F1

VSS_NCTF_32#F49

C40 B41 C41 A40

P4 AU16 P5 AY11 AY10 T14 AY1

AH8 AK11 AH10 AK10

P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

SATA_ODD_PWRGT BOARD_ID2 PCH_GPIO70 PCH_GPIO71

H_A20GATE_PCH H_PECI_R H_RCIN# H_CPUPW RGD PCH_THERMTRIP_R INIT3_3V# DF_TVS

PCH_NCTF_BG2 PCH_NCTF_BG48 PCH_NCTF_BH3 PCH_NCTF_BH47

PCH_NCTF_C2PCH_NCTF_B3 PCH_NCTF_C48PCH_NCTF_B47

1 1

1

SATA_ODD_PWRGT [56] BOARD_ID2 [20]

TP2201 TPAD14-OP-GPTP2201 TPAD14-OP-GP TP2202 TPAD14-OP-GPTP2202 TPAD14-OP-GP

A00 3/23

R2205

R2205 0R0402-PAD-2-GP

0R0402-PAD-2-GP

1 2

R2203 0R2J-2-GP

1 2

DY

H_RCIN# [27] H_CPUPW RGD [5]

R2204 390R2J-1-GPR2204 390R2J-1-GP

1 2

TP2213 TPAD14-OP-GPTP2213 TPAD14-OP-GP

Layout Note:

Check these fuor balls are connected firstly, then to GND

TP2203 TPAD14-OP-GPTP2203 TPAD14-OP-GP

1

TP2204 TPAD14-OP-GPTP2204 TPAD14-OP-GP

1

TP2205 TPAD14-OP-GPTP2205 TPAD14-OP-GP

1

TP2206 TPAD14-OP-GPTP2206 TPAD14-OP-GP

1

TP2207 TPAD14-OP-GPTP2207 TPAD14-OP-GP

1

TP2208 TPAD14-OP-GPTP2208 TPAD14-OP-GP

1

H_A20GATE [27]

H_PECI [5,27]

R2202 2K2R2J-2-GPR2202 2K2R2J-2-GP

1 2

R2209

DF_TVS

R2209

1 2

1KR2J-1-GP

VCCP_CPU

1D8V_S0

12

R2207

R2207 2K2R2J-2-GP

2K2R2J-2-GP

H_THERMTRIP# [5]

H_SNB_IVB# [5]

A A

R2212 1KR2J-1-GP

PLL ON DIE VR ENABLE

GPIO28 (PLL_ODVR_EN)

5

Weakly internal pull up 20k. High - Enable LOW - Disable

DMB40

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, March 30, 2012

Date: Sheet of

4

3

2

Date: Sheet of

PCH (GPIO/CPU)

BMW Z4 DIS

Taipei Hsien 221, Taiwan, R.O.C.

22 105

1

A00

PLL_ODVR_EN

12

DY

R2212 1KR2J-1-GP

5

4

3

2

1

SSID = PCH

Voltage Rail

V_PROC_IO V5REF V5REF_Sus Vcc3_3 VccADAC VccADPLLA VccADPLLB VccCore VccDMI VccIO VccASW VccSPI VccDSW3_3 VccDFTERM VccRTC VccSus3_3 VccSusHDA VccVRM VccClkDMI VccSSC VccDIFFCLKN VccALVDS VccTX_LVDS

Refer to chipset EDS V.0.7

R2307

R2306

R2308

3D3V_S0

1D8V_S0

3D3V_S0

1D5V_S0

VCCP_CPU

1D05V_PCH

1D8V_S0

3D3V_S5

7 OF 10

POWER

PCH1G

AA23 AC23 AD21 AD23 AF21

AF23 AG21 AG23 AG24 AG26 AG27 AG29

AJ23 AJ26 AJ27 AJ29 AJ31

AN19

BJ22

AN16

AN17

AN21

AN26

AN27

AP21

AP23

AP24

AP26

AT24

AN33

AN34

BH29

AP16

BG6

AP17

AU20

PCH1G

VCCCORE1 VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE5 VCCCORE6 VCCCORE7 VCCCORE8 VCCCORE9 VCCCORE10 VCCCORE11 VCCCORE12 VCCCORE13 VCCCORE14 VCCCORE15 VCCCORE16 VCCCORE17

VCCIO28

VCCAPLLEXP

VCCIO15 VCCIO16

VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26

VCC3_3_3

VCCVRM2

VCCAFDIPLL

VCCIO27

VCCDMI2

PANTHER-GP-NF

71.PANTH.00U

1D05V_PCH

D D

C C

1D05V_PCH

B B

X03 2/16

3D3V_S0

12

1.7A

3.711A

EC2305

SCD1U10V2KX-5GP

0.228A

C2310

SCD1U10V2KX-5GP

DY

12

DY

C2301

SC10U6D3V5KX-1GP

TP2301TPAD14-OP-GP TP2301TPAD14-OP-GP

12

C2306

DY

SC1U6D3V2KX-GP

12

C2302

SC1U6D3V2KX-GP

12

C2307

SCD1U10V2KX-5GP

TP2302TPAD14-OP-GP TP2302TPAD14-OP-GP

C2303

SC1U6D3V2KX-GP

1D05V_PCH

1

C2308

SCD1U10V2KX-5GP

1D05V_PCH

1D05VS_VCC_DMI

12

VCCAPLLEXP

12

VCCVRM

VCCFDIPLL

1

C2304

SC1U6D3V2KX-GP

C2309

SC1U6D3V2KX-GP

POWER

VCC CORE

VCCIO

FDI

CRTLVDS

DMI

DFT / SPI HVCMOS

7 OF 10

VCCADAC

VSSADAC

VCCALVDS VSSALVDS

VCCTX_LVDS1 VCCTX_LVDS2 VCCTX_LVDS3 VCCTX_LVDS4

VCC3_3_6

VCC3_3_7

VCCVRM3

VCCDMI1

VCCCLKDMI

VCCDFTERM1

VCCDFTERM2

VCCDFTERM3

VCCDFTERM4

VCCSPI

U48

U47

AK36 AK37

AM37 AM38 AP36 AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

12

C2313

+3VS_VCCA_LVDS

+1.8VS_VCCTX_LVDS

12

C2319

C2319 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

VCCVRM

1D05VS_VCC_DMI

12

C2320

C2320 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

+1.05VS_VCC_DMI_CCI

12

C2321

C2321 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C2322

C2322 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2323

C2323 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

0.061A

C2314

12

DY

C2315

SCD1U10V2KX-5GP

SC10U6D3V3MX-GP

12

C2317

C2318

SCD01U16V2KX-3GP

SC22U6D3V5MX-2GP

0.001A

0.04A

0.228A

X03 2/6

R2304

1 2

0R0603-PAD-2-GP

R2301

1 2

0R0603-PAD-2-GP

X03 2/6

0R0402-PAD-2-GP

0.167A

0.047A

0.07A

0R0402-PAD-2-GP

1 2

0R0402-PAD-2-GP

1 2

0R0402-PAD-2-GP

1 2

12

SCD01U16V2KX-3GP

C2316

SCD01U16V2KX-3GP

0.002A

0.01A

Voltage(V)

1.05 5 5

3.3

1.05

1.1

1.05

3.3

1.8

3.3

1.5

1.05

3.3

1.8

Iccmax(A)

0.001

0.228

0.063

0.08

1.7

0.047

3.711

0.903

0.01

0.001

0.002 6uA

0.095

0.01

0.167

0.07

0.095

0.055

0.001

0.04

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, March 30, 2012

Date: Sheet of

PCH (POWER1)

BMW Z4 DIS

Taipei Hsien 221, Taiwan, R.O.C.

23 105

1

A00

5

4

3

2

1

SSID = PCH

DY

12

VCCVRM

12

1

C2405

SC1U6D3V2KX-GPDYC2405

SC1U6D3V2KX-GP

1

C2418

SCD1U10V2KX-5GP

C2421

SCD1U10V2KX-5GP

VCCACLK

3D3V_S5

DCPSUSBYP

+V3.3S_VCC_CLKF33

+VCCAPLL_CPY_PCH

+VCCSUS1

C2419

SC1U6D3V2KX-GPDYC2419

SC1U6D3V2KX-GP

12

DY

+VCCRTCEXT

0.167A

+1.05VS_VCCA_A_DPL +1.05VS_VCCA_B_DPL

+VCCDIFFCLK

+V1.05S_SSCVCC

+VCCSST

DCPSUS

12

C2420

SCD1U10V2KX-5GP

12

C2422

SCD1U10V2KX-5GP

12

SC22U6D3V5MX-2GP

C2411

+VCCDIFFCLKN

C2414

C2415

C2417

C2436

TP2401TPAD14-OP-GP TP2401TPAD14-OP-GP

TP2402

TPAD14-OP-GP

TP2403

TPAD14-OP-GP

TP2404

TPAD14-OP-GP

C2406

SC1U6D3V2KX-GP

C2406

SC1U6D3V2KX-GP

12

TP2405

TPAD14-OP-GP

12

4

3D3V_S5

DG: none

3D3V_S0

D D

C C

1D05V_PCH

B B

CRB: 10uH

L2401

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.1001E.10N

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.1001E.10N

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.1001E.10N

L2402

L2403

SC10U6D3V5KX-1GP

C2401

+1.05VS_VCCA_A_DPL

12

DY

+1.05VS_VCCA_B_DPL

12

X03 2/16

+V3.3S_VCC_CLKF33

12

DY

0.08A

12

C2408

0.08A

SC10U6D3V5KX-1GP

12

EC2409

SCD1U10V2KX-5GP

1D05V_PCH

X03 2/6

1D05V_PCH

A A

1D05V_PCH

R2403

R2403 0R0402-PAD-2-GP

0R0402-PAD-2-GP

1 2

R2404

R2404 0R0402-PAD-2-GP

0R0402-PAD-2-GP

1 2

+VCCDIFFCLK

12

C2412

SC1U6D3V2KX-GP

0.095A

+V1.05S_SSCVCC

12

C2413

SC1U6D3V2KX-GP

5

0.001A

12

C2402

C2402 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1D05V_PCH

0.93A

DY

X01 1/9

C2407

C2407 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2410

C2410 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

0.055A

R2412

R2412 0R0603-PAD-2-GP

0R0603-PAD-2-GP

X03 2/6

VCCP_CPU

RTC_AUX_S5

SCD1U10V2KX-5GP

1D05V_PCH

SC22U6D3V5MX-2GP

12

C2403

SCD1U10V2KX-5GP

1 2

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

SC1U6D3V2KX-GP

C2416

12

C2404

0.001A

6uA

AD49

BH23 AL29

AL24

AA19 AA21 AA24 AA26 AA27 AA29 AA31 AC26 AC27 AC29 AC31 AD29 AD31

W21 W23 W24 W26 W29 W31 W33

BD47 BF47

AF17 AF33 AF34

AG34

AG33

T16

V12

T38

N16

Y49

V16

T17 V19

BJ8

A22

PCH1J

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3_5

VCCAPLLDMI2 VCCIO14

DCPSUS3

VCCASW1 VCCASW2 VCCASW3 VCCASW4 VCCASW5 VCCASW6 VCCASW7 VCCASW8 VCCASW9 VCCASW10 VCCASW11 VCCASW12 VCCASW13 VCCASW14 VCCASW15 VCCASW16 VCCASW17 VCCASW18 VCCASW19 VCCASW20

DCPRTC

VCCVRM4

VCCADPLLA VCCADPLLB

VCCIO7 VCCDIFFCLKN1 VCCDIFFCLKN2 VCCDIFFCLKN3

VCCSSC

DCPSST

DCPSUS1 DCPSUS2

V_PROC_IO

VCCRTC

PANTHER-GP-NF

71.PANTH.00U

POWER

Clock and Miscellaneous

CPURTC

3

PCI/GPIO/LPCMISC

SATA USB

HDA

10 OF 10

N26

VCCIO29

P26

VCCIO30

P28

VCCIO31

T27

VCCIO32

T29

VCCIO33

VCCSUS3_3_7 VCCSUS3_3_8 VCCSUS3_3_9

VCCSUS3_3_10

VCCSUS3_3_6

V5REF_SUS

VCCSUS3_3_1

VCCSUS3_3_2 VCCSUS3_3_3 VCCSUS3_3_4 VCCSUS3_3_5

VCCAPLLSATA

VCCASW22

VCCASW23

VCCASW21

VCCSUSHDA

T23 T24 V23 V24 P24

T26

VCCIO34

M26

AN23

DCPSUS4

AN24

P34

V5REF

N20 N22 P20 P22

AA16

VCC3_3_1

W16

VCC3_3_8

T34

VCC3_3_4

AJ2

VCC3_3_2

AF13

VCCIO5

AH13

VCCIO12

AH14

VCCIO13

AF14

VCCIO6

AK1

AF11

VCCVRM1

AC16

VCCIO2

AC17

VCCIO3

AD17

VCCIO4

1D05V_PCH

T21

V21

T19

P32

SCD1U10V2KX-5GP

VCCSUSHDA need to be at either 3.3V or 1.5V. All the CODEC I/O Voltages need to be at the same level either 3.3 V or 1.5 V.

12

C2424

C2424 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1D05V_PCH

+5VA_PCH_VCC5REFSUS

+VCCA_USBSUS

3D3V_S5

+5VS_PCH_VCC5REF

SC1U6D3V2KX-GP

12

C2431

C2431 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

+V1.05S_VCCAPLL_SATA3

VCCVRM

SC1U6D3V2KX-GP

+3VS_+1.5VS_HDA_IO

0.01A

12

C2433

C2438

C2438 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

DY

12

C2428

3D3V_S0

12

C2429

12

C2432

DY

12

C2435

C2425

C2425 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2437

C2437 SC1U10V2KX-1GP

SC1U10V2KX-1GP

1

TPAD14-OP-GP

1 2

R2402

R2402 0R0402-PAD-2-GP

0R0402-PAD-2-GP

X03 2/6

2

0.095A

TP2406

1D05V_PCH

3D3V_S5

(0.1uFx1)

0.001A

3D3V_S5

3D3V_S0

12

3D3V_S0

1D05V_PCH

3D3V_S5

21

D2401

D2401 CH751H-40PT-GP

12

3D3V_S0

21

12

CH751H-40PT-GP

D2402

D2402 CH751H-40PT-GP

CH751H-40PT-GP

R2408

1 2

10R2J-2-GP

C2426

C2426 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1 2

10R2J-2-GP

C2427

C2427 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

83.R0304.A8F

2nd = 83.R2004.B8F

83.R0304.A8F

2nd = 83.R2004.B8F

Voltage Rail

C2430

C2430 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

V_PROC_IO V5REF V5REF_Sus Vcc3_3 VccADAC VccADPLLA VccADPLLB VccCore VccDMI VccIO VccASW VccSPI VccDSW3_3 VccDFTERM VccRTC VccSus3_3 VccSusHDA VccVRM VccClkDMI VccSSC VccDIFFCLKN VccALVDS VccTX_LVDS

DMB40

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, March 30, 2012

Date: Sheet of

Refer to chipset EDS V.0.7

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (POWER2)

BMW Z4 DIS

R2407

5V_S5

5V_S0

Voltage(V)

1.05 5 5

3.3

1.05

1.1

1.05

3.3

1.8

3.3

1.5

1.05

3.3

1.8

24 105

1

Iccmax(A)

0.001

0.228

0.063

0.08

1.7

0.047

3.711

0.903

0.01

0.001

0.002 6uA

0.095

0.01

0.167

0.07

0.095

0.055

0.001

0.04

A00

5

4

3

2

1

SSID = PCH

D D

C C

B B

A A

5

PCH1H

H5

VSS0

AA17

VSS1

AA2

VSS2

AA3

VSS3

AA33

VSS4

AA34

VSS5

AB11

VSS6

AB14

VSS7

AB39

VSS8

AB4

VSS9

AB43

VSS10

AB5

VSS11

AB7

VSS12

AC19

VSS13

AC2

VSS14

AC21

VSS15

AC24

VSS16

AC33

VSS17

AC34

VSS18

AC48

VSS19

AD10

VSS20

AD11

VSS21

AD12

VSS22

AD13

VSS23

AD19

VSS24

AD24

VSS25

AD26

VSS26

AD27

VSS27

AD33

VSS28

AD34

VSS29

AD36

VSS30

AD37

VSS31

AD38

VSS32

AD39

VSS33

AD4

VSS34

AD40

VSS35

AD42

VSS36

AD43

VSS37

AD45

VSS38

AD46

VSS39

AD8

VSS40

AE2

VSS41

AE3

VSS42

AF10

VSS43

AF12

VSS44

AD14

VSS45

AD16

VSS46

AF16

VSS47

AF19

VSS48

AF24

VSS49

AF26

VSS50

AF27

VSS51

AF29

VSS52

AF31

VSS53

AF38

VSS54

AF4

VSS55

AF42

VSS56

AF46

VSS57

AF5

VSS58

AF7

VSS59

AF8

VSS60

AG19

VSS61

AG2

VSS62

AG31

VSS63

AG48

VSS64

AH11

VSS65

AH3

VSS66

AH36

VSS67

AH39

VSS68

AH40

VSS69

AH42

VSS70

AH46

VSS71

AH7

VSS72

AJ19

VSS73

AJ21

VSS74

AJ24

VSS75

AJ33

VSS76

AJ34

VSS77

AK12

VSS78

AK3

VSS79

PANTHER-GP-NF

71.PANTH.00U

8 OF 10

VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

4

PCH1I

AY4

VSS159

AY42

VSS160

AY46

VSS161

AY8

VSS162

B11

VSS163

B15

VSS164

B19

VSS165

B23

VSS166

B27

VSS167

B31

VSS168

B35

VSS169

B39

VSS170

B7

VSS171

F45

VSS172

BB12

VSS173

BB16

VSS174

BB20

VSS175

BB22

VSS176

BB24

VSS177

BB28

VSS178

BB30

VSS179

BB38

VSS180

BB4

VSS181

BB46

VSS182

BC14

VSS183

BC18

VSS184

BC2

VSS185

BC22

VSS186

BC26

VSS187

BC32

VSS188

BC34

VSS189

BC36

VSS190

BC40

VSS191

BC42

VSS192

BC48

VSS193

BD46

VSS194

BD5

VSS195

BE22

VSS196

BE26

VSS197

BE40

VSS198

BF10

VSS199

BF12

VSS200

BF16

VSS201

BF20

VSS202

BF22

VSS203

BF24

VSS204

BF26

VSS205

BF28

VSS206

BD3

VSS207

BF30

VSS208

BF38

VSS209

BF40

VSS210

BF8

VSS211

BG17

VSS212

BG21

VSS213

BG33

VSS214

BG44

VSS215

BG8

VSS216

BH11

VSS217

BH15

VSS218

BH17

VSS219

BH19

VSS220

H10

VSS221

BH27

VSS222

BH31

VSS223

BH33

VSS224

BH35

VSS225

BH39

VSS226

BH43

VSS227

BH7

VSS228

D3

VSS229

D12

VSS230

D16

VSS231

D18

VSS232

D22

VSS233

D24

VSS234

D26

VSS235

D30

VSS236

D32

VSS237

D34

VSS238

D38

VSS239

D42

VSS240

D8

VSS241

E18

VSS242

E26

VSS243

G18

VSS244

G20

VSS245

G26

VSS246

G28

VSS247

G36

VSS248

G48

VSS249

H12

VSS250

H18

VSS251

H22

VSS252

H24

VSS253

H26

VSS254

H30

VSS255

H32

VSS256

H34

VSS257

F3

VSS258

PANTHER-GP-NF

71.PANTH.00U

3

9 OF 10

VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS328 VSS329 VSS330 VSS331 VSS333 VSS334 VSS335 VSS337 VSS338 VSS340 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

DMB40

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, March 30, 2012

Date: Sheet of

2

Date: Sheet of

PCH (VSS)

BMW Z4 DIS

Taipei Hsien 221, Taiwan, R.O.C.

25 105

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DMB40

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, March 30, 2012

Date: Sheet of

Reserved

BMW Z4 DIS

Taipei Hsien 221, Taiwan, R.O.C.

26 105

1

A00

SSID = KBC

3D3V_AUX_KBC 3D3V_S0

R2771

R2771 2D2R3-1-U- GP

2D2R3-1-U- GP

1 2

X03 2/6

R2702

1 2

0R0603-PAD-2- GP

5

VBAT

3D3V_AUX_KBC _VCC

D D

C2704

R2713

R2703

SCD1U10V2KX-5GP

AC_IN#[40]

12

DY

TP_LOCK_LED#[68]

EC_AGND

12

C2706

C2707

SPI_SO_R[21,60]

SPI_SI_R[21,60]

SCD1U10V2KX-5GP

EC_AGND

1 2

DY

SCD1U10V2KX-5GP

AOAC_WW AN_EN#[66]

USBCHARG ER_CB0[62]

AUDIO_PRESEN T#[82]

BATT_WH ITE_LED#[68]

AOAC_WLA N_EN#[65]

C2725

SC100P50V2JN-3GP

X03 2/6

R2767

0R0402-PAD-2- GP

1 2

R2768

0R0402-PAD-2- GP

1 2

C2707

SCD1U10V2KX-5GP

C2714 SCD1U10V2KX- 5GPC2714 SCD 1U10V2KX-5GP

PSID_EC[38]

VGA_THRM[28]

FAN1_DAC[28]

AD_IA_HW[40]

IMVP_PWRGD[36,42]

3G_EN[66]

CAP_LED#[69]

S5_ENABLE[36]

BAT_IN#[39]

LID_CLOSE#[70]

RSMRST#_KBC[19]

PM_SLP_S4#[19,46]

USBCHG_EN[62] WIFI_RF_EN[65]

S0_PWR_GO OD[19,36]

33R2J-2-GP R273633R 2J-2-GP R2736 33R2J-2-GP R271933R2J-2- GP R2719

PM_PWRBT N#[19]

AC_PRESENT[19]

USB_PWR _EN#[82]

AMB_TEMP

12

3D3V_AUX_S5 3D3V_AUX_S5 3D3V_AUX_S5

C2705

SCD1U10V2KX-5GP

SPI_CS0#_R[21,60]

SPI_CLK_R[21,60]

12

C2726

1 2

AD_IA[40]

C2708

DY

SCD1U10V2KX-5GP

1 2

1 2 1 2 1 2 1 2

R2704

R2704 330KR2J-L1-GP

330KR2J-L1-GP

1 2

12

EC_AGND

R272533R2J-2-GP R 272533R2J-2-GP R272233R2J-2-GP R 272233R2J-2-GP

PSL_IN2#

PSL_IN1#

C2709

SC2D2U10V3KX-1GP

12

C2710

SCD1U10V2KX-5GP

PCB_VER_AD AMB_TEMP

MODEL_ID_DET

3G_EN ECSMI#_KBC

ECSWI#_KBC

EC_SPI_CS#_C EC_SPI_CLK_C

EC_SPI_DI_C EC_SPI_DO_C

115

U2701A

VCC119VCC246VCC376VCC488VCC5

104

VREF

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

GPIO93/AD3

108

GPIO5/AD4

96

GPIO4/AD5

95

GPIO3/AD6

94

GPIO7/AD7

101

GPIO94/DA0

105

GPIO95/DA1

106

GPIO96/DA2

107

GPIO97/DA3

79

GPIO02

6

GPIO24

109

GPIO30/F_WP#

14

GPIO34/CIRRXL

15

GPIO36

80

GPIO41/F_WP#

17

GPIO42/TCK

20

GPIO43/TMS

21

GPIO44/TDI

26

GPIO51/N2TCK

123

GPIO67/N2TMS

82

GPIO75

83

GPIO76

84

GPIO77

90

F_CS0#

92

F_SCK

86

F_SDI&F_SDIO1

87

F_SDIO&F_SDIO0

91

GPIO81/F_WP#

117

GPIO20/TA2/IOX_DIN_DIO

112

GP/I/O84/IOX_SCLK/XORTR#

110

GPO82/IOX_LDSH/TEST#

NPCE885PA0DX -1-GP

GND118GND245GND378GND489GND5

EC_GPIO47 High Active

PROCHOT _EC

12

R2732

100KR2J-1-GP

X01 12/21

R2716

PSL_OUT#

1 2

1KR2J-1-GP

12

C2701

SC2D2U10V3KX-1GP

C C

Layout Note:

Need very close to EC

AOAC Ambient temperature detect

10KR2B-GP

B B

NTC-10K-27- GP

69.60013.131

2nd = 69.60011.201

3rd = 69.60037.011

Power Switch Logic(PSL)

KBC_PWR BTN#[68]

A A

D2707

1

USBDET_CO N#[62]

3

BAT54CPT-GP

83.R2003.E81

2ND = 83.00054.Q81

KBC_ON#_GAT E_L

2

USB_DET#

X01 12/21 X01 12/13 X01 12/02

5

SCD1U10V2KX- 5GP

102

4

VDD

AVCC

GND6

5

116

X03 2/6

1 2

R2765

0R0402-PAD-2- GP

R2740

R2740 0R2J-2-GP

0R2J-2-GP

1 2

DY

Q2702

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

4

C2702

EC_VBKUP

X01 12/12

75

114

VSBY

VBKUP

LRESET#/GPIOF7

LCLK/GPIOF5

LFRAME#/GPIOF6

LAD3/GPIOF4 LAD2/GPIOF3 LAD1/GPIOF2 LAD0/GPIOF1

SERIRQ/GPIOF0

GPIO11/CLKRUN#

GPIO65/SMI#

ECSCI#/GPIO54

GPIO10/LPCPD#

GPIO85/GA20

KBRST#/GPIO86

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

GPIO27/PSDAT2 GPIO26/PSCLK2 GPIO35/PSDAT1 GPIO37/PSCLK1

GPIO17/SCL1/N2TCK

GPIO22/SDA1/N2TMS

GPIO73/SCL2

GPIO74/SDA2

GPIO23/SCL3

GPIO31/SDA3

GPIO47/SCL4

GPIO53/SDA4

PSL_OUT_GPIO71#

PSL_IN2_GPI06# PSL_IN1_GPI70#

AGND

103

EC_AGND

H_PROCHO T#_EC

D

R2734

R2734 330KR2J-L1-GP

330KR2J-L1-GP

X01 12/13

1 2

R2735

R2735 20KR2J-L2-GP

20KR2J-L2-GP

4

A00 3/15 X03 2/16 X01 12/02

12

C2703

DY

SC2D2U10V3KX- 1GP

3D3V_AUX_S5

X03 2/6

1 2

RTC_AUX_S5

R2794

0R0402-PAD-2- GP

1 0F 2

PLT_RST#_EC

7 2 3

LPC_AD3

1

LPC_AD2

128

LPC_AD1

127

LPC_AD0

126 125 8 9

ECSCI#_KBC

29 124 121 122

27

AD_IA_HW2

25 11 10 71 72

70 69 67 68 119 120

PROCHOT _EC

24 28

1 2

PSL_OUT#

74

PSL_IN2#

93

PSL_IN1#

73

KBC_VCORF

44

VCORF

Layout Note:

Connect GND and AGND planes via either 0R resistor or connect directly.

X03 2/6

R2733

0R0402-PAD-2- GP

1 2

C2722

C2722 SCD1U10V2KX- 5GP

SCD1U10V2KX- 5GP

1 2

KBC_ON#_GAT EKBC_ON#_GAT E_L

Q2703

Q2703 DMP2130L-7-GP

DMP2130L-7-GP

84.02130.031

2ND = 84.03413.A31

PCB_VER_AD

C2717

SCD1U10V2KX- 5GP

CLK_PCI_KBC [18]

LPC_FRAME# [ 21,71]

INT_SERIRQ [21] PM_CLKRUN #_EC [1 9]

L_BKLT_EN [17] MOBILITY_CENTER# [82]

H_A20GATE [22] H_RCIN# [22]

BLON_OUT [49]

AD_IA_HW2 [40] PWR_CH G_AD_OFF [3 8] INSTANT_LAUN CH# [82] TPDATA [69] TPCLK [69]

BAT_SCL [39,40]

BAT_SDA [39,40]

SML1_CLK [20,28,85]

SML1_DATA [20,28,85]

PM_LAN_ENABLE [31]

RTCRST_O N [21]

R2792

0R0402-PAD-2- GP

LCD_TST_EN [49] LCD_TST [49]

12

C2712

SC1U25V3KX-1- GP

Layout Note:

Need very close to EC

H_PROCHO T# [5,40]

12

C2713

C2713 SC47P50V2JN-3G P

SC47P50V2JN-3G P

S

G

D

Q2704

G

D

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

VBAT VB AT

12

DY

1 2

EC_AGND

C2711

C2711 SC220P50V2KX-3GP

SC220P50V2KX-3GP

1 2

DY

X03 2/6

R2778 0R 0402-PAD-2-G PR2778 0R 0402-PAD-2-G P

1 2

X03 2/6

R2791

DY

0R2J-2-GP

1 2

3D3V_AUX_KBC

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

R2724

R2724 64K9R2F-1-GP

64K9R2F-1-GP

R2726

R2726 100KR2F-L1-GP

100KR2F-L1-GP

X01 X02 X03

A00

Reserved

100.0KX00

100.0K

100.0K 1.358V

Reserved 100.0K 215.0K 1.048V

PLT_RST# [5,18,31,65 ,66,71]

LPC_AD[3..0] [21,71]

TP

Charger PCH

3D3V_AUX_S5

12

R2705

R2705 10KR2J-3-GP

10KR2J-3-GP

3D3V_AUX_KBC

12

R2709

R2709 10KR2J-3-GP

10KR2J-3-GP

S5_ENABLE

PURE_HW _SHUTDO WN#[28,36,85]

Q2701

MMBT3906-4-GP

84.T3906.A11

2nd = 84.03906.F11

10.0K

20.0K

33.0K

47.0K

64.9K

76.8

100.0K

143.0K

174.0KReserved 100.0K

VCCP_CPU

B

E

C

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.65VReserved

1.204V

FAN_TACH 1[28] PCIE_WAKE#[31] PM_SLP_S3#[19,36,37,47]

PWRLED #[68]

KBC_BEEP[82]

INSTANT_LAUN CH#_LED#[82]

AC_IN_KBC#[38]

AUDIO_PRESEN T#_LED#[ 82]

PCH_WA KE#_EC[19]

MOBILITY_CENTER#_LED #[82]

CHG_AMBER_L ED#[68]

ME_UNLOCK[21]

AOAC_PCIE_W AKE#[65,66]

E51_TxD[65]

PCH_SUSCL K_KBC[19]

AMP_MUTE#[82]

H_PECI[5,22]

Layout Note:

Need very close to EC

ECRST#

C2715

12

DY

SC1U6D3V2KX-GP

BAT_SCL BAT_SDA

ECRST#

X01 12/20 X01 12/09

AC_IN_KBC# BAT_IN#

FAN_TACH 1

3G_EN

LID_CLOSE#

VGA_THRM

0R0402-PAD-2- GP

X03 2/6

3

2

12

MODEL_ID_DET

12

C2718

DY

SCD1U10V2KX- 5GP

R2720

R2721

R2721 43R2J-GP

43R2J-GP

1 2 1 2

ECRST#

1 2

PECI EC_VTT

EC_AGND

12

For System Reset.

X01 12/02

3D3V_AUX_KBC

RN2701

23 1

4

SRN4K7J-8-G P

R2707 1 0KR2J-3-GPR2707 10KR 2J-3-GP

1 2

DY

1 2

DY

1 2

12

DY

3D3V_AUX_KBC

3D3V_S0

R2714 1 00KR2J-1-GP

R2714 1 00KR2J-1-GP R2715 1 00KR2J-1-GPR2715 100KR2J-1-G P

R2708 10KR 2J-3-GPR2708 10KR2J- 3-GP

R2712 1 0KR2J-3-GP

R2799 100KR2J-1-GPR2799 100KR2J-1-GP

C2720 SCD1U 10V2KX-5GP

2

MODEL_ID_DET(GPIO07)

R2710

R2710 10KR2F-2-GP

10KR2F-2-GP

R2739

R2739 100KR2F-L1-GP

100KR2F-L1-GP

U2701B

31

GPIO56/TA1

63

GPIO14/TB1

64

GPIO1/TB2

32

GPIO15/A_PWM

118

GPIO21/B_PWM

62

GPIO13/C_PWM

65

GPIO32/D_PWM

22

GPIO45/E_PWM

81

GPIO66/G_PWM

66

GPIO33/H_PWM

16

GPIO40/F_PWM

23

GPIO46/CIRRXM/TRIST#

113

GPIO87/CIRRXM/SIN_CR

111

GP/I/O83/SOUT_CR/TRIST#

77

GPIO0/EXTCLK

30

GPIO55/CLKOUT/IOX_DIN_DIO

85

VCC_POR#

13

PECI

12

VTT

NPCE885PA0DX -1-GP

C2716

SCD1U10V2KX-5GP

43

56

RSTSW1

RSTSW1 SW-TAC T-130-GP-U

SW-TAC T-130-GP-U

1 2

62.40009.731

2nd = 62.40089.441

X01 12/09

3D3V_S5

EC_AGND

PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

TBD TBD TBD TBD 2.702V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

KBSOUT0/GPOB0/JENK#

KBSOUT1/GPIOB1/TCK KBSOUT2/GPIOB2/TMS

KBSOUT4/GPOB4/JEN0#

KBSOUT5/GPIOB5/TDO

KBSOUT6/GPIOB6/RDY#

KBSOUT9/GPOC1/SDP_VIS# KBSOUT10&P80_CLK/GPIOC2 KBSOUT11&P80_DAT/GPIOC3

KBSOUT15/GPIO61/XOR_OUT

KBSIN0/GPIOA0/N2TCK

KBSIN1/GPIOA1/N2TMS

PM_CLKRUN #_EC

H_A20GATE

3D3V_WLAN _AOAC

R2706

100KR2J-1-GP

3D3V_LAN_S5

R2711

100KR2J-1-GP

PCIE_WAKE#

100.0K 3.0V

100.0K

2 0F 2

KBSOUT3/GPIOB3/TDI

KBSOUT7/GPIOB7 KBSOUT8/GPIOC0

KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62

GPIO60/KBSOUT16 GPIO57/KBSOUT17

KBSIN2/GPIOA2 KBSIN3/GPIOA3 KBSIN4/GPIOA4 KBSIN5/GPIOA5 KBSIN6/GPIOA6 KBSIN7/GPIOA7

EC_SCI#[22] EC_SMI#[22] EC_SWI#[20]

R2730 0R2J-2-GP

R2731 0R2J-2-GP

USB_DET# MOBILITY_CENTER# INSTANT_LAUN CH# AUDIO_PRESEN T#

1 2

DY

R2701

100KR2J-1-GP

1 2

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Tuesday, April 03, 2012

Date: Sheet of

10.0K(64.10025.6DL)

13.7K(64.13725.6DL)

17.8K(64.17825.6DL)

22.1K(64.22125.6DL)

27.0K(64.27025.6DL)

32.4K(64.32425.6DL)

37.4K(64.37425.6DL)

43.2K(64.43225.6DL)

57.6K(64.57625.6DL)

64.9K(64.64925.6DL)

73.2K(64.73225.6DL) 1.905V

82.5K(64.82525.6DL) 1.808V

93.1K(64.93125.6DL) 107K(64.10735.6DL) 120K(64.12035.6DL) 137K(64.13735.6DL) 154K(64.15435.6DL) 200K(64.20035.6DL) 1.099V 232K(64.23236.6DL)

KCOL0

53

KCOL1

52

KCOL2

51

KCOL3

50

KCOL4

49

KCOL5

48

KCOL6

47

KCOL7

43

KCOL8

42

KCOL9

41

KCOL10

40

KCOL11

39

KCOL12

38

KCOL13

37

KCOL14

36

KCOL15

35

KCOL16

34

USB_DET#

33

KROW0

54

KROW1

55

KROW2

56

KROW3

57

KROW4

58

KROW5

59

KROW6

60

KROW7

61

X03 2/6

R2764 0R0402-PAD-2-GPR2764 0R0402-PAD-2-GP

1 2

R2723 0R0402-PAD-2-GPR2723 0R0402-PAD-2-GP

1 2

R2727 0R0402-PAD-2-GPR2727 0R0402-PAD-2-GP

1 2

AOAC_PCIE_W AKE#_RAOAC_PCIE_W AKE#

12

DY

X01 12/02

RN2702

1 2 3 4 5

SRN100KJ-5-G P

D2702

3

CH715FPT-G P

83.R0304.B81

2nd = 83.00040.E81

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

KBC Nuvoton NPCE885

BMW Z4 DIS

KCOL[0..16] [69]

KROW[0..7] [69]

BOOST_MODE# [40]

DGPU_PW ROK [22,86,92,93]

3D3V_AUX_KBCVBAT

8 7 6

3D3V_WLAN _AOAC

2

3D3V_WW AN_AOAC

DY

1

27 105

1

2.902V

2.801V

2.598V

2.492V

2.402V

2.304V

2.201V49.9K(64.49925.6DL)

2.093V

2.001V

1.709V

1.594V

1.499V

1.392V

1.299V

0.994V

ECSCI#_KBC

ECSMI#_KBC ECSWI#_KBC

A00

5

4

3

2

1

SSID = Thermal

3D3V_S0

D D

12

C2813

C2814

SCD1U10V2KX-5GP

SC10U6D3V3MX-GP

84.03904.L06

2ND = 84.03904.P11

3

1

Q2803

PMBS3904-1-GP

2

NCT7718_DXP

12

C2816

C2816 SC470P50V3JN-2GP

SC470P50V3JN-2GP

DY

NCT7718_DXN

12

C2812

C2812 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

2.System Sensor, Put on palm rest

C C

THERM_SYS_SHDN#

X03 2/13

1 2

R2813 0R0402-PAD-2-GPR2813 0R0402-PAD-2-GP

Layout Note:

C2812 close U2801

Layout Note:

Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

T_CRIT#

1 2 3

ALERT# T_CRIT#

U2801

NCT7718W-GP

74.07718.0B9

SML1_DATA[20,27,85]

SML1_CLK[20,27,85]

VDD D+ D-

ALERT#

T_CRIT#4GND

R2815 18K7R2F-GPR2815 18K7R2F-GP R2814 2KR2F-3-GPR2814 2KR2F-3-GP

SCL SDA

1 2 1 2

8 7 6 5

3D3V_S0

ALERT#

RN2801

2 3 1

SRN2K2J-1-GP

6 5

Q2804

Q2804 2N7002KDW-GP

2N7002KDW-GP

3D3V_S0

4

1 2 34

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

THM_SML1_DATA

THM_SML1_CLK

FAN1_DAC[27]

Layout Note:

Need 10 mil trace width.

Fan controller

R2802

0R2J-2-GP

1 2

DY

5V_S0

FAN_VCC

FON#

U2802

1

FON#

2

VIN

3

VO

4

VSET

G991P11U-GP

74.00991.031

2nd = 74.02793.A31

3rd = 74.05606.A71

GND GND GND GND

5V_S0

8 7 6 5

12

C2803

12

C2804

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

X03 2/6

DY

THM_SML1_CLK THM_SML1_DATA

12

DY

C2815

C2808

SCD1U10V2KX-5GP

Layout Note:

Signal Routing Guideline: Trace width = 15mil

FAN_TACH1[27]

C2809

SC4D7U6D3V3KX-GP

R2807

0R0402-PAD-2-GP

1 2

21

12

DY

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

DY

D2802

CH551H-30PT-GP

FAN_TACH1_C

FAN_VCC

C2810

12

SC2200P50V2KX-2GP

DY

1

2

3

2nd = 20.F1841.003

FAN_TACH1_C FAN_VCC

FAN1

4

5

ACES-CON3-11-GP

20.F0772.003

AFTP2801AFTP2801

1

AFTP2802AFTP2802

1

3D3V_S0

GPU thermal sensor

B B

P2800_VGA_DXP[85]

P2800_VGA_DXN[85]

X01 12/02

SCD1U10V2KX-5GP

12

C2818

C2818 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

DY

Layout Note:

Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

C2817

DY

12

U2803

5

VCC

6

DXP

7

DXN

8

OTZ

DY

P2800EB0-GP

74.02800.B71

TDR

TDL

GND

ADJ

4 3 2 1

MISC_THRM

VGA_THRM [27]

1

TP2803 TPAD14-OP-GPTP2803 TPAD14-OP-GP

VGA_THRM

12

R2837

R2837 402KR2F-GP

402KR2F-GP

DY

EMI

FAN_VCC

12

EC2801

DY

SCD1U16V2KX-3GP

Thermal Sensor

Q2802

DY

Q2802

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

S

G

THERM_SYS_SHDN#

3D3V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Thermal NCT7718W/Fan Controllor P2793

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, March 30, 2012

Date: Sheet of

2

Date: Sheet of

BMW Z4 DIS

Taipei Hsien 221, Taiwan, R.O.C.

28 105

1

A00

A A

ADJ

Pull low

Floating

5

Temp.(C)

95Pull high

90

85

PURE_HW _SHUTDOWN#[27,36,85]

12

C2811

SCD1U10V2KX-5GP

4

3

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DMB40

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

BMW Z4 DIS

29 105Friday, March 30, 2012

1

A00

5

D D

4

3

2

1

(Blanking)

C C

B B

A A

5

4

3

2

DMB40

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

BMW Z4 DIS

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

30 105Friday, March 30, 2012

A00

Dell Inspiron 14z-5423 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual