Dell 3421 Schematics

5

D D

4

3

2

1

Essentials Oak 14 Schematic

Chief River

C C

2012-09-05

REV : A00

B B

A A

DY : None Installed UMA: UMA only installed OPS: DISCRTE OPTIMUS installed

5

4

3

2

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

OAK14 Chief River DIS

Wednesd ay, September 05, 20 12

Date: Sheet of

Cover Page

Taipei Hsien 221, Taiwan, R.O.C.

1 105

1

A00

5

Project code: 91.4WT01.001

91.4XP01.001 PCB P/N : 12204 Revision: A00

D

VRAM(DDR3) *8

128Mx16bx4(1GB) 256Mx16bx4(2GB) 128Mx16bx8(2GB)

88,89,90,91

Switchable Graphic only

C

MIC_IN/GND

B

A

58

Combo Jack

5

HP_R/L

58

Thermal

NUVOTON NCT7718W

28

Fan Control

NUVOTON NCT3940S-A

FAN

28

DDR3

2CH SPEAKER (2CH 2W/4ohm)

SMBUS

28

HDMI V1.4a

14.0" LCD (16:9)

Camera

Digital MIC

HDA CODEC

Realtek ALC3221

LPC debug port

KBC

NUVOTON

NPCE885P

Int.

69

KB

4

Nvidia

N13P - GS - OP N13M- GSR

25W

83,84,85,86,87

51

49

29

71

Touch PAD

Profile/Image sensor

4

HDMI

LVDS (2channel)

USB2.0 x 1

HDA

LPC BUS

27

PS2

69

3

Oak14 Block Diagram

Intel CPU

Ivy Bridge

PCIe x 8

17W (DC)

BGA1023

4,5,6,7,8,9,10

Intel PCH

Panther Point

BGA989

HM76

12 USB 2.0/1.1 ports

4 USB 3.0 ports

High Definition Audio

6 SATA ports

8 PCIE ports

LPC I/F

ACPI 4.0a

17,18,19,20,21,22,23,24,25

SPI

Flash ROM

8MB

60

SMBUS

www.schematic-x.blogspot.com

3

DDR3 1333/1600M Hz Channel A

DDR3 1333/1600M Hz Channel B

DMIx4FDIx4x2

PCIE x 1

USB2.0 x 1

USB3.0 x 2

USB2.0 x 2

USB2.0 x 1

SATA(Gen3) x 1

SATA(Gen1) x 1

2

10/100 NIC

Realtek RTL8105E-VD

Mini-Card

802.11 b/g/n BT V4.0 combo

Left side

USB3.0 Port x 2

61,62,63

Right side

USB2.0 Port x 1

CardReader

Realtek RTS5170

32

HDD

56

ODD

56

2

31

65

USB Board

SD/SDHC/MS/MS Pro Slot

1

CHARGER

BQ24727

DDR3 1333/1600

SODIMM A

DDR3 1333/1600

SODIMM B

RJ45 Conn.

INPUTS

AD+

BT+

SYSTEM DC/DC

TPS51225

INPUTS

DCBATOUT

CPU Core/NB Power

ISL95833

14

15

INPUTS

DCBATOUT

DDR3 SUS

TPS51216

INPUTS

DCBATOUT

DDR3 VTT

TPS51216

INPUTS

DCBATOUT

CPU VCCP_CPU

TPS51219

DCBATOUT

59

Intel PCH 1D8V_S0

SYW231

INPUTS

3D3V_S5

Intel CPU_VCCSA

TPS51463

INPUTS

5V_S5

Nvidia VGA_CORE

ADP3211MNR2G

INPUTS

DCBATOUT

OUTPUTS

DCBATOUT

OUTPUTS

3D3V_AUX_S5 5V_AUX_S5 5V_S5 3D3V_S5

OUTPUTS

VCC_CORE VCC_GFXCORE

OUTPUTS

1D5V_S3

OUTPUTS

0D75V_S0

OUTPUTSINPUTS

1D05V_S0

OUTPUTS

1D8V_S0

OUTPUTS

0D85V_S0

OUTPUTS

VGA_CORE

Switches

2 105Wednesday, September 05, 2012

OUTPUTS

3D3V_S03D3V_S5

1D05V_VGA_S0VCCP_CPU

L4:Signal L5:GND L6:Bottom

of

INPUTS

1D5V_S3 1D5V_S0

5V_S5 5V_S0

3D3V_S0 3D3V_VGA_S0

1D5V_S3 1D5V_VGA_S0

74

M14 DIS

Title

Size Document Number Rev

C

Date: Sheet

Block Diagram

OAK14 Chief River DIS

PCB LAYER

L1:Top L2:VCC L3:Signal

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

1

42~44

33

26

36 93

A00

40

41

D

46

45

C

47

48

92

B

A

PCH Strapping

Name Schematics Notes

The signal has a weak internal pull-down.

SPKR

INIT3_3V#

4 4

INTVRMEN

GNT3#/GPIO55 GNT2#/GPIO53 GNT1#/GPIO51

DF_TVS

SATA1GP/ GPIO19

3 3

SATA2GP/ GPIO36

SATA3GP/ GPIO37

HDA_DOCK_EN# /GPIO33

HDA_SDO

HDA_SYNC

2 2

GPIO15

L_DDC_DATA

SDVO_CTRLDATA

DDPC_CTRLDATA

DDPD_CTRLDATA

1 1

GPIO28

GPIO29/ SLP_LAN#

Note: the internal pull-down is disabled after PLTRST# deasserts. If the signal is sampled high, this indicates that the system is strapped to the “No Reboot” mode (Panther Point will disable the TCO Timer system reboot feature).

This signal has a weak internal pull-up. Note: The internal pull-up is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled low. Leave as "No Connect".

Integrated 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when high NOTE: This signal should always be pulled high External 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when Low. NOTE: This signal should be pulled down to GND through 330 kOhms resistor

GNT[3:0]# functionality is not available on Mobile. Used as GPIO only. Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail.

This signal is a strap for selecting DMI and FDI termination voltage. For Ivy Bridge processor only implementation: DF_TVS needs to be pulled up to VccDFTERM power rail through 2.2 kOhms ±5% resistor. For future processor compatibility: It needs to be connected to PROC_SELECT through a

1.0 kOhms ±5% series resistor. The PROC_SELECT signal would need a 2.2 kOhms ±5% pull-up resistor to PCH VccDFTERM.

Bit11 Bit 10 Boot BIOS Destination 0 1 Reserved 1 0 PCI 1 1 SPI 0 0 LPC NOTE: If option 00 LPC is selected BIOS may still be placed on LPC, but all platforms with Panther Point require SPI flash connected directly to the Panther Point's SPI bus with a valid descriptor in order to boot. NOTE: Booting to PCI is intended for debut/testing only. Boot BIOS Destination Select to LPC/PCI by functional strap or via Boot BIOS Destination Bit will not affect SPI accesses initiated by Management Engine or Integrated GbE LAN. NOTE: PCI Boot BIOS destination is not supported on mobile.

Reserved. This signal has a weak internal pull-down. NOTE: The internal pull-down is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled high when strap is sampled.

Reserved This signal has a weak internal pull-down. NOTE: The internal pull-down is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled high when strap is sampled.

High Definition Audio Dock Enable: This signal controls the external Intel HD Audio docking isolation logic. This is an active-low-signal. When deasserted the external docking switch is in isolate mode. When asserted the external docking switch electrically connects the IntelR HD Audio dock signals to the corresponding Panther Point signals. This signal can instead be used as GPIO33.

Signal has a weak internal pull-down. If strap is sampled low, the security measures defined in the Flash Descriptor will be in effect (default).If sampled high, the Flash Descriptor Security will be overridden. This strap should only be asserted high via external pull-up in manufacturing/debug environments ONLY. Note: The weak internal pull-down is disabled after PLTRST# deasserts. Asserting the HDA_SDO high on the rising edge of PWROK will also halt Intel Management Engine after chipset bring up and disable runtime Intel Management Engine features. This is a debug mode and must not be asserted after manufacturing/ debug.This signal has a 20k internal pull down resistor. This signal has a weak internal pull-down. On Die PLL VR is supplied by 1.5 V from VCCVRM when sampled high, 1.8 V from VCCVRM when sampled low. Needs to be pulled High for Chief River platform. Note: HDA_SYNC signal also serves as a strap for selecting VRM voltage to the PCH. The strap is sampled on the rising edge of RSMRST# signal. Due to potential leakage on the codec (path to GND), the strap may not be able to achieve the Vihmin at PCH input.Therefore, platform may need to isolate this signal from the codec during the strap phase. Refer to the example circuits provided in the latest Chief River platform design guide. TLS Confidentiality Low (0) – Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality This signal has a weak internal pull-down. NOTE:The weak internal pull-down is disabled after RSMRST# deasserts. NOTE: A strong pull-up may be needed for GPIO functionality

LVDS Detected. When '1'- LVDS is detected; When '0'- LVDS is not detected. This signal has a weak internal pull-down. NOTE:The internal pull-down is disabled after PLTRST# deasserts.

Port B Detected When '1'- Port B is detected; When '0'- Port B is not detected This signal has a weak internal pull-down. NOTE:The internal pull-down is disabled after PLTRST# deasserts.

Port C Detected. When '1'- Port C is detected; When '0'- Port C is not detected This signal has a weak internal pull-down. NOTE:The internal pull-down is disabled after PLTRST# deasserts.

Port D Detected. When '1'- Port D is detected; When '0'- Port D is not detected This signal has a weak internal pull-down. NOTE:The internal pull-down is disabled after PLTRST# deasserts.

The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL Voltage Regulator is disabled.If not used, 8.2-kΩ to 10-kΩ pull-up to +V3.3A power-rail. GPIO28 signal also needs to be pulled up to 3.3V_SUS with 4.7K resistor to ensure proper strap setting when use as the chipset test interface.Refer to the latest platform debug design guide and platform design guide for more details. NOTE:This signal has a weak internal pull-up. The internal pull-up is disabled after RSMRST# deasserts.

GPIO29 is multiplexed with SLP_LAN#. If Intel LAN is implemented on the platform, SLP_LAN# must be used to control the power to the PHY LAN (no other implementation is supported). If integrated Intel LAN is not supported on the platform, GPIO29 can be used as a normal GPIO. A soft strap determines the functionality of GPIO29, either as SLP_LAN# or GPIO. By default, the soft strap enables SLP_LAN# functionality on the pin. If the soft trap is changed to enable GPIO functionality, then SLP_LAN# functionality is no longer available, and the signal can be used as a normal GPIO (default to GPI).

Chief River Schematic Checklist Revision 1.5

A

B

Processor Strapping

Pin Name Strap Description

CFG[0] Connect a series 1 kOhms resistor on the critical CFG[0]

CFG[2] PCIe Static x16 Lane

Numbering Reversal.

CFG[4]

Display Port Presence strap

PCIE Port Bifurcation

CFG[6:5]

Straps

Reserved configuration

CFG[17:7]

lands. A test point may be placed on the board for these lands.

Sandy Bridge + Ivy Bridge Compatibility Requirements

Pin Name Configuration Schematic Notes

DDR3 VREF

PROC_SELECT# & DF_TVS

VCCIO VR Implementation

VCCSA_SEL connection to VCCSA_VID[1:0] lines

Layout Requirement on PCI Express Gen3

GT Core VR Implementation

Processor PCI Express Graphics Guidelines

Sandy Bridge + Ivy Bridge

Ivy Bridge

Sandy Bridge + Ivy Bridge

Ivy Bridge No change.

Sandy Bridge + Ivy Bridge

Ivy Bridge No change.

Sandy Bridge + Ivy Bridge

Ivy Bridge No change.

Sandy Bridge + Ivy Bridge

Ivy Bridge No change.

Sandy Bridge + Ivy Bridge

Ivy Bridge No change.

Sandy Bridge + Ivy Bridge (PCIe Gen3):

B

C

Chief River Schematic Checklist Revision 1.5

Configuration (Default value f or each bit is 1 unless specified otherwise)

trace in a manner which does not introduce any stubs to CFG[0] trace. Route as needed from the opposite side of this series isolation resistor to the debug port. ITP will drive the net to GND.

1: Normal Operation; Lane # definition matches socket pin map definition 0:Lane Reversed

1:Disabled - No Physical Display Port attached to Embedded DisplayPort No connect for disable 0:Enabled - An external Display Port device is connected to the Embedded Display Port Pull-down to GND through a 1KΩ ± 5% resistor to enable port

00 = 1 x 8, 2 x 4 PCI Express 01 = reserved 10 = 2 x 8 PCI Express 11 = 1 x 16 PCI Express

Chief River Schematic Checklist Revision 1.5

DDR3 VREF M1 and M3 Guidelines are required. Note: The M3 traces are routed to the Sandy Bridge Processor reserved pins.

No change.

Connect DF_TVS signal of the PCH to PROC_SELECT# of the processor through a 1K±5% series resistor. PROC_SELECT# also needs a 2.2K±5% pull up resistor to PCH VccDFTERM rail.

The POR for Ivy Bridge mobile parts is now 1.05 V. There is no longer a requirement for a separate VCCIO VR for Sandy Bridge + Ivy Bridge compatibility.

VCCSA_SELECT[0:1] which should be connected to VID[1:0] of the System Agent (SA) VR controller.

The total motherboard length for a pair of consecutive PCI Express Tx lanes be length matched within 100 mils (2.54 mm)

Depending on the PDDG specifications, some IVB GT2 SKUs may require a new VR controller and 2 phase VCC GT core VR.

To support Gen 3 PCI Express Graphic, the value of the AC coupling capacitor should be 180 - 265 nF.

No change.Ivy Bridge

C

Default Value

1

D

Power Plane

VOLTAGE DESCRIPTION

POWER PLANE

5V_S0

5V

3D3V_S0

3.3V

1D8V_S0

1.8V

1D5V_S0

1.5V

1D05V_VTT

1.05V

0D85V_S0

0.95 - 0.85V

0D75V_S0

0.75V

VCC_CORE

0.35V to 1.5V

VCC_GFXCORE

0.4 to 1.25V

1D8V_VGA_S0

1.8V

3D3V_VGA_S0

3.3V

1V_VGA_S0

1V

5V

5V_USBX_S3

1.5V

1D5V_S3

0.75V

DDR_VREF_S3

BT+

6V-14.1V

DCBATOUT

6V-14.1V

5V_S5

5V

5V_AUX_S5

5V

3D3V_S5

3.3V

3D3V_AUX_S5

3.3V

3.3V3D3V_LAN_S5

3.3V

3D3V_AUX_KBC

3D3V_AUX_S5

3.3V

PCIE Routing

LANE1 X

X

LANE2

LANE3xMini Card1(WLAN)

LANE4

LANE5

X

Onboard LAN

LANE6

LANE7

X

LANE8 X

SATA Table

Pair

SATA

Device

HDD1

0

X

1

X

2

X

3

ODD1

4

X

5

E

Voltage Rails

ACTIVE IN

S0

S3

All S states

WOL_EN

DSW, Sx ON for supporting Deep Sleep states

G3, Sx

CPU Core Rail Graphics Core Rail

AC Brick Mode only

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

USB Table

Pair

0

1

2

3

4

5

6

7

8

9

10

11

12

13

M14 DIS

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

OAK14 Chief River DIS

Wednesd ay, September 05, 2012

Date: Sheet of

Device

USB3.0 port1

USB3.0 port2, with Debug Port

USB2.0 port3

X

Touch Panel

HM76 NC

X

CARD READER

Mini Card (WLAN)

X

CAMERA

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Table of Content

E

3 105

A00

5

4

3

2

1

SSID = CPU

Layout Note:

Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.

D D

1 OF 9

CPU1A

DMI_CPU_R XN_PCH_TXN[3:0]19

Layout Note:

DMI trace length 2000~8000mil

C C

Layout Note:

FDI trace length 2000~6500mil

B B

Layout Note:

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

DMI_CPU_R XP_PCH_TXP[3:0]19

DMI_CPU_T XN_PCH_RXN[3:0]19

DMI_CPU_T XP_PCH_RXP[3:0]19

FDI_CPU_T XN_PCH_RXN[7:0]19

FDI_CPU_T XP_PCH_RXP[7:0]19

VCCP_CP U

FDI_FSYNC019 FDI_FSYNC119

FDI_INT19

FDI_LSYNC019 FDI_LSYNC119

R402 24D 9R2F-L-GPR402 24D 9R2F-L-GP

1 2

DMI_CPU_R XN_PCH_TXN0 DMI_CPU_R XN_PCH_TXN1 DMI_CPU_R XN_PCH_TXN2 DMI_CPU_R XN_PCH_TXN3

DMI_CPU_R XP_PCH_TXP0 DMI_CPU_R XP_PCH_TXP1 DMI_CPU_R XP_PCH_TXP2 DMI_CPU_R XP_PCH_TXP3

DMI_CPU_T XN_PCH_RXN0 DMI_CPU_T XN_PCH_RXN1 DMI_CPU_T XN_PCH_RXN2 DMI_CPU_T XN_PCH_RXN3

DMI_CPU_T XP_PCH_RXP0 DMI_CPU_T XP_PCH_RXP1 DMI_CPU_T XP_PCH_RXP2 DMI_CPU_T XP_PCH_RXP3

FDI_CPU_T XN_PCH_RXN0 FDI_CPU_T XN_PCH_RXN1 FDI_CPU_T XN_PCH_RXN2 FDI_CPU_T XN_PCH_RXN3 FDI_CPU_T XN_PCH_RXN4 FDI_CPU_T XN_PCH_RXN5 FDI_CPU_T XN_PCH_RXN6 FDI_CPU_T XN_PCH_RXN7

FDI_CPU_T XP_PCH_RXP0 FDI_CPU_T XP_PCH_RXP1 FDI_CPU_T XP_PCH_RXP2 FDI_CPU_T XP_PCH_RXP3 FDI_CPU_T XP_PCH_RXP4 FDI_CPU_T XP_PCH_RXP5 FDI_CPU_T XP_PCH_RXP6 FDI_CPU_T XP_PCH_RXP7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT

FDI_LSYNC0 FDI_LSYNC1

DP_COMP

M2

DMI_RX#0

P6

DMI_RX#1

P1

DMI_RX#2

P10

DMI_RX#3

N3

DMI_RX0

P7

DMI_RX1

P3

DMI_RX2

P11

DMI_RX3

K1

DMI_TX#0

M8

DMI_TX#1

N4

DMI_TX#2

R2

DMI_TX#3

K3

DMI_TX0

M7

DMI_TX1

P4

DMI_TX2

T3

DMI_TX3

U7

FDI0_TX#0

W11

FDI0_TX#1

W1

FDI0_TX#2

AA6

FDI0_TX#3

W6

FDI1_TX#0

V4

FDI1_TX#1

Y2

FDI1_TX#2

AC9

FDI1_TX#3

U6

FDI0_TX0

W10

FDI0_TX1

W3

FDI0_TX2

AA7

FDI0_TX3

W7

FDI1_TX0

T4

FDI1_TX1

AA3

FDI1_TX2

AC8

FDI1_TX3

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

EDP_COMPIO

AD2

EDP_ICOMPO

AG11

EDP_HPD#

AG4

EDP_AUX#

AF4

EDP_AUX

AC3

EDP_TX#0

AC4

EDP_TX#1

AE11

EDP_TX#2

AE7

EDP_TX#3

AC1

EDP_TX0

AA4

EDP_TX1

AE10

EDP_TX2

AE6

EDP_TX3

IVY-BRIDGE-GP-NF

71.00IVY.A0U

DMI

Intel(R) FDI

eDP

1 OF 9

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8

PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PCI EXPRESS -- GRAPHICS

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

PEG_IRCOM P_R

G3 G1 G4

H22 J21 B22 D21 A19 D17 B14 D13

CPU_RXN _C_dGPU_TXN7

A11

CPU_RXN _C_dGPU_TXN6

B10

CPU_RXN _C_dGPU_TXN5

G8

CPU_RXN _C_dGPU_TXN4

A8

CPU_RXN _C_dGPU_TXN3

B6

CPU_RXN _C_dGPU_TXN2

H8

CPU_RXN _C_dGPU_TXN1

E5

CPU_RXN _C_dGPU_TXN0

K7

K22 K19 C21 D19 C19 D16 C13 D12

CPU_RXP _C_dGPU_TXP7

C11

CPU_RXP _C_dGPU_TXP6

C9

CPU_RXP _C_dGPU_TXP5

F8

CPU_RXP _C_dGPU_TXP4

C8

CPU_RXP _C_dGPU_TXP3

C5

CPU_RXP _C_dGPU_TXP2

H6

CPU_RXP _C_dGPU_TXP1

F6

CPU_RXP _C_dGPU_TXP0

K6

G22 C23 D23 F21 H19 C17 K15 F17

CPU_TXN _dGPU_RXN7

F14

CPU_TXN _dGPU_RXN6

A15

CPU_TXN _dGPU_RXN5

J14

CPU_TXN _dGPU_RXN4

H13

CPU_TXN _dGPU_RXN3

M10

CPU_TXN _dGPU_RXN2

F10

CPU_TXN _dGPU_RXN1

D9

CPU_TXN _dGPU_RXN0

J4

F22 A23 D24 E21 G19 B18 K17 G17

CPU_TXP _dGPU_RXP7

E14

CPU_TXP _dGPU_RXP6

C15

CPU_TXP _dGPU_RXP5

K13

CPU_TXP _dGPU_RXP4

G13

CPU_TXP _dGPU_RXP3

K10

CPU_TXP _dGPU_RXP2

G10

CPU_TXP _dGPU_RXP1

D8

CPU_TXP _dGPU_RXP0

K4

Note: PEG with reversal type.

R401 24D9R2F -L-GPR401 24D9R2F -L-GP

PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

VCCP_CP U

1 2

CPU_RXN _C_dGPU_TXN[7 ..0] 83

CPU_RXP _C_dGPU_TXP[7 ..0] 83

dGPU_RX N_C_CPU_TXN[8 ..15] 83

dGPU_RX P_C_CPU_TXP[8 ..15] 83

OPS

C401 SCD 22U10V2KX-1GP

1 2

OPS

C402 SCD 22U10V2KX-1GP

1 2

OPS

C403 SCD 22U10V2KX-1GP

1 2

OPS

C404 SCD 22U10V2KX-1GP

1 2

OPS

C405 SCD 22U10V2KX-1GP

1 2

OPS

C406 SCD 22U10V2KX-1GP

1 2

OPS

C407 SCD 22U10V2KX-1GP

1 2

OPS

C408 SCD 22U10V2KX-1GP

1 2

OPS

C409 SCD 22U10V2KX-1GP

1 2

OPS

C410 SCD 22U10V2KX-1GP

1 2

OPS

C411 SCD 22U10V2KX-1GP

1 2

OPS

C412 SCD 22U10V2KX-1GP

1 2

OPS

C413 SCD 22U10V2KX-1GP

1 2

OPS

C414 SCD 22U10V2KX-1GP

1 2

OPS

C415 SCD 22U10V2KX-1GP

1 2

OPS

C416 SCD 22U10V2KX-1GP

1 2

dGPU_RX N_C_CPU_TXN8 dGPU_RX N_C_CPU_TXN9 dGPU_RX N_C_CPU_TXN1 0 dGPU_RX N_C_CPU_TXN1 1 dGPU_RX N_C_CPU_TXN1 2 dGPU_RX N_C_CPU_TXN1 3 dGPU_RX N_C_CPU_TXN1 4 dGPU_RX N_C_CPU_TXN1 5

dGPU_RX P_C_CPU_TXP8 dGPU_RX P_C_CPU_TXP9 dGPU_RX P_C_CPU_TXP1 0 dGPU_RX P_C_CPU_TXP1 1 dGPU_RX P_C_CPU_TXP1 2 dGPU_RX P_C_CPU_TXP1 3 dGPU_RX P_C_CPU_TXP1 4 dGPU_RX P_C_CPU_TXP1 5

M14 DIS

A A

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

OAK14 Chief River DIS

Taipei Hsien 221, Taiwan, R.O.C.

CPU(PCIE/DMI/FDI)

4 105Wednesd ay, September 05, 20 12

A00

5

4

3

2

1

SSID = CPU

2 OF 9

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

MISC

2 OF 9

BCLK

BCLK#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

PRDY# PREQ#

TCK TMS

TRST#

TDO

DBR#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

CLK_EXP _P

J3

CLK_EXP _N

H2

CLK_DP_ P_R

AG3

CLK_DP_ N_R

AG1

SM_DRAM RST#

AT30

SM_RCOM P_0

BF44

SM_RCOM P_1

BE43

SM_RCOM P_2

BG43

XDP_PRD Y#

N53

XDP_PRE Q#

N55

XDP_TCL K

L56

XDP_TMS

L55

XDP_TRS T#

J58

XDP_TDI

M60

TDI

L59

K58

G58 E55 E59 G55 G59 H60 J59 J61

XDP_TDO

XDP_DBR ESET#

XDP_BPM 0 XDP_BPM 1 XDP_BPM 2 XDP_BPM 3 XDP_BPM 4 XDP_BPM 5 XDP_BPM 6 XDP_BPM 7

RN503

1

4

2 3

SRN1KJ-7 -GP

R507

4K99R2F -L-GP

1 2

R506 140 R2F-GPR506 140 R2F-GP

1 2

R508 25D 5R2F-GPR508 25D 5R2F-GP

1 2

R511 200 R2F-L-GPR511 200 R2F-L-GP

1 2

XDP_PRD Y# 71

XDP_PRE Q# 71

XDP_DBR ESET# 19

XDP_BPM 0 71 XDP_BPM 1 71 XDP_BPM 2 71 XDP_BPM 3 71 XDP_BPM 4 71 XDP_BPM 5 71 XDP_BPM 6 71 XDP_BPM 7 71

CLK_EXP _P 20 CLK_EXP _N 20

VCCP_CP U

SM_DRAM RST# 37

Layout Note:

Checking the connector pin's LAYOUT

Layout Note:

Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils. Trace width = 15mil

RN501

XDP_TDI XDP_TMS XDP_TDO

XDP_TRS T# XDP_TCL K

RN501

1 2 3

XDP

4 5

SRN51J-1 -GP

RN502

1 2 3

XDP

SRN51J-G P

8 7 6

4

VCCP_CP U

CPU1B

D D

R513

R504

R503

R509

H_SNB_IVB #

SKTOCC# _R

H_CATER R#

H_PECI

H_PROCH OT#_R

H_THERM TRIP#

H_PM_SYNC

H_CPUPW RGD_R

VDDPW RGOOD

BUF_CPU _RST#

12

DY

C501

C501 SC220P5 0V2KX-3GP

SC220P5 0V2KX-3GP

H_SNB_IVB #22

TP501TPAD14-O P-GP TP5 01TPAD14-O P-GP

VCCP_CP U

R501

1 2

62R2J-GP

C C

H_PROCH OT#

Layout Note:

R501, R513 place near to CPU

TP502TPAD14-O P-GP TP5 02TPAD14-O P-GP

H_PECI22,27

H_PROCH OT#27,38,40,4 2

H_THERM TRIP#22

H_PM_SYNC19

H_CPUPW RGD22

VDDPW RGOOD3 7

PLT_RST #18,27 ,31,65,71,83

1

1 2

R510

1K5R2F-2 -GP

56R2J-4-G P

0R0402-P AD

10KR2J-3 -GP

698R2F-G P

CPU1B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

MISC

CLOCKS

THERMAL

DDR3

PWR MANAGEMENT

JTAG & BPM

IVY-BRIDGE-GP-NF

71.00IVY.A0U

B B

H_CPUPW RGD PLT_RST # XD P_DBRESET#

12

EC501

EC501 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

DY

12

EC502

EC502 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

DY

Layout Note:

C501 place near to CPU

12

EC503

EC503 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

DY

71.00IVY.A0U

reserve for EMI Request

M14 DIS

A A

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

CPU(THERMAL/CLOCK/PM)

OAK14 Chief River DIS

Taipei Hsien 221, Taiwan, R.O.C.

5 105Wednesd ay, September 05, 20 12

A00

5

4

3

2

1

SSID = CPU

4 OF 9

CPU1D

AL4

AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9

BD13 BF12

BF8

BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54

BA58 AW59 AW58

AU58

AN61

AN59

AU59

AU61

AN58

AR58

AK58

AL58 AG58 AG59 AM60

AL59 AF61 AH60

BG39 BD42 AT22

AV43 BF40 BD45

CPU1D

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

3 OF 9

CPU1C

D D

C C

B B

M_A_DQ[6 3:0]14

M_A_DQ[6 3:0]

M_A_BS014 M_A_BS114 M_A_BS214

M_A_CAS #14 M_A_RAS #14 M_A_W E#14

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ1 0 M_A_DQ1 1 M_A_DQ1 2 M_A_DQ1 3 M_A_DQ1 4 M_A_DQ1 5 M_A_DQ1 6 M_A_DQ1 7 M_A_DQ1 8 M_A_DQ1 9 M_A_DQ2 0 M_A_DQ2 1 M_A_DQ2 2 M_A_DQ2 3 M_A_DQ2 4 M_A_DQ2 5 M_A_DQ2 6 M_A_DQ2 7 M_A_DQ2 8 M_A_DQ2 9 M_A_DQ3 0 M_A_DQ3 1 M_A_DQ3 2 M_A_DQ3 3 M_A_DQ3 4 M_A_DQ3 5 M_A_DQ3 6 M_A_DQ3 7 M_A_DQ3 8 M_A_DQ3 9 M_A_DQ4 0 M_A_DQ4 1 M_A_DQ4 2 M_A_DQ4 3 M_A_DQ4 4 M_A_DQ4 5 M_A_DQ4 6 M_A_DQ4 7 M_A_DQ4 8 M_A_DQ4 9 M_A_DQ5 0 M_A_DQ5 1 M_A_DQ5 2 M_A_DQ5 3 M_A_DQ5 4 M_A_DQ5 5 M_A_DQ5 6 M_A_DQ5 7 M_A_DQ5 8 M_A_DQ5 9 M_A_DQ6 0 M_A_DQ6 1 M_A_DQ6 2 M_A_DQ6 3

AG6

AP11

AJ10

AR11

AP6 AU6 AV9 AR6

AP8 AT13 AU13

BC7

BB7 BA13 BB11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37 BF36 BA28

BE39 BD39 AT41

AJ6

AL6

AJ8 AL8 AL7

CPU1C

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

3 OF 9

SA_CK0

SA_CK#0

SA_CKE0

SA_CK1

SA_CK#1

SA_CKE1

SA_CS#0 SA_CS#1

SA_ODT0 SA_ODT1

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AU36 AV36 AY26

AT40 AU40 BB26

BB40 BC41

AY40 BA41

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

M_A_DQS #0 M_A_DQS #1 M_A_DQS #2 M_A_DQS #3 M_A_DQS #4 M_A_DQS #5 M_A_DQS #6 M_A_DQS #7

M_A_DQS 0 M_A_DQS 1 M_A_DQS 2 M_A_DQS 3 M_A_DQS 4 M_A_DQS 5 M_A_DQS 6 M_A_DQS 7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DIMA_ CLK_DDR0 14 M_A_DIMA_ CLK_DDR#0 1 4 M_A_DIMA_ CKE0 14

M_A_DIMA_ CLK_DDR1 14 M_A_DIMA_ CLK_DDR#1 1 4 M_A_DIMA_ CKE1 14

M_A_DIMA_ CS#0 14 M_A_DIMA_ CS#1 14

M_A_DIMA_ ODT0 14 M_A_DIMA_ ODT1 14

M_A_DQS #[7:0] 14

M_A_DQS [7:0] 1 4

M_A_A[15 :0] 14

M_B_DQ[6 3:0]15

M_B_DQ[6 3:0]

M_B_BS015 M_B_BS115 M_B_BS215

M_B_CAS #15 M_B_RAS #15 M_B_W E#15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ1 0 M_B_DQ1 1 M_B_DQ1 2 M_B_DQ1 3 M_B_DQ1 4 M_B_DQ1 5 M_B_DQ1 6 M_B_DQ1 7 M_B_DQ1 8 M_B_DQ1 9 M_B_DQ2 0 M_B_DQ2 1 M_B_DQ2 2 M_B_DQ2 3 M_B_DQ2 4 M_B_DQ2 5 M_B_DQ2 6 M_B_DQ2 7 M_B_DQ2 8 M_B_DQ2 9 M_B_DQ3 0 M_B_DQ3 1 M_B_DQ3 2 M_B_DQ3 3 M_B_DQ3 4 M_B_DQ3 5 M_B_DQ3 6 M_B_DQ3 7 M_B_DQ3 8 M_B_DQ3 9 M_B_DQ4 0 M_B_DQ4 1 M_B_DQ4 2 M_B_DQ4 3 M_B_DQ4 4 M_B_DQ4 5 M_B_DQ4 6 M_B_DQ4 7 M_B_DQ4 8 M_B_DQ4 9 M_B_DQ5 0 M_B_DQ5 1 M_B_DQ5 2 M_B_DQ5 3 M_B_DQ5 4 M_B_DQ5 5 M_B_DQ5 6 M_B_DQ5 7 M_B_DQ5 8 M_B_DQ5 9 M_B_DQ6 0 M_B_DQ6 1 M_B_DQ6 2 M_B_DQ6 3

4 OF 9

SB_CK0 SB_CK#0 SB_CKE0

SB_CK1 SB_CK#1 SB_CKE1

SB_CS#0 SB_CS#1

SB_ODT0 SB_ODT1

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0

SB_MA1

SB_MA2

SB_MA3

SB_MA4

SB_MA5

SB_MA6

SB_MA7

SB_MA8

SB_MA9

SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

BA34 AY34 AR22

BA36 BB36 BF27

BE41 BE47

AT43 BG47

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

M_B_DQS #0 M_B_DQS #1 M_B_DQS #2 M_B_DQS #3 M_B_DQS #4 M_B_DQS #5 M_B_DQS #6 M_B_DQS #7

M_B_DQS 0 M_B_DQS 1 M_B_DQS 2 M_B_DQS 3 M_B_DQS 4 M_B_DQS 5 M_B_DQS 6 M_B_DQS 7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DIMB_ CLK_DDR0 15 M_B_DIMB_ CLK_DDR#0 1 5 M_B_DIMB_ CKE0 15

M_B_DIMB_ CLK_DDR1 15 M_B_DIMB_ CLK_DDR#1 1 5 M_B_DIMB_ CKE1 15

M_B_DIMB_ CS#0 15 M_B_DIMB_ CS#1 15

M_B_DIMB_ ODT0 15 M_B_DIMB_ ODT1 15

M_B_DQS #[7:0] 15

M_B_DQS [7:0] 1 5

M_B_A[15 :0] 15

IVY-BRIDGE-GP-NF

71.00IVY.A0U

A A

5

4

3

IVY-BRIDGE-GP-NF

71.00IVY.A0U

2

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Wednesd ay, September 05, 20 12

Date: Sheet of

CPU (DDR)

OAK14 Chief River DIS

Taipei Hsien 221, Taiwan, R.O.C.

6 105

1

A00

5

SSID = CPU

4

3

2

1

CFG6

CFG2

CFG5

DY

12

R701

R701 1KR2J-1-G P

1KR2J-1-G P

12

OPS

12

OPS

R702

R702 1KR2J-1-G P

1KR2J-1-G P

R704

R704 1KR2J-1-G P

1KR2J-1-G P

PEG Static Lane Reversal

CFG[2]

1: Normal Opera tion; Lane # definition m atches socket pin map definit ion

0:Lane Reversed

Display Port Pr esence Strap

1: Disabled; No Physical Disp lay Port

CFG[4]

attached to Emb edded Display Port

0: Enabled; An external Displ ay Port device is connected to the Embedded Display Port

PCIE Port Bifur cation Straps

CFG[6:5]

11:

1x16 PCI Express

2 x8 - PCI Express

10:

Reserved

01:

1x8, 2x4 PCI Express

00:

5 OF 9

CPU1E

D D

CFG071

TP701TP701

TP702TP702 TP703TP703

C C

TP719TP719

B B

1

1 1

VCC_DIE_S ENSE

1

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6

CPU1E

B50

CFG0

C51

CFG1

B54

CFG2

D53

CFG3

A51

CFG4

C53

CFG5

C55

CFG6

H49

CFG7

A55

CFG8

H51

CFG9

K49

CFG10

K53

CFG11

F53

CFG12

G53

CFG13

L51

CFG14

F51

CFG15

D52

CFG16

L53

CFG17

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

G48

RSVD47

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

RESERVED

5 OF 9

BCLK_ITP

BCLK_ITP#

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RSVD45

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59

DC_TEST_C59

DC_TEST_A61

DC_TEST_C61

DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4

DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1

DC_TEST_BD1

BCLK_ITP

N59

BCLK_ITP#

N58

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4

DC_TEST _C4_D3

D3 D1 A58 A59

TP_DC_T EST_A59_C59

C59 A61

TP_DC_T EST_A61_C61

C61 D61 BD61 BE61

TP_DC_T EST_BE59_BE6 1

BE59 BG61

DC_TEST _BG59_BG61

BG59 BG58 BG4 BG3

DC_TEST _BE3_BG3

BE3 BG1

DC_TEST _BE1_BG1

BE1 BD1

TP721TP721

1

TP722TP722

1

IVY-BRIDGE-GP-NF

71.00IVY.A0U

M14 DIS

A A

5

4

3

2

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Wednesd ay, September 05, 20 12

Date: Sheet of

CPU (RESERVED)

OAK14 Chief River DIS

Taipei Hsien 221, Taiwan, R.O.C.

7 105

1

A00

5

4

3

2

1

SSID = CPU

VCC_CORE

SC22U6D3V5MX-2GP

C801

C803

12

D D

C C

B B

A A

SC10U6D3V3MX-GP

C812

C813

12

SC2D2U6D3V2MX-GP

C814

C815

12

SC2D2U6D3V2MX-GP

C824

C825

12

DY

Refer to CPU EDS V.1.7.5

SC22U6D3V5MX-2GP

C805

C804

12

SC2D2U6D3V2MX-GP

C817

C816

12

SC2D2U6D3V2MX-GP

C826

C827

12

DY

Voltage Rail

VCC_CORE

VAXG

VCCIO

VDDQ 1.5

VCCSA

VCCPLL

5

SC22U6D3V5MX-2GP

C806

12

SC2D2U6D3V2MX-GP

C819

12

DY

SC2D2U6D3V2MX-GP

C828

12

DY

Voltage(V)

0.3~1.52

0~1.52

1.05

0.675~0.9

1.8

SC22U6D3V5MX-2GP

C807

12

SC2D2U6D3V2MX-GP

C818

12

SC2D2U6D3V2MX-GP

C829

12

C808

12

SC2D2U6D3V2MX-GP

C820

12

Iccmax(A)

33

29

8.5

1.2

12

(GT2)

5

4

C809

SC2D2U6D3V2MX-GP

C821

SC10U6D3V3MX-GP

SC22U6D3V5MX-2GP

SC10U6D3V3MX-GP

C811

C810

12

SC2D2U6D3V2MX-GP

C822

C823

12

DY

VCC_CORE

4

ULV 33A

CPU1F

A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

IVY-BRIDGE-GP-N F

71.00IVY.A0U

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76

POWER

CORE SUPPLY

6 OF 9

VCCIO1 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29

VCCIO30 VCCIO31 VCCIO32

PEG IO AND DDR IO

VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 VCCIO40 VCCIO41 VCCIO42 VCCIO43 VCCIO44 VCCIO45 VCCIO46 VCCIO47 VCCIO48 VCCIO49

VCCIO50 VCCIO51

VCCIO_SEL

VCCPQE1 VCCPQE2

RAILS

VIDALERT#

VIDSCLK VIDSOUT

SVID QUIET

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES

3

AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

H_CPU_SVIDALR T# H_CPU_SVIDC LK H_CPU_SVIDD AT

VCCSENSE VSSSENSE

H_SNB_IVB#_PW RCTRL

+V1.05S_VCCPQE _R

DY

12

C802

C802 SC1U6D3V2KX- GP

SC1U6D3V2KX- GP

VCCP_CPU

C830

12

C843

12

C887

12

R812

R812 0R0402-PAD

0R0402-PAD

12

R807

R807 10R2F-L-GP

10R2F-L-GP

12

R806

R806 10R2F-L-GP

10R2F-L-GP

VCCP_CPU

8.5A

SC1U6D3V2KX-GP

C831

C832

12

SC1U6D3V2KX-GP

C844

C845

12

C894

12

SC1U6D3V2KX-GP

C890

C891

12

DY

C895

12

TP801TP801

1

12

R803

R803 43R2J-GP

43R2J-GP

1 2

SC1U6D3V2KX-GP

C833

C834

C835

12

DY

SC1U6D3V2KX-GP

C837

C839

C840

12

DY

SC10U6D3V3MX-GP

SC4D7U6D3V3KX-GP

C892

C896

12

DY

SC1U6D3V2KX-GP

C846

C847

C848

12

DY

SC10U6D3V3MX-GP

C897

12

DY

75R2F-2-GP

VCCIO_SENSE 45 VSSIO_SENSE 45

12

R805

SC10U6D3V3MX-GP

C893

VCCP_CPUVCCP_CPU

VCC_CORE

DY

12

SC10U6D3V3MX-GP

Layout Note:

1. PH/PL resisors place close CPU

2. SENSE signal recommend differential routing

SC1U6D3V2KX-GP

12

SC1U6D3V2KX-GP

12

C888

12

SC1U6D3V2KX-GP

12

C889

12

R804

R804 130R2F-1-GP

130R2F-1-GP

12

R801

R801 100R2F-L1-GP- U

100R2F-L1-GP- U

12

R802

R802 100R2F-L1-GP- U

100R2F-L1-GP- U

2

SC1U6D3V2KX-GP

C838

C836

12

SC1U6D3V2KX-GP

C842

C841

12

DY

SC10U6D3V3MX-GP

SC4D7U6D3V3KX-GP

C884

12

VCCP_CPU

SC1U6D3V2KX-GP

C881

C883

C886

C882

12

SC10U6D3V3MX-GP

C885

12

VCCPQ Output Decoupling CAP Recommendation:

1 x 1 uF (0402)

Layout Note:

R803, R804, R805 need close to CPU Alert# signal must be routed between the Clock and Data lines to reduce the cross talk between them

VR_SVID_ALERT# 42

H_CPU_SVIDC LK 42

H_CPU_SVIDD AT 42

Layout Note:

1. PH/PL resisors place close CPU

2. SENSE signal recommend differential routing

VCCSENSE 43 VSSSENSE 43

Need place Pull Hi at IMVP page

M14 DIS

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Wednesd ay, September 05, 2012

Wednesd ay, September 05, 2012 Date: Sheet of

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

CPU (VCC_CORE)

OAK14 Chief River DIS

1

8 105

A00

SSID = CPU

5

4

3

2

1

Voltage Rail

Layout Note:

POWER

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54 VAXG55 VAXG56

VAXG_SENSE VSSAXG_SENSE

VCCPLL1 VCCPLL2 VCCPLL3

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 VCCSA9 VCCSA10 VCCSA11 VCCSA12 VCCSA13 VCCSA14 VCCSA15 VCCSA16

POWER

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

VCCSA VID

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VREF

DDR3 - 1.5V RAILS

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

SENSE LINES

VCCSA_VID0 VCCSA_VID1

lines

SM_VREF

CPU1G

VCC_GFXCO RE

C901

SC22U6D3V5MX-2GP

C901

D D

SC22U6D3V5MX-2GP

12

C938

SC10U6D3V3MX-GP

C938

SC10U6D3V3MX-GP

12

C902

SC10U6D3V5KX-1GP

C902

SC10U6D3V5KX-1GP

12

C939

SC10U6D3V3MX-GP

C939

SC10U6D3V3MX-GP

12

ULV GT2 33A

C904

SC10U6D3V5KX-1GP

C904

SC10U6D3V5KX-1GP

C903

SC22U6D3V5MX-2GP

C903

SC22U6D3V5MX-2GP

12

C941

SC10U6D3V3MX-GP

C941

SC10U6D3V3MX-GP

C940

SC10U6D3V3MX-GPDYC940

SC10U6D3V3MX-GP

12

C906

SC22U6D3V5MX-2GP

C906

SC22U6D3V5MX-2GP

C905

SC22U6D3V5MX-2GP

C905

SC22U6D3V5MX-2GP

12

C942

SC10U6D3V3MX-GP

C942

SC10U6D3V3MX-GP

C943

SC10U6D3V3MX-GP

C943

SC10U6D3V3MX-GP

12

DY

C948

SC1U6D3V2KX-GPDYC948

C944

SC1U6D3V2KX-GPDYC944

SC1U6D3V2KX-GP

C946

SC1U6D3V2KX-GP

C946

SC1U6D3V2KX-GP

C945

SC1U6D3V2KX-GP

C945

SC1U6D3V2KX-GP

12

DY

C951

SC1U6D3V2KX-GPDYC951

SC1U6D3V2KX-GP

C952

SC1U6D3V2KX-GP

C952

C953

SC1U6D3V2KX-GP

C953

SC1U6D3V2KX-GP

12

DY

C C

Layout Note:

1. PH/PL resisors place close CPU

2. SENSE signal recommend differential routing

SC1U6D3V2KX-GP

C949

SC1U6D3V2KX-GP

C949

C947

SC1U6D3V2KX-GP

C947

SC1U6D3V2KX-GP

12

SC1U6D3V2KX-GP

12

DY

C954

SC1U6D3V2KX-GP

C954

SC1U6D3V2KX-GP

C950

SC1U6D3V2KX-GPDYC950

SC1U6D3V2KX-GP

12

DY

VCC_GFXCO RE

12

R901

100R2F-L1-GP- U

VCC_AXG_SEN SE44

VSS_AXG_SENSE44

100R2F-L1-GP- U

1D8V_S0

1.2A

C907

SC1U6D3V2KX-GP

C907

SC1U6D3V2KX-GP

VCC_AXG_SEN SE

VSS_AXG_SENSE

12

R902

C955

SC10U6D3V5KX-1GPDYC955

SC10U6D3V5KX-1GP

C908

SC1U6D3V2KX-GP

C908

SC1U6D3V2KX-GP

12

DY

B B

0D85V_S0

C913

SC10U6D3V3MX-GP

DY

ULV 4A

C912

12

C918

SC1U6D3V2KX-GPDYC918

SC1U6D3V2KX-GP

12

C911

SC10U6D3V3MX-GPDYC911

SC10U6D3V3MX-GP

SC10U6D3V3MX-GPDYC912

SC10U6D3V3MX-GP

C910

SC10U6D3V3MX-GP

C910

SC10U6D3V3MX-GP

C909

SC10U6D3V3MX-GP

C909

SC10U6D3V3MX-GP

12

DY

C917

12

DY

C915

SC1U6D3V2KX-GP

C915

SC1U6D3V2KX-GP

C916

SC1U6D3V2KX-GP

C916

SC1U6D3V2KX-GP

SC1U6D3V2KX-GPDYC917

SC1U6D3V2KX-GP

12

DY

CPU1G

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46

N45 P47 P48 P50 P51 P52 P53 P55 P56 P61

T48 T58 T59

T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61

F45 G45

BB3 BC1 BC4

L17

L21 N16 N20 N22 P17 P20 R16 R18 R21 U15 V16 V17 V18 V21 W20

C914

SC1U6D3V2KX-GP

C914

SC1U6D3V2KX-GP

IVY-BRIDGE-GP-N F

71.00IVY.A0U

+V_SM_VREF_CNT should have 10 mil trace width

7 OF 9

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26

VCCDQ1 VCCDQ2

AY43

DDR_W R_VREFA

BE7

DDR_W R_VREFB

BG7

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

BC43 BA43

U10

D48 D49

+V_SM_VREF_C NT

C927

12

TP_VDDQ_SEN SE TP_VDDQ_VSS

VCCSA_SENS E

VCCSA_SEL0 VCCSA_SEL1

RN902

4

SRN1KJ-7-G P

SC1U6D3V2KX-GP

12

C937

SC1U6D3V2KX-GP

C937

SC1U6D3V2KX-GP

12

1 1

23

23 1

DY

C929

C928

SC1U6D3V2KX-GP

C928

SC1U6D3V2KX-GP

12

C919

12

R903

R903 0R0402-PAD

0R0402-PAD

TP901 TPAD 14-OP-GPTP901 TPAD14-OP-GP TP902 TPAD 14-OP-GPTP902 TPAD14-OP-GP

VCCSA_SEL0 48 VCCSA_SEL1 48

1

RN901

RN901 SRN1KJ-7-G P

SRN1KJ-7-G P

4

SC1U6D3V2KX-GP

C930

SC1U6D3V2KX-GP

C930

SC1U6D3V2KX-GP

12

SC10U6D3V3MX-GP

C920

SC10U6D3V3MX-GP

C920

SC10U6D3V3MX-GP

12

VCCSA_SENS E 48

C932

SC1U6D3V2KX-GP

C932

SC1U6D3V2KX-GP

C931

SC1U6D3V2KX-GPDYC931

SC1U6D3V2KX-GP

12

DY

C922

SC10U6D3V3MX-GP

C922

SC10U6D3V3MX-GP

C921

SC10U6D3V3MX-GPDYC921

SC10U6D3V3MX-GP

12

DY

1D5V_S0+V1.5S_VCCD_Q

VCC_CORE

VAXG

VCCIO

VDDQ 1.5

VCCSA

VCCPLL

Refer to CPU EDS V2.0

C934

SC1U6D3V2KX-GP

C934

SC1U6D3V2KX-GP

C933

SC1U6D3V2KX-GP

C933

SC1U6D3V2KX-GP

12

DY

C923

SC10U6D3V3MX-GP

C923

SC10U6D3V3MX-GP

C924

SC10U6D3V3MX-GP

C924

SC10U6D3V3MX-GP

12

VCCSA Power Select

Voltage(ULV)

0.9

0.85

0.775

0.75

5A

C935

SC1U6D3V2KX-GPDYC935

SC1U6D3V2KX-GP

12

C925

SC4D7U6D3V3KX-GP

C925

SC4D7U6D3V3KX-GP

12

VID[0] VID[1]

Voltage(V)

0.3~1.52

0~1.52

1.05

0.675~0.9

1.8

C936

SC1U6D3V2KX-GP

C936

SC1U6D3V2KX-GP

C926

SC10U6D3V3MX-GP

C926

SC10U6D3V3MX-GP

0

0 1

1D5V_S0

Iccmax(A)

33

(GT2)

29

8.5

5

3

1.2

0

01

11

A A

M14 DIS

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Wednesd ay, September 05, 2012

Wednesd ay, September 05, 2012 Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

CPU (VCC_GFXCORE)

OAK14 Chief River DIS

1

9 105

A00

5

SSID = CPU

CPU1H

4

8 OF 9

3

CPU1I

2

9 OF 9

1

A13

VSS1

A17

VSS2

A21

VSS3

A25

VSS4

D D

C C

B B

A A

A28 A33 A37 A40 A45 A49 A53

AA1 AA13 AA50 AA51 AA52 AA53 AA55 AA56

AA8 AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46

AC6 AD17 AD20

AD4 AD61 AE13

AE8

AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59

AG10 AG14 AG18 AG47 AG52 AG61

AG7 AH4

AH58

AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48

AJ7

AK1

AK52

AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61

AM13 AM20 AM22 AM26 AM30 AM34

VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11

A9

VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90

VSS

VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53

BG9

C29 C35 C40 D10 D14 D18 D22 D26 D29 D35

D4 D40 D43 D46 D50 D54 D58

D6 E25 E29

E3 E35 E40 F13 F15 F19 F29 F35 F40 F55

G51

G6

G61

H10 H14 H17 H21

H4 H53 H58

J1 J49 J55

K11 K21 K51

K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61

M11 M15

IVY-BRIDGE-GP-NF

71.00IVY.A0U

VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249

VSS

NCTF TEST PIN：A5,A57,BC61,BG5

NCTF

VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300

VSS_NCTF_1#A5

VSS_NCTF_2#A57

VSS_NCTF_3#BC61

VSS_NCTF_8#BG5

VSS_NCTF_9#BG57

VSS_NCTF_10#C3

VSS_NCTF_13#E1

VSS_NCTF_14#E61

BG57,C3,E1,E61

VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6

VSS_NCTF_7 VSS_NCTF_11 VSS_NCTF_12

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59

A5 A57 BC61 BG5 BG57 C3 E1 E61

BD3 BD59 BE4 BE58 C58 D59

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

IVY-BRIDGE-GP-NF

71.00IVY.A0U

5

4

3

2

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Wednesd ay, September 05, 20 12

Date: Sheet of

CPU (VSS)

OAK14 Chief River DIS

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

10 10 5

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Wednesd ay, September 05, 20 12

Date: Sheet of

XDP

OAK14 Chief River DIS

Taipei Hsien 221, Taiwan, R.O.C.

11 10 5

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document N umber Rev

A3

Date: Sheet of

Reserved

OAK14 Chief River DIS

Taipei Hsien 221, Taiwan, R.O.C.

12 10 5Wednesd ay, September 05, 20 12

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)

Size Document N umber Rev

A3

Date: Sheet of

(Reserved)

OAK14 Chief River DIS

Taipei Hsien 221, Taiwan, R.O.C.

13 10 5Wednesd ay, September 05, 20 12

1

A00

5

SSID = MEMORY

M_A_A[15:0]6

D D

DDR_VREF _S3

12

DDR_VREF _S3

12

C C

12

0D75V_S0

12

B B

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

R1405

R1405 0R0402-PAD

0R0402-PAD

C1427

SCD1U10V2KX-5GP

R1404

R1404 0R0402-PAD

0R0402-PAD

C1411

SCD1U10V2KX-5GP

C1419

DY

SC1U6D3V2KX-GP

Layout Note:

Place these caps close to VREF_CA

M_VREF_CA_D IMMA

12

DY

C1428

SC2D2U10V3KX-1GP

Layout Note:

Place these caps close to VREF_DQ

M_VREF_DQ_D IMMA

12

DY

C1423

SC2D2U10V3KX-1GP

Layout Note:

Place these caps close to VTT1 and VTT2.

12

C1420

SC1U6D3V2KX-GP

12

C1426

SCD1U10V2KX-5GP

12

C1429

SCD1U10V2KX-5GP

C1418

SC1U6D3V2KX-GP

M_A_BS26

M_A_BS06 M_A_BS16

M_A_DQ[63:0]6

M_A_DQS#[7:0]6

M_A_DQS[7:0]6

M_A_DIMA_ODT06 M_A_DIMA_ODT16

M_VREF_CA_D IMMA M_VREF_DQ_D IMMA

DDR3_DR AMRST#15,37

0D75V_S0

EC1401

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

1 2

SCD1U10V2KX- 5GP

DY

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P- 119-GP-U

62.10017.Z81

RAS#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

4

NP1

NP2

110 113

WE#

115

114 121

73 74

101

CK0

103

102

CK1

104

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

199

SA0_DIMA

197

SA0

SA1_DIMA

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D5V_S3

M_A_RAS# 6 M_A_WE# 6 M_A_CAS# 6

M_A_DIMA_CS#0 6 M_A_DIMA_CS#1 6

M_A_DIMA_CKE0 6 M_A_DIMA_CKE1 6

M_A_DIMA_CLK_DD R0 6 M_A_DIMA_CLK_DD R#0 6

M_A_DIMA_CLK_DD R1 6 M_A_DIMA_CLK_DD R#1 6

PCH_SMBDAT A 15,20,69 PCH_SMBCLK 15,20, 69

SCD1U10V2KX- 5GP

Close to DIMM1.199

3D3V_S0

12

C1401

Layout Note:

Place these Caps near SO-DIMMA.

3

SA0_DIMA SA1_DIMA

0R0402-PAD

1D5V_S3

12

C1403

TC1401

DY

ST330U2VDM-4-GP

SC10U6D3V5KX-1GP

12

C1414

C1415

SCD1U10V2KX-5GP

1D5V_S31D5V_S0

1 2

DY

C1421

SCD1U10V2KX- 5GP

1 2

DY

C1424

SCD1U10V2KX- 5GP

Layout Note:

For S3 reduction circuit's 1D5V return pass.

12

R1402

R1402 0R0402-PAD

0R0402-PAD

R1401

12

C1405

C1404

DY

SC10U6D3V5KX-1GP

12

C1417

C1416

SC1U6D3V2KX-GP

2

Note: SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

12

C1406

SC10U6D3V5KX-1GP

C1408

C1407

DY

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

1

A A

M14 DIS

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Wednesd ay, September 05, 2012

Wednesd ay, September 05, 2012 Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

DDR3-SODIMM1

DNE40 14 CR DIS

1

14 105

A00

5

SSID = MEMORY

DDR_VREF _S3

D D

12

R1505

R1505 0R0402-PAD

0R0402-PAD

M_VREF_CA_D IMMB

Layout Note:

Place these caps

12

DY

SCD1U10V2KX-5GP

12

DY

SCD1U10V2KX-5GP

12

C1524

SC2D2U10V3KX-1GP

M_VREF_DQ_D IMMB

12

C1516

SC2D2U10V3KX-1GP

12

C1519

SC1U6D3V2KX-GP

close to VREF_CA

C1522

SCD1U10V2KX-5GP

C1517

SCD1U10V2KX-5GP

C1521

SC1U6D3V2KX-GP

12

C1523

DDR_VREF _S3

12

R1503

R1503 0R0402-PAD

0R0402-PAD

C C

B B

12

C1515

0D75V_S0

12

C1518

DY

SC1U6D3V2KX-GP

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

M_B_A[15:0]6

M_B_BS26

M_B_BS06 M_B_BS16

M_B_DQ[63:0]6

Layout Note:

Place these caps close to VREF_DQ

Layout Note:

Place these caps close to VTT1 and VTT2.

M_B_DQS#[7:0]6

M_B_DQS[7:0]6

M_B_DIMB_ODT06 M_B_DIMB_ODT16

M_VREF_CA_D IMMB M_VREF_DQ_D IMMB

DDR3_DR AMRST#14,37

0D75V_S0

EC1501

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

1 2

SCD1U10V2KX- 5GP

DY

107

119

109 108

129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

135 152 169 186

137 154 171 188

116 120

126

203 204

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9 A10/AP

84

A11

83

A12 A13

80

A14

78

A15

79

A16/BA2

BA0 BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3# DQS4# DQS5# DQS6# DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3 DQS4 DQS5 DQS6 DQS7

ODT0 ODT1

VREF_CA

1

VREF_DQ

30

RESET#

VTT1 VTT2

DDR3-204P- 90-GP

62.10017.U81

4

EVENT#

VDDSPD

NC#/TEST

VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

RAS#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

NC#1 NC#2

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9

3

NP1

NP2

110 113

WE#

115

114 121

73 74

101

CK0

103

102

CK1

104

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

199

SA0_DIMB

197

SA0

SA1_DIMB

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D5V_S3

M_B_RAS# 6 M_B_WE# 6 M_B_CAS# 6

M_B_DIMB_CS#0 6 M_B_DIMB_CS#1 6

M_B_DIMB_CKE0 6 M_B_DIMB_CKE1 6

M_B_DIMB_CLK_DD R0 6 M_B_DIMB_CLK_DD R#0 6

M_B_DIMB_CLK_DD R1 6 M_B_DIMB_CLK_DD R#1 6

PCH_SMBDAT A 14,20,69 PCH_SMBCLK 14,20, 69

SCD1U10V2KX- 5GP

C1501

3D3V_S0

Close to DIMM1.199

1D5V_S3

12

C1503

C1504

C1507

DY

SC10U10V5ZY-1GP

12

C1511

SCD1U10V2KX-5GP

Layout Note:

Place these Caps near SO-DIMMA.

C1507

DY

SC10U10V5ZY-1GP

12

C1513

C1512

SCD1U10V2KX-5GP

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

3D3V_S0

R1507

SA1_DIMB

1 2

10KR2J-3-GP

R1506

SA0_DIMB

1 2

0R0402-PAD

12

DY

C1508

SC10U6D3V5KX-1GP

12

C1514

DY

SCD1U10V2KX-5GP

C1510

C1509

SC10U6D3V5KX-1GP

2

1

A A

M14 DIS

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Wednesd ay, September 05, 2012

Wednesd ay, September 05, 2012 Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

DDR3-SODIMM2

OAK14 Chief River DIS

1

15 105

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

OAK14 Chief River DIS

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

16 10 5Wednesd ay, September 05, 20 12

A00

5

4

3

2

1

SSID = PCH

D D

3D3V_S0

RN1701

1 2 3

SRN2K2J -1-GP

RN1702

2 3 1

SRN100K J-6-GP

C C

B B

4

L_CTRL_ DATA L_CTRL_ CLK

L_BKLT_ EN LVDS_VD D_EN

Layout Note:

Place near PCH; trace to trace spacing=20mil

Layout Note:

LVDS signal trace length max 4000mil

SRN2K2J -1-GP

Layout Note:

Place near PCH; trace to trace spacing=30mil

RN1707

12

R1701

R1701 2K37R2F -GP

2K37R2F -GP

3D3V_S0

2 3

L_BKLT_ EN27 LVDS_VD D_EN49

L_BKLT_ CTRL49

LVDS_DD C_CLK_R49 LVDS_DD C_DATA_R49

TP1701TP1701

LVDSA_C LK#49 LVDSA_C LK49

LVDSA_D ATA0#49 LVDSA_D ATA1#49 LVDSA_D ATA2#49

LVDSA_D ATA049 LVDSA_D ATA149 LVDSA_D ATA249

LVDSB_C LK#49 LVDSB_C LK49

LVDSB_D ATA0#49 LVDSB_D ATA1#49 LVDSB_D ATA2#49

LVDSB_D ATA049 LVDSB_D ATA149 LVDSB_D ATA249

4

1

1KR2J-1-G P

R1702

LVDS_DD C_CLK_R LVDS_DD C_DATA_R

L_CTRL_ CLK L_CTRL_ DATA

LVDS_IBG LVDS_VB G

1

CRT_DDC CLK CRT_DDC DATA

DAC_IREF_ R

12

PCH1D

J47

M45

P45

T40 K47

T45 P39

AF37 AF36

AE48 AE47

AK39 AK40

AN48

AM47

AK47

AJ48

AN47 AM49

AK49

AJ47

AF40 AF39

AH45 AH47

AF49 AF45

AH43 AH49

AF47 AF43

N48

P49 T49

T39

M40

M47 M49

T43 T42

PANTHER -GP-NF

71.0HM76.A0U

L_BKLTEN L_VDD_EN

L_BKLTCTL

L_DDC_CLK L_DDC_DATA

L_CTRL_CLK L_CTRL_DATA

LVD_IBG LVD_VBG

LVD_VREFH LVD_VREFL

LVDSA_CLK# LVDSA_CLK

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSB_CLK# LVDSB_CLK

LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

DAC_IREF CRT_IRTN

LVDS

Digital Display Interface

CRT

4 OF 10

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SRN2K2J -1-GP

RN1706

3D3V_S0

4

1

2 3

Layout Note:

Close HDMI port

PCH_HDM I_CLK 51 PCH_HDM I_DATA 51

HDMI_PCH_ DET 51

HDMI_DATA 2_R# 51 HDMI_DATA 2_R 51 HDMI_DATA 1_R# 51 HDMI_DATA 1_R 51 HDMI_DATA 0_R# 51 HDMI_DATA 0_R 51 HDMI_CLK_ R# 51 HDMI_CLK_ R 51

Layout Note:

HDMI trace length to DC CAP. max 10000mil

A A

5

4

3

2

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Wednesd ay, September 05, 20 12

Date: Sheet of

PCH (LVDS/CRT/DDI)

OAK14 Chief River DIS

Taipei Hsien 221, Taiwan, R.O.C.

17 10 5

1

A00

5

4

3

2

1

SSID = PCH

5 OF 10

PCH1E

BG26

BJ26

BH25

BJ16 BG16 AH38 AH37 AK43 AK45

C18 N30

AH12

AM4 AM5

Y13 K24

AB46 AB45

B21

M20 AY16 BG46

BE28 BC30 BE32

BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

G38

C46 C44 E40

D47 E42

G42 G40 C42 D44

K10

H49 H43

K42 H40

L24

K40 K38 H38

F46

J48

H3

C6

PCH1E

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

USB3RN1 USB3RN2 USB3RN3 USB3RN4 USB3RP1 USB3RP2 USB3RP3 USB3RP4 USB3TN1 USB3TN2 USB3TN3 USB3TN4 USB3TP1 USB3TP2 USB3TP3 USB3TP4

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PME#

PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

PANTHER -GP-NF

71.PANTH.00U

3

RSVD

PCI

USB

3D3V_S0

RN1803

SRN10KJ -6-GP

8 7

3D3V_S0

6

RN1804

SRN10KJ -6-GP

8 7 6

RN1805

SRN10KJ -6-GP

8 7 6

D D

C C

Boot Bios Strap

GNT1#/GPIO51

0 0

B B

1

10

0

1 1

PCI_GNT3#

12

DY

R1801

R1801 4K7R2J-2 -GP

4K7R2J-2 -GP

A16 Swap Overr ide jumper

PCI_GNT#3 Lo w = A16 swap o verride/Top-Blo ck

A A

Swap Override e nabled High = Default

5

PCH_GPIO5 0

1

PCH_GPIO5 4

2

PCH_GPIO0 2

3

BOARD_ID1

45

1 2 3 45

INT_PIRQD# KB_LED_ BL_DET INT_PIRQC# PCH_GPIO0 4

PCH_GPIO5 2 INT_PIRQB# SATA_OD D_DA# INT_PIRQA#

BOARD_ID1 20

USB3.0/2.0 Mapping Table

USB 3.0 Port USB 2.0 port

Port 1

Port 2

Port 3

Port 4

Boot BIOS Locat ionSATA1GP/GPIO19

LPC

Reserved

SPI(Default)

Port 0

Port 1

Port 2

Port 3

CLK_PCI_L PC71 CLK_PCI_F B20 CLK_PCI_K BC27

EC1802

Layout Note:

Trace Length : PCH ~~9000mil~~Cap~~1000mil~~CONN

USB3_RX 1_N62 USB3_RX 2_N62

USB3_RX 1_P62 USB3_RX 2_P62

USB3_TX 1_N62 USB3_TX 2_N62

USB3_TX 1_P62 USB3_TX 2_P62

3D3V_S0

R1808 10K R2J-3-GP

1 2

TP1801TP1801

DY

SATA_OD D_DA#56

TP1802TP1802

R1807 22R 2J-2-GP

1 2

LPC

R1805 22R 2J-2-GPR1805 22R 2J-2-GP

1 2

R1806 22R 2J-2-GPR1806 22R 2J-2-GP

1 2

EC1805

EC1804

DY

1 2

SC4D7P50V2CN-1GP

100KR2J -1-GP

R1816

DY

1 2

SC10P50V2JN-4GP

12

DY

1 2

SC4D7P50V2CN-1GP

PLT_RST #5,27,31,65 ,71,83

4

USB3_RX 1_N USB3_RX 2_N

USB3_RX 1_P USB3_RX 2_P

USB3_TX 1_N USB3_TX 2_N

USB3_TX 1_P USB3_TX 2_P

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

PCH_GPIO5 0 PCH_GPIO5 2 PCH_GPIO5 4

BBS_BIT1 PCH_GPIO5 3

1

PCI_GNT3#

PCH_GPIO0 2

PCH_GPIO0 4 KB_LED_ BL_DET

PCI_PME#

1

PCI_PLTRS T#

CLK_PCI_L PC_R CLK_PCI_F B_R CLK_PCI_K BC_R

R1823

1 2

0R0402-P AD

C1801

C1801 SC220P5 0V2KX-3GP

SC220P5 0V2KX-3GP

PCI_PLTRS T#

5 OF 10

RSVD1 RSVD2 RSVD3 RSVD4

RSVD5 RSVD6

RSVD7 RSVD8

RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22

RSVD23 RSVD24

RSVD25

RSVD26 RSVD27

RSVD28 RSVD29

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5 AV10

AT8

AY5 BA2

AT12 BF3

USB2.0 Signal Group

C24 A24 C25 B25 C26 A26 K28 H28

USB_PN4 USB_PP4

USB_OC# 0_1

USB_OC# 4_5

1 1

2

E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

USB_RBIAS

USB_PN0 62 USB_PP0 62 USB_PN1 62 USB_PP1 62 USB_PN2 82 USB_PP2 82

TP1803TP1803 TP1804TP1804

USB_PN5 49 USB_PP5 49

USB_PN1 0 32 USB_PP1 0 32 USB_PN1 1 65 USB_PP1 1 65

USB_PN1 3 49 USB_PP1 3 49

1 2

R1811

R1811 22D6R2F -L1-GP

22D6R2F -L1-GP

OC#

USB_OC# 0_1 USB_OC# 4_5

USB Table

Pair

USB3.0 port2

0

USB3.0 port1, with Debug Port

1

USB2.0 port3

2

NC

3

NC

4

Touch Panel

5

HM76 NC

6

HM76 NC

7

NC

8

NC

9

Card reader

10

WLAN

11

NC

12

CAMERA

13

1. USB Ext. port 9 (HS) External debug port use on Chief River platform.

2. 2011 July; Microsoft will support USB3.0 debug--> Port1 useable.

Layout Note:

1. USBRBIAS/# use 50ohm single-ended impedance spacing to other signal=15mil

2. Length < 500mil

USB_OC# 0_1 61

USB_OC# 4_5 61

R1812

R1812 8K2R2J-3 -GP

8K2R2J-3 -GP

1 2

RN1802

1 2 3

SRN10KJ -5-GP

M14 DIS

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Wednesd ay, September 05, 20 12

Date: Sheet of

3D3V_S5

4

3D3V_S5

PCH (PCI/USB/NVRAM)

DNE40 14 CR DIS

Device

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

18 10 5

1

A00

5

4

3

2

1

SSID = PCH

3 OF 10

PCH1C

DMI_CPU_T XN_PCH_RXN[3:0]4

D D

Layout Note:

DMI_ZCOMP keep W=4 mils and routing length less than 500 mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.

C C

PM_DRAM _PWRGD37

B B

Sequence: S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

DMI_CPU_T XP_PCH_RXP[3:0]4

DMI_CPU_R XN_PCH_TXN[3:0]4

DMI_CPU_R XP_PCH_TXP[3:0]4

1D05V_P CH

R1901 4 9D9R2F-GPR1901 49D9R2F -GP

1 2

R1902 750R2F-GPR 1902 750R2F-G P

1 2

3D3V_S0

XDP_DBR ESET#5

SYS_PW ROK36

R1921

S0_PW R_GOOD27,36

RUNPW ROK45,46,47,9 3

RSMRST# _KBC27

PM_PW RBTN#27

AC_PRES ENT27,86

BATLOW #27

1 2

0R0402-P AD

R1905 1 0KR2J-3-GPR1905 10KR2J-3 -GP

1 2

DY

R1907 0R2J-2-GP

R1924

1 2

0R0402-P AD

TP1907TP1907

1 2

PWRO K

1 2

0R0402-P AD

DMI_CPU_T XN_PCH_RXN0 DMI_CPU_T XN_PCH_RXN1 DMI_CPU_T XN_PCH_RXN2 DMI_CPU_T XN_PCH_RXN3

DMI_CPU_T XP_PCH_RXP0 DMI_CPU_T XP_PCH_RXP1 DMI_CPU_T XP_PCH_RXP2 DMI_CPU_T XP_PCH_RXP3

DMI_CPU_R XN_PCH_TXN0 DMI_CPU_R XN_PCH_TXN1 DMI_CPU_R XN_PCH_TXN2 DMI_CPU_R XN_PCH_TXN3

DMI_CPU_R XP_PCH_TXP0 DMI_CPU_R XP_PCH_TXP1 DMI_CPU_R XP_PCH_TXP2 DMI_CPU_R XP_PCH_TXP3

DMI_COMP_ R

RBIAS_CPY

SUSACK#

1

R1916

MEPW ROK

PM_RSMR ST#

SUS_PW R_ACK

PM_PW RBTN#

AC_PRES ENT

BATLOW #

PM_RI#

PCH1C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT/GPIO31

E10

BATLOW#/GPIO72

A10

RI#

PANTHER -GP-NF

71.PANTH.00U

DMI

SUS_STAT#/GPIO61

System Power Management

3 OF 10

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN#/GPIO32

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN#/GPIO29

FDI_CPU_T XN_PCH_RXN0

BJ14

FDI_CPU_T XN_PCH_RXN1

AY14

FDI_CPU_T XN_PCH_RXN2

BE14

FDI_CPU_T XN_PCH_RXN3

BH13

FDI_CPU_T XN_PCH_RXN4

BC12

FDI_CPU_T XN_PCH_RXN5

BJ12

FDI_CPU_T XN_PCH_RXN6

BG10

FDI_CPU_T XN_PCH_RXN7

BG9

FDI_CPU_T XP_PCH_RXP0

BG14

FDI_CPU_T XP_PCH_RXP1

BB14

FDI_CPU_T XP_PCH_RXP2

BF14

FDI_CPU_T XP_PCH_RXP3

BG13

FDI_CPU_T XP_PCH_RXP4

BE12

FDI_CPU_T XP_PCH_RXP5

BG12

FDI_CPU_T XP_PCH_RXP6

BJ10

FDI_CPU_T XP_PCH_RXP7

BH9

FDI_INT

AW16

FDI_FSYNC0

AV12

FDI_FSYNC1

BC10

FDI_LSYNC0

AV14

FDI_LSYNC1

BB10

DSWO DVREN

A18

PCH_DPW ROK

E22

PCH_W AKE#

B9

PM_CLKR UN#

N3

PM_SUS_ STAT#

G8

SUS_CLK

N14

PM_SLP_ S5#

D10

PM_SLP_ S4#

H4

PM_SLP_ S3#

F4

PM_SLP_ A#

G10

PM_SLP_ SUS#

G16

H_PM_SYNC

AP14

PM_SLP_ LAN#

K14

FDI_CPU_T XN_PCH_RXN[7:0] 4

FDI_CPU_T XP_PCH_RXP[7:0] 4

FDI_INT 4

FDI_FSYNC0 4

FDI_FSYNC1 4

FDI_LSYNC0 4

FDI_LSYNC1 4

R1911 10K R2J-3-GP

1 2

DY

R1927

1

1 2

0R0402-P AD

1 2

0R0402-P AD

R1929

TP1901 TPAD14-OP-G PT P1901 TP AD14-OP-GP

R1925

TP1902 TPAD14-OP-G PT P1902 TP AD14-OP-GP

TP1903TP1903

TP1904TP1904

TP1905TP1905

RTC_AUX _S5

PM_RSMR ST#

PM_CLKR UN#_EC 27

PCH_SUS CLK_KBC 27

PM_SLP_ S4# 27,46

PM_SLP_ S3# 27,36,3 7,47

H_PM_SYNC 5

DSWODVREN - On Die DSW VR Ena ble

HIGH Enabled (DEFAULT)

LOW Disable d

DSWO DVREN

PM_CLKR UN#

PCH_SUS CLK_KBC

R1917 330 KR2J-L1-GPR1917 330 KR2J-L1-GP

1 2

R1919 8K2 R2J-3-GPR1919 8K2 R2J-3-GP

1 2

EC1901

SC4D7P5 0V2CN-1GP

EC1901

RTC_AUX _S5

3D3V_S0

DY

1 2

3D3V_S5

RN1901

SRN10KJ -6-GP

12

DY

12

DY

1 2 3 45

8 7 6

R1909 100 KR2J-1-GPR1909 100 KR2J-1-GP

1 2

R1920 10K R2J-3-GP

A A

R1908 10K R2J-3-GPR1908 10K R2J-3-GP

R1926 100 KR2J-1-GP

1 2

R1904 100 KR2J-1-GPR1904 100 KR2J-1-GP

1 2

5

BATLOW # PM_RI# SUS_PW R_ACK PCH_W AKE#

AC_PRES ENT PM_SLP_ LAN#

PM_RSMR ST#

SYS_PW ROK PWRO K

4

SYS_PW ROK S0_PWR _GOOD RUNPW ROK

12

EC1907

EC1907 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

DY

PM_DRAM _PWRGD R SMRST#_KBC AC_PRES ENT

12

EC1904

EC1904 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

DY

12

EC1902

EC1902 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

DY

12

EC1905

EC1905 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

DY

12

EC1903

EC1903 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

DY

12

EC1906

EC1906 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

DY

reserve for EMI Request

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Wednesd ay, September 05, 20 12

Date: Sheet of

3

2

Date: Sheet of

PCH (DM I/FDI/PM)

DNE40 14 CR DIS

Taipei Hsien 221, Taiwan, R.O.C.

19 10 5

1

A00

5

SSID = PCH

3D3V_S5

D D

PCH_RXN _C_LAN_TXN631 PCH_RXP _C_LAN_TXP631 LAN_RXN _C_PCH_TXN631 LAN_RXP _C_PCH_TXP631

Layout Note:

C C

Layout trace < 14000mil

3D3V_S0

B B

Layout Note:

Layout trace < 14000mil

A A

RN2001

1

8

2

7

3

6

4 5

SRN10KJ -6-GP

RN2002

1

8 2 3 4 5

SRN10KJ -6-GP

PCIE_RXN365 PCIE_RXP365 PCIE_TXN365 PCIE_TXP365

S0 power rail CLKREQ#: PCIECLKRQ[2:1]#

RN2018

1 2 3

SRN10KJ -5-GP

CLK_PCIE_ WLAN_REQ#65

PCIE_CLK_ LAN_REQ#

7

6

CLK_PCIE_ WLAN_REQ#

4

CLK_PCIE_ REQ1#

CLK_PCIE_ WLAN#65 CLK_PCIE_ WLAN65

C2005 S CD1U10V2KX-5G PC20 05 SCD1U10V2 KX-5GP C2006 S CD1U10V2KX-5G PC20 06 SCD1U10V2 KX-5GP

C2001 S CD1U10V2KX-5G PC20 01 SCD1U10V2 KX-5GP C2002 S CD1U10V2KX-5G PC20 02 SCD1U10V2 KX-5GP

Layout Note:

CLKOUT termination place close to PCH <500mil

CLK_PCIE_ LAN#31 CLK_PCIE_ LAN3 1

PCIE_CLK_ LAN_REQ#31

5

PCIE_CLK_ REQ6#

PCIE_CLK_ REQ3# PCIE_CLK_ REQ0# PCIE_CLK_ REQ4#

EC_SW I#

CLK_PCIE_ REQ7#

CLK_PEG _B_REQ#

1 2 1 2

S5 power rail CLKREQ#: PCIECLKRQ[0]# PCIECLKRQ[7:3]#

PCIE_CLK_RQ6# PCIE_CLK_RQ3# PCIE_CLK_RQ0# PCIE_CLK_RQ4#

PCIE_CLK_RQ5# PCIE_CLK_RQ7#

PCIE_CLK_RQ2# PCIE_CLK_RQ1#

R1918

1 2

R1922

0R0402-P AD

1 2

0R0402-P AD

R1923

1 2

R1928

0R0402-P AD

1 2

0R0402-P AD

PCIE_TXN3 _C PCIE_TXP3 _C

PCH_TXN _LAN_RXN6 PCH_TXP _LAN_RXP6

PCIE_CLK_ REQ0#

CLK_PCIE_ REQ1#

CLK_PCH _SRC2_N CLK_PCH _SRC2_P

PCIE_CLK_ REQ3#

PCIE_CLK_ REQ4#

CLK_PCH _SRC5_N CLK_PCH _SRC5_P

CLK_PEG _B_REQ#

PCIE_CLK_ REQ6#

CLK_PCIE_ REQ7#

4

PCH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0#/GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1#/GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2#/GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4#/GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5#/GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ#/GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6#/GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7#/GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

PANTHER -GP-NF

71.PANTH.00U

4

NC

WLAN

NC

LAN

NC

PCI-E*

NC

CLOCKS

WLAN CLK

NC

LAN CLK

NC

SMBALERT#/GPIO11

SMBDATA

SML0ALERT#/GPIO60

SMBUSController

SML1ALERT#/PCHHOT#/GPIO74

Link

PEG_A_CLKRQ#/GPIO47

FLEX CLOCKS

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

2 OF 10

SMBCLK

SML0CLK

CL_CLK1

3

E12

H14

C9

A12

C8

G12

C13

E14

M16

M7

T11

P10

M10

AB37 AB38

AV22 AU22

AM12 AM13

BF18 BE18

BJ30 BG30

G24 E24

AK7 AK5

K45

H45

V47 V49

XCLK_RC OMP

Y47

JTAG_TC K

K43

CARD_RE ADER_48M

F47

CLK_27M _VGA_R

H47

BOARD_ID1

K49

3

EC_SW I#

SMB_CLK

SMB_DAT A

DRAMRST _CNTRL_PCH

SML0_CL K

SML0_DA TA

PCH_GPIO7 4

SML1_CL K

SML1_DA TA

CLKOUT_ PEG_A_N CLKOUT_ PEG_A_P

CLKOUT_ DMI_N CLKOUT_ DMI_P

CLK_BUF _EXP_N CLK_BUF _EXP_P

CLK_BUF _CPYCLK_N CLK_BUF _CPYCLK_P

CLK_BUF _DOT96_N CLK_BUF _DOT96_P

CLK_BUF _CKSSCD_N CLK_BUF _CKSSCD_P

CLK_BUF _REF14

CLK_PCI_F B

XTAL25_ IN XTAL25_ OUT

R1930

R1930 R1931

R1931

1 2

EC_SW I# 27

SML1_CL K 27,28,86

SML1_DA TA 27,28,86

RN2016

1 2 3

OPS

SRN0J-6-G P

1 2

0R0402-P AD

1 2

0R0402-P AD

RN2019

SRN10KJ -5-GP

RN2008

SRN10KJ -5-GP

RN2020

SRN10KJ -5-GP

RN2021

SRN10KJ -5-GP

R2008

10KR2J-3 -GP

CLK_PCI_F B 18

R2007

90D9R2F -1-GP

1

2

DRAMRST _CNTRL_PCH 37

Layout Note:

Can Place Far away PCH

Layout Note:

CLKOUT termination place close to PCH <500mil

PEG_CLK REQ# 83

4

2 3 1

1 2

+VCCDIFFC LKN

TP2004TP2004

TP2005TP2005

TP2006TP2006

CLK_PCIE_ VGA# 83 CLK_PCIE_ VGA 83

CLK_EXP _N 5 CLK_EXP _P 5

4

Layout Note:

1500mil < Layout trace < 10000mil

BOARD_ID1 18

2

SMB_CLK SMB_DAT A

SML0_DA TA SML0_CL K SML1_CL K SML1_DA TA

PCH_GPIO7 4

DRAMRST _CNTRL_PCH

3D3V_S0

SMB_DAT A

SMB_CLK

XTAL25_ IN

XTAL25_ OUT

PEG_CLK REQ#

1

3D3V_S5

RN2003

1

4

1 2 3 4 5

R2011 10K R2J-3-GPR2011 10K R2J-3-GP

1 2

R2009 1 KR2J-1-GPR2 009 1KR2J-1-GP

RN2007

2 3 1

SRN2K2J -1-GP

6

5

Q2001

Q2001 2N7002K DW-GP

2N7002K DW-GP

R2006

1M1R2J-G P

1 2

3D3V_S5

12

R2004

R2004 10KR2J-3 -GP

10KR2J-3 -GP

SRN2K2J -1-GP

23

RN2004

8

SRN2K2J -2-GP

7 6

4

1

2

34

X2001

2 3

82.30020.D41

2nd = 82.30020.G61

BOARD_ID222

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

SC15P50 V2JN-2-GP

41

XTAL-25M HZ-155-GP

PCH_SMB DATA 14,15,6 9

PCH_SMB CLK 14,1 5,69

1 2

C2008

C2007

SC15P50 V2JN-2-GP

1 2

3D3V_S0

12

R2014

R2014 10KR2J-3 -GP

10KR2J-3 -GP

OPS

12

R2010

R2010 10KR2J-3 -GP

10KR2J-3 -GP

UMA

BIOS UMA/DIS St rap pin

BOARD_ID1

PX(AMD)

DIS

UMA

M14 DIS

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Date: Sheet of

Optimus(NV)

PCH (PCI-E/SMBUS/CLOCK/CL)

OAK14 Chief River DIS

Wednesd ay, September 05, 20 12

OAK14 Chief River DIS

0 0

0

1

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

BOARD_ID2

20 10 5

1

0

1

A00

5

4

3

2

1

SSID = PCH

D D

84.07002.I31

2nd = 84.2N702.W31

3rd = 84.2N702.J31

RTCRST_ ON27

R2122

10KR2J-3 -GP

C C

12

Layout Note:

Flash Descriptor Security Overide/ Intel ME Debug Mode

HDA_SDOUT

Place at the separated point

3D3V_S0

R2106 1 KR2J-1-GP

B B

HDA_SPKR

+3VS_+1 .5VS_HDA_IO

R2103 1KR 2J-1-GPR2 103 1KR2J-1-GP

1 2

HDA_SYNC

HDA_COD EC_SYNC29

A A

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.

5

G

Low = Default High = Enable

1 2

DY

No Reboot Strap

Low = Default High = No Reboot

PLL ODVR VOLTAGE

Low = 1.8V High = 1.5V

R2124

33R2J-2-G P

*

12

DS

*

RTC_AUX _S5

R2127 2 0KR2F-L-GPR2127 20KR2F-L-GP

1 2

R2128 2 0KR2F-L-GPR2128 20KR2F-L-GP

1 2

SC1U6D3 V2KX-GP

Q2102

Q2102 2N7002B K-GP

2N7002B K-GP

*

HDA_SPK R

HDA_SYNC

12

C2103

HDA_COD EC_BITCLK2 9

HDA_COD EC_RST#29

Layout Note:

Place close together.

Layout Note:

HDA_SDO and HDA_BCLK must be length matched to within 500 m ils

HDA_COD EC_SDOUT2 9

ME_UNLO CK27

RUN_ENA BLE36,37

R2117

R2117 1M1R2J-G P

1M1R2J-G P

1 2

4

12

C2104

SC1U6D3V2KX-GP

RTC_AUX _S5

HDA_SPK R29

HDA_SDIN029

3D3V_S5

R2111 51R 2J-2-GP

R2118 210 R2F-L-GP

R2119 210 R2F-L-GP

R2120 210 R2F-L-GP

SPI_CLK_R27,60

SPI_CS0#_ R27,60

SPI_SI_R27,60

SPI_SO_R27,60

G

DS

Q2101

Q2101 2N7002B K-GP

2N7002B K-GP

84.07002.I31

2nd = 84.2N702.W31

3rd = 84.2N702.J31

Integrated SUS 1V VRM Enable

INTVRMEN

1 2

R2107

1KR2J-1-G P

1 2

DY

1 2

DY

1 2

DY

1 2

DY

HDA_SYNCHDA_COD EC_SYNC_R

R2126

33R2J-2-G P

R2125

33R2J-2-G P

R2123

R2123 33R2J-2-G P

33R2J-2-G P

Low = External VRs High = Internal VRs

R2104

12

1M1R2J-G P

1 2

R2105

R2105 330KR2J -L1-GP

330KR2J -L1-GP

HDA_BITCL K

12

HDA_RST #

12

TP2101TP2101

TP2102TP2102

1 2

R2108 3 3R2J-2-GPR2108 3 3R2J-2-GP

1 2

R2109 33 R2J-2-GPR2109 33R2J -2-GP

1 2

R2110 33 R2J-2-GPR2110 33R2J -2-GP

1 2

R2115 33 R2J-2-GPR2115 33R2J -2-GP

SPI_CLK_R HDA_COD EC_RST#

EC2104

EC2104 SC10P50 V2JN-4GP

SC10P50 V2JN-4GP

DY

1 2

HDA_COD EC_BITCLK HDA_CODEC_S DOUT

EC2102

DY

SC4D7P5 0V2CN-1GP

1 2

*

PCH1A

RTC_X1

RTC_X2

RTC_RST #

SRTC_RS T#

SM_INTRUD ER#

PCH_INTVR MEN

HDA_SYNC

HDA_SDO UT

PCH_GPIO3 3

1

PCH_GPIO1 3

1

PCH_JTA G_TCK_BUF

PCH_JTA G_TMS

PCH_JTA G_TDI

PCH_JTA G_TDO

PCH_SPI_C LK

PCH_SPI_C S0#

PCH_SPI_S I

PCH_SPI_S O

reserve for EMI Request

12

EC2105

EC2105 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

DY

EC2103

DY

SC4D7P5 0V2CN-1GP

1 2

3

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN#/GPIO33

N32

HDA_DOCK_RST#/GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER -GP-NF

71.PANTH.00U

Layout Note:

Place near PCH

1 OF 10

LPC_LAD 0_PCH

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATALED#

41

C38

LPC_LAD 1_PCH

A38

LPC_LAD 2_PCH

B37

LPC_LAD 3_PCH

C37

LPC_LFR AME#_PCH

D36

E36 K36

V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

Y10

AB12

AB13

AH1

SATA_LE D#

P3

PCH_GPIO2 1

V14

BBS_BIT0

P1

RTC_X1

RTC_X2

12

C2102

C2102 SC15P50 V2JN-2-GP

SC15P50 V2JN-2-GP

2

Layout Note:

HDD < 6000mil, mSATA < 6000mil, ODD < 12500mil

SATA_CO MP

SATA3_C OMP

RBIAS_SAT A3

INT_SERIRQ PCH_GPIO2 1

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LPC

FWH4/LFRAME#

LDRQ1#/GPIO23

RTCIHDA

SATA 6G

SATA

SATAICOMPO

JTAG

SPI

12

C2101

SC15P50V2JN-2-GP

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATA0GP/GPIO21

SATA1GP/GPIO19

1 2

R2101 1 0MR2J-L-GPR2101 10MR2J-L-GP

X2101

2 3

X-32D768 KHZ-65-GP

82.30001.A41

2nd = 82.30001.841

RN2101 SRN0J-7-GPRN2101 SRN0J-7-GP

1 2 3 4 5

R2136

1 2

0R0402-P AD

KB_DET# 6 9

INT_SERIRQ 27

PCH_RXN _C_HDD_TXN0 56 PCH_RXP _C_HDD_TXP0 56 PCH_TXN _HDD_RXN0 56 PCH_TXP _HDD_RXP0 56

PCH_RXN _C_ODD_TXN4 56 PCH_RXP _C_ODD_TXP4 56 PCH_TXN _ODD_RXN4 56 PCH_TXP _ODD_RXP4 5 6

R2112 37D 4R2F-GPR2112 37D 4R2F-GP

1 2

R2113 49D 9R2F-GPR2113 49D 9R2F-GP

1 2

R2114 750 R2F-GPR2114 750 R2F-GP

1 2

SATA_LE D# 68

R2116 10K R2J-3-GP

1 2

DY

RN2103

1 2 3

SRN10KJ -5-GP

M14 DIS

Title

PCH (SPI/RTC/LPC/SATA/IHDA)

Size Document N umber Rev

Size Document N umber Rev A3

A3

Wednesd ay, September 05, 20 12

Date: Sheet of

LPC_AD0

8

LPC_AD1

7

LPC_AD2

6

LPC_AD3

4

OAK14 Chief River DIS

LPC_AD[3 ..0]

LPC_FRA ME# 27,7 1

HDD1

ODD

1D05V_P CH

Layout Note:

Place close PCH(<500mil)

3D3V_S0

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

LPC_AD[3 ..0] 27,71

21 10 5

A00

5

4

3

2

1

SSID = PCH

6 OF 10

PCH1F

PCH_GPIO0 0

1

12

R2210

R2210 10KR2J-3 -GP

10KR2J-3 -GP

VRAM_2G

1

EC_SMI#

PCH_GPIO6

EC_SCI#

PCH_GPIO0 8

RTC_DET #

PCH_GPIO1 5

SATA_OD D_PRSNT#

DGPU_PW ROK

DBC_EN

PCH_GPIO2 4

PCH_GPIO2 7

PLL_ODV R_EN

PCH_GPIO3 4

PCH_GPIO3 5

PCH_GPIO3 6

PCH_GPIO3 7

PCH_GPIO3 8

DGPU_HO LD_RST#

DGPU_PW R_EN#

PCH_GPIO4 9

VRAM_DE T

EC_SMI#27

3D3V_S0

D D

3D3V_S0

C C

3D3V_S5

B B

3D3V_S0

RN2203

RN2203 SRN10KJ -5-GP

SRN10KJ -5-GP

1 2 3

1 2 3 4 5

R2206

1 2

4

R2201 1 KR2J-1-GP

4

1 2 3

4

RN2205

RN2205 SRN10KJ -5-GP

SRN10KJ -5-GP

4

RN2206

SRN10KJ -6-GP

8 7 6

RN2201

RN2201 SRN10KJ -6-GP

SRN10KJ -6-GP

8 7 6

10KR2J-3 -GP

RN2207

1 23

DY

SRN10KJ -5-GP

12

DY

RN2208 SRN10KJ-5 -GP

1 23

DY

4

RN2209 SRN10KJ-5 -GPRN 2209 SRN1 0KJ-5-GP

RN2202

RN2202 SRN10KJ -5-GP

SRN10KJ -5-GP

4

H_A20GA TE_PCH H_RCIN#

SATA_OD D_PRSNT# PCH_GPIO0 0

PCH_GPIO4 9

PCH_GPIO3 4

PCH_GPIO3 8

DBC_EN

EC_SMI# EC_SCI# PCH_GPIO6 DGPU_PW ROK

RTC_DET #

PCH_GPIO2 4

PCH_GPIO0 8

PCH_GPIO1 5

DGPU_PW R_EN# DGPU_HO LD_RST#

DGPU_PW R_EN#

DGPU_HO LD_RST#

PCH_GPIO3 6

PCH_GPIO3 7

SATA_OD D_PRSNT#56

DGPU_HO LD_RST#83

DGPU_PW R_EN#93

3D3V_S5

VRAM_1G_UMA

EC_SCI#27

RTC_DET #60

DGPU_PW ROK27,92,93

DBC_EN49

TP2209TPAD14 -OP-GP TP2209TPAD14-OP-G P

TP2210TPAD14 -OP-GP TP2210TPAD14-OP-G P

R2208

10KR2J-3 -GP

TP2211TPAD14 -OP-GP TP2211TPAD14-OP-G P

TP2212TPAD14 -OP-GP TP2212TPAD14-OP-G P

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49/TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1#A4

A44

VSS_NCTF_2#A44

A45

VSS_NCTF_3#A45

A46

VSS_NCTF_4#A46

A5

VSS_NCTF_5#A5

A6

VSS_NCTF_6#A6

B3

VSS_NCTF_7#B3

B47

VSS_NCTF_8#B47

BD1

VSS_NCTF_9#BD1

BD49

VSS_NCTF_10#BD49

BE1

VSS_NCTF_11#BE1

BE49

VSS_NCTF_12#BE49

BF1

VSS_NCTF_13#BF1

BF49

VSS_NCTF_14#BF49

PANTHER -GP-NF

71.PANTH.00U

GPIO

NCTF

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,

BD1,BD49,BE1,BE49,BF1,BF49,

BG2,BG48,BH3,BH47,BJ4,BJ44,

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,

D49,E1,E49,F1,F49

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,

BD1,BD49,BE1,BE49,BF1,BF49,

BG2,BG48,BH3,BH47,BJ4,BJ44,

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,

D49,E1,E49,F1,F49

6 OF 10

TACH4/GPIO68

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

VSS_NCTF_15#BG2

VSS_NCTF_16#BG48

VSS_NCTF_17#BH3

VSS_NCTF_18#BH47

VSS_NCTF_19#BJ4

VSS_NCTF_20#BJ44

VSS_NCTF_21#BJ45

VSS_NCTF_22#BJ46

VSS_NCTF_23#BJ5

VSS_NCTF_24#BJ6

VSS_NCTF_25#C2

VSS_NCTF_26#C48

VSS_NCTF_27#D1

VSS_NCTF_28#D49

VSS_NCTF_29#E1

VSS_NCTF_30#E49

VSS_NCTF_31#F1

VSS_NCTF_32#F49

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AY1

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

SATA_OD D_PWRGT

BOARD_ID2

PCH_GPIO7 0

PCH_GPIO7 1

H_A20GA TE_PCH

H_PECI_R

H_RCIN#

H_CPUPW RGD

PCH_THE RMTRIP_R

INIT3_3V#

DF_TVS

PCH_NCT F_BG2

PCH_NCT F_BG48

PCH_NCT F_BH3

PCH_NCT F_BH47

PCH_NCT F_C2PCH_NCT F_B3

PCH_NCT F_C48PCH_NCT F_B47

1

SATA_OD D_PWRGT 56

BOARD_ID2 20

TP2201 TPAD14-OP-G PT P2201 TP AD14-OP-GP

TP2202 TPAD14-OP-G PT P2202 TP AD14-OP-GP

R2205

1 2

0R0402-P AD

R2203 0R2 J-2-GP

1 2

DY

H_RCIN# 27

H_CPUPW RGD 5

R2204 390 R2J-1-GPR2 204 390R2J-1-GP

1 2

TP2213 TPAD14-OP-G PT P2213 TP AD14-OP-GP

Layout Note:

Check these fuor balls are connected firstly, then to GND

TP2203 TPAD14-OP-G PT P2203 TP AD14-OP-GP

1

TP2204 TPAD14-OP-G PT P2204 TP AD14-OP-GP

1

TP2205 TPAD14-OP-G PT P2205 TP AD14-OP-GP

1

TP2206 TPAD14-OP-G PT P2206 TP AD14-OP-GP

1

TP2207 TPAD14-OP-G PT P2207 TP AD14-OP-GP

1

TP2208 TPAD14-OP-G PT P2208 TP AD14-OP-GP

1

H_A20GA TE 27

H_PECI 5,27

R2202 2K2 R2J-2-GP

1 2

DY

R2209

DF_TVS

R2209

1 2

1KR2J-1-G P

VCCP_CP U

1D8V_S0

12

H_THERM TRIP# 5

R2207

R2207 2K2R2J-2 -GP

2K2R2J-2 -GP

H_SNB_IVB # 5

A A

R2212 1 KR2J-1-GP

PLL ON DIE VR E NABLE

GPIO28 (PLL_ODVR_EN)

5

Weakly internal pull up 20k. High - Enable LOW - Disable

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Wednesd ay, September 05, 20 12

Date: Sheet of

4

3

2

Date: Sheet of

PCH (GPIO/CPU)

OAK14 Chief River DIS

Taipei Hsien 221, Taiwan, R.O.C.

22 10 5

1

A00

PLL_ODV R_EN

12

DY

R2212 1 KR2J-1-GP

5

4

3

2

1

SSID = PCH

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

VccIO

VccASW

VccSPI

VccDSW3_3

VccDFTERM

VccRTC

VccSus3_3

VccSusHDA

VccVRM

VccClkDMI

VccSSC

VccDIFFCLKN

VccALVDS

VccTX_LVDS

Refer to chipset EDS V.1.8

R2307

R2306

R2308

3D3V_S0

1D8V_S0

3D3V_S0

1D5V_S0

VCCP_CP U

1D05V_P CH

1D8V_S0

3D3V_S5

7 OF 10

POWER

PCH1G

1D05V_P CH

D D

C C

1D05V_P CH

B B

3D3V_S0

12

1.73A

3.799A

C2305

SC10U6D3V5KX-1GP

0.178A

C2310

SCD1U10V2KX-5GP

DY

12

C2301

DY

SC10U6D3V5KX-1GP

TP2301TP2301

12

C2306

DY

SC1U6D3V2KX-GP

12

C2302

SC1U6D3V2KX-GP

12

C2307

SCD1U10V2KX-5GP

TP2302TP2302

C2303

SC1U6D3V2KX-GP

1D05V_P CH

1

C2308

SCD1U10V2KX-5GP

VCCVRM

1D05V_P CH

1D05VS_ VCC_DMI

12

C2304

SC1U6D3V2KX-GP

VCCAPLL EXP

12

C2309

SC1U6D3V2KX-GP

VCCFDIPLL

1

PCH1G

AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29

AJ23 AJ26 AJ27 AJ29 AJ31

AN19

BJ22

AN16

AN17

AN21

AN26

AN27

AP21

AP23

AP24

AP26

AT24

AN33

AN34

BH29

AP16

BG6

AP17

AU20

PANTHER -GP-NF

71.PANTH.00U

VCCCORE1 VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE5 VCCCORE6 VCCCORE7 VCCCORE8 VCCCORE9 VCCCORE10 VCCCORE11 VCCCORE12 VCCCORE13 VCCCORE14 VCCCORE15 VCCCORE16 VCCCORE17

VCCIO28

VCCAPLLEXP

VCCIO15

VCCIO16

VCCIO17

VCCIO18

VCCIO19

VCCIO20

VCCIO21

VCCIO22

VCCIO23

VCCIO24

VCCIO25

VCCIO26

VCC3_3_3

VCCVRM2

VCCAFDIPLL

VCCIO27

VCCDMI2

POWER

VCC CORE

VCCIO

FDI

CRTLVDS

DMI

DFT / SPI HVCMOS

7 OF 10

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCCTX_LVDS1

VCCTX_LVDS2

VCCTX_LVDS3

VCCTX_LVDS4

VCC3_3_6

VCC3_3_7

VCCVRM3

VCCDMI1

VCCCLKDMI

VCCDFTERM1

VCCDFTERM2

VCCDFTERM3

VCCDFTERM4

VCCSPI

U48

U47

AK36

AK37

AM37

AM38

AP36

AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

12

C2313

DY

+3VS_VC CA_LVDS

+1.8VS_V CCTX_LVDS

12

C2319

C2319 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

VCCVRM

1D05VS_ VCC_DMI

12

C2320

C2320 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

+1.05VS_ VCC_DMI_CCI

12

C2321

C2321 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

12

C2322

C2322 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

12

C2323

C2323 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

0.063A

12

C2314

R2304

0R0603-P AD

SCD1U10V2KX-5GP

SCD01U16V2KX-3GP

SCD1U10V2KX-5GP

0.001A

0.04A

12

C2316

SCD01U16V2KX-3GP

12

C2318

C2317

SC10U6D3V3MX-GP

SCD01U16V2KX-3GP

SC10U6D3V3MX-GP

0.178A

0.147A

0.047A

0.075A

0R0603-P AD

1 2

R2301

0R0603-P AD

1 2

0R0402-P AD

1 2

0R0402-P AD

1 2

0R0402-P AD

1 2

0.002A

0.01A

Voltage(V)

1.05/1.0

5

3.3

1.05

1.1

1.05

3.3

1.8

3.3

1.5

1.05

3.3

1.8

check

Iccmax(A)

0.002

0.001

0.178

0.063

0.075

1.73

0.047

3.799

0.803

0.01

0.001

0.002

6uA

0.065

0.01

0.147

0.075

0.095

0.05

0.001

0.04

A A

5

4

3

2

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Wednesd ay, September 05, 20 12

Date: Sheet of

PCH (POWER1)

OAK14 Chief River DIS

Taipei Hsien 221, Taiwan, R.O.C.

23 10 5

1

A00

5

4

3

2

1

SSID = PCH

VCCACLK

1

3D3V_S5

DCPSUSB YP

1

+V3.3S_V CC_CLKF33

+VCCAPL L_CPY_PCH

1

+VCCSUS 1

1

C2405

SC1U6D3V2KX-GPDYC2405

SC1U6D3V2KX-GP

12

DY

+VCCRTC EXT

VCCVRM

+1.05VS_ VCCA_A_DPL

+1.05VS_ VCCA_B_DPL

+VCCDIFFC LK

+V1.05S_ SSCVCC

+VCCSST

DCPSUS

1

12

C2418

SCD1U10V2KX-5GP

12

C2421

SCD1U10V2KX-5GP

DY

12

DY

C2419

12

0.147A

C2420

12

SC1U6D3V2KX-GPDYC2419

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

C2422

SCD1U10V2KX-5GP

12

SC10U6D3V5KX-1GP

C2411

+VCCDIFFC LKN

C2414

C2415

C2417

C2436

12

TP2401TP2401

TP2402TP2402

TP2403TP2403

TP2404TP2404

C2406

SC1U6D3V2KX-GP

C2406

SC1U6D3V2KX-GP

TP2405TP2405

12

4

3D3V_S5

3D3V_S0

L2401

D D

C C

1D05V_P CH

B B

1D05V_P CH

A A

1D05V_P CH

L2401

1 2

IND-10UH-21 8-GP

68.10050.10Y

2nd = 68.1001E.10N

SC10U6D 3V5KX-1GP

L2402

1 2

IND-10UH-21 8-GP

68.10050.10Y

2nd = 68.1001E.10N

L2403

1 2

IND-10UH-21 8-GP

68.10050.10Y

2nd = 68.1001E.10N

R2403

0R0402-P AD

1 2

R2404

0R0402-P AD

1 2

C2401

+1.05VS_ VCCA_A_DPL

12

C2408

SC10U6D3V3MX-GP

DY

+1.05VS_ VCCA_B_DPL

12

C2409

SC10U6D3V3MX-GP

DY

+VCCDIFFC LK

12

C2412

SC1U6D3 V2KX-GP

0.095A

+V1.05S_ SSCVCC

12

C2413

SC1U6D3 V2KX-GP

5

+V3.3S_V CC_CLKF33

12

DY

0.075A

12

0.075A

12

1D05V_P CH

0.001A

12

C2402

C2402 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

1D05V_P CH

C2407

C2407 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

C2410

C2410 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

0.05A

VCCP_CP U

RTC_AUX _S5

SCD1U10 V2KX-5GP

1D05V_P CH

0.803A

SC10U6D3V5KX-1GP

C2403

12

DY

SCD1U10 V2KX-5GP

R2412

0R0603-P AD

1 2

SC1U6D3 V2KX-GP

SCD1U10 V2KX-5GP

SC4D7U6 D3V3KX-GP

SC1U6D3 V2KX-GP

C2416

12

0.002A

6uA

C2404

PCH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3_5

BH23

VCCAPLLDMI2

AL29

VCCIO14

AL24

DCPSUS3

AA19

VCCASW1

AA21

VCCASW2

AA24

VCCASW3

AA26

VCCASW4

AA27

VCCASW5

AA29

VCCASW6

AA31

VCCASW7

AC26

VCCASW8

AC27

VCCASW9

AC29

VCCASW10

AC31

VCCASW11

AD29

VCCASW12

AD31

VCCASW13

W21

VCCASW14

W23

VCCASW15

W24

VCCASW16

W26

VCCASW17

W29

VCCASW18

W31

VCCASW19

W33

VCCASW20

N16

DCPRTC

Y49

VCCVRM4

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO7

AF33

VCCDIFFCLKN1

AF34

VCCDIFFCLKN2

AG34

VCCDIFFCLKN3

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS1

V19

DCPSUS2

BJ8

V_PROC_IO

A22

VCCRTC

PANTHER -GP-NF

71.PANTH.00U

POWER

Clock and Miscellaneous

CPURTC

3

PCI/GPIO/LPCMISC

SATA USB

HDA

10 OF 10

N26

VCCIO29

P26

VCCIO30

P28

VCCIO31

T27

VCCIO32

T29

VCCIO33

VCCSUS3_3_7

VCCSUS3_3_8

VCCSUS3_3_9

VCCSUS3_3_10

VCCSUS3_3_6

V5REF_SUS

VCCSUS3_3_1

VCCSUS3_3_2

VCCSUS3_3_3

VCCSUS3_3_4

VCCSUS3_3_5

VCCAPLLSATA

VCCASW22

VCCASW23

VCCASW21

VCCSUSHDA

T23

T24

V23

V24

P24

T26

VCCIO34

M26

AN23

DCPSUS4

AN24

P34

V5REF

N20

N22

P20

P22

AA16

VCC3_3_1

W16

VCC3_3_8

T34

VCC3_3_4

AJ2

VCC3_3_2

AF13

VCCIO5

AH13

VCCIO12

AH14

VCCIO13

AF14

VCCIO6

AK1

AF11

VCCVRM1

AC16

VCCIO2

AC17

VCCIO3

AD17

VCCIO4

1D05V_P CH

T21

V21

T19

P32

SCD1U10 V2KX-5GP

VCCSUSHDA need to be at eithe r 3.3V or 1.5V. All the CODEC I /O Voltages ne ed to be at the same level either 3. 3 V or 1.5 V.

12

C2424

C2424 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

1D05V_P CH

+5VA_PC H_VCC5REFSUS

+VCCA_U SBSUS

3D3V_S5

+5VS_PC H_VCC5REF

SC1U6D3 V2KX-GP

12

C2431

C2431 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

SC1U6D3 V2KX-GP

+V1.05S_ VCCAPLL_SATA 3

VCCVRM

SC1U6D3 V2KX-GP

+3VS_+1 .5VS_HDA_IO

0.01A

12

C2433

C2438

C2438 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

12

DY

12

C2428

3D3V_S0

12

C2429

12

C2432

DY

12

C2435

C2425

C2425 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

C2437

C2437 SC1U10V 2KX-1GP

SC1U10V 2KX-1GP

1

R2402

0R0402-P AD

1 2

2

0.065A

0.001A

TP2406TP2406

1D05V_P CH

3D3V_S5

(0.1uFx1)

3D3V_S5

3D3V_S0

12

3D3V_S0

1D05V_P CH

3D3V_S5

21

D2401

D2401 CH751H-4 0PT-GP

12

3D3V_S0

21

12

CH751H-4 0PT-GP

D2402

D2402 CH751H-4 0PT-GP

CH751H-4 0PT-GP

R2408

1 2

10R2J-2-G P

C2426

C2426 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

1 2

10R2J-2-G P

C2427

C2427 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

83.R0304.A8F

2nd = 83.R2004.B8F

83.R0304.A8F

2nd = 83.R2004.B8F

Voltage Rail

C2430

C2430 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

VccIO

VccASW

VccSPI

VccDSW3_3

VccDFTERM

VccRTC

VccSus3_3

VccSusHDA

VccVRM

VccClkDMI

VccSSC

VccDIFFCLKN

VccALVDS

VccTX_LVDS

M14 DIS

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Date: Sheet of

Refer to chipset EDS V.1.8

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (POWER2)

DNE40 14 CR DIS

Wednesd ay, September 05, 20 12

DNE40 14 CR DIS

R2407

Voltage(V)

1.05/1.0

1

5V_S5

5V_S0

Iccmax(A)

5

3.3

1.05

1.1

1.05

3.3

1.8

3.3

1.5

1.05

3.3

1.8

24 10 5

0.002

0.001

0.178

0.063

0.075

1.73

0.047

3.799

0.803

0.01

0.001

0.002

6uA

0.065

0.01

0.147

0.075

0.095

0.05

0.001

0.04

A00

5

4

3

2

1

SSID = PCH

D D

C C

B B

A A

5

PCH1H

H5

VSS0

AA17

VSS1

AA2

VSS2

AA3

VSS3

AA33

VSS4

AA34

VSS5

AB11

VSS6

AB14

VSS7

AB39

VSS8

AB4

VSS9

AB43

VSS10

AB5

VSS11

AB7

VSS12

AC19

VSS13

AC2

VSS14

AC21

VSS15

AC24

VSS16

AC33

VSS17

AC34

VSS18

AC48

VSS19

AD10

VSS20

AD11

VSS21

AD12

VSS22

AD13

VSS23

AD19

VSS24

AD24

VSS25

AD26

VSS26

AD27

VSS27

AD33

VSS28

AD34

VSS29

AD36

VSS30

AD37

VSS31

AD38

VSS32

AD39

VSS33

AD4

VSS34

AD40

VSS35

AD42

VSS36

AD43

VSS37

AD45

VSS38

AD46

VSS39

AD8

VSS40

AE2

VSS41

AE3

VSS42

AF10

VSS43

AF12

VSS44

AD14

VSS45

AD16

VSS46

AF16

VSS47

AF19

VSS48

AF24

VSS49

AF26

VSS50

AF27

VSS51

AF29

VSS52

AF31

VSS53

AF38

VSS54

AF4

VSS55

AF42

VSS56

AF46

VSS57

AF5

VSS58

AF7

VSS59

AF8

VSS60

AG19

VSS61

AG2

VSS62

AG31

VSS63

AG48

VSS64

AH11

VSS65

AH3

VSS66

AH36

VSS67

AH39

VSS68

AH40

VSS69

AH42

VSS70

AH46

VSS71

AH7

VSS72

AJ19

VSS73

AJ21

VSS74

AJ24

VSS75

AJ33

VSS76

AJ34

VSS77

AK12

VSS78

AK3

VSS79

PANTHER -GP-NF

71.PANTH.00U

8 OF 10

VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

4

PCH1I

AY4

VSS159

AY42

VSS160

AY46

VSS161

AY8

VSS162

B11

VSS163

B15

VSS164

B19

VSS165

B23

VSS166

B27

VSS167

B31

VSS168

B35

VSS169

B39

VSS170

B7

VSS171

F45

VSS172

BB12

VSS173

BB16

VSS174

BB20

VSS175

BB22

VSS176

BB24

VSS177

BB28

VSS178

BB30

VSS179

BB38

VSS180

BB4

VSS181

BB46

VSS182

BC14

VSS183

BC18

VSS184

BC2

VSS185

BC22

VSS186

BC26

VSS187

BC32

VSS188

BC34

VSS189

BC36

VSS190

BC40

VSS191

BC42

VSS192

BC48

VSS193

BD46

VSS194

BD5

VSS195

BE22

VSS196

BE26

VSS197

BE40

VSS198

BF10

VSS199

BF12

VSS200

BF16

VSS201

BF20

VSS202

BF22

VSS203

BF24

VSS204

BF26

VSS205

BF28

VSS206

BD3

VSS207

BF30

VSS208

BF38

VSS209

BF40

VSS210

BF8

VSS211

BG17

VSS212

BG21

VSS213

BG33

VSS214

BG44

VSS215

BG8

VSS216

BH11

VSS217

BH15

VSS218

BH17

VSS219

BH19

VSS220

H10

VSS221

BH27

VSS222

BH31

VSS223

BH33

VSS224

BH35

VSS225

BH39

VSS226

BH43

VSS227

BH7

VSS228

D3

VSS229

D12

VSS230

D16

VSS231

D18

VSS232

D22

VSS233

D24

VSS234

D26

VSS235

D30

VSS236

D32

VSS237

D34

VSS238

D38

VSS239

D42

VSS240

D8

VSS241

E18

VSS242

E26

VSS243

G18

VSS244

G20

VSS245

G26

VSS246

G28

VSS247

G36

VSS248

G48

VSS249

H12

VSS250

H18

VSS251

H22

VSS252

H24

VSS253

H26

VSS254

H30

VSS255

H32

VSS256

H34

VSS257

F3

VSS258

PANTHER -GP-NF

71.PANTH.00U

3

9 OF 10

VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS328 VSS329 VSS330 VSS331 VSS333 VSS334 VSS335 VSS337 VSS338 VSS340 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Wednesd ay, September 05, 20 12

Date: Sheet of

2

Date: Sheet of

PCH (VSS)

OAK14 Chief River DIS

Taipei Hsien 221, Taiwan, R.O.C.

25 10 5

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Wednesd ay, September 05, 20 12

Date: Sheet of

Reserved

OAK14 Chief River DIS

Taipei Hsien 221, Taiwan, R.O.C.

26 10 5

1

A00

SSID = KBC

3D3V_AUX_KBC

1 2

12

D D

3D3V_AUX_KBC

12

Ins

12

Vos

Need very close to EC

R2771

R2771 2D2R3-1-U- GP

2D2R3-1-U- GP

12

C2704

C2701

SC2D2U10V3KX-1GP

R2737

R2737 100KR2J-1-GP

100KR2J-1-GP

SERIES_ID

R2738

R2738 100KR2J-1-GP

100KR2J-1-GP

Layout Note:

R2702

0R0603-PAD

1 2

12

DY

SCD1U10V2KX-5GP

C C

5

VBAT

VGA_THRM

EC_SPI_CS#_C EC_SPI_CLK_C EC_SPI_DI_C EC_SPI_DO_C

3D3V_AUX_KBC _VCC

U2701A

VCC119VCC246VCC376VCC488VCC5

104

VREF

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

GPIO93/AD3

108

GPIO5/AD4

96

GPIO4/AD5

95

GPIO3/AD6

94

GPIO7/AD7

101

GPIO94/DA0

105

GPIO95/DA1

106

GPIO96/DA2

107

GPIO97/DA3

79

GPIO02

6

GPIO24

109

GPIO30/F_WP#

14

GPIO34/CIRRXL

15

GPIO36

80

GPIO41/F_WP#

17

GPIO42/TCK

20

GPIO43/TMS

21

GPIO44/TDI

26

GPIO51/N2TCK

123

GPIO67N2TMS

82

GPIO75

83

GPIO76

84

GPIO77

90

F_CS0#

92

F_SCK

86

F_SDI&F_SDIO1

87

F_SDIO&F_SDIO0

91

GPIO81/F_WP#

117

GPIO20/TA2/IOX_DIN_DIO

112

GP/I/O84/IOX_SCLK/XORTR#

110

GPO82/IOX_LDSH/TEST#

NPCE885PA0DX -GP

115

GND118GND245GND378GND489GND5

12

C2705

SCD1U10V2KX-5GP

EC_AGND

BATLOW#19

SPI_CS0#_R21,60

SPI_CLK_R21,60

SPI_SO_R21 ,60 SPI_SI_R21,60

CARD_W PAN_OUT#65

12

C2706

C2707

DY

SCD1U10V2KX-5GP

C2714 SCD1U10V2KX- 5GPC2714 SCD1U10V 2KX-5GP

1 2

AD_IA40

PSID_EC38

FAN1_DAC28

AD_IA_HW40

IMVP_PWRGD36,42

R2793 0R 2J-2-GP

1 2

DY

CAP_LED#69

S5_ENABLE36

BATT_WH ITE_LED#68

BAT_IN#39

LID_CLOSE#70

RSMRST#_KBC19

PM_SLP_S4#19,46 DGPU_PW ROK22,92,93

WIFI_RF_EN65 BLUETOOTH _EN65 S0_PWR_GO OD19,36

33R2J-2-GP R273633R2J-2-G P R 2736 33R2J-2-GP R271933R2J-2-G P R 2719

PM_PWRBT N#19

AC_PRESENT19,86

USB_PWR _EN#61

TP2720TP2720

C2708

SCD1U10V2KX-5GP

12

DY

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP C2709

C2709

C2710

SC2D2U10V3KX-1GP

EC_AGND

PCB_VER_AD

SERIES_ID

USBCHARG ER_CB0

1

MODEL_ID_DET

BATLOW#_E C ECSMI#_KBC

ECSWI#_KBC

BLUETOOTH _EN PROCHOT _EC

1 2 1 2

R272533R2J-2-GP R272533R2J-2- GP

1 2

R272233R2J-2-GP R272233R2J-2- GP

1 2

EC_GPIO23 High Active

PROCHOT _EC

G

Q2702

2N7002BK-GP

12

R2732

B B

R2732

100KR2J-1-GP

H_PROCHO T#_EC

DS

84.07002.I31

2nd = 84.2N702.W31

3rd = 84.2N702.J31

Power Switch Logic(PSL)

3D3V_AUX_S5

R2704

R2704 330KR2J-L1-GP

330KR2J-L1-GP

R2767

0R0402-PAD

1 2

KBC_PWR BTN#68

AC_IN#40

1 2

R2768

0R0402-PAD

1 2

A A

PSL_IN2#

PSL_IN1#

R2733

0R0402-PAD

1 2

H_PROCHO T# 5,38 ,40,42

12

C2720

C2720 SC47P50V2JN-3G P

SC47P50V2JN-3G P

C502 : check list 1.5

3D3V_AUX_S5

PSL_OUT#

1 2

3D3V_AUX_KBC

1 2

S5_ENABLE

DS

5

4

SCD1U10V2KX- 5GP

102

4

75

114

VDD

VSBY

AVCC

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

GPIO17/SCL1/N2TCK GPIO22/SDA1/N2TMS

PSL_OUT_GPIO71#

GND6

5

116

R2765

1 2

0R0402-PAD

EC_AGND

R2734

R2734 330KR2J-L1-GP

330KR2J-L1-GP

R2735

KBC_ON#_GAT E

1 2

20KR2F-L-GP

R2709

R2709 10KR2J-3-GP

10KR2J-3-GP

G

Q2706

Q2706 2N7002BK-GP

2N7002BK-GP

84.07002.I31

2nd = 84.2N702.W31

3rd = 84.2N702.J31

4

3D3V_S0

12

C2702

DY

3D3V_AUX_S5

EC_VBKUP

1 2

0R0402-PAD

1 0F 2

VBKUP

LRESET#/GPIOF7

LCLK/GPIOF5

LFRAME#/GPIOF6

LAD3/GPIOF4 LAD2/GPIOF3 LAD1/GPIOF2 LAD0/GPIOF1

SERIRQ/GPIOF0

GPIO11/CLKRUN#

GPIO65/SMI#

ECSCI#/GPIO54

GPIO10/LPCPD#

GPIO85/GA20

KBRST#/GPIO86

GPIO27/PSDAT2

GPIO26/PSCLK2

GPIO35/PSDAT1

GPIO37/PSCLK1

GPIO73/SCL2

GPIO74/SDA2

GPIO23/SCL3

GPIO31/SDA3

GPIO47/SCL4

GPIO53/SDA4

PSL_IN2_GPI06# PSL_IN1_GPI70#

VCORF

AGND

103

EC_AGND

C2722

SCD1U10V2KX- 5GP

84.02130.031

2nd = 84.00102.031

3rd = 84.03413.A31

4th = 84.02301.G31

12

C2703

C2703 SC2D2U10V3KX- 1GP

SC2D2U10V3KX- 1GP

RTC_AUX_S5

R2794

C2711

C2711 SC220P50V2KX-3GP

SC220P50V2KX-3GP

1 2

DY

PLT_RST#_EC

7 2 3

LPC_AD3

1

LPC_AD2

128

LPC_AD1

127

LPC_AD0

126 125 8

PANEL_BLEN

9

ECSCI#_KBC

29 124 121 122

27

AD_IA_HW2

25 11 10 71 72

70 69 67 68 119 120 24 28

R2792

1 2

0R0402-PAD

PSL_OUT#

74

PSL_IN2#

93

PSL_IN1#

73

44

Layout Note:

Connect GND and AGND planes via either 0R resistor or connect directly.

3D3V_AUX_S5

1 2

S

G

D

PCB_VER_AD

C2717

SCD1U10V2KX-5GP

R2778

1 2

0R0402-PAD

CLK_PCI_KBC 18

LPC_FRAME# 21,71

INT_SERIRQ 21 PM_CLKRUN #_EC 19

R2761

1 2

0R0402-PAD

BOOST_MODE# 40

H_A20GATE 22 H_RCIN# 22

BLON_OUT 49

AD_IA_HW2 4 0

PWR_CH G_AD_OFF 38

CARD_W LAN_OUT# 65

TPDATA 69 TPCLK 69

BAT_SCL 39,40

BAT_SDA 39,40

SML1_CLK 20,28, 86

SML1_DATA 20,28, 86

RTCRST_O N 21 PM_LAN_ENABLE 31 LCD_TST_EN 49 LCD_TST 49

KBC_VCORF

12

C2712

C2712 SC1U10V3KX-4G P-U

SC1U10V3KX-4G P-U

Layout Note:

Need very close to EC

Q2703

Q2703 DMP2130L-7-GP

DMP2130L-7-GP

3D3V_AUX_KBC

R2791

DY

0R2J-2-GP

1 2

DY

1 2

EC_AGND

PLT_RST# 5,18,31,65,71,83

VBAT

12

A00 0905

R2724

R2724 47KR2F-GP

47KR2F-GP

R2726

R2726 100KR2F-L1-GP

100KR2F-L1-GP

3

PCB VER AD(GPIO91) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

X00 3.0V

A00

Reserved

Reserved 100.0K

Reserved 100.0K 215.0K 1.048V

LPC_AD[3..0] 21,71

L_BKLT_EN 17

<------ TP

<------ BATTERY / CHARGER

<------PCH / eDP

PURE_HW _SHUTDOW N#28,36,86

EC GPIO standard PH/PL

VGA_THRM

R2708 10KR 2J-3-GP

1 2

DY

BLUETOOTH _EN

R2714 10KR 2J-3-GP

1 2

DY

RN2706

RSMRST#_KBC S0_PWR_GO OD

RN2706

4

DY

SRN100KJ-6-G P

3

2

100.0K

100.0KX01

100.0K

VCCP_CPU

3D3V_AUX_S5

12

2nd = 84.03906.F11

EC_AGND

1 23

OVER_CUR RENT_P8#86

CHG_AMBER_L ED#68

PCH_SUSCL K_KBC19

H_PECI5,22

Layout Note:

Need very close to EC

R2705

R2705 10KR2J-3-GP

10KR2J-3-GP

MMBT3906-4-GP

84.T3906.A11

BAT_SCL BAT_SDA

BAT_IN# PCIE_WAKE#

ECRST#

BOOST_MODE#

OVER_CUR RENT_P8#

AC_IN_KBC#

X00 0608

E51_RxD

10.0K

20.0K

47.0K

64.9K

76.8

100.0K

143.0K

174.0K

FAN_TACH 128 PCIE_WAKE#31 PM_SLP_S3#19,36,37,47

PWRLED #68

KBC_BEEP29

AC_IN_KBC#38 WLAN_LED #68

TP2721TP2721

KBC_BKLT49

ME_UNLOCK21

E51_RxD65

E51_TxD65

AMP_MUTE#29

43R2J-GP

1 2 1 2

0R0402-PAD

ECRST#

12

C2715

E

SC1U6D3V2KX- GP

B

Q2701

DY

C

RN2701

4

SRN4K7J-8-G P

RN2708

4

SRN100KJ-6-G P

R2707 10KR2J-3-G PR 2707 10K R2J-3-GP

1 2

R2711 10KR2J-3-G P

1 2

DY

R2716 100KR2J-1-G P

1 2

DY

R2717 100KR2J-1-G PR2717 100KR 2J-1-GP

1 2

R2715 10KR2J-3-G P

1 2

DY

2.75V

2.48V33.0KX02

2.24V100.0K

2.0V

1.87V

1.65VReserved

1.358V

1.204V

OVER_CUR RENT_P8# AC_IN_KBC#

KB_BL_CTRL

1

ECRST#

R2721

R2720

C2716

23 1

1 23

PECI EC_VTT

N13M

MODEL_ID_DET

C2718

31 63 64

32

118

62 65 22 81 66 16

23 113 111

77

30

85

13

12

SCD1U10V2KX-5GP

3D3V_AUX_KBC

3D3V_S0

SCD1U10V2KX-5GP

VBAT

12

DY

U2701B

NPCE885PA0DX -GP

R2712

R2710

R2713

1 2

EC_AGND

GPIO56/TA1 GPIO14/TB1 GPIO1/TB2

GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PWM GPIO32/D_PWM GPIO45/E_PWM GPIO66/G_PWM GPIO33/H_PWM GPIO40/F_PWM

GPIO46/CIRRXM/TRIST# GPIO87/CIRRXM/SIN_CR GP/I/O83/SOUT_CR/TRIST#

GPIO0/EXTCLK GPIO55/CLKOUT/IOX_DIN_DIO

VCC_POR#

PECI VTT

33KR2F-GP

UMA

10KR2F-2-GP

N13P

12

R2739

R2739 100KR2F-L1-GP

100KR2F-L1-GP

20KR2F-L-GP

MODEL_ID_DET(GPIO07)

OAK14_UMA OAK14_DIS_N13P OAK14_DIS_N13M

TBD TBD TBD TBD TBD TBD TBD

2 0F 2

KBSOUT0/GPOB0/JENK#

KBSOUT1/GPIOB1/TCK KBSOUT2/GPIOB2/TMS

KBSOUT3/GPIOB3/TDI

KBSOUT4/GPOB4/JEN0#

KBSOUT5/GPIOB5/TDO

KBSOUT6/GPIOB6/RDY#

KBSOUT7/GPIOB7 KBSOUT8/GPIOC0

KBSOUT9/GPOC1/SDP_VIS# KBSOUT10&P80_CLK/GPIOC2 KBSOUT11&P80_DAT/GPIOC3

KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62

KBSOUT15/GPIO61/XOR_OUT

GPIO60/KBSOUT16 GPIO57/KBSOUT17

KBSIN0/GPIOA0/N2TCK KBSIN1/GPIOA1/N2TMS

KBSIN2/GPIOA2 KBSIN3/GPIOA3 KBSIN4/GPIOA4 KBSIN5/GPIOA5 KBSIN6/GPIOA6 KBSIN7/GPIOA7

EC_SWI#20

EC_SCI#22

EC_SMI#22

PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33

54 55 56 57 58 59 60 61

R2766

0R0402-PAD

1 2

D2702

1

DY

2

BAS16-6-GP

R2764

0R0402-PAD

1 2

1

2

R2723

0R0402-PAD

1 2

1

2

M14 DIS

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Wednesd ay, September 05, 2012

Date: Sheet of

2

1

100.0K 3.0V

100.0K

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KBC_GPIO57

KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7

D2703

DY

BAS16-6-GP

D2704

DY

BAS16-6-GP

OAK14 Chief River DIS

10.0K(64.10025.6DL)

20.0K(64.20025.6DL)

33.0K(64.33025.6DL)

47.0K(64.47025.6DL)

64.9K(64.64925.6DL)

76.8K(64.76825.6DL)

100.0K(64.10035.6DL)

143.0K(64.14335.6DL)

174.0K(64.17435.6DL)

215.0K(64.21535.6DL)

KCOL[16..0] 69

1

TP2717TP2717

KROW[7..0] 69

ECSWI#_KBC

3

83.00016.K11

2nd = 83.00016.F11

ECSCI#_KBC

3

83.00016.K11

2nd = 83.00016.F11

ECSMI#_KBC

3

83.00016.K11

2nd = 83.00016.F11

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

KBC Nuvoton NPCE885

27 105

1

2.75V

2.48V

2.24V

2.0V

1.87V

1.65V

1.358V

1.204V

1.048V

A00

5

SSID = Thermal

Thermal sensor NCT7718W

4

3D3V_S0

RN2801

2 3 1

SRN2K2J -1-GP

4

3

2

1

Fan controller NCT3940S-A

1

8 7 6 5

ALERT#

T_CRIT#

6

2

5

34

Q2804

Q2804 2N7002K DW-GP

2N7002K DW-GP

THM_SML 1_CLK THM_SML 1_DATA

ALERT#

12

C2808

DY

R5

R2815 18K 7R2F-GPR2815 1 8K7R2F-GP

1 2

R2814 2KR 2F-3-GPR2814 2KR 2F-3-GP

1 2

DY

SCD1U10V2KX-5GP

D D

R2808

DY

NTC-100K -8-GP

C C

DY

3D3V_S0

12

2ND = 84.03904.P11

3

84.03904.L06

PMBS390 4-1-GP

2

Q2801

12

SC10U6D3V3MX-GP

12

DY

1

C2802

C2805

SCD1U10V2KX-5GP

NCT7718 _DXP

C2806

C2806 SC470P5 0V2KX-3GP

SC470P5 0V2KX-3GP

NCT7718 _DXN

2.System Sensor, Put on palm rest

0R0402-P AD

THERM_S YS_SHDN#

0R0402-P AD

1 2

12

C2807

C2807 SC2200P 50V2KX-2GP

SC2200P 50V2KX-2GP

R2813

T_CRIT#

SML1_DA TA20,27,86

SML1_CL K20,27,8 6

U2801

1

VDD

2

D+

3

DT_CRIT#4GND

NCT7718 W-GP

74.07718.0B9

SCL SDA

ALERT#

THM_SML 1_DATA

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

THM_SML 1_CLK

12

Reserved for

C2812

signal quality improvement.

SCD1U10V2KX-5GP

3D3V_S0

C2803

SC4D7U6 D3V3KX-GP

5V_S0

U2802

R2802

1 2

DY

0R2J-2-GP

5V_S0

FAN1_DA C27

12

C2804

C2804 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

For linear FAN

FAN_VCC

*Layout* 10 mil

FON#

U2802

1

FON#

GND

2

VIN

GND

3

VOUT

GND

VSET4GND

NCT3940 S-A-GP

74.03940.A71

8 7 6 5

X02 0730 change main source

R7

3D3V_S0

R2820

Layout notice : Both DXN and DX P routing 10 m il trace width and 10 mil spacin g. and route ha s to be away f rom the high no ise area. Put the C2807 2 200pF to close the NCT7718W

B B

FAN_TAC H127

R2820 10KR2J-3 -GP

10KR2J-3 -GP

1 2

0R0402-P AD

1 2

R2807

FAN_TAC H1_C

*Layout* 15 mil

3D3V_S0

Q2802

Q2802 2N7002B K-GP

2N7002B K-GP

THERM_S YS_SHDN#

84.07002.I31

2nd = 84.2N702.W31

3rd = 84.2N702.J31

12

D S

G

PURE_HW _SHUTDOW N#27,36,86

C2811

SCD1U10 V2KX-5GP

DY

12

R2809

R2809 100KR2J -1-GP

100KR2J -1-GP

AFTP280 2AFTP2802 AFTP280 1AFTP2801

C2809

SC4D7U6 D3V3KX-GP

FAN_TAC H1_C

1

FAN_VCC

1

21

12

DY

83.R5003.C8F

2nd = 83.R5003.G8H

3rd = 83.R5003.H8H

4th = 83.5R003.08F

Fan Connecter

D2802

AFTP280 3AFTP2803

CH551H-30PT-GP

DY

FAN_VCC

12

C2810

SC2200P50V2KX-2GP

DY

1

12

EC2801

SCD1U16V2KX-3GP

FAN1

5 3 2

1

4

ETY-CON3-8-GP

20.F1841.003

3D3V_S0

A A

5

4

3

2

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Thermal NCT7718W/Fan Controllor P2793

Size Document N umber Rev

Size Document N umber Rev A3

A3

OAK14 Chief River DIS

Wednesd ay, September 05, 20 12

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

28 10 5

1

A00

5

4

3

2

1

SSID = AUDIO

HV mode : performance up , chip power consumption up

3D3V_S0 +3V_AVD D

D D

C C

AUD_AGN D

25mA

R2906 0R0 402-PADR2906 0R0402-PA D

1 2

60mA

5V_S0 +5V_PV DD

R2912

0R0603-P AD

1 2

R2913

0R0603-P AD

1 2

Layout Note:

R2908 0R0 603-PADR2908 0R0603-PA D

1 2

R2909 0R0 603-PADR2909 0R0603-PA D

1 2

R2910 0R0 603-PADR2910 0R0603-PA D

1 2

Layout Note:

Tied at point only under Codec or near the Codec

C2920

C2920 SC4D7U6 D3V3KX-GP

SC4D7U6 D3V3KX-GP

1 2

close to pin 36

C2904

C2905

12

SCD1U10V2KX-5GP

SC10U6D3V3MX-GP

Layout Note:

Close PIN41

Close PIN46

LV mode : performance down , chip power consumption down

3D3V_S0

R2902 0 R2J-2-GP

1 2

DY

1D5V_S0

DY

R2903 0 R0402-PADR2903 0R040 2-PAD

1 2

close to pin 40

C2907

C2906

12

SCD1U10V2KX-5GP

SC10U6D3V3MX-GP

Analog

AUD_AGN D

DigiTal

AMP_MUT E#27

83.R0304.A8F

2nd = 83.R2004.B8F

+3V_1D5 V_AVDD

12

C2903

SC4D7U6 D3V3KX-GP

AUD_AGN D

AUD_SPK _L+58

AUD_SPK _L-58 AUD_SPK _R-5 8 AUD_SPK _R+58

D2901C H751H-40PT-GP

21

1 2

DY

R2921 0R 2J-2-GP

COMBO-GP I58

3D3V_S0

1 2

10KR2J-3 -GP

1 2

1KR2J-1-G P

SC1U10V 2KX-1GP

C2901SC10U6D3V 3MX-GP C 2901SC10U6D 3V3MX-GP

12

+3V_1D5 V_AVDD

DY

R2923

DY

R2918

C2921

+5V_PVD D

ALC3221 : 71.03221.A03

Azalia I/F EMI

ER2902

ER2902 47R2J-2-G P

47R2J-2-G P

PCH_AZ_ CODEC_SDOUT1HD A_CODEC_SDOUT

1 2

DY

B B

HDA_COD EC_BITCLK

DY

HDA_COD EC_BITCLK_C

12

DY

ER2901

ER2901 47R2J-2-G P

47R2J-2-G P

EC2924

SCD1U10 V2KX-5GP

1 2

DY

1 2

DY

EC2922

SC22P50 V2JN-4GP

DMIC: > 5mil and keep out the analog signal

R2904

close to pin 3

DMIC_CLK

C2919

SC22P50 V2JN-4GP

DMIC_DATA49 DMIC_CLK49

HDA_COD EC_SDOUT2 1

HDA_COD EC_BITCLK2 1

1 2

HDA_SDIN021

HDA_COD EC_SYNC21 HDA_COD EC_RST#21

R2904 R2905

R2905

AUD_HP1 _JACK_L58 AUD_HP1 _JACK_R58

12

CBP

LDO2_CA P

AUD_SPK _L+ AUD_SPK _LAUD_SPK _RAUD_SPK _R+

EAPD#

C2909

1 2 1 2

R2907

1 2

33R2J-2-G P

MIC2-VREFO58

U2901

37 38 39 40 41 42 43 44 45 46 47 48 49

ALC3221 -CG-GP

12

C2908

SC4D7U6D3V3KX-GP

DMIC_DATA _R

0R2J-2-GP

HDA_COD EC_SDIN0

HDA_COD EC_SYNC HDA_COD EC_RST#

CBP AVSS2 LDO2_CAP AVDD2 PVDD1 SPK_L+ SPK_LSPK_RSPK_R+ PVDD2 PDB SPDIFO/GPIO2 GND

12

SCD1U10V2KX-5GP

DMIC_CLK_ R

AUD_EAP D#

12

+3V_AVDD

CBN

CPVEE

34

35

36

CBN

CPVDD

DVDD1GPIO0/DMIC_DATA2GPIO1/DMIC_CLK3DVSS4SDATA_OUT5BIT_CLK6LDO3_CAP7SDATA_IN8DVDD_IO9SYNC10RESET#11PCBEEP

AUD_AGND

C2917

SC2D2U6D3V2MX-GP

12

C2918 SC1U6D3V2KX-GPC2918 SC1U6D3V2KX-GP

AUD_VREF

LDO1_CAP

27

28

29

30

31

32

33

HP_OUT_R

HP_OUT_L

LINE1/MIC1_VREFO-L

MIC2_VREFO

LINE1/MIC1_VREFO-R

LDO3_CAP

12

C2911SC10U6D3V3MX-GP C2911SC10U6D3V3MX-GP

VREF

LDO1_CAP

CPVREF/MIC1_R

MIC_CAP/MIC1_L

SLEEVE/MIC2_R

C2910SCD1U10V2KX-5GP C2910SCD1U10V2KX-5GP

CPVEE

AUD_AGND

C2916

12

SC10U6D3V3MX-GP

25

26

AVSS1

AVDD1

LINE2_L

LINE2_R

LINE1_L

LINE1_R

RING2/MIC2_L

MONO_OUT

JDREF SENSEB SENSEA

71.03221.A03

12

AUD_PC_ BEEP

+5V_AVD D

AUD_AGN D

24 23 22 21 20 19 18 17 16 15 14 13

SCD1U10 V2KX-5GP

12

C2914

C2915

SCD1U10V2KX-5GP

AUD_AGN D

SC4D7U6D3V3KX-GP

SC4D7U6 D3V3KX-GP

RING2_R

JDREF

R2916 2 0KR2F-L-GPR2916 20KR2F-L-GP

AUD_SEN SE_A

3D3V_S03D3V_S0

SB_SPKR _R

1 2

C2912

SC100P5 0V2JN-3GP

KBC_BEE P_R

1 2

C2913

SCD1U10 V2KX-5GP

SC100P5 0V2JN-3GP

R2911

0R0603-P AD

1 2

12

Layout Note:

Place close to Pin 26

C2902

RING2_C

1 2

39K2R2F -L-GP

C2922

C2923

AUD_SEN SECOMBO-GP I

R2917

Layout Note:

Place close to Pin 13

12

R2919

DY

R2919 10KR2J-3 -GP

10KR2J-3 -GP

DY

12

R2920

R2920 10KR2J-3 -GP

10KR2J-3 -GP

DY

5V_S0+5V_AVDD

R2924

1KR2J-1-G P

1 2

R2914

1KR2J-1-G P

R2915

1KR2J-1-G P

AUD_AGN D+5V_PVD D

12

SLEEVE 58

AUD_SEN SE 58

Analog DigiTal

HDA_SPK R 21

KBC_BEE P 27

3D3V_S0

R2922 10 KR2J-3-GP

AMP_MUT E#27

A A

DY

12

AUD_EAP D#

D2902

1

POP

2

BAT54A-7 -F-GP

83.BAT54.V01

5

Depop sound

3

AUD_PD# _C

12

C2950

POP

SC10U6D 3V3MX-GP

R2925

POP

22KR2J-G P

AUD_PD# _C1

12

R2926

R2926 220KR2J -L2-GP

220KR2J -L2-GP

POP

B

Q2901

MMBT390 6-4-GP

84.T3906.A11

2nd = 84.03906.F11

4

E

POP

C

HP_MUTE

3D3V_S0

POP

R2927

R2927 4K7R2J-2 -GP

4K7R2J-2 -GP

12

AUD_AGN D

12

C2949

DY

SC10U6D 3V3MX-GP

AUD_HP1 _JACK_R15 8

AUD_HP1 _JACK_L158

R2928 1 KR2J-1-GP

R2929 1 KR2J-1-GP

POP

3

12

AUD_HP1 _JACK_R1

AUD_HP1 _JACK_L1

HP_MUTE _RC2HP_MUTE _R

HP_MUTE _RC1

84.02043.011

C

B

POP

E

84.02043.011

Q2902

BTD2040 N3S-GP

B

POP

AUD_AGN DAUD_ AGND

C

Q2903

Q2903 BTD2040 N3S-GP

BTD2040 N3S-GP

E

2

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Audio Codec ALC3221

Size Document N umber Rev

A3

Date: Sheet of

Audio Codec ALC3221

OAK14 Chief River DIS

Taipei Hsien 221, Taiwan, R.O.C.

29 10 5Wednesd ay, September 05, 20 12

1

A00

5

D D

4

3

2

1

(Blanking)

C C

B B

A A

5

4

3

2

M14 DIS

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

OAK14 Chief River DIS

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

30 10 5Wednesd ay, September 05, 20 12

A00

Dell 3421 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual