Datasheet Z89304, Z89306, Z89302 Datasheet (ZILOG)

P R E L I M I N A R Y

FEATURES

ROM

Device

Z89302 24 640 12
Z89304 16 640 12
Z89306 12 640 12

Note: * General-Purpose

■

40-Pin DIP Packages

4.75- to 5.25-Volt Operating Range

■

(KB)

RAM*

(Bytes)

Speed

MHz

C

USTOMER

P

ROCUREMENT

S

PECIFICATION

Z89302/04/06

D

IGITAL

■

0

■

Fully Customized Character Set
Character-Control and Closed-Caption Modes

■

■

Keypad User Control

■

TV Tuner Serial Interface

■

Direct Video Signals

T

°

C to +70

ELEVISION

°

C Temperature Range

C

ONTROLLER

1

GENERAL DESCRIPTION

The Z89302/04/06 Digital Television Controllers are
designed to provide complete audio and video control of
television receivers, video recorders, and advanced on­screen display facilities. The Television Controllers feature
a Z89C00 RISC processor core that controls the on-board
peripheral functions and registers using the standard
processor instruction set.

Character attributes can be controlled through two modes:
the on-screen display Character-Control Mode and the
Closed-Caption Mode. The Character-Control Mode
provides access to the full set of attribute controls, allowing
the modification of attributes on a character-by-character
basis. The insertion of control characters permits direction
of other character attributes.

The fully customized 512 character set, formatted in two
256 character banks, can be displayed with a host of
display attributes that include underlining, italics, blinking,
eight foreground/background colors, character position
offset delay, and background transparency.

Serial interfacing with the television tuner is provided
through the tuner serial port. Other serial devices, such as
digital channel tuning adjustments, may be accessed
through the industry-standard I

User control can be monitored through the keypad
scanning port, or the 16-bit remote control capture
register. Receiver functions such as color and volume can
be directly controlled by eight 8-bit pulse width modulated
ports.

The Z89302/04/06 has two internal 12 MHz VCOs that are
referenced to a 32 kHz internal oscillator to provide the
system clock. In Sleep Mode, the controller uses the
32 kHz clock for the system clock to reduce power
consumption. The processor can be suspended by placing
it into STOP Mode when main power is not available for
low-power consumption.

2

C port.

CP96TEL[phone]

Z89302/04/06
Digital Television Controller P R E L I M I N A R Y

GENERAL DESCRIPTION (Continued)

Port 17

Port 00

Capture
IRIN

ADC

ADC0
ADC1
ADC2
ADC3

Port 0

Port 00
Port 01
Port 02

Port 03
Port 04
Port 05
Port 06
Port 07

Port 08
Port 09

Port 0A
Port 0B
Port 0C
Port 0D
Port 0E
Port 0F

PWM

PWM1
PWM2
PWM3
PWM4
PWM5
PWM6

PWM7
PWM8
PWM9

Port1

Port 10
Port 11
Port 12
Port 13
Port 14
Port 15
Port 16

Port 17
Port 18
Port 19

Note: Dotted pin functions
not available on 40-pin device.

I2C

RAM

640 x 16

Address

Data

Control
XTAL1

XTAL2
LPF
HSYNC
VSYNC

Register Addr/Data

OSD

/Reset

CPU

HALFBLNK

ROM Addr

ROM

12K x 16

ROM Data

16K x 16
24K x 16

Figure 1. Z8930X Functional Block Diagram

SCL
SCD

V1
V2
V3

BLANK

Port 01/11
Port 02/12

Port0F

Note: Z89306 has
12K words of ROM.
Z89304 has 16K.
Z89302 has 24K.

2

1

PIN DESCRIPTION

Z89302/04/06

P R E L I M I N A R Y Digital Television Controller

PWM9

IRIN

Port 18/G<0>

Port 00/ADC2

Port 01/I2SSC

Port 02/I2SSD

Port 03

Port 04/ADC4
Port 05/ADC3

Port 06/Counter

Port 07/C Sync

Port 08/R<1>

Port 09

Port 10/R<0>

Port 11/I2MSC

Port 12/I2MSD

Port 13/G<1>

Port 14/B<0>
Port 15/B<1>

Port 16/SCLK

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Z89302
Z89304
Z89306

40-Pin

DIP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

PWM6
PWM5
PWM4

PWM3
PWM2

PWM1
CVI/ADC0

LPF
XTAL2

GND
XTAL1
VCC
/Reset
Port 17/ADC1
VBlank
V1
V2
V3
VSync
HSync

Figure 2. 40-Pin DIP Configuration

3

Z89302/04/06
Digital Television Controller P R E L I M I N A R Y

PIN DESCRIPTIONS

Z89302/03/06/07

Reset

Pin Name Function 40-Pin, Z89302/04/06 Direction

V

CC

+5V 29,– PWR–
GND 0V 31,– PWR–
IRIN Infrared Remote Capture Input 2 I I
ADC[5:0]

4-Bit Analog to Digital

–,9,8,4,27,34 nAI I

Converter Input
PWM9 14-Bit Pulse Width Modulator

1

OD/O

Output
PWM[8:1]

8-Bit Pulse Width Modulator

–,–,40,39,38

OD/O

Output
Port0[F:0]

Bit Programmable Input/Output

–,–,–,–,–,–,13,12,11,10,9,8,7,6,5,4 B I

Ports
Port1[9:0]

Bit Programmable Input/Output

–,3,27,20,19,18,17,16,15,14 B I

Ports
SCL
SCD

b

c

2

I

C Clock I/O

2

I

C Data I/O

5 or 15 BOD

6 or 16 BOD
XTAL1 Crystal Oscillator Input 30 AI I
XTAL2 Crystam Oscillator Output 32 AO O
LPF Loop Filter 33 AB O
HSYNC H_Sync 21 B I
VSYNC V_Sync 22 B I
/RESET Device Reset 28 I I
V[3:1] OSD Video Output (Typically

23,24,25 O O

Drive B, G, and R Outputs)

Blank OSD Blank Output 26 O O

d

Half Blank
RGB Digital

Outputs
SCLK

Notes:

a) Port19 is not available on the 40-pin DIP Version, Revision D is Push-Pull.
b) SCL I/O pin is shared with Port01 or Port11
c) SCD I/O pin is shared with Port02 or Port12
d) Half Blank output is a function shared with Port0F. Half Blank output is not available on the 40-pin DIP version.
e) Digital RGB outputs and the internal SCLK are shared with Port1[5:0].
f) Internal processor SCLK is shared with Port16.

e

f

OSD Half Blank Output – O I
R[1:0],G[1:0], and B[1:0]

19,18,17,14,12,3 O

Outputs of the RGB Matrix
Internal Processor SCLK O

a

a

Configuration

O

O

4

1

P R E L I M I N A R Y Digital Television Controller

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Min Max Units Conditions

V

CC

V

ID

V

IA

V

O

V

O

I

OH

I

OH

I

OL

I

OL

T

A

T

A

Note: Revision D and later have push-pull PWM outputs.

Power Supply Voltage 0 7 V
Input V oltage –0.3 V
Input V oltage –0.3 V
Output V oltage –0.3 V
Output V oltage –0.3 V

+0.3 V Digital Inputs

CC

+0.3 V Analog Inputs (A/D0-A/D4)

CC

+0.3 V All Push-Pull Digital Output

CC

+0.3 V Open-Drain/Push-Pull PWM

CC

Outputs (PWM1-PWM8)
Output Current High –10 mA One Pin
Output Current High –100 mA All Pins

Output Current Low 20 mA One Pin
Output Current Low 200 mA All Pins
Operating Temperature 0 70

Storage Temperature –65 150

°

C

°

C

Z89302/04/06

DC CHARACTERISTICS

T

= 0

°

A

C to + 70

°

C; V

Symbol Parameter Min Max Typical Units Conditions

V

V
V
V

V
V

V

V

I
I

I

I

CC1E

I

I

I

ADC

I

ADC

CC

CC1

CC2

Input V oltage Low 0 0.2 V

IL

Input V oltage High 0.6 V

IH

Max. Pull-Up Voltage 5 V All Pins

PU

Output Voltage Low 0.4 0.16 V @ I

OL

Output V oltage High V

OL

Input Voltage XTAL1 Low 0.3 V

XL

Input Voltage XTAL1 High V

XH

Schmitt Hysteresis 3.0 0.75 0.5 V On XTAL1 Input Pin

HY

Reset Input Current 150 90

IR

Input Leakage –3.0 3.0 0.01

IL

Supply Current 100 60 mA
Supply Current of the OTP 700 300

Supply Current 300 100
Supply Current 10 5
Input Current 0.5 mA C Revision
Input Current 10

= 4.5 V to + 5.5 V; F

CC

–0.9 4.75 V @ I

CC

–2.0 3.5 V Generator Driven

CC

CC

= 32.768 kHz

OSC

CC

V

CC

CC

0.4 V

3.6 V

= 1 mA

OL

= 0.75 mA

OL

1.0 V External Clock

m

AV

m

A @ 0 V and V

m

A Sleep Mode @ 32 kHz

m

A Sleep Mode @ 32 kHz

m

A Sleep Mode

m

A D Revision

= 0V

RL

CC

5

Z89302/04/06
Digital Television Controller P R E L I M I N A R Y

V1,V2,V3 ANALOG OUTPUT

Condition 4.75 V 5.25 V

11 3.6 – 4.4 4.0 – 5.0 V
10
01

79% of V
50% of V

±

5%

II

± 5%

II

00 0.0 – 0.8V

Notes:

Maximum Variance Between V1, V2, V3 is 100 mV
Settling Time 70% of DC Level, 10pF Load <50n Sec

II

47

pF

68 pF

XTAL1

32.768K

10 MO

hm

XTAL2

27 K

32K Oscillator Recomended Circuit

Figure 3. 32K Oscillator Recommended Circuit

Z893XX

510 W
10 mF

0.1 mF

Figure 4. Low Pass Filter

6

1

AC CHARACTERISTICS

Z89302/04/06

P R E L I M I N A R Y Digital Television Controller

= 0°C to + 70°C; VCC = 4.5 V to 5.5 V; F

T

A

= 32.768 kHz

OSC

Symbol Parameter Min Max Typical Units

TPC Input Clock Period 16 100 32 ms

C,TFC Clock Input Rise and Fall 12 ms

T

R

POR Power-On Reset Delay 0.8 1.2 s

T

D

AC CHARACTERISTICS

= 0°C to + 70°C; VCC = 4.5 V to 5.5 V; F

T

A

Symbol Parameter Min. Max. Typical Units

TWRES Power-On Reset Min. Width 5TPC ms
T

DHS

T

DVS

T

DES

H_Sync Incoming Signal Width 5.5 12.5 11 ms
V_Sync Incoming Signal Width 0.15 1.5 1.0 ms
Time Delay Between Leading Edge of

V_Sync and H_Sync on Even Field

TDO

S

Time Delay Between Leading Edge of
H_Sync in Odd Field

TWHV

S

Note: All timing of the I2C bus interface is defined by related specifications of the I2C bus interface.

H_Sync/V_Sync Edge Width 2.0 0.5 ms

= 32.768 kHz

OSC

–12 +12 0 ms

20 44 32 ms

ANALOG INPUT

ADC0

Step Min. Max

1 1.45 1.55

15 Step 1 + 0.468 Step 1 + 0.532

ADC1

Step Min. Max

1 0.2 0.4

15 Step_1 + 4.95 Step_1 + 5.15

Note: VCC = 5V

7

Z89302/04/06
Digital Television Controller P R E L I M I N A R Y

Development Projects:

Customer is cautioned that while reasonable efforts will be
employed to meet performance objectives and milestone
dates, development is subject to unanticipated problems

and delays. No production release is authorized or
committed until the Customer and Zilog have agreed upon
a Customer Procurement Specification for this project.

Pre-Characterization Product:

The product represented by this CPS is newly introduced
and Zilog has not completed the full characterization of the
product. The CPS states what Zilog knows about this
product at this time, but additional features or non-

either by Zilog or its customers in the course of further
application and characterization work. In addition, Zilog
cautions that delivery may be uncertain at times, due to
start-up yield issues.

conformance with some aspects of the CPS may be found,

© 1996 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means with­out the prior written consent of Zilog, Inc. The information in this
document is subject to change without notice. Devices sold by
Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or re­garding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer­chantability or fitness for any purpose. Zilog, Inc. shall not be re­sponsible for any errors that may appear in this document. Zilog,
Inc. makes no commitment to update or keep current the informa­tion contained in this document.

Zilog’s products are not authorized for use as critical components
in life support devices or systems unless a specific written agree­ment pertaining to such intended use is executed between the
customer and Zilog prior to use. Life support devices or systems
are those which are intended for surgical implantation into the
body, or which sustains life whose failure to perform, when prop­erly used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in significant injury
to the user.

Zilog, Inc., 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone [phone]
FAX: [phone]
Internet: http://www.zilog.com

8