Datasheet XWM8740EDS Datasheet (Wolfson)

WM8740

RSTB

24-bit, High Performance 192kHz Stereo DAC

Advanced Information, July 2000, Rev 1.7

DESCRIPTION

The WM8740 is a very high performance stereo DAC
designed for audio applications such as CD, DVD, home
theatre systems, set top boxes and digital TV. The WM8740
supports data input word lengths from 16 to 24-bits and
sampling rates up to 192kHz. The WM8740 consists of a
serial interface port, di gi tal interpolation filter, multi-bit sigma
delta modulator and stereo DAC in a small 28-pin SSOP
package. The WM8740 also inc ludes a digitally cont rollable
mute and attenuator function on each channel.

The internal digital filter has two selectable roll-off
characteristics. A sharp or slow roll-off can be selected
dependent on application requirements. Additionally, the
internal digital filter can be by-passed and the WM8740
used with an external digital filter.

The WM8740 supports two connection sc hemes for audio
DAC control. The SPI-compatible serial control port
provides access to a wide range of features inc luding on­chip mute, attenuation and phase reversal. A hardware
controllable interface is also available.

BLOCK DIAGRAM

MODE

(24)

ML/I2S

(28)

MC/DM1

(27)

MD/DM0

(26)

DIFFHW

(6)

MUTEB

(25)

FEATURES

• 120dB SNR (‘A’ weighted mono @48kHz), THD+N: -104dB
@ FS

• 117dB SNR (‘A’ weighted stereo @48kHz), THD+N: -104dB
@ FS

• Sampling frequency: 8kHz to 192kHz

• Selectable digital fi l t er rol l -off

• Optional interface to indus try standard external filters

• Differential mono mode needing no glue logic

• Input data word: 16 to 24-bit

• Hardware or SPI compatible seri al port control modes:

• Hardware mode: mute, de-emphasis, audio form at

control

• Serial mode: mute, de-emphasis, attenuation (256
steps), phase reversal

• Fully differential voltage output s

APPLICATIONS

• CD, DVD audio

• Home theatre systems

• Professional audio syst ems

AGNDR

CSBIWO

(23)

(22)

ZERO

(21)

MODE8X

(4)

(10)

AVDDR
(9)

CONTROL INTERFACE

SCLK (5)

BCKIN (3)

LRCIN (1)

DIN (2)

SERIAL

INTERFACE

MUTE/
ATTEN

DIGITAL

FILTERS

MUTE/
ATTEN

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edi nburgh, EH8 9NX, UK
Tel: [phone]
Fax: [phone]
Email: [email protected]
http://www.wolfson.co.uk

MUX

MUX

(15)

AVDD

SIGMA
DELTA

MODULATOR

SIGMA
DELTA

MODULATOR

(8)

DVDD

RIGHT
DAC

LEFT
DAC

(20)

AVDDL.

(19)
AGNDL

WM8740

LOW

PASS

FILTER

LOW

PASS

FILTER

(14)

AGND

(11) VMIDR

(12) VOUTRP
(13) VOUTRN

(17) VOUTLP
(16) VOUTLN

(18) VMIDL

(7)
DGND

Advanced Information data sheets contain

preliminary data on new products in t he

preproduction phase of development .

Supplementary data will be published at a

later date.

2000 Wolfson Microelectronics Ltd.

WM8740 Advanced Information

PIN CONFIGURATION ORDERING INFORMATION

LRCIN

DIN

BCKIN

MODE8X

SCLK

DIFFHW

DGND

DVDD
AVDDR
AGNDR

VMIDR

VOUTRP
VOUTRN

AGND

1
2
3
4
5
6
7
8
9
10
11
12
13

ML/I2S

28

MC/DM1

27

MD/DM0

26

MUTEB

25

MODE

24

CSBIWO

23

RSTB

22

ZERO

21

AVDDL

20

AGNDL

19

VMIDL

18

VOUTLP

17

VOUTLN

16

AVDD

1514

PIN DESCRIPTION

PIN NAME TYPE DESCRIPTION

1 LRCIN Digital input
2 DIN Digital input
3 BCKIN Digital input
4 MODE8X Digital input
5 SCLK Digital input
6 DIFFHW Digital input
7 DGND Supply
8 DVDD Supply

9 AVDDR Supply
10 AGNDR Supply
11 VMIDR Analogue output
12 VOUTRP Analogue output
13 VOUTRN Analogue output
14 AGND Supply
15 AVDD Supply
16 VOUTLN Analogue output
17 VOUTLP Analogue output
18 VMIDL Analogue output
19 AGNDL Supply
20 AVDDL Supply
21 ZERO Digital output

22 RSTB Digital input

Sample rate clock i nput.
Audio data serial input (except in 8XMODE when it is DI NL).
Audio data bit clock i nput .
Internal pull-down, active high, 8 x fs mode.
System clock i nput.
Internal pull-down, active high, dif ferential mono mode.
Digital ground supply.
Digital positive supply.
Analogue positive supply.
Analogue ground supply.
Mid rail right channel.
Right channel DAC output positive.
Right channel DAC output negative.
Analogue ground supply.
Analogue positive supply.
Left channel DAC output negative.
Left channel DAC output positive.
Mid rail left channel.
Analogue ground supply.
Analogue positive supply.

Infinite zero detect – active low. Open drain type output with active pul l -down.
Reset input – active low. Internal pull-up.

DEVICE TEMP. RANGE PACKAGE

XWM8740EDS -25° to +85°C 28-pin SSOP

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Advanced Information WM8740

PIN NAME TYPE DESCRIPTION

23 CSBIWO Digital input

Internal pull-down

24 MODE Digital input

Internal pull-up

Hardware Mode
Normal Mode Differential Mode 8X Mode

Wordlength:
Low for 16-bit data.
High for 20-bit
(normal) or 24-bit

2

S data.

I
Low for hardware

mode.

Wordlength:
Low for 16-bit data.
High for 20-bit
(normal) or 24-bit
I2S data.

Low for left
mono mode.

Wordlength:
Low for 20-bit data.
High for 24-bit data.

DINR High for

High for right

Software
Mode

Low for
serial
interface
operation.

software
mode.

mono mode

25 MUTEB Digital input

Internal pull-up

Low to soft mute.
High for normal

operation.

Low to soft mute.
High for normal

operation.

Low to soft mute.
High for normal

operation.

Low to
soft mute.

High for
normal
operation.

26 MD/DM0 Digi tal input

Internal pull-up

De-emphasis mode
select bit 0.

Low for no
de-emphasis.

High for 44.1kHz

LRP – LRCLK
polarity select.

Control serial
interface
data signal.

de-emphasis.

27 MC/DM1 Digi tal input

Internal pull-up

De-emphasis mode
select bit 1.

Low for normal filter
operation.

High for filter slow

Unused.
Leave unconnected.

Control serial
interface
clock signal.

roll-off.

28 ML/I2S Digital input

Internal pull-up

Audio serial format:
Low – right justified.

2

High – I

S.

Audio serial format:
Low – right justified.
High – I2S.

Input data format:
Low – right justified.
High – left justified.

Control serial
interface
load signal.

Note: Digital input pins have Schmitt tri gger i nput buffers.

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are s tres s rat ings only. P erm anent damage to the device may be c aused by c ontinuous ly operat ing at
or beyond these limits. Device functional operating lim its and guaranteed performance s pecifications are gi ven under Electrical
Characteristics at the test conditions s pecified

ESD Sensitive Device. Thi s device i s m anufactured on a CMOS process . It i s t herefore generi cally suscept ible
to damage from excessi ve stati c voltages . Proper ES D precautions mus t be tak en during handling and st orage
of this device.

CONDITION MIN MAX

Supply voltage
Reference input
Operating temperature range, T

A

Storage temperature
Package body temperature (s ol deri ng, 10 seconds)
Package body temperature (s ol deri ng, 2 minutes)

-0.3V +7.0V
VDD + 0.3V

-25°C+85

°

C

-65°C +150°C
+240°C
+183°C

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WM8740 Advanced Information RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Digital supply range
Analogue supply range
Ground
Difference DGND to AGND
Analogue supply current
Digital supply current
Analogue supply current
Digital supply current

DVDD -10% 3.3 to 5 +10% V
AVDD -10% 3.3 to 5 +10% V

AGND, DGND 0 V

-0.3 0 +0.3 V
AVDD = 5V 15 mA
DVDD = 5V 15 mA

AVDD = 3.3V 15 mA
DVDD = 3.3V 9 mA

ELECTRICAL CHARACTERISTICS

TEST CONDITIONS

AVDD, DVDD = 5V, AGND, DGND = 0V , T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNI T
DAC Circuit Specifications

SNR
(See Note 1)

THD (full-scale)
(See Note 2)

THD+N (Dynamic range)
(See Note 2)

Filter Characteristics (Sharp Roll-off)

Passband
Stopband
Passband ripple
Stopband attenuation
Delay time

Filter Characteristics (Slow Roll -off)

Passband
Stopband
Passband ripple
Stopband attenuation
Delay time

Internal Analogue Filter

Bandwidth
Passband edge response

Digital Logic Levels

Input LOW level
Input HIGH level
Output LOW level
Output HIGH level

V

V
V
V

= +25oC, fs = 48kHz, SCKI = 256f s unless otherwise stated.

A

Mono fs @ 48kHz 120 dB
Stereo fs @ 48kHz 110 117 dB
Stereo fs @ 96kHz 116 dB

Mono 0dB -104 dB

Stereo 0dB -95 -104 dB

-60dB 117 dB

±0.0012 dB 0.4535fs dB

-3dB 0.491fs

f > 0.5465fs -82 dB

±0.001dB 0.274fs

-3dB 0.459fs

f > 0.732fs -82 dB

-3dB 195 kHz

20kHz -0.043 dB

IL

2.0 V

OL
OH

IH

IOL = 2mA AVSS + 0.3V V
IOH = 2mA AVDD - 0.3V

±0.0012 dB

30/fs s

±0.001 dB

9/fs s

0.8

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Advanced Information WM8740

TEST CONDITIONS

AVDD, DVDD = 5V, AGND, DGND = 0V , T

= +25oC, fs = 48kHz, SCKI = 256f s unless otherwise stated.

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNI T
Analogue Output Levels

Output level differential

Into 10kohm, full scale 0dB,

2

V

RMS

(5V supply)

Into 10kohm, full scale 0dB,

1.32 V

RMS

(3.3V supply)

Minimum resist ance load

To midrail or AC coupled

1 kohms

(5V supply)

To midrail or AC coupled

600 ohms

(3.3V supply)
Maximum capacitance load
Output DC level

5V or 3.3V 100 pF

AVDD/2 V

Reference Levels

Potential divider resis tance

AVDD to VMIDL/VMIDR and

10 kohms

VMIDL/VMIDR to AGND

Voltage at VMIDL/VMIDR

AVDD/2

POR

POR threshold

2.2 V

Notes: 1. Ratio of output level with 1kHz full scale i nput , to the output level with all zeros i nt o the digital input, measured ‘A’

weighted over a 20Hz to 20kHz bandwidth.

2. All performanc e measurements done with 20kHz low pass filter. Failure to use such a filter will result in higher
THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteri stics. The low
pass filter removes out of band noise; although it is not audible it may affect dynamic specifi cation values.

LRCIN

t

BCH

t

BCL

t

LB

BCKIN

t

BCY

t

BL

DIN

t

DS

t

DH

Figure 1 Audio Data Input Timing

Test Conditions

AVDD, DVDD = 5V, AGND, DGND = 0V , T

= +25oC, fs = 48kHz, SCKI = 256f s unless otherwise stated.

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Audio Data Input Timing Information

BCKIN pulse cycle time
BCKIN pulse width high
BCKIN pulse width low
BCKIN rising edge to

t

BCY

t

BCH

t

t

BCL

BL

100 ns

40 ns
40 ns
20 ns

LRCIN edge
LRCIN rising edge to

t

LB

20 ns

BCKIN rising edge

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WM8740 Advanced Information

Test Conditions

AVDD, DVDD = 5V, AGND, DGND = 0V , T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

DIN setup time
DIN hold time

t

DS

t

DH

SCKI

Figure 2 System Clock Timing Requirements

Test Conditions

AVDD, DVDD = 5V, AGND, DGND = 0V , T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
System Clock Timing Information

System clock pul se width high
System clock pul se width low
System clock cycle time

= +25oC, fs = 48kHz, SCKI = 256f s unless otherwise stated.

A

20 ns
20 ns

t

SCKIL

t

SCKIH

t

SCKY

= +25oC, fs = 48kHz, SCKI = 256f s unless otherwise stated.

A

t

SCKIH

t

SCKIL

t

SCKY

10 ns
10 ns
27 ns

t

MLL

t

MHH

ML/I2S

t

MCY

t

MCHtMCL

t

MLD

t

MLS

MC/DM1

t

MDStMDH

MD/DM0

Figure 3 Program Register Input Timing – SPI Compatible Serial Control Mode

Test Conditions

AVDD, DVDD = 5V, AGND, DGND = 0V , T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Program Register Input Information

MC/DM1 pulse cycle time
MC/DM1 pulse width low
MD/DM0 pulse width high
MD/DM0 set-up time
MC/DM1 hold time
ML/I2S pulse width low
ML/I2S pulse width high
ML/I2S set-up time
ML/I2S delay from MC

= +25oC, fs = 48kHz, SCKI = 256f s unless otherwise stated.

A

t

MCY

t

MCL

t

MCH

t

MDS

t

MDH

t

MLL

t

MHH

t

MLS

t

MLD

LSB

80 ns
32 ns
32 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns

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Advanced Information WM8740

DEVICE DESCRIPTION

The WM8740 is a high performance 128f s oversam pling rate s tereo DAC em ploying a novel 64 l evel
sigma delta DAC design which provides optimised signal-to-noise performance and clock jitter
tolerance. It is ideally suited to high quali ty audio applic ations s uch as CD, DVD-audio, hom e theat re
receivers and professional mixing consoles. The WM8740 supports sample rates from 8ks/s to
192ks/s.

The control functions of the WM8740 are either pin selec ted (hardware mode) or program med via the
serial interface (soft ware mode). Control functions that are available include: dat a input word length
and format selection (16-24 bits: I
selection (48kHz, 44.1kHz and 32kHz); differential output modes; a software or hardware mute and
independently digitally controllabl e at tenuation on both channels.

The digital filtering may be bypassed enti rely by selec ting MODE8X. Data is then input direc tly to t he
DAC, bypassing the digital filters. Left and ri ght channels are input separatel y, using the MODE pin
as the right channel input. This mode allows the use of alternative digital fil ters, such as the P acific
Microsonics PMD100 HDCD filt er.

In addition to the normal s tereo operating mode the W M8740 may also be used in dual diff erential
mode with either the left or right channel (selectable) being out put dual differentiall y. Two WM8740s
can then be used in parallel to implement a stereo channel, each supporting a single channel
differentially. Note that this mode uses 2 pairs of differential outputs for eac h channel – the benefit is
SNR improved by 3dB. This mode is available in both s oftware and hardware modes and may also
be used in conjunction with MODE8X.

SYSTEM CLOCK

Sample rates from 8ks/s up t o 96ks/s are available, and autom atically s elected, with a system cl ock
of 256fs or 384fs. In addit ion a s ystem c loc k of 128fs or 192fs m ay be us ed, with s am ple rates up t o
192ks/s. With a 128fs or 192fs system clock 64x oversampling mode operation is automatically
selected and the first stage of the digital filt er i s bypassed.

2

S, left justified or right justified): de-emphasis sample rate

WM8740 has an asynchronous m onitor circuit, which in t he event of removal of the mas ter system
clock, resets t he digital fi lters and analogue circ uits, m uting the out put. Re-applic ation of the sys tem
clock re-starts the filters from an intitialised state. Cont rol registers are not reset under this condition.

The WM8740 is tolerant of asynchronous bit clock jitter. The internal signal processing
resynchronises to the external LRCIN once the phase difference between bit cloc k and the system
clock exceeds half an LRCIN period. During this re-s ynch period the interpolating filters will either
miss or repeat an audio sample, minimising t he audible effects of t he operation. Table 1 shows the
typical system clock frequency inputs for the WM8740.

SAMPLING

RATE

(LRCIN)

32kHz 4.096 6.144 8.192 12.288

44.1kHz 5.6448 8.467 11.2896 16.9340
48kHz 6.114 9.216 12.288 18.432
96kHz 12.288 18.432 24.576 36.864

192kHz 24.576 36.864 Unavailable Unavailable

Table 1 System Clock Frequencies Versus Sampling Rate

AUDIO DATA INTERFACE

Data may be input at a rate corresponding to the system clock having a rat e of 256fs or 384fs, in
which case an oversampling rati o of 128x is selected. Alt ernatively a rate of 128fs or 192fs may be
used, in which case the firs t f ilt er st age is bypas s ed and an oversam pl ing rati o of 64x results . Final ly,
in MODE8X, data may be input at 8x the normal rate, in which cas e separate input pins are us ed to
input the two stereo channels of dat a (unless DIFFHW mode and MODE8X are both selected, in
which case only a mono channel is converted differentially). In MODE8X all filter stages are by­passed, prior to the sigma delta modulator. Data i s input MSB first in all modes.

SYSTEM CLOCK FREQUENCY (MHZ)

128fs 192fs 256fs 384fs

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WM8740 Advanced Information

NORMAL SAMPLE RATE

In normal mode, the dat a i s input serially on one pin for both lef t and ri ght channels.
Data can be “right justified” meaning that the last 16, 20 or 24 bits (depending on c hosen PCM word

length) that were clocked in prior t o t he transition on LRCIN are valid.
Alternatively data can be “left justified” (20 and 24-bit PCM data only), where the bit s are cloc ked in

as the first 20 or 24 bits after a transition on LRCIN.
For the three I

except with one additional preceding clock cycle.

LRCIN (PIN 1)

BCKIN (PIN 3)

2

S modes supported (16-bit, 20-bit and 24-bi t P CM data), data is c loc ked “left justified”

1/fs

RIGHTLEFT

16-BIT RIGHT

JUSTIFIED
DIN (PIN 2)

20-BIT RIGHT

JUSTIFIED
DIN (PIN 2)

24-BIT RIGHT

JUSTIFIED
DIN (PIN 2)

24-BIT LEFT

JUSTIFIED
DIN (PIN 2)

20-BIT LEFT

JUSTIFIED
DIN (PIN 2)

LRCIN (PIN 1)

BCKIN (PIN 3)

16-BIT I

DIN (PIN 2)

24-BIT I

DIN (PIN 2)

20-BIT I

DIN (PIN 2)

2

S

2

S

2

S

B2 B1 B0

B2 B1 B0

B2 B1 B0

B0

B0

B23 B22 B21 B20 B19

B23 B22 B21

B19 B18 B17

B15

B23

B19

B19 B18 B17

B4 B3 B2 B1 B0

B0

B2 B1 B0

B6 B5 B4

B2 B1 B0

B15 B2 B1 B0

B2 B1 B0

B2 B1 B0

B0

B3 B2 B1

B23 B22 B21 B20 B19

B23 B22 B21

B19 B18 B17 B0

B2 B1 B0

B15

B23

B6 B5 B4 B0

B19

B2 B1 B0

B15 B2 B1 B0

B19 B18 B17

B4 B3 B2 B1 B0

RIGHTLEFT

B3 B2 B1

B2 B1 B0

B2 B1 B0

B15

B23

B19

Figure 4 Audio Data Input Format

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Advanced Information WM8740

8 X FS INPUT SAMPLE RATE

Due to the higher speed of the interface in 8 x fs mode, audio data is input on two pins. The MODE
pin (pin 24) is used as the second input for t he right channel dat a and lef t dat a is i nput on DI N (pin2).
In this mode, software control of the device is not availabl e. The data c an be input in t wo format s, left
or right justified, s elec table by ML/I 2S and t wo word lengths (20 or 24 bi t), s elec table by CSB IWO. In
both modes the data is al ways c l ocked in MSB first.

For left justified data t he word start is marked by the falling edge of LRCIN. The data is cloc ked i n on
the next 20/24 BCKIN rising edges. Thi s format is compatible with devices such as the PMD100.

For right justified the data i s justified to the ris ing edge of LRCIN and the data is cloc ked in on the
preceding 20/24 BCKIN rising edges before the LRCIN ris ing edge. This format is com patible with
devices such as the DF1704 or SM5842.

In both modes the polarit y of LRCIN can be switched using MD/DM0.
Differential hardware mode can be used in conjunction with 8fs mode by s etting the DIFFHW

pin high. In differential 8f s mode the data is input on DIN and output dif ferentially. MODE is

unused and must be tied low.

1/8fs

LRCIN (PIN 1)

BCKIN (PIN 3)

Figure 5 Audio Data Input Format (8 x fs Operation)

MODES OF OPERATION

Control of the various modes of operation i s either by software control over the serial interf ace, or
by hard-wired pin control. Selection of software or hardware mode is via MODE pin. The following
functions may be controlled either via the serial control interface or by hard wiring of the
appropriate pins.

LEFT AUDIO

DATA DIN

(PIN 2)

RIGHT AUDIO

DATA MODE

(PIN 24)

LRCIN (PIN 1)

BCKIN (PIN 3)

LEFT AUDIO

DATA DIN

(PIN 2)

RIGHT AUDIO

DATA MODE

(PIN 24)

B19B22B23 B20B21 B2 B1 B0 B23 B22 B21 B20

B19B22B23 B20B21 B2 B1 B0 B23 B22 B21 B20

1/8fs

B19B22B23 B20B21

B19B22B23 B20B21

B2 B1 B0

B2 B1 B0

HARDWARE CONTROL MODES

When the MODE pin is held ‘low’ the following hardware modes of operation are available. In
Hardware differential mode or 8X mode some of these modes/control words are altered or
unavailable.

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WM8740 Advanced Information

DE-EMPHASIS CONTROL

MDDM1

PIN 27

LL Off
L H 48kHz
H L 44.1kHz
H H 32kHz

Table 2 De-Emphasis Control

AUDIO INPUT FORMAT

ML/I2S

PIN 28

L L 16 bit normal right

L H 20 bit normal right

H L 16 bit I2S
H H 24 bit I2S

Table 3 Audio Input Format

SOFT MUTE

MUTEB

PIN 25

L Mute On (no output)
H Mute Off (normal operation)

Table 4 Soft Mute

MCDMO

PIN 26

CSBIWO

PIN 23

DE-EMPHASIS

DATA FORMAT

justified

justified

FUNCTION

A logic low on the MUTEB pin will cause the attenuation to ramp to inf inite attenuation at a rate of
128/fs seconds per 0.5dB step. Setting MUTEB high will cause t he attenuation to ramp back to its
previous value.

SOFTWARE CONTROL INTERFACE

The WM8740 can be controlled using a 3-wire serial interface. MD/DM0 (pin 26) is used for the
program data, MC/DM1 (pin 22) is used to c lock in the program data and ML/I2S (pin 28) is use t o
latch in the program data. The 3-wire int erfac e protoc ol is shown in Figure 6. CS B/ IWO (pin 23) must
be low when writing.

ML/I2S (PIN 28)

MC/DM1 (PIN 27)

MD/DM0 (PIN 26)

Figure 6 Three-Wire Serial Interface

B15 B14 B13 B2 B1 B0

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Advanced Information WM8740

REGISTER MAP

WM8740 controls the special functions using 4 program registers, which are 16-bits long. These
registers are all loaded through input pin MD/DM0. Aft er the 16 data bits are clocked in, ML/I 2S is
used to latch in the data to t he appropriate register. Table 5 shows the com plete mapping of the 4
registers. Note that i n hardware differential mode and 8X modes, software control is not available.
The hardware differential mode (Diff[1:0]) clock loss detector disable (CDD) can only be accessed by
writing to M2[8:5] with the pattern 1111. Register M4 is then accessibl e by setting A[2:0] to 110.

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

M0

----A2 (0)A1(0)A0(0)LDLAL7AL6AL5AL4AL3AL2AL1AL0

M1

----A2(0)A1(0)A0(1)LDRAR7AR6AR5AR4AR3AR2AR1AR0

M2

----A2(0)A1(1)A0(0)----IW1IW0OPEDEMMUT

M3

----A2(0)A1(1)A0(1)IZDSF1SF0CK0REVSR0ATCLRPI

M4

----A2(1)A1(1)A0(0)--CDDDIFF1DIFF0----

Table 5 Mapping of Program Registers

REGISTER BITS NAME DEFAULT DESCRIPTION

0

1

2

3

4

Table 6 Register Bit Descriptions

[7:0] AL[7:0] FF

8LDL 0

[7:0] AR[7:0] FF

8LDR 0
0MUT 0
1DEM 0
2OPE 0

[4:3] IW[1:0] 0

0I2S 0
1LRP 0
2ATC 0
3SR0 0
4REV 0
5CKO 0

[7:6] SF[1:0] 0

8IZD 0

[5:4] DIFF 0

6 CDD 0

Attenuation data for left channel.
Attenuation data load control for left channel.
Attenuation data for right channel.
Attenuation data load control for right channel.
Left and right DACs soft mute control.
De-emphasis control.
Left and right DACs operation c ont rol .
Input audio data bit select .
Audio data format select.
Polarity of LRCIN selec t.
Attenuator control.
Digital filter slow roll-off select.
Output phase reverse.
CLKO frequency select.
Sampling rate select.
Infinite zero detection circuit control.
Differential output mode.
Clock loss detector disable.

2

S

DAC OUTPUT ATTENUATION

The level of attenuation for eight bi t code X, is given by:

0.5 ∗ (X - 255) dB, 1 ≤ X ≤ 255

- ∞dB (mute), X = 0

Bit 8 in register 0 (LDL) is us ed to control the l oading of attenuati on data in B [7:0]. W hen LDL is set
to 0, attenuation data will be loaded into AL[7:0], but it will not affect the filter attenuation. LDR in
register 1 has the same f unct ion f or right c hannel at tenuat ion. Onl y when LDL or LDR i s s et to ’1’ will
the filter attenuation be updated. This permits left and right channel attenuation to be updated
simultaneously.

Attenuation level is c ontrolled by AL[7:0] (left channel) or AR[7:0] (right channel). Att enuation levels
are given in Table 7.

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WM8740 Advanced Information

X[7:0] ATTENUATION LEVEL

00(hex) - ∞dB (mute)
01(hex) -127.0dB

::

::
FD(hex) -1.0dB
FE(hex) -0.5dB
FF(hex) 0.0dB

Table 7 Attenuation Control Level

Bit 2 in Reg3 is used to control the attenuator (ATC). W hen ATC is “high”, the attenuation data
loaded in program register 0 is us ed for both the left and the right channels. When AT C is low, the
attenuation data for each regis t er i s applied separately to left and right channels.

SOFT MUTE

MUT

(REG2, B0)

L

H

Table 8 Soft Mute

Setting MUT causes the att enuation to ramp from t he current value down to 00. The values held in
the attenuation registers are unchanged. When MUT is reset the attenuation will ramp back up to the
previous value. The ramp rate is 128/fs s/0.5dB step.

DIGITAL DE-EMPHASIS

DEM

(REG2, B1)

L

H

Table 9 Digital De-Emphasis

Soft Mute off (normal operat i on)
Soft Mute on (no output)

De-emphasis off
De-emphasis on

DAC OPERATION ENABLE

OPE

(REG2,B2)

L

H

Table 10 DAC Operation Enable

Normal operation
DAC output forced to bipolar zero,

irrespective of input data.

AUDIO DATA INPUT FORMAT

I2S

(REG3, B0)

000
001
010
011
100
101
110
111

Table 11 Audio Data Input Format

IW1

(REG2, B4)

IW0

(REG2, B3)

AUDIO INTERFACE

16-bit standard right justi fied
20-bit standard right justi fied
24-bit standard right justi fied
24-bit left justified (MSB first)

2

S

16-bit I

2

S

24-bit I

2

S

20-bit I
20-bit left justified (MSB first)

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Advanced Information WM8740

POLARITY OF LR INPUT CLOCK

The left channel data for a particular sample instant i s always input first, then t he ri ght channel data.

LRP

(REG3, B1)

L

H

Table 12 Polarity of LR Input Clock

LR High – left channel
LR Low – right channel
LR Low – left channel
LR High – right channel

INDIVIDUAL OR COMMON ATTENUTATION CONTROL

ATC

(REG3, B2)

L

H

Table 13 Individual or Common Attenuation Control

Individual control
Common control from Reg0

DIGITAL FILTER ROLL-OFF SELECTION

SRO

(REG3, B3)

L

H

Table 14 Digital Filter Roll-Off Selection

Sharp
Slow

ANALOGUE OUTPUT POLARITY REVERSAL

REV

(REG3, B4)

L

H

Table 15 Analogue Output Polarity Reversal

Normal
Inverted

CLKO OUTPUT FREQUENCY

CKO

(REG3, B5)

L

H

Table 16 CLKO Output Frequency

XTI
XTI/2

DE-EMPHASIS SAMPLE RATE

SF1

(REG3, B7)

0 0 No de-emphasis
0 1 48kHz
1 0 44.1kHz
1 1 32kHz

Table 17 De-Emphasis Sample Rate

SF0

(REG3, B6)

SAMPLE RATE

INFINITE ZERO DETECT

IZD

(REG3, B8)

L

H

Table 18 Infinite Zero Detect

Zero detect mute off
Zero detect mute on

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WM8740 Advanced Information

DIFFERENTIAL MONO MODE

Using bits 4 and 5, the differential output mode m ay be selected to be one of normal stereo, reversed
stereo, mono left or mono right, as shown in Table 19.

DIFF[1:0]

B[4:5])

00
01
10

11

Table 19 Differential Output Modes

Using these controls a pair of WM8740 devices may be used to build a dual differential stereo
implementation with hi gher perf ormance and differential output.

Note: DIFFHW mode pin may be used to achieve the same result by hardware means.

DIFFERENTIAL OUTPUT MODE

Stereo
Stereo reverse.
Mono left – differential outputs.
VOUTL is left channel.
VOUTR is the negative of left channel.
Mono right – differential outputs.
VOUTL is the negative right channel.
VOUTR is right channel.

CLOCK LOSS DETECTOR DISABLE

CDD (REG4, B6)

L
R

Table 20 Clock Loss Detector Disable

When the system c loc k i s inac ti ve for approxim ately 100 µs, the cl ock los s det ect or ci rcuit detec ts the
loss of clock and the analogue circui try is forced into a mute conditi on and the digital filters reset.
Setting the CDD bit disabl es this behaviour.

Clock loss detector on
Clock loss detector off

MUTE MODES

The device has various mute modes.

DIGITAL FILTER

ANRES ANMUTE

Reg bit OPE = ‘1’ Unaffected Asserted
MUTEB pin Gain ramped to zero

On release volume ramps

to previous value
AUTOMUTE
(detect 1024 zero

input samples)
Reg bit MUT As MUTEB pin As MUTEB pin
Gain = 00

(left & right)
RAM initialise Gain initialised to 0dB Asserted
Loss of system

clock

No LRCLK or invalid
SCLK/LRCLK ratio

RB Reset – gain initialised to 0dB Asserted Asserted
Power-on reset Reset Asserted Asserted

Table 21 Mute Modes

Automute has no effect on digital

filters

Gain = -∞dB Asserted

Not running (no clock). On clock

restart, filters initialised, RAM

initialised. Regist ers unchanged

Filters initialised, RAM initialised.

Registers unchanged

Asserted Asserted

Asserted Asserted

ANALOGUE

Asserted when
gain = 0

Asserted after
1024 zero input
samples if IZD = 1

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Advanced Information WM8740

• ANRES is the reset to the s witched capacitor filter.

• ANMUTE is an analogue muting signal gating t he anal ogue signal at the output (after

the SC filter)

• AUTOMUTE is asserted when both the IZD register bit is asserted and the input audio
data has been zero on both left and right channel s for 1024 input samples. The first
non-zero sample de-asserts .

• Appl yi ng a l ogi c low to MUTEB or setting MUT in Reg2 causes the gai n regi sters to
ramp to zero. W hen a l ogi c high is applied, the gain ram ps slowly back up to the value
held in the appropriate attenuation regis ter (AL or AR). The ramp rate = 128/fs s/0.5dB
step.

If SOFTMUTE is set or

MUTEB=0 then GAINL and

GAINR are overridden to 00

MUTEB

ZERO

SOFTMUTE

Automute:
Detect 1024
zero input
samples

GAINL[0:7]

GAINR[0:7]

IZD

gain ramps between
previous and new gain
setting

OPE

FREQ_INVALID

INIT

Signal
Processing

ANMUTE

Figure 7 Mute Modes

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WM8740 Advanced Information

FILTER RESPONSES

Figure 8 Digital Filter Response (Sharp Roll-off Mode) Figure 9 Digital Filter Response (Sharp Roll-off Mode)

Figure 10 Digital Filter Response (Slow Roll-off Mode) Figure 11 Digital Filter Response (Slow Roll-off Mode)

0

-20

-40

-60

Response (dB)

-80

-100

-120
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Frequency (Fs)

Figure 12 Digital Filter Response 128fs Mode (192kHz
Sample Rate) Normal Mo d e – Solid, Slow Mode – Dashed

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Advanced Information WM8740

1

0.8

0.6

0.4

0.2
0

Impulse Response

-0.2

-0.4
0 10 20 30 40 50 60

Time (input samples)

1

0.8

0.6

0.4

0.2
0

Impulse Response

-0.2

-0.4
0 10 20 30 40 50 60

Time (input samples)

Figure 13 Impulse Response (Normal Roll-off,
no De-emphasis)

Figure 14 Impulse Response (Slow Roll-off,
no De-emphasis)

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WM8740 Advanced Information RECOMMENDED EXTERNAL COMPONENTS

Software I/F or

Hardware Control

Audio Serial Data I/F

System Clock Input

DVDD

C

1

DGND

8

7

28
27
26
23
22

12

6

24

25

1
2
3

5

DVDD

DGND

ML/I2S
MC/DM1
MD/DM0
CSB/IWO
RSTB

MODE8X

DIFFHW

MODE

MUTEB

LRCIN
DIN
BCKIN

SCLK

VOUTLN
VOUTLP

VOUTRN
VOUTRP

WM8740

+

C

2

AVDD

AVDDR

AVDDL

AGND

AGNDR

AGNDL

ZERO

VMIDR

VMIDL

15

9

20

C

C4C

3

14
10
19
16
17

13
12

21

11
18

­+

-

+

AVDD

R

C

+

C

C

10

9

AGND

AVDD

+

C

5

6

AGND

LEFT OUTPUT DATA

RIGHT OUTPUT DATA

1

+

C

11

12

Notes: 1. AGND and DGND should be connected as close to the WM8740 as possible.

2. C

to C5, C9 and C11 should be positioned as close to the WM8740 as possible.

2

3. Capacitor type used can have a big effect on device perf ormance. It is
recomme nded that capacitors with very low ESR are used and that c e ramics are
either NPO or COG type material to achieve best performance from the WM8740.

Figure 15 External Components Diagram

RECOMMENDED EXTERNAL COMPONENTS VALUES

COMPONENT

REFERENCE

C1 and C6 10µF

C2 to C5 0.1µF

C7 and C8 10µF

C9 and C11 0.1µF

C10 and C12 10µF

R1 10kΩ

Table 22 External Components Description

WOLFSON MICROELECTRONICS LTD AI Rev 1.7 July 2000

SUGGESTED

VALUE

DESCRIPTION

De-coupling for DVDD and AVDD.
De-coupling for DVDD and AVDD.
Output AC coupling caps t o remove VMID DC level from outputs.
Reference de-coupling capacit ors for VMIDR and VMIDL.

Resistor to AVDD for open drain output operation.

18

Advanced Information WM8740

SUGGESTED DIFFERENTIAL OUTPUT FILTER CIRCUIT

Figure 16 Suggested Differential Output Filter Circuit

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WM8740 Advanced Information PACKAGE DIMENSIONS

DM007.BDS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)

b

D

A2

A1

A

e

1528

E1 E

141

0.10

-C-

C

SEATING PLANE

GAUGE
PLANE

Θ

0.25

c

L

Dimensions

Symbols

(mm)

MIN NOM MAX
A
A

1

A

2

b
c
D
e
E
E

1

L

θ

REF:

NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

----- ----- 2.13

0.05 ----- 0.25

1.62 1.75 1.88

0.22 ----- 0.38

0.09 ----- 0.20

9.90 10.20 10.50

0.65 BSC

7.40 7.80 8.20

5.00 5.30 5.60

0.63 0.90 1.03

o

0

o

4

o

8

JEDEC.95, MO- 150

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