Datasheet XWM8728EDS Datasheet (Wolfson)

WM8728

specifications for products in the

24-bit, 192kHz Stereo DAC

with Volume Contr ol and DSD Support

Product Preview, Rev 1.2, April 2001

DESCRIPTION

The WM8728 is a high perform ance stereo DAC designed
for audio applications suc h as DVD, hom e theatre syst ems,
and digital TV. The W M8728 supports PCM data i nput word
lengths from 16 to 32-bit s and s am pling rat es up t o 192kHz.
Alternatively the WM8728 can operate in DSD compatible
mode where a 64x bitstream is input for each c hannel. The
WM8728 consists of a serial interface port, digital
interpolation filters, multi-bit sigma delta modulators and
stereo DAC in a small 20-pin SSOP package. The W M8728
also includes a digitally controllable mute and attenuate
function for each channel.

The WM8728 supports a variet y of connection sc hemes f or
audio DAC control. The 2 or 3-wire MPU serial port provides
access to a wide range of features including on-chip m ute,
attenuation and phase reversal. A hardware controllable
interface is also available (DSD operation is only pos sible i n
hardware mode).

The WM8728 is an ideal device to interface to AC-3,
DTS, and MPEG audio decoders for surround sound
applications, or for us e i n DVD players supporting DVD-A.

BLOCK DIAGRAM

LATI2S

MODE

FEATURES

• Stereo DAC with 24 bit PCM or single bit DS D operation

• Audio Performance

- 106dB SNR (‘A’ weighted @ 48kHz) DAC

- -97dB THD

• DAC Sampling Frequency: 8kHz - 192kHz

• 2 or 3-Wire Serial Control Interface or Hardware Control

• Programmable Audio Data Interface Modes

2

- I

S, Left, Right Justified, DSP

- 16/20/24/32 bit W ord Lengths

• Independent Digital Volum e Control on Each Channel with

127.5dB Range in 0.5dB Steps

• 3.0V - 5.5V Supply Operation

• 20-pin SSOP Package

• Exceeds Dolby Class A Performance Requirements

APPLICATIONS

• DVD-Audio and DVD ‘Universal’ Pl ayers

• Home theatre systems

• Digital TV

• Digital broadcast receivers

MUTEB

SDIDEMSCKDSD

CSBIWL ZERO

CONTROL INTERFACE

MUTE/

BCKIN

LRCIN

DIN

SERIAL

INTERFACE

ATTEN

DIGITAL FILTERS

MUTE/
ATTEN

MCLK

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edi nburgh, EH8 9NX, UK
Tel: [phone]
Fax: [phone]
Email: [email protected]
www.wolfsonmicro.com

SIGMA
DELTA

MODULATOR

SIGMA
DELTA

MODULATOR

DVDDAVDD

WM8728

PCM/DSD

MUX

MUX

RIGHT
DAC

LEFT
DAC

VREFP VREFN

LOW

PASS

FILTER

LOW

PASS

FILTER

AGND D GND

Product Preview data sheets contain

formative phase of development. These

products may be changed or dis continued

without notice.

2001 Wolfson Microelectronics Ltd.

VOUTR

VOUTL

VMID

WM8728 Product Preview

PIN CONFIGURATION ORDERING INFORMATION

LRCIN

DIN

BCKIN

MCLK

ZERO

DGND

DVDD

VOUTR

AGND

AVDD

1
2
3
4
5

WM8728

6
7

8
9
10

20
19
18
17
16
15
14

13
12
11

L

2

A

T

S

I

SCKDSD
SDIDEM
MUTEB

M

O

D

E

CSBIWL
VREFP

VREFN
VMID
VOUTL

DEVICE TEMP. RANGE PACKAGE

XWM8728EDS -25 to +85oC 20-pin SSOP

PIN DESCRIPTION

PIN NAME TYPE DESCRIPTION

1 LRCIN Digital Input

2 DIN Digital Input

3 BCKIN Digital Input
4 MCLK Digital Input
5 ZERO Digital Output (Open drain)
6 DGND Supply
7 DVDD Supply
8 VOUTR Analogue Output

9 AGND Supply
10 AVDD Supply
11 VOUTL Analogue Output
12 VMID Analogue Output
13 VREFN Supply

14 VREFP Supply
15 CSBIWL Digital Input

(pull-up)
16 MODE Digital I nput (pull-down)
17 MUTEB Digital Bi-directional
18 SDIDEM Digital Bi-directional

19 SCKDSD Digital Input

(pull-down)

20 LATI2S Digital Input

(pull-up)

Note:

Digital input pins have Schmitt trigger input buff ers.

DAC Sample Rate Clock Input: PCM Input Mode
Right Channel DSD Bitstream Input: DSD Input Mode
Serial Audio Data Input: PCM Input Mode
Left Channel DSD Bitstream Input: DSD Input Mode
Audio Data Bit Clock Input
Master Clock Input
Infinite ZERO Detect Flag
Digital Ground Supply
Digital Positive S uppl y
Right Channel DAC Output
Analogue Ground Supply
Analogue Positive Supply
Left Channel DAC Output
Mid Rail Decoupling Point

DAC Negative Reference – normally AG ND, must not be below AGND
DAC Positive Reference – normally AVDD, must not be above AVDD
Software Mode: 3-Wire Serial Control Chip Select
Hardware Mode: Input Word Length
Control Mode Selection (L = Hardware, H = Software)
Mute Control (L = Mute on, H = Mute off, Z = Automute Enabled)
Software Mode: 3 or 2-Wire Serial Control Data Input:
Hardware Mode: De-Emphasis Select
Software Mode: 3 or 2-Wire Serial Control Clock Input
Hardware Mode: DSD Bitstream Operation S el ect
Software Mode 3-Wire Serial Cont rol Load Input
Hardware Mode: Input Data Format Selecti on

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

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WM8728 Product Preview

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are s tres s rat ings only. P erm anent damage to the device may be c aused by c ontinuous ly operat ing at
or beyond these limits. Device functional operating lim its and guaranteed performance s pecifications are gi ven under Electrical
Characteristics at the test conditions s pecified.

ESD Sensitive Device. Thi s device i s m anufactured on a CMOS process . It i s t herefore generi cally suscept ible
to damage from excessi ve stati c voltages . Proper ES D precautions mus t be tak en during handling and st orage
of this device.

CONDITION MIN MAX

Digital supply voltage
Analogue supply voltage
Voltage range digital inputs
Voltage range analogue inputs
Master Clock Frequency
Operating temperature range, T
Storage temperature
Package body temperature (s ol deri ng 10 seconds)
Package body temperature (s ol deri ng 2 minutes)

Note:

Analogue and digital grounds mus t always be within 0.3V of each other.

A

-0.3V +7V

-0.3V +7V
DGND -0.3V DVDD +0.3V
AGND -0.3V AVDD +0. 3V

50MHz

-25°C+85°C

-65°C +150°C
+240°C
+183°C

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

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WM8728 Product Preview

DC ELECTRICAL CHARACTERISTICS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Digital supply range
Analogue supply range
Ground
Difference DGND to AGND
Analogue supply current
Digital supply current
Analogue supply current
Digital supply current

DVDD 3.0 5.5 V
AVDD 3.0 5.5 V

AGND, DGND 0 V

-0.3 0 +0.3 V
AVDD = 5V 19 mA
DVDD = 5V 8 mA

AVDD = 3.3V 18 mA
DVDD = 3.3V 4 mA

ELECTRICAL CHARACTERISTICS

Test Conditions

AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T

PARAMETER SYM BOL TEST CONDITIONS MIN TYP MAX UNIT
Digital Logic Levels (TTL Levels)

Input LOW level V
Input HIGH level V
Output LOW V
Output HIGH V

Analogue Reference Levels

Reference voltage

Potential divider resis tance R

VMID

DAC Output (Load = 10k ohms. 50pF)

0dBFs Full scale output volt age

SNR (Note 1,2,3)

SNR (Note 1,2,3)

SNR (Note 1,2,3)

SNR (Note 1,2,3)

SNR (Note 1,2,3)

SNR (Note 1,2,3)

THD (Note 1,2,3)
THD+N (Dynamic range, Note 2)
DAC channel separation

Analogue Output Levels

Output level

Gain mismatch
channel-to-channel

= +25oC, fs = 48kHz, MCLK = 256fs unles s otherwise stated.

A

IL

2.0 V

(VREFP -

VREFN)/2 -

VREFN)/2

OL
OH

IH

IOL = 1mA AGND + 0.3V V
IOH = 1mA AVDD – 0.3V V

VMID (VR EFP -

50mV

At DAC outputs 1. 1 x

AVDD/5

A-weighted,

100 106 dB

@ fs = 48kHz

A-weighted

@ fs = 96kHz

A-weighted

@ fs = 192kHz

A-weighted,
@ fs = 48kHz

AVDD, DVDD = 3.3V

A-weighted

@ fs = 96kHz

AVDD, DVDD = 3.3V

Non ‘A’ weighted @ fs

= 48kHz

1kHz, 0dBFs -97 dB

1kHz, -60dBFs 100 106 dB

Load = 10k Ohms,

0dBFS

Load = 10k Ohms,

0.726 V

0dBFS,

(AVDD = 3.3V)

0.8 V

(VREFP -

V

VREFN)/2 +

50mV

12k ohms

Vrms

106 dB

106 dB

105 dB

103 dB

106 dB

100 dB

1.1 V

RMS

RMS

±1 %FSR

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

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WM8728 Product Preview

Test Conditions

AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T

PARAMETER SYM BOL TEST CONDITIONS MIN TYP MAX UNIT

Minimum resist ance load

Maximum capacitance load
Output d.c. level

Power On Reset (POR)

POR threshold

Notes:

1. Ratio of output level with 1kHz full s cale input, to the output level with al l ZE ROS into the digital input, over a 20Hz to
20kHz bandwidth.

2. All performance measurements done with 20kHz low pass filt er, and where noted an A -weight f i l ter. Failure to use such a
filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The l ow pass filter removes out of band noise; although it is not audible i t may affect dynam i c specification
values.

3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).

= +25oC, fs = 48kHz, MCLK = 256fs unles s otherwise stated.

A

To midrail or a.c.

coupled

To midrail or a.c.

coupled

(AVDD = 3.3V)

5V or 3.3V 100 pF

1 kohms

600 ohms

(VREFP -

VREFN)/2

2.4 V

V

TERMINOLOGY

1. Signal-to-noise ratio (dB) - SNR is a meas ure of the dif ference in level between the full-s cale output and the out put with a
ZERO signal applied. (No Auto-ZERO or A ut omute function is employed in achieving these result s).

2. Dynamic range (dB) - DNR is a measure of the difference between the highest and l owest portions of a signal. Normal ly a
THD+N measurement at 60dB bel ow full scale. The measured signal is t hen corrected by adding the 60dB to it. (e.g.
THD+N @ -60dB= -32dB, DR= 92dB).

3. THD+N (dB) - THD+N is a ratio, of the rms val ues, of (Noise + Distortion)/Signal.

4. Stop band attenuation (dB) - Is the degree t o which the frequency spectrum is attenuated (outside audio band).

5. Channel Separation (dB) - Also known as Cross Talk. This is a measure of the am ount one channel is is olated from the
other. Normally measured by sending a full-scale signal down one channel and measuring the other.

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

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WM8728 Product Preview MASTER CLOCK TIMING

t

MCLKL

MCLK

t

MCLKH

t

MCLKY

Figure 1 Master Clock Timing Requirements

Test Conditions

AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unles s otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Master Clock Timing Information

MCLK Master clock pulse width high
MCLK Master clock pulse width low
MCLK Master clock cycle time
MCLK Duty cycle

t

MCLKH

t

MCLKL

t

MCLKY

13 ns
13 ns
26 ns

40:60 60:40

DIGITAL AUDIO INTERFACE

t

BCH

t

BCL

BCKIN

t

BCY

LRCIN

t

DS

t

LRH

t

LRSU

DIN

t

DH

Figure 2 Digital Audio Data Timing

Test Conditions

AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unles s otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Audio Data Input Timing Information

BCKIN cycle time
BCKIN pulse width high
BCKIN pulse width low
LRCIN set-up time to

t
t
t

t

LRSU

BCY
BCH
BCL

40 ns
16 ns
16 ns

8ns

BCKIN rising edge
LRCIN hold time from

t

LRH

8ns

BCKIN rising edge
DIN set-up time to BCKIN

t

DS

8ns

rising edge
DIN hold time from BCKIN

t

DH

8ns

rising edge

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

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WM8728 Product Preview

DSD AUDIO MONOPHASE INTERFACE

t

BCH

t

BCL

MCLK

t

BCY

DIN/LRCIN

t

DS

t

DH

Figure 3 Normal DSD timing requirements

Test Conditions

AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T

= +25oC, fs = 48kHz, MCLK = 256fs unles s otherwise stated.

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Audio Data Input Timing Information

MCLK cycle time
MCLK pulse width high
MCLK pulse width low
DIN/LRCIN set-up time to

t
t
t

BCY
BCH
BCL

t

DS

344 ns
160 ns
160 ns

10 ns

MCLK rising edge
DIN/LRCIN hold time from

t

DH

10 ns

MCLK rising edge

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

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WM8728 Product Preview DSD AUDIO BIPHASE INTERFACE

t

PH

t

BCY

BCKIN

MCLK

DIN/LRCIN

Figure 4 Biphase DSD Timing Requirements

Test Conditions

AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Audio Data Input Timing Information

BCKIN cycle time
BCKIN pulse width high
BCKIN pulse width low
MCLK cycle time
MCLK pulse width high
MCLK pulse width low
Phase shift between BCKIN

and MCLK
Data setup time to BCKIN

falling edge
Data hold time to BCKIN

rising edge

t

t

BCH

t

BCL

t

SU

HD

t

MCL

t

MCY

t

MCH

D0 D1 D1 D2 D2

= +25oC, fs = 48kHz, MCLK = 256fs unles s otherwise stated.

A

t
t

BCH

t
t

MCY

t

MCH

t

t

t

t

BCY

BCL

MCL

PH

SU

HD

80 81.4 ns
80 81.4 ns

160 162.8 ns
160 162.8 ns

10 ns

10 ns

162.8 ns

325.5 ns

20 ns

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

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WM8728 Product Preview

MPU 3-WIRE INTERFACE TIMING

CSBIWL

t

CSL

t

CSSH

t

CSH

LATI2S

t

CSSU

t

SCH

t

SCY

t

SCL

t

SCS

t

CSS

SCKDSD

SDIDEM

t

DSU

Figure 5 Program Register Input Timing - 3-Wire Serial Control Mode

Test Conditions

AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Program Register Input Information

SCKDSD rising edge to LATI2S

t

SCS

rising edge
SCKDSD pulse cycle time
SCKDSD pulse width low
SCKDSD pulse width high
SDIDEM to SCKDSD set-up

t
t
t
t

SCY
SCL
SCH
DSU

time
SCKDSD to SDIDEM hold time
LATI2S pulse width low
LATI2S pulse width high
LATI2S rising to SCKDSD rising
CSBIWL to LATI2S set-up time
LATI2S to CSBIWL hold time

t

DHO

t

CSL

t

CSH

t

CSS

t

CSSU

t

CSSH

t

DHO

= +25oC, fs = 48kHz, MCLK = 256fs unles s otherwise stated.

A

LSB

40 ns

80 ns
20 ns
20 ns
20 ns

20 ns
20 ns
20 ns
20 ns
20 ns
20 ns

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

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WM8728 Product Preview MPU 2-WIRE INTERFACE TIMING

t

SCF

t

t

SCR

DR

t

ESU

SCKDSD

t

SSUtSHD

t

SCY

t

SCHtSCL

t

t

DSU

DHD

SDIDEM

t

DF

Figure 6 Program Register Input Timing - 2-Wire Serial Control Mode

Test Conditions

AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Program Register Input Information

SCKDSD pulse cycle time
SCKDSD pulse width low
SCKDSD pulse width high
SDIDEM to SCKDSD data set-

t
t
t
t

SCY
SCL
SCH
SSU

up time for start signal
SDIDEM from SCKDSD data

t

SHD

hold time for start signal
SDIDEM to SCKDSD data set-

t

DSU

up time
SCKDSD to SDIDEM data hold

t

DHD

time
SCKDSD rise time
SCKDSD fall time
SDIDEM rise time
SDIDEM fall time
SDIDEM to SCKDSD data set-

t
t

t

t

SCR
SCF

DR

t

DF

ESU

up time for stop si gnal

Notes:

1. The address for the device in the 2-wire mode is 001101X (binary) with the last bit selectable.

2. In the two-wire interface mode, the CSBIWL pin indicates the final bit of the chi p address.

3. In 2-wire mode the LATI2S pin should be tied to either DGND or DVSS to avoid noise toggling the interfac e into 3-wire
mode.

= +25oC, fs = 48kHz, MCLK = 256fs unles s otherwise stated.

A

80 ns
20 ns
20 ns
10 ns

10 ns

20 ns

20 ns

5ns
5ns
5ns
5ns

10 ns

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

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WM8728 Product Preview

DEVICE DESCRIPTION

INTRODUCTION

The WM8728 is a high perform ance DAC designed for digital consumer audio applications. Its
range of features makes it ideall y suited f or use in DVD players , A V rec eivers and other high-end
consumer audio equipment .

WM8728 is a complete 2-channel stereo audio digital-to-analogue converter, including digital
interpolation filter, m ulti-bit sigma delta with dither, switched capacitor multi-bit stereo DAC and
output smoothing fil ters. The WM8728 includes an on-chip digital volum e control, configurable
digital audio interface and a 2 or 3 wire MPU control interface. It i s fully compatib le and an ideal
partner for a range of industry standard microprocessors, controllers and DSPs.

Control of internal functi onality of the device is by eit her hardware control (pin programmed) or
software control (2 or 3-wire serial control i nterface). The MODE pin selects between hardware
and software control. The software control interface may be asynchronous to the audio data
interface. In which case control data will be re-synchronised to the audio processing internally.

Operation using a master c lock of 256fs, 384fs, 512fs or 768fs is provided, selection between
clock rates being autom aticall y controlled i n hardware mode, or serial controll ed when in software
mode. Sample rates (fs) from less than 8ks/s to 96k s/s are allowed, provided the appropriate
master clock is input. S upport is also provi ded for up to 192ks/ s using a m aster cloc k of 128fs or
192fs.

The audio data interface supports ri ght justified, left justif ied and I
delayed) interface formats along with a highly flexible DSP serial port i nterf ace. When in hardware
mode, the three serial interface pi ns become control pins to allow selection of, i nput data format

2

type (I

S or right justified), i nput word length (20 or 24 bit) and de-emphasis func t ions.

2

S (Philips left justified, one bit

In DSD mode, a separate bit stream data input pin is requi red for each of the channels, pl us a 64fs
dataclock MCLK. These signals are applied via pins DIN and LRCIN and the signals routed
internally into the DAC circ ui ts, under control of the SCKDS D mode select pin (19) See Figure 3.

Additionally a Phase Modulation sc hem e is support ed, whereby the audio dat a is t ransm it ted as a
Manchester encoded bitstream . Thi s has the advant age of rem oving the s ignif ic ant spec tral audi o
energy from the datastream , m i nim is ing digi tal s ignal corrupt ion of t he analogue out puts . I n order
to simplify decoding of this Phase modulat ed data, a 2x speed clock (BCKI N) is used to sampl e
the incoming data. See Figure 4.

The device is packaged in a small 20-pin SSOP.

CLOCKING SCHEMES

In a typical digital audio system there is only one c entral cl ock sourc e produci ng a referenc e cl ock
to which all audio data processing is synchronised. This clock is often referred to as the audio
system’s Master Clock. The external master system clock can be applied directly through the
MCLK input pin with no software configuration nec essary for sample rate s el ection.

Note that on the WM8728, MCLK is used to derive clocks for the DAC path. The DAC path
consists of DAC sampli ng clock, DAC digital f ilter cloc k and DAC digita l audio interfac e timing. In
a system where there are a number of pos sible sources for the referenc e clock it is recommended
that the clock source with the lowest jitter be used to opt i mise the performance of the DAC.

WM8728 always acts as a slave and requires clocks to be inputs.

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

11

WM8728 Product Preview DIGITAL AUDIO INTERFACE

Audio data is applied to the internal DAC filters via the Digital Audio Interface. Five popular
interface formats are supported:

• Left Justified mode

• Right Justified mode

2

• I

S mode

• DSP Early mode

• DSP Late mode

All five formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits with the
exception that 32 bit data is not supported in right justified mode. DIN and LRCIN maybe
configured to be sampled on t he ri sing or falling edge of BCKIN.

In left justified, right justified and I
input. Audio Data is ti me multiplexed with LRCIN indicating whether the left or right channel is
present. LRCIN is also us ed as a timing reference to indicate t he beginning or end of the data
words. The minimum number of BCKINs per LRCIN period is 2 ti mes the select ed word length.
LRCIN must be high for a m inimum of word length BCKINs and low f or a m ini m um of word length
BCKINs. Any mark to space ratio on LRCIN is ac ceptable provided the above requirements are
met

The WM8728 will automatically detect when data with a LRCIN period of exactly 32 BCKINs is
sent, and select 16-bit mode - overri ding any previously programmed word length. W ord length
will revert to a programmed value only if a LRCIN period other than 32 BCKINs is detected.

2

S modes, the digital audio interface receives dat a on the DIN

In DSP early or DSP late m ode, the data i s tim e m ultiplexed onto DI N. LRCIN is used as a fram e
sync signal to identify the MSB of the first word. The minimum number of BCKINs per LRCIN
period is 2 times the selected word length. Any mark to space ratio is acceptable on LRCIN
provided the rising edge is correct l y pos i tioned. (See Figure 10 and Figure 11)

LEFT JUSTIFIED MODE

In left justifi ed mode, the MSB is sampled on the f irst rising edge of BCKIN f ollowing a LRCIN
transition. LRCIN is hi gh duri ng the left data word and low during the right data word.

1/fs

LEFT CHANNEL RIGHT CHANNEL

LRCIN

BCKIN

DIN

Figure 7 Left Justified Mode Timing Diagram

n-2 n-1

n321

LSBMSB

n-2 n-1

n321

LSBMSB

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

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WM8728 Product Preview

RIGHT JUSTIFIED MODE

In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN
transition. LRCIN is hi gh duri ng the left data word and low during the right data word.

1/fs

LEFT CHANNEL RIGHT CHANNEL

LRCIN

BCKIN

DIN

n-2 n-1

n321

LSBMSB

n-2 n-1

n321

LSBMSB

Figure 8 Right Justified Mode Timing Diagram

I2S MODE

In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN
transition. LRCIN is l ow during the l ef t data word and high during the right data word.

1/fs

LEFT CHANNEL RIGHT CHANNEL

LRCIN

BCKIN

MSB

1 BCKIN

n-2 n-1

n321

LSB

DIN

MSB

1 BCKIN

n-2 n-1

n321

LSB

Figure 9 I2S Mode Timing Diagram

DSP EARLY MODE

In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that
detects a low to high transit ion on LRCIN. No B CKIN edges are allowed between the data words.
The word order is DIN left, DIN right.

LRCIN

BCKIN

DIN

1 BCKIN 1 BCKIN

LEFT CHANNEL

n-1

Input Word Length (IWL)

RIGHT CHA NN E L

n21

LSBMSB

1/fs

NO VALID DATA

n21

n-1

Figure 10 DSP Early Mode Timing Diagram

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

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WM8728 Product Preview

DSP LATE MODE

In DSP late mode, t he first bit is sampled on the BCK IN rising edge, which detec ts a low to high
transition on LRCIN. No BCKIN edges are allowed between the data words. The word order is
DIN left, DIN right.

1/fs

LRCIN

BCKIN

DIN

Input Word Length (IWL)

Figure 11 DSP Late Mode Timing Diagram

AUDIO DATA SAMPLING RATES

The master clock for W M8728 can range from 128fs to 768fs, where fs is the audio sam pling
frequency (LRCIN) typically 32kHz, 44.1kHz, 48k Hz, 96kHz or 192kHz. The m aster clock is us ed
to operate the digital filt ers and the noise shaping circuits.

The WM8728 has a master cloc k detection circuit that automatically determ ines the relationship
between the master clock frequency and the sampling rate (to within +/- 32 syst em clocks). If
there is a greater than 32 clocks error, the interface shuts down the DAC and mutes the output.
The master clock s hould be sync hronised with LRCIN, although the WM8728 is t olerant of phase
differences or jitter on t hi s clock. See Table 1

SAMPLING

RATE

(LRCIN)

32kHz 4.096 6.144 8.192 12.288 16.384 24.576

44.1kHz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688
48kHz 6.114 9.216 12.288 18.432 24.576 36.864
96kHz 12.288 18.432 24.576 36.864 Unavailable Unavailable

192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unavailable

Table 1 Typical Relationships Between Master Clock Frequency and Sampling Rate

LEFT CHANNEL

n-1

RIGHT CHA N NE L NO VALID DATA

n21

LSBMSB

n21

n-1

MASTER CLOCK FREQUENCY (MHZ) (MCL K)

128fs 192fs 256fs 384fs 512fs 768fs

1

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WM8728 Product Preview

HARDWARE DSD MODE

DSD mode is select ed by taking the SCKDS D pin high whilst the MODE pin is low. In this mode
the internal digital filters are bypassed, and the already modulated bitstream data is applied
directly to the Switched Capacitor DAC filter where it is c onverted and lo wpass fi ltered, see Fi gure
26 to Figure 29.

Two formats are supported for data transfer, MONOPHASE or BIPHASE MODULATED.
In Monophase mode, DSD data is s im pl y cloc ked i nto t he device us ing t he risi ng edge of t he 64f s

MCLK signal.
In Biphase mode, the data is supplied in Manchester encoded form (a bit transi tion occurs during

every data bit, which shapes the spectral energy minim ising corruption of the anal ogue outputs).
A secondary clock BCKIN, at 128fs is used to simplify data recovery, the data simply being
clocked with the falling edge of B CKIN when MCLK is at logic low (0V).

See Figure 3 and Figure 4 for details of DSD i nt erface timing.

HARDWARE CONTROL MODES

When the MODE pin is hel d l ow, t he f ollowing hardware modes of operation are available.

MUTE AND AUTOMUTE OPERATION

In both hardware and software modes, pin 17 (MUTEB) cont rols the selection of MUTE direc tly,
and can be used to enable and disable the automute f unction. This pin bec omes an output when
left floating and indicates infinite ZERO detect (IZD) see also pin 5 (ZERO).

MUTEB PIN DESCRIPTION

0
1

Floating

Mute DAC channels
Normal Operation
Enable IZD, MUTEB becomes an output to indicate when IZD occurs.
L=IZD detected, H=IZD not det ected.

Table 2 Mute and Automute Control

Figure 12 shows the application and release of MUTE whilst a full amplitude sinusoid is being
played at 48kHz sampling rate. When MUTE (lower trace) is asserted, t he output (upper trace)
begins to decay exponentially from the DC level of the last input s ample. The output will decay
towards V

with a time constant of approximately 64 input samples. When MUTE is de-

MID

asserted, the output will restart almost immediately from the current input sample.

1.5

1

0.5

0

-0.5

-1

-1.5

-2

-2.5

0 0.001 0.002 0.003 0.004 0.005 0.006

Time(s)

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WM8728 Product Preview

Figure 12 Application and Release of Soft Mute

The MUTEB pin is an input to select mute or not mute. MUTEB is active low; t aking the pin l ow
causes the filters to soft m ute, ramping down the audio signal over a few milliseconds. Taking
MUTEB high again allows data into the filt er.

The automute function detects a series of ZERO value audio samples of 1024 samples long
being applied to both channels. Af ter such an event, a latch i s set whose output (AUTOMUTED)
is wire OR’ed through a 10kohm resistor to the MUTEB pi n. Thus if the MUTEB pin is not being
driven, the automute function will assert mute.

If MUTEB is tied high, AUTOMUTED is overridden and will not mute unless the I ZD regist er bit is
set. If MUTEB is driven from a bi-direc tional sourc e, then bot h MUTE and aut omute funct ions are
available. If MUTEB is not driven, AUTOMUTED appears as a weak output (10kOhm-source
impedance) so can be used to drive external mute circuits. AUTOMUTED will be removed as
soon as any channel receives a non-ZERO input .

A diagram showing how the various Mute modes i nteract is shown below Figure 13.

IZD (Register Bit)

AUTOMUTED

(Internal Signal)

Ω

10k

MUTEB

PIN

SOFTMUTE
(Internal
Signal)

MUT (Register Bit)

Figure 13 Selection Logic for MUTE Modes

INPUT FORMAT SELECTION

In hardware mode, LATI2S (pin 20) and CSBIW L (pin 15) becom e input controls for sel ection of
input data format type and input data word length.

LATI2S CSBIWL INPUT DATA MODE

00
01
10
11

24-bit right justified
20-bit right justified

2

S

16-bit I

2

S

24-bit I

Table 3 Input Format Selection
Note:

In 24 bit I

2

S mode, any width of 24 bits or less is supported provided that LRCIN is hi gh for a
minimum of 24 BCK INs and low for a m inim um of 24 BCKINs. I f exactly 32 BCK INs oc cu r i n one
LRCIN (16 high, 16 low) the chip will auto detect and run a 16 bit data mode.

DE-EMPHASIS CONTROL

In hardware mode, SDIDEM (pin 18) becomes an input control for selection of de-emphasis
filtering to be applied.

SDIDEM DE-EMPHASIS

0Off
1On

Table 4 De-emphasis Control

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WM8728 Product Preview

SOFTWARE CONTROL INTERFACE

The software control interface may be operated using a 2-wire interface compatible or 3-wire (SPI­compatible) interface.

SELECTION OF CONTROL MODE

The WM8728 may be programm ed to operate in hardware or software control modes. This is
achieved by setting the st ate of the MODE pin.

MODE INTERFACE FORMAT

0
1

Table 5 Control Interface Mode Selection

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

In this mode, SDIDEM is used for the program data, SCKDSD is used t o clock in the program
data and LATI2S is used to latch in t he program data. The 3-wire interface protocol i s shown in
Figure 14.

LATI2S

SCKDSD

Hardware Control Mode
Software Control Mode

SDIDEM

B15 B6B7B8B9B10B11B12B13B14 B1B2B3B4B5 B0

Figure 14 3-Wire Serial Interface

Notes:

1. B[15:9] are Control Address Bi t s

2. B[8:0] are Control Data Bits

3. CSBIWL needs to be low during writes – s ee Fi gure 5

2-WIRE SERIAL CONTROL MODE

In 2-wire mode, which is the default, SDIDEM is used for t he program data and SCK DSD is used
to clock in the program dat a see Figure 15.

WM8728 has an address of 001101X (binary) which represents an audio device. The final
address digit is dependent on pin CS BIW L, which should be t ied to either DVDD or DGND. Thi s
allows the device to have a choice of two identification header addresses used in the 2 wire
interface word. This feature allows more than one WM8728 device to be present on the int erface
bus.

LATI2S should be tied to either DV DD or DGND, as it is unus ed. This pin if toggled f rom low to
high and high to low, will cause the device to enter the 3-wire interface mode and cannot be
placed back into 2-wire mode except by toggl i ng the MODE pin, or powering off the device.

SDIDEM

R ADDR

ACK

DATA B15-8

ACK

DATA B7-0R/W

ACK

SCKDSD

START

STOP

Figure 15 2-Wire Serial Interface

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WM8728 Product Preview REGISTER MAP

WM8728 uses a total of 4 program regist ers, which are 16-bits long. These regist ers are all loaded through i nput pin S DIDEM.
Using either 2-wire or 3-wire serial control mode as shown in Figure 14 and Figure 15.

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

M0

0 0 0 0 0 0 0 UPDATEL LAT7 LAT6 LAT5 LAT4 LAT3 LAT2 LAT1 LAT0

M1

0 0 0 0 0 0 1 UPDATER RAT7 RAT6 RAT5 RAT4 RAT3 RAT2 RAT1 RAT0

M2

0 0 0 0 0 1 0 0 0 0 IW2 IW1 IW0 PWDN EEMPH MUT

M3

0 0 0 0 0 1 1 IZD 0 0 BCP REV 0 ATC LRP I2S

ADDRESS DATA

Table 6 Mapping of Program Registers

REGISTER

BITS NAME DEFAULT DESCRIPTION

ADDRESS

(A3,A2,A1,A0)

0000
DACL

[7:0] LAT[7:0] 11111111 (0dB)

8 UPDATEL 0

Attenuation

0001
DACR

[7:0] RAT[7:0] 11111111 (0dB )

8 UPDATER 0

Attenuation

0010

0MUT 0

DAC Control

1 DEEMPH 0

2PWDN 0

[5:3] IW[2:0] 0
0011
Interface

0I
1LRP 0

2

S0

Control

2ATC 0

4REV 0
5BCP 0

8IZD 0

Table 7 Register Bit Descriptions

Attenuation data for left channel in 0.5dB steps, see Tabl e 9
Attenuation data load control for left channel.

0: Store DACL in intermedi ate latch (no change to output)

1: Store DACL and update attenuation on both channels.
Attenuation data for right c hannel i n 0.5dB steps, see Table 9
Attenuation data load control for right channel.

0: Store DACR in intermedi ate latch (no change to output)

1: Store DACR and update attenuation on both channels.
Left and right DACs soft mute control.

0: No mute

1: Mute
De-emphasis control.

0: De-emphasis off
1: De-emphasis on

Left and Right DACs Power-down Control

0: All DACs running, output is active

1: All DACs in power saving m ode, output muted
Audio data format select, see Table 14
Audio data format select, see Table 14
Polarity select f or LRCIN/DSP mode selec t.

0: normal LRCIN polarity/ DS P late mode
1: inverted LRCIN polarity/DSP early mode

Attenuator Control.

0: All DACs use attenuation as programmed.

1: Right channel DACs use c o rresponding left DAC

attenuation
Output phase reverse.
BCKIN Polarity

0 : normal BCKIN polarit y

1: inverted BCKIN polarity
Infinite ZERO detection circuit control and automute control

0: Infinite ZERO detect di sabled

1: Infinite ZERO detect enabl ed

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WM8728 Product Preview

ATTENUATION CONTROL

Each DAC channel can be attenuat ed digit ally bef ore being applied t o the di gital fil ter. A tt enuation
is 0dB by default but can be set between 0 and 127.5dB in 0.5dB steps using the 8 Attenuation
control bits. All attenuation regist ers are double latched allowing new values to be pre-latc hed to
both channels before being updated synchronous ly. Setting the UPDATE bit on any at tenuation
write will cause all pre-latched values to be immediately applied to the DAC channels.

REGISTER

ADDRESS

Attenuation
DACL

Attenuation
DACR

Table 8 Attenuation Register Map
Note:

1. The UPDATE bit is not latched. If UP DA TE =0, the Attenuation value will be written to the pre-latch but not applied to the
relevant DAC. If UPDATE=1, all pre-latc hed values and the current value being written will be applied on the next input
sample.

2. Care should be used in reducing the attenuation as rapid large volume changes can introduce zipper noise.

BITS LABEL DEFAULT DESCRIPTION

[7:0]

8

[7:0]

8

LAT[7:0] 11111111 (0dB)

UPDATEL 0

RAT[7:0] 11111111 (0dB )

UPDATER 0

Attenuation data for Left channel DACL in 0.5dB steps.0000

Controls simultaneous update of all Attenuation Lat ches

0: Store DACL in intermedi ate latch (no change to output)
1: Store DACL and update attenuation on al l channels.

Attenuation data for Right channel DACR in 0.5dB steps.0001

Controls simultaneous update of all Attenuation Lat ches

0: Store DACR in intermedi ate latch (no change to output)
1: Store DACR and update attenuation on al l channels.

DAC OUTPUT ATTENUATION

Registers LAT and RAT control t he left and right channel attenuation. Table 9 shows how the
attenuation levels are selec ted from the 8-bit words.

XAT[7:0] ATTENUATION LEVEL

00(hex) ∞dB (mute)
01(hex) 127.5dB

::
::

::
FE(hex) 0.5dB
FF(hex) 0dB

Table 9 Attenuation Control Levels

MUTE MODES

Setting the MUT register bit will apply a ’soft’ mute to the input of the digital filters:

REGISTER ADDRESS BIT LABEL DEFAULT DES CRIPTION

0010
DAC Control

Table 10 Mute control

0MUT 0

Soft Mute select
0 : Normal Operation
1: Soft mute all channels

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WM8728 Product Preview

DE-EMPHASIS MODE

Setting the DEEMPH regist er bi t puts the digital filt ers into de-emphasis m ode:

REGISTER ADDRESS BIT LABEL DEFAULT DES CRIPTION

0010

1 DEEMPH 0

DAC Control

Table 11 De-emphasis Control

POWERDOWN MODE

Setting the PW DN register bit immedi ately connects all output s to V
mode. All trace of t he previous input samples is removed, and all control register settings are
cleared. When PW DN is cleared again the fi rst 16 input samples will be ignored, as the FIR will
repeat it’s power-on initialisation sequence.

REGISTER ADDRESS BIT LABEL DEFAULT DES CRIPTION

0010

2PWDN 0

DAC Control

Table 12 Powerdown control

DIGITAL AUDIO INTERFACE CONTROL REGISTERS

The WM8728 has a fully feat ured digital audio i nterface t hat is a s uperset of that contained in t he
WM8716. Interface form at is selected via the I WL[2:0] register bits in register M2 and the I
register bit in M3.

De-emphasis mode s el ect:
0 : De-emphasis Off
1: De-emphasis On

and selects a low power

MID

Power Down Mode Select:
0 : Normal Mode
1: Power Down Mode

2

S

REGISTER ADDRESS BIT LABEL DEFAULT DES CRIPTION

0010

5:3 IWL[2:0] 000000

Interface format Select
DAC Control
0011

0I

2

S0

Interface format Select
Interface Control

Table 13 Interface Format Controls

2

IW2 I

S IW1 IW0 AUDIO INTERFACE DESCRIPTION

(NOTE 1)

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100

16 bit right justified mode
20 bit right justified mode
24 bit right justified mode
24 bit left justifi ed mode

2

S mode

16 bit I

2

S mode

24 bit I

2

S mode

20 bit I
20 bit left justifi ed mode
16 bit DSP mode
20 bit DSP mode
24 bit DSP mode
32 bit DSP mode
16 bit left justifi ed mode

Table 14 Audio Data Input Format
Note:

In all modes, the data i s signed 2’s compl ement. The di gital filt ers always input 24-bit data. I f the
DAC is programmed to receive 16 or 20 bit data, the WM8728 pads the unused LSBs with
ZEROS. If the DAC is programmed into 32-bit m ode, the 8 LSBs are treated as zero.

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WM8728 Product Preview

SELECTION OF LRCIN POLARITY

In left justified, right justified or I2S modes, the LRP regis ter bit controls t he polarity of LRCI N. If
this bit is set high, the expected polarity of LRCI N will be the opposite of that shown in Figure 7,
Figure 8 and Figure 9. Note that if this feat ure is used as a m eans of swapping the left and right
channels, a 1 sample phase diff erenc e will be introduced.

REGISTER ADDRESS BIT LABEL DEFAULT DES CRIPTION

0011
Interface Control

Table 15 LRCIN Polarity Control

In DSP modes, the LRCI N regis ter bit is used t o selec t between early and late m odes (s ee Fi gure
10 and Figure 11.

REGISTER ADDRESS BIT LABEL DEFAULT DES CRIPTION

0011
Interface Control

Table 16 DSP Format Control

In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that
detects a low to high transit i on on LRCIN. In DSP late mode, the first bi t is sampled on the BCKIN
rising edge, which detects a low to high transition on LRCIN. No BCKIN edges are allowed
between the data words. The word order is DIN left, DIN right.

1 LRP 0 LRCIN Polarit y (normal)

0 : normal LRCIN polarity
1: inverted LRCIN polarity

1 LRP 0 DSP Format (DS P modes)

0 : Late DSP mode
1: Early DSP mode

ATTENUATOR CONTROL MODE

Setting the ATC register bit causes the left c hannel attenuation set tings to be applied to bot h left
and right channel DACs from the next audio input sam ple. No update to the attenuat ion regist ers
is required for ATC to take effect.

REGISTER ADDRESS BIT LABEL DEFAULT DES CRIPTION

0011
Interface Control

Table 17 Attenuation Control Select

2 ATC 0 Attenuator Control Mode:

0 : Right channels use Right

attenuation

1: Right Channel s use Left

Attenuation

OUTPUT PHASE REVERSAL

The REV register bit controls the phase of the output signal. Setting the REV bit causes the
phase of the output signal to be i nvert ed.

REGISTER ADDRESS BIT LABEL DEFAULT DES CRIPTION

0011
Interface Control

Table 18 Output Phase Control

4 REV 0 Analogue Output Phase

0: Normal
1: Inverted

BCKIN POLARITY

By default, LRCIN and DIN are sampled on the rising edge of BCKIN and should ideally change
on the falling edge. Data sources which c hange LRCIN and DI N on the ris ing edge of B CKI N c an
be supported by setting the BCP regi ster bit. Setting BCP to 1 inverts the polarity of BCKIN to the
inverse of that shown in Figure 7, Figure 8, Figure 9, Fi gure 10 and Fi gure 11.

REGISTER ADDRESS BIT LABEL DEFAULT DES CRIPTION

0011
Interface Control

Table 19 BCKIN Polarity Control

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

5 BCP 0 BCKIN Polarity

0 : normal BCKIN polarit y
1: inverted BCKIN polarity

21

WM8728 Product Preview

INFINITE ZERO DETECTION

Setting the IZD regist er bi t determines whether the device is automuted when a sequence of more
than 1024 ZEROS is detected.

REGISTER ADDRESS BIT LABEL DEFAULT DES CRIPTION

0011
Interface Control

Table 20 IZD Control

8IZD 0

Infinite ZERO detection circuit

control and automute cont rol

0: Infinite ZERO detect di sabled
1: Infinite ZERO detect enabl ed

DIGITAL FILTER CHARACTERISTICS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Passband Edge
Passband Ripple
Stopband Attenuation

-3dB 0.487fs
f < 0.444fs ±0.05 dB
f > 0.555fs -60 dB

Table 21 Digital Filter Characteristics

DAC FILTER RESPONSES

0

-20

-40

0.2

0.15

0.1

0.05

-60

Response (dB)

-80

-100

-120
0 0.5 1 1.5 2 2.5 3

Frequency (Fs)

Figure 16 DAC Digital Filter Frequency Response

-44.1, 48 and 96kHz

0

-20

-40

Response (dB)

-60

-80

0 0.2 0.4 0.6 0.8 1

Frequency (Fs)

0

Response (dB)

-0.05

-0.1

-0.15

-0.2
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency (Fs)

Figure 17 DAC Digital Filter Ripple

-44.1, 48 and 96kHz

0.2

0

-0.2

-0.4

Response (dB)

-0.6

-0.8

-1
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency (Fs)

Figure 18 DAC Digital Filter Frequency Response

-192kHz

Figure 19 DAC Digital Filter Ripple

-192kHz

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WM8728 Product Preview

DIGITAL DE-EMPHASIS CHARACTERISTICS

0

-2

1

0.5

0

-4

-6

Response (dB)

-8

-10
0 2 4 6 8 10 12 14 16

Frequency (kHz)

Figure 20 De-Emphasis Frequency Response (32kHz)

0

-2

-4

-6

Response (dB)

-8

-10
0 5 10 15 20

Frequency (kHz)

-0.5

-1

Response (dB)

-1.5

-2

-2.5

-3
0 2 4 6 8 10 12 14 16

Frequency (kHz)

Figure 21 De-Emphasis Error (32kHz)

0.4

0.3

0.2

0.1

0

Response (dB)

-0.1

-0.2

-0.3

-0.4
0 5 10 15 20

Frequency (kHz)

Figure 22 De-Emphasis Frequency Response (44.1kHz)

0

-2

-4

-6

Response (dB)

-8

-10
0 5 10 15 20

Frequency (kHz)

Figure 24 De-Emphasis Frequency Response (48kHz)

Figure 23 De-Emphasis Error (44.1kHz)

1

0.8

0.6

0.4

0.2

0

-0.2

Response (dB)

-0.4

-0.6

-0.8

-1
0 5 10 15 20

Frequency (kHz)

Figure 25 De-Emphasis Error (48kHz)

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WM8728 Product Preview

DSD MODE CHARACTERISTICS

0

-10

-20

-30

Response (dB)

-40

-50

-60

0 500 1000 1500 2000

Frequency (kHz)

5

0

-5

-10

-15

-20

-25

Response (dB)

-30

-35

-40

-45
0 50 100 150 200 250 300 350 400

Frequency (kHz)

Figure 26 DSD Frequency Response - no post filter

0

-20

-40

-60

Response (dB)

-80

-100

-120
0 50 100 150 200 250 300 350 400

Frequency (kHz)

Figure 28 DSD frequency response - 4th order post filter

Figure 27 DSD Frequency Response - no post filter

0

-2

-4

Response (dB)

-6

-8

0 10 20 30 40 50 60

Frequency (kHz)

Figure 29 DSD frequency response - 4th order post filter

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

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WM8728 Product Preview

RECOMMENDED EXTERNAL COMPONENTS

Hardware Control

Software/hardware

contro l mode select

Audio Serial Data I/F

Notes:

1. AGND and DGND should be connected as close to the WM8728 as possible.

2. C

3. Capacitor types should be carefully chosen. Capacitors with very low ESR are
recommended for optimum performance.

DVDD

+

C

1

DGND

Software I/F or

, C3, C4 and C8 should be positioned as close to the WM8728 as possible.

2

7

DVDD

C

2

6

DGND

15

CSBIWL

20

LATI2S

19

SCKDSD

18

SDIDEM

17

MUTEB

16

MODE

WM8728

1

LRCIN

4

MCLK

3

BCKIN

2

DIN

5

ZERO

AVDD

VREFP

AGND

VREFN

VOUTR

VOUTL

VMID

10
14

C3C4C

9

13

C

6

8

+ +

C

7

11

12

C

C

9

8

AVDD

+

5

AGND

AC-Coupled
VOUTR/L
to External LPF

+

AGND

Figure 30 External Components Diagram

RECOMMENDED EXTERNAL COMPONENTS VALUES

COMPONENT

REFERENCE

C1 and C5 10µF

C2 to C4 0.1µF

C6 and C7 10µF

C8 0.1µF
C9 10µF

Table 22 External Components Description

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

SUGGESTED

VALUE

DESCRIPTION

De-coupling for DVDD and AVDD/V RE F P
De-coupling for DVDD and AVDD/V RE F P
Output AC coupling caps t o remove midrail DC level from outputs.
Reference de-coupling capacit ors for VMID pin.

25

WM8728 Product Preview

RECOMMENDED DSD EXTERNAL COMPONENTS

MUTE Control

DSD right bitstream

DSD bit clock

DSD biphase mode clock

DSD left bitstream

Notes:

1. AGND and DGND should be connected as close to the WM8728 as possible.

, C3, C4 and C8 should be positioned as close to the WM8728 as possible.

2. C

2

3. Capacitor types should be carefully chosen. Capacitors with very low ESR are

recommended for optimum performance.

4. When using monophase DSD encoding pin 3 BCKIN should be tied to
DVDD. In Biphase DSD encoding BCKIN runs at 2 cycles per bit.

C

DVDD

1

DGND

DGND

C

9

AGND

AVDD

+

5

AGND

AC-Coupled
VOUTR/L
to External LPF

+

7

DVDD

6

15
20
19
18
17

16

1
4

3
2

5

DVDD

DGND

CSBIWL
LATI2S
SCKDSD
SDIDEM
MUTEB

MODE

LRCIN
MCLK

BCKIN
DIN

ZERO

WM8728

+

C

2

AVDD

VREFP

AGND

VREFN

VOUTR

VOUTL

VMID

10
14

C3C4C

9

13

C

6

8

+ +

C

7

11

12

C

8

Figure 31 External Connections for DSD Applications

RECOMMENDED EXTERNAL COMPONENTS VALUES FOR DSD

COMPONENT

REFERENCE

C1 and C5 10µF

C2 to C4 0.1µF

C6 and C7 10µF

C8 0.1µF
C9 10µF

Table 23 External Components for DSD

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

SUGGESTED

VALUE

DESCRIPTION

De-coupling for DVDD and AVDD.
De-coupling for DVDD and AVDD.
Output AC coupling caps t o remove midrail DC level from outputs.
Reference de-coupling capacit ors for VMID pin.

26

WM8728 Product Preview

RECOMMENDED DSD CONNECTIONS

BCKA

CXD2751Q WM8728EDS

DSAR

DSAL

64fs

Right Channel Data

Left Channel Data

MCLK

LRCIN

DIN

Figure 32 Monophase Mode Connection Diagram

BCKA

BCKD

CXD2751Q WM8728EDS

DSAR

DSAL

128fs

64fs

Right Channel Data

Left Channel Data

BCKIN

MCLK

LRCIN

DIN

Figure 33 Biphase Mode Connection Diagram

• DSD mode is selected with the WM8728 by pulling the SCKDSD pin high while the MODE pin is held low.

• DSD mode is hardware only operation.

• The CXD2751Q from Sony is a signal proces sor for Super Audio CD playback.

RECOMMENDED ANALOGUE LOW PASS FILTER FOR PCM DATA FORMAT (OPTIONAL)

4.7k

Ω

4.7k

Ω

+VS

+

10uF

47k

1.8k

Ω

_

7.5K

1.0nF

Ω

+

-VS

680pF

Ω

Ω

51

Figure 34 Recommended Low Pass Filter (Optional)

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

27

WM8728 Product Preview

PACKAGE DIMENSIONS

DM0015.ADS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)

b

D

A2

A1

A

e

101

0.10

1120

C

Dimensions

Symbols

(mm)

MIN NOM MAX
A
A

1

A

2

----- ----- 2.0

0.05 ----- -----

1.65 1.75 1.85

b 0.22 ----- 0.38
c
D
e
E
E

1

L

θ

0.09 ----- 0.25

6.90 7.20 7.50

0.65 BSC

7.40 7.80 8.20

5.00 5.30 5.60

0.55 0.75 0.95

o

0

o

4

E1 E

-C-

SEATING PLANE

o

8

GAUGE
PLANE

Θ

0.25

c

L

REF: JEDEC.95, MO-150

NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001

28